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[PATCH] rt2x00: Fix rfkill handling
[linux-block.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt73usb"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/usb.h>
38
39#include "rt2x00.h"
40#include "rt2x00usb.h"
41#include "rt73usb.h"
42
43/*
44 * Register access.
45 * All access to the CSR registers will go through the methods
46 * rt73usb_register_read and rt73usb_register_write.
47 * BBP and RF register require indirect register access,
48 * and use the CSR registers BBPCSR and RFCSR to achieve this.
49 * These indirect registers work with busy bits,
50 * and we will try maximal REGISTER_BUSY_COUNT times to access
51 * the register while taking a REGISTER_BUSY_DELAY us delay
52 * between each attampt. When the busy bit is still set at that time,
53 * the access attempt is considered to have failed,
54 * and we will print an error.
55 */
56static inline void rt73usb_register_read(const struct rt2x00_dev *rt2x00dev,
57 const unsigned int offset, u32 *value)
58{
59 __le32 reg;
60 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
61 USB_VENDOR_REQUEST_IN, offset,
62 &reg, sizeof(u32), REGISTER_TIMEOUT);
63 *value = le32_to_cpu(reg);
64}
65
66static inline void rt73usb_register_multiread(const struct rt2x00_dev
67 *rt2x00dev,
68 const unsigned int offset,
69 void *value, const u32 length)
70{
71 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
72 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
73 USB_VENDOR_REQUEST_IN, offset,
74 value, length, timeout);
75}
76
77static inline void rt73usb_register_write(const struct rt2x00_dev *rt2x00dev,
78 const unsigned int offset, u32 value)
79{
80 __le32 reg = cpu_to_le32(value);
81 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
82 USB_VENDOR_REQUEST_OUT, offset,
83 &reg, sizeof(u32), REGISTER_TIMEOUT);
84}
85
86static inline void rt73usb_register_multiwrite(const struct rt2x00_dev
87 *rt2x00dev,
88 const unsigned int offset,
89 void *value, const u32 length)
90{
91 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
92 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
93 USB_VENDOR_REQUEST_OUT, offset,
94 value, length, timeout);
95}
96
97static u32 rt73usb_bbp_check(const struct rt2x00_dev *rt2x00dev)
98{
99 u32 reg;
100 unsigned int i;
101
102 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
103 rt73usb_register_read(rt2x00dev, PHY_CSR3, &reg);
104 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
105 break;
106 udelay(REGISTER_BUSY_DELAY);
107 }
108
109 return reg;
110}
111
112static void rt73usb_bbp_write(const struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, const u8 value)
114{
115 u32 reg;
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt73usb_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
122 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
123 return;
124 }
125
126 /*
127 * Write the data into the BBP.
128 */
129 reg = 0;
130 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
131 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
132 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
133 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
134
135 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
136}
137
138static void rt73usb_bbp_read(const struct rt2x00_dev *rt2x00dev,
139 const unsigned int word, u8 *value)
140{
141 u32 reg;
142
143 /*
144 * Wait until the BBP becomes ready.
145 */
146 reg = rt73usb_bbp_check(rt2x00dev);
147 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
148 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
149 return;
150 }
151
152 /*
153 * Write the request into the BBP.
154 */
155 reg = 0;
156 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
157 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
158 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
159
160 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
161
162 /*
163 * Wait until the BBP becomes ready.
164 */
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
168 *value = 0xff;
169 return;
170 }
171
172 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
173}
174
175static void rt73usb_rf_write(const struct rt2x00_dev *rt2x00dev,
176 const unsigned int word, const u32 value)
177{
178 u32 reg;
179 unsigned int i;
180
181 if (!word)
182 return;
183
184 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
185 rt73usb_register_read(rt2x00dev, PHY_CSR4, &reg);
186 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
187 goto rf_write;
188 udelay(REGISTER_BUSY_DELAY);
189 }
190
191 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
192 return;
193
194rf_write:
195 reg = 0;
196 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
197
198 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
199 rt2x00_rf(&rt2x00dev->chip, RF2527))
200 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
201 else
202 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 20);
203
204 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
205 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
206
207 rt73usb_register_write(rt2x00dev, PHY_CSR4, reg);
208 rt2x00_rf_write(rt2x00dev, word, value);
209}
210
211#ifdef CONFIG_RT2X00_LIB_DEBUGFS
212#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
213
214static void rt73usb_read_csr(const struct rt2x00_dev *rt2x00dev,
215 const unsigned int word, u32 *data)
216{
217 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
218}
219
220static void rt73usb_write_csr(const struct rt2x00_dev *rt2x00dev,
221 const unsigned int word, u32 data)
222{
223 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
224}
225
226static const struct rt2x00debug rt73usb_rt2x00debug = {
227 .owner = THIS_MODULE,
228 .csr = {
229 .read = rt73usb_read_csr,
230 .write = rt73usb_write_csr,
231 .word_size = sizeof(u32),
232 .word_count = CSR_REG_SIZE / sizeof(u32),
233 },
234 .eeprom = {
235 .read = rt2x00_eeprom_read,
236 .write = rt2x00_eeprom_write,
237 .word_size = sizeof(u16),
238 .word_count = EEPROM_SIZE / sizeof(u16),
239 },
240 .bbp = {
241 .read = rt73usb_bbp_read,
242 .write = rt73usb_bbp_write,
243 .word_size = sizeof(u8),
244 .word_count = BBP_SIZE / sizeof(u8),
245 },
246 .rf = {
247 .read = rt2x00_rf_read,
248 .write = rt73usb_rf_write,
249 .word_size = sizeof(u32),
250 .word_count = RF_SIZE / sizeof(u32),
251 },
252};
253#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
254
255/*
256 * Configuration handlers.
257 */
4abee4bb 258static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
95ea3627 259{
95ea3627
ID		 260 u32 tmp;
261
4abee4bb 262 tmp = le32_to_cpu(mac[1]);
95ea3627 263 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
4abee4bb 264 mac[1] = cpu_to_le32(tmp);
95ea3627 265
4abee4bb
ID		 266 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
267 (2 * sizeof(__le32)));
95ea3627
ID		 268}
269
4abee4bb 270static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
95ea3627 271{
95ea3627
ID		 272 u32 tmp;
273
4abee4bb 274 tmp = le32_to_cpu(bssid[1]);
95ea3627 275 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
4abee4bb 276 bssid[1] = cpu_to_le32(tmp);
95ea3627 277
4abee4bb
ID		 278 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
279 (2 * sizeof(__le32)));
95ea3627
ID		 280}
281
95ea3627
ID		 282static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type)
283{
4150c572 284 struct interface *intf = &rt2x00dev->interface;
95ea3627
ID		 285 u32 reg;
286
287 /*
288 * Clear current synchronisation setup.
289 * For the Beacon base registers we only need to clear
290 * the first byte since that byte contains the VALID and OWNER
291 * bits which (when set to 0) will invalidate the entire beacon.
292 */
293 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
294 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
295 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
296 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
297 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
298
95ea3627
ID		 299 /*
300 * Enable synchronisation.
301 */
302 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
4150c572
JB		 303 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
304 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 305 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
4150c572
JB		 306 if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
307 is_interface_type(intf, IEEE80211_IF_TYPE_AP))
95ea3627 308 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 2);
4150c572 309 else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
95ea3627 310 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 1);
4150c572 311 else
95ea3627 312 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
95ea3627
ID		 313 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
314}
315
316static void rt73usb_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
317{
318 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
319 u32 reg;
320 u32 value;
321 u32 preamble;
322
323 if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
324 preamble = SHORT_PREAMBLE;
325 else
326 preamble = PREAMBLE;
327
328 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
329
330 rt73usb_register_write(rt2x00dev, TXRX_CSR5, reg);
331
332 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
333 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
334 SHORT_DIFS : DIFS) +
335 PLCP + preamble + get_duration(ACK_SIZE, 10);
336 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, value);
337 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
338
339 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
340 if (preamble == SHORT_PREAMBLE)
341 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 1);
342 else
343 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 0);
344 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
345}
346
347static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
348 const int phymode)
349{
350 struct ieee80211_hw_mode *mode;
351 struct ieee80211_rate *rate;
352
353 if (phymode == MODE_IEEE80211A)
354 rt2x00dev->curr_hwmode = HWMODE_A;
355 else if (phymode == MODE_IEEE80211B)
356 rt2x00dev->curr_hwmode = HWMODE_B;
357 else
358 rt2x00dev->curr_hwmode = HWMODE_G;
359
360 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
361 rate = &mode->rates[mode->num_rates - 1];
362
363 rt73usb_config_rate(rt2x00dev, rate->val2);
364}
365
366static void rt73usb_config_lock_channel(struct rt2x00_dev *rt2x00dev,
367 struct rf_channel *rf,
368 const int txpower)
369{
370 u8 r3;
371 u8 r94;
372 u8 smart;
373
374 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
375 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
376
377 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
378 rt2x00_rf(&rt2x00dev->chip, RF2527));
379
380 rt73usb_bbp_read(rt2x00dev, 3, &r3);
381 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
382 rt73usb_bbp_write(rt2x00dev, 3, r3);
383
384 r94 = 6;
385 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
386 r94 += txpower - MAX_TXPOWER;
387 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
388 r94 += txpower;
389 rt73usb_bbp_write(rt2x00dev, 94, r94);
390
391 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
392 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
393 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
394 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
395
396 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
397 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
398 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
399 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
400
401 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
402 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
403 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
404 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
405
406 udelay(10);
407}
408
409static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
410 const int index, const int channel,
411 const int txpower)
412{
413 struct rf_channel rf;
414
415 /*
416 * Fill rf_reg structure.
417 */
418 memcpy(&rf, &rt2x00dev->spec.channels[index], sizeof(rf));
419
420 rt73usb_config_lock_channel(rt2x00dev, &rf, txpower);
421}
422
423static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
424 const int txpower)
425{
426 struct rf_channel rf;
427
428 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
429 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
430 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
431 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
432
433 rt73usb_config_lock_channel(rt2x00dev, &rf, txpower);
434}
435
436static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
437 const int antenna_tx,
438 const int antenna_rx)
439{
440 u8 r3;
441 u8 r4;
442 u8 r77;
443
444 rt73usb_bbp_read(rt2x00dev, 3, &r3);
445 rt73usb_bbp_read(rt2x00dev, 4, &r4);
446 rt73usb_bbp_read(rt2x00dev, 77, &r77);
447
448 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
449
450 switch (antenna_rx) {
451 case ANTENNA_SW_DIVERSITY:
452 case ANTENNA_HW_DIVERSITY:
453 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
454 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
455 !!(rt2x00dev->curr_hwmode != HWMODE_A));
456 break;
457 case ANTENNA_A:
458 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
459 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
460
461 if (rt2x00dev->curr_hwmode == HWMODE_A)
462 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
463 else
464 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
465 break;
466 case ANTENNA_B:
467 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
468 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
469
470 if (rt2x00dev->curr_hwmode == HWMODE_A)
471 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
472 else
473 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
474 break;
475 }
476
477 rt73usb_bbp_write(rt2x00dev, 77, r77);
478 rt73usb_bbp_write(rt2x00dev, 3, r3);
479 rt73usb_bbp_write(rt2x00dev, 4, r4);
480}
481
482static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
483 const int antenna_tx,
484 const int antenna_rx)
485{
486 u8 r3;
487 u8 r4;
488 u8 r77;
489
490 rt73usb_bbp_read(rt2x00dev, 3, &r3);
491 rt73usb_bbp_read(rt2x00dev, 4, &r4);
492 rt73usb_bbp_read(rt2x00dev, 77, &r77);
493
494 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
495 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
496 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
497
498 switch (antenna_rx) {
499 case ANTENNA_SW_DIVERSITY:
500 case ANTENNA_HW_DIVERSITY:
501 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
502 break;
503 case ANTENNA_A:
504 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
505 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
506 break;
507 case ANTENNA_B:
508 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
509 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
510 break;
511 }
512
513 rt73usb_bbp_write(rt2x00dev, 77, r77);
514 rt73usb_bbp_write(rt2x00dev, 3, r3);
515 rt73usb_bbp_write(rt2x00dev, 4, r4);
516}
517
518struct antenna_sel {
519 u8 word;
520 /*
521 * value[0] -> non-LNA
522 * value[1] -> LNA
523 */
524 u8 value[2];
525};
526
527static const struct antenna_sel antenna_sel_a[] = {
528 { 96, { 0x58, 0x78 } },
529 { 104, { 0x38, 0x48 } },
530 { 75, { 0xfe, 0x80 } },
531 { 86, { 0xfe, 0x80 } },
532 { 88, { 0xfe, 0x80 } },
533 { 35, { 0x60, 0x60 } },
534 { 97, { 0x58, 0x58 } },
535 { 98, { 0x58, 0x58 } },
536};
537
538static const struct antenna_sel antenna_sel_bg[] = {
539 { 96, { 0x48, 0x68 } },
540 { 104, { 0x2c, 0x3c } },
541 { 75, { 0xfe, 0x80 } },
542 { 86, { 0xfe, 0x80 } },
543 { 88, { 0xfe, 0x80 } },
544 { 35, { 0x50, 0x50 } },
545 { 97, { 0x48, 0x48 } },
546 { 98, { 0x48, 0x48 } },
547};
548
549static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
550 const int antenna_tx, const int antenna_rx)
551{
552 const struct antenna_sel *sel;
553 unsigned int lna;
554 unsigned int i;
555 u32 reg;
556
557 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
558
559 if (rt2x00dev->curr_hwmode == HWMODE_A) {
560 sel = antenna_sel_a;
561 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
562
563 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
564 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
565 } else {
566 sel = antenna_sel_bg;
567 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
568
569 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
570 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
571 }
572
573 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
574 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
575
576 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
577
578 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
579 rt2x00_rf(&rt2x00dev->chip, RF5225))
580 rt73usb_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
581 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
582 rt2x00_rf(&rt2x00dev->chip, RF2527))
583 rt73usb_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
584}
585
586static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
587 const int short_slot_time,
588 const int beacon_int)
589{
590 u32 reg;
591
592 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
593 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME,
594 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
595 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
596
597 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
598 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, SIFS);
599 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
600 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, EIFS);
601 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
602
603 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
604 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
605 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
606
607 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
608 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
609 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
610
611 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
612 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16);
613 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
614}
615
616static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
617 const unsigned int flags,
618 struct ieee80211_conf *conf)
619{
620 int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
621
622 if (flags & CONFIG_UPDATE_PHYMODE)
623 rt73usb_config_phymode(rt2x00dev, conf->phymode);
624 if (flags & CONFIG_UPDATE_CHANNEL)
625 rt73usb_config_channel(rt2x00dev, conf->channel_val,
626 conf->channel, conf->power_level);
627 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
628 rt73usb_config_txpower(rt2x00dev, conf->power_level);
629 if (flags & CONFIG_UPDATE_ANTENNA)
630 rt73usb_config_antenna(rt2x00dev, conf->antenna_sel_tx,
631 conf->antenna_sel_rx);
632 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
633 rt73usb_config_duration(rt2x00dev, short_slot_time,
634 conf->beacon_int);
635}
636
637/*
638 * LED functions.
639 */
640static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
641{
642 u32 reg;
643
644 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
645 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
646 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
647 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
648
649 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
650 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
651 rt2x00_set_field16(&rt2x00dev->led_reg,
652 MCU_LEDCS_LINK_A_STATUS, 1);
653 else
654 rt2x00_set_field16(&rt2x00dev->led_reg,
655 MCU_LEDCS_LINK_BG_STATUS, 1);
656
657 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
658 rt2x00dev->led_reg, REGISTER_TIMEOUT);
659}
660
661static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
662{
663 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
664 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
665 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
666
667 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
668 rt2x00dev->led_reg, REGISTER_TIMEOUT);
669}
670
671static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
672{
673 u32 led;
674
675 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
676 return;
677
678 /*
679 * Led handling requires a positive value for the rssi,
680 * to do that correctly we need to add the correction.
681 */
682 rssi += rt2x00dev->rssi_offset;
683
684 if (rssi <= 30)
685 led = 0;
686 else if (rssi <= 39)
687 led = 1;
688 else if (rssi <= 49)
689 led = 2;
690 else if (rssi <= 53)
691 led = 3;
692 else if (rssi <= 63)
693 led = 4;
694 else
695 led = 5;
696
697 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
698 rt2x00dev->led_reg, REGISTER_TIMEOUT);
699}
700
701/*
702 * Link tuning
703 */
704static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev)
705{
706 u32 reg;
707
708 /*
709 * Update FCS error count from register.
710 */
711 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
712 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
713
714 /*
715 * Update False CCA count from register.
716 */
717 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
718 reg = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
719 rt2x00dev->link.false_cca =
720 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
721}
722
723static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
724{
725 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
726 rt2x00dev->link.vgc_level = 0x20;
727}
728
729static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
730{
731 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
732 u8 r17;
733 u8 up_bound;
734 u8 low_bound;
735
736 /*
737 * Update Led strength
738 */
739 rt73usb_activity_led(rt2x00dev, rssi);
740
741 rt73usb_bbp_read(rt2x00dev, 17, &r17);
742
743 /*
744 * Determine r17 bounds.
745 */
746 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
747 low_bound = 0x28;
748 up_bound = 0x48;
749
750 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
751 low_bound += 0x10;
752 up_bound += 0x10;
753 }
754 } else {
755 if (rssi > -82) {
756 low_bound = 0x1c;
757 up_bound = 0x40;
758 } else if (rssi > -84) {
759 low_bound = 0x1c;
760 up_bound = 0x20;
761 } else {
762 low_bound = 0x1c;
763 up_bound = 0x1c;
764 }
765
766 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
767 low_bound += 0x14;
768 up_bound += 0x10;
769 }
770 }
771
772 /*
773 * Special big-R17 for very short distance
774 */
775 if (rssi > -35) {
776 if (r17 != 0x60)
777 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
778 return;
779 }
780
781 /*
782 * Special big-R17 for short distance
783 */
784 if (rssi >= -58) {
785 if (r17 != up_bound)
786 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
787 return;
788 }
789
790 /*
791 * Special big-R17 for middle-short distance
792 */
793 if (rssi >= -66) {
794 low_bound += 0x10;
795 if (r17 != low_bound)
796 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
797 return;
798 }
799
800 /*
801 * Special mid-R17 for middle distance
802 */
803 if (rssi >= -74) {
804 if (r17 != (low_bound + 0x10))
805 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
806 return;
807 }
808
809 /*
810 * Special case: Change up_bound based on the rssi.
811 * Lower up_bound when rssi is weaker then -74 dBm.
812 */
813 up_bound -= 2 * (-74 - rssi);
814 if (low_bound > up_bound)
815 up_bound = low_bound;
816
817 if (r17 > up_bound) {
818 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
819 return;
820 }
821
822 /*
823 * r17 does not yet exceed upper limit, continue and base
824 * the r17 tuning on the false CCA count.
825 */
826 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
827 r17 += 4;
828 if (r17 > up_bound)
829 r17 = up_bound;
830 rt73usb_bbp_write(rt2x00dev, 17, r17);
831 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
832 r17 -= 4;
833 if (r17 < low_bound)
834 r17 = low_bound;
835 rt73usb_bbp_write(rt2x00dev, 17, r17);
836 }
837}
838
839/*
840 * Firmware name function.
841 */
842static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
843{
844 return FIRMWARE_RT2571;
845}
846
847/*
848 * Initialization functions.
849 */
850static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
851 const size_t len)
852{
853 unsigned int i;
854 int status;
855 u32 reg;
856 char *ptr = data;
857 char *cache;
858 int buflen;
859 int timeout;
860
861 /*
862 * Wait for stable hardware.
863 */
864 for (i = 0; i < 100; i++) {
865 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
866 if (reg)
867 break;
868 msleep(1);
869 }
870
871 if (!reg) {
872 ERROR(rt2x00dev, "Unstable hardware.\n");
873 return -EBUSY;
874 }
875
876 /*
877 * Write firmware to device.
878 * We setup a seperate cache for this action,
879 * since we are going to write larger chunks of data
880 * then normally used cache size.
881 */
882 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
883 if (!cache) {
884 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
885 return -ENOMEM;
886 }
887
888 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
889 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
890 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
891
892 memcpy(cache, ptr, buflen);
893
894 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
895 USB_VENDOR_REQUEST_OUT,
896 FIRMWARE_IMAGE_BASE + i, 0x0000,
897 cache, buflen, timeout);
898
899 ptr += buflen;
900 }
901
902 kfree(cache);
903
904 /*
905 * Send firmware request to device to load firmware,
906 * we need to specify a long timeout time.
907 */
908 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
909 0x0000, USB_MODE_FIRMWARE,
910 REGISTER_TIMEOUT_FIRMWARE);
911 if (status < 0) {
912 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
913 return status;
914 }
915
916 rt73usb_disable_led(rt2x00dev);
917
918 return 0;
919}
920
921static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
922{
923 u32 reg;
924
925 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
926 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
927 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
928 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
929 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
930
931 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
932 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
933 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
934 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
935 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
936 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
937 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
938 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
939 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
940 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
941
942 /*
943 * CCK TXD BBP registers
944 */
945 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
946 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
947 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
948 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
949 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
950 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
951 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
952 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
953 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
954 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
955
956 /*
957 * OFDM TXD BBP registers
958 */
959 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
960 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
961 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
962 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
963 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
964 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
965 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
966 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
967
968 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
969 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
970 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
971 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
972 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
973 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
974
975 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
976 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
977 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
978 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
979 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
980 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
981
982 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
983
984 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
985 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
986 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
987
988 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
989
990 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
991 return -EBUSY;
992
993 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
994
995 /*
996 * Invalidate all Shared Keys (SEC_CSR0),
997 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
998 */
999 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1000 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1001 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1002
1003 reg = 0x000023b0;
1004 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1005 rt2x00_rf(&rt2x00dev->chip, RF2527))
1006 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1007 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1008
1009 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1010 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1011 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1012
1013 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1014 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1015 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1016 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1017
1018 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1019 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1020 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1021 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1022
1023 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1024 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1025 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1026
1027 /*
1028 * We must clear the error counters.
1029 * These registers are cleared on read,
1030 * so we may pass a useless variable to store the value.
1031 */
1032 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1033 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1034 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1035
1036 /*
1037 * Reset MAC and BBP registers.
1038 */
1039 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1040 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1041 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1042 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1043
1044 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1045 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1046 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1047 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1048
1049 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1050 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1051 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1052
1053 return 0;
1054}
1055
1056static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1057{
1058 unsigned int i;
1059 u16 eeprom;
1060 u8 reg_id;
1061 u8 value;
1062
1063 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1064 rt73usb_bbp_read(rt2x00dev, 0, &value);
1065 if ((value != 0xff) && (value != 0x00))
1066 goto continue_csr_init;
1067 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1068 udelay(REGISTER_BUSY_DELAY);
1069 }
1070
1071 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1072 return -EACCES;
1073
1074continue_csr_init:
1075 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1076 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1077 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1078 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1079 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1080 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1081 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1082 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1083 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1084 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1085 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1086 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1087 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1088 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1089 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1090 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1091 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1092 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1093 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1094 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1095 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1096 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1097 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1098 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1099 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1100
1101 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1102 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1103 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1104
1105 if (eeprom != 0xffff && eeprom != 0x0000) {
1106 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1107 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1108 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1109 reg_id, value);
1110 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1111 }
1112 }
1113 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1114
1115 return 0;
1116}
1117
1118/*
1119 * Device state switch handlers.
1120 */
1121static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1122 enum dev_state state)
1123{
1124 u32 reg;
1125
1126 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1127 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1128 state == STATE_RADIO_RX_OFF);
1129 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1130}
1131
1132static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1133{
1134 /*
1135 * Initialize all registers.
1136 */
1137 if (rt73usb_init_registers(rt2x00dev) ||
1138 rt73usb_init_bbp(rt2x00dev)) {
1139 ERROR(rt2x00dev, "Register initialization failed.\n");
1140 return -EIO;
1141 }
1142
1143 rt2x00usb_enable_radio(rt2x00dev);
1144
1145 /*
1146 * Enable LED
1147 */
1148 rt73usb_enable_led(rt2x00dev);
1149
1150 return 0;
1151}
1152
1153static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1154{
1155 /*
1156 * Disable LED
1157 */
1158 rt73usb_disable_led(rt2x00dev);
1159
1160 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1161
1162 /*
1163 * Disable synchronisation.
1164 */
1165 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1166
1167 rt2x00usb_disable_radio(rt2x00dev);
1168}
1169
1170static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1171{
1172 u32 reg;
1173 unsigned int i;
1174 char put_to_sleep;
1175 char current_state;
1176
1177 put_to_sleep = (state != STATE_AWAKE);
1178
1179 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1180 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1181 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1182 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1183
1184 /*
1185 * Device is not guaranteed to be in the requested state yet.
1186 * We must wait until the register indicates that the
1187 * device has entered the correct state.
1188 */
1189 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1190 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1191 current_state =
1192 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1193 if (current_state == !put_to_sleep)
1194 return 0;
1195 msleep(10);
1196 }
1197
1198 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1199 "current device state %d.\n", !put_to_sleep, current_state);
1200
1201 return -EBUSY;
1202}
1203
1204static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1205 enum dev_state state)
1206{
1207 int retval = 0;
1208
1209 switch (state) {
1210 case STATE_RADIO_ON:
1211 retval = rt73usb_enable_radio(rt2x00dev);
1212 break;
1213 case STATE_RADIO_OFF:
1214 rt73usb_disable_radio(rt2x00dev);
1215 break;
1216 case STATE_RADIO_RX_ON:
1217 case STATE_RADIO_RX_OFF:
1218 rt73usb_toggle_rx(rt2x00dev, state);
1219 break;
1220 case STATE_DEEP_SLEEP:
1221 case STATE_SLEEP:
1222 case STATE_STANDBY:
1223 case STATE_AWAKE:
1224 retval = rt73usb_set_state(rt2x00dev, state);
1225 break;
1226 default:
1227 retval = -ENOTSUPP;
1228 break;
1229 }
1230
1231 return retval;
1232}
1233
1234/*
1235 * TX descriptor initialization
1236 */
1237static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1238 struct data_desc *txd,
4150c572 1239 struct txdata_entry_desc *desc,
95ea3627
ID		 1240 struct ieee80211_hdr *ieee80211hdr,
1241 unsigned int length,
1242 struct ieee80211_tx_control *control)
1243{
1244 u32 word;
1245
1246 /*
1247 * Start writing the descriptor words.
1248 */
1249 rt2x00_desc_read(txd, 1, &word);
1250 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1251 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1252 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1253 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1254 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1255 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1256 rt2x00_desc_write(txd, 1, word);
1257
1258 rt2x00_desc_read(txd, 2, &word);
1259 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1260 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1261 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1262 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1263 rt2x00_desc_write(txd, 2, word);
1264
1265 rt2x00_desc_read(txd, 5, &word);
1266 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1267 TXPOWER_TO_DEV(control->power_level));
1268 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1269 rt2x00_desc_write(txd, 5, word);
1270
1271 rt2x00_desc_read(txd, 0, &word);
1272 rt2x00_set_field32(&word, TXD_W0_BURST,
1273 test_bit(ENTRY_TXD_BURST, &desc->flags));
1274 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1275 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1276 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1277 rt2x00_set_field32(&word, TXD_W0_ACK,
1278 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1279 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1280 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1281 rt2x00_set_field32(&word, TXD_W0_OFDM,
1282 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1283 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1284 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1285 !!(control->flags &
1286 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1287 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1288 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1289 rt2x00_set_field32(&word, TXD_W0_BURST2,
1290 test_bit(ENTRY_TXD_BURST, &desc->flags));
1291 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1292 rt2x00_desc_write(txd, 0, word);
1293}
1294
1295/*
1296 * TX data initialization
1297 */
1298static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1299 unsigned int queue)
1300{
1301 u32 reg;
1302
1303 if (queue != IEEE80211_TX_QUEUE_BEACON)
1304 return;
1305
1306 /*
1307 * For Wi-Fi faily generated beacons between participating stations.
1308 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1309 */
1310 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1311
1312 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1313 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1314 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1315 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1316 }
1317}
1318
1319/*
1320 * RX control handlers
1321 */
1322static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1323{
1324 u16 eeprom;
1325 u8 offset;
1326 u8 lna;
1327
1328 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1329 switch (lna) {
1330 case 3:
1331 offset = 90;
1332 break;
1333 case 2:
1334 offset = 74;
1335 break;
1336 case 1:
1337 offset = 64;
1338 break;
1339 default:
1340 return 0;
1341 }
1342
1343 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1344 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1345 if (lna == 3 || lna == 2)
1346 offset += 10;
1347 } else {
1348 if (lna == 3)
1349 offset += 6;
1350 else if (lna == 2)
1351 offset += 8;
1352 }
1353
1354 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1355 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1356 } else {
1357 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1358 offset += 14;
1359
1360 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1361 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1362 }
1363
1364 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1365}
1366
4150c572
JB		 1367static void rt73usb_fill_rxdone(struct data_entry *entry,
1368 struct rxdata_entry_desc *desc)
95ea3627
ID		 1369{
1370 struct data_desc *rxd = (struct data_desc *)entry->skb->data;
1371 u32 word0;
1372 u32 word1;
1373
1374 rt2x00_desc_read(rxd, 0, &word0);
1375 rt2x00_desc_read(rxd, 1, &word1);
1376
4150c572
JB		 1377 desc->flags = 0;
1378 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1379 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1380
1381 /*
1382 * Obtain the status about this packet.
1383 */
4150c572
JB		 1384 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1385 desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
1386 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1387 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627
ID		 1388
1389 /*
1390 * Pull the skb to clear the descriptor area.
1391 */
1392 skb_pull(entry->skb, entry->ring->desc_size);
1393
4150c572 1394 return;
95ea3627
ID		 1395}
1396
1397/*
1398 * Device probe functions.
1399 */
1400static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1401{
1402 u16 word;
1403 u8 *mac;
1404 s8 value;
1405
1406 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1407
1408 /*
1409 * Start validation of the data that has been read.
1410 */
1411 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1412 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1413 DECLARE_MAC_BUF(macbuf);
1414
95ea3627 1415 random_ether_addr(mac);
0795af57 1416 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1417 }
1418
1419 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1420 if (word == 0xffff) {
1421 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1422 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1423 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1424 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1425 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1426 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1427 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1428 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1429 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1430 }
1431
1432 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1433 if (word == 0xffff) {
1434 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1435 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1436 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1437 }
1438
1439 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1440 if (word == 0xffff) {
1441 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1442 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1443 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1444 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1445 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1446 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1447 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1448 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1449 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1450 LED_MODE_DEFAULT);
1451 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1452 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1453 }
1454
1455 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1456 if (word == 0xffff) {
1457 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1458 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1459 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1460 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1461 }
1462
1463 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1464 if (word == 0xffff) {
1465 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1466 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1467 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1468 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1469 } else {
1470 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1471 if (value < -10 || value > 10)
1472 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1473 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1474 if (value < -10 || value > 10)
1475 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1476 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1477 }
1478
1479 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1480 if (word == 0xffff) {
1481 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1482 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1483 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1484 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1485 } else {
1486 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1487 if (value < -10 || value > 10)
1488 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1489 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1490 if (value < -10 || value > 10)
1491 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1492 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1493 }
1494
1495 return 0;
1496}
1497
1498static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1499{
1500 u32 reg;
1501 u16 value;
1502 u16 eeprom;
1503
1504 /*
1505 * Read EEPROM word for configuration.
1506 */
1507 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1508
1509 /*
1510 * Identify RF chipset.
1511 */
1512 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1513 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1514 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1515
1516 if (!rt2x00_rev(&rt2x00dev->chip, 0x25730)) {
1517 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1518 return -ENODEV;
1519 }
1520
1521 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1522 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1523 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1524 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1525 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1526 return -ENODEV;
1527 }
1528
1529 /*
1530 * Identify default antenna configuration.
1531 */
1532 rt2x00dev->hw->conf.antenna_sel_tx =
1533 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1534 rt2x00dev->hw->conf.antenna_sel_rx =
1535 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1536
1537 /*
1538 * Read the Frame type.
1539 */
1540 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1541 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1542
1543 /*
1544 * Read frequency offset.
1545 */
1546 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1547 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1548
1549 /*
1550 * Read external LNA informations.
1551 */
1552 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1553
1554 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1555 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1556 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1557 }
1558
1559 /*
1560 * Store led settings, for correct led behaviour.
1561 */
1562 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1563
1564 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1565 rt2x00dev->led_mode);
1566 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1567 rt2x00_get_field16(eeprom,
1568 EEPROM_LED_POLARITY_GPIO_0));
1569 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1570 rt2x00_get_field16(eeprom,
1571 EEPROM_LED_POLARITY_GPIO_1));
1572 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1573 rt2x00_get_field16(eeprom,
1574 EEPROM_LED_POLARITY_GPIO_2));
1575 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1576 rt2x00_get_field16(eeprom,
1577 EEPROM_LED_POLARITY_GPIO_3));
1578 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1579 rt2x00_get_field16(eeprom,
1580 EEPROM_LED_POLARITY_GPIO_4));
1581 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1582 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1583 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1584 rt2x00_get_field16(eeprom,
1585 EEPROM_LED_POLARITY_RDY_G));
1586 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1587 rt2x00_get_field16(eeprom,
1588 EEPROM_LED_POLARITY_RDY_A));
1589
1590 return 0;
1591}
1592
1593/*
1594 * RF value list for RF2528
1595 * Supports: 2.4 GHz
1596 */
1597static const struct rf_channel rf_vals_bg_2528[] = {
1598 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1599 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1600 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1601 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1602 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1603 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1604 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1605 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1606 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1607 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1608 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1609 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1610 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1611 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1612};
1613
1614/*
1615 * RF value list for RF5226
1616 * Supports: 2.4 GHz & 5.2 GHz
1617 */
1618static const struct rf_channel rf_vals_5226[] = {
1619 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1620 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1621 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1622 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1623 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1624 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1625 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1626 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1627 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1628 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1629 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1630 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1631 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1632 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1633
1634 /* 802.11 UNI / HyperLan 2 */
1635 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1636 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1637 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1638 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1639 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1640 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1641 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1642 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1643
1644 /* 802.11 HyperLan 2 */
1645 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1646 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1647 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1648 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1649 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1650 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1651 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1652 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1653 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1654 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1655
1656 /* 802.11 UNII */
1657 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1658 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1659 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1660 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1661 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1662 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1663
1664 /* MMAC(Japan)J52 ch 34,38,42,46 */
1665 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1666 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1667 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1668 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1669};
1670
1671/*
1672 * RF value list for RF5225 & RF2527
1673 * Supports: 2.4 GHz & 5.2 GHz
1674 */
1675static const struct rf_channel rf_vals_5225_2527[] = {
1676 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1677 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1678 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1679 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1680 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1681 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1682 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1683 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1684 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1685 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1686 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1687 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1688 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1689 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1690
1691 /* 802.11 UNI / HyperLan 2 */
1692 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1693 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1694 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1695 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1696 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1697 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1698 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1699 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1700
1701 /* 802.11 HyperLan 2 */
1702 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1703 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1704 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1705 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1706 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1707 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1708 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1709 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1710 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1711 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1712
1713 /* 802.11 UNII */
1714 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1715 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1716 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1717 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1718 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1719 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1720
1721 /* MMAC(Japan)J52 ch 34,38,42,46 */
1722 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1723 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1724 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1725 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1726};
1727
1728
1729static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1730{
1731 struct hw_mode_spec *spec = &rt2x00dev->spec;
1732 u8 *txpower;
1733 unsigned int i;
1734
1735 /*
1736 * Initialize all hw fields.
1737 */
1738 rt2x00dev->hw->flags =
1739 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 1740 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1741 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1742 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1743 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1744 rt2x00dev->hw->queues = 5;
1745
1746 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1747 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1748 rt2x00_eeprom_addr(rt2x00dev,
1749 EEPROM_MAC_ADDR_0));
1750
1751 /*
1752 * Convert tx_power array in eeprom.
1753 */
1754 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1755 for (i = 0; i < 14; i++)
1756 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1757
1758 /*
1759 * Initialize hw_mode information.
1760 */
1761 spec->num_modes = 2;
1762 spec->num_rates = 12;
1763 spec->tx_power_a = NULL;
1764 spec->tx_power_bg = txpower;
1765 spec->tx_power_default = DEFAULT_TXPOWER;
1766
1767 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1768 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1769 spec->channels = rf_vals_bg_2528;
1770 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1771 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1772 spec->channels = rf_vals_5226;
1773 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1774 spec->num_channels = 14;
1775 spec->channels = rf_vals_5225_2527;
1776 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1777 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1778 spec->channels = rf_vals_5225_2527;
1779 }
1780
1781 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1782 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1783 spec->num_modes = 3;
1784
1785 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1786 for (i = 0; i < 14; i++)
1787 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1788
1789 spec->tx_power_a = txpower;
1790 }
1791}
1792
1793static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1794{
1795 int retval;
1796
1797 /*
1798 * Allocate eeprom data.
1799 */
1800 retval = rt73usb_validate_eeprom(rt2x00dev);
1801 if (retval)
1802 return retval;
1803
1804 retval = rt73usb_init_eeprom(rt2x00dev);
1805 if (retval)
1806 return retval;
1807
1808 /*
1809 * Initialize hw specifications.
1810 */
1811 rt73usb_probe_hw_mode(rt2x00dev);
1812
1813 /*
95ea3627
ID		 1814 * This device requires firmware
1815 */
066cb637 1816 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 1817
1818 /*
1819 * Set the rssi offset.
1820 */
1821 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1822
1823 return 0;
1824}
1825
1826/*
1827 * IEEE80211 stack callback functions.
1828 */
4150c572
JB		 1829static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1830 unsigned int changed_flags,
1831 unsigned int *total_flags,
1832 int mc_count,
1833 struct dev_addr_list *mc_list)
1834{
1835 struct rt2x00_dev *rt2x00dev = hw->priv;
1836 struct interface *intf = &rt2x00dev->interface;
1837 u32 reg;
1838
1839 /*
1840 * Mask off any flags we are going to ignore from
1841 * the total_flags field.
1842 */
1843 *total_flags &=
1844 FIF_ALLMULTI |
1845 FIF_FCSFAIL |
1846 FIF_PLCPFAIL |
1847 FIF_CONTROL |
1848 FIF_OTHER_BSS |
1849 FIF_PROMISC_IN_BSS;
1850
1851 /*
1852 * Apply some rules to the filters:
1853 * - Some filters imply different filters to be set.
1854 * - Some things we can't filter out at all.
1855 * - Some filters are set based on interface type.
1856 */
1857 if (mc_count)
1858 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1859 if (*total_flags & FIF_OTHER_BSS ||
1860 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 1861 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1862 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1863 *total_flags |= FIF_PROMISC_IN_BSS;
1864
1865 /*
1866 * Check if there is any work left for us.
1867 */
1868 if (intf->filter == *total_flags)
1869 return;
1870 intf->filter = *total_flags;
1871
1872 /*
1873 * When in atomic context, reschedule and let rt2x00lib
1874 * call this function again.
1875 */
1876 if (in_atomic()) {
1877 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1878 return;
1879 }
1880
1881 /*
1882 * Start configuration steps.
1883 * Note that the version error will always be dropped
1884 * and broadcast frames will always be accepted since
1885 * there is no filter for it at this time.
1886 */
1887 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1888 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1889 !(*total_flags & FIF_FCSFAIL));
1890 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1891 !(*total_flags & FIF_PLCPFAIL));
1892 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1893 !(*total_flags & FIF_CONTROL));
1894 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1895 !(*total_flags & FIF_PROMISC_IN_BSS));
1896 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1897 !(*total_flags & FIF_PROMISC_IN_BSS));
1898 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1899 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1900 !(*total_flags & FIF_ALLMULTI));
1901 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1902 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1903 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1904}
1905
95ea3627
ID		 1906static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1907 u32 short_retry, u32 long_retry)
1908{
1909 struct rt2x00_dev *rt2x00dev = hw->priv;
1910 u32 reg;
1911
1912 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1913 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1914 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1915 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1916
1917 return 0;
1918}
1919
1920#if 0
1921/*
1922 * Mac80211 demands get_tsf must be atomic.
1923 * This is not possible for rt73usb since all register access
1924 * functions require sleeping. Untill mac80211 no longer needs
1925 * get_tsf to be atomic, this function should be disabled.
1926 */
1927static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1928{
1929 struct rt2x00_dev *rt2x00dev = hw->priv;
1930 u64 tsf;
1931 u32 reg;
1932
1933 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1934 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1935 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1936 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1937
1938 return tsf;
1939}
1940#endif
1941
1942static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1943{
1944 struct rt2x00_dev *rt2x00dev = hw->priv;
1945
1946 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1947 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1948}
1949
24845910 1950static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 1951 struct ieee80211_tx_control *control)
1952{
1953 struct rt2x00_dev *rt2x00dev = hw->priv;
1954 int timeout;
1955
1956 /*
1957 * Just in case the ieee80211 doesn't set this,
1958 * but we need this queue set for the descriptor
1959 * initialization.
1960 */
1961 control->queue = IEEE80211_TX_QUEUE_BEACON;
1962
1963 /*
1964 * First we create the beacon.
1965 */
1966 skb_push(skb, TXD_DESC_SIZE);
1967 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
1968 (struct ieee80211_hdr *)(skb->data +
1969 TXD_DESC_SIZE),
1970 skb->len - TXD_DESC_SIZE, control);
1971
1972 /*
1973 * Write entire beacon with descriptor to register,
1974 * and kick the beacon generator.
1975 */
1976 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
1977 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
1978 USB_VENDOR_REQUEST_OUT,
1979 HW_BEACON_BASE0, 0x0000,
1980 skb->data, skb->len, timeout);
1981 rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1982
1983 return 0;
1984}
1985
1986static const struct ieee80211_ops rt73usb_mac80211_ops = {
1987 .tx = rt2x00mac_tx,
4150c572
JB		 1988 .start = rt2x00mac_start,
1989 .stop = rt2x00mac_stop,
95ea3627
ID		 1990 .add_interface = rt2x00mac_add_interface,
1991 .remove_interface = rt2x00mac_remove_interface,
1992 .config = rt2x00mac_config,
1993 .config_interface = rt2x00mac_config_interface,
4150c572 1994 .configure_filter = rt73usb_configure_filter,
95ea3627
ID		 1995 .get_stats = rt2x00mac_get_stats,
1996 .set_retry_limit = rt73usb_set_retry_limit,
1997 .conf_tx = rt2x00mac_conf_tx,
1998 .get_tx_stats = rt2x00mac_get_tx_stats,
1999#if 0
2000/*
2001 * See comment at the rt73usb_get_tsf function.
2002 */
2003 .get_tsf = rt73usb_get_tsf,
2004#endif
2005 .reset_tsf = rt73usb_reset_tsf,
2006 .beacon_update = rt73usb_beacon_update,
2007};
2008
2009static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2010 .probe_hw = rt73usb_probe_hw,
2011 .get_firmware_name = rt73usb_get_firmware_name,
2012 .load_firmware = rt73usb_load_firmware,
2013 .initialize = rt2x00usb_initialize,
2014 .uninitialize = rt2x00usb_uninitialize,
2015 .set_device_state = rt73usb_set_device_state,
2016 .link_stats = rt73usb_link_stats,
2017 .reset_tuner = rt73usb_reset_tuner,
2018 .link_tuner = rt73usb_link_tuner,
2019 .write_tx_desc = rt73usb_write_tx_desc,
2020 .write_tx_data = rt2x00usb_write_tx_data,
2021 .kick_tx_queue = rt73usb_kick_tx_queue,
2022 .fill_rxdone = rt73usb_fill_rxdone,
2023 .config_mac_addr = rt73usb_config_mac_addr,
2024 .config_bssid = rt73usb_config_bssid,
95ea3627
ID		 2025 .config_type = rt73usb_config_type,
2026 .config = rt73usb_config,
2027};
2028
2029static const struct rt2x00_ops rt73usb_ops = {
2030 .name = DRV_NAME,
2031 .rxd_size = RXD_DESC_SIZE,
2032 .txd_size = TXD_DESC_SIZE,
2033 .eeprom_size = EEPROM_SIZE,
2034 .rf_size = RF_SIZE,
2035 .lib = &rt73usb_rt2x00_ops,
2036 .hw = &rt73usb_mac80211_ops,
2037#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2038 .debugfs = &rt73usb_rt2x00debug,
2039#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2040};
2041
2042/*
2043 * rt73usb module information.
2044 */
2045static struct usb_device_id rt73usb_device_table[] = {
2046 /* AboCom */
2047 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2048 /* Askey */
2049 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2050 /* ASUS */
2051 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2052 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2053 /* Belkin */
2054 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2055 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2056 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2057 /* Billionton */
2058 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2059 /* Buffalo */
2060 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2061 /* CNet */
2062 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2063 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2064 /* Conceptronic */
2065 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2066 /* D-Link */
2067 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2068 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2069 /* Gemtek */
2070 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2071 /* Gigabyte */
2072 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2073 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2074 /* Huawei-3Com */
2075 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2076 /* Hercules */
2077 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2078 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2079 /* Linksys */
2080 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2081 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2082 /* MSI */
2083 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2084 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2085 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2086 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2087 /* Ralink */
2088 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2089 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2090 /* Qcom */
2091 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2092 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2093 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2094 /* Senao */
2095 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2096 /* Sitecom */
2097 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2098 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2099 /* Surecom */
2100 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2101 /* Planex */
2102 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2103 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2104 { 0, }
2105};
2106
2107MODULE_AUTHOR(DRV_PROJECT);
2108MODULE_VERSION(DRV_VERSION);
2109MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2110MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2111MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2112MODULE_FIRMWARE(FIRMWARE_RT2571);
2113MODULE_LICENSE("GPL");
2114
2115static struct usb_driver rt73usb_driver = {
2116 .name = DRV_NAME,
2117 .id_table = rt73usb_device_table,
2118 .probe = rt2x00usb_probe,
2119 .disconnect = rt2x00usb_disconnect,
2120 .suspend = rt2x00usb_suspend,
2121 .resume = rt2x00usb_resume,
2122};
2123
2124static int __init rt73usb_init(void)
2125{
2126 return usb_register(&rt73usb_driver);
2127}
2128
2129static void __exit rt73usb_exit(void)
2130{
2131 usb_deregister(&rt73usb_driver);
2132}
2133
2134module_init(rt73usb_init);
2135module_exit(rt73usb_exit);
Linux 6.x block layer and io_uring tree(s)