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rt2x00: Implement HW encryption (rt61pci)
[linux-block.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt73usb_register_read and rt73usb_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
3d82346c 51 * The _lock versions must be used if you already hold the usb_cache_mutex
95ea3627 52 */
0e14f6d3 53static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 54 const unsigned int offset, u32 *value)
55{
56 __le32 reg;
57 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
58 USB_VENDOR_REQUEST_IN, offset,
59 &reg, sizeof(u32), REGISTER_TIMEOUT);
60 *value = le32_to_cpu(reg);
61}
62
3d82346c
AB		 63static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
64 const unsigned int offset, u32 *value)
65{
66 __le32 reg;
67 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
68 USB_VENDOR_REQUEST_IN, offset,
69 &reg, sizeof(u32), REGISTER_TIMEOUT);
70 *value = le32_to_cpu(reg);
71}
72
0e14f6d3 73static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 74 const unsigned int offset,
75 void *value, const u32 length)
76{
95ea3627
ID		 77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
bd394a74
ID		 79 value, length,
80 REGISTER_TIMEOUT32(length));
95ea3627
ID		 81}
82
0e14f6d3 83static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int offset, u32 value)
85{
86 __le32 reg = cpu_to_le32(value);
87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
88 USB_VENDOR_REQUEST_OUT, offset,
89 &reg, sizeof(u32), REGISTER_TIMEOUT);
90}
91
3d82346c
AB		 92static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
93 const unsigned int offset, u32 value)
94{
95 __le32 reg = cpu_to_le32(value);
96 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
97 USB_VENDOR_REQUEST_OUT, offset,
98 &reg, sizeof(u32), REGISTER_TIMEOUT);
99}
100
0e14f6d3 101static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 102 const unsigned int offset,
103 void *value, const u32 length)
104{
95ea3627
ID		 105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
bd394a74
ID		 107 value, length,
108 REGISTER_TIMEOUT32(length));
95ea3627
ID		 109}
110
0e14f6d3 111static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 112{
113 u32 reg;
114 unsigned int i;
115
116 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 117 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 118 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
119 break;
120 udelay(REGISTER_BUSY_DELAY);
121 }
122
123 return reg;
124}
125
0e14f6d3 126static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 127 const unsigned int word, const u8 value)
128{
129 u32 reg;
130
3d82346c
AB		 131 mutex_lock(&rt2x00dev->usb_cache_mutex);
132
95ea3627
ID		 133 /*
134 * Wait until the BBP becomes ready.
135 */
136 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 137 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
138 goto exit_fail;
95ea3627
ID		 139
140 /*
141 * Write the data into the BBP.
142 */
143 reg = 0;
144 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
145 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
146 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
147 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
148
3d82346c
AB		 149 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
150 mutex_unlock(&rt2x00dev->usb_cache_mutex);
99ade259
ID		 151
152 return;
153
154exit_fail:
155 mutex_unlock(&rt2x00dev->usb_cache_mutex);
156
157 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
95ea3627
ID		 158}
159
0e14f6d3 160static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 161 const unsigned int word, u8 *value)
162{
163 u32 reg;
164
3d82346c
AB		 165 mutex_lock(&rt2x00dev->usb_cache_mutex);
166
95ea3627
ID		 167 /*
168 * Wait until the BBP becomes ready.
169 */
170 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 171 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
172 goto exit_fail;
95ea3627
ID		 173
174 /*
175 * Write the request into the BBP.
176 */
177 reg = 0;
178 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
179 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
180 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
181
3d82346c 182 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 183
184 /*
185 * Wait until the BBP becomes ready.
186 */
187 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 188 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
189 goto exit_fail;
95ea3627
ID		 190
191 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
3d82346c 192 mutex_unlock(&rt2x00dev->usb_cache_mutex);
99ade259
ID		 193
194 return;
195
196exit_fail:
197 mutex_unlock(&rt2x00dev->usb_cache_mutex);
198
199 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
200 *value = 0xff;
95ea3627
ID		 201}
202
0e14f6d3 203static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 204 const unsigned int word, const u32 value)
205{
206 u32 reg;
207 unsigned int i;
208
209 if (!word)
210 return;
211
3d82346c
AB		 212 mutex_lock(&rt2x00dev->usb_cache_mutex);
213
95ea3627 214 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 215 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 216 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
217 goto rf_write;
218 udelay(REGISTER_BUSY_DELAY);
219 }
220
3d82346c 221 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 222 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
223 return;
224
225rf_write:
226 reg = 0;
227 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
228
4f5af6eb
ID		 229 /*
230 * RF5225 and RF2527 contain 21 bits per RF register value,
231 * all others contain 20 bits.
232 */
233 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 234 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
235 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 236 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
237 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
238
3d82346c 239 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 240 rt2x00_rf_write(rt2x00dev, word, value);
3d82346c 241 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 242}
243
244#ifdef CONFIG_RT2X00_LIB_DEBUGFS
245#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
246
0e14f6d3 247static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 248 const unsigned int word, u32 *data)
249{
250 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
251}
252
0e14f6d3 253static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 254 const unsigned int word, u32 data)
255{
256 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
257}
258
259static const struct rt2x00debug rt73usb_rt2x00debug = {
260 .owner = THIS_MODULE,
261 .csr = {
262 .read = rt73usb_read_csr,
263 .write = rt73usb_write_csr,
264 .word_size = sizeof(u32),
265 .word_count = CSR_REG_SIZE / sizeof(u32),
266 },
267 .eeprom = {
268 .read = rt2x00_eeprom_read,
269 .write = rt2x00_eeprom_write,
270 .word_size = sizeof(u16),
271 .word_count = EEPROM_SIZE / sizeof(u16),
272 },
273 .bbp = {
274 .read = rt73usb_bbp_read,
275 .write = rt73usb_bbp_write,
276 .word_size = sizeof(u8),
277 .word_count = BBP_SIZE / sizeof(u8),
278 },
279 .rf = {
280 .read = rt2x00_rf_read,
281 .write = rt73usb_rf_write,
282 .word_size = sizeof(u32),
283 .word_count = RF_SIZE / sizeof(u32),
284 },
285};
286#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
287
a9450b70 288#ifdef CONFIG_RT73USB_LEDS
a2e1d52a 289static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 290 enum led_brightness brightness)
291{
292 struct rt2x00_led *led =
293 container_of(led_cdev, struct rt2x00_led, led_dev);
294 unsigned int enabled = brightness != LED_OFF;
295 unsigned int a_mode =
296 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
297 unsigned int bg_mode =
298 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
299
300 if (led->type == LED_TYPE_RADIO) {
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_RADIO_STATUS, enabled);
303
47b10cd1
ID		 304 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
305 0, led->rt2x00dev->led_mcu_reg,
306 REGISTER_TIMEOUT);
a9450b70
ID		 307 } else if (led->type == LED_TYPE_ASSOC) {
308 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
309 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
310 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
311 MCU_LEDCS_LINK_A_STATUS, a_mode);
312
47b10cd1
ID		 313 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
314 0, led->rt2x00dev->led_mcu_reg,
315 REGISTER_TIMEOUT);
a9450b70
ID		 316 } else if (led->type == LED_TYPE_QUALITY) {
317 /*
318 * The brightness is divided into 6 levels (0 - 5),
319 * this means we need to convert the brightness
320 * argument into the matching level within that range.
321 */
47b10cd1
ID		 322 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
323 brightness / (LED_FULL / 6),
324 led->rt2x00dev->led_mcu_reg,
325 REGISTER_TIMEOUT);
a9450b70
ID		 326 }
327}
a2e1d52a
ID		 328
329static int rt73usb_blink_set(struct led_classdev *led_cdev,
330 unsigned long *delay_on,
331 unsigned long *delay_off)
332{
333 struct rt2x00_led *led =
334 container_of(led_cdev, struct rt2x00_led, led_dev);
335 u32 reg;
336
337 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
338 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
339 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
340 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
341
342 return 0;
343}
475433be
ID		 344
345static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
346 struct rt2x00_led *led,
347 enum led_type type)
348{
349 led->rt2x00dev = rt2x00dev;
350 led->type = type;
351 led->led_dev.brightness_set = rt73usb_brightness_set;
352 led->led_dev.blink_set = rt73usb_blink_set;
353 led->flags = LED_INITIALIZED;
354}
a9450b70
ID		 355#endif /* CONFIG_RT73USB_LEDS */
356
95ea3627
ID		 357/*
358 * Configuration handlers.
359 */
3a643d24
ID		 360static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
361 const unsigned int filter_flags)
362{
363 u32 reg;
364
365 /*
366 * Start configuration steps.
367 * Note that the version error will always be dropped
368 * and broadcast frames will always be accepted since
369 * there is no filter for it at this time.
370 */
371 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
372 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
373 !(filter_flags & FIF_FCSFAIL));
374 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
375 !(filter_flags & FIF_PLCPFAIL));
376 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
377 !(filter_flags & FIF_CONTROL));
378 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
379 !(filter_flags & FIF_PROMISC_IN_BSS));
380 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 381 !(filter_flags & FIF_PROMISC_IN_BSS) &&
382 !rt2x00dev->intf_ap_count);
3a643d24
ID		 383 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
384 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
385 !(filter_flags & FIF_ALLMULTI));
386 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
387 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
388 !(filter_flags & FIF_CONTROL));
389 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
390}
391
6bb40dd1
ID		 392static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
393 struct rt2x00_intf *intf,
394 struct rt2x00intf_conf *conf,
395 const unsigned int flags)
95ea3627 396{
6bb40dd1
ID		 397 unsigned int beacon_base;
398 u32 reg;
95ea3627 399
6bb40dd1
ID		 400 if (flags & CONFIG_UPDATE_TYPE) {
401 /*
402 * Clear current synchronisation setup.
403 * For the Beacon base registers we only need to clear
404 * the first byte since that byte contains the VALID and OWNER
405 * bits which (when set to 0) will invalidate the entire beacon.
406 */
407 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 408 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 409
6bb40dd1
ID		 410 /*
411 * Enable synchronisation.
412 */
413 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 414 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 415 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 416 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 417 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
418 }
95ea3627 419
6bb40dd1
ID		 420 if (flags & CONFIG_UPDATE_MAC) {
421 reg = le32_to_cpu(conf->mac[1]);
422 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
423 conf->mac[1] = cpu_to_le32(reg);
95ea3627 424
6bb40dd1
ID		 425 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
426 conf->mac, sizeof(conf->mac));
427 }
95ea3627 428
6bb40dd1
ID		 429 if (flags & CONFIG_UPDATE_BSSID) {
430 reg = le32_to_cpu(conf->bssid[1]);
431 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
432 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 433
6bb40dd1
ID		 434 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
435 conf->bssid, sizeof(conf->bssid));
436 }
95ea3627
ID		 437}
438
3a643d24
ID		 439static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
440 struct rt2x00lib_erp *erp)
95ea3627 441{
95ea3627 442 u32 reg;
95ea3627 443
95ea3627 444 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 445 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 446 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
447
448 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 449 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 450 !!erp->short_preamble);
95ea3627
ID		 451 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
452}
453
454static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 455 const int basic_rate_mask)
95ea3627 456{
5c58ee51 457 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 458}
459
5c58ee51
ID		 460static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
461 struct rf_channel *rf, const int txpower)
95ea3627
ID		 462{
463 u8 r3;
464 u8 r94;
465 u8 smart;
466
467 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
468 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
469
470 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
471 rt2x00_rf(&rt2x00dev->chip, RF2527));
472
473 rt73usb_bbp_read(rt2x00dev, 3, &r3);
474 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
475 rt73usb_bbp_write(rt2x00dev, 3, r3);
476
477 r94 = 6;
478 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
479 r94 += txpower - MAX_TXPOWER;
480 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
481 r94 += txpower;
482 rt73usb_bbp_write(rt2x00dev, 94, r94);
483
484 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
485 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
486 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
487 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
488
489 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
490 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
491 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
492 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
493
494 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
495 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
496 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
497 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
498
499 udelay(10);
500}
501
95ea3627
ID		 502static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
503 const int txpower)
504{
505 struct rf_channel rf;
506
507 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
508 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
509 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
510 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
511
5c58ee51 512 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 513}
514
515static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 516 struct antenna_setup *ant)
95ea3627
ID		 517{
518 u8 r3;
519 u8 r4;
520 u8 r77;
2676c94d 521 u8 temp;
95ea3627
ID		 522
523 rt73usb_bbp_read(rt2x00dev, 3, &r3);
524 rt73usb_bbp_read(rt2x00dev, 4, &r4);
525 rt73usb_bbp_read(rt2x00dev, 77, &r77);
526
527 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
528
e4cd2ff8
ID		 529 /*
530 * Configure the RX antenna.
531 */
addc81bd 532 switch (ant->rx) {
95ea3627 533 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
535 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 536 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 537 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 538 break;
539 case ANTENNA_A:
2676c94d 540 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 541 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 542 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 543 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
544 else
545 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 546 break;
547 case ANTENNA_B:
a4fe07d9 548 default:
2676c94d 549 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 550 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 551 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 552 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
553 else
554 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 555 break;
556 }
557
558 rt73usb_bbp_write(rt2x00dev, 77, r77);
559 rt73usb_bbp_write(rt2x00dev, 3, r3);
560 rt73usb_bbp_write(rt2x00dev, 4, r4);
561}
562
563static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 564 struct antenna_setup *ant)
95ea3627
ID		 565{
566 u8 r3;
567 u8 r4;
568 u8 r77;
569
570 rt73usb_bbp_read(rt2x00dev, 3, &r3);
571 rt73usb_bbp_read(rt2x00dev, 4, &r4);
572 rt73usb_bbp_read(rt2x00dev, 77, &r77);
573
574 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
575 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
576 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
577
e4cd2ff8
ID		 578 /*
579 * Configure the RX antenna.
580 */
addc81bd 581 switch (ant->rx) {
95ea3627 582 case ANTENNA_HW_DIVERSITY:
2676c94d 583 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 584 break;
585 case ANTENNA_A:
2676c94d
MN		 586 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
587 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 588 break;
589 case ANTENNA_B:
a4fe07d9 590 default:
2676c94d
MN		 591 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
592 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 593 break;
594 }
595
596 rt73usb_bbp_write(rt2x00dev, 77, r77);
597 rt73usb_bbp_write(rt2x00dev, 3, r3);
598 rt73usb_bbp_write(rt2x00dev, 4, r4);
599}
600
601struct antenna_sel {
602 u8 word;
603 /*
604 * value[0] -> non-LNA
605 * value[1] -> LNA
606 */
607 u8 value[2];
608};
609
610static const struct antenna_sel antenna_sel_a[] = {
611 { 96, { 0x58, 0x78 } },
612 { 104, { 0x38, 0x48 } },
613 { 75, { 0xfe, 0x80 } },
614 { 86, { 0xfe, 0x80 } },
615 { 88, { 0xfe, 0x80 } },
616 { 35, { 0x60, 0x60 } },
617 { 97, { 0x58, 0x58 } },
618 { 98, { 0x58, 0x58 } },
619};
620
621static const struct antenna_sel antenna_sel_bg[] = {
622 { 96, { 0x48, 0x68 } },
623 { 104, { 0x2c, 0x3c } },
624 { 75, { 0xfe, 0x80 } },
625 { 86, { 0xfe, 0x80 } },
626 { 88, { 0xfe, 0x80 } },
627 { 35, { 0x50, 0x50 } },
628 { 97, { 0x48, 0x48 } },
629 { 98, { 0x48, 0x48 } },
630};
631
632static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 633 struct antenna_setup *ant)
95ea3627
ID		 634{
635 const struct antenna_sel *sel;
636 unsigned int lna;
637 unsigned int i;
638 u32 reg;
639
a4fe07d9
ID		 640 /*
641 * We should never come here because rt2x00lib is supposed
642 * to catch this and send us the correct antenna explicitely.
643 */
644 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
645 ant->tx == ANTENNA_SW_DIVERSITY);
646
8318d78a 647 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 648 sel = antenna_sel_a;
649 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 650 } else {
651 sel = antenna_sel_bg;
652 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 653 }
654
2676c94d
MN		 655 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
656 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
657
658 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
659
ddc827f9 660 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 661 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 662 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 663 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 664
95ea3627
ID		 665 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
666
667 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
668 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 669 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 670 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
671 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 672 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 673}
674
675static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 676 struct rt2x00lib_conf *libconf)
95ea3627
ID		 677{
678 u32 reg;
679
680 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 681 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 682 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
683
684 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 685 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 686 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 687 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 688 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
689
690 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
691 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
692 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
693
694 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
695 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
696 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
697
698 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 699 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
700 libconf->conf->beacon_int * 16);
95ea3627
ID		 701 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
702}
703
704static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 705 struct rt2x00lib_conf *libconf,
706 const unsigned int flags)
95ea3627 707{
95ea3627 708 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 709 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 710 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 711 rt73usb_config_channel(rt2x00dev, &libconf->rf,
712 libconf->conf->power_level);
95ea3627 713 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 714 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 715 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 716 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 717 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 718 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 719}
720
95ea3627
ID		 721/*
722 * Link tuning
723 */
ebcf26da
ID		 724static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
725 struct link_qual *qual)
95ea3627
ID		 726{
727 u32 reg;
728
729 /*
730 * Update FCS error count from register.
731 */
732 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 733 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 734
735 /*
736 * Update False CCA count from register.
737 */
738 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 739 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 740}
741
742static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
743{
744 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
745 rt2x00dev->link.vgc_level = 0x20;
746}
747
748static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
749{
750 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
751 u8 r17;
752 u8 up_bound;
753 u8 low_bound;
754
95ea3627
ID		 755 rt73usb_bbp_read(rt2x00dev, 17, &r17);
756
757 /*
758 * Determine r17 bounds.
759 */
8318d78a 760 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 761 low_bound = 0x28;
762 up_bound = 0x48;
763
764 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
765 low_bound += 0x10;
766 up_bound += 0x10;
767 }
768 } else {
769 if (rssi > -82) {
770 low_bound = 0x1c;
771 up_bound = 0x40;
772 } else if (rssi > -84) {
773 low_bound = 0x1c;
774 up_bound = 0x20;
775 } else {
776 low_bound = 0x1c;
777 up_bound = 0x1c;
778 }
779
780 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
781 low_bound += 0x14;
782 up_bound += 0x10;
783 }
784 }
785
6bb40dd1
ID		 786 /*
787 * If we are not associated, we should go straight to the
788 * dynamic CCA tuning.
789 */
790 if (!rt2x00dev->intf_associated)
791 goto dynamic_cca_tune;
792
95ea3627
ID		 793 /*
794 * Special big-R17 for very short distance
795 */
796 if (rssi > -35) {
797 if (r17 != 0x60)
798 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
799 return;
800 }
801
802 /*
803 * Special big-R17 for short distance
804 */
805 if (rssi >= -58) {
806 if (r17 != up_bound)
807 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
808 return;
809 }
810
811 /*
812 * Special big-R17 for middle-short distance
813 */
814 if (rssi >= -66) {
815 low_bound += 0x10;
816 if (r17 != low_bound)
817 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
818 return;
819 }
820
821 /*
822 * Special mid-R17 for middle distance
823 */
824 if (rssi >= -74) {
825 if (r17 != (low_bound + 0x10))
826 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
827 return;
828 }
829
830 /*
831 * Special case: Change up_bound based on the rssi.
832 * Lower up_bound when rssi is weaker then -74 dBm.
833 */
834 up_bound -= 2 * (-74 - rssi);
835 if (low_bound > up_bound)
836 up_bound = low_bound;
837
838 if (r17 > up_bound) {
839 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
840 return;
841 }
842
6bb40dd1
ID		 843dynamic_cca_tune:
844
95ea3627
ID		 845 /*
846 * r17 does not yet exceed upper limit, continue and base
847 * the r17 tuning on the false CCA count.
848 */
ebcf26da 849 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 850 r17 += 4;
851 if (r17 > up_bound)
852 r17 = up_bound;
853 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 854 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 855 r17 -= 4;
856 if (r17 < low_bound)
857 r17 = low_bound;
858 rt73usb_bbp_write(rt2x00dev, 17, r17);
859 }
860}
861
862/*
a7f3a06c 863 * Firmware functions
95ea3627
ID		 864 */
865static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
866{
867 return FIRMWARE_RT2571;
868}
869
f160ebcb 870static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
a7f3a06c
ID		 871{
872 u16 crc;
873
874 /*
875 * Use the crc itu-t algorithm.
876 * The last 2 bytes in the firmware array are the crc checksum itself,
877 * this means that we should never pass those 2 bytes to the crc
878 * algorithm.
879 */
880 crc = crc_itu_t(0, data, len - 2);
881 crc = crc_itu_t_byte(crc, 0);
882 crc = crc_itu_t_byte(crc, 0);
883
884 return crc;
885}
886
f160ebcb 887static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
95ea3627
ID		 888 const size_t len)
889{
890 unsigned int i;
891 int status;
892 u32 reg;
95ea3627
ID		 893
894 /*
895 * Wait for stable hardware.
896 */
897 for (i = 0; i < 100; i++) {
898 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
899 if (reg)
900 break;
901 msleep(1);
902 }
903
904 if (!reg) {
905 ERROR(rt2x00dev, "Unstable hardware.\n");
906 return -EBUSY;
907 }
908
909 /*
910 * Write firmware to device.
95ea3627 911 */
3e0c1abe
IM		 912 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
913 USB_VENDOR_REQUEST_OUT,
914 FIRMWARE_IMAGE_BASE,
915 data, len,
916 REGISTER_TIMEOUT32(len));
95ea3627
ID		 917
918 /*
919 * Send firmware request to device to load firmware,
920 * we need to specify a long timeout time.
921 */
922 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 923 0, USB_MODE_FIRMWARE,
95ea3627
ID		 924 REGISTER_TIMEOUT_FIRMWARE);
925 if (status < 0) {
926 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
927 return status;
928 }
929
95ea3627
ID		 930 return 0;
931}
932
a7f3a06c
ID		 933/*
934 * Initialization functions.
935 */
95ea3627
ID		 936static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
937{
938 u32 reg;
939
940 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
941 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
942 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
943 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
944 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
945
946 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
947 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
948 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
949 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
950 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
951 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
952 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
953 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
954 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
955 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
956
957 /*
958 * CCK TXD BBP registers
959 */
960 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
961 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
962 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
963 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
964 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
965 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
966 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
967 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
968 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
969 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
970
971 /*
972 * OFDM TXD BBP registers
973 */
974 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
975 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
976 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
977 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
978 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
979 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
980 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
981 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
982
983 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
984 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
985 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
986 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
987 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
988 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
989
990 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
991 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
992 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
993 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
994 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
995 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
996
1f909162
ID		 997 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
998 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
999 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1000 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1001 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1002 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1003 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1004 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1005
95ea3627
ID		 1006 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1007
1008 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1009 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1010 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1011
1012 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1013
1014 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1015 return -EBUSY;
1016
1017 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1018
1019 /*
1020 * Invalidate all Shared Keys (SEC_CSR0),
1021 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1022 */
1023 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1024 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1025 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1026
1027 reg = 0x000023b0;
1028 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1029 rt2x00_rf(&rt2x00dev->chip, RF2527))
1030 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1031 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1032
1033 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1034 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1035 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1036
1037 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1038 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1039 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1040 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1041
1042 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1043 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1044 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1045 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1046
1047 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1048 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1049 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1050
6bb40dd1
ID		 1051 /*
1052 * Clear all beacons
1053 * For the Beacon base registers we only need to clear
1054 * the first byte since that byte contains the VALID and OWNER
1055 * bits which (when set to 0) will invalidate the entire beacon.
1056 */
1057 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1058 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1059 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1060 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1061
95ea3627
ID		 1062 /*
1063 * We must clear the error counters.
1064 * These registers are cleared on read,
1065 * so we may pass a useless variable to store the value.
1066 */
1067 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1068 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1069 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1070
1071 /*
1072 * Reset MAC and BBP registers.
1073 */
1074 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1075 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1076 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1077 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1078
1079 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1080 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1081 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1082 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1083
1084 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1085 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1086 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1087
1088 return 0;
1089}
1090
2b08da3f 1091static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1092{
1093 unsigned int i;
95ea3627
ID		 1094 u8 value;
1095
1096 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1097 rt73usb_bbp_read(rt2x00dev, 0, &value);
1098 if ((value != 0xff) && (value != 0x00))
2b08da3f 1099 return 0;
95ea3627
ID		 1100 udelay(REGISTER_BUSY_DELAY);
1101 }
1102
1103 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1104 return -EACCES;
2b08da3f
ID		 1105}
1106
1107static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1108{
1109 unsigned int i;
1110 u16 eeprom;
1111 u8 reg_id;
1112 u8 value;
1113
1114 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1115 return -EACCES;
95ea3627 1116
95ea3627
ID		 1117 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1118 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1119 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1120 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1121 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1122 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1123 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1124 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1125 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1126 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1127 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1128 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1129 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1130 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1131 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1132 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1133 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1134 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1135 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1136 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1137 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1138 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1139 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1140 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1141 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1142
95ea3627
ID		 1143 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1144 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1145
1146 if (eeprom != 0xffff && eeprom != 0x0000) {
1147 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1148 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1149 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1150 }
1151 }
95ea3627
ID		 1152
1153 return 0;
1154}
1155
1156/*
1157 * Device state switch handlers.
1158 */
1159static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1160 enum dev_state state)
1161{
1162 u32 reg;
1163
1164 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1165 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1166 (state == STATE_RADIO_RX_OFF) ||
1167 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1168 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1169}
1170
1171static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1172{
1173 /*
1174 * Initialize all registers.
1175 */
2b08da3f
ID		 1176 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1177 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1178 return -EIO;
95ea3627 1179
95ea3627
ID		 1180 return 0;
1181}
1182
1183static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1184{
95ea3627
ID		 1185 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1186
1187 /*
1188 * Disable synchronisation.
1189 */
1190 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1191
1192 rt2x00usb_disable_radio(rt2x00dev);
1193}
1194
1195static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1196{
1197 u32 reg;
1198 unsigned int i;
1199 char put_to_sleep;
95ea3627
ID		 1200
1201 put_to_sleep = (state != STATE_AWAKE);
1202
1203 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1204 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1205 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1206 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1207
1208 /*
1209 * Device is not guaranteed to be in the requested state yet.
1210 * We must wait until the register indicates that the
1211 * device has entered the correct state.
1212 */
1213 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1214 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1215 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1216 if (state == !put_to_sleep)
95ea3627
ID		 1217 return 0;
1218 msleep(10);
1219 }
1220
95ea3627
ID		 1221 return -EBUSY;
1222}
1223
1224static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1225 enum dev_state state)
1226{
1227 int retval = 0;
1228
1229 switch (state) {
1230 case STATE_RADIO_ON:
1231 retval = rt73usb_enable_radio(rt2x00dev);
1232 break;
1233 case STATE_RADIO_OFF:
1234 rt73usb_disable_radio(rt2x00dev);
1235 break;
1236 case STATE_RADIO_RX_ON:
61667d8d 1237 case STATE_RADIO_RX_ON_LINK:
95ea3627 1238 case STATE_RADIO_RX_OFF:
61667d8d 1239 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1240 rt73usb_toggle_rx(rt2x00dev, state);
1241 break;
1242 case STATE_RADIO_IRQ_ON:
1243 case STATE_RADIO_IRQ_OFF:
1244 /* No support, but no error either */
95ea3627
ID		 1245 break;
1246 case STATE_DEEP_SLEEP:
1247 case STATE_SLEEP:
1248 case STATE_STANDBY:
1249 case STATE_AWAKE:
1250 retval = rt73usb_set_state(rt2x00dev, state);
1251 break;
1252 default:
1253 retval = -ENOTSUPP;
1254 break;
1255 }
1256
2b08da3f
ID		 1257 if (unlikely(retval))
1258 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1259 state, retval);
1260
95ea3627
ID		 1261 return retval;
1262}
1263
1264/*
1265 * TX descriptor initialization
1266 */
1267static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1268 struct sk_buff *skb,
61486e0f 1269 struct txentry_desc *txdesc)
95ea3627 1270{
181d6902 1271 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1272 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1273 u32 word;
1274
1275 /*
1276 * Start writing the descriptor words.
1277 */
1278 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1279 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1280 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1281 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1282 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627 1283 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
5adf6d63
ID		 1284 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1285 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1286 rt2x00_desc_write(txd, 1, word);
1287
1288 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1289 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1290 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1291 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1292 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1293 rt2x00_desc_write(txd, 2, word);
1294
1295 rt2x00_desc_read(txd, 5, &word);
1296 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1297 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1298 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1299 rt2x00_desc_write(txd, 5, word);
1300
1301 rt2x00_desc_read(txd, 0, &word);
1302 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1303 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1304 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1305 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1306 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1307 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1308 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1309 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1310 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1311 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1312 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1313 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1314 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1315 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1316 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
d56d453a
GW		 1317 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT,
1318 skb->len - skbdesc->desc_len);
95ea3627 1319 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1320 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1321 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1322 rt2x00_desc_write(txd, 0, word);
1323}
1324
bd88a781
ID		 1325/*
1326 * TX data initialization
1327 */
1328static void rt73usb_write_beacon(struct queue_entry *entry)
1329{
1330 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1331 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1332 unsigned int beacon_base;
1333 u32 reg;
b93ce437 1334 u32 word, len;
bd88a781
ID		 1335
1336 /*
1337 * Add the descriptor in front of the skb.
1338 */
1339 skb_push(entry->skb, entry->queue->desc_size);
1340 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1341 skbdesc->desc = entry->skb->data;
1342
b93ce437
IM		 1343 /*
1344 * Adjust the beacon databyte count. The current number is
1345 * calculated before this function gets called, but falsely
1346 * assumes that the descriptor was already present in the SKB.
1347 */
1348 rt2x00_desc_read(skbdesc->desc, 0, &word);
1349 len = rt2x00_get_field32(word, TXD_W0_DATABYTE_COUNT);
1350 len += skbdesc->desc_len;
1351 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, len);
1352 rt2x00_desc_write(skbdesc->desc, 0, word);
1353
bd88a781
ID		 1354 /*
1355 * Disable beaconing while we are reloading the beacon data,
1356 * otherwise we might be sending out invalid data.
1357 */
1358 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1359 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1360 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1361 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1362 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1363
1364 /*
1365 * Write entire beacon with descriptor to register.
1366 */
1367 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3e0c1abe
IM		 1368 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1369 USB_VENDOR_REQUEST_OUT, beacon_base,
1370 entry->skb->data, entry->skb->len,
1371 REGISTER_TIMEOUT32(entry->skb->len));
bd88a781
ID		 1372
1373 /*
1374 * Clean up the beacon skb.
1375 */
1376 dev_kfree_skb(entry->skb);
1377 entry->skb = NULL;
1378}
1379
dd9fa2d2 1380static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1381 struct sk_buff *skb)
dd9fa2d2
ID		 1382{
1383 int length;
1384
1385 /*
1386 * The length _must_ be a multiple of 4,
1387 * but it must _not_ be a multiple of the USB packet size.
1388 */
1389 length = roundup(skb->len, 4);
b242e891 1390 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1391
1392 return length;
1393}
1394
95ea3627 1395static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1396 const enum data_queue_qid queue)
95ea3627
ID		 1397{
1398 u32 reg;
1399
f019d514
ID		 1400 if (queue != QID_BEACON) {
1401 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1402 return;
f019d514 1403 }
95ea3627
ID		 1404
1405 /*
1406 * For Wi-Fi faily generated beacons between participating stations.
1407 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1408 */
1409 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1410
1411 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1412 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1413 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1414 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1415 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1416 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1417 }
1418}
1419
1420/*
1421 * RX control handlers
1422 */
1423static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1424{
1425 u16 eeprom;
1426 u8 offset;
1427 u8 lna;
1428
1429 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1430 switch (lna) {
1431 case 3:
1432 offset = 90;
1433 break;
1434 case 2:
1435 offset = 74;
1436 break;
1437 case 1:
1438 offset = 64;
1439 break;
1440 default:
1441 return 0;
1442 }
1443
8318d78a 1444 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1445 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1446 if (lna == 3 || lna == 2)
1447 offset += 10;
1448 } else {
1449 if (lna == 3)
1450 offset += 6;
1451 else if (lna == 2)
1452 offset += 8;
1453 }
1454
1455 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1456 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1457 } else {
1458 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1459 offset += 14;
1460
1461 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1462 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1463 }
1464
1465 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1466}
1467
181d6902
ID		 1468static void rt73usb_fill_rxdone(struct queue_entry *entry,
1469 struct rxdone_entry_desc *rxdesc)
95ea3627 1470{
181d6902 1471 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1472 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1473 u32 word0;
1474 u32 word1;
1475
f855c10b 1476 /*
a26cbc65
GW		 1477 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1478 * frame data in rt2x00usb.
f855c10b 1479 */
a26cbc65 1480 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1481 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1482
1483 /*
70a96109 1484 * It is now safe to read the descriptor on all architectures.
f855c10b 1485 */
95ea3627
ID		 1486 rt2x00_desc_read(rxd, 0, &word0);
1487 rt2x00_desc_read(rxd, 1, &word1);
1488
4150c572 1489 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1490 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1491
1492 /*
1493 * Obtain the status about this packet.
89993890
ID		 1494 * When frame was received with an OFDM bitrate,
1495 * the signal is the PLCP value. If it was received with
1496 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1497 */
181d6902
ID		 1498 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1499 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
181d6902 1500 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1501
19d30e02
ID		 1502 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1503 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1504 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1505 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1506
2ae23854 1507 /*
70a96109 1508 * Set skb pointers, and update frame information.
2ae23854 1509 */
70a96109 1510 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1511 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1512}
1513
1514/*
1515 * Device probe functions.
1516 */
1517static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1518{
1519 u16 word;
1520 u8 *mac;
1521 s8 value;
1522
1523 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1524
1525 /*
1526 * Start validation of the data that has been read.
1527 */
1528 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1529 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1530 DECLARE_MAC_BUF(macbuf);
1531
95ea3627 1532 random_ether_addr(mac);
0795af57 1533 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1534 }
1535
1536 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1537 if (word == 0xffff) {
1538 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1539 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1540 ANTENNA_B);
1541 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1542 ANTENNA_B);
95ea3627
ID		 1543 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1544 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1545 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1546 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1547 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1548 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1549 }
1550
1551 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1552 if (word == 0xffff) {
1553 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1554 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1555 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1556 }
1557
1558 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1559 if (word == 0xffff) {
1560 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1561 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1562 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1563 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1564 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1565 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1566 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1567 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1568 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1569 LED_MODE_DEFAULT);
1570 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1571 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1572 }
1573
1574 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1575 if (word == 0xffff) {
1576 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1577 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1578 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1579 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1580 }
1581
1582 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1583 if (word == 0xffff) {
1584 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1585 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1586 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1587 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1588 } else {
1589 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1590 if (value < -10 || value > 10)
1591 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1592 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1593 if (value < -10 || value > 10)
1594 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1595 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1596 }
1597
1598 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1599 if (word == 0xffff) {
1600 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1601 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1602 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1603 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1604 } else {
1605 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1606 if (value < -10 || value > 10)
1607 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1608 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1609 if (value < -10 || value > 10)
1610 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1611 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1612 }
1613
1614 return 0;
1615}
1616
1617static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1618{
1619 u32 reg;
1620 u16 value;
1621 u16 eeprom;
1622
1623 /*
1624 * Read EEPROM word for configuration.
1625 */
1626 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1627
1628 /*
1629 * Identify RF chipset.
1630 */
1631 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1632 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1633 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1634
755a957d 1635 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1636 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1637 return -ENODEV;
1638 }
1639
1640 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1641 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1642 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1643 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1644 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1645 return -ENODEV;
1646 }
1647
1648 /*
1649 * Identify default antenna configuration.
1650 */
addc81bd 1651 rt2x00dev->default_ant.tx =
95ea3627 1652 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1653 rt2x00dev->default_ant.rx =
95ea3627
ID		 1654 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1655
1656 /*
1657 * Read the Frame type.
1658 */
1659 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1660 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1661
1662 /*
1663 * Read frequency offset.
1664 */
1665 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1666 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1667
1668 /*
1669 * Read external LNA informations.
1670 */
1671 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1672
1673 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1674 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1675 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1676 }
1677
1678 /*
1679 * Store led settings, for correct led behaviour.
1680 */
a9450b70 1681#ifdef CONFIG_RT73USB_LEDS
95ea3627
ID		 1682 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1683
475433be
ID		 1684 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1685 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1686 if (value == LED_MODE_SIGNAL_STRENGTH)
1687 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1688 LED_TYPE_QUALITY);
a9450b70
ID		 1689
1690 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1691 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1692 rt2x00_get_field16(eeprom,
1693 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1694 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1695 rt2x00_get_field16(eeprom,
1696 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1697 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1698 rt2x00_get_field16(eeprom,
1699 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1700 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1701 rt2x00_get_field16(eeprom,
1702 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1703 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1704 rt2x00_get_field16(eeprom,
1705 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1706 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1707 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1708 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1709 rt2x00_get_field16(eeprom,
1710 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1711 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1712 rt2x00_get_field16(eeprom,
1713 EEPROM_LED_POLARITY_RDY_A));
a9450b70 1714#endif /* CONFIG_RT73USB_LEDS */
95ea3627
ID		 1715
1716 return 0;
1717}
1718
1719/*
1720 * RF value list for RF2528
1721 * Supports: 2.4 GHz
1722 */
1723static const struct rf_channel rf_vals_bg_2528[] = {
1724 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1725 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1726 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1727 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1728 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1729 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1730 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1731 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1732 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1733 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1734 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1735 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1736 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1737 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1738};
1739
1740/*
1741 * RF value list for RF5226
1742 * Supports: 2.4 GHz & 5.2 GHz
1743 */
1744static const struct rf_channel rf_vals_5226[] = {
1745 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1746 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1747 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1748 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1749 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1750 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1751 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1752 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1753 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1754 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1755 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1756 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1757 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1758 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1759
1760 /* 802.11 UNI / HyperLan 2 */
1761 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1762 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1763 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1764 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1765 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1766 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1767 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1768 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1769
1770 /* 802.11 HyperLan 2 */
1771 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1772 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1773 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1774 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1775 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1776 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1777 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1778 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1779 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1780 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1781
1782 /* 802.11 UNII */
1783 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1784 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1785 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1786 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1787 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1788 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1789
1790 /* MMAC(Japan)J52 ch 34,38,42,46 */
1791 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1792 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1793 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1794 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1795};
1796
1797/*
1798 * RF value list for RF5225 & RF2527
1799 * Supports: 2.4 GHz & 5.2 GHz
1800 */
1801static const struct rf_channel rf_vals_5225_2527[] = {
1802 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1803 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1804 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1805 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1806 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1807 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1808 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1809 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1810 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1811 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1812 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1813 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1814 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1815 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1816
1817 /* 802.11 UNI / HyperLan 2 */
1818 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1819 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1820 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1821 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1822 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1823 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1824 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1825 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1826
1827 /* 802.11 HyperLan 2 */
1828 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1829 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1830 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1831 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1832 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1833 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1834 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1835 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1836 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1837 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1838
1839 /* 802.11 UNII */
1840 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1841 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1842 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1843 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1844 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1845 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1846
1847 /* MMAC(Japan)J52 ch 34,38,42,46 */
1848 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1849 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1850 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1851 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1852};
1853
1854
1855static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1856{
1857 struct hw_mode_spec *spec = &rt2x00dev->spec;
1858 u8 *txpower;
1859 unsigned int i;
1860
1861 /*
1862 * Initialize all hw fields.
1863 */
1864 rt2x00dev->hw->flags =
566bfe5a
BR		 1865 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1866 IEEE80211_HW_SIGNAL_DBM;
95ea3627 1867 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
95ea3627 1868
14a3bf89 1869 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1870 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1871 rt2x00_eeprom_addr(rt2x00dev,
1872 EEPROM_MAC_ADDR_0));
1873
1874 /*
1875 * Convert tx_power array in eeprom.
1876 */
1877 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1878 for (i = 0; i < 14; i++)
1879 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1880
1881 /*
1882 * Initialize hw_mode information.
1883 */
31562e80
ID		 1884 spec->supported_bands = SUPPORT_BAND_2GHZ;
1885 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1886 spec->tx_power_a = NULL;
1887 spec->tx_power_bg = txpower;
1888 spec->tx_power_default = DEFAULT_TXPOWER;
1889
1890 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1891 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1892 spec->channels = rf_vals_bg_2528;
1893 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 1894 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1895 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1896 spec->channels = rf_vals_5226;
1897 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1898 spec->num_channels = 14;
1899 spec->channels = rf_vals_5225_2527;
1900 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 1901 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1902 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1903 spec->channels = rf_vals_5225_2527;
1904 }
1905
1906 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1907 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
95ea3627
ID		 1908 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1909 for (i = 0; i < 14; i++)
1910 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1911
1912 spec->tx_power_a = txpower;
1913 }
1914}
1915
1916static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1917{
1918 int retval;
1919
1920 /*
1921 * Allocate eeprom data.
1922 */
1923 retval = rt73usb_validate_eeprom(rt2x00dev);
1924 if (retval)
1925 return retval;
1926
1927 retval = rt73usb_init_eeprom(rt2x00dev);
1928 if (retval)
1929 return retval;
1930
1931 /*
1932 * Initialize hw specifications.
1933 */
1934 rt73usb_probe_hw_mode(rt2x00dev);
1935
1936 /*
9404ef34 1937 * This device requires firmware.
95ea3627 1938 */
066cb637 1939 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 1940 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
95ea3627
ID		 1941
1942 /*
1943 * Set the rssi offset.
1944 */
1945 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1946
1947 return 0;
1948}
1949
1950/*
1951 * IEEE80211 stack callback functions.
1952 */
1953static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1954 u32 short_retry, u32 long_retry)
1955{
1956 struct rt2x00_dev *rt2x00dev = hw->priv;
1957 u32 reg;
1958
1959 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1960 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1961 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1962 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1963
1964 return 0;
1965}
1966
1967#if 0
1968/*
1969 * Mac80211 demands get_tsf must be atomic.
1970 * This is not possible for rt73usb since all register access
1971 * functions require sleeping. Untill mac80211 no longer needs
1972 * get_tsf to be atomic, this function should be disabled.
1973 */
1974static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1975{
1976 struct rt2x00_dev *rt2x00dev = hw->priv;
1977 u64 tsf;
1978 u32 reg;
1979
1980 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1981 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1982 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1983 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1984
1985 return tsf;
1986}
37894473
ID		 1987#else
1988#define rt73usb_get_tsf NULL
95ea3627
ID		 1989#endif
1990
95ea3627
ID		 1991static const struct ieee80211_ops rt73usb_mac80211_ops = {
1992 .tx = rt2x00mac_tx,
4150c572
JB		 1993 .start = rt2x00mac_start,
1994 .stop = rt2x00mac_stop,
95ea3627
ID		 1995 .add_interface = rt2x00mac_add_interface,
1996 .remove_interface = rt2x00mac_remove_interface,
1997 .config = rt2x00mac_config,
1998 .config_interface = rt2x00mac_config_interface,
3a643d24 1999 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 2000 .get_stats = rt2x00mac_get_stats,
2001 .set_retry_limit = rt73usb_set_retry_limit,
471b3efd 2002 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2003 .conf_tx = rt2x00mac_conf_tx,
2004 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2005 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2006};
2007
2008static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2009 .probe_hw = rt73usb_probe_hw,
2010 .get_firmware_name = rt73usb_get_firmware_name,
a7f3a06c 2011 .get_firmware_crc = rt73usb_get_firmware_crc,
95ea3627
ID		 2012 .load_firmware = rt73usb_load_firmware,
2013 .initialize = rt2x00usb_initialize,
2014 .uninitialize = rt2x00usb_uninitialize,
837e7f24
ID		 2015 .init_rxentry = rt2x00usb_init_rxentry,
2016 .init_txentry = rt2x00usb_init_txentry,
95ea3627
ID		 2017 .set_device_state = rt73usb_set_device_state,
2018 .link_stats = rt73usb_link_stats,
2019 .reset_tuner = rt73usb_reset_tuner,
2020 .link_tuner = rt73usb_link_tuner,
2021 .write_tx_desc = rt73usb_write_tx_desc,
2022 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2023 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2024 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2025 .kick_tx_queue = rt73usb_kick_tx_queue,
2026 .fill_rxdone = rt73usb_fill_rxdone,
3a643d24 2027 .config_filter = rt73usb_config_filter,
6bb40dd1 2028 .config_intf = rt73usb_config_intf,
72810379 2029 .config_erp = rt73usb_config_erp,
95ea3627
ID		 2030 .config = rt73usb_config,
2031};
2032
181d6902
ID		 2033static const struct data_queue_desc rt73usb_queue_rx = {
2034 .entry_num = RX_ENTRIES,
2035 .data_size = DATA_FRAME_SIZE,
2036 .desc_size = RXD_DESC_SIZE,
b8be63ff 2037 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2038};
2039
2040static const struct data_queue_desc rt73usb_queue_tx = {
2041 .entry_num = TX_ENTRIES,
2042 .data_size = DATA_FRAME_SIZE,
2043 .desc_size = TXD_DESC_SIZE,
b8be63ff 2044 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2045};
2046
2047static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2048 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2049 .data_size = MGMT_FRAME_SIZE,
2050 .desc_size = TXINFO_SIZE,
b8be63ff 2051 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2052};
2053
95ea3627 2054static const struct rt2x00_ops rt73usb_ops = {
2360157c 2055 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2056 .max_sta_intf = 1,
2057 .max_ap_intf = 4,
95ea3627
ID		 2058 .eeprom_size = EEPROM_SIZE,
2059 .rf_size = RF_SIZE,
61448f88 2060 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2061 .rx = &rt73usb_queue_rx,
2062 .tx = &rt73usb_queue_tx,
2063 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2064 .lib = &rt73usb_rt2x00_ops,
2065 .hw = &rt73usb_mac80211_ops,
2066#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2067 .debugfs = &rt73usb_rt2x00debug,
2068#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2069};
2070
2071/*
2072 * rt73usb module information.
2073 */
2074static struct usb_device_id rt73usb_device_table[] = {
2075 /* AboCom */
2076 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2077 /* Askey */
2078 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2079 /* ASUS */
2080 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2081 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2082 /* Belkin */
2083 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2084 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2085 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2086 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2087 /* Billionton */
2088 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2089 /* Buffalo */
2090 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2091 /* CNet */
2092 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2093 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2094 /* Conceptronic */
2095 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2096 /* Corega */
2097 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2098 /* D-Link */
2099 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2100 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2101 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2102 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2103 /* Gemtek */
2104 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2105 /* Gigabyte */
2106 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2107 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2108 /* Huawei-3Com */
2109 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2110 /* Hercules */
2111 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2112 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2113 /* Linksys */
2114 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2115 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2116 /* MSI */
2117 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2118 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2119 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2120 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2121 /* Ralink */
2122 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2123 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2124 /* Qcom */
2125 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2126 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2127 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2128 /* Senao */
2129 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2130 /* Sitecom */
2131 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2132 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2133 /* Surecom */
2134 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2135 /* Planex */
2136 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2137 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2138 { 0, }
2139};
2140
2141MODULE_AUTHOR(DRV_PROJECT);
2142MODULE_VERSION(DRV_VERSION);
2143MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2144MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2145MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2146MODULE_FIRMWARE(FIRMWARE_RT2571);
2147MODULE_LICENSE("GPL");
2148
2149static struct usb_driver rt73usb_driver = {
2360157c 2150 .name = KBUILD_MODNAME,
95ea3627
ID		 2151 .id_table = rt73usb_device_table,
2152 .probe = rt2x00usb_probe,
2153 .disconnect = rt2x00usb_disconnect,
2154 .suspend = rt2x00usb_suspend,
2155 .resume = rt2x00usb_resume,
2156};
2157
2158static int __init rt73usb_init(void)
2159{
2160 return usb_register(&rt73usb_driver);
2161}
2162
2163static void __exit rt73usb_exit(void)
2164{
2165 usb_deregister(&rt73usb_driver);
2166}
2167
2168module_init(rt73usb_init);
2169module_exit(rt73usb_exit);
Linux 6.x block layer and io_uring tree(s)