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rt2x00: Fix queue initialization
[linux-block.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt73usb_register_read and rt73usb_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
3d82346c 51 * The _lock versions must be used if you already hold the usb_cache_mutex
95ea3627 52 */
0e14f6d3 53static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 54 const unsigned int offset, u32 *value)
55{
56 __le32 reg;
57 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
58 USB_VENDOR_REQUEST_IN, offset,
59 &reg, sizeof(u32), REGISTER_TIMEOUT);
60 *value = le32_to_cpu(reg);
61}
62
3d82346c
AB		 63static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
64 const unsigned int offset, u32 *value)
65{
66 __le32 reg;
67 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
68 USB_VENDOR_REQUEST_IN, offset,
69 &reg, sizeof(u32), REGISTER_TIMEOUT);
70 *value = le32_to_cpu(reg);
71}
72
0e14f6d3 73static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 74 const unsigned int offset,
75 void *value, const u32 length)
76{
95ea3627
ID		 77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
bd394a74
ID		 79 value, length,
80 REGISTER_TIMEOUT32(length));
95ea3627
ID		 81}
82
0e14f6d3 83static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int offset, u32 value)
85{
86 __le32 reg = cpu_to_le32(value);
87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
88 USB_VENDOR_REQUEST_OUT, offset,
89 &reg, sizeof(u32), REGISTER_TIMEOUT);
90}
91
3d82346c
AB		 92static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
93 const unsigned int offset, u32 value)
94{
95 __le32 reg = cpu_to_le32(value);
96 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
97 USB_VENDOR_REQUEST_OUT, offset,
98 &reg, sizeof(u32), REGISTER_TIMEOUT);
99}
100
0e14f6d3 101static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 102 const unsigned int offset,
103 void *value, const u32 length)
104{
95ea3627
ID		 105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
bd394a74
ID		 107 value, length,
108 REGISTER_TIMEOUT32(length));
95ea3627
ID		 109}
110
0e14f6d3 111static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 112{
113 u32 reg;
114 unsigned int i;
115
116 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 117 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 118 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
119 break;
120 udelay(REGISTER_BUSY_DELAY);
121 }
122
123 return reg;
124}
125
0e14f6d3 126static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 127 const unsigned int word, const u8 value)
128{
129 u32 reg;
130
3d82346c
AB		 131 mutex_lock(&rt2x00dev->usb_cache_mutex);
132
95ea3627
ID		 133 /*
134 * Wait until the BBP becomes ready.
135 */
136 reg = rt73usb_bbp_check(rt2x00dev);
137 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
138 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
3d82346c 139 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 140 return;
141 }
142
143 /*
144 * Write the data into the BBP.
145 */
146 reg = 0;
147 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
148 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
149 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
150 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
151
3d82346c
AB		 152 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
153 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 154}
155
0e14f6d3 156static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 157 const unsigned int word, u8 *value)
158{
159 u32 reg;
160
3d82346c
AB		 161 mutex_lock(&rt2x00dev->usb_cache_mutex);
162
95ea3627
ID		 163 /*
164 * Wait until the BBP becomes ready.
165 */
166 reg = rt73usb_bbp_check(rt2x00dev);
167 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
168 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
3d82346c 169 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 170 return;
171 }
172
173 /*
174 * Write the request into the BBP.
175 */
176 reg = 0;
177 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
178 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
179 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
180
3d82346c 181 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 182
183 /*
184 * Wait until the BBP becomes ready.
185 */
186 reg = rt73usb_bbp_check(rt2x00dev);
187 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
188 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
189 *value = 0xff;
190 return;
191 }
192
193 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
3d82346c 194 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 195}
196
0e14f6d3 197static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 198 const unsigned int word, const u32 value)
199{
200 u32 reg;
201 unsigned int i;
202
203 if (!word)
204 return;
205
3d82346c
AB		 206 mutex_lock(&rt2x00dev->usb_cache_mutex);
207
95ea3627 208 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 209 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 210 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
211 goto rf_write;
212 udelay(REGISTER_BUSY_DELAY);
213 }
214
3d82346c 215 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 216 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
217 return;
218
219rf_write:
220 reg = 0;
221 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
222
4f5af6eb
ID		 223 /*
224 * RF5225 and RF2527 contain 21 bits per RF register value,
225 * all others contain 20 bits.
226 */
227 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 228 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
229 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 230 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
231 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
232
3d82346c 233 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 234 rt2x00_rf_write(rt2x00dev, word, value);
3d82346c 235 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 236}
237
238#ifdef CONFIG_RT2X00_LIB_DEBUGFS
239#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
240
0e14f6d3 241static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 242 const unsigned int word, u32 *data)
243{
244 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
245}
246
0e14f6d3 247static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 248 const unsigned int word, u32 data)
249{
250 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
251}
252
253static const struct rt2x00debug rt73usb_rt2x00debug = {
254 .owner = THIS_MODULE,
255 .csr = {
256 .read = rt73usb_read_csr,
257 .write = rt73usb_write_csr,
258 .word_size = sizeof(u32),
259 .word_count = CSR_REG_SIZE / sizeof(u32),
260 },
261 .eeprom = {
262 .read = rt2x00_eeprom_read,
263 .write = rt2x00_eeprom_write,
264 .word_size = sizeof(u16),
265 .word_count = EEPROM_SIZE / sizeof(u16),
266 },
267 .bbp = {
268 .read = rt73usb_bbp_read,
269 .write = rt73usb_bbp_write,
270 .word_size = sizeof(u8),
271 .word_count = BBP_SIZE / sizeof(u8),
272 },
273 .rf = {
274 .read = rt2x00_rf_read,
275 .write = rt73usb_rf_write,
276 .word_size = sizeof(u32),
277 .word_count = RF_SIZE / sizeof(u32),
278 },
279};
280#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
281
a9450b70 282#ifdef CONFIG_RT73USB_LEDS
a2e1d52a 283static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 284 enum led_brightness brightness)
285{
286 struct rt2x00_led *led =
287 container_of(led_cdev, struct rt2x00_led, led_dev);
288 unsigned int enabled = brightness != LED_OFF;
289 unsigned int a_mode =
290 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
291 unsigned int bg_mode =
292 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
293
294 if (led->type == LED_TYPE_RADIO) {
295 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
296 MCU_LEDCS_RADIO_STATUS, enabled);
297
47b10cd1
ID		 298 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
299 0, led->rt2x00dev->led_mcu_reg,
300 REGISTER_TIMEOUT);
a9450b70
ID		 301 } else if (led->type == LED_TYPE_ASSOC) {
302 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
303 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
304 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
305 MCU_LEDCS_LINK_A_STATUS, a_mode);
306
47b10cd1
ID		 307 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
308 0, led->rt2x00dev->led_mcu_reg,
309 REGISTER_TIMEOUT);
a9450b70
ID		 310 } else if (led->type == LED_TYPE_QUALITY) {
311 /*
312 * The brightness is divided into 6 levels (0 - 5),
313 * this means we need to convert the brightness
314 * argument into the matching level within that range.
315 */
47b10cd1
ID		 316 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
317 brightness / (LED_FULL / 6),
318 led->rt2x00dev->led_mcu_reg,
319 REGISTER_TIMEOUT);
a9450b70
ID		 320 }
321}
a2e1d52a
ID		 322
323static int rt73usb_blink_set(struct led_classdev *led_cdev,
324 unsigned long *delay_on,
325 unsigned long *delay_off)
326{
327 struct rt2x00_led *led =
328 container_of(led_cdev, struct rt2x00_led, led_dev);
329 u32 reg;
330
331 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
332 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
333 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
334 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
335
336 return 0;
337}
475433be
ID		 338
339static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
340 struct rt2x00_led *led,
341 enum led_type type)
342{
343 led->rt2x00dev = rt2x00dev;
344 led->type = type;
345 led->led_dev.brightness_set = rt73usb_brightness_set;
346 led->led_dev.blink_set = rt73usb_blink_set;
347 led->flags = LED_INITIALIZED;
348}
a9450b70
ID		 349#endif /* CONFIG_RT73USB_LEDS */
350
95ea3627
ID		 351/*
352 * Configuration handlers.
353 */
3a643d24
ID		 354static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
355 const unsigned int filter_flags)
356{
357 u32 reg;
358
359 /*
360 * Start configuration steps.
361 * Note that the version error will always be dropped
362 * and broadcast frames will always be accepted since
363 * there is no filter for it at this time.
364 */
365 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
366 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
367 !(filter_flags & FIF_FCSFAIL));
368 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
369 !(filter_flags & FIF_PLCPFAIL));
370 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
371 !(filter_flags & FIF_CONTROL));
372 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
373 !(filter_flags & FIF_PROMISC_IN_BSS));
374 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 375 !(filter_flags & FIF_PROMISC_IN_BSS) &&
376 !rt2x00dev->intf_ap_count);
3a643d24
ID		 377 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
378 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
379 !(filter_flags & FIF_ALLMULTI));
380 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
381 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
382 !(filter_flags & FIF_CONTROL));
383 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
384}
385
6bb40dd1
ID		 386static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
387 struct rt2x00_intf *intf,
388 struct rt2x00intf_conf *conf,
389 const unsigned int flags)
95ea3627 390{
6bb40dd1
ID		 391 unsigned int beacon_base;
392 u32 reg;
95ea3627 393
6bb40dd1
ID		 394 if (flags & CONFIG_UPDATE_TYPE) {
395 /*
396 * Clear current synchronisation setup.
397 * For the Beacon base registers we only need to clear
398 * the first byte since that byte contains the VALID and OWNER
399 * bits which (when set to 0) will invalidate the entire beacon.
400 */
401 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 402 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 403
6bb40dd1
ID		 404 /*
405 * Enable synchronisation.
406 */
407 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 408 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 409 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 410 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 411 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
412 }
95ea3627 413
6bb40dd1
ID		 414 if (flags & CONFIG_UPDATE_MAC) {
415 reg = le32_to_cpu(conf->mac[1]);
416 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
417 conf->mac[1] = cpu_to_le32(reg);
95ea3627 418
6bb40dd1
ID		 419 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
420 conf->mac, sizeof(conf->mac));
421 }
95ea3627 422
6bb40dd1
ID		 423 if (flags & CONFIG_UPDATE_BSSID) {
424 reg = le32_to_cpu(conf->bssid[1]);
425 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
426 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 427
6bb40dd1
ID		 428 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
429 conf->bssid, sizeof(conf->bssid));
430 }
95ea3627
ID		 431}
432
3a643d24
ID		 433static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
434 struct rt2x00lib_erp *erp)
95ea3627 435{
95ea3627 436 u32 reg;
95ea3627 437
95ea3627 438 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 439 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 440 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
441
442 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 443 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 444 !!erp->short_preamble);
95ea3627
ID		 445 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
446}
447
448static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 449 const int basic_rate_mask)
95ea3627 450{
5c58ee51 451 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 452}
453
5c58ee51
ID		 454static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
455 struct rf_channel *rf, const int txpower)
95ea3627
ID		 456{
457 u8 r3;
458 u8 r94;
459 u8 smart;
460
461 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
462 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
463
464 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
465 rt2x00_rf(&rt2x00dev->chip, RF2527));
466
467 rt73usb_bbp_read(rt2x00dev, 3, &r3);
468 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
469 rt73usb_bbp_write(rt2x00dev, 3, r3);
470
471 r94 = 6;
472 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
473 r94 += txpower - MAX_TXPOWER;
474 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
475 r94 += txpower;
476 rt73usb_bbp_write(rt2x00dev, 94, r94);
477
478 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
479 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
480 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
481 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
482
483 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
484 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
485 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
486 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
487
488 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
489 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
490 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
491 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
492
493 udelay(10);
494}
495
95ea3627
ID		 496static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
497 const int txpower)
498{
499 struct rf_channel rf;
500
501 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
502 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
503 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
504 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
505
5c58ee51 506 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 507}
508
509static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 510 struct antenna_setup *ant)
95ea3627
ID		 511{
512 u8 r3;
513 u8 r4;
514 u8 r77;
2676c94d 515 u8 temp;
95ea3627
ID		 516
517 rt73usb_bbp_read(rt2x00dev, 3, &r3);
518 rt73usb_bbp_read(rt2x00dev, 4, &r4);
519 rt73usb_bbp_read(rt2x00dev, 77, &r77);
520
521 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
522
e4cd2ff8
ID		 523 /*
524 * Configure the RX antenna.
525 */
addc81bd 526 switch (ant->rx) {
95ea3627 527 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 528 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
529 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 530 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 531 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 532 break;
533 case ANTENNA_A:
2676c94d 534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 535 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 536 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 537 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
538 else
539 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 540 break;
541 case ANTENNA_B:
a4fe07d9 542 default:
2676c94d 543 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 544 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 545 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 546 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
547 else
548 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 549 break;
550 }
551
552 rt73usb_bbp_write(rt2x00dev, 77, r77);
553 rt73usb_bbp_write(rt2x00dev, 3, r3);
554 rt73usb_bbp_write(rt2x00dev, 4, r4);
555}
556
557static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 558 struct antenna_setup *ant)
95ea3627
ID		 559{
560 u8 r3;
561 u8 r4;
562 u8 r77;
563
564 rt73usb_bbp_read(rt2x00dev, 3, &r3);
565 rt73usb_bbp_read(rt2x00dev, 4, &r4);
566 rt73usb_bbp_read(rt2x00dev, 77, &r77);
567
568 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
569 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
570 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
571
e4cd2ff8
ID		 572 /*
573 * Configure the RX antenna.
574 */
addc81bd 575 switch (ant->rx) {
95ea3627 576 case ANTENNA_HW_DIVERSITY:
2676c94d 577 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 578 break;
579 case ANTENNA_A:
2676c94d
MN		 580 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
581 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 582 break;
583 case ANTENNA_B:
a4fe07d9 584 default:
2676c94d
MN		 585 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
586 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 587 break;
588 }
589
590 rt73usb_bbp_write(rt2x00dev, 77, r77);
591 rt73usb_bbp_write(rt2x00dev, 3, r3);
592 rt73usb_bbp_write(rt2x00dev, 4, r4);
593}
594
595struct antenna_sel {
596 u8 word;
597 /*
598 * value[0] -> non-LNA
599 * value[1] -> LNA
600 */
601 u8 value[2];
602};
603
604static const struct antenna_sel antenna_sel_a[] = {
605 { 96, { 0x58, 0x78 } },
606 { 104, { 0x38, 0x48 } },
607 { 75, { 0xfe, 0x80 } },
608 { 86, { 0xfe, 0x80 } },
609 { 88, { 0xfe, 0x80 } },
610 { 35, { 0x60, 0x60 } },
611 { 97, { 0x58, 0x58 } },
612 { 98, { 0x58, 0x58 } },
613};
614
615static const struct antenna_sel antenna_sel_bg[] = {
616 { 96, { 0x48, 0x68 } },
617 { 104, { 0x2c, 0x3c } },
618 { 75, { 0xfe, 0x80 } },
619 { 86, { 0xfe, 0x80 } },
620 { 88, { 0xfe, 0x80 } },
621 { 35, { 0x50, 0x50 } },
622 { 97, { 0x48, 0x48 } },
623 { 98, { 0x48, 0x48 } },
624};
625
626static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 627 struct antenna_setup *ant)
95ea3627
ID		 628{
629 const struct antenna_sel *sel;
630 unsigned int lna;
631 unsigned int i;
632 u32 reg;
633
a4fe07d9
ID		 634 /*
635 * We should never come here because rt2x00lib is supposed
636 * to catch this and send us the correct antenna explicitely.
637 */
638 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
639 ant->tx == ANTENNA_SW_DIVERSITY);
640
8318d78a 641 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 642 sel = antenna_sel_a;
643 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 644 } else {
645 sel = antenna_sel_bg;
646 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 647 }
648
2676c94d
MN		 649 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
650 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
651
652 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
653
ddc827f9 654 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 655 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 656 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 657 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 658
95ea3627
ID		 659 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
660
661 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
662 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 663 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 664 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
665 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 666 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 667}
668
669static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 670 struct rt2x00lib_conf *libconf)
95ea3627
ID		 671{
672 u32 reg;
673
674 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 675 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 676 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
677
678 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 679 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 680 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 681 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 682 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
683
684 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
685 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
686 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
687
688 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
689 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
690 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
691
692 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 693 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
694 libconf->conf->beacon_int * 16);
95ea3627
ID		 695 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
696}
697
698static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 699 struct rt2x00lib_conf *libconf,
700 const unsigned int flags)
95ea3627 701{
95ea3627 702 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 703 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 704 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 705 rt73usb_config_channel(rt2x00dev, &libconf->rf,
706 libconf->conf->power_level);
95ea3627 707 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 708 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 709 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 710 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 711 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 712 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 713}
714
95ea3627
ID		 715/*
716 * Link tuning
717 */
ebcf26da
ID		 718static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
719 struct link_qual *qual)
95ea3627
ID		 720{
721 u32 reg;
722
723 /*
724 * Update FCS error count from register.
725 */
726 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 727 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 728
729 /*
730 * Update False CCA count from register.
731 */
732 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 733 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 734}
735
736static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
737{
738 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
739 rt2x00dev->link.vgc_level = 0x20;
740}
741
742static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
743{
744 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
745 u8 r17;
746 u8 up_bound;
747 u8 low_bound;
748
95ea3627
ID		 749 rt73usb_bbp_read(rt2x00dev, 17, &r17);
750
751 /*
752 * Determine r17 bounds.
753 */
8318d78a 754 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 755 low_bound = 0x28;
756 up_bound = 0x48;
757
758 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
759 low_bound += 0x10;
760 up_bound += 0x10;
761 }
762 } else {
763 if (rssi > -82) {
764 low_bound = 0x1c;
765 up_bound = 0x40;
766 } else if (rssi > -84) {
767 low_bound = 0x1c;
768 up_bound = 0x20;
769 } else {
770 low_bound = 0x1c;
771 up_bound = 0x1c;
772 }
773
774 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
775 low_bound += 0x14;
776 up_bound += 0x10;
777 }
778 }
779
6bb40dd1
ID		 780 /*
781 * If we are not associated, we should go straight to the
782 * dynamic CCA tuning.
783 */
784 if (!rt2x00dev->intf_associated)
785 goto dynamic_cca_tune;
786
95ea3627
ID		 787 /*
788 * Special big-R17 for very short distance
789 */
790 if (rssi > -35) {
791 if (r17 != 0x60)
792 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
793 return;
794 }
795
796 /*
797 * Special big-R17 for short distance
798 */
799 if (rssi >= -58) {
800 if (r17 != up_bound)
801 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
802 return;
803 }
804
805 /*
806 * Special big-R17 for middle-short distance
807 */
808 if (rssi >= -66) {
809 low_bound += 0x10;
810 if (r17 != low_bound)
811 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
812 return;
813 }
814
815 /*
816 * Special mid-R17 for middle distance
817 */
818 if (rssi >= -74) {
819 if (r17 != (low_bound + 0x10))
820 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
821 return;
822 }
823
824 /*
825 * Special case: Change up_bound based on the rssi.
826 * Lower up_bound when rssi is weaker then -74 dBm.
827 */
828 up_bound -= 2 * (-74 - rssi);
829 if (low_bound > up_bound)
830 up_bound = low_bound;
831
832 if (r17 > up_bound) {
833 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
834 return;
835 }
836
6bb40dd1
ID		 837dynamic_cca_tune:
838
95ea3627
ID		 839 /*
840 * r17 does not yet exceed upper limit, continue and base
841 * the r17 tuning on the false CCA count.
842 */
ebcf26da 843 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 844 r17 += 4;
845 if (r17 > up_bound)
846 r17 = up_bound;
847 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 848 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 849 r17 -= 4;
850 if (r17 < low_bound)
851 r17 = low_bound;
852 rt73usb_bbp_write(rt2x00dev, 17, r17);
853 }
854}
855
856/*
a7f3a06c 857 * Firmware functions
95ea3627
ID		 858 */
859static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
860{
861 return FIRMWARE_RT2571;
862}
863
a7f3a06c
ID		 864static u16 rt73usb_get_firmware_crc(void *data, const size_t len)
865{
866 u16 crc;
867
868 /*
869 * Use the crc itu-t algorithm.
870 * The last 2 bytes in the firmware array are the crc checksum itself,
871 * this means that we should never pass those 2 bytes to the crc
872 * algorithm.
873 */
874 crc = crc_itu_t(0, data, len - 2);
875 crc = crc_itu_t_byte(crc, 0);
876 crc = crc_itu_t_byte(crc, 0);
877
878 return crc;
879}
880
95ea3627
ID		 881static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
882 const size_t len)
883{
884 unsigned int i;
885 int status;
886 u32 reg;
887 char *ptr = data;
888 char *cache;
889 int buflen;
95ea3627
ID		 890
891 /*
892 * Wait for stable hardware.
893 */
894 for (i = 0; i < 100; i++) {
895 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
896 if (reg)
897 break;
898 msleep(1);
899 }
900
901 if (!reg) {
902 ERROR(rt2x00dev, "Unstable hardware.\n");
903 return -EBUSY;
904 }
905
906 /*
907 * Write firmware to device.
908 * We setup a seperate cache for this action,
909 * since we are going to write larger chunks of data
910 * then normally used cache size.
911 */
912 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
913 if (!cache) {
914 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
915 return -ENOMEM;
916 }
917
918 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
919 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
95ea3627
ID		 920
921 memcpy(cache, ptr, buflen);
922
923 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
924 USB_VENDOR_REQUEST_OUT,
3b640f21 925 FIRMWARE_IMAGE_BASE + i, 0,
bd394a74
ID		 926 cache, buflen,
927 REGISTER_TIMEOUT32(buflen));
95ea3627
ID		 928
929 ptr += buflen;
930 }
931
932 kfree(cache);
933
934 /*
935 * Send firmware request to device to load firmware,
936 * we need to specify a long timeout time.
937 */
938 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 939 0, USB_MODE_FIRMWARE,
95ea3627
ID		 940 REGISTER_TIMEOUT_FIRMWARE);
941 if (status < 0) {
942 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
943 return status;
944 }
945
95ea3627
ID		 946 return 0;
947}
948
a7f3a06c
ID		 949/*
950 * Initialization functions.
951 */
95ea3627
ID		 952static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
953{
954 u32 reg;
955
956 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
957 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
958 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
959 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
960 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
961
962 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
963 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
964 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
965 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
966 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
967 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
968 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
969 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
970 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
971 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
972
973 /*
974 * CCK TXD BBP registers
975 */
976 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
977 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
978 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
979 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
980 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
981 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
982 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
983 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
984 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
985 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
986
987 /*
988 * OFDM TXD BBP registers
989 */
990 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
991 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
992 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
993 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
994 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
995 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
996 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
997 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
998
999 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1000 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1001 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1002 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1003 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1004 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1005
1006 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1007 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1008 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1009 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1010 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1011 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1012
1013 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1014
1015 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1016 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1017 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1018
1019 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1020
1021 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1022 return -EBUSY;
1023
1024 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1025
1026 /*
1027 * Invalidate all Shared Keys (SEC_CSR0),
1028 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1029 */
1030 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1031 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1032 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1033
1034 reg = 0x000023b0;
1035 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1036 rt2x00_rf(&rt2x00dev->chip, RF2527))
1037 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1038 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1039
1040 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1041 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1042 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1043
1044 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1045 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1046 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1047 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1048
1049 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1050 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1051 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1052 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1053
1054 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1055 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1056 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1057
6bb40dd1
ID		 1058 /*
1059 * Clear all beacons
1060 * For the Beacon base registers we only need to clear
1061 * the first byte since that byte contains the VALID and OWNER
1062 * bits which (when set to 0) will invalidate the entire beacon.
1063 */
1064 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1065 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1066 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1067 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1068
95ea3627
ID		 1069 /*
1070 * We must clear the error counters.
1071 * These registers are cleared on read,
1072 * so we may pass a useless variable to store the value.
1073 */
1074 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1075 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1076 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1077
1078 /*
1079 * Reset MAC and BBP registers.
1080 */
1081 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1082 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1083 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1084 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1085
1086 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1087 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1088 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1089 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1090
1091 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1092 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1093 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1094
1095 return 0;
1096}
1097
2b08da3f 1098static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1099{
1100 unsigned int i;
95ea3627
ID		 1101 u8 value;
1102
1103 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1104 rt73usb_bbp_read(rt2x00dev, 0, &value);
1105 if ((value != 0xff) && (value != 0x00))
2b08da3f 1106 return 0;
95ea3627
ID		 1107 udelay(REGISTER_BUSY_DELAY);
1108 }
1109
1110 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1111 return -EACCES;
2b08da3f
ID		 1112}
1113
1114static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1115{
1116 unsigned int i;
1117 u16 eeprom;
1118 u8 reg_id;
1119 u8 value;
1120
1121 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1122 return -EACCES;
95ea3627 1123
95ea3627
ID		 1124 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1125 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1126 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1127 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1128 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1129 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1130 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1131 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1132 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1133 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1134 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1135 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1136 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1137 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1138 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1139 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1140 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1141 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1142 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1143 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1144 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1145 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1146 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1147 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1148 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1149
95ea3627
ID		 1150 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1151 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1152
1153 if (eeprom != 0xffff && eeprom != 0x0000) {
1154 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1155 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1156 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1157 }
1158 }
95ea3627
ID		 1159
1160 return 0;
1161}
1162
1163/*
1164 * Device state switch handlers.
1165 */
1166static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1167 enum dev_state state)
1168{
1169 u32 reg;
1170
1171 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1172 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1173 (state == STATE_RADIO_RX_OFF) ||
1174 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1175 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1176}
1177
1178static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1179{
1180 /*
1181 * Initialize all registers.
1182 */
2b08da3f
ID		 1183 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1184 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1185 return -EIO;
95ea3627 1186
95ea3627
ID		 1187 return 0;
1188}
1189
1190static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1191{
95ea3627
ID		 1192 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1193
1194 /*
1195 * Disable synchronisation.
1196 */
1197 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1198
1199 rt2x00usb_disable_radio(rt2x00dev);
1200}
1201
1202static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1203{
1204 u32 reg;
1205 unsigned int i;
1206 char put_to_sleep;
95ea3627
ID		 1207
1208 put_to_sleep = (state != STATE_AWAKE);
1209
1210 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1211 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1212 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1213 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1214
1215 /*
1216 * Device is not guaranteed to be in the requested state yet.
1217 * We must wait until the register indicates that the
1218 * device has entered the correct state.
1219 */
1220 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1221 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1222 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1223 if (state == !put_to_sleep)
95ea3627
ID		 1224 return 0;
1225 msleep(10);
1226 }
1227
95ea3627
ID		 1228 return -EBUSY;
1229}
1230
1231static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1232 enum dev_state state)
1233{
1234 int retval = 0;
1235
1236 switch (state) {
1237 case STATE_RADIO_ON:
1238 retval = rt73usb_enable_radio(rt2x00dev);
1239 break;
1240 case STATE_RADIO_OFF:
1241 rt73usb_disable_radio(rt2x00dev);
1242 break;
1243 case STATE_RADIO_RX_ON:
61667d8d 1244 case STATE_RADIO_RX_ON_LINK:
95ea3627 1245 case STATE_RADIO_RX_OFF:
61667d8d 1246 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1247 rt73usb_toggle_rx(rt2x00dev, state);
1248 break;
1249 case STATE_RADIO_IRQ_ON:
1250 case STATE_RADIO_IRQ_OFF:
1251 /* No support, but no error either */
95ea3627
ID		 1252 break;
1253 case STATE_DEEP_SLEEP:
1254 case STATE_SLEEP:
1255 case STATE_STANDBY:
1256 case STATE_AWAKE:
1257 retval = rt73usb_set_state(rt2x00dev, state);
1258 break;
1259 default:
1260 retval = -ENOTSUPP;
1261 break;
1262 }
1263
2b08da3f
ID		 1264 if (unlikely(retval))
1265 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1266 state, retval);
1267
95ea3627
ID		 1268 return retval;
1269}
1270
1271/*
1272 * TX descriptor initialization
1273 */
1274static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1275 struct sk_buff *skb,
61486e0f 1276 struct txentry_desc *txdesc)
95ea3627 1277{
181d6902 1278 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1279 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1280 u32 word;
1281
1282 /*
1283 * Start writing the descriptor words.
1284 */
1285 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1286 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1287 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1288 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1289 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1290 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1291 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1292 rt2x00_desc_write(txd, 1, word);
1293
1294 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1295 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1296 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1297 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1298 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1299 rt2x00_desc_write(txd, 2, word);
1300
1301 rt2x00_desc_read(txd, 5, &word);
1302 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1303 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1304 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1305 rt2x00_desc_write(txd, 5, word);
1306
1307 rt2x00_desc_read(txd, 0, &word);
1308 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1309 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1310 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1311 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1312 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1313 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1314 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1315 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1316 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1317 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1318 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1319 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1320 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1321 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1322 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1323 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1324 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1325 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1326 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1327 rt2x00_desc_write(txd, 0, word);
1328}
1329
dd9fa2d2 1330static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1331 struct sk_buff *skb)
dd9fa2d2
ID		 1332{
1333 int length;
1334
1335 /*
1336 * The length _must_ be a multiple of 4,
1337 * but it must _not_ be a multiple of the USB packet size.
1338 */
1339 length = roundup(skb->len, 4);
b242e891 1340 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1341
1342 return length;
1343}
1344
95ea3627
ID		 1345/*
1346 * TX data initialization
1347 */
1348static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1349 const enum data_queue_qid queue)
95ea3627
ID		 1350{
1351 u32 reg;
1352
e58c6aca 1353 if (queue != QID_BEACON)
95ea3627
ID		 1354 return;
1355
1356 /*
1357 * For Wi-Fi faily generated beacons between participating stations.
1358 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1359 */
1360 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1361
1362 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1363 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1364 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1365 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1366 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1367 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1368 }
1369}
1370
1371/*
1372 * RX control handlers
1373 */
1374static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1375{
1376 u16 eeprom;
1377 u8 offset;
1378 u8 lna;
1379
1380 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1381 switch (lna) {
1382 case 3:
1383 offset = 90;
1384 break;
1385 case 2:
1386 offset = 74;
1387 break;
1388 case 1:
1389 offset = 64;
1390 break;
1391 default:
1392 return 0;
1393 }
1394
8318d78a 1395 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1396 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1397 if (lna == 3 || lna == 2)
1398 offset += 10;
1399 } else {
1400 if (lna == 3)
1401 offset += 6;
1402 else if (lna == 2)
1403 offset += 8;
1404 }
1405
1406 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1407 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1408 } else {
1409 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1410 offset += 14;
1411
1412 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1413 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1414 }
1415
1416 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1417}
1418
181d6902
ID		 1419static void rt73usb_fill_rxdone(struct queue_entry *entry,
1420 struct rxdone_entry_desc *rxdesc)
95ea3627 1421{
181d6902 1422 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1423 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1424 u32 word0;
1425 u32 word1;
1426
f855c10b 1427 /*
70a96109
ID		 1428 * Copy descriptor to the skb->cb array, this has 2 benefits:
1429 * 1) Each descriptor word is 4 byte aligned.
1430 * 2) Descriptor is safe from moving of frame data in rt2x00usb.
f855c10b 1431 */
70a96109
ID		 1432 skbdesc->desc_len =
1433 min_t(u16, entry->queue->desc_size, sizeof(entry->skb->cb));
1434 memcpy(entry->skb->cb, rxd, skbdesc->desc_len);
1435 skbdesc->desc = entry->skb->cb;
1436 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1437
1438 /*
70a96109 1439 * It is now safe to read the descriptor on all architectures.
f855c10b 1440 */
95ea3627
ID		 1441 rt2x00_desc_read(rxd, 0, &word0);
1442 rt2x00_desc_read(rxd, 1, &word1);
1443
4150c572 1444 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1445 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1446
1447 /*
1448 * Obtain the status about this packet.
89993890
ID		 1449 * When frame was received with an OFDM bitrate,
1450 * the signal is the PLCP value. If it was received with
1451 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1452 */
181d6902
ID		 1453 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1454 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
181d6902 1455 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1456
19d30e02
ID		 1457 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1458 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1459 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1460 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1461
2ae23854 1462 /*
70a96109 1463 * Set skb pointers, and update frame information.
2ae23854 1464 */
70a96109 1465 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1466 skb_trim(entry->skb, rxdesc->size);
f855c10b 1467 skbdesc->data = entry->skb->data;
647d0ca9 1468 skbdesc->data_len = rxdesc->size;
95ea3627
ID		 1469}
1470
1471/*
1472 * Device probe functions.
1473 */
1474static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1475{
1476 u16 word;
1477 u8 *mac;
1478 s8 value;
1479
1480 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1481
1482 /*
1483 * Start validation of the data that has been read.
1484 */
1485 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1486 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1487 DECLARE_MAC_BUF(macbuf);
1488
95ea3627 1489 random_ether_addr(mac);
0795af57 1490 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1491 }
1492
1493 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1494 if (word == 0xffff) {
1495 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1496 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1497 ANTENNA_B);
1498 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1499 ANTENNA_B);
95ea3627
ID		 1500 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1501 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1502 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1503 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1504 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1505 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1506 }
1507
1508 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1509 if (word == 0xffff) {
1510 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1511 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1512 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1513 }
1514
1515 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1516 if (word == 0xffff) {
1517 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1518 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1519 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1520 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1521 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1522 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1523 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1524 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1525 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1526 LED_MODE_DEFAULT);
1527 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1528 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1529 }
1530
1531 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1532 if (word == 0xffff) {
1533 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1534 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1535 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1536 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1537 }
1538
1539 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1540 if (word == 0xffff) {
1541 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1542 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1543 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1544 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1545 } else {
1546 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1547 if (value < -10 || value > 10)
1548 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1549 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1550 if (value < -10 || value > 10)
1551 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1552 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1553 }
1554
1555 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1556 if (word == 0xffff) {
1557 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1558 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1559 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1560 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1561 } else {
1562 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1563 if (value < -10 || value > 10)
1564 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1565 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1566 if (value < -10 || value > 10)
1567 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1568 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1569 }
1570
1571 return 0;
1572}
1573
1574static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1575{
1576 u32 reg;
1577 u16 value;
1578 u16 eeprom;
1579
1580 /*
1581 * Read EEPROM word for configuration.
1582 */
1583 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1584
1585 /*
1586 * Identify RF chipset.
1587 */
1588 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1589 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1590 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1591
755a957d 1592 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1593 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1594 return -ENODEV;
1595 }
1596
1597 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1598 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1599 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1600 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1601 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1602 return -ENODEV;
1603 }
1604
1605 /*
1606 * Identify default antenna configuration.
1607 */
addc81bd 1608 rt2x00dev->default_ant.tx =
95ea3627 1609 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1610 rt2x00dev->default_ant.rx =
95ea3627
ID		 1611 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1612
1613 /*
1614 * Read the Frame type.
1615 */
1616 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1617 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1618
1619 /*
1620 * Read frequency offset.
1621 */
1622 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1623 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1624
1625 /*
1626 * Read external LNA informations.
1627 */
1628 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1629
1630 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1631 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1632 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1633 }
1634
1635 /*
1636 * Store led settings, for correct led behaviour.
1637 */
a9450b70 1638#ifdef CONFIG_RT73USB_LEDS
95ea3627
ID		 1639 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1640
475433be
ID		 1641 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1642 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1643 if (value == LED_MODE_SIGNAL_STRENGTH)
1644 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1645 LED_TYPE_QUALITY);
a9450b70
ID		 1646
1647 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1648 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1649 rt2x00_get_field16(eeprom,
1650 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1651 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1652 rt2x00_get_field16(eeprom,
1653 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1654 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1655 rt2x00_get_field16(eeprom,
1656 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1657 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1658 rt2x00_get_field16(eeprom,
1659 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1660 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1661 rt2x00_get_field16(eeprom,
1662 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1663 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1664 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1665 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1666 rt2x00_get_field16(eeprom,
1667 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1668 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1669 rt2x00_get_field16(eeprom,
1670 EEPROM_LED_POLARITY_RDY_A));
a9450b70 1671#endif /* CONFIG_RT73USB_LEDS */
95ea3627
ID		 1672
1673 return 0;
1674}
1675
1676/*
1677 * RF value list for RF2528
1678 * Supports: 2.4 GHz
1679 */
1680static const struct rf_channel rf_vals_bg_2528[] = {
1681 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1682 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1683 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1684 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1685 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1686 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1687 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1688 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1689 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1690 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1691 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1692 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1693 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1694 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1695};
1696
1697/*
1698 * RF value list for RF5226
1699 * Supports: 2.4 GHz & 5.2 GHz
1700 */
1701static const struct rf_channel rf_vals_5226[] = {
1702 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1703 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1704 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1705 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1706 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1707 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1708 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1709 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1710 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1711 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1712 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1713 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1714 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1715 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1716
1717 /* 802.11 UNI / HyperLan 2 */
1718 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1719 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1720 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1721 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1722 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1723 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1724 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1725 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1726
1727 /* 802.11 HyperLan 2 */
1728 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1729 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1730 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1731 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1732 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1733 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1734 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1735 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1736 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1737 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1738
1739 /* 802.11 UNII */
1740 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1741 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1742 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1743 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1744 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1745 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1746
1747 /* MMAC(Japan)J52 ch 34,38,42,46 */
1748 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1749 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1750 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1751 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1752};
1753
1754/*
1755 * RF value list for RF5225 & RF2527
1756 * Supports: 2.4 GHz & 5.2 GHz
1757 */
1758static const struct rf_channel rf_vals_5225_2527[] = {
1759 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1760 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1761 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1762 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1763 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1764 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1765 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1766 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1767 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1768 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1769 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1770 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1771 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1772 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1773
1774 /* 802.11 UNI / HyperLan 2 */
1775 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1776 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1777 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1778 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1779 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1780 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1781 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1782 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1783
1784 /* 802.11 HyperLan 2 */
1785 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1786 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1787 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1788 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1789 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1790 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1791 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1792 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1793 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1794 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1795
1796 /* 802.11 UNII */
1797 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1798 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1799 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1800 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1801 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1802 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1803
1804 /* MMAC(Japan)J52 ch 34,38,42,46 */
1805 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1806 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1807 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1808 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1809};
1810
1811
1812static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1813{
1814 struct hw_mode_spec *spec = &rt2x00dev->spec;
1815 u8 *txpower;
1816 unsigned int i;
1817
1818 /*
1819 * Initialize all hw fields.
1820 */
1821 rt2x00dev->hw->flags =
1822 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
566bfe5a
BR		 1823 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1824 IEEE80211_HW_SIGNAL_DBM;
95ea3627 1825 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
95ea3627
ID		 1826
1827 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1828 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1829 rt2x00_eeprom_addr(rt2x00dev,
1830 EEPROM_MAC_ADDR_0));
1831
1832 /*
1833 * Convert tx_power array in eeprom.
1834 */
1835 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1836 for (i = 0; i < 14; i++)
1837 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1838
1839 /*
1840 * Initialize hw_mode information.
1841 */
31562e80
ID		 1842 spec->supported_bands = SUPPORT_BAND_2GHZ;
1843 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1844 spec->tx_power_a = NULL;
1845 spec->tx_power_bg = txpower;
1846 spec->tx_power_default = DEFAULT_TXPOWER;
1847
1848 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1849 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1850 spec->channels = rf_vals_bg_2528;
1851 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 1852 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1853 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1854 spec->channels = rf_vals_5226;
1855 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1856 spec->num_channels = 14;
1857 spec->channels = rf_vals_5225_2527;
1858 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 1859 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1860 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1861 spec->channels = rf_vals_5225_2527;
1862 }
1863
1864 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1865 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
95ea3627
ID		 1866 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1867 for (i = 0; i < 14; i++)
1868 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1869
1870 spec->tx_power_a = txpower;
1871 }
1872}
1873
1874static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1875{
1876 int retval;
1877
1878 /*
1879 * Allocate eeprom data.
1880 */
1881 retval = rt73usb_validate_eeprom(rt2x00dev);
1882 if (retval)
1883 return retval;
1884
1885 retval = rt73usb_init_eeprom(rt2x00dev);
1886 if (retval)
1887 return retval;
1888
1889 /*
1890 * Initialize hw specifications.
1891 */
1892 rt73usb_probe_hw_mode(rt2x00dev);
1893
1894 /*
9404ef34 1895 * This device requires firmware.
95ea3627 1896 */
066cb637 1897 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 1898 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
95ea3627
ID		 1899
1900 /*
1901 * Set the rssi offset.
1902 */
1903 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1904
1905 return 0;
1906}
1907
1908/*
1909 * IEEE80211 stack callback functions.
1910 */
1911static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1912 u32 short_retry, u32 long_retry)
1913{
1914 struct rt2x00_dev *rt2x00dev = hw->priv;
1915 u32 reg;
1916
1917 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1918 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1919 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1920 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1921
1922 return 0;
1923}
1924
1925#if 0
1926/*
1927 * Mac80211 demands get_tsf must be atomic.
1928 * This is not possible for rt73usb since all register access
1929 * functions require sleeping. Untill mac80211 no longer needs
1930 * get_tsf to be atomic, this function should be disabled.
1931 */
1932static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1933{
1934 struct rt2x00_dev *rt2x00dev = hw->priv;
1935 u64 tsf;
1936 u32 reg;
1937
1938 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1939 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1940 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1941 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1942
1943 return tsf;
1944}
37894473
ID		 1945#else
1946#define rt73usb_get_tsf NULL
95ea3627
ID		 1947#endif
1948
e039fa4a 1949static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
95ea3627
ID		 1950{
1951 struct rt2x00_dev *rt2x00dev = hw->priv;
e039fa4a
JB		 1952 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1953 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
181d6902 1954 struct skb_frame_desc *skbdesc;
7050ec82 1955 struct txentry_desc txdesc;
6bb40dd1 1956 unsigned int beacon_base;
8af244cc 1957 u32 reg;
95ea3627 1958
6bb40dd1
ID		 1959 if (unlikely(!intf->beacon))
1960 return -ENOBUFS;
95ea3627 1961
7050ec82
ID		 1962 /*
1963 * Copy all TX descriptor information into txdesc,
1964 * after that we are free to use the skb->cb array
1965 * for our information.
1966 */
1967 intf->beacon->skb = skb;
e039fa4a 1968 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
7050ec82 1969
95ea3627 1970 /*
08992f7f 1971 * Add the descriptor in front of the skb.
95ea3627 1972 */
6bb40dd1
ID		 1973 skb_push(skb, intf->beacon->queue->desc_size);
1974 memset(skb->data, 0, intf->beacon->queue->desc_size);
c22eb87b 1975
08992f7f
ID		 1976 /*
1977 * Fill in skb descriptor
1978 */
181d6902
ID		 1979 skbdesc = get_skb_frame_desc(skb);
1980 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1981 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
6bb40dd1
ID		 1982 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
1983 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 1984 skbdesc->desc = skb->data;
6bb40dd1
ID		 1985 skbdesc->desc_len = intf->beacon->queue->desc_size;
1986 skbdesc->entry = intf->beacon;
08992f7f 1987
8af244cc
ID		 1988 /*
1989 * Disable beaconing while we are reloading the beacon data,
1990 * otherwise we might be sending out invalid data.
1991 */
1992 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1993 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1994 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1995 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1996 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1997
95ea3627
ID		 1998 /*
1999 * Write entire beacon with descriptor to register,
2000 * and kick the beacon generator.
2001 */
7050ec82 2002 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
6bb40dd1 2003 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
95ea3627 2004 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
6bb40dd1 2005 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
bd394a74
ID		 2006 skb->data, skb->len,
2007 REGISTER_TIMEOUT32(skb->len));
e58c6aca 2008 rt73usb_kick_tx_queue(rt2x00dev, QID_BEACON);
95ea3627
ID		 2009
2010 return 0;
2011}
2012
2013static const struct ieee80211_ops rt73usb_mac80211_ops = {
2014 .tx = rt2x00mac_tx,
4150c572
JB		 2015 .start = rt2x00mac_start,
2016 .stop = rt2x00mac_stop,
95ea3627
ID		 2017 .add_interface = rt2x00mac_add_interface,
2018 .remove_interface = rt2x00mac_remove_interface,
2019 .config = rt2x00mac_config,
2020 .config_interface = rt2x00mac_config_interface,
3a643d24 2021 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 2022 .get_stats = rt2x00mac_get_stats,
2023 .set_retry_limit = rt73usb_set_retry_limit,
471b3efd 2024 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2025 .conf_tx = rt2x00mac_conf_tx,
2026 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2027 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2028 .beacon_update = rt73usb_beacon_update,
2029};
2030
2031static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2032 .probe_hw = rt73usb_probe_hw,
2033 .get_firmware_name = rt73usb_get_firmware_name,
a7f3a06c 2034 .get_firmware_crc = rt73usb_get_firmware_crc,
95ea3627
ID		 2035 .load_firmware = rt73usb_load_firmware,
2036 .initialize = rt2x00usb_initialize,
2037 .uninitialize = rt2x00usb_uninitialize,
837e7f24
ID		 2038 .init_rxentry = rt2x00usb_init_rxentry,
2039 .init_txentry = rt2x00usb_init_txentry,
95ea3627
ID		 2040 .set_device_state = rt73usb_set_device_state,
2041 .link_stats = rt73usb_link_stats,
2042 .reset_tuner = rt73usb_reset_tuner,
2043 .link_tuner = rt73usb_link_tuner,
2044 .write_tx_desc = rt73usb_write_tx_desc,
2045 .write_tx_data = rt2x00usb_write_tx_data,
dd9fa2d2 2046 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2047 .kick_tx_queue = rt73usb_kick_tx_queue,
2048 .fill_rxdone = rt73usb_fill_rxdone,
3a643d24 2049 .config_filter = rt73usb_config_filter,
6bb40dd1 2050 .config_intf = rt73usb_config_intf,
72810379 2051 .config_erp = rt73usb_config_erp,
95ea3627
ID		 2052 .config = rt73usb_config,
2053};
2054
181d6902
ID		 2055static const struct data_queue_desc rt73usb_queue_rx = {
2056 .entry_num = RX_ENTRIES,
2057 .data_size = DATA_FRAME_SIZE,
2058 .desc_size = RXD_DESC_SIZE,
b8be63ff 2059 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2060};
2061
2062static const struct data_queue_desc rt73usb_queue_tx = {
2063 .entry_num = TX_ENTRIES,
2064 .data_size = DATA_FRAME_SIZE,
2065 .desc_size = TXD_DESC_SIZE,
b8be63ff 2066 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2067};
2068
2069static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2070 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2071 .data_size = MGMT_FRAME_SIZE,
2072 .desc_size = TXINFO_SIZE,
b8be63ff 2073 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2074};
2075
95ea3627 2076static const struct rt2x00_ops rt73usb_ops = {
2360157c 2077 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2078 .max_sta_intf = 1,
2079 .max_ap_intf = 4,
95ea3627
ID		 2080 .eeprom_size = EEPROM_SIZE,
2081 .rf_size = RF_SIZE,
61448f88 2082 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2083 .rx = &rt73usb_queue_rx,
2084 .tx = &rt73usb_queue_tx,
2085 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2086 .lib = &rt73usb_rt2x00_ops,
2087 .hw = &rt73usb_mac80211_ops,
2088#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2089 .debugfs = &rt73usb_rt2x00debug,
2090#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2091};
2092
2093/*
2094 * rt73usb module information.
2095 */
2096static struct usb_device_id rt73usb_device_table[] = {
2097 /* AboCom */
2098 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2099 /* Askey */
2100 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2101 /* ASUS */
2102 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2103 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2104 /* Belkin */
2105 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2106 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2107 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2108 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2109 /* Billionton */
2110 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2111 /* Buffalo */
2112 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2113 /* CNet */
2114 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2115 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2116 /* Conceptronic */
2117 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2118 /* Corega */
2119 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2120 /* D-Link */
2121 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2122 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2123 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2124 /* Gemtek */
2125 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2126 /* Gigabyte */
2127 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2128 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2129 /* Huawei-3Com */
2130 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2131 /* Hercules */
2132 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2133 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2134 /* Linksys */
2135 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2136 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2137 /* MSI */
2138 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2139 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2140 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2141 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2142 /* Ralink */
2143 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2144 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2145 /* Qcom */
2146 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2147 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2148 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2149 /* Senao */
2150 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2151 /* Sitecom */
2152 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2153 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2154 /* Surecom */
2155 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2156 /* Planex */
2157 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2158 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2159 { 0, }
2160};
2161
2162MODULE_AUTHOR(DRV_PROJECT);
2163MODULE_VERSION(DRV_VERSION);
2164MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2165MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2166MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2167MODULE_FIRMWARE(FIRMWARE_RT2571);
2168MODULE_LICENSE("GPL");
2169
2170static struct usb_driver rt73usb_driver = {
2360157c 2171 .name = KBUILD_MODNAME,
95ea3627
ID		 2172 .id_table = rt73usb_device_table,
2173 .probe = rt2x00usb_probe,
2174 .disconnect = rt2x00usb_disconnect,
2175 .suspend = rt2x00usb_suspend,
2176 .resume = rt2x00usb_resume,
2177};
2178
2179static int __init rt73usb_init(void)
2180{
2181 return usb_register(&rt73usb_driver);
2182}
2183
2184static void __exit rt73usb_exit(void)
2185{
2186 usb_deregister(&rt73usb_driver);
2187}
2188
2189module_init(rt73usb_init);
2190module_exit(rt73usb_exit);
Linux 6.x block layer and io_uring tree(s)