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95ea3627 ID |
1 | /* |
2 | Copyright (C) 2004 - 2007 rt2x00 SourceForge Project | |
3 | <http://rt2x00.serialmonkey.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt73usb | |
23 | Abstract: rt73usb device specific routines. | |
24 | Supported chipsets: rt2571W & rt2671. | |
25 | */ | |
26 | ||
27 | /* | |
28 | * Set enviroment defines for rt2x00.h | |
29 | */ | |
30 | #define DRV_NAME "rt73usb" | |
31 | ||
32 | #include <linux/delay.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/usb.h> | |
38 | ||
39 | #include "rt2x00.h" | |
40 | #include "rt2x00usb.h" | |
41 | #include "rt73usb.h" | |
42 | ||
43 | /* | |
44 | * Register access. | |
45 | * All access to the CSR registers will go through the methods | |
46 | * rt73usb_register_read and rt73usb_register_write. | |
47 | * BBP and RF register require indirect register access, | |
48 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
49 | * These indirect registers work with busy bits, | |
50 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
51 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
52 | * between each attampt. When the busy bit is still set at that time, | |
53 | * the access attempt is considered to have failed, | |
54 | * and we will print an error. | |
55 | */ | |
56 | static inline void rt73usb_register_read(const struct rt2x00_dev *rt2x00dev, | |
57 | const unsigned int offset, u32 *value) | |
58 | { | |
59 | __le32 reg; | |
60 | rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ, | |
61 | USB_VENDOR_REQUEST_IN, offset, | |
62 | ®, sizeof(u32), REGISTER_TIMEOUT); | |
63 | *value = le32_to_cpu(reg); | |
64 | } | |
65 | ||
66 | static inline void rt73usb_register_multiread(const struct rt2x00_dev | |
67 | *rt2x00dev, | |
68 | const unsigned int offset, | |
69 | void *value, const u32 length) | |
70 | { | |
71 | int timeout = REGISTER_TIMEOUT * (length / sizeof(u32)); | |
72 | rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ, | |
73 | USB_VENDOR_REQUEST_IN, offset, | |
74 | value, length, timeout); | |
75 | } | |
76 | ||
77 | static inline void rt73usb_register_write(const struct rt2x00_dev *rt2x00dev, | |
78 | const unsigned int offset, u32 value) | |
79 | { | |
80 | __le32 reg = cpu_to_le32(value); | |
81 | rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE, | |
82 | USB_VENDOR_REQUEST_OUT, offset, | |
83 | ®, sizeof(u32), REGISTER_TIMEOUT); | |
84 | } | |
85 | ||
86 | static inline void rt73usb_register_multiwrite(const struct rt2x00_dev | |
87 | *rt2x00dev, | |
88 | const unsigned int offset, | |
89 | void *value, const u32 length) | |
90 | { | |
91 | int timeout = REGISTER_TIMEOUT * (length / sizeof(u32)); | |
92 | rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE, | |
93 | USB_VENDOR_REQUEST_OUT, offset, | |
94 | value, length, timeout); | |
95 | } | |
96 | ||
97 | static u32 rt73usb_bbp_check(const struct rt2x00_dev *rt2x00dev) | |
98 | { | |
99 | u32 reg; | |
100 | unsigned int i; | |
101 | ||
102 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
103 | rt73usb_register_read(rt2x00dev, PHY_CSR3, ®); | |
104 | if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY)) | |
105 | break; | |
106 | udelay(REGISTER_BUSY_DELAY); | |
107 | } | |
108 | ||
109 | return reg; | |
110 | } | |
111 | ||
112 | static void rt73usb_bbp_write(const struct rt2x00_dev *rt2x00dev, | |
113 | const unsigned int word, const u8 value) | |
114 | { | |
115 | u32 reg; | |
116 | ||
117 | /* | |
118 | * Wait until the BBP becomes ready. | |
119 | */ | |
120 | reg = rt73usb_bbp_check(rt2x00dev); | |
121 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { | |
122 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n"); | |
123 | return; | |
124 | } | |
125 | ||
126 | /* | |
127 | * Write the data into the BBP. | |
128 | */ | |
129 | reg = 0; | |
130 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); | |
131 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
132 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
133 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); | |
134 | ||
135 | rt73usb_register_write(rt2x00dev, PHY_CSR3, reg); | |
136 | } | |
137 | ||
138 | static void rt73usb_bbp_read(const struct rt2x00_dev *rt2x00dev, | |
139 | const unsigned int word, u8 *value) | |
140 | { | |
141 | u32 reg; | |
142 | ||
143 | /* | |
144 | * Wait until the BBP becomes ready. | |
145 | */ | |
146 | reg = rt73usb_bbp_check(rt2x00dev); | |
147 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { | |
148 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n"); | |
149 | return; | |
150 | } | |
151 | ||
152 | /* | |
153 | * Write the request into the BBP. | |
154 | */ | |
155 | reg = 0; | |
156 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
157 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
158 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); | |
159 | ||
160 | rt73usb_register_write(rt2x00dev, PHY_CSR3, reg); | |
161 | ||
162 | /* | |
163 | * Wait until the BBP becomes ready. | |
164 | */ | |
165 | reg = rt73usb_bbp_check(rt2x00dev); | |
166 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { | |
167 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n"); | |
168 | *value = 0xff; | |
169 | return; | |
170 | } | |
171 | ||
172 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); | |
173 | } | |
174 | ||
175 | static void rt73usb_rf_write(const struct rt2x00_dev *rt2x00dev, | |
176 | const unsigned int word, const u32 value) | |
177 | { | |
178 | u32 reg; | |
179 | unsigned int i; | |
180 | ||
181 | if (!word) | |
182 | return; | |
183 | ||
184 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
185 | rt73usb_register_read(rt2x00dev, PHY_CSR4, ®); | |
186 | if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY)) | |
187 | goto rf_write; | |
188 | udelay(REGISTER_BUSY_DELAY); | |
189 | } | |
190 | ||
191 | ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n"); | |
192 | return; | |
193 | ||
194 | rf_write: | |
195 | reg = 0; | |
196 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); | |
197 | ||
198 | if (rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
199 | rt2x00_rf(&rt2x00dev->chip, RF2527)) | |
200 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); | |
201 | else | |
202 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 20); | |
203 | ||
204 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); | |
205 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); | |
206 | ||
207 | rt73usb_register_write(rt2x00dev, PHY_CSR4, reg); | |
208 | rt2x00_rf_write(rt2x00dev, word, value); | |
209 | } | |
210 | ||
211 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
212 | #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) ) | |
213 | ||
214 | static void rt73usb_read_csr(const struct rt2x00_dev *rt2x00dev, | |
215 | const unsigned int word, u32 *data) | |
216 | { | |
217 | rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data); | |
218 | } | |
219 | ||
220 | static void rt73usb_write_csr(const struct rt2x00_dev *rt2x00dev, | |
221 | const unsigned int word, u32 data) | |
222 | { | |
223 | rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data); | |
224 | } | |
225 | ||
226 | static const struct rt2x00debug rt73usb_rt2x00debug = { | |
227 | .owner = THIS_MODULE, | |
228 | .csr = { | |
229 | .read = rt73usb_read_csr, | |
230 | .write = rt73usb_write_csr, | |
231 | .word_size = sizeof(u32), | |
232 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
233 | }, | |
234 | .eeprom = { | |
235 | .read = rt2x00_eeprom_read, | |
236 | .write = rt2x00_eeprom_write, | |
237 | .word_size = sizeof(u16), | |
238 | .word_count = EEPROM_SIZE / sizeof(u16), | |
239 | }, | |
240 | .bbp = { | |
241 | .read = rt73usb_bbp_read, | |
242 | .write = rt73usb_bbp_write, | |
243 | .word_size = sizeof(u8), | |
244 | .word_count = BBP_SIZE / sizeof(u8), | |
245 | }, | |
246 | .rf = { | |
247 | .read = rt2x00_rf_read, | |
248 | .write = rt73usb_rf_write, | |
249 | .word_size = sizeof(u32), | |
250 | .word_count = RF_SIZE / sizeof(u32), | |
251 | }, | |
252 | }; | |
253 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
254 | ||
255 | /* | |
256 | * Configuration handlers. | |
257 | */ | |
258 | static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr) | |
259 | { | |
260 | __le32 reg[2]; | |
261 | u32 tmp; | |
262 | ||
263 | memset(®, 0, sizeof(reg)); | |
264 | memcpy(®, addr, ETH_ALEN); | |
265 | ||
266 | tmp = le32_to_cpu(reg[1]); | |
267 | rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); | |
268 | reg[1] = cpu_to_le32(tmp); | |
269 | ||
270 | /* | |
271 | * The MAC address is passed to us as an array of bytes, | |
272 | * that array is little endian, so no need for byte ordering. | |
273 | */ | |
274 | rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, ®, sizeof(reg)); | |
275 | } | |
276 | ||
277 | static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid) | |
278 | { | |
279 | __le32 reg[2]; | |
280 | u32 tmp; | |
281 | ||
282 | memset(®, 0, sizeof(reg)); | |
283 | memcpy(®, bssid, ETH_ALEN); | |
284 | ||
285 | tmp = le32_to_cpu(reg[1]); | |
286 | rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3); | |
287 | reg[1] = cpu_to_le32(tmp); | |
288 | ||
289 | /* | |
290 | * The BSSID is passed to us as an array of bytes, | |
291 | * that array is little endian, so no need for byte ordering. | |
292 | */ | |
293 | rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, ®, sizeof(reg)); | |
294 | } | |
295 | ||
95ea3627 ID |
296 | static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type) |
297 | { | |
4150c572 | 298 | struct interface *intf = &rt2x00dev->interface; |
95ea3627 ID |
299 | u32 reg; |
300 | ||
301 | /* | |
302 | * Clear current synchronisation setup. | |
303 | * For the Beacon base registers we only need to clear | |
304 | * the first byte since that byte contains the VALID and OWNER | |
305 | * bits which (when set to 0) will invalidate the entire beacon. | |
306 | */ | |
307 | rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0); | |
308 | rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); | |
309 | rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); | |
310 | rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); | |
311 | rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); | |
312 | ||
95ea3627 ID |
313 | /* |
314 | * Enable synchronisation. | |
315 | */ | |
316 | rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
4150c572 JB |
317 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
318 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); | |
95ea3627 | 319 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
4150c572 JB |
320 | if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) || |
321 | is_interface_type(intf, IEEE80211_IF_TYPE_AP)) | |
95ea3627 | 322 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 2); |
4150c572 | 323 | else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA)) |
95ea3627 | 324 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 1); |
4150c572 | 325 | else |
95ea3627 | 326 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); |
95ea3627 ID |
327 | rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
328 | } | |
329 | ||
330 | static void rt73usb_config_rate(struct rt2x00_dev *rt2x00dev, const int rate) | |
331 | { | |
332 | struct ieee80211_conf *conf = &rt2x00dev->hw->conf; | |
333 | u32 reg; | |
334 | u32 value; | |
335 | u32 preamble; | |
336 | ||
337 | if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE)) | |
338 | preamble = SHORT_PREAMBLE; | |
339 | else | |
340 | preamble = PREAMBLE; | |
341 | ||
342 | reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK; | |
343 | ||
344 | rt73usb_register_write(rt2x00dev, TXRX_CSR5, reg); | |
345 | ||
346 | rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
347 | value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ? | |
348 | SHORT_DIFS : DIFS) + | |
349 | PLCP + preamble + get_duration(ACK_SIZE, 10); | |
350 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, value); | |
351 | rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
352 | ||
353 | rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®); | |
354 | if (preamble == SHORT_PREAMBLE) | |
355 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, 1); | |
356 | else | |
357 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, 0); | |
358 | rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); | |
359 | } | |
360 | ||
361 | static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev, | |
362 | const int phymode) | |
363 | { | |
364 | struct ieee80211_hw_mode *mode; | |
365 | struct ieee80211_rate *rate; | |
366 | ||
367 | if (phymode == MODE_IEEE80211A) | |
368 | rt2x00dev->curr_hwmode = HWMODE_A; | |
369 | else if (phymode == MODE_IEEE80211B) | |
370 | rt2x00dev->curr_hwmode = HWMODE_B; | |
371 | else | |
372 | rt2x00dev->curr_hwmode = HWMODE_G; | |
373 | ||
374 | mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode]; | |
375 | rate = &mode->rates[mode->num_rates - 1]; | |
376 | ||
377 | rt73usb_config_rate(rt2x00dev, rate->val2); | |
378 | } | |
379 | ||
380 | static void rt73usb_config_lock_channel(struct rt2x00_dev *rt2x00dev, | |
381 | struct rf_channel *rf, | |
382 | const int txpower) | |
383 | { | |
384 | u8 r3; | |
385 | u8 r94; | |
386 | u8 smart; | |
387 | ||
388 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
389 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
390 | ||
391 | smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
392 | rt2x00_rf(&rt2x00dev->chip, RF2527)); | |
393 | ||
394 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
395 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); | |
396 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
397 | ||
398 | r94 = 6; | |
399 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) | |
400 | r94 += txpower - MAX_TXPOWER; | |
401 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) | |
402 | r94 += txpower; | |
403 | rt73usb_bbp_write(rt2x00dev, 94, r94); | |
404 | ||
405 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
406 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
407 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
408 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
409 | ||
410 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
411 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
412 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
413 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
414 | ||
415 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
416 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
417 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
418 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
419 | ||
420 | udelay(10); | |
421 | } | |
422 | ||
423 | static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev, | |
424 | const int index, const int channel, | |
425 | const int txpower) | |
426 | { | |
427 | struct rf_channel rf; | |
428 | ||
429 | /* | |
430 | * Fill rf_reg structure. | |
431 | */ | |
432 | memcpy(&rf, &rt2x00dev->spec.channels[index], sizeof(rf)); | |
433 | ||
434 | rt73usb_config_lock_channel(rt2x00dev, &rf, txpower); | |
435 | } | |
436 | ||
437 | static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, | |
438 | const int txpower) | |
439 | { | |
440 | struct rf_channel rf; | |
441 | ||
442 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); | |
443 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); | |
444 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); | |
445 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); | |
446 | ||
447 | rt73usb_config_lock_channel(rt2x00dev, &rf, txpower); | |
448 | } | |
449 | ||
450 | static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, | |
451 | const int antenna_tx, | |
452 | const int antenna_rx) | |
453 | { | |
454 | u8 r3; | |
455 | u8 r4; | |
456 | u8 r77; | |
457 | ||
458 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
459 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
460 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
461 | ||
462 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
463 | ||
464 | switch (antenna_rx) { | |
465 | case ANTENNA_SW_DIVERSITY: | |
466 | case ANTENNA_HW_DIVERSITY: | |
467 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2); | |
468 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, | |
469 | !!(rt2x00dev->curr_hwmode != HWMODE_A)); | |
470 | break; | |
471 | case ANTENNA_A: | |
472 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1); | |
473 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); | |
474 | ||
475 | if (rt2x00dev->curr_hwmode == HWMODE_A) | |
476 | rt2x00_set_field8(&r77, BBP_R77_PAIR, 0); | |
477 | else | |
478 | rt2x00_set_field8(&r77, BBP_R77_PAIR, 3); | |
479 | break; | |
480 | case ANTENNA_B: | |
481 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1); | |
482 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); | |
483 | ||
484 | if (rt2x00dev->curr_hwmode == HWMODE_A) | |
485 | rt2x00_set_field8(&r77, BBP_R77_PAIR, 3); | |
486 | else | |
487 | rt2x00_set_field8(&r77, BBP_R77_PAIR, 0); | |
488 | break; | |
489 | } | |
490 | ||
491 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
492 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
493 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
494 | } | |
495 | ||
496 | static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev, | |
497 | const int antenna_tx, | |
498 | const int antenna_rx) | |
499 | { | |
500 | u8 r3; | |
501 | u8 r4; | |
502 | u8 r77; | |
503 | ||
504 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
505 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
506 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
507 | ||
508 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
509 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, | |
510 | !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); | |
511 | ||
512 | switch (antenna_rx) { | |
513 | case ANTENNA_SW_DIVERSITY: | |
514 | case ANTENNA_HW_DIVERSITY: | |
515 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2); | |
516 | break; | |
517 | case ANTENNA_A: | |
518 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1); | |
519 | rt2x00_set_field8(&r77, BBP_R77_PAIR, 3); | |
520 | break; | |
521 | case ANTENNA_B: | |
522 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1); | |
523 | rt2x00_set_field8(&r77, BBP_R77_PAIR, 0); | |
524 | break; | |
525 | } | |
526 | ||
527 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
528 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
529 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
530 | } | |
531 | ||
532 | struct antenna_sel { | |
533 | u8 word; | |
534 | /* | |
535 | * value[0] -> non-LNA | |
536 | * value[1] -> LNA | |
537 | */ | |
538 | u8 value[2]; | |
539 | }; | |
540 | ||
541 | static const struct antenna_sel antenna_sel_a[] = { | |
542 | { 96, { 0x58, 0x78 } }, | |
543 | { 104, { 0x38, 0x48 } }, | |
544 | { 75, { 0xfe, 0x80 } }, | |
545 | { 86, { 0xfe, 0x80 } }, | |
546 | { 88, { 0xfe, 0x80 } }, | |
547 | { 35, { 0x60, 0x60 } }, | |
548 | { 97, { 0x58, 0x58 } }, | |
549 | { 98, { 0x58, 0x58 } }, | |
550 | }; | |
551 | ||
552 | static const struct antenna_sel antenna_sel_bg[] = { | |
553 | { 96, { 0x48, 0x68 } }, | |
554 | { 104, { 0x2c, 0x3c } }, | |
555 | { 75, { 0xfe, 0x80 } }, | |
556 | { 86, { 0xfe, 0x80 } }, | |
557 | { 88, { 0xfe, 0x80 } }, | |
558 | { 35, { 0x50, 0x50 } }, | |
559 | { 97, { 0x48, 0x48 } }, | |
560 | { 98, { 0x48, 0x48 } }, | |
561 | }; | |
562 | ||
563 | static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev, | |
564 | const int antenna_tx, const int antenna_rx) | |
565 | { | |
566 | const struct antenna_sel *sel; | |
567 | unsigned int lna; | |
568 | unsigned int i; | |
569 | u32 reg; | |
570 | ||
571 | rt73usb_register_read(rt2x00dev, PHY_CSR0, ®); | |
572 | ||
573 | if (rt2x00dev->curr_hwmode == HWMODE_A) { | |
574 | sel = antenna_sel_a; | |
575 | lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
576 | ||
577 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 0); | |
578 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 1); | |
579 | } else { | |
580 | sel = antenna_sel_bg; | |
581 | lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
582 | ||
583 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 1); | |
584 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 0); | |
585 | } | |
586 | ||
587 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) | |
588 | rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); | |
589 | ||
590 | rt73usb_register_write(rt2x00dev, PHY_CSR0, reg); | |
591 | ||
592 | if (rt2x00_rf(&rt2x00dev->chip, RF5226) || | |
593 | rt2x00_rf(&rt2x00dev->chip, RF5225)) | |
594 | rt73usb_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx); | |
595 | else if (rt2x00_rf(&rt2x00dev->chip, RF2528) || | |
596 | rt2x00_rf(&rt2x00dev->chip, RF2527)) | |
597 | rt73usb_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx); | |
598 | } | |
599 | ||
600 | static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev, | |
601 | const int short_slot_time, | |
602 | const int beacon_int) | |
603 | { | |
604 | u32 reg; | |
605 | ||
606 | rt73usb_register_read(rt2x00dev, MAC_CSR9, ®); | |
607 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, | |
608 | short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME); | |
609 | rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); | |
610 | ||
611 | rt73usb_register_read(rt2x00dev, MAC_CSR8, ®); | |
612 | rt2x00_set_field32(®, MAC_CSR8_SIFS, SIFS); | |
613 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); | |
614 | rt2x00_set_field32(®, MAC_CSR8_EIFS, EIFS); | |
615 | rt73usb_register_write(rt2x00dev, MAC_CSR8, reg); | |
616 | ||
617 | rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
618 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); | |
619 | rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
620 | ||
621 | rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®); | |
622 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); | |
623 | rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); | |
624 | ||
625 | rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
626 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16); | |
627 | rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
628 | } | |
629 | ||
630 | static void rt73usb_config(struct rt2x00_dev *rt2x00dev, | |
631 | const unsigned int flags, | |
632 | struct ieee80211_conf *conf) | |
633 | { | |
634 | int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME; | |
635 | ||
636 | if (flags & CONFIG_UPDATE_PHYMODE) | |
637 | rt73usb_config_phymode(rt2x00dev, conf->phymode); | |
638 | if (flags & CONFIG_UPDATE_CHANNEL) | |
639 | rt73usb_config_channel(rt2x00dev, conf->channel_val, | |
640 | conf->channel, conf->power_level); | |
641 | if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL)) | |
642 | rt73usb_config_txpower(rt2x00dev, conf->power_level); | |
643 | if (flags & CONFIG_UPDATE_ANTENNA) | |
644 | rt73usb_config_antenna(rt2x00dev, conf->antenna_sel_tx, | |
645 | conf->antenna_sel_rx); | |
646 | if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT)) | |
647 | rt73usb_config_duration(rt2x00dev, short_slot_time, | |
648 | conf->beacon_int); | |
649 | } | |
650 | ||
651 | /* | |
652 | * LED functions. | |
653 | */ | |
654 | static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev) | |
655 | { | |
656 | u32 reg; | |
657 | ||
658 | rt73usb_register_read(rt2x00dev, MAC_CSR14, ®); | |
659 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70); | |
660 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30); | |
661 | rt73usb_register_write(rt2x00dev, MAC_CSR14, reg); | |
662 | ||
663 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1); | |
664 | if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) | |
665 | rt2x00_set_field16(&rt2x00dev->led_reg, | |
666 | MCU_LEDCS_LINK_A_STATUS, 1); | |
667 | else | |
668 | rt2x00_set_field16(&rt2x00dev->led_reg, | |
669 | MCU_LEDCS_LINK_BG_STATUS, 1); | |
670 | ||
671 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000, | |
672 | rt2x00dev->led_reg, REGISTER_TIMEOUT); | |
673 | } | |
674 | ||
675 | static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev) | |
676 | { | |
677 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0); | |
678 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0); | |
679 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0); | |
680 | ||
681 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000, | |
682 | rt2x00dev->led_reg, REGISTER_TIMEOUT); | |
683 | } | |
684 | ||
685 | static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi) | |
686 | { | |
687 | u32 led; | |
688 | ||
689 | if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH) | |
690 | return; | |
691 | ||
692 | /* | |
693 | * Led handling requires a positive value for the rssi, | |
694 | * to do that correctly we need to add the correction. | |
695 | */ | |
696 | rssi += rt2x00dev->rssi_offset; | |
697 | ||
698 | if (rssi <= 30) | |
699 | led = 0; | |
700 | else if (rssi <= 39) | |
701 | led = 1; | |
702 | else if (rssi <= 49) | |
703 | led = 2; | |
704 | else if (rssi <= 53) | |
705 | led = 3; | |
706 | else if (rssi <= 63) | |
707 | led = 4; | |
708 | else | |
709 | led = 5; | |
710 | ||
711 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led, | |
712 | rt2x00dev->led_reg, REGISTER_TIMEOUT); | |
713 | } | |
714 | ||
715 | /* | |
716 | * Link tuning | |
717 | */ | |
718 | static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev) | |
719 | { | |
720 | u32 reg; | |
721 | ||
722 | /* | |
723 | * Update FCS error count from register. | |
724 | */ | |
725 | rt73usb_register_read(rt2x00dev, STA_CSR0, ®); | |
726 | rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); | |
727 | ||
728 | /* | |
729 | * Update False CCA count from register. | |
730 | */ | |
731 | rt73usb_register_read(rt2x00dev, STA_CSR1, ®); | |
732 | reg = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); | |
733 | rt2x00dev->link.false_cca = | |
734 | rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); | |
735 | } | |
736 | ||
737 | static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev) | |
738 | { | |
739 | rt73usb_bbp_write(rt2x00dev, 17, 0x20); | |
740 | rt2x00dev->link.vgc_level = 0x20; | |
741 | } | |
742 | ||
743 | static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev) | |
744 | { | |
745 | int rssi = rt2x00_get_link_rssi(&rt2x00dev->link); | |
746 | u8 r17; | |
747 | u8 up_bound; | |
748 | u8 low_bound; | |
749 | ||
750 | /* | |
751 | * Update Led strength | |
752 | */ | |
753 | rt73usb_activity_led(rt2x00dev, rssi); | |
754 | ||
755 | rt73usb_bbp_read(rt2x00dev, 17, &r17); | |
756 | ||
757 | /* | |
758 | * Determine r17 bounds. | |
759 | */ | |
760 | if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) { | |
761 | low_bound = 0x28; | |
762 | up_bound = 0x48; | |
763 | ||
764 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { | |
765 | low_bound += 0x10; | |
766 | up_bound += 0x10; | |
767 | } | |
768 | } else { | |
769 | if (rssi > -82) { | |
770 | low_bound = 0x1c; | |
771 | up_bound = 0x40; | |
772 | } else if (rssi > -84) { | |
773 | low_bound = 0x1c; | |
774 | up_bound = 0x20; | |
775 | } else { | |
776 | low_bound = 0x1c; | |
777 | up_bound = 0x1c; | |
778 | } | |
779 | ||
780 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { | |
781 | low_bound += 0x14; | |
782 | up_bound += 0x10; | |
783 | } | |
784 | } | |
785 | ||
786 | /* | |
787 | * Special big-R17 for very short distance | |
788 | */ | |
789 | if (rssi > -35) { | |
790 | if (r17 != 0x60) | |
791 | rt73usb_bbp_write(rt2x00dev, 17, 0x60); | |
792 | return; | |
793 | } | |
794 | ||
795 | /* | |
796 | * Special big-R17 for short distance | |
797 | */ | |
798 | if (rssi >= -58) { | |
799 | if (r17 != up_bound) | |
800 | rt73usb_bbp_write(rt2x00dev, 17, up_bound); | |
801 | return; | |
802 | } | |
803 | ||
804 | /* | |
805 | * Special big-R17 for middle-short distance | |
806 | */ | |
807 | if (rssi >= -66) { | |
808 | low_bound += 0x10; | |
809 | if (r17 != low_bound) | |
810 | rt73usb_bbp_write(rt2x00dev, 17, low_bound); | |
811 | return; | |
812 | } | |
813 | ||
814 | /* | |
815 | * Special mid-R17 for middle distance | |
816 | */ | |
817 | if (rssi >= -74) { | |
818 | if (r17 != (low_bound + 0x10)) | |
819 | rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08); | |
820 | return; | |
821 | } | |
822 | ||
823 | /* | |
824 | * Special case: Change up_bound based on the rssi. | |
825 | * Lower up_bound when rssi is weaker then -74 dBm. | |
826 | */ | |
827 | up_bound -= 2 * (-74 - rssi); | |
828 | if (low_bound > up_bound) | |
829 | up_bound = low_bound; | |
830 | ||
831 | if (r17 > up_bound) { | |
832 | rt73usb_bbp_write(rt2x00dev, 17, up_bound); | |
833 | return; | |
834 | } | |
835 | ||
836 | /* | |
837 | * r17 does not yet exceed upper limit, continue and base | |
838 | * the r17 tuning on the false CCA count. | |
839 | */ | |
840 | if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) { | |
841 | r17 += 4; | |
842 | if (r17 > up_bound) | |
843 | r17 = up_bound; | |
844 | rt73usb_bbp_write(rt2x00dev, 17, r17); | |
845 | } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) { | |
846 | r17 -= 4; | |
847 | if (r17 < low_bound) | |
848 | r17 = low_bound; | |
849 | rt73usb_bbp_write(rt2x00dev, 17, r17); | |
850 | } | |
851 | } | |
852 | ||
853 | /* | |
854 | * Firmware name function. | |
855 | */ | |
856 | static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) | |
857 | { | |
858 | return FIRMWARE_RT2571; | |
859 | } | |
860 | ||
861 | /* | |
862 | * Initialization functions. | |
863 | */ | |
864 | static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data, | |
865 | const size_t len) | |
866 | { | |
867 | unsigned int i; | |
868 | int status; | |
869 | u32 reg; | |
870 | char *ptr = data; | |
871 | char *cache; | |
872 | int buflen; | |
873 | int timeout; | |
874 | ||
875 | /* | |
876 | * Wait for stable hardware. | |
877 | */ | |
878 | for (i = 0; i < 100; i++) { | |
879 | rt73usb_register_read(rt2x00dev, MAC_CSR0, ®); | |
880 | if (reg) | |
881 | break; | |
882 | msleep(1); | |
883 | } | |
884 | ||
885 | if (!reg) { | |
886 | ERROR(rt2x00dev, "Unstable hardware.\n"); | |
887 | return -EBUSY; | |
888 | } | |
889 | ||
890 | /* | |
891 | * Write firmware to device. | |
892 | * We setup a seperate cache for this action, | |
893 | * since we are going to write larger chunks of data | |
894 | * then normally used cache size. | |
895 | */ | |
896 | cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL); | |
897 | if (!cache) { | |
898 | ERROR(rt2x00dev, "Failed to allocate firmware cache.\n"); | |
899 | return -ENOMEM; | |
900 | } | |
901 | ||
902 | for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) { | |
903 | buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE); | |
904 | timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32)); | |
905 | ||
906 | memcpy(cache, ptr, buflen); | |
907 | ||
908 | rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE, | |
909 | USB_VENDOR_REQUEST_OUT, | |
910 | FIRMWARE_IMAGE_BASE + i, 0x0000, | |
911 | cache, buflen, timeout); | |
912 | ||
913 | ptr += buflen; | |
914 | } | |
915 | ||
916 | kfree(cache); | |
917 | ||
918 | /* | |
919 | * Send firmware request to device to load firmware, | |
920 | * we need to specify a long timeout time. | |
921 | */ | |
922 | status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, | |
923 | 0x0000, USB_MODE_FIRMWARE, | |
924 | REGISTER_TIMEOUT_FIRMWARE); | |
925 | if (status < 0) { | |
926 | ERROR(rt2x00dev, "Failed to write Firmware to device.\n"); | |
927 | return status; | |
928 | } | |
929 | ||
930 | rt73usb_disable_led(rt2x00dev); | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
935 | static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev) | |
936 | { | |
937 | u32 reg; | |
938 | ||
939 | rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
940 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); | |
941 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
942 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); | |
943 | rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
944 | ||
945 | rt73usb_register_read(rt2x00dev, TXRX_CSR1, ®); | |
946 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ | |
947 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); | |
948 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ | |
949 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); | |
950 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ | |
951 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); | |
952 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ | |
953 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); | |
954 | rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg); | |
955 | ||
956 | /* | |
957 | * CCK TXD BBP registers | |
958 | */ | |
959 | rt73usb_register_read(rt2x00dev, TXRX_CSR2, ®); | |
960 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); | |
961 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); | |
962 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); | |
963 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); | |
964 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); | |
965 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); | |
966 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); | |
967 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); | |
968 | rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg); | |
969 | ||
970 | /* | |
971 | * OFDM TXD BBP registers | |
972 | */ | |
973 | rt73usb_register_read(rt2x00dev, TXRX_CSR3, ®); | |
974 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); | |
975 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); | |
976 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); | |
977 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); | |
978 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); | |
979 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); | |
980 | rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg); | |
981 | ||
982 | rt73usb_register_read(rt2x00dev, TXRX_CSR7, ®); | |
983 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); | |
984 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); | |
985 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); | |
986 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); | |
987 | rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg); | |
988 | ||
989 | rt73usb_register_read(rt2x00dev, TXRX_CSR8, ®); | |
990 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); | |
991 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); | |
992 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); | |
993 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); | |
994 | rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg); | |
995 | ||
996 | rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); | |
997 | ||
998 | rt73usb_register_read(rt2x00dev, MAC_CSR6, ®); | |
999 | rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); | |
1000 | rt73usb_register_write(rt2x00dev, MAC_CSR6, reg); | |
1001 | ||
1002 | rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); | |
1003 | ||
1004 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
1005 | return -EBUSY; | |
1006 | ||
1007 | rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); | |
1008 | ||
1009 | /* | |
1010 | * Invalidate all Shared Keys (SEC_CSR0), | |
1011 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) | |
1012 | */ | |
1013 | rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); | |
1014 | rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); | |
1015 | rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); | |
1016 | ||
1017 | reg = 0x000023b0; | |
1018 | if (rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
1019 | rt2x00_rf(&rt2x00dev->chip, RF2527)) | |
1020 | rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1); | |
1021 | rt73usb_register_write(rt2x00dev, PHY_CSR1, reg); | |
1022 | ||
1023 | rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); | |
1024 | rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); | |
1025 | rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); | |
1026 | ||
1027 | rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, ®); | |
1028 | rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0); | |
1029 | rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0); | |
1030 | rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg); | |
1031 | ||
1032 | rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, ®); | |
1033 | rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192); | |
1034 | rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48); | |
1035 | rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg); | |
1036 | ||
1037 | rt73usb_register_read(rt2x00dev, MAC_CSR9, ®); | |
1038 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); | |
1039 | rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); | |
1040 | ||
1041 | /* | |
1042 | * We must clear the error counters. | |
1043 | * These registers are cleared on read, | |
1044 | * so we may pass a useless variable to store the value. | |
1045 | */ | |
1046 | rt73usb_register_read(rt2x00dev, STA_CSR0, ®); | |
1047 | rt73usb_register_read(rt2x00dev, STA_CSR1, ®); | |
1048 | rt73usb_register_read(rt2x00dev, STA_CSR2, ®); | |
1049 | ||
1050 | /* | |
1051 | * Reset MAC and BBP registers. | |
1052 | */ | |
1053 | rt73usb_register_read(rt2x00dev, MAC_CSR1, ®); | |
1054 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); | |
1055 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
1056 | rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); | |
1057 | ||
1058 | rt73usb_register_read(rt2x00dev, MAC_CSR1, ®); | |
1059 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); | |
1060 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
1061 | rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); | |
1062 | ||
1063 | rt73usb_register_read(rt2x00dev, MAC_CSR1, ®); | |
1064 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); | |
1065 | rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1071 | { | |
1072 | unsigned int i; | |
1073 | u16 eeprom; | |
1074 | u8 reg_id; | |
1075 | u8 value; | |
1076 | ||
1077 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1078 | rt73usb_bbp_read(rt2x00dev, 0, &value); | |
1079 | if ((value != 0xff) && (value != 0x00)) | |
1080 | goto continue_csr_init; | |
1081 | NOTICE(rt2x00dev, "Waiting for BBP register.\n"); | |
1082 | udelay(REGISTER_BUSY_DELAY); | |
1083 | } | |
1084 | ||
1085 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
1086 | return -EACCES; | |
1087 | ||
1088 | continue_csr_init: | |
1089 | rt73usb_bbp_write(rt2x00dev, 3, 0x80); | |
1090 | rt73usb_bbp_write(rt2x00dev, 15, 0x30); | |
1091 | rt73usb_bbp_write(rt2x00dev, 21, 0xc8); | |
1092 | rt73usb_bbp_write(rt2x00dev, 22, 0x38); | |
1093 | rt73usb_bbp_write(rt2x00dev, 23, 0x06); | |
1094 | rt73usb_bbp_write(rt2x00dev, 24, 0xfe); | |
1095 | rt73usb_bbp_write(rt2x00dev, 25, 0x0a); | |
1096 | rt73usb_bbp_write(rt2x00dev, 26, 0x0d); | |
1097 | rt73usb_bbp_write(rt2x00dev, 32, 0x0b); | |
1098 | rt73usb_bbp_write(rt2x00dev, 34, 0x12); | |
1099 | rt73usb_bbp_write(rt2x00dev, 37, 0x07); | |
1100 | rt73usb_bbp_write(rt2x00dev, 39, 0xf8); | |
1101 | rt73usb_bbp_write(rt2x00dev, 41, 0x60); | |
1102 | rt73usb_bbp_write(rt2x00dev, 53, 0x10); | |
1103 | rt73usb_bbp_write(rt2x00dev, 54, 0x18); | |
1104 | rt73usb_bbp_write(rt2x00dev, 60, 0x10); | |
1105 | rt73usb_bbp_write(rt2x00dev, 61, 0x04); | |
1106 | rt73usb_bbp_write(rt2x00dev, 62, 0x04); | |
1107 | rt73usb_bbp_write(rt2x00dev, 75, 0xfe); | |
1108 | rt73usb_bbp_write(rt2x00dev, 86, 0xfe); | |
1109 | rt73usb_bbp_write(rt2x00dev, 88, 0xfe); | |
1110 | rt73usb_bbp_write(rt2x00dev, 90, 0x0f); | |
1111 | rt73usb_bbp_write(rt2x00dev, 99, 0x00); | |
1112 | rt73usb_bbp_write(rt2x00dev, 102, 0x16); | |
1113 | rt73usb_bbp_write(rt2x00dev, 107, 0x04); | |
1114 | ||
1115 | DEBUG(rt2x00dev, "Start initialization from EEPROM...\n"); | |
1116 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { | |
1117 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1118 | ||
1119 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1120 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1121 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
1122 | DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n", | |
1123 | reg_id, value); | |
1124 | rt73usb_bbp_write(rt2x00dev, reg_id, value); | |
1125 | } | |
1126 | } | |
1127 | DEBUG(rt2x00dev, "...End initialization from EEPROM.\n"); | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
1132 | /* | |
1133 | * Device state switch handlers. | |
1134 | */ | |
1135 | static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev, | |
1136 | enum dev_state state) | |
1137 | { | |
1138 | u32 reg; | |
1139 | ||
1140 | rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1141 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, | |
1142 | state == STATE_RADIO_RX_OFF); | |
1143 | rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1144 | } | |
1145 | ||
1146 | static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) | |
1147 | { | |
1148 | /* | |
1149 | * Initialize all registers. | |
1150 | */ | |
1151 | if (rt73usb_init_registers(rt2x00dev) || | |
1152 | rt73usb_init_bbp(rt2x00dev)) { | |
1153 | ERROR(rt2x00dev, "Register initialization failed.\n"); | |
1154 | return -EIO; | |
1155 | } | |
1156 | ||
1157 | rt2x00usb_enable_radio(rt2x00dev); | |
1158 | ||
1159 | /* | |
1160 | * Enable LED | |
1161 | */ | |
1162 | rt73usb_enable_led(rt2x00dev); | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1168 | { | |
1169 | /* | |
1170 | * Disable LED | |
1171 | */ | |
1172 | rt73usb_disable_led(rt2x00dev); | |
1173 | ||
1174 | rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); | |
1175 | ||
1176 | /* | |
1177 | * Disable synchronisation. | |
1178 | */ | |
1179 | rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0); | |
1180 | ||
1181 | rt2x00usb_disable_radio(rt2x00dev); | |
1182 | } | |
1183 | ||
1184 | static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) | |
1185 | { | |
1186 | u32 reg; | |
1187 | unsigned int i; | |
1188 | char put_to_sleep; | |
1189 | char current_state; | |
1190 | ||
1191 | put_to_sleep = (state != STATE_AWAKE); | |
1192 | ||
1193 | rt73usb_register_read(rt2x00dev, MAC_CSR12, ®); | |
1194 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); | |
1195 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); | |
1196 | rt73usb_register_write(rt2x00dev, MAC_CSR12, reg); | |
1197 | ||
1198 | /* | |
1199 | * Device is not guaranteed to be in the requested state yet. | |
1200 | * We must wait until the register indicates that the | |
1201 | * device has entered the correct state. | |
1202 | */ | |
1203 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1204 | rt73usb_register_read(rt2x00dev, MAC_CSR12, ®); | |
1205 | current_state = | |
1206 | rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); | |
1207 | if (current_state == !put_to_sleep) | |
1208 | return 0; | |
1209 | msleep(10); | |
1210 | } | |
1211 | ||
1212 | NOTICE(rt2x00dev, "Device failed to enter state %d, " | |
1213 | "current device state %d.\n", !put_to_sleep, current_state); | |
1214 | ||
1215 | return -EBUSY; | |
1216 | } | |
1217 | ||
1218 | static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1219 | enum dev_state state) | |
1220 | { | |
1221 | int retval = 0; | |
1222 | ||
1223 | switch (state) { | |
1224 | case STATE_RADIO_ON: | |
1225 | retval = rt73usb_enable_radio(rt2x00dev); | |
1226 | break; | |
1227 | case STATE_RADIO_OFF: | |
1228 | rt73usb_disable_radio(rt2x00dev); | |
1229 | break; | |
1230 | case STATE_RADIO_RX_ON: | |
1231 | case STATE_RADIO_RX_OFF: | |
1232 | rt73usb_toggle_rx(rt2x00dev, state); | |
1233 | break; | |
1234 | case STATE_DEEP_SLEEP: | |
1235 | case STATE_SLEEP: | |
1236 | case STATE_STANDBY: | |
1237 | case STATE_AWAKE: | |
1238 | retval = rt73usb_set_state(rt2x00dev, state); | |
1239 | break; | |
1240 | default: | |
1241 | retval = -ENOTSUPP; | |
1242 | break; | |
1243 | } | |
1244 | ||
1245 | return retval; | |
1246 | } | |
1247 | ||
1248 | /* | |
1249 | * TX descriptor initialization | |
1250 | */ | |
1251 | static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |
1252 | struct data_desc *txd, | |
4150c572 | 1253 | struct txdata_entry_desc *desc, |
95ea3627 ID |
1254 | struct ieee80211_hdr *ieee80211hdr, |
1255 | unsigned int length, | |
1256 | struct ieee80211_tx_control *control) | |
1257 | { | |
1258 | u32 word; | |
1259 | ||
1260 | /* | |
1261 | * Start writing the descriptor words. | |
1262 | */ | |
1263 | rt2x00_desc_read(txd, 1, &word); | |
1264 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue); | |
1265 | rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs); | |
1266 | rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min); | |
1267 | rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max); | |
1268 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER); | |
1269 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1); | |
1270 | rt2x00_desc_write(txd, 1, word); | |
1271 | ||
1272 | rt2x00_desc_read(txd, 2, &word); | |
1273 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal); | |
1274 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service); | |
1275 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low); | |
1276 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high); | |
1277 | rt2x00_desc_write(txd, 2, word); | |
1278 | ||
1279 | rt2x00_desc_read(txd, 5, &word); | |
1280 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, | |
1281 | TXPOWER_TO_DEV(control->power_level)); | |
1282 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); | |
1283 | rt2x00_desc_write(txd, 5, word); | |
1284 | ||
1285 | rt2x00_desc_read(txd, 0, &word); | |
1286 | rt2x00_set_field32(&word, TXD_W0_BURST, | |
1287 | test_bit(ENTRY_TXD_BURST, &desc->flags)); | |
1288 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1289 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
1290 | test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags)); | |
1291 | rt2x00_set_field32(&word, TXD_W0_ACK, | |
1292 | !(control->flags & IEEE80211_TXCTL_NO_ACK)); | |
1293 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, | |
1294 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags)); | |
1295 | rt2x00_set_field32(&word, TXD_W0_OFDM, | |
1296 | test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags)); | |
1297 | rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs); | |
1298 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, | |
1299 | !!(control->flags & | |
1300 | IEEE80211_TXCTL_LONG_RETRY_LIMIT)); | |
1301 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0); | |
1302 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length); | |
1303 | rt2x00_set_field32(&word, TXD_W0_BURST2, | |
1304 | test_bit(ENTRY_TXD_BURST, &desc->flags)); | |
1305 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); | |
1306 | rt2x00_desc_write(txd, 0, word); | |
1307 | } | |
1308 | ||
1309 | /* | |
1310 | * TX data initialization | |
1311 | */ | |
1312 | static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev, | |
1313 | unsigned int queue) | |
1314 | { | |
1315 | u32 reg; | |
1316 | ||
1317 | if (queue != IEEE80211_TX_QUEUE_BEACON) | |
1318 | return; | |
1319 | ||
1320 | /* | |
1321 | * For Wi-Fi faily generated beacons between participating stations. | |
1322 | * Set TBTT phase adaptive adjustment step to 8us (default 16us) | |
1323 | */ | |
1324 | rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); | |
1325 | ||
1326 | rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1327 | if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) { | |
1328 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); | |
1329 | rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | /* | |
1334 | * RX control handlers | |
1335 | */ | |
1336 | static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) | |
1337 | { | |
1338 | u16 eeprom; | |
1339 | u8 offset; | |
1340 | u8 lna; | |
1341 | ||
1342 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); | |
1343 | switch (lna) { | |
1344 | case 3: | |
1345 | offset = 90; | |
1346 | break; | |
1347 | case 2: | |
1348 | offset = 74; | |
1349 | break; | |
1350 | case 1: | |
1351 | offset = 64; | |
1352 | break; | |
1353 | default: | |
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) { | |
1358 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { | |
1359 | if (lna == 3 || lna == 2) | |
1360 | offset += 10; | |
1361 | } else { | |
1362 | if (lna == 3) | |
1363 | offset += 6; | |
1364 | else if (lna == 2) | |
1365 | offset += 8; | |
1366 | } | |
1367 | ||
1368 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); | |
1369 | offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); | |
1370 | } else { | |
1371 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) | |
1372 | offset += 14; | |
1373 | ||
1374 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); | |
1375 | offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); | |
1376 | } | |
1377 | ||
1378 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; | |
1379 | } | |
1380 | ||
4150c572 JB |
1381 | static void rt73usb_fill_rxdone(struct data_entry *entry, |
1382 | struct rxdata_entry_desc *desc) | |
95ea3627 ID |
1383 | { |
1384 | struct data_desc *rxd = (struct data_desc *)entry->skb->data; | |
1385 | u32 word0; | |
1386 | u32 word1; | |
1387 | ||
1388 | rt2x00_desc_read(rxd, 0, &word0); | |
1389 | rt2x00_desc_read(rxd, 1, &word1); | |
1390 | ||
4150c572 JB |
1391 | desc->flags = 0; |
1392 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) | |
1393 | desc->flags |= RX_FLAG_FAILED_FCS_CRC; | |
95ea3627 ID |
1394 | |
1395 | /* | |
1396 | * Obtain the status about this packet. | |
1397 | */ | |
4150c572 JB |
1398 | desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
1399 | desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1); | |
1400 | desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM); | |
1401 | desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); | |
95ea3627 ID |
1402 | |
1403 | /* | |
1404 | * Pull the skb to clear the descriptor area. | |
1405 | */ | |
1406 | skb_pull(entry->skb, entry->ring->desc_size); | |
1407 | ||
4150c572 | 1408 | return; |
95ea3627 ID |
1409 | } |
1410 | ||
1411 | /* | |
1412 | * Device probe functions. | |
1413 | */ | |
1414 | static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
1415 | { | |
1416 | u16 word; | |
1417 | u8 *mac; | |
1418 | s8 value; | |
1419 | ||
1420 | rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE); | |
1421 | ||
1422 | /* | |
1423 | * Start validation of the data that has been read. | |
1424 | */ | |
1425 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1426 | if (!is_valid_ether_addr(mac)) { | |
0795af57 JP |
1427 | DECLARE_MAC_BUF(macbuf); |
1428 | ||
95ea3627 | 1429 | random_ether_addr(mac); |
0795af57 | 1430 | EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac)); |
95ea3627 ID |
1431 | } |
1432 | ||
1433 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1434 | if (word == 0xffff) { | |
1435 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
1436 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2); | |
1437 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2); | |
1438 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); | |
1439 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); | |
1440 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
1441 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226); | |
1442 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
1443 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); | |
1444 | } | |
1445 | ||
1446 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
1447 | if (word == 0xffff) { | |
1448 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0); | |
1449 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
1450 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); | |
1451 | } | |
1452 | ||
1453 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); | |
1454 | if (word == 0xffff) { | |
1455 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0); | |
1456 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0); | |
1457 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0); | |
1458 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0); | |
1459 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0); | |
1460 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0); | |
1461 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0); | |
1462 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0); | |
1463 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, | |
1464 | LED_MODE_DEFAULT); | |
1465 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); | |
1466 | EEPROM(rt2x00dev, "Led: 0x%04x\n", word); | |
1467 | } | |
1468 | ||
1469 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
1470 | if (word == 0xffff) { | |
1471 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
1472 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); | |
1473 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
1474 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); | |
1475 | } | |
1476 | ||
1477 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); | |
1478 | if (word == 0xffff) { | |
1479 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1480 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1481 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1482 | EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); | |
1483 | } else { | |
1484 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); | |
1485 | if (value < -10 || value > 10) | |
1486 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1487 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); | |
1488 | if (value < -10 || value > 10) | |
1489 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1490 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1491 | } | |
1492 | ||
1493 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); | |
1494 | if (word == 0xffff) { | |
1495 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1496 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1497 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
1498 | EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); | |
1499 | } else { | |
1500 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); | |
1501 | if (value < -10 || value > 10) | |
1502 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1503 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); | |
1504 | if (value < -10 || value > 10) | |
1505 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1506 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
1507 | } | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1513 | { | |
1514 | u32 reg; | |
1515 | u16 value; | |
1516 | u16 eeprom; | |
1517 | ||
1518 | /* | |
1519 | * Read EEPROM word for configuration. | |
1520 | */ | |
1521 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1522 | ||
1523 | /* | |
1524 | * Identify RF chipset. | |
1525 | */ | |
1526 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
1527 | rt73usb_register_read(rt2x00dev, MAC_CSR0, ®); | |
1528 | rt2x00_set_chip(rt2x00dev, RT2571, value, reg); | |
1529 | ||
1530 | if (!rt2x00_rev(&rt2x00dev->chip, 0x25730)) { | |
1531 | ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); | |
1532 | return -ENODEV; | |
1533 | } | |
1534 | ||
1535 | if (!rt2x00_rf(&rt2x00dev->chip, RF5226) && | |
1536 | !rt2x00_rf(&rt2x00dev->chip, RF2528) && | |
1537 | !rt2x00_rf(&rt2x00dev->chip, RF5225) && | |
1538 | !rt2x00_rf(&rt2x00dev->chip, RF2527)) { | |
1539 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); | |
1540 | return -ENODEV; | |
1541 | } | |
1542 | ||
1543 | /* | |
1544 | * Identify default antenna configuration. | |
1545 | */ | |
1546 | rt2x00dev->hw->conf.antenna_sel_tx = | |
1547 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); | |
1548 | rt2x00dev->hw->conf.antenna_sel_rx = | |
1549 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); | |
1550 | ||
1551 | /* | |
1552 | * Read the Frame type. | |
1553 | */ | |
1554 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) | |
1555 | __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); | |
1556 | ||
1557 | /* | |
1558 | * Read frequency offset. | |
1559 | */ | |
1560 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
1561 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
1562 | ||
1563 | /* | |
1564 | * Read external LNA informations. | |
1565 | */ | |
1566 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
1567 | ||
1568 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) { | |
1569 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
1570 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
1571 | } | |
1572 | ||
1573 | /* | |
1574 | * Store led settings, for correct led behaviour. | |
1575 | */ | |
1576 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); | |
1577 | ||
1578 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE, | |
1579 | rt2x00dev->led_mode); | |
1580 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0, | |
1581 | rt2x00_get_field16(eeprom, | |
1582 | EEPROM_LED_POLARITY_GPIO_0)); | |
1583 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1, | |
1584 | rt2x00_get_field16(eeprom, | |
1585 | EEPROM_LED_POLARITY_GPIO_1)); | |
1586 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2, | |
1587 | rt2x00_get_field16(eeprom, | |
1588 | EEPROM_LED_POLARITY_GPIO_2)); | |
1589 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3, | |
1590 | rt2x00_get_field16(eeprom, | |
1591 | EEPROM_LED_POLARITY_GPIO_3)); | |
1592 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4, | |
1593 | rt2x00_get_field16(eeprom, | |
1594 | EEPROM_LED_POLARITY_GPIO_4)); | |
1595 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT, | |
1596 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); | |
1597 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG, | |
1598 | rt2x00_get_field16(eeprom, | |
1599 | EEPROM_LED_POLARITY_RDY_G)); | |
1600 | rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A, | |
1601 | rt2x00_get_field16(eeprom, | |
1602 | EEPROM_LED_POLARITY_RDY_A)); | |
1603 | ||
1604 | return 0; | |
1605 | } | |
1606 | ||
1607 | /* | |
1608 | * RF value list for RF2528 | |
1609 | * Supports: 2.4 GHz | |
1610 | */ | |
1611 | static const struct rf_channel rf_vals_bg_2528[] = { | |
1612 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1613 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1614 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1615 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1616 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1617 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1618 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1619 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1620 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1621 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
1622 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
1623 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
1624 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
1625 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
1626 | }; | |
1627 | ||
1628 | /* | |
1629 | * RF value list for RF5226 | |
1630 | * Supports: 2.4 GHz & 5.2 GHz | |
1631 | */ | |
1632 | static const struct rf_channel rf_vals_5226[] = { | |
1633 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1634 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1635 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1636 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1637 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1638 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1639 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1640 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1641 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1642 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
1643 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
1644 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
1645 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
1646 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
1647 | ||
1648 | /* 802.11 UNI / HyperLan 2 */ | |
1649 | { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 }, | |
1650 | { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 }, | |
1651 | { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b }, | |
1652 | { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 }, | |
1653 | { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b }, | |
1654 | { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 }, | |
1655 | { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 }, | |
1656 | { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b }, | |
1657 | ||
1658 | /* 802.11 HyperLan 2 */ | |
1659 | { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 }, | |
1660 | { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b }, | |
1661 | { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 }, | |
1662 | { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b }, | |
1663 | { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 }, | |
1664 | { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 }, | |
1665 | { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b }, | |
1666 | { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 }, | |
1667 | { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b }, | |
1668 | { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 }, | |
1669 | ||
1670 | /* 802.11 UNII */ | |
1671 | { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 }, | |
1672 | { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f }, | |
1673 | { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 }, | |
1674 | { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 }, | |
1675 | { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f }, | |
1676 | { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 }, | |
1677 | ||
1678 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
1679 | { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b }, | |
1680 | { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 }, | |
1681 | { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b }, | |
1682 | { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 }, | |
1683 | }; | |
1684 | ||
1685 | /* | |
1686 | * RF value list for RF5225 & RF2527 | |
1687 | * Supports: 2.4 GHz & 5.2 GHz | |
1688 | */ | |
1689 | static const struct rf_channel rf_vals_5225_2527[] = { | |
1690 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
1691 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
1692 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
1693 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
1694 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
1695 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
1696 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
1697 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
1698 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
1699 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
1700 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
1701 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
1702 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
1703 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
1704 | ||
1705 | /* 802.11 UNI / HyperLan 2 */ | |
1706 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, | |
1707 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, | |
1708 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, | |
1709 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, | |
1710 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, | |
1711 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, | |
1712 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, | |
1713 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, | |
1714 | ||
1715 | /* 802.11 HyperLan 2 */ | |
1716 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, | |
1717 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, | |
1718 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, | |
1719 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, | |
1720 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, | |
1721 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, | |
1722 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, | |
1723 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, | |
1724 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, | |
1725 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, | |
1726 | ||
1727 | /* 802.11 UNII */ | |
1728 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, | |
1729 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, | |
1730 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, | |
1731 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, | |
1732 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, | |
1733 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, | |
1734 | ||
1735 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
1736 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, | |
1737 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, | |
1738 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, | |
1739 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, | |
1740 | }; | |
1741 | ||
1742 | ||
1743 | static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |
1744 | { | |
1745 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
1746 | u8 *txpower; | |
1747 | unsigned int i; | |
1748 | ||
1749 | /* | |
1750 | * Initialize all hw fields. | |
1751 | */ | |
1752 | rt2x00dev->hw->flags = | |
1753 | IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | | |
4150c572 | 1754 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; |
95ea3627 ID |
1755 | rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE; |
1756 | rt2x00dev->hw->max_signal = MAX_SIGNAL; | |
1757 | rt2x00dev->hw->max_rssi = MAX_RX_SSI; | |
1758 | rt2x00dev->hw->queues = 5; | |
1759 | ||
1760 | SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev); | |
1761 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, | |
1762 | rt2x00_eeprom_addr(rt2x00dev, | |
1763 | EEPROM_MAC_ADDR_0)); | |
1764 | ||
1765 | /* | |
1766 | * Convert tx_power array in eeprom. | |
1767 | */ | |
1768 | txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); | |
1769 | for (i = 0; i < 14; i++) | |
1770 | txpower[i] = TXPOWER_FROM_DEV(txpower[i]); | |
1771 | ||
1772 | /* | |
1773 | * Initialize hw_mode information. | |
1774 | */ | |
1775 | spec->num_modes = 2; | |
1776 | spec->num_rates = 12; | |
1777 | spec->tx_power_a = NULL; | |
1778 | spec->tx_power_bg = txpower; | |
1779 | spec->tx_power_default = DEFAULT_TXPOWER; | |
1780 | ||
1781 | if (rt2x00_rf(&rt2x00dev->chip, RF2528)) { | |
1782 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528); | |
1783 | spec->channels = rf_vals_bg_2528; | |
1784 | } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) { | |
1785 | spec->num_channels = ARRAY_SIZE(rf_vals_5226); | |
1786 | spec->channels = rf_vals_5226; | |
1787 | } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) { | |
1788 | spec->num_channels = 14; | |
1789 | spec->channels = rf_vals_5225_2527; | |
1790 | } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) { | |
1791 | spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527); | |
1792 | spec->channels = rf_vals_5225_2527; | |
1793 | } | |
1794 | ||
1795 | if (rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
1796 | rt2x00_rf(&rt2x00dev->chip, RF5226)) { | |
1797 | spec->num_modes = 3; | |
1798 | ||
1799 | txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); | |
1800 | for (i = 0; i < 14; i++) | |
1801 | txpower[i] = TXPOWER_FROM_DEV(txpower[i]); | |
1802 | ||
1803 | spec->tx_power_a = txpower; | |
1804 | } | |
1805 | } | |
1806 | ||
1807 | static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev) | |
1808 | { | |
1809 | int retval; | |
1810 | ||
1811 | /* | |
1812 | * Allocate eeprom data. | |
1813 | */ | |
1814 | retval = rt73usb_validate_eeprom(rt2x00dev); | |
1815 | if (retval) | |
1816 | return retval; | |
1817 | ||
1818 | retval = rt73usb_init_eeprom(rt2x00dev); | |
1819 | if (retval) | |
1820 | return retval; | |
1821 | ||
1822 | /* | |
1823 | * Initialize hw specifications. | |
1824 | */ | |
1825 | rt73usb_probe_hw_mode(rt2x00dev); | |
1826 | ||
1827 | /* | |
95ea3627 ID |
1828 | * This device requires firmware |
1829 | */ | |
1830 | __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->flags); | |
95ea3627 ID |
1831 | |
1832 | /* | |
1833 | * Set the rssi offset. | |
1834 | */ | |
1835 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
1836 | ||
1837 | return 0; | |
1838 | } | |
1839 | ||
1840 | /* | |
1841 | * IEEE80211 stack callback functions. | |
1842 | */ | |
4150c572 JB |
1843 | static void rt73usb_configure_filter(struct ieee80211_hw *hw, |
1844 | unsigned int changed_flags, | |
1845 | unsigned int *total_flags, | |
1846 | int mc_count, | |
1847 | struct dev_addr_list *mc_list) | |
1848 | { | |
1849 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1850 | struct interface *intf = &rt2x00dev->interface; | |
1851 | u32 reg; | |
1852 | ||
1853 | /* | |
1854 | * Mask off any flags we are going to ignore from | |
1855 | * the total_flags field. | |
1856 | */ | |
1857 | *total_flags &= | |
1858 | FIF_ALLMULTI | | |
1859 | FIF_FCSFAIL | | |
1860 | FIF_PLCPFAIL | | |
1861 | FIF_CONTROL | | |
1862 | FIF_OTHER_BSS | | |
1863 | FIF_PROMISC_IN_BSS; | |
1864 | ||
1865 | /* | |
1866 | * Apply some rules to the filters: | |
1867 | * - Some filters imply different filters to be set. | |
1868 | * - Some things we can't filter out at all. | |
1869 | * - Some filters are set based on interface type. | |
1870 | */ | |
1871 | if (mc_count) | |
1872 | *total_flags |= FIF_ALLMULTI; | |
1873 | if (changed_flags & FIF_OTHER_BSS || | |
1874 | changed_flags & FIF_PROMISC_IN_BSS) | |
1875 | *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS; | |
1876 | if (is_interface_type(intf, IEEE80211_IF_TYPE_AP)) | |
1877 | *total_flags |= FIF_PROMISC_IN_BSS; | |
1878 | ||
1879 | /* | |
1880 | * Check if there is any work left for us. | |
1881 | */ | |
1882 | if (intf->filter == *total_flags) | |
1883 | return; | |
1884 | intf->filter = *total_flags; | |
1885 | ||
1886 | /* | |
1887 | * When in atomic context, reschedule and let rt2x00lib | |
1888 | * call this function again. | |
1889 | */ | |
1890 | if (in_atomic()) { | |
1891 | queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work); | |
1892 | return; | |
1893 | } | |
1894 | ||
1895 | /* | |
1896 | * Start configuration steps. | |
1897 | * Note that the version error will always be dropped | |
1898 | * and broadcast frames will always be accepted since | |
1899 | * there is no filter for it at this time. | |
1900 | */ | |
1901 | rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1902 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, | |
1903 | !(*total_flags & FIF_FCSFAIL)); | |
1904 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, | |
1905 | !(*total_flags & FIF_PLCPFAIL)); | |
1906 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, | |
1907 | !(*total_flags & FIF_CONTROL)); | |
1908 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, | |
1909 | !(*total_flags & FIF_PROMISC_IN_BSS)); | |
1910 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, | |
1911 | !(*total_flags & FIF_PROMISC_IN_BSS)); | |
1912 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); | |
1913 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, | |
1914 | !(*total_flags & FIF_ALLMULTI)); | |
1915 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); | |
1916 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1); | |
1917 | rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1918 | } | |
1919 | ||
95ea3627 ID |
1920 | static int rt73usb_set_retry_limit(struct ieee80211_hw *hw, |
1921 | u32 short_retry, u32 long_retry) | |
1922 | { | |
1923 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1924 | u32 reg; | |
1925 | ||
1926 | rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®); | |
1927 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry); | |
1928 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry); | |
1929 | rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); | |
1930 | ||
1931 | return 0; | |
1932 | } | |
1933 | ||
1934 | #if 0 | |
1935 | /* | |
1936 | * Mac80211 demands get_tsf must be atomic. | |
1937 | * This is not possible for rt73usb since all register access | |
1938 | * functions require sleeping. Untill mac80211 no longer needs | |
1939 | * get_tsf to be atomic, this function should be disabled. | |
1940 | */ | |
1941 | static u64 rt73usb_get_tsf(struct ieee80211_hw *hw) | |
1942 | { | |
1943 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1944 | u64 tsf; | |
1945 | u32 reg; | |
1946 | ||
1947 | rt73usb_register_read(rt2x00dev, TXRX_CSR13, ®); | |
1948 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; | |
1949 | rt73usb_register_read(rt2x00dev, TXRX_CSR12, ®); | |
1950 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); | |
1951 | ||
1952 | return tsf; | |
1953 | } | |
1954 | #endif | |
1955 | ||
1956 | static void rt73usb_reset_tsf(struct ieee80211_hw *hw) | |
1957 | { | |
1958 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1959 | ||
1960 | rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0); | |
1961 | rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0); | |
1962 | } | |
1963 | ||
1964 | int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, | |
1965 | struct ieee80211_tx_control *control) | |
1966 | { | |
1967 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1968 | int timeout; | |
1969 | ||
1970 | /* | |
1971 | * Just in case the ieee80211 doesn't set this, | |
1972 | * but we need this queue set for the descriptor | |
1973 | * initialization. | |
1974 | */ | |
1975 | control->queue = IEEE80211_TX_QUEUE_BEACON; | |
1976 | ||
1977 | /* | |
1978 | * First we create the beacon. | |
1979 | */ | |
1980 | skb_push(skb, TXD_DESC_SIZE); | |
1981 | rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data, | |
1982 | (struct ieee80211_hdr *)(skb->data + | |
1983 | TXD_DESC_SIZE), | |
1984 | skb->len - TXD_DESC_SIZE, control); | |
1985 | ||
1986 | /* | |
1987 | * Write entire beacon with descriptor to register, | |
1988 | * and kick the beacon generator. | |
1989 | */ | |
1990 | timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32)); | |
1991 | rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE, | |
1992 | USB_VENDOR_REQUEST_OUT, | |
1993 | HW_BEACON_BASE0, 0x0000, | |
1994 | skb->data, skb->len, timeout); | |
1995 | rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON); | |
1996 | ||
1997 | return 0; | |
1998 | } | |
1999 | ||
2000 | static const struct ieee80211_ops rt73usb_mac80211_ops = { | |
2001 | .tx = rt2x00mac_tx, | |
4150c572 JB |
2002 | .start = rt2x00mac_start, |
2003 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
2004 | .add_interface = rt2x00mac_add_interface, |
2005 | .remove_interface = rt2x00mac_remove_interface, | |
2006 | .config = rt2x00mac_config, | |
2007 | .config_interface = rt2x00mac_config_interface, | |
4150c572 | 2008 | .configure_filter = rt73usb_configure_filter, |
95ea3627 ID |
2009 | .get_stats = rt2x00mac_get_stats, |
2010 | .set_retry_limit = rt73usb_set_retry_limit, | |
2011 | .conf_tx = rt2x00mac_conf_tx, | |
2012 | .get_tx_stats = rt2x00mac_get_tx_stats, | |
2013 | #if 0 | |
2014 | /* | |
2015 | * See comment at the rt73usb_get_tsf function. | |
2016 | */ | |
2017 | .get_tsf = rt73usb_get_tsf, | |
2018 | #endif | |
2019 | .reset_tsf = rt73usb_reset_tsf, | |
2020 | .beacon_update = rt73usb_beacon_update, | |
2021 | }; | |
2022 | ||
2023 | static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { | |
2024 | .probe_hw = rt73usb_probe_hw, | |
2025 | .get_firmware_name = rt73usb_get_firmware_name, | |
2026 | .load_firmware = rt73usb_load_firmware, | |
2027 | .initialize = rt2x00usb_initialize, | |
2028 | .uninitialize = rt2x00usb_uninitialize, | |
2029 | .set_device_state = rt73usb_set_device_state, | |
2030 | .link_stats = rt73usb_link_stats, | |
2031 | .reset_tuner = rt73usb_reset_tuner, | |
2032 | .link_tuner = rt73usb_link_tuner, | |
2033 | .write_tx_desc = rt73usb_write_tx_desc, | |
2034 | .write_tx_data = rt2x00usb_write_tx_data, | |
2035 | .kick_tx_queue = rt73usb_kick_tx_queue, | |
2036 | .fill_rxdone = rt73usb_fill_rxdone, | |
2037 | .config_mac_addr = rt73usb_config_mac_addr, | |
2038 | .config_bssid = rt73usb_config_bssid, | |
95ea3627 ID |
2039 | .config_type = rt73usb_config_type, |
2040 | .config = rt73usb_config, | |
2041 | }; | |
2042 | ||
2043 | static const struct rt2x00_ops rt73usb_ops = { | |
2044 | .name = DRV_NAME, | |
2045 | .rxd_size = RXD_DESC_SIZE, | |
2046 | .txd_size = TXD_DESC_SIZE, | |
2047 | .eeprom_size = EEPROM_SIZE, | |
2048 | .rf_size = RF_SIZE, | |
2049 | .lib = &rt73usb_rt2x00_ops, | |
2050 | .hw = &rt73usb_mac80211_ops, | |
2051 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
2052 | .debugfs = &rt73usb_rt2x00debug, | |
2053 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
2054 | }; | |
2055 | ||
2056 | /* | |
2057 | * rt73usb module information. | |
2058 | */ | |
2059 | static struct usb_device_id rt73usb_device_table[] = { | |
2060 | /* AboCom */ | |
2061 | { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2062 | /* Askey */ | |
2063 | { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2064 | /* ASUS */ | |
2065 | { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2066 | { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2067 | /* Belkin */ | |
2068 | { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2069 | { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2070 | { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2071 | /* Billionton */ | |
2072 | { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2073 | /* Buffalo */ | |
2074 | { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2075 | /* CNet */ | |
2076 | { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2077 | { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2078 | /* Conceptronic */ | |
2079 | { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2080 | /* D-Link */ | |
2081 | { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2082 | { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2083 | /* Gemtek */ | |
2084 | { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2085 | /* Gigabyte */ | |
2086 | { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2087 | { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2088 | /* Huawei-3Com */ | |
2089 | { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2090 | /* Hercules */ | |
2091 | { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2092 | { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2093 | /* Linksys */ | |
2094 | { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2095 | { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2096 | /* MSI */ | |
2097 | { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2098 | { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2099 | { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2100 | { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2101 | /* Ralink */ | |
2102 | { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2103 | { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2104 | /* Qcom */ | |
2105 | { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2106 | { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2107 | { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2108 | /* Senao */ | |
2109 | { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2110 | /* Sitecom */ | |
2111 | { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2112 | { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2113 | /* Surecom */ | |
2114 | { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2115 | /* Planex */ | |
2116 | { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2117 | { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2118 | { 0, } | |
2119 | }; | |
2120 | ||
2121 | MODULE_AUTHOR(DRV_PROJECT); | |
2122 | MODULE_VERSION(DRV_VERSION); | |
2123 | MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver."); | |
2124 | MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards"); | |
2125 | MODULE_DEVICE_TABLE(usb, rt73usb_device_table); | |
2126 | MODULE_FIRMWARE(FIRMWARE_RT2571); | |
2127 | MODULE_LICENSE("GPL"); | |
2128 | ||
2129 | static struct usb_driver rt73usb_driver = { | |
2130 | .name = DRV_NAME, | |
2131 | .id_table = rt73usb_device_table, | |
2132 | .probe = rt2x00usb_probe, | |
2133 | .disconnect = rt2x00usb_disconnect, | |
2134 | .suspend = rt2x00usb_suspend, | |
2135 | .resume = rt2x00usb_resume, | |
2136 | }; | |
2137 | ||
2138 | static int __init rt73usb_init(void) | |
2139 | { | |
2140 | return usb_register(&rt73usb_driver); | |
2141 | } | |
2142 | ||
2143 | static void __exit rt73usb_exit(void) | |
2144 | { | |
2145 | usb_deregister(&rt73usb_driver); | |
2146 | } | |
2147 | ||
2148 | module_init(rt73usb_init); | |
2149 | module_exit(rt73usb_exit); |