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mac80211: convert HW flags to unsigned long bitmap
[linux-2.6-block.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
a05b8c58 16 along with this program; if not, see <http://www.gnu.org/licenses/>.
95ea3627
ID		 17 */
18
19/*
20 Module: rt73usb
21 Abstract: rt73usb device specific routines.
22 Supported chipsets: rt2571W & rt2671.
23 */
24
a7f3a06c 25#include <linux/crc-itu-t.h>
95ea3627
ID		 26#include <linux/delay.h>
27#include <linux/etherdevice.h>
95ea3627
ID		 28#include <linux/kernel.h>
29#include <linux/module.h>
5a0e3ad6 30#include <linux/slab.h>
95ea3627
ID		 31#include <linux/usb.h>
32
33#include "rt2x00.h"
34#include "rt2x00usb.h"
35#include "rt73usb.h"
36
008c4482
ID		 37/*
38 * Allow hardware encryption to be disabled.
39 */
eb939922 40static bool modparam_nohwcrypt;
008c4482
ID		 41module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
42MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
43
95ea3627
ID		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
0f829b1d 47 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
8ff48a8b 56 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 57 */
c9c3b1a5 58#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 59 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 60#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 61 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 62
0e14f6d3 63static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 64 const unsigned int word, const u8 value)
65{
66 u32 reg;
67
8ff48a8b 68 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 69
95ea3627 70 /*
c9c3b1a5
ID		 71 * Wait until the BBP becomes available, afterwards we
72 * can safely write the new data into the register.
95ea3627 73 */
c9c3b1a5
ID		 74 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
75 reg = 0;
76 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
77 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
78 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
79 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
80
0f829b1d 81 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 82 }
99ade259 83
8ff48a8b 84 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 85}
86
0e14f6d3 87static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 88 const unsigned int word, u8 *value)
89{
90 u32 reg;
91
8ff48a8b 92 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 93
95ea3627 94 /*
c9c3b1a5
ID		 95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the read request into the register.
97 * After the data has been written, we wait until hardware
98 * returns the correct value, if at any time the register
99 * doesn't become available in time, reg will be 0xffffffff
100 * which means we return 0xff to the caller.
95ea3627 101 */
c9c3b1a5
ID		 102 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
103 reg = 0;
104 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
105 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
106 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 107
0f829b1d 108 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 109
c9c3b1a5
ID		 110 WAIT_FOR_BBP(rt2x00dev, &reg);
111 }
95ea3627
ID		 112
113 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 114
8ff48a8b 115 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 116}
117
0e14f6d3 118static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 119 const unsigned int word, const u32 value)
120{
121 u32 reg;
95ea3627 122
8ff48a8b 123 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 124
4f5af6eb 125 /*
c9c3b1a5
ID		 126 * Wait until the RF becomes available, afterwards we
127 * can safely write the new data into the register.
4f5af6eb 128 */
c9c3b1a5
ID		 129 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
130 reg = 0;
131 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
132 /*
133 * RF5225 and RF2527 contain 21 bits per RF register value,
134 * all others contain 20 bits.
135 */
136 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
5122d898
GW		 137 20 + (rt2x00_rf(rt2x00dev, RF5225) ||
138 rt2x00_rf(rt2x00dev, RF2527)));
c9c3b1a5
ID		 139 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
140 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
141
0f829b1d 142 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 143 rt2x00_rf_write(rt2x00dev, word, value);
144 }
8ff48a8b
ID		 145
146 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 147}
148
149#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 150static const struct rt2x00debug rt73usb_rt2x00debug = {
151 .owner = THIS_MODULE,
152 .csr = {
0f829b1d
ID		 153 .read = rt2x00usb_register_read,
154 .write = rt2x00usb_register_write,
743b97ca
ID		 155 .flags = RT2X00DEBUGFS_OFFSET,
156 .word_base = CSR_REG_BASE,
95ea3627
ID		 157 .word_size = sizeof(u32),
158 .word_count = CSR_REG_SIZE / sizeof(u32),
159 },
160 .eeprom = {
161 .read = rt2x00_eeprom_read,
162 .write = rt2x00_eeprom_write,
743b97ca 163 .word_base = EEPROM_BASE,
95ea3627
ID		 164 .word_size = sizeof(u16),
165 .word_count = EEPROM_SIZE / sizeof(u16),
166 },
167 .bbp = {
168 .read = rt73usb_bbp_read,
169 .write = rt73usb_bbp_write,
743b97ca 170 .word_base = BBP_BASE,
95ea3627
ID		 171 .word_size = sizeof(u8),
172 .word_count = BBP_SIZE / sizeof(u8),
173 },
174 .rf = {
175 .read = rt2x00_rf_read,
176 .write = rt73usb_rf_write,
743b97ca 177 .word_base = RF_BASE,
95ea3627
ID		 178 .word_size = sizeof(u32),
179 .word_count = RF_SIZE / sizeof(u32),
180 },
181};
182#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
183
7396faf4
ID		 184static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
185{
186 u32 reg;
187
188 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
99bdf51a 189 return rt2x00_get_field32(reg, MAC_CSR13_VAL7);
7396faf4 190}
7396faf4 191
771fd565 192#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 193static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 194 enum led_brightness brightness)
195{
196 struct rt2x00_led *led =
197 container_of(led_cdev, struct rt2x00_led, led_dev);
198 unsigned int enabled = brightness != LED_OFF;
199 unsigned int a_mode =
200 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
201 unsigned int bg_mode =
202 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
203
204 if (led->type == LED_TYPE_RADIO) {
205 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
206 MCU_LEDCS_RADIO_STATUS, enabled);
207
47b10cd1
ID		 208 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
209 0, led->rt2x00dev->led_mcu_reg,
210 REGISTER_TIMEOUT);
a9450b70
ID		 211 } else if (led->type == LED_TYPE_ASSOC) {
212 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
213 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
214 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
215 MCU_LEDCS_LINK_A_STATUS, a_mode);
216
47b10cd1
ID		 217 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
218 0, led->rt2x00dev->led_mcu_reg,
219 REGISTER_TIMEOUT);
a9450b70
ID		 220 } else if (led->type == LED_TYPE_QUALITY) {
221 /*
222 * The brightness is divided into 6 levels (0 - 5),
223 * this means we need to convert the brightness
224 * argument into the matching level within that range.
225 */
47b10cd1
ID		 226 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
227 brightness / (LED_FULL / 6),
228 led->rt2x00dev->led_mcu_reg,
229 REGISTER_TIMEOUT);
a9450b70
ID		 230 }
231}
a2e1d52a
ID		 232
233static int rt73usb_blink_set(struct led_classdev *led_cdev,
234 unsigned long *delay_on,
235 unsigned long *delay_off)
236{
237 struct rt2x00_led *led =
238 container_of(led_cdev, struct rt2x00_led, led_dev);
239 u32 reg;
240
0f829b1d 241 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 242 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
243 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 244 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 245
246 return 0;
247}
475433be
ID		 248
249static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
250 struct rt2x00_led *led,
251 enum led_type type)
252{
253 led->rt2x00dev = rt2x00dev;
254 led->type = type;
255 led->led_dev.brightness_set = rt73usb_brightness_set;
256 led->led_dev.blink_set = rt73usb_blink_set;
257 led->flags = LED_INITIALIZED;
258}
771fd565 259#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 260
95ea3627
ID		 261/*
262 * Configuration handlers.
263 */
906c110f
ID		 264static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
265 struct rt2x00lib_crypto *crypto,
266 struct ieee80211_key_conf *key)
267{
268 struct hw_key_entry key_entry;
269 struct rt2x00_field32 field;
906c110f
ID		 270 u32 mask;
271 u32 reg;
272
273 if (crypto->cmd == SET_KEY) {
274 /*
275 * rt2x00lib can't determine the correct free
276 * key_idx for shared keys. We have 1 register
277 * with key valid bits. The goal is simple, read
278 * the register, if that is full we have no slots
279 * left.
280 * Note that each BSS is allowed to have up to 4
281 * shared keys, so put a mask over the allowed
282 * entries.
283 */
284 mask = (0xf << crypto->bssidx);
285
0f829b1d 286 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 287 reg &= mask;
288
289 if (reg && reg == mask)
290 return -ENOSPC;
291
acaf908d 292 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 293
294 /*
295 * Upload key to hardware
296 */
297 memcpy(key_entry.key, crypto->key,
298 sizeof(key_entry.key));
299 memcpy(key_entry.tx_mic, crypto->tx_mic,
300 sizeof(key_entry.tx_mic));
301 memcpy(key_entry.rx_mic, crypto->rx_mic,
302 sizeof(key_entry.rx_mic));
303
304 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
96b61baf
GW		 305 rt2x00usb_register_multiwrite(rt2x00dev, reg,
306 &key_entry, sizeof(key_entry));
906c110f
ID		 307
308 /*
309 * The cipher types are stored over 2 registers.
310 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
311 * bssidx 1 and 2 keys are stored in SEC_CSR5.
312 * Using the correct defines correctly will cause overhead,
313 * so just calculate the correct offset.
314 */
315 if (key->hw_key_idx < 8) {
316 field.bit_offset = (3 * key->hw_key_idx);
317 field.bit_mask = 0x7 << field.bit_offset;
318
0f829b1d 319 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 320 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 321 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 322 } else {
323 field.bit_offset = (3 * (key->hw_key_idx - 8));
324 field.bit_mask = 0x7 << field.bit_offset;
325
0f829b1d 326 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 327 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 328 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 329 }
330
331 /*
332 * The driver does not support the IV/EIV generation
333 * in hardware. However it doesn't support the IV/EIV
334 * inside the ieee80211 frame either, but requires it
3ad2f3fb 335 * to be provided separately for the descriptor.
906c110f
ID		 336 * rt2x00lib will cut the IV/EIV data out of all frames
337 * given to us by mac80211, but we must tell mac80211
338 * to generate the IV/EIV data.
339 */
340 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
341 }
342
343 /*
344 * SEC_CSR0 contains only single-bit fields to indicate
345 * a particular key is valid. Because using the FIELD32()
346 * defines directly will cause a lot of overhead we use
347 * a calculation to determine the correct bit directly.
348 */
349 mask = 1 << key->hw_key_idx;
350
0f829b1d 351 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 352 if (crypto->cmd == SET_KEY)
353 reg |= mask;
354 else if (crypto->cmd == DISABLE_KEY)
355 reg &= ~mask;
0f829b1d 356 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 357
358 return 0;
359}
360
361static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
362 struct rt2x00lib_crypto *crypto,
363 struct ieee80211_key_conf *key)
364{
365 struct hw_pairwise_ta_entry addr_entry;
366 struct hw_key_entry key_entry;
906c110f
ID		 367 u32 mask;
368 u32 reg;
369
370 if (crypto->cmd == SET_KEY) {
371 /*
372 * rt2x00lib can't determine the correct free
373 * key_idx for pairwise keys. We have 2 registers
374 * with key valid bits. The goal is simple, read
375 * the first register, if that is full move to
376 * the next register.
377 * When both registers are full, we drop the key,
378 * otherwise we use the first invalid entry.
379 */
0f829b1d 380 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 381 if (reg && reg == ~0) {
382 key->hw_key_idx = 32;
0f829b1d 383 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 384 if (reg && reg == ~0)
385 return -ENOSPC;
386 }
387
acaf908d 388 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 389
390 /*
391 * Upload key to hardware
392 */
393 memcpy(key_entry.key, crypto->key,
394 sizeof(key_entry.key));
395 memcpy(key_entry.tx_mic, crypto->tx_mic,
396 sizeof(key_entry.tx_mic));
397 memcpy(key_entry.rx_mic, crypto->rx_mic,
398 sizeof(key_entry.rx_mic));
399
400 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
96b61baf
GW		 401 rt2x00usb_register_multiwrite(rt2x00dev, reg,
402 &key_entry, sizeof(key_entry));
906c110f
ID		 403
404 /*
405 * Send the address and cipher type to the hardware register.
906c110f
ID		 406 */
407 memset(&addr_entry, 0, sizeof(addr_entry));
408 memcpy(&addr_entry, crypto->address, ETH_ALEN);
409 addr_entry.cipher = crypto->cipher;
410
411 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 412 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 413 &addr_entry, sizeof(addr_entry));
414
415 /*
416 * Enable pairwise lookup table for given BSS idx,
417 * without this received frames will not be decrypted
418 * by the hardware.
419 */
0f829b1d 420 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 421 reg |= (1 << crypto->bssidx);
0f829b1d 422 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 423
424 /*
425 * The driver does not support the IV/EIV generation
426 * in hardware. However it doesn't support the IV/EIV
427 * inside the ieee80211 frame either, but requires it
3ad2f3fb 428 * to be provided separately for the descriptor.
906c110f
ID		 429 * rt2x00lib will cut the IV/EIV data out of all frames
430 * given to us by mac80211, but we must tell mac80211
431 * to generate the IV/EIV data.
432 */
433 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
434 }
435
436 /*
437 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
438 * a particular key is valid. Because using the FIELD32()
439 * defines directly will cause a lot of overhead we use
440 * a calculation to determine the correct bit directly.
441 */
442 if (key->hw_key_idx < 32) {
443 mask = 1 << key->hw_key_idx;
444
0f829b1d 445 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 446 if (crypto->cmd == SET_KEY)
447 reg |= mask;
448 else if (crypto->cmd == DISABLE_KEY)
449 reg &= ~mask;
0f829b1d 450 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 451 } else {
452 mask = 1 << (key->hw_key_idx - 32);
453
0f829b1d 454 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 455 if (crypto->cmd == SET_KEY)
456 reg |= mask;
457 else if (crypto->cmd == DISABLE_KEY)
458 reg &= ~mask;
0f829b1d 459 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 460 }
461
462 return 0;
463}
464
3a643d24
ID		 465static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
466 const unsigned int filter_flags)
467{
468 u32 reg;
469
470 /*
471 * Start configuration steps.
472 * Note that the version error will always be dropped
473 * and broadcast frames will always be accepted since
474 * there is no filter for it at this time.
475 */
0f829b1d 476 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 477 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
478 !(filter_flags & FIF_FCSFAIL));
479 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
480 !(filter_flags & FIF_PLCPFAIL));
481 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 482 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
df140465 483 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME, 1);
3a643d24 484 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa 485 !rt2x00dev->intf_ap_count);
3a643d24
ID		 486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
487 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
488 !(filter_flags & FIF_ALLMULTI));
489 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
490 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
491 !(filter_flags & FIF_CONTROL));
0f829b1d 492 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 493}
494
6bb40dd1
ID		 495static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
496 struct rt2x00_intf *intf,
497 struct rt2x00intf_conf *conf,
498 const unsigned int flags)
95ea3627 499{
6bb40dd1 500 u32 reg;
95ea3627 501
6bb40dd1 502 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 503 /*
504 * Enable synchronisation.
505 */
0f829b1d 506 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
6bb40dd1 507 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
0f829b1d 508 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 509 }
95ea3627 510
6bb40dd1
ID		 511 if (flags & CONFIG_UPDATE_MAC) {
512 reg = le32_to_cpu(conf->mac[1]);
513 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
514 conf->mac[1] = cpu_to_le32(reg);
95ea3627 515
0f829b1d 516 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 517 conf->mac, sizeof(conf->mac));
518 }
95ea3627 519
6bb40dd1
ID		 520 if (flags & CONFIG_UPDATE_BSSID) {
521 reg = le32_to_cpu(conf->bssid[1]);
522 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
523 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 524
0f829b1d 525 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 526 conf->bssid, sizeof(conf->bssid));
527 }
95ea3627
ID		 528}
529
3a643d24 530static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 531 struct rt2x00lib_erp *erp,
532 u32 changed)
95ea3627 533{
95ea3627 534 u32 reg;
95ea3627 535
0f829b1d 536 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 537 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 538 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 539 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 540
02044643
HS		 541 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
542 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
543 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
544 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
545 !!erp->short_preamble);
546 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
547 }
95ea3627 548
02044643
HS		 549 if (changed & BSS_CHANGED_BASIC_RATES)
550 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
551 erp->basic_rates);
95ea3627 552
02044643
HS		 553 if (changed & BSS_CHANGED_BEACON_INT) {
554 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
555 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
556 erp->beacon_int * 16);
557 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
558 }
8a566afe 559
02044643
HS		 560 if (changed & BSS_CHANGED_ERP_SLOT) {
561 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
562 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
563 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 564
02044643
HS		 565 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
566 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
567 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
568 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
569 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
570 }
95ea3627
ID		 571}
572
573static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 574 struct antenna_setup *ant)
95ea3627
ID		 575{
576 u8 r3;
577 u8 r4;
578 u8 r77;
2676c94d 579 u8 temp;
95ea3627
ID		 580
581 rt73usb_bbp_read(rt2x00dev, 3, &r3);
582 rt73usb_bbp_read(rt2x00dev, 4, &r4);
583 rt73usb_bbp_read(rt2x00dev, 77, &r77);
584
585 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
586
e4cd2ff8
ID		 587 /*
588 * Configure the RX antenna.
589 */
addc81bd 590 switch (ant->rx) {
95ea3627 591 case ANTENNA_HW_DIVERSITY:
2676c94d 592 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
7e43f3b0
GJ		 593 temp = !rt2x00_has_cap_frame_type(rt2x00dev) &&
594 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 595 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 596 break;
597 case ANTENNA_A:
2676c94d 598 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 599 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 600 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 601 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
602 else
603 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 604 break;
605 case ANTENNA_B:
a4fe07d9 606 default:
2676c94d 607 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 608 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 609 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 610 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
611 else
612 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 613 break;
614 }
615
616 rt73usb_bbp_write(rt2x00dev, 77, r77);
617 rt73usb_bbp_write(rt2x00dev, 3, r3);
618 rt73usb_bbp_write(rt2x00dev, 4, r4);
619}
620
621static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 622 struct antenna_setup *ant)
95ea3627
ID		 623{
624 u8 r3;
625 u8 r4;
626 u8 r77;
627
628 rt73usb_bbp_read(rt2x00dev, 3, &r3);
629 rt73usb_bbp_read(rt2x00dev, 4, &r4);
630 rt73usb_bbp_read(rt2x00dev, 77, &r77);
631
632 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
633 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
7e43f3b0 634 !rt2x00_has_cap_frame_type(rt2x00dev));
95ea3627 635
e4cd2ff8
ID		 636 /*
637 * Configure the RX antenna.
638 */
addc81bd 639 switch (ant->rx) {
95ea3627 640 case ANTENNA_HW_DIVERSITY:
2676c94d 641 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 642 break;
643 case ANTENNA_A:
2676c94d
MN		 644 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
645 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 646 break;
647 case ANTENNA_B:
a4fe07d9 648 default:
2676c94d
MN		 649 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
650 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 651 break;
652 }
653
654 rt73usb_bbp_write(rt2x00dev, 77, r77);
655 rt73usb_bbp_write(rt2x00dev, 3, r3);
656 rt73usb_bbp_write(rt2x00dev, 4, r4);
657}
658
659struct antenna_sel {
660 u8 word;
661 /*
662 * value[0] -> non-LNA
663 * value[1] -> LNA
664 */
665 u8 value[2];
666};
667
668static const struct antenna_sel antenna_sel_a[] = {
669 { 96, { 0x58, 0x78 } },
670 { 104, { 0x38, 0x48 } },
671 { 75, { 0xfe, 0x80 } },
672 { 86, { 0xfe, 0x80 } },
673 { 88, { 0xfe, 0x80 } },
674 { 35, { 0x60, 0x60 } },
675 { 97, { 0x58, 0x58 } },
676 { 98, { 0x58, 0x58 } },
677};
678
679static const struct antenna_sel antenna_sel_bg[] = {
680 { 96, { 0x48, 0x68 } },
681 { 104, { 0x2c, 0x3c } },
682 { 75, { 0xfe, 0x80 } },
683 { 86, { 0xfe, 0x80 } },
684 { 88, { 0xfe, 0x80 } },
685 { 35, { 0x50, 0x50 } },
686 { 97, { 0x48, 0x48 } },
687 { 98, { 0x48, 0x48 } },
688};
689
e4ea1c40
ID		 690static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
691 struct antenna_setup *ant)
95ea3627
ID		 692{
693 const struct antenna_sel *sel;
694 unsigned int lna;
695 unsigned int i;
696 u32 reg;
697
a4fe07d9
ID		 698 /*
699 * We should never come here because rt2x00lib is supposed
700 * to catch this and send us the correct antenna explicitely.
701 */
702 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
703 ant->tx == ANTENNA_SW_DIVERSITY);
704
8318d78a 705 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627 706 sel = antenna_sel_a;
7e43f3b0 707 lna = rt2x00_has_cap_external_lna_a(rt2x00dev);
95ea3627
ID		 708 } else {
709 sel = antenna_sel_bg;
7e43f3b0 710 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev);
95ea3627
ID		 711 }
712
2676c94d
MN		 713 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
714 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
715
0f829b1d 716 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 717
ddc827f9 718 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 719 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 720 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 721 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 722
0f829b1d 723 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627 724
5122d898 725 if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
addc81bd 726 rt73usb_config_antenna_5x(rt2x00dev, ant);
5122d898 727 else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
addc81bd 728 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 729}
730
e4ea1c40 731static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 732 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 733{
734 u16 eeprom;
735 short lna_gain = 0;
736
675a0b04 737 if (libconf->conf->chandef.chan->band == IEEE80211_BAND_2GHZ) {
7e43f3b0 738 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
e4ea1c40
ID		 739 lna_gain += 14;
740
741 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
742 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
743 } else {
744 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
745 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
746 }
747
748 rt2x00dev->lna_gain = lna_gain;
749}
750
751static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
752 struct rf_channel *rf, const int txpower)
753{
754 u8 r3;
755 u8 r94;
756 u8 smart;
757
758 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
759 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
760
5122d898 761 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 762
763 rt73usb_bbp_read(rt2x00dev, 3, &r3);
764 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
765 rt73usb_bbp_write(rt2x00dev, 3, r3);
766
767 r94 = 6;
768 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
769 r94 += txpower - MAX_TXPOWER;
770 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
771 r94 += txpower;
772 rt73usb_bbp_write(rt2x00dev, 94, r94);
773
774 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
775 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
776 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
777 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
778
779 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
780 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
781 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
782 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
783
784 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
785 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
786 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
787 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
788
789 udelay(10);
790}
791
792static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
793 const int txpower)
794{
795 struct rf_channel rf;
796
797 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
798 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
799 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
800 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
801
802 rt73usb_config_channel(rt2x00dev, &rf, txpower);
803}
804
805static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
806 struct rt2x00lib_conf *libconf)
95ea3627
ID		 807{
808 u32 reg;
809
0f829b1d 810 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e1b4d7b7
ID		 811 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
812 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
813 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
e4ea1c40
ID		 814 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
815 libconf->conf->long_frame_max_tx_count);
816 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
817 libconf->conf->short_frame_max_tx_count);
0f829b1d 818 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 819}
95ea3627 820
7d7f19cc
ID		 821static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
822 struct rt2x00lib_conf *libconf)
823{
824 enum dev_state state =
825 (libconf->conf->flags & IEEE80211_CONF_PS) ?
826 STATE_SLEEP : STATE_AWAKE;
827 u32 reg;
828
829 if (state == STATE_SLEEP) {
830 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
831 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 832 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 833 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
834 libconf->conf->listen_interval - 1);
835 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
836
837 /* We must first disable autowake before it can be enabled */
838 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
839 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
840
841 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
842 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
843
844 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
845 USB_MODE_SLEEP, REGISTER_TIMEOUT);
846 } else {
7d7f19cc
ID		 847 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
848 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
849 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
850 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
851 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
852 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
5731858d
GW		 853
854 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
855 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
7d7f19cc
ID		 856 }
857}
858
95ea3627 859static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 860 struct rt2x00lib_conf *libconf,
861 const unsigned int flags)
95ea3627 862{
ba2ab471
ID		 863 /* Always recalculate LNA gain before changing configuration */
864 rt73usb_config_lna_gain(rt2x00dev, libconf);
865
e4ea1c40 866 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 867 rt73usb_config_channel(rt2x00dev, &libconf->rf,
868 libconf->conf->power_level);
e4ea1c40
ID		 869 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
870 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 871 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 872 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
873 rt73usb_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 874 if (flags & IEEE80211_CONF_CHANGE_PS)
875 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 876}
877
95ea3627
ID		 878/*
879 * Link tuning
880 */
ebcf26da
ID		 881static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
882 struct link_qual *qual)
95ea3627
ID		 883{
884 u32 reg;
885
886 /*
887 * Update FCS error count from register.
888 */
0f829b1d 889 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 890 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 891
892 /*
893 * Update False CCA count from register.
894 */
0f829b1d 895 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 896 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 897}
898
5352ff65
ID		 899static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
900 struct link_qual *qual, u8 vgc_level)
eb20b4e8 901{
5352ff65 902 if (qual->vgc_level != vgc_level) {
eb20b4e8 903 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 904 qual->vgc_level = vgc_level;
905 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 906 }
907}
908
5352ff65
ID		 909static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
910 struct link_qual *qual)
95ea3627 911{
5352ff65 912 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 913}
914
5352ff65
ID		 915static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
916 struct link_qual *qual, const u32 count)
95ea3627 917{
95ea3627
ID		 918 u8 up_bound;
919 u8 low_bound;
920
95ea3627
ID		 921 /*
922 * Determine r17 bounds.
923 */
e5ef5bad 924 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 925 low_bound = 0x28;
926 up_bound = 0x48;
927
7e43f3b0 928 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
95ea3627
ID		 929 low_bound += 0x10;
930 up_bound += 0x10;
931 }
932 } else {
5352ff65 933 if (qual->rssi > -82) {
95ea3627
ID		 934 low_bound = 0x1c;
935 up_bound = 0x40;
5352ff65 936 } else if (qual->rssi > -84) {
95ea3627
ID		 937 low_bound = 0x1c;
938 up_bound = 0x20;
939 } else {
940 low_bound = 0x1c;
941 up_bound = 0x1c;
942 }
943
7e43f3b0 944 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
95ea3627
ID		 945 low_bound += 0x14;
946 up_bound += 0x10;
947 }
948 }
949
6bb40dd1
ID		 950 /*
951 * If we are not associated, we should go straight to the
952 * dynamic CCA tuning.
953 */
954 if (!rt2x00dev->intf_associated)
955 goto dynamic_cca_tune;
956
95ea3627
ID		 957 /*
958 * Special big-R17 for very short distance
959 */
5352ff65
ID		 960 if (qual->rssi > -35) {
961 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 962 return;
963 }
964
965 /*
966 * Special big-R17 for short distance
967 */
5352ff65
ID		 968 if (qual->rssi >= -58) {
969 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 970 return;
971 }
972
973 /*
974 * Special big-R17 for middle-short distance
975 */
5352ff65
ID		 976 if (qual->rssi >= -66) {
977 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 978 return;
979 }
980
981 /*
982 * Special mid-R17 for middle distance
983 */
5352ff65
ID		 984 if (qual->rssi >= -74) {
985 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 986 return;
987 }
988
989 /*
990 * Special case: Change up_bound based on the rssi.
991 * Lower up_bound when rssi is weaker then -74 dBm.
992 */
5352ff65 993 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 994 if (low_bound > up_bound)
995 up_bound = low_bound;
996
5352ff65
ID		 997 if (qual->vgc_level > up_bound) {
998 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 999 return;
1000 }
1001
6bb40dd1
ID		 1002dynamic_cca_tune:
1003
95ea3627
ID		 1004 /*
1005 * r17 does not yet exceed upper limit, continue and base
1006 * the r17 tuning on the false CCA count.
1007 */
5352ff65
ID		 1008 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1009 rt73usb_set_vgc(rt2x00dev, qual,
1010 min_t(u8, qual->vgc_level + 4, up_bound));
1011 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1012 rt73usb_set_vgc(rt2x00dev, qual,
1013 max_t(u8, qual->vgc_level - 4, low_bound));
95ea3627
ID		 1014}
1015
5450b7e2
ID		 1016/*
1017 * Queue handlers.
1018 */
1019static void rt73usb_start_queue(struct data_queue *queue)
1020{
1021 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1022 u32 reg;
1023
1024 switch (queue->qid) {
1025 case QID_RX:
1026 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1027 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1028 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1029 break;
1030 case QID_BEACON:
1031 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1032 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1033 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1034 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1035 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1036 break;
1037 default:
1038 break;
1039 }
1040}
1041
1042static void rt73usb_stop_queue(struct data_queue *queue)
1043{
1044 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1045 u32 reg;
1046
1047 switch (queue->qid) {
1048 case QID_RX:
1049 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1050 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1051 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1052 break;
1053 case QID_BEACON:
1054 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1055 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1056 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1057 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1058 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1059 break;
1060 default:
1061 break;
1062 }
5450b7e2
ID		 1063}
1064
95ea3627 1065/*
a7f3a06c 1066 * Firmware functions
95ea3627
ID		 1067 */
1068static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1069{
1070 return FIRMWARE_RT2571;
1071}
1072
0cbe0064
ID		 1073static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1074 const u8 *data, const size_t len)
a7f3a06c 1075{
0cbe0064 1076 u16 fw_crc;
a7f3a06c
ID		 1077 u16 crc;
1078
1079 /*
0cbe0064
ID		 1080 * Only support 2kb firmware files.
1081 */
1082 if (len != 2048)
1083 return FW_BAD_LENGTH;
1084
1085 /*
a7f3a06c
ID		 1086 * The last 2 bytes in the firmware array are the crc checksum itself,
1087 * this means that we should never pass those 2 bytes to the crc
1088 * algorithm.
1089 */
0cbe0064
ID		 1090 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1091
1092 /*
1093 * Use the crc itu-t algorithm.
1094 */
a7f3a06c
ID		 1095 crc = crc_itu_t(0, data, len - 2);
1096 crc = crc_itu_t_byte(crc, 0);
1097 crc = crc_itu_t_byte(crc, 0);
1098
0cbe0064 1099 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1100}
1101
0cbe0064
ID		 1102static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1103 const u8 *data, const size_t len)
95ea3627
ID		 1104{
1105 unsigned int i;
1106 int status;
1107 u32 reg;
95ea3627
ID		 1108
1109 /*
1110 * Wait for stable hardware.
1111 */
1112 for (i = 0; i < 100; i++) {
0f829b1d 1113 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1114 if (reg)
1115 break;
1116 msleep(1);
1117 }
1118
1119 if (!reg) {
ec9c4989 1120 rt2x00_err(rt2x00dev, "Unstable hardware\n");
95ea3627
ID		 1121 return -EBUSY;
1122 }
1123
1124 /*
1125 * Write firmware to device.
95ea3627 1126 */
96b61baf 1127 rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
95ea3627
ID		 1128
1129 /*
1130 * Send firmware request to device to load firmware,
1131 * we need to specify a long timeout time.
1132 */
1133 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1134 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1135 REGISTER_TIMEOUT_FIRMWARE);
1136 if (status < 0) {
ec9c4989 1137 rt2x00_err(rt2x00dev, "Failed to write Firmware to device\n");
95ea3627
ID		 1138 return status;
1139 }
1140
95ea3627
ID		 1141 return 0;
1142}
1143
a7f3a06c
ID		 1144/*
1145 * Initialization functions.
1146 */
95ea3627
ID		 1147static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1148{
1149 u32 reg;
1150
0f829b1d 1151 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1152 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1153 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1154 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1155 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1156
0f829b1d 1157 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1158 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1159 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1160 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1161 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1162 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1163 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1164 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1165 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1166 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1167
1168 /*
1169 * CCK TXD BBP registers
1170 */
0f829b1d 1171 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1172 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1173 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1174 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1175 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1176 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1177 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1178 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1179 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1180 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1181
1182 /*
1183 * OFDM TXD BBP registers
1184 */
0f829b1d 1185 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1186 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1187 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1188 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1189 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1190 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1191 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1192 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1193
0f829b1d 1194 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1195 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1196 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1197 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1198 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1199 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1200
0f829b1d 1201 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1202 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1203 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1204 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1205 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1206 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1207
0f829b1d 1208 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1209 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1210 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1211 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1212 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1213 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1214 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1215 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1216
0f829b1d 1217 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1218
0f829b1d 1219 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1220 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1221 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1222
0f829b1d 1223 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1224
1225 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1226 return -EBUSY;
1227
0f829b1d 1228 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1229
1230 /*
1231 * Invalidate all Shared Keys (SEC_CSR0),
1232 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1233 */
0f829b1d
ID		 1234 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1235 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1236 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1237
1238 reg = 0x000023b0;
5122d898 1239 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
95ea3627 1240 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1241 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1242
0f829b1d
ID		 1243 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1244 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1245 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1246
0f829b1d 1247 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1248 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1249 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1250
6bb40dd1
ID		 1251 /*
1252 * Clear all beacons
1253 * For the Beacon base registers we only need to clear
1254 * the first byte since that byte contains the VALID and OWNER
1255 * bits which (when set to 0) will invalidate the entire beacon.
1256 */
0f829b1d
ID		 1257 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1258 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1259 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1260 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1261
95ea3627
ID		 1262 /*
1263 * We must clear the error counters.
1264 * These registers are cleared on read,
1265 * so we may pass a useless variable to store the value.
1266 */
0f829b1d
ID		 1267 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1268 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1269 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1270
1271 /*
1272 * Reset MAC and BBP registers.
1273 */
0f829b1d 1274 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1275 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1276 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1277 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1278
0f829b1d 1279 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1280 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1281 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1282 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1283
0f829b1d 1284 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1285 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1286 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1287
1288 return 0;
1289}
1290
2b08da3f 1291static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1292{
1293 unsigned int i;
95ea3627
ID		 1294 u8 value;
1295
7a5a7352 1296 for (i = 0; i < REGISTER_USB_BUSY_COUNT; i++) {
95ea3627
ID		 1297 rt73usb_bbp_read(rt2x00dev, 0, &value);
1298 if ((value != 0xff) && (value != 0x00))
2b08da3f 1299 return 0;
95ea3627
ID		 1300 udelay(REGISTER_BUSY_DELAY);
1301 }
1302
ec9c4989 1303 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
95ea3627 1304 return -EACCES;
2b08da3f
ID		 1305}
1306
1307static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1308{
1309 unsigned int i;
1310 u16 eeprom;
1311 u8 reg_id;
1312 u8 value;
1313
1314 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1315 return -EACCES;
95ea3627 1316
95ea3627
ID		 1317 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1318 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1319 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1320 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1321 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1322 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1323 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1324 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1325 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1326 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1327 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1328 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1329 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1330 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1331 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1332 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1333 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1334 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1335 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1336 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1337 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1338 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1339 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1340 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1341 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1342
95ea3627
ID		 1343 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1344 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1345
1346 if (eeprom != 0xffff && eeprom != 0x0000) {
1347 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1348 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1349 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1350 }
1351 }
95ea3627
ID		 1352
1353 return 0;
1354}
1355
1356/*
1357 * Device state switch handlers.
1358 */
95ea3627
ID		 1359static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1360{
1361 /*
1362 * Initialize all registers.
1363 */
2b08da3f
ID		 1364 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1365 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1366 return -EIO;
95ea3627 1367
95ea3627
ID		 1368 return 0;
1369}
1370
1371static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1372{
0f829b1d 1373 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1374
1375 /*
1376 * Disable synchronisation.
1377 */
0f829b1d 1378 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1379
1380 rt2x00usb_disable_radio(rt2x00dev);
1381}
1382
1383static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1384{
9655a6ec 1385 u32 reg, reg2;
95ea3627
ID		 1386 unsigned int i;
1387 char put_to_sleep;
95ea3627
ID		 1388
1389 put_to_sleep = (state != STATE_AWAKE);
1390
0f829b1d 1391 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1392 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1393 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1394 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1395
1396 /*
1397 * Device is not guaranteed to be in the requested state yet.
1398 * We must wait until the register indicates that the
1399 * device has entered the correct state.
1400 */
1401 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1402 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg2);
1403 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
2b08da3f 1404 if (state == !put_to_sleep)
95ea3627 1405 return 0;
9655a6ec 1406 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1407 msleep(10);
1408 }
1409
95ea3627
ID		 1410 return -EBUSY;
1411}
1412
1413static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1414 enum dev_state state)
1415{
1416 int retval = 0;
1417
1418 switch (state) {
1419 case STATE_RADIO_ON:
1420 retval = rt73usb_enable_radio(rt2x00dev);
1421 break;
1422 case STATE_RADIO_OFF:
1423 rt73usb_disable_radio(rt2x00dev);
1424 break;
2b08da3f
ID		 1425 case STATE_RADIO_IRQ_ON:
1426 case STATE_RADIO_IRQ_OFF:
1427 /* No support, but no error either */
95ea3627
ID		 1428 break;
1429 case STATE_DEEP_SLEEP:
1430 case STATE_SLEEP:
1431 case STATE_STANDBY:
1432 case STATE_AWAKE:
1433 retval = rt73usb_set_state(rt2x00dev, state);
1434 break;
1435 default:
1436 retval = -ENOTSUPP;
1437 break;
1438 }
1439
2b08da3f 1440 if (unlikely(retval))
ec9c4989
JP		 1441 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1442 state, retval);
2b08da3f 1443
95ea3627
ID		 1444 return retval;
1445}
1446
1447/*
1448 * TX descriptor initialization
1449 */
93331458 1450static void rt73usb_write_tx_desc(struct queue_entry *entry,
906c110f 1451 struct txentry_desc *txdesc)
95ea3627 1452{
93331458
ID		 1453 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1454 __le32 *txd = (__le32 *) entry->skb->data;
95ea3627
ID		 1455 u32 word;
1456
1457 /*
1458 * Start writing the descriptor words.
1459 */
e01f1ec3
GW		 1460 rt2x00_desc_read(txd, 0, &word);
1461 rt2x00_set_field32(&word, TXD_W0_BURST,
1462 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1463 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1464 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1465 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1466 rt2x00_set_field32(&word, TXD_W0_ACK,
1467 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1468 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1469 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1470 rt2x00_set_field32(&word, TXD_W0_OFDM,
1471 (txdesc->rate_mode == RATE_MODE_OFDM));
2517794b 1472 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
e01f1ec3
GW		 1473 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1474 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1475 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1476 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1477 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1478 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1479 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1480 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1481 rt2x00_set_field32(&word, TXD_W0_BURST2,
1482 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1483 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1484 rt2x00_desc_write(txd, 0, word);
1485
95ea3627 1486 rt2x00_desc_read(txd, 1, &word);
2b23cdaa
HS		 1487 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1488 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1489 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1490 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
906c110f 1491 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1492 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1493 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1494 rt2x00_desc_write(txd, 1, word);
1495
1496 rt2x00_desc_read(txd, 2, &word);
26a1d07f
HS		 1497 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1498 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1499 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1500 txdesc->u.plcp.length_low);
1501 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1502 txdesc->u.plcp.length_high);
95ea3627
ID		 1503 rt2x00_desc_write(txd, 2, word);
1504
906c110f 1505 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1506 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1507 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1508 }
1509
95ea3627
ID		 1510 rt2x00_desc_read(txd, 5, &word);
1511 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
93331458 1512 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
95ea3627
ID		 1513 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1514 rt2x00_desc_write(txd, 5, word);
1515
85b7a8b3
GW		 1516 /*
1517 * Register descriptor details in skb frame descriptor.
1518 */
0b8004aa 1519 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
85b7a8b3
GW		 1520 skbdesc->desc = txd;
1521 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1522}
1523
bd88a781
ID		 1524/*
1525 * TX data initialization
1526 */
f224f4ef
GW		 1527static void rt73usb_write_beacon(struct queue_entry *entry,
1528 struct txentry_desc *txdesc)
bd88a781
ID		 1529{
1530 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781 1531 unsigned int beacon_base;
739fd940 1532 unsigned int padding_len;
d76dfc61 1533 u32 orig_reg, reg;
bd88a781 1534
bd88a781
ID		 1535 /*
1536 * Disable beaconing while we are reloading the beacon data,
1537 * otherwise we might be sending out invalid data.
1538 */
0f829b1d 1539 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
d76dfc61 1540 orig_reg = reg;
bd88a781 1541 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1542 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781 1543
0b8004aa
GW		 1544 /*
1545 * Add space for the descriptor in front of the skb.
1546 */
1547 skb_push(entry->skb, TXD_DESC_SIZE);
1548 memset(entry->skb->data, 0, TXD_DESC_SIZE);
1549
5c3b685c
GW		 1550 /*
1551 * Write the TX descriptor for the beacon.
1552 */
93331458 1553 rt73usb_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1554
1555 /*
1556 * Dump beacon to userspace through debugfs.
1557 */
1558 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1559
bd88a781 1560 /*
739fd940 1561 * Write entire beacon with descriptor and padding to register.
bd88a781 1562 */
739fd940 1563 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 1564 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1565 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1566 /* skb freed by skb_pad() on failure */
1567 entry->skb = NULL;
1568 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1569 return;
1570 }
1571
bd88a781 1572 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 1573 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1574 entry->skb->len + padding_len);
bd88a781 1575
d61cb266
GW		 1576 /*
1577 * Enable beaconing again.
1578 *
1579 * For Wi-Fi faily generated beacons between participating stations.
1580 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1581 */
1582 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1583
d61cb266
GW		 1584 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1585 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1586
bd88a781
ID		 1587 /*
1588 * Clean up the beacon skb.
1589 */
1590 dev_kfree_skb(entry->skb);
1591 entry->skb = NULL;
1592}
1593
69cf36a4
HS		 1594static void rt73usb_clear_beacon(struct queue_entry *entry)
1595{
1596 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1597 unsigned int beacon_base;
bc0df75a 1598 u32 orig_reg, reg;
69cf36a4
HS		 1599
1600 /*
1601 * Disable beaconing while we are reloading the beacon data,
1602 * otherwise we might be sending out invalid data.
1603 */
bc0df75a
SG		 1604 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &orig_reg);
1605 reg = orig_reg;
69cf36a4
HS		 1606 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1607 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1608
1609 /*
1610 * Clear beacon.
1611 */
1612 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1613 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
1614
1615 /*
bc0df75a 1616 * Restore beaconing state.
69cf36a4 1617 */
bc0df75a 1618 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
69cf36a4
HS		 1619}
1620
f1ca2167 1621static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1622{
1623 int length;
1624
1625 /*
1626 * The length _must_ be a multiple of 4,
1627 * but it must _not_ be a multiple of the USB packet size.
1628 */
f1ca2167
ID		 1629 length = roundup(entry->skb->len, 4);
1630 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1631
1632 return length;
1633}
1634
95ea3627
ID		 1635/*
1636 * RX control handlers
1637 */
1638static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1639{
ba2ab471 1640 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1641 u8 lna;
1642
1643 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1644 switch (lna) {
1645 case 3:
ba2ab471 1646 offset += 90;
95ea3627
ID		 1647 break;
1648 case 2:
ba2ab471 1649 offset += 74;
95ea3627
ID		 1650 break;
1651 case 1:
ba2ab471 1652 offset += 64;
95ea3627
ID		 1653 break;
1654 default:
1655 return 0;
1656 }
1657
e5ef5bad 1658 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
7e43f3b0 1659 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
95ea3627
ID		 1660 if (lna == 3 || lna == 2)
1661 offset += 10;
1662 } else {
1663 if (lna == 3)
1664 offset += 6;
1665 else if (lna == 2)
1666 offset += 8;
1667 }
95ea3627
ID		 1668 }
1669
1670 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1671}
1672
181d6902 1673static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1674 struct rxdone_entry_desc *rxdesc)
95ea3627 1675{
906c110f 1676 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1677 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1678 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1679 u32 word0;
1680 u32 word1;
1681
f855c10b 1682 /*
a26cbc65
GW		 1683 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1684 * frame data in rt2x00usb.
f855c10b 1685 */
a26cbc65 1686 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1687 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1688
1689 /*
70a96109 1690 * It is now safe to read the descriptor on all architectures.
f855c10b 1691 */
95ea3627
ID		 1692 rt2x00_desc_read(rxd, 0, &word0);
1693 rt2x00_desc_read(rxd, 1, &word1);
1694
4150c572 1695 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1696 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1697
78b8f3b0
GW		 1698 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1699 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
906c110f
ID		 1700
1701 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1702 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1703 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1704 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1705
906c110f 1706 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1707 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1708
1709 /*
1710 * Hardware has stripped IV/EIV data from 802.11 frame during
3ad2f3fb 1711 * decryption. It has provided the data separately but rt2x00lib
906c110f
ID		 1712 * should decide if it should be reinserted.
1713 */
1714 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1715
1716 /*
a0aff623
GW		 1717 * The hardware has already checked the Michael Mic and has
1718 * stripped it from the frame. Signal this to mac80211.
906c110f
ID		 1719 */
1720 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1721
1722 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1723 rxdesc->flags |= RX_FLAG_DECRYPTED;
1724 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1725 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1726 }
1727
95ea3627
ID		 1728 /*
1729 * Obtain the status about this packet.
89993890
ID		 1730 * When frame was received with an OFDM bitrate,
1731 * the signal is the PLCP value. If it was received with
1732 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1733 */
181d6902 1734 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1735 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1736 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1737
19d30e02
ID		 1738 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1739 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1740 else
1741 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1742 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1743 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1744
2ae23854 1745 /*
70a96109 1746 * Set skb pointers, and update frame information.
2ae23854 1747 */
70a96109 1748 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1749 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1750}
1751
1752/*
1753 * Device probe functions.
1754 */
1755static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1756{
1757 u16 word;
1758 u8 *mac;
1759 s8 value;
1760
1761 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1762
1763 /*
1764 * Start validation of the data that has been read.
1765 */
1766 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1767 if (!is_valid_ether_addr(mac)) {
f4f7f414 1768 eth_random_addr(mac);
ec9c4989 1769 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1770 }
1771
1772 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1773 if (word == 0xffff) {
1774 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1775 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1776 ANTENNA_B);
1777 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1778 ANTENNA_B);
95ea3627
ID		 1779 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1780 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1781 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1782 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1783 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
ec9c4989 1784 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
95ea3627
ID		 1785 }
1786
1787 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1788 if (word == 0xffff) {
1789 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1790 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
ec9c4989 1791 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
95ea3627
ID		 1792 }
1793
1794 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1795 if (word == 0xffff) {
1796 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1797 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1798 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1799 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1800 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1801 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1802 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1803 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1804 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1805 LED_MODE_DEFAULT);
1806 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
ec9c4989 1807 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
95ea3627
ID		 1808 }
1809
1810 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1811 if (word == 0xffff) {
1812 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1813 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1814 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 1815 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
95ea3627
ID		 1816 }
1817
1818 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1819 if (word == 0xffff) {
1820 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1821 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1822 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
ec9c4989 1823 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
95ea3627
ID		 1824 } else {
1825 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1826 if (value < -10 || value > 10)
1827 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1828 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1829 if (value < -10 || value > 10)
1830 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1831 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1832 }
1833
1834 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1835 if (word == 0xffff) {
1836 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1837 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1838 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
ec9c4989 1839 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1840 } else {
1841 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1842 if (value < -10 || value > 10)
1843 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1844 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1845 if (value < -10 || value > 10)
1846 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1847 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1848 }
1849
1850 return 0;
1851}
1852
1853static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1854{
1855 u32 reg;
1856 u16 value;
1857 u16 eeprom;
1858
1859 /*
1860 * Read EEPROM word for configuration.
1861 */
1862 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1863
1864 /*
1865 * Identify RF chipset.
1866 */
1867 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1868 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 1869 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1870 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 1871
49e721ec 1872 if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
ec9c4989 1873 rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n");
95ea3627
ID		 1874 return -ENODEV;
1875 }
1876
5122d898
GW		 1877 if (!rt2x00_rf(rt2x00dev, RF5226) &&
1878 !rt2x00_rf(rt2x00dev, RF2528) &&
1879 !rt2x00_rf(rt2x00dev, RF5225) &&
1880 !rt2x00_rf(rt2x00dev, RF2527)) {
ec9c4989 1881 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
95ea3627
ID		 1882 return -ENODEV;
1883 }
1884
1885 /*
1886 * Identify default antenna configuration.
1887 */
addc81bd 1888 rt2x00dev->default_ant.tx =
95ea3627 1889 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1890 rt2x00dev->default_ant.rx =
95ea3627
ID		 1891 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1892
1893 /*
1894 * Read the Frame type.
1895 */
1896 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
7dab73b3 1897 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
95ea3627 1898
7396faf4
ID		 1899 /*
1900 * Detect if this device has an hardware controlled radio.
1901 */
7396faf4 1902 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
7dab73b3 1903 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7396faf4 1904
95ea3627
ID		 1905 /*
1906 * Read frequency offset.
1907 */
1908 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1909 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1910
1911 /*
1912 * Read external LNA informations.
1913 */
1914 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1915
1916 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
7dab73b3
ID		 1917 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
1918 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
95ea3627
ID		 1919 }
1920
1921 /*
1922 * Store led settings, for correct led behaviour.
1923 */
771fd565 1924#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1925 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1926
475433be
ID		 1927 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1928 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1929 if (value == LED_MODE_SIGNAL_STRENGTH)
1930 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1931 LED_TYPE_QUALITY);
a9450b70
ID		 1932
1933 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1934 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1935 rt2x00_get_field16(eeprom,
1936 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1937 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1938 rt2x00_get_field16(eeprom,
1939 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1940 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1941 rt2x00_get_field16(eeprom,
1942 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1943 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1944 rt2x00_get_field16(eeprom,
1945 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1946 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1947 rt2x00_get_field16(eeprom,
1948 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1949 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1950 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1951 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1952 rt2x00_get_field16(eeprom,
1953 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1954 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1955 rt2x00_get_field16(eeprom,
1956 EEPROM_LED_POLARITY_RDY_A));
771fd565 1957#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1958
1959 return 0;
1960}
1961
1962/*
1963 * RF value list for RF2528
1964 * Supports: 2.4 GHz
1965 */
1966static const struct rf_channel rf_vals_bg_2528[] = {
1967 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1968 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1969 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1970 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1971 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1972 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1973 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1974 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1975 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1976 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1977 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1978 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1979 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1980 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1981};
1982
1983/*
1984 * RF value list for RF5226
1985 * Supports: 2.4 GHz & 5.2 GHz
1986 */
1987static const struct rf_channel rf_vals_5226[] = {
1988 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1989 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1990 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1991 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1992 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1993 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1994 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1995 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1996 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1997 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1998 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1999 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
2000 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
2001 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
2002
2003 /* 802.11 UNI / HyperLan 2 */
2004 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2005 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2006 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2007 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2008 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2009 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2010 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2011 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2012
2013 /* 802.11 HyperLan 2 */
2014 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2015 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2016 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2017 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2018 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2019 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2020 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2021 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2022 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2023 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2024
2025 /* 802.11 UNII */
2026 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2027 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2028 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2029 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2030 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2031 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2032
2033 /* MMAC(Japan)J52 ch 34,38,42,46 */
2034 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2035 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2036 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2037 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2038};
2039
2040/*
2041 * RF value list for RF5225 & RF2527
2042 * Supports: 2.4 GHz & 5.2 GHz
2043 */
2044static const struct rf_channel rf_vals_5225_2527[] = {
2045 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2046 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2047 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2048 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2049 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2050 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2051 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2052 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2053 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2054 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2055 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2056 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2057 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2058 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2059
2060 /* 802.11 UNI / HyperLan 2 */
2061 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2062 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2063 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2064 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2065 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2066 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2067 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2068 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2069
2070 /* 802.11 HyperLan 2 */
2071 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2072 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2073 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2074 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2075 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2076 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2077 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2078 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2079 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2080 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2081
2082 /* 802.11 UNII */
2083 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2084 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2085 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2086 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2087 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2088 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2089
2090 /* MMAC(Japan)J52 ch 34,38,42,46 */
2091 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2092 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2093 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2094 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2095};
2096
2097
8c5e7a5f 2098static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2099{
2100 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2101 struct channel_info *info;
2102 char *tx_power;
95ea3627
ID		 2103 unsigned int i;
2104
2105 /*
2106 * Initialize all hw fields.
5a5b6ed6 2107 *
30686bf7 2108 * Don't set IEEE80211_HOST_BROADCAST_PS_BUFFERING unless we are
5a5b6ed6
HS		 2109 * capable of sending the buffered frames out after the DTIM
2110 * transmission using rt2x00lib_beacondone. This will send out
2111 * multicast and broadcast traffic immediately instead of buffering it
2112 * infinitly and thus dropping it after some time.
95ea3627 2113 */
30686bf7
JB		 2114 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
2115 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
2116 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
95ea3627 2117
14a3bf89 2118 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2119 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2120 rt2x00_eeprom_addr(rt2x00dev,
2121 EEPROM_MAC_ADDR_0));
2122
95ea3627
ID		 2123 /*
2124 * Initialize hw_mode information.
2125 */
31562e80
ID		 2126 spec->supported_bands = SUPPORT_BAND_2GHZ;
2127 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 2128
5122d898 2129 if (rt2x00_rf(rt2x00dev, RF2528)) {
95ea3627
ID		 2130 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2131 spec->channels = rf_vals_bg_2528;
5122d898 2132 } else if (rt2x00_rf(rt2x00dev, RF5226)) {
31562e80 2133 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2134 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2135 spec->channels = rf_vals_5226;
5122d898 2136 } else if (rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 2137 spec->num_channels = 14;
2138 spec->channels = rf_vals_5225_2527;
5122d898 2139 } else if (rt2x00_rf(rt2x00dev, RF5225)) {
31562e80 2140 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2141 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2142 spec->channels = rf_vals_5225_2527;
2143 }
2144
8c5e7a5f
ID		 2145 /*
2146 * Create channel information array
2147 */
baeb2ffa 2148 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 2149 if (!info)
2150 return -ENOMEM;
95ea3627 2151
8c5e7a5f
ID		 2152 spec->channels_info = info;
2153
2154 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
8d1331b3
ID		 2155 for (i = 0; i < 14; i++) {
2156 info[i].max_power = MAX_TXPOWER;
2157 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2158 }
8c5e7a5f
ID		 2159
2160 if (spec->num_channels > 14) {
2161 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
8d1331b3
ID		 2162 for (i = 14; i < spec->num_channels; i++) {
2163 info[i].max_power = MAX_TXPOWER;
0a6f3a8e
GJ		 2164 info[i].default_power1 =
2165 TXPOWER_FROM_DEV(tx_power[i - 14]);
8d1331b3 2166 }
95ea3627 2167 }
8c5e7a5f
ID		 2168
2169 return 0;
95ea3627
ID		 2170}
2171
2172static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2173{
2174 int retval;
a396e100 2175 u32 reg;
95ea3627
ID		 2176
2177 /*
2178 * Allocate eeprom data.
2179 */
2180 retval = rt73usb_validate_eeprom(rt2x00dev);
2181 if (retval)
2182 return retval;
2183
2184 retval = rt73usb_init_eeprom(rt2x00dev);
2185 if (retval)
2186 return retval;
2187
a396e100
GW		 2188 /*
2189 * Enable rfkill polling by setting GPIO direction of the
2190 * rfkill switch GPIO pin correctly.
2191 */
2192 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
99bdf51a 2193 rt2x00_set_field32(&reg, MAC_CSR13_DIR7, 0);
a396e100
GW		 2194 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg);
2195
95ea3627
ID		 2196 /*
2197 * Initialize hw specifications.
2198 */
8c5e7a5f
ID		 2199 retval = rt73usb_probe_hw_mode(rt2x00dev);
2200 if (retval)
2201 return retval;
95ea3627 2202
1afcfd54
IP		 2203 /*
2204 * This device has multiple filters for control frames,
2205 * but has no a separate filter for PS Poll frames.
2206 */
7dab73b3 2207 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
1afcfd54 2208
95ea3627 2209 /*
9404ef34 2210 * This device requires firmware.
95ea3627 2211 */
7dab73b3 2212 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
008c4482 2213 if (!modparam_nohwcrypt)
7dab73b3
ID		 2214 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2215 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1c0bcf89 2216 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
95ea3627
ID		 2217
2218 /*
2219 * Set the rssi offset.
2220 */
2221 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2222
2223 return 0;
2224}
2225
2226/*
2227 * IEEE80211 stack callback functions.
2228 */
8a3a3c85
EP		 2229static int rt73usb_conf_tx(struct ieee80211_hw *hw,
2230 struct ieee80211_vif *vif, u16 queue_idx,
2af0a570
ID		 2231 const struct ieee80211_tx_queue_params *params)
2232{
2233 struct rt2x00_dev *rt2x00dev = hw->priv;
2234 struct data_queue *queue;
2235 struct rt2x00_field32 field;
2236 int retval;
2237 u32 reg;
5e790023 2238 u32 offset;
2af0a570
ID		 2239
2240 /*
2241 * First pass the configuration through rt2x00lib, that will
2242 * update the queue settings and validate the input. After that
2243 * we are free to update the registers based on the value
2244 * in the queue parameter.
2245 */
8a3a3c85 2246 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2af0a570
ID		 2247 if (retval)
2248 return retval;
2249
5e790023
ID		 2250 /*
2251 * We only need to perform additional register initialization
2252 * for WMM queues/
2253 */
2254 if (queue_idx >= 4)
2255 return 0;
2256
11f818e0 2257 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2af0a570
ID		 2258
2259 /* Update WMM TXOP register */
5e790023
ID		 2260 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2261 field.bit_offset = (queue_idx & 1) * 16;
2262 field.bit_mask = 0xffff << field.bit_offset;
2263
2264 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2265 rt2x00_set_field32(&reg, field, queue->txop);
2266 rt2x00usb_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2267
2268 /* Update WMM registers */
2269 field.bit_offset = queue_idx * 4;
2270 field.bit_mask = 0xf << field.bit_offset;
2271
0f829b1d 2272 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2273 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2274 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2275
0f829b1d 2276 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2277 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2278 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2279
0f829b1d 2280 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2281 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2282 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2283
2284 return 0;
2285}
2286
37a41b4a 2287static u64 rt73usb_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
95ea3627
ID		 2288{
2289 struct rt2x00_dev *rt2x00dev = hw->priv;
2290 u64 tsf;
2291 u32 reg;
2292
0f829b1d 2293 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2294 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2295 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2296 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2297
2298 return tsf;
2299}
95ea3627 2300
95ea3627
ID		 2301static const struct ieee80211_ops rt73usb_mac80211_ops = {
2302 .tx = rt2x00mac_tx,
4150c572
JB		 2303 .start = rt2x00mac_start,
2304 .stop = rt2x00mac_stop,
95ea3627
ID		 2305 .add_interface = rt2x00mac_add_interface,
2306 .remove_interface = rt2x00mac_remove_interface,
2307 .config = rt2x00mac_config,
3a643d24 2308 .configure_filter = rt2x00mac_configure_filter,
930c06f2 2309 .set_tim = rt2x00mac_set_tim,
906c110f 2310 .set_key = rt2x00mac_set_key,
d8147f9d
ID		 2311 .sw_scan_start = rt2x00mac_sw_scan_start,
2312 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2313 .get_stats = rt2x00mac_get_stats,
471b3efd 2314 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2315 .conf_tx = rt73usb_conf_tx,
95ea3627 2316 .get_tsf = rt73usb_get_tsf,
e47a5cdd 2317 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 2318 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 2319 .set_antenna = rt2x00mac_set_antenna,
2320 .get_antenna = rt2x00mac_get_antenna,
e7dee444 2321 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 2322 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 2323};
2324
2325static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2326 .probe_hw = rt73usb_probe_hw,
2327 .get_firmware_name = rt73usb_get_firmware_name,
0cbe0064 2328 .check_firmware = rt73usb_check_firmware,
95ea3627
ID		 2329 .load_firmware = rt73usb_load_firmware,
2330 .initialize = rt2x00usb_initialize,
2331 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2332 .clear_entry = rt2x00usb_clear_entry,
95ea3627 2333 .set_device_state = rt73usb_set_device_state,
7396faf4 2334 .rfkill_poll = rt73usb_rfkill_poll,
95ea3627
ID		 2335 .link_stats = rt73usb_link_stats,
2336 .reset_tuner = rt73usb_reset_tuner,
2337 .link_tuner = rt73usb_link_tuner,
c965c74b 2338 .watchdog = rt2x00usb_watchdog,
dbba306f
ID		 2339 .start_queue = rt73usb_start_queue,
2340 .kick_queue = rt2x00usb_kick_queue,
2341 .stop_queue = rt73usb_stop_queue,
5be65609 2342 .flush_queue = rt2x00usb_flush_queue,
95ea3627 2343 .write_tx_desc = rt73usb_write_tx_desc,
bd88a781 2344 .write_beacon = rt73usb_write_beacon,
69cf36a4 2345 .clear_beacon = rt73usb_clear_beacon,
dd9fa2d2 2346 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627 2347 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2348 .config_shared_key = rt73usb_config_shared_key,
2349 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2350 .config_filter = rt73usb_config_filter,
6bb40dd1 2351 .config_intf = rt73usb_config_intf,
72810379 2352 .config_erp = rt73usb_config_erp,
e4ea1c40 2353 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2354 .config = rt73usb_config,
2355};
2356
0d7aada3
GJ		 2357static void rt73usb_queue_init(struct data_queue *queue)
2358{
2359 switch (queue->qid) {
2360 case QID_RX:
2361 queue->limit = 32;
2362 queue->data_size = DATA_FRAME_SIZE;
2363 queue->desc_size = RXD_DESC_SIZE;
2364 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2365 break;
181d6902 2366
0d7aada3
GJ		 2367 case QID_AC_VO:
2368 case QID_AC_VI:
2369 case QID_AC_BE:
2370 case QID_AC_BK:
2371 queue->limit = 32;
2372 queue->data_size = DATA_FRAME_SIZE;
2373 queue->desc_size = TXD_DESC_SIZE;
2374 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2375 break;
181d6902 2376
0d7aada3
GJ		 2377 case QID_BEACON:
2378 queue->limit = 4;
2379 queue->data_size = MGMT_FRAME_SIZE;
2380 queue->desc_size = TXINFO_SIZE;
2381 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2382 break;
2383
2384 case QID_ATIM:
2385 /* fallthrough */
2386 default:
2387 BUG();
2388 break;
2389 }
2390}
181d6902 2391
95ea3627 2392static const struct rt2x00_ops rt73usb_ops = {
04d0362e 2393 .name = KBUILD_MODNAME,
04d0362e
GW		 2394 .max_ap_intf = 4,
2395 .eeprom_size = EEPROM_SIZE,
2396 .rf_size = RF_SIZE,
2397 .tx_queues = NUM_TX_QUEUES,
0d7aada3 2398 .queue_init = rt73usb_queue_init,
04d0362e
GW		 2399 .lib = &rt73usb_rt2x00_ops,
2400 .hw = &rt73usb_mac80211_ops,
95ea3627 2401#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2402 .debugfs = &rt73usb_rt2x00debug,
95ea3627
ID		 2403#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2404};
2405
2406/*
2407 * rt73usb module information.
2408 */
2409static struct usb_device_id rt73usb_device_table[] = {
2410 /* AboCom */
e01ae27f
GW		 2411 { USB_DEVICE(0x07b8, 0xb21b) },
2412 { USB_DEVICE(0x07b8, 0xb21c) },
2413 { USB_DEVICE(0x07b8, 0xb21d) },
2414 { USB_DEVICE(0x07b8, 0xb21e) },
2415 { USB_DEVICE(0x07b8, 0xb21f) },
ef4bb70d 2416 /* AL */
e01ae27f 2417 { USB_DEVICE(0x14b2, 0x3c10) },
144d9ad9 2418 /* Amigo */
e01ae27f
GW		 2419 { USB_DEVICE(0x148f, 0x9021) },
2420 { USB_DEVICE(0x0eb0, 0x9021) },
ef4bb70d 2421 /* AMIT */
e01ae27f 2422 { USB_DEVICE(0x18c5, 0x0002) },
95ea3627 2423 /* Askey */
e01ae27f 2424 { USB_DEVICE(0x1690, 0x0722) },
95ea3627 2425 /* ASUS */
e01ae27f
GW		 2426 { USB_DEVICE(0x0b05, 0x1723) },
2427 { USB_DEVICE(0x0b05, 0x1724) },
95ea3627 2428 /* Belkin */
8f35f787 2429 { USB_DEVICE(0x050d, 0x7050) }, /* FCC ID: K7SF5D7050B ver. 3.x */
e01ae27f
GW		 2430 { USB_DEVICE(0x050d, 0x705a) },
2431 { USB_DEVICE(0x050d, 0x905b) },
2432 { USB_DEVICE(0x050d, 0x905c) },
95ea3627 2433 /* Billionton */
e01ae27f
GW		 2434 { USB_DEVICE(0x1631, 0xc019) },
2435 { USB_DEVICE(0x08dd, 0x0120) },
95ea3627 2436 /* Buffalo */
e01ae27f
GW		 2437 { USB_DEVICE(0x0411, 0x00d8) },
2438 { USB_DEVICE(0x0411, 0x00d9) },
b8b1ec61 2439 { USB_DEVICE(0x0411, 0x00e6) },
e01ae27f
GW		 2440 { USB_DEVICE(0x0411, 0x00f4) },
2441 { USB_DEVICE(0x0411, 0x0116) },
2442 { USB_DEVICE(0x0411, 0x0119) },
2443 { USB_DEVICE(0x0411, 0x0137) },
51b2853f 2444 /* CEIVA */
e01ae27f 2445 { USB_DEVICE(0x178d, 0x02be) },
95ea3627 2446 /* CNet */
e01ae27f
GW		 2447 { USB_DEVICE(0x1371, 0x9022) },
2448 { USB_DEVICE(0x1371, 0x9032) },
95ea3627 2449 /* Conceptronic */
e01ae27f 2450 { USB_DEVICE(0x14b2, 0x3c22) },
0a74892b 2451 /* Corega */
e01ae27f 2452 { USB_DEVICE(0x07aa, 0x002e) },
95ea3627 2453 /* D-Link */
e01ae27f
GW		 2454 { USB_DEVICE(0x07d1, 0x3c03) },
2455 { USB_DEVICE(0x07d1, 0x3c04) },
2456 { USB_DEVICE(0x07d1, 0x3c06) },
2457 { USB_DEVICE(0x07d1, 0x3c07) },
ef4bb70d 2458 /* Edimax */
e01ae27f
GW		 2459 { USB_DEVICE(0x7392, 0x7318) },
2460 { USB_DEVICE(0x7392, 0x7618) },
ef4bb70d 2461 /* EnGenius */
e01ae27f 2462 { USB_DEVICE(0x1740, 0x3701) },
95ea3627 2463 /* Gemtek */
e01ae27f 2464 { USB_DEVICE(0x15a9, 0x0004) },
95ea3627 2465 /* Gigabyte */
e01ae27f
GW		 2466 { USB_DEVICE(0x1044, 0x8008) },
2467 { USB_DEVICE(0x1044, 0x800a) },
95ea3627 2468 /* Huawei-3Com */
e01ae27f 2469 { USB_DEVICE(0x1472, 0x0009) },
95ea3627 2470 /* Hercules */
e01ae27f
GW		 2471 { USB_DEVICE(0x06f8, 0xe002) },
2472 { USB_DEVICE(0x06f8, 0xe010) },
2473 { USB_DEVICE(0x06f8, 0xe020) },
95ea3627 2474 /* Linksys */
e01ae27f
GW		 2475 { USB_DEVICE(0x13b1, 0x0020) },
2476 { USB_DEVICE(0x13b1, 0x0023) },
2477 { USB_DEVICE(0x13b1, 0x0028) },
95ea3627 2478 /* MSI */
e01ae27f
GW		 2479 { USB_DEVICE(0x0db0, 0x4600) },
2480 { USB_DEVICE(0x0db0, 0x6877) },
2481 { USB_DEVICE(0x0db0, 0x6874) },
2482 { USB_DEVICE(0x0db0, 0xa861) },
2483 { USB_DEVICE(0x0db0, 0xa874) },
22720645 2484 /* Ovislink */
e01ae27f 2485 { USB_DEVICE(0x1b75, 0x7318) },
95ea3627 2486 /* Ralink */
e01ae27f
GW		 2487 { USB_DEVICE(0x04bb, 0x093d) },
2488 { USB_DEVICE(0x148f, 0x2573) },
2489 { USB_DEVICE(0x148f, 0x2671) },
2490 { USB_DEVICE(0x0812, 0x3101) },
95ea3627 2491 /* Qcom */
e01ae27f
GW		 2492 { USB_DEVICE(0x18e8, 0x6196) },
2493 { USB_DEVICE(0x18e8, 0x6229) },
2494 { USB_DEVICE(0x18e8, 0x6238) },
ef4bb70d 2495 /* Samsung */
e01ae27f 2496 { USB_DEVICE(0x04e8, 0x4471) },
95ea3627 2497 /* Senao */
e01ae27f 2498 { USB_DEVICE(0x1740, 0x7100) },
95ea3627 2499 /* Sitecom */
e01ae27f
GW		 2500 { USB_DEVICE(0x0df6, 0x0024) },
2501 { USB_DEVICE(0x0df6, 0x0027) },
2502 { USB_DEVICE(0x0df6, 0x002f) },
2503 { USB_DEVICE(0x0df6, 0x90ac) },
2504 { USB_DEVICE(0x0df6, 0x9712) },
95ea3627 2505 /* Surecom */
e01ae27f 2506 { USB_DEVICE(0x0769, 0x31f3) },
14344b81 2507 /* Tilgin */
e01ae27f 2508 { USB_DEVICE(0x6933, 0x5001) },
ef4bb70d 2509 /* Philips */
e01ae27f 2510 { USB_DEVICE(0x0471, 0x200a) },
95ea3627 2511 /* Planex */
e01ae27f
GW		 2512 { USB_DEVICE(0x2019, 0xab01) },
2513 { USB_DEVICE(0x2019, 0xab50) },
22720645 2514 /* WideTell */
e01ae27f 2515 { USB_DEVICE(0x7167, 0x3840) },
ef4bb70d 2516 /* Zcom */
e01ae27f 2517 { USB_DEVICE(0x0cde, 0x001c) },
144d9ad9 2518 /* ZyXEL */
e01ae27f 2519 { USB_DEVICE(0x0586, 0x3415) },
95ea3627
ID		 2520 { 0, }
2521};
2522
2523MODULE_AUTHOR(DRV_PROJECT);
2524MODULE_VERSION(DRV_VERSION);
2525MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2526MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2527MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2528MODULE_FIRMWARE(FIRMWARE_RT2571);
2529MODULE_LICENSE("GPL");
2530
e01ae27f
GW		 2531static int rt73usb_probe(struct usb_interface *usb_intf,
2532 const struct usb_device_id *id)
2533{
2534 return rt2x00usb_probe(usb_intf, &rt73usb_ops);
2535}
2536
95ea3627 2537static struct usb_driver rt73usb_driver = {
2360157c 2538 .name = KBUILD_MODNAME,
95ea3627 2539 .id_table = rt73usb_device_table,
e01ae27f 2540 .probe = rt73usb_probe,
95ea3627
ID		 2541 .disconnect = rt2x00usb_disconnect,
2542 .suspend = rt2x00usb_suspend,
2543 .resume = rt2x00usb_resume,
761ce8c4 2544 .reset_resume = rt2x00usb_resume,
e1f12eb6 2545 .disable_hub_initiated_lpm = 1,
95ea3627
ID		 2546};
2547
d632eb1b 2548module_usb_driver(rt73usb_driver);
Linux 6.x block layer and io_uring tree(s)