Commit | Line | Data |
---|---|---|
95ea3627 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt73usb | |
23 | Abstract: rt73usb device specific routines. | |
24 | Supported chipsets: rt2571W & rt2671. | |
25 | */ | |
26 | ||
a7f3a06c | 27 | #include <linux/crc-itu-t.h> |
95ea3627 ID |
28 | #include <linux/delay.h> |
29 | #include <linux/etherdevice.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
95ea3627 ID |
34 | #include <linux/usb.h> |
35 | ||
36 | #include "rt2x00.h" | |
37 | #include "rt2x00usb.h" | |
38 | #include "rt73usb.h" | |
39 | ||
008c4482 ID |
40 | /* |
41 | * Allow hardware encryption to be disabled. | |
42 | */ | |
821cde63 | 43 | static int modparam_nohwcrypt; |
008c4482 ID |
44 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
45 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); | |
46 | ||
95ea3627 ID |
47 | /* |
48 | * Register access. | |
49 | * All access to the CSR registers will go through the methods | |
0f829b1d | 50 | * rt2x00usb_register_read and rt2x00usb_register_write. |
95ea3627 ID |
51 | * BBP and RF register require indirect register access, |
52 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
53 | * These indirect registers work with busy bits, | |
54 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
55 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
56 | * between each attampt. When the busy bit is still set at that time, | |
57 | * the access attempt is considered to have failed, | |
58 | * and we will print an error. | |
8ff48a8b | 59 | * The _lock versions must be used if you already hold the csr_mutex |
95ea3627 | 60 | */ |
c9c3b1a5 | 61 | #define WAIT_FOR_BBP(__dev, __reg) \ |
0f829b1d | 62 | rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) |
c9c3b1a5 | 63 | #define WAIT_FOR_RF(__dev, __reg) \ |
0f829b1d | 64 | rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) |
c9c3b1a5 | 65 | |
0e14f6d3 | 66 | static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
67 | const unsigned int word, const u8 value) |
68 | { | |
69 | u32 reg; | |
70 | ||
8ff48a8b | 71 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 72 | |
95ea3627 | 73 | /* |
c9c3b1a5 ID |
74 | * Wait until the BBP becomes available, afterwards we |
75 | * can safely write the new data into the register. | |
95ea3627 | 76 | */ |
c9c3b1a5 ID |
77 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
78 | reg = 0; | |
79 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); | |
80 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
81 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
82 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); | |
83 | ||
0f829b1d | 84 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); |
c9c3b1a5 | 85 | } |
99ade259 | 86 | |
8ff48a8b | 87 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
88 | } |
89 | ||
0e14f6d3 | 90 | static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
91 | const unsigned int word, u8 *value) |
92 | { | |
93 | u32 reg; | |
94 | ||
8ff48a8b | 95 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 96 | |
95ea3627 | 97 | /* |
c9c3b1a5 ID |
98 | * Wait until the BBP becomes available, afterwards we |
99 | * can safely write the read request into the register. | |
100 | * After the data has been written, we wait until hardware | |
101 | * returns the correct value, if at any time the register | |
102 | * doesn't become available in time, reg will be 0xffffffff | |
103 | * which means we return 0xff to the caller. | |
95ea3627 | 104 | */ |
c9c3b1a5 ID |
105 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
106 | reg = 0; | |
107 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
108 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
109 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); | |
95ea3627 | 110 | |
0f829b1d | 111 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); |
95ea3627 | 112 | |
c9c3b1a5 ID |
113 | WAIT_FOR_BBP(rt2x00dev, ®); |
114 | } | |
95ea3627 ID |
115 | |
116 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); | |
99ade259 | 117 | |
8ff48a8b | 118 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
119 | } |
120 | ||
0e14f6d3 | 121 | static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
122 | const unsigned int word, const u32 value) |
123 | { | |
124 | u32 reg; | |
95ea3627 | 125 | |
8ff48a8b | 126 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 127 | |
4f5af6eb | 128 | /* |
c9c3b1a5 ID |
129 | * Wait until the RF becomes available, afterwards we |
130 | * can safely write the new data into the register. | |
4f5af6eb | 131 | */ |
c9c3b1a5 ID |
132 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
133 | reg = 0; | |
134 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); | |
135 | /* | |
136 | * RF5225 and RF2527 contain 21 bits per RF register value, | |
137 | * all others contain 20 bits. | |
138 | */ | |
139 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, | |
5122d898 GW |
140 | 20 + (rt2x00_rf(rt2x00dev, RF5225) || |
141 | rt2x00_rf(rt2x00dev, RF2527))); | |
c9c3b1a5 ID |
142 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); |
143 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); | |
144 | ||
0f829b1d | 145 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); |
c9c3b1a5 ID |
146 | rt2x00_rf_write(rt2x00dev, word, value); |
147 | } | |
8ff48a8b ID |
148 | |
149 | mutex_unlock(&rt2x00dev->csr_mutex); | |
95ea3627 ID |
150 | } |
151 | ||
152 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
95ea3627 ID |
153 | static const struct rt2x00debug rt73usb_rt2x00debug = { |
154 | .owner = THIS_MODULE, | |
155 | .csr = { | |
0f829b1d ID |
156 | .read = rt2x00usb_register_read, |
157 | .write = rt2x00usb_register_write, | |
743b97ca ID |
158 | .flags = RT2X00DEBUGFS_OFFSET, |
159 | .word_base = CSR_REG_BASE, | |
95ea3627 ID |
160 | .word_size = sizeof(u32), |
161 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
162 | }, | |
163 | .eeprom = { | |
164 | .read = rt2x00_eeprom_read, | |
165 | .write = rt2x00_eeprom_write, | |
743b97ca | 166 | .word_base = EEPROM_BASE, |
95ea3627 ID |
167 | .word_size = sizeof(u16), |
168 | .word_count = EEPROM_SIZE / sizeof(u16), | |
169 | }, | |
170 | .bbp = { | |
171 | .read = rt73usb_bbp_read, | |
172 | .write = rt73usb_bbp_write, | |
743b97ca | 173 | .word_base = BBP_BASE, |
95ea3627 ID |
174 | .word_size = sizeof(u8), |
175 | .word_count = BBP_SIZE / sizeof(u8), | |
176 | }, | |
177 | .rf = { | |
178 | .read = rt2x00_rf_read, | |
179 | .write = rt73usb_rf_write, | |
743b97ca | 180 | .word_base = RF_BASE, |
95ea3627 ID |
181 | .word_size = sizeof(u32), |
182 | .word_count = RF_SIZE / sizeof(u32), | |
183 | }, | |
184 | }; | |
185 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
186 | ||
7396faf4 ID |
187 | static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
188 | { | |
189 | u32 reg; | |
190 | ||
191 | rt2x00usb_register_read(rt2x00dev, MAC_CSR13, ®); | |
192 | return rt2x00_get_field32(reg, MAC_CSR13_BIT7); | |
193 | } | |
7396faf4 | 194 | |
771fd565 | 195 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 196 | static void rt73usb_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
197 | enum led_brightness brightness) |
198 | { | |
199 | struct rt2x00_led *led = | |
200 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
201 | unsigned int enabled = brightness != LED_OFF; | |
202 | unsigned int a_mode = | |
203 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | |
204 | unsigned int bg_mode = | |
205 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
206 | ||
207 | if (led->type == LED_TYPE_RADIO) { | |
208 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
209 | MCU_LEDCS_RADIO_STATUS, enabled); | |
210 | ||
47b10cd1 ID |
211 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
212 | 0, led->rt2x00dev->led_mcu_reg, | |
213 | REGISTER_TIMEOUT); | |
a9450b70 ID |
214 | } else if (led->type == LED_TYPE_ASSOC) { |
215 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
216 | MCU_LEDCS_LINK_BG_STATUS, bg_mode); | |
217 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
218 | MCU_LEDCS_LINK_A_STATUS, a_mode); | |
219 | ||
47b10cd1 ID |
220 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
221 | 0, led->rt2x00dev->led_mcu_reg, | |
222 | REGISTER_TIMEOUT); | |
a9450b70 ID |
223 | } else if (led->type == LED_TYPE_QUALITY) { |
224 | /* | |
225 | * The brightness is divided into 6 levels (0 - 5), | |
226 | * this means we need to convert the brightness | |
227 | * argument into the matching level within that range. | |
228 | */ | |
47b10cd1 ID |
229 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
230 | brightness / (LED_FULL / 6), | |
231 | led->rt2x00dev->led_mcu_reg, | |
232 | REGISTER_TIMEOUT); | |
a9450b70 ID |
233 | } |
234 | } | |
a2e1d52a ID |
235 | |
236 | static int rt73usb_blink_set(struct led_classdev *led_cdev, | |
237 | unsigned long *delay_on, | |
238 | unsigned long *delay_off) | |
239 | { | |
240 | struct rt2x00_led *led = | |
241 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
242 | u32 reg; | |
243 | ||
0f829b1d | 244 | rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, ®); |
a2e1d52a ID |
245 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); |
246 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); | |
0f829b1d | 247 | rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg); |
a2e1d52a ID |
248 | |
249 | return 0; | |
250 | } | |
475433be ID |
251 | |
252 | static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev, | |
253 | struct rt2x00_led *led, | |
254 | enum led_type type) | |
255 | { | |
256 | led->rt2x00dev = rt2x00dev; | |
257 | led->type = type; | |
258 | led->led_dev.brightness_set = rt73usb_brightness_set; | |
259 | led->led_dev.blink_set = rt73usb_blink_set; | |
260 | led->flags = LED_INITIALIZED; | |
261 | } | |
771fd565 | 262 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 263 | |
95ea3627 ID |
264 | /* |
265 | * Configuration handlers. | |
266 | */ | |
906c110f ID |
267 | static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev, |
268 | struct rt2x00lib_crypto *crypto, | |
269 | struct ieee80211_key_conf *key) | |
270 | { | |
271 | struct hw_key_entry key_entry; | |
272 | struct rt2x00_field32 field; | |
906c110f ID |
273 | u32 mask; |
274 | u32 reg; | |
275 | ||
276 | if (crypto->cmd == SET_KEY) { | |
277 | /* | |
278 | * rt2x00lib can't determine the correct free | |
279 | * key_idx for shared keys. We have 1 register | |
280 | * with key valid bits. The goal is simple, read | |
281 | * the register, if that is full we have no slots | |
282 | * left. | |
283 | * Note that each BSS is allowed to have up to 4 | |
284 | * shared keys, so put a mask over the allowed | |
285 | * entries. | |
286 | */ | |
287 | mask = (0xf << crypto->bssidx); | |
288 | ||
0f829b1d | 289 | rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); |
906c110f ID |
290 | reg &= mask; |
291 | ||
292 | if (reg && reg == mask) | |
293 | return -ENOSPC; | |
294 | ||
acaf908d | 295 | key->hw_key_idx += reg ? ffz(reg) : 0; |
906c110f ID |
296 | |
297 | /* | |
298 | * Upload key to hardware | |
299 | */ | |
300 | memcpy(key_entry.key, crypto->key, | |
301 | sizeof(key_entry.key)); | |
302 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
303 | sizeof(key_entry.tx_mic)); | |
304 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
305 | sizeof(key_entry.rx_mic)); | |
306 | ||
307 | reg = SHARED_KEY_ENTRY(key->hw_key_idx); | |
96b61baf GW |
308 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
309 | &key_entry, sizeof(key_entry)); | |
906c110f ID |
310 | |
311 | /* | |
312 | * The cipher types are stored over 2 registers. | |
313 | * bssidx 0 and 1 keys are stored in SEC_CSR1 and | |
314 | * bssidx 1 and 2 keys are stored in SEC_CSR5. | |
315 | * Using the correct defines correctly will cause overhead, | |
316 | * so just calculate the correct offset. | |
317 | */ | |
318 | if (key->hw_key_idx < 8) { | |
319 | field.bit_offset = (3 * key->hw_key_idx); | |
320 | field.bit_mask = 0x7 << field.bit_offset; | |
321 | ||
0f829b1d | 322 | rt2x00usb_register_read(rt2x00dev, SEC_CSR1, ®); |
906c110f | 323 | rt2x00_set_field32(®, field, crypto->cipher); |
0f829b1d | 324 | rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg); |
906c110f ID |
325 | } else { |
326 | field.bit_offset = (3 * (key->hw_key_idx - 8)); | |
327 | field.bit_mask = 0x7 << field.bit_offset; | |
328 | ||
0f829b1d | 329 | rt2x00usb_register_read(rt2x00dev, SEC_CSR5, ®); |
906c110f | 330 | rt2x00_set_field32(®, field, crypto->cipher); |
0f829b1d | 331 | rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg); |
906c110f ID |
332 | } |
333 | ||
334 | /* | |
335 | * The driver does not support the IV/EIV generation | |
336 | * in hardware. However it doesn't support the IV/EIV | |
337 | * inside the ieee80211 frame either, but requires it | |
3ad2f3fb | 338 | * to be provided separately for the descriptor. |
906c110f ID |
339 | * rt2x00lib will cut the IV/EIV data out of all frames |
340 | * given to us by mac80211, but we must tell mac80211 | |
341 | * to generate the IV/EIV data. | |
342 | */ | |
343 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
344 | } | |
345 | ||
346 | /* | |
347 | * SEC_CSR0 contains only single-bit fields to indicate | |
348 | * a particular key is valid. Because using the FIELD32() | |
349 | * defines directly will cause a lot of overhead we use | |
350 | * a calculation to determine the correct bit directly. | |
351 | */ | |
352 | mask = 1 << key->hw_key_idx; | |
353 | ||
0f829b1d | 354 | rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); |
906c110f ID |
355 | if (crypto->cmd == SET_KEY) |
356 | reg |= mask; | |
357 | else if (crypto->cmd == DISABLE_KEY) | |
358 | reg &= ~mask; | |
0f829b1d | 359 | rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg); |
906c110f ID |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |
365 | struct rt2x00lib_crypto *crypto, | |
366 | struct ieee80211_key_conf *key) | |
367 | { | |
368 | struct hw_pairwise_ta_entry addr_entry; | |
369 | struct hw_key_entry key_entry; | |
906c110f ID |
370 | u32 mask; |
371 | u32 reg; | |
372 | ||
373 | if (crypto->cmd == SET_KEY) { | |
374 | /* | |
375 | * rt2x00lib can't determine the correct free | |
376 | * key_idx for pairwise keys. We have 2 registers | |
377 | * with key valid bits. The goal is simple, read | |
378 | * the first register, if that is full move to | |
379 | * the next register. | |
380 | * When both registers are full, we drop the key, | |
381 | * otherwise we use the first invalid entry. | |
382 | */ | |
0f829b1d | 383 | rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); |
906c110f ID |
384 | if (reg && reg == ~0) { |
385 | key->hw_key_idx = 32; | |
0f829b1d | 386 | rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); |
906c110f ID |
387 | if (reg && reg == ~0) |
388 | return -ENOSPC; | |
389 | } | |
390 | ||
acaf908d | 391 | key->hw_key_idx += reg ? ffz(reg) : 0; |
906c110f ID |
392 | |
393 | /* | |
394 | * Upload key to hardware | |
395 | */ | |
396 | memcpy(key_entry.key, crypto->key, | |
397 | sizeof(key_entry.key)); | |
398 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
399 | sizeof(key_entry.tx_mic)); | |
400 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
401 | sizeof(key_entry.rx_mic)); | |
402 | ||
403 | reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
96b61baf GW |
404 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
405 | &key_entry, sizeof(key_entry)); | |
906c110f ID |
406 | |
407 | /* | |
408 | * Send the address and cipher type to the hardware register. | |
906c110f ID |
409 | */ |
410 | memset(&addr_entry, 0, sizeof(addr_entry)); | |
411 | memcpy(&addr_entry, crypto->address, ETH_ALEN); | |
412 | addr_entry.cipher = crypto->cipher; | |
413 | ||
414 | reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); | |
0f829b1d | 415 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
906c110f ID |
416 | &addr_entry, sizeof(addr_entry)); |
417 | ||
418 | /* | |
419 | * Enable pairwise lookup table for given BSS idx, | |
420 | * without this received frames will not be decrypted | |
421 | * by the hardware. | |
422 | */ | |
0f829b1d | 423 | rt2x00usb_register_read(rt2x00dev, SEC_CSR4, ®); |
906c110f | 424 | reg |= (1 << crypto->bssidx); |
0f829b1d | 425 | rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg); |
906c110f ID |
426 | |
427 | /* | |
428 | * The driver does not support the IV/EIV generation | |
429 | * in hardware. However it doesn't support the IV/EIV | |
430 | * inside the ieee80211 frame either, but requires it | |
3ad2f3fb | 431 | * to be provided separately for the descriptor. |
906c110f ID |
432 | * rt2x00lib will cut the IV/EIV data out of all frames |
433 | * given to us by mac80211, but we must tell mac80211 | |
434 | * to generate the IV/EIV data. | |
435 | */ | |
436 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
437 | } | |
438 | ||
439 | /* | |
440 | * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate | |
441 | * a particular key is valid. Because using the FIELD32() | |
442 | * defines directly will cause a lot of overhead we use | |
443 | * a calculation to determine the correct bit directly. | |
444 | */ | |
445 | if (key->hw_key_idx < 32) { | |
446 | mask = 1 << key->hw_key_idx; | |
447 | ||
0f829b1d | 448 | rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); |
906c110f ID |
449 | if (crypto->cmd == SET_KEY) |
450 | reg |= mask; | |
451 | else if (crypto->cmd == DISABLE_KEY) | |
452 | reg &= ~mask; | |
0f829b1d | 453 | rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg); |
906c110f ID |
454 | } else { |
455 | mask = 1 << (key->hw_key_idx - 32); | |
456 | ||
0f829b1d | 457 | rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); |
906c110f ID |
458 | if (crypto->cmd == SET_KEY) |
459 | reg |= mask; | |
460 | else if (crypto->cmd == DISABLE_KEY) | |
461 | reg &= ~mask; | |
0f829b1d | 462 | rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg); |
906c110f ID |
463 | } |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
3a643d24 ID |
468 | static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev, |
469 | const unsigned int filter_flags) | |
470 | { | |
471 | u32 reg; | |
472 | ||
473 | /* | |
474 | * Start configuration steps. | |
475 | * Note that the version error will always be dropped | |
476 | * and broadcast frames will always be accepted since | |
477 | * there is no filter for it at this time. | |
478 | */ | |
0f829b1d | 479 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
3a643d24 ID |
480 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, |
481 | !(filter_flags & FIF_FCSFAIL)); | |
482 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, | |
483 | !(filter_flags & FIF_PLCPFAIL)); | |
484 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, | |
1afcfd54 | 485 | !(filter_flags & (FIF_CONTROL | FIF_PSPOLL))); |
3a643d24 ID |
486 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, |
487 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
488 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, | |
e0b005fa ID |
489 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
490 | !rt2x00dev->intf_ap_count); | |
3a643d24 ID |
491 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); |
492 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, | |
493 | !(filter_flags & FIF_ALLMULTI)); | |
494 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); | |
495 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, | |
496 | !(filter_flags & FIF_CONTROL)); | |
0f829b1d | 497 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
3a643d24 ID |
498 | } |
499 | ||
6bb40dd1 ID |
500 | static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev, |
501 | struct rt2x00_intf *intf, | |
502 | struct rt2x00intf_conf *conf, | |
503 | const unsigned int flags) | |
95ea3627 | 504 | { |
6bb40dd1 | 505 | u32 reg; |
95ea3627 | 506 | |
6bb40dd1 | 507 | if (flags & CONFIG_UPDATE_TYPE) { |
6bb40dd1 ID |
508 | /* |
509 | * Enable synchronisation. | |
510 | */ | |
0f829b1d | 511 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
6bb40dd1 | 512 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); |
0f829b1d | 513 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
6bb40dd1 | 514 | } |
95ea3627 | 515 | |
6bb40dd1 ID |
516 | if (flags & CONFIG_UPDATE_MAC) { |
517 | reg = le32_to_cpu(conf->mac[1]); | |
518 | rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); | |
519 | conf->mac[1] = cpu_to_le32(reg); | |
95ea3627 | 520 | |
0f829b1d | 521 | rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2, |
6bb40dd1 ID |
522 | conf->mac, sizeof(conf->mac)); |
523 | } | |
95ea3627 | 524 | |
6bb40dd1 ID |
525 | if (flags & CONFIG_UPDATE_BSSID) { |
526 | reg = le32_to_cpu(conf->bssid[1]); | |
527 | rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); | |
528 | conf->bssid[1] = cpu_to_le32(reg); | |
95ea3627 | 529 | |
0f829b1d | 530 | rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4, |
6bb40dd1 ID |
531 | conf->bssid, sizeof(conf->bssid)); |
532 | } | |
95ea3627 ID |
533 | } |
534 | ||
3a643d24 | 535 | static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev, |
02044643 HS |
536 | struct rt2x00lib_erp *erp, |
537 | u32 changed) | |
95ea3627 | 538 | { |
95ea3627 | 539 | u32 reg; |
95ea3627 | 540 | |
0f829b1d | 541 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
4789666e | 542 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); |
8a566afe | 543 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); |
0f829b1d | 544 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 545 | |
02044643 HS |
546 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
547 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); | |
548 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); | |
549 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, | |
550 | !!erp->short_preamble); | |
551 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); | |
552 | } | |
95ea3627 | 553 | |
02044643 HS |
554 | if (changed & BSS_CHANGED_BASIC_RATES) |
555 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, | |
556 | erp->basic_rates); | |
95ea3627 | 557 | |
02044643 HS |
558 | if (changed & BSS_CHANGED_BEACON_INT) { |
559 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
560 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, | |
561 | erp->beacon_int * 16); | |
562 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
563 | } | |
8a566afe | 564 | |
02044643 HS |
565 | if (changed & BSS_CHANGED_ERP_SLOT) { |
566 | rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); | |
567 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); | |
568 | rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); | |
95ea3627 | 569 | |
02044643 HS |
570 | rt2x00usb_register_read(rt2x00dev, MAC_CSR8, ®); |
571 | rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); | |
572 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); | |
573 | rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); | |
574 | rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg); | |
575 | } | |
95ea3627 ID |
576 | } |
577 | ||
578 | static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 579 | struct antenna_setup *ant) |
95ea3627 ID |
580 | { |
581 | u8 r3; | |
582 | u8 r4; | |
583 | u8 r77; | |
2676c94d | 584 | u8 temp; |
95ea3627 ID |
585 | |
586 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
587 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
588 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
589 | ||
590 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
591 | ||
e4cd2ff8 ID |
592 | /* |
593 | * Configure the RX antenna. | |
594 | */ | |
addc81bd | 595 | switch (ant->rx) { |
95ea3627 | 596 | case ANTENNA_HW_DIVERSITY: |
2676c94d | 597 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
7dab73b3 | 598 | temp = !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags) |
8318d78a | 599 | && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ); |
2676c94d | 600 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp); |
95ea3627 ID |
601 | break; |
602 | case ANTENNA_A: | |
2676c94d | 603 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 604 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 605 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
2676c94d MN |
606 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
607 | else | |
608 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
95ea3627 ID |
609 | break; |
610 | case ANTENNA_B: | |
a4fe07d9 | 611 | default: |
2676c94d | 612 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 613 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 614 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
2676c94d MN |
615 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
616 | else | |
617 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
95ea3627 ID |
618 | break; |
619 | } | |
620 | ||
621 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
622 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
623 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
624 | } | |
625 | ||
626 | static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 627 | struct antenna_setup *ant) |
95ea3627 ID |
628 | { |
629 | u8 r3; | |
630 | u8 r4; | |
631 | u8 r77; | |
632 | ||
633 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
634 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
635 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
636 | ||
637 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
638 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, | |
7dab73b3 | 639 | !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags)); |
95ea3627 | 640 | |
e4cd2ff8 ID |
641 | /* |
642 | * Configure the RX antenna. | |
643 | */ | |
addc81bd | 644 | switch (ant->rx) { |
95ea3627 | 645 | case ANTENNA_HW_DIVERSITY: |
2676c94d | 646 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
95ea3627 ID |
647 | break; |
648 | case ANTENNA_A: | |
2676c94d MN |
649 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
650 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); | |
95ea3627 ID |
651 | break; |
652 | case ANTENNA_B: | |
a4fe07d9 | 653 | default: |
2676c94d MN |
654 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
655 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); | |
95ea3627 ID |
656 | break; |
657 | } | |
658 | ||
659 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
660 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
661 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
662 | } | |
663 | ||
664 | struct antenna_sel { | |
665 | u8 word; | |
666 | /* | |
667 | * value[0] -> non-LNA | |
668 | * value[1] -> LNA | |
669 | */ | |
670 | u8 value[2]; | |
671 | }; | |
672 | ||
673 | static const struct antenna_sel antenna_sel_a[] = { | |
674 | { 96, { 0x58, 0x78 } }, | |
675 | { 104, { 0x38, 0x48 } }, | |
676 | { 75, { 0xfe, 0x80 } }, | |
677 | { 86, { 0xfe, 0x80 } }, | |
678 | { 88, { 0xfe, 0x80 } }, | |
679 | { 35, { 0x60, 0x60 } }, | |
680 | { 97, { 0x58, 0x58 } }, | |
681 | { 98, { 0x58, 0x58 } }, | |
682 | }; | |
683 | ||
684 | static const struct antenna_sel antenna_sel_bg[] = { | |
685 | { 96, { 0x48, 0x68 } }, | |
686 | { 104, { 0x2c, 0x3c } }, | |
687 | { 75, { 0xfe, 0x80 } }, | |
688 | { 86, { 0xfe, 0x80 } }, | |
689 | { 88, { 0xfe, 0x80 } }, | |
690 | { 35, { 0x50, 0x50 } }, | |
691 | { 97, { 0x48, 0x48 } }, | |
692 | { 98, { 0x48, 0x48 } }, | |
693 | }; | |
694 | ||
e4ea1c40 ID |
695 | static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev, |
696 | struct antenna_setup *ant) | |
95ea3627 ID |
697 | { |
698 | const struct antenna_sel *sel; | |
699 | unsigned int lna; | |
700 | unsigned int i; | |
701 | u32 reg; | |
702 | ||
a4fe07d9 ID |
703 | /* |
704 | * We should never come here because rt2x00lib is supposed | |
705 | * to catch this and send us the correct antenna explicitely. | |
706 | */ | |
707 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
708 | ant->tx == ANTENNA_SW_DIVERSITY); | |
709 | ||
8318d78a | 710 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 | 711 | sel = antenna_sel_a; |
7dab73b3 | 712 | lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); |
95ea3627 ID |
713 | } else { |
714 | sel = antenna_sel_bg; | |
7dab73b3 | 715 | lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); |
95ea3627 ID |
716 | } |
717 | ||
2676c94d MN |
718 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) |
719 | rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); | |
720 | ||
0f829b1d | 721 | rt2x00usb_register_read(rt2x00dev, PHY_CSR0, ®); |
2676c94d | 722 | |
ddc827f9 | 723 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, |
8318d78a | 724 | (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)); |
ddc827f9 | 725 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, |
8318d78a | 726 | (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)); |
ddc827f9 | 727 | |
0f829b1d | 728 | rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg); |
95ea3627 | 729 | |
5122d898 | 730 | if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225)) |
addc81bd | 731 | rt73usb_config_antenna_5x(rt2x00dev, ant); |
5122d898 | 732 | else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527)) |
addc81bd | 733 | rt73usb_config_antenna_2x(rt2x00dev, ant); |
95ea3627 ID |
734 | } |
735 | ||
e4ea1c40 | 736 | static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev, |
5c58ee51 | 737 | struct rt2x00lib_conf *libconf) |
e4ea1c40 ID |
738 | { |
739 | u16 eeprom; | |
740 | short lna_gain = 0; | |
741 | ||
742 | if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) { | |
7dab73b3 | 743 | if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) |
e4ea1c40 ID |
744 | lna_gain += 14; |
745 | ||
746 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); | |
747 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); | |
748 | } else { | |
749 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); | |
750 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); | |
751 | } | |
752 | ||
753 | rt2x00dev->lna_gain = lna_gain; | |
754 | } | |
755 | ||
756 | static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev, | |
757 | struct rf_channel *rf, const int txpower) | |
758 | { | |
759 | u8 r3; | |
760 | u8 r94; | |
761 | u8 smart; | |
762 | ||
763 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
764 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
765 | ||
5122d898 | 766 | smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); |
e4ea1c40 ID |
767 | |
768 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
769 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); | |
770 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
771 | ||
772 | r94 = 6; | |
773 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) | |
774 | r94 += txpower - MAX_TXPOWER; | |
775 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) | |
776 | r94 += txpower; | |
777 | rt73usb_bbp_write(rt2x00dev, 94, r94); | |
778 | ||
779 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
780 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
781 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
782 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
783 | ||
784 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
785 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
786 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
787 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
788 | ||
789 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
790 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
791 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
792 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
793 | ||
794 | udelay(10); | |
795 | } | |
796 | ||
797 | static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, | |
798 | const int txpower) | |
799 | { | |
800 | struct rf_channel rf; | |
801 | ||
802 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); | |
803 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); | |
804 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); | |
805 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); | |
806 | ||
807 | rt73usb_config_channel(rt2x00dev, &rf, txpower); | |
808 | } | |
809 | ||
810 | static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev, | |
811 | struct rt2x00lib_conf *libconf) | |
95ea3627 ID |
812 | { |
813 | u32 reg; | |
814 | ||
0f829b1d | 815 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); |
e1b4d7b7 ID |
816 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); |
817 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); | |
818 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); | |
e4ea1c40 ID |
819 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, |
820 | libconf->conf->long_frame_max_tx_count); | |
821 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, | |
822 | libconf->conf->short_frame_max_tx_count); | |
0f829b1d | 823 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); |
e4ea1c40 | 824 | } |
95ea3627 | 825 | |
7d7f19cc ID |
826 | static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev, |
827 | struct rt2x00lib_conf *libconf) | |
828 | { | |
829 | enum dev_state state = | |
830 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
831 | STATE_SLEEP : STATE_AWAKE; | |
832 | u32 reg; | |
833 | ||
834 | if (state == STATE_SLEEP) { | |
835 | rt2x00usb_register_read(rt2x00dev, MAC_CSR11, ®); | |
836 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, | |
6b347bff | 837 | rt2x00dev->beacon_int - 10); |
7d7f19cc ID |
838 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, |
839 | libconf->conf->listen_interval - 1); | |
840 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); | |
841 | ||
842 | /* We must first disable autowake before it can be enabled */ | |
843 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); | |
844 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
845 | ||
846 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); | |
847 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
848 | ||
849 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, | |
850 | USB_MODE_SLEEP, REGISTER_TIMEOUT); | |
851 | } else { | |
7d7f19cc ID |
852 | rt2x00usb_register_read(rt2x00dev, MAC_CSR11, ®); |
853 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); | |
854 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); | |
855 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); | |
856 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); | |
857 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
5731858d GW |
858 | |
859 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, | |
860 | USB_MODE_WAKEUP, REGISTER_TIMEOUT); | |
7d7f19cc ID |
861 | } |
862 | } | |
863 | ||
95ea3627 | 864 | static void rt73usb_config(struct rt2x00_dev *rt2x00dev, |
6bb40dd1 ID |
865 | struct rt2x00lib_conf *libconf, |
866 | const unsigned int flags) | |
95ea3627 | 867 | { |
ba2ab471 ID |
868 | /* Always recalculate LNA gain before changing configuration */ |
869 | rt73usb_config_lna_gain(rt2x00dev, libconf); | |
870 | ||
e4ea1c40 | 871 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
5c58ee51 ID |
872 | rt73usb_config_channel(rt2x00dev, &libconf->rf, |
873 | libconf->conf->power_level); | |
e4ea1c40 ID |
874 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
875 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) | |
5c58ee51 | 876 | rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level); |
e4ea1c40 ID |
877 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
878 | rt73usb_config_retry_limit(rt2x00dev, libconf); | |
7d7f19cc ID |
879 | if (flags & IEEE80211_CONF_CHANGE_PS) |
880 | rt73usb_config_ps(rt2x00dev, libconf); | |
95ea3627 ID |
881 | } |
882 | ||
95ea3627 ID |
883 | /* |
884 | * Link tuning | |
885 | */ | |
ebcf26da ID |
886 | static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev, |
887 | struct link_qual *qual) | |
95ea3627 ID |
888 | { |
889 | u32 reg; | |
890 | ||
891 | /* | |
892 | * Update FCS error count from register. | |
893 | */ | |
0f829b1d | 894 | rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); |
ebcf26da | 895 | qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); |
95ea3627 ID |
896 | |
897 | /* | |
898 | * Update False CCA count from register. | |
899 | */ | |
0f829b1d | 900 | rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); |
ebcf26da | 901 | qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); |
95ea3627 ID |
902 | } |
903 | ||
5352ff65 ID |
904 | static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev, |
905 | struct link_qual *qual, u8 vgc_level) | |
eb20b4e8 | 906 | { |
5352ff65 | 907 | if (qual->vgc_level != vgc_level) { |
eb20b4e8 | 908 | rt73usb_bbp_write(rt2x00dev, 17, vgc_level); |
5352ff65 ID |
909 | qual->vgc_level = vgc_level; |
910 | qual->vgc_level_reg = vgc_level; | |
eb20b4e8 ID |
911 | } |
912 | } | |
913 | ||
5352ff65 ID |
914 | static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev, |
915 | struct link_qual *qual) | |
95ea3627 | 916 | { |
5352ff65 | 917 | rt73usb_set_vgc(rt2x00dev, qual, 0x20); |
95ea3627 ID |
918 | } |
919 | ||
5352ff65 ID |
920 | static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev, |
921 | struct link_qual *qual, const u32 count) | |
95ea3627 | 922 | { |
95ea3627 ID |
923 | u8 up_bound; |
924 | u8 low_bound; | |
925 | ||
95ea3627 ID |
926 | /* |
927 | * Determine r17 bounds. | |
928 | */ | |
e5ef5bad | 929 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
930 | low_bound = 0x28; |
931 | up_bound = 0x48; | |
932 | ||
7dab73b3 | 933 | if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) { |
95ea3627 ID |
934 | low_bound += 0x10; |
935 | up_bound += 0x10; | |
936 | } | |
937 | } else { | |
5352ff65 | 938 | if (qual->rssi > -82) { |
95ea3627 ID |
939 | low_bound = 0x1c; |
940 | up_bound = 0x40; | |
5352ff65 | 941 | } else if (qual->rssi > -84) { |
95ea3627 ID |
942 | low_bound = 0x1c; |
943 | up_bound = 0x20; | |
944 | } else { | |
945 | low_bound = 0x1c; | |
946 | up_bound = 0x1c; | |
947 | } | |
948 | ||
7dab73b3 | 949 | if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) { |
95ea3627 ID |
950 | low_bound += 0x14; |
951 | up_bound += 0x10; | |
952 | } | |
953 | } | |
954 | ||
6bb40dd1 ID |
955 | /* |
956 | * If we are not associated, we should go straight to the | |
957 | * dynamic CCA tuning. | |
958 | */ | |
959 | if (!rt2x00dev->intf_associated) | |
960 | goto dynamic_cca_tune; | |
961 | ||
95ea3627 ID |
962 | /* |
963 | * Special big-R17 for very short distance | |
964 | */ | |
5352ff65 ID |
965 | if (qual->rssi > -35) { |
966 | rt73usb_set_vgc(rt2x00dev, qual, 0x60); | |
95ea3627 ID |
967 | return; |
968 | } | |
969 | ||
970 | /* | |
971 | * Special big-R17 for short distance | |
972 | */ | |
5352ff65 ID |
973 | if (qual->rssi >= -58) { |
974 | rt73usb_set_vgc(rt2x00dev, qual, up_bound); | |
95ea3627 ID |
975 | return; |
976 | } | |
977 | ||
978 | /* | |
979 | * Special big-R17 for middle-short distance | |
980 | */ | |
5352ff65 ID |
981 | if (qual->rssi >= -66) { |
982 | rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10); | |
95ea3627 ID |
983 | return; |
984 | } | |
985 | ||
986 | /* | |
987 | * Special mid-R17 for middle distance | |
988 | */ | |
5352ff65 ID |
989 | if (qual->rssi >= -74) { |
990 | rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08); | |
95ea3627 ID |
991 | return; |
992 | } | |
993 | ||
994 | /* | |
995 | * Special case: Change up_bound based on the rssi. | |
996 | * Lower up_bound when rssi is weaker then -74 dBm. | |
997 | */ | |
5352ff65 | 998 | up_bound -= 2 * (-74 - qual->rssi); |
95ea3627 ID |
999 | if (low_bound > up_bound) |
1000 | up_bound = low_bound; | |
1001 | ||
5352ff65 ID |
1002 | if (qual->vgc_level > up_bound) { |
1003 | rt73usb_set_vgc(rt2x00dev, qual, up_bound); | |
95ea3627 ID |
1004 | return; |
1005 | } | |
1006 | ||
6bb40dd1 ID |
1007 | dynamic_cca_tune: |
1008 | ||
95ea3627 ID |
1009 | /* |
1010 | * r17 does not yet exceed upper limit, continue and base | |
1011 | * the r17 tuning on the false CCA count. | |
1012 | */ | |
5352ff65 ID |
1013 | if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) |
1014 | rt73usb_set_vgc(rt2x00dev, qual, | |
1015 | min_t(u8, qual->vgc_level + 4, up_bound)); | |
1016 | else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) | |
1017 | rt73usb_set_vgc(rt2x00dev, qual, | |
1018 | max_t(u8, qual->vgc_level - 4, low_bound)); | |
95ea3627 ID |
1019 | } |
1020 | ||
5450b7e2 ID |
1021 | /* |
1022 | * Queue handlers. | |
1023 | */ | |
1024 | static void rt73usb_start_queue(struct data_queue *queue) | |
1025 | { | |
1026 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1027 | u32 reg; | |
1028 | ||
1029 | switch (queue->qid) { | |
1030 | case QID_RX: | |
1031 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1032 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1033 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1034 | break; | |
1035 | case QID_BEACON: | |
1036 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1037 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); | |
1038 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); | |
1039 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); | |
1040 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1041 | break; | |
1042 | default: | |
1043 | break; | |
1044 | } | |
1045 | } | |
1046 | ||
1047 | static void rt73usb_stop_queue(struct data_queue *queue) | |
1048 | { | |
1049 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1050 | u32 reg; | |
1051 | ||
1052 | switch (queue->qid) { | |
1053 | case QID_RX: | |
1054 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1055 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); | |
1056 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1057 | break; | |
1058 | case QID_BEACON: | |
1059 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1060 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1061 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1062 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1063 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1064 | break; | |
1065 | default: | |
1066 | break; | |
1067 | } | |
5450b7e2 ID |
1068 | } |
1069 | ||
95ea3627 | 1070 | /* |
a7f3a06c | 1071 | * Firmware functions |
95ea3627 ID |
1072 | */ |
1073 | static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) | |
1074 | { | |
1075 | return FIRMWARE_RT2571; | |
1076 | } | |
1077 | ||
0cbe0064 ID |
1078 | static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev, |
1079 | const u8 *data, const size_t len) | |
a7f3a06c | 1080 | { |
0cbe0064 | 1081 | u16 fw_crc; |
a7f3a06c ID |
1082 | u16 crc; |
1083 | ||
1084 | /* | |
0cbe0064 ID |
1085 | * Only support 2kb firmware files. |
1086 | */ | |
1087 | if (len != 2048) | |
1088 | return FW_BAD_LENGTH; | |
1089 | ||
1090 | /* | |
a7f3a06c ID |
1091 | * The last 2 bytes in the firmware array are the crc checksum itself, |
1092 | * this means that we should never pass those 2 bytes to the crc | |
1093 | * algorithm. | |
1094 | */ | |
0cbe0064 ID |
1095 | fw_crc = (data[len - 2] << 8 | data[len - 1]); |
1096 | ||
1097 | /* | |
1098 | * Use the crc itu-t algorithm. | |
1099 | */ | |
a7f3a06c ID |
1100 | crc = crc_itu_t(0, data, len - 2); |
1101 | crc = crc_itu_t_byte(crc, 0); | |
1102 | crc = crc_itu_t_byte(crc, 0); | |
1103 | ||
0cbe0064 | 1104 | return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; |
a7f3a06c ID |
1105 | } |
1106 | ||
0cbe0064 ID |
1107 | static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, |
1108 | const u8 *data, const size_t len) | |
95ea3627 ID |
1109 | { |
1110 | unsigned int i; | |
1111 | int status; | |
1112 | u32 reg; | |
95ea3627 ID |
1113 | |
1114 | /* | |
1115 | * Wait for stable hardware. | |
1116 | */ | |
1117 | for (i = 0; i < 100; i++) { | |
0f829b1d | 1118 | rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); |
95ea3627 ID |
1119 | if (reg) |
1120 | break; | |
1121 | msleep(1); | |
1122 | } | |
1123 | ||
1124 | if (!reg) { | |
1125 | ERROR(rt2x00dev, "Unstable hardware.\n"); | |
1126 | return -EBUSY; | |
1127 | } | |
1128 | ||
1129 | /* | |
1130 | * Write firmware to device. | |
95ea3627 | 1131 | */ |
96b61baf | 1132 | rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len); |
95ea3627 ID |
1133 | |
1134 | /* | |
1135 | * Send firmware request to device to load firmware, | |
1136 | * we need to specify a long timeout time. | |
1137 | */ | |
1138 | status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, | |
3b640f21 | 1139 | 0, USB_MODE_FIRMWARE, |
95ea3627 ID |
1140 | REGISTER_TIMEOUT_FIRMWARE); |
1141 | if (status < 0) { | |
1142 | ERROR(rt2x00dev, "Failed to write Firmware to device.\n"); | |
1143 | return status; | |
1144 | } | |
1145 | ||
95ea3627 ID |
1146 | return 0; |
1147 | } | |
1148 | ||
a7f3a06c ID |
1149 | /* |
1150 | * Initialization functions. | |
1151 | */ | |
95ea3627 ID |
1152 | static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev) |
1153 | { | |
1154 | u32 reg; | |
1155 | ||
0f829b1d | 1156 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
95ea3627 ID |
1157 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); |
1158 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1159 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); | |
0f829b1d | 1160 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 1161 | |
0f829b1d | 1162 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, ®); |
95ea3627 ID |
1163 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ |
1164 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); | |
1165 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ | |
1166 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); | |
1167 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ | |
1168 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); | |
1169 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ | |
1170 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); | |
0f829b1d | 1171 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg); |
95ea3627 ID |
1172 | |
1173 | /* | |
1174 | * CCK TXD BBP registers | |
1175 | */ | |
0f829b1d | 1176 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, ®); |
95ea3627 ID |
1177 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); |
1178 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); | |
1179 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); | |
1180 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); | |
1181 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); | |
1182 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); | |
1183 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); | |
1184 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); | |
0f829b1d | 1185 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg); |
95ea3627 ID |
1186 | |
1187 | /* | |
1188 | * OFDM TXD BBP registers | |
1189 | */ | |
0f829b1d | 1190 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, ®); |
95ea3627 ID |
1191 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); |
1192 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); | |
1193 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); | |
1194 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); | |
1195 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); | |
1196 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); | |
0f829b1d | 1197 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg); |
95ea3627 | 1198 | |
0f829b1d | 1199 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, ®); |
95ea3627 ID |
1200 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); |
1201 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); | |
1202 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); | |
1203 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); | |
0f829b1d | 1204 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg); |
95ea3627 | 1205 | |
0f829b1d | 1206 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, ®); |
95ea3627 ID |
1207 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); |
1208 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); | |
1209 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); | |
1210 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); | |
0f829b1d | 1211 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg); |
95ea3627 | 1212 | |
0f829b1d | 1213 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
1f909162 ID |
1214 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); |
1215 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1216 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); | |
1217 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1218 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1219 | rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); | |
0f829b1d | 1220 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
1f909162 | 1221 | |
0f829b1d | 1222 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); |
95ea3627 | 1223 | |
0f829b1d | 1224 | rt2x00usb_register_read(rt2x00dev, MAC_CSR6, ®); |
95ea3627 | 1225 | rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); |
0f829b1d | 1226 | rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg); |
95ea3627 | 1227 | |
0f829b1d | 1228 | rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); |
95ea3627 ID |
1229 | |
1230 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
1231 | return -EBUSY; | |
1232 | ||
0f829b1d | 1233 | rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); |
95ea3627 ID |
1234 | |
1235 | /* | |
1236 | * Invalidate all Shared Keys (SEC_CSR0), | |
1237 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) | |
1238 | */ | |
0f829b1d ID |
1239 | rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); |
1240 | rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); | |
1241 | rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); | |
95ea3627 ID |
1242 | |
1243 | reg = 0x000023b0; | |
5122d898 | 1244 | if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)) |
95ea3627 | 1245 | rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1); |
0f829b1d | 1246 | rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg); |
95ea3627 | 1247 | |
0f829b1d ID |
1248 | rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); |
1249 | rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); | |
1250 | rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); | |
95ea3627 | 1251 | |
0f829b1d | 1252 | rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); |
95ea3627 | 1253 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); |
0f829b1d | 1254 | rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); |
95ea3627 | 1255 | |
6bb40dd1 ID |
1256 | /* |
1257 | * Clear all beacons | |
1258 | * For the Beacon base registers we only need to clear | |
1259 | * the first byte since that byte contains the VALID and OWNER | |
1260 | * bits which (when set to 0) will invalidate the entire beacon. | |
1261 | */ | |
0f829b1d ID |
1262 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
1263 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); | |
1264 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); | |
1265 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); | |
6bb40dd1 | 1266 | |
95ea3627 ID |
1267 | /* |
1268 | * We must clear the error counters. | |
1269 | * These registers are cleared on read, | |
1270 | * so we may pass a useless variable to store the value. | |
1271 | */ | |
0f829b1d ID |
1272 | rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); |
1273 | rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); | |
1274 | rt2x00usb_register_read(rt2x00dev, STA_CSR2, ®); | |
95ea3627 ID |
1275 | |
1276 | /* | |
1277 | * Reset MAC and BBP registers. | |
1278 | */ | |
0f829b1d | 1279 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1280 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
1281 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
0f829b1d | 1282 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1283 | |
0f829b1d | 1284 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1285 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
1286 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
0f829b1d | 1287 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1288 | |
0f829b1d | 1289 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 | 1290 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
0f829b1d | 1291 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 ID |
1292 | |
1293 | return 0; | |
1294 | } | |
1295 | ||
2b08da3f | 1296 | static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1297 | { |
1298 | unsigned int i; | |
95ea3627 ID |
1299 | u8 value; |
1300 | ||
1301 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1302 | rt73usb_bbp_read(rt2x00dev, 0, &value); | |
1303 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 1304 | return 0; |
95ea3627 ID |
1305 | udelay(REGISTER_BUSY_DELAY); |
1306 | } | |
1307 | ||
1308 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
1309 | return -EACCES; | |
2b08da3f ID |
1310 | } |
1311 | ||
1312 | static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1313 | { | |
1314 | unsigned int i; | |
1315 | u16 eeprom; | |
1316 | u8 reg_id; | |
1317 | u8 value; | |
1318 | ||
1319 | if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev))) | |
1320 | return -EACCES; | |
95ea3627 | 1321 | |
95ea3627 ID |
1322 | rt73usb_bbp_write(rt2x00dev, 3, 0x80); |
1323 | rt73usb_bbp_write(rt2x00dev, 15, 0x30); | |
1324 | rt73usb_bbp_write(rt2x00dev, 21, 0xc8); | |
1325 | rt73usb_bbp_write(rt2x00dev, 22, 0x38); | |
1326 | rt73usb_bbp_write(rt2x00dev, 23, 0x06); | |
1327 | rt73usb_bbp_write(rt2x00dev, 24, 0xfe); | |
1328 | rt73usb_bbp_write(rt2x00dev, 25, 0x0a); | |
1329 | rt73usb_bbp_write(rt2x00dev, 26, 0x0d); | |
1330 | rt73usb_bbp_write(rt2x00dev, 32, 0x0b); | |
1331 | rt73usb_bbp_write(rt2x00dev, 34, 0x12); | |
1332 | rt73usb_bbp_write(rt2x00dev, 37, 0x07); | |
1333 | rt73usb_bbp_write(rt2x00dev, 39, 0xf8); | |
1334 | rt73usb_bbp_write(rt2x00dev, 41, 0x60); | |
1335 | rt73usb_bbp_write(rt2x00dev, 53, 0x10); | |
1336 | rt73usb_bbp_write(rt2x00dev, 54, 0x18); | |
1337 | rt73usb_bbp_write(rt2x00dev, 60, 0x10); | |
1338 | rt73usb_bbp_write(rt2x00dev, 61, 0x04); | |
1339 | rt73usb_bbp_write(rt2x00dev, 62, 0x04); | |
1340 | rt73usb_bbp_write(rt2x00dev, 75, 0xfe); | |
1341 | rt73usb_bbp_write(rt2x00dev, 86, 0xfe); | |
1342 | rt73usb_bbp_write(rt2x00dev, 88, 0xfe); | |
1343 | rt73usb_bbp_write(rt2x00dev, 90, 0x0f); | |
1344 | rt73usb_bbp_write(rt2x00dev, 99, 0x00); | |
1345 | rt73usb_bbp_write(rt2x00dev, 102, 0x16); | |
1346 | rt73usb_bbp_write(rt2x00dev, 107, 0x04); | |
1347 | ||
95ea3627 ID |
1348 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
1349 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1350 | ||
1351 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1352 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1353 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
1354 | rt73usb_bbp_write(rt2x00dev, reg_id, value); |
1355 | } | |
1356 | } | |
95ea3627 ID |
1357 | |
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | /* | |
1362 | * Device state switch handlers. | |
1363 | */ | |
95ea3627 ID |
1364 | static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) |
1365 | { | |
1366 | /* | |
1367 | * Initialize all registers. | |
1368 | */ | |
2b08da3f ID |
1369 | if (unlikely(rt73usb_init_registers(rt2x00dev) || |
1370 | rt73usb_init_bbp(rt2x00dev))) | |
95ea3627 | 1371 | return -EIO; |
95ea3627 | 1372 | |
95ea3627 ID |
1373 | return 0; |
1374 | } | |
1375 | ||
1376 | static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1377 | { | |
0f829b1d | 1378 | rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
95ea3627 ID |
1379 | |
1380 | /* | |
1381 | * Disable synchronisation. | |
1382 | */ | |
0f829b1d | 1383 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0); |
95ea3627 ID |
1384 | |
1385 | rt2x00usb_disable_radio(rt2x00dev); | |
1386 | } | |
1387 | ||
1388 | static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) | |
1389 | { | |
9655a6ec | 1390 | u32 reg, reg2; |
95ea3627 ID |
1391 | unsigned int i; |
1392 | char put_to_sleep; | |
95ea3627 ID |
1393 | |
1394 | put_to_sleep = (state != STATE_AWAKE); | |
1395 | ||
0f829b1d | 1396 | rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®); |
95ea3627 ID |
1397 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); |
1398 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); | |
0f829b1d | 1399 | rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1400 | |
1401 | /* | |
1402 | * Device is not guaranteed to be in the requested state yet. | |
1403 | * We must wait until the register indicates that the | |
1404 | * device has entered the correct state. | |
1405 | */ | |
1406 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
9655a6ec GW |
1407 | rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®2); |
1408 | state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); | |
2b08da3f | 1409 | if (state == !put_to_sleep) |
95ea3627 | 1410 | return 0; |
9655a6ec | 1411 | rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1412 | msleep(10); |
1413 | } | |
1414 | ||
95ea3627 ID |
1415 | return -EBUSY; |
1416 | } | |
1417 | ||
1418 | static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1419 | enum dev_state state) | |
1420 | { | |
1421 | int retval = 0; | |
1422 | ||
1423 | switch (state) { | |
1424 | case STATE_RADIO_ON: | |
1425 | retval = rt73usb_enable_radio(rt2x00dev); | |
1426 | break; | |
1427 | case STATE_RADIO_OFF: | |
1428 | rt73usb_disable_radio(rt2x00dev); | |
1429 | break; | |
2b08da3f ID |
1430 | case STATE_RADIO_IRQ_ON: |
1431 | case STATE_RADIO_IRQ_OFF: | |
1432 | /* No support, but no error either */ | |
95ea3627 ID |
1433 | break; |
1434 | case STATE_DEEP_SLEEP: | |
1435 | case STATE_SLEEP: | |
1436 | case STATE_STANDBY: | |
1437 | case STATE_AWAKE: | |
1438 | retval = rt73usb_set_state(rt2x00dev, state); | |
1439 | break; | |
1440 | default: | |
1441 | retval = -ENOTSUPP; | |
1442 | break; | |
1443 | } | |
1444 | ||
2b08da3f ID |
1445 | if (unlikely(retval)) |
1446 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", | |
1447 | state, retval); | |
1448 | ||
95ea3627 ID |
1449 | return retval; |
1450 | } | |
1451 | ||
1452 | /* | |
1453 | * TX descriptor initialization | |
1454 | */ | |
93331458 | 1455 | static void rt73usb_write_tx_desc(struct queue_entry *entry, |
906c110f | 1456 | struct txentry_desc *txdesc) |
95ea3627 | 1457 | { |
93331458 ID |
1458 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
1459 | __le32 *txd = (__le32 *) entry->skb->data; | |
95ea3627 ID |
1460 | u32 word; |
1461 | ||
1462 | /* | |
1463 | * Start writing the descriptor words. | |
1464 | */ | |
e01f1ec3 GW |
1465 | rt2x00_desc_read(txd, 0, &word); |
1466 | rt2x00_set_field32(&word, TXD_W0_BURST, | |
1467 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); | |
1468 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1469 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
1470 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); | |
1471 | rt2x00_set_field32(&word, TXD_W0_ACK, | |
1472 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); | |
1473 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, | |
1474 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); | |
1475 | rt2x00_set_field32(&word, TXD_W0_OFDM, | |
1476 | (txdesc->rate_mode == RATE_MODE_OFDM)); | |
2517794b | 1477 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); |
e01f1ec3 GW |
1478 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
1479 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); | |
1480 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, | |
1481 | test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); | |
1482 | rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, | |
1483 | test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); | |
1484 | rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); | |
1485 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); | |
1486 | rt2x00_set_field32(&word, TXD_W0_BURST2, | |
1487 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); | |
1488 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); | |
1489 | rt2x00_desc_write(txd, 0, word); | |
1490 | ||
95ea3627 | 1491 | rt2x00_desc_read(txd, 1, &word); |
2b23cdaa HS |
1492 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); |
1493 | rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); | |
1494 | rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); | |
1495 | rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); | |
906c110f | 1496 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); |
5adf6d63 ID |
1497 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, |
1498 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
95ea3627 ID |
1499 | rt2x00_desc_write(txd, 1, word); |
1500 | ||
1501 | rt2x00_desc_read(txd, 2, &word); | |
26a1d07f HS |
1502 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); |
1503 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); | |
1504 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, | |
1505 | txdesc->u.plcp.length_low); | |
1506 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, | |
1507 | txdesc->u.plcp.length_high); | |
95ea3627 ID |
1508 | rt2x00_desc_write(txd, 2, word); |
1509 | ||
906c110f | 1510 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { |
1ce9cdac ID |
1511 | _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); |
1512 | _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); | |
906c110f ID |
1513 | } |
1514 | ||
95ea3627 ID |
1515 | rt2x00_desc_read(txd, 5, &word); |
1516 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, | |
93331458 | 1517 | TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); |
95ea3627 ID |
1518 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
1519 | rt2x00_desc_write(txd, 5, word); | |
1520 | ||
85b7a8b3 GW |
1521 | /* |
1522 | * Register descriptor details in skb frame descriptor. | |
1523 | */ | |
0b8004aa | 1524 | skbdesc->flags |= SKBDESC_DESC_IN_SKB; |
85b7a8b3 GW |
1525 | skbdesc->desc = txd; |
1526 | skbdesc->desc_len = TXD_DESC_SIZE; | |
95ea3627 ID |
1527 | } |
1528 | ||
bd88a781 ID |
1529 | /* |
1530 | * TX data initialization | |
1531 | */ | |
f224f4ef GW |
1532 | static void rt73usb_write_beacon(struct queue_entry *entry, |
1533 | struct txentry_desc *txdesc) | |
bd88a781 ID |
1534 | { |
1535 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
bd88a781 | 1536 | unsigned int beacon_base; |
739fd940 | 1537 | unsigned int padding_len; |
d76dfc61 | 1538 | u32 orig_reg, reg; |
bd88a781 | 1539 | |
bd88a781 ID |
1540 | /* |
1541 | * Disable beaconing while we are reloading the beacon data, | |
1542 | * otherwise we might be sending out invalid data. | |
1543 | */ | |
0f829b1d | 1544 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
d76dfc61 | 1545 | orig_reg = reg; |
bd88a781 | 1546 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
0f829b1d | 1547 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
bd88a781 | 1548 | |
0b8004aa GW |
1549 | /* |
1550 | * Add space for the descriptor in front of the skb. | |
1551 | */ | |
1552 | skb_push(entry->skb, TXD_DESC_SIZE); | |
1553 | memset(entry->skb->data, 0, TXD_DESC_SIZE); | |
1554 | ||
5c3b685c GW |
1555 | /* |
1556 | * Write the TX descriptor for the beacon. | |
1557 | */ | |
93331458 | 1558 | rt73usb_write_tx_desc(entry, txdesc); |
5c3b685c GW |
1559 | |
1560 | /* | |
1561 | * Dump beacon to userspace through debugfs. | |
1562 | */ | |
1563 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
1564 | ||
bd88a781 | 1565 | /* |
739fd940 | 1566 | * Write entire beacon with descriptor and padding to register. |
bd88a781 | 1567 | */ |
739fd940 | 1568 | padding_len = roundup(entry->skb->len, 4) - entry->skb->len; |
d76dfc61 SF |
1569 | if (padding_len && skb_pad(entry->skb, padding_len)) { |
1570 | ERROR(rt2x00dev, "Failure padding beacon, aborting\n"); | |
1571 | /* skb freed by skb_pad() on failure */ | |
1572 | entry->skb = NULL; | |
1573 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg); | |
1574 | return; | |
1575 | } | |
1576 | ||
bd88a781 | 1577 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
739fd940 WK |
1578 | rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, |
1579 | entry->skb->len + padding_len); | |
bd88a781 | 1580 | |
d61cb266 GW |
1581 | /* |
1582 | * Enable beaconing again. | |
1583 | * | |
1584 | * For Wi-Fi faily generated beacons between participating stations. | |
1585 | * Set TBTT phase adaptive adjustment step to 8us (default 16us) | |
1586 | */ | |
1587 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); | |
1588 | ||
d61cb266 GW |
1589 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); |
1590 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1591 | ||
bd88a781 ID |
1592 | /* |
1593 | * Clean up the beacon skb. | |
1594 | */ | |
1595 | dev_kfree_skb(entry->skb); | |
1596 | entry->skb = NULL; | |
1597 | } | |
1598 | ||
69cf36a4 HS |
1599 | static void rt73usb_clear_beacon(struct queue_entry *entry) |
1600 | { | |
1601 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
1602 | unsigned int beacon_base; | |
1603 | u32 reg; | |
1604 | ||
1605 | /* | |
1606 | * Disable beaconing while we are reloading the beacon data, | |
1607 | * otherwise we might be sending out invalid data. | |
1608 | */ | |
1609 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1610 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1611 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1612 | ||
1613 | /* | |
1614 | * Clear beacon. | |
1615 | */ | |
1616 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); | |
1617 | rt2x00usb_register_write(rt2x00dev, beacon_base, 0); | |
1618 | ||
1619 | /* | |
1620 | * Enable beaconing again. | |
1621 | */ | |
1622 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); | |
1623 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1624 | } | |
1625 | ||
f1ca2167 | 1626 | static int rt73usb_get_tx_data_len(struct queue_entry *entry) |
dd9fa2d2 ID |
1627 | { |
1628 | int length; | |
1629 | ||
1630 | /* | |
1631 | * The length _must_ be a multiple of 4, | |
1632 | * but it must _not_ be a multiple of the USB packet size. | |
1633 | */ | |
f1ca2167 ID |
1634 | length = roundup(entry->skb->len, 4); |
1635 | length += (4 * !(length % entry->queue->usb_maxpacket)); | |
dd9fa2d2 ID |
1636 | |
1637 | return length; | |
1638 | } | |
1639 | ||
95ea3627 ID |
1640 | /* |
1641 | * RX control handlers | |
1642 | */ | |
1643 | static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) | |
1644 | { | |
ba2ab471 | 1645 | u8 offset = rt2x00dev->lna_gain; |
95ea3627 ID |
1646 | u8 lna; |
1647 | ||
1648 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); | |
1649 | switch (lna) { | |
1650 | case 3: | |
ba2ab471 | 1651 | offset += 90; |
95ea3627 ID |
1652 | break; |
1653 | case 2: | |
ba2ab471 | 1654 | offset += 74; |
95ea3627 ID |
1655 | break; |
1656 | case 1: | |
ba2ab471 | 1657 | offset += 64; |
95ea3627 ID |
1658 | break; |
1659 | default: | |
1660 | return 0; | |
1661 | } | |
1662 | ||
e5ef5bad | 1663 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
7dab73b3 | 1664 | if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) { |
95ea3627 ID |
1665 | if (lna == 3 || lna == 2) |
1666 | offset += 10; | |
1667 | } else { | |
1668 | if (lna == 3) | |
1669 | offset += 6; | |
1670 | else if (lna == 2) | |
1671 | offset += 8; | |
1672 | } | |
95ea3627 ID |
1673 | } |
1674 | ||
1675 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; | |
1676 | } | |
1677 | ||
181d6902 | 1678 | static void rt73usb_fill_rxdone(struct queue_entry *entry, |
55887511 | 1679 | struct rxdone_entry_desc *rxdesc) |
95ea3627 | 1680 | { |
906c110f | 1681 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
181d6902 | 1682 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
4bd7c452 | 1683 | __le32 *rxd = (__le32 *)entry->skb->data; |
95ea3627 ID |
1684 | u32 word0; |
1685 | u32 word1; | |
1686 | ||
f855c10b | 1687 | /* |
a26cbc65 GW |
1688 | * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of |
1689 | * frame data in rt2x00usb. | |
f855c10b | 1690 | */ |
a26cbc65 | 1691 | memcpy(skbdesc->desc, rxd, skbdesc->desc_len); |
70a96109 | 1692 | rxd = (__le32 *)skbdesc->desc; |
f855c10b ID |
1693 | |
1694 | /* | |
70a96109 | 1695 | * It is now safe to read the descriptor on all architectures. |
f855c10b | 1696 | */ |
95ea3627 ID |
1697 | rt2x00_desc_read(rxd, 0, &word0); |
1698 | rt2x00_desc_read(rxd, 1, &word1); | |
1699 | ||
4150c572 | 1700 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 1701 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
95ea3627 | 1702 | |
78b8f3b0 GW |
1703 | rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); |
1704 | rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); | |
906c110f ID |
1705 | |
1706 | if (rxdesc->cipher != CIPHER_NONE) { | |
1ce9cdac ID |
1707 | _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]); |
1708 | _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]); | |
74415edb ID |
1709 | rxdesc->dev_flags |= RXDONE_CRYPTO_IV; |
1710 | ||
906c110f | 1711 | _rt2x00_desc_read(rxd, 4, &rxdesc->icv); |
74415edb | 1712 | rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; |
906c110f ID |
1713 | |
1714 | /* | |
1715 | * Hardware has stripped IV/EIV data from 802.11 frame during | |
3ad2f3fb | 1716 | * decryption. It has provided the data separately but rt2x00lib |
906c110f ID |
1717 | * should decide if it should be reinserted. |
1718 | */ | |
1719 | rxdesc->flags |= RX_FLAG_IV_STRIPPED; | |
1720 | ||
1721 | /* | |
a0aff623 GW |
1722 | * The hardware has already checked the Michael Mic and has |
1723 | * stripped it from the frame. Signal this to mac80211. | |
906c110f ID |
1724 | */ |
1725 | rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; | |
1726 | ||
1727 | if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) | |
1728 | rxdesc->flags |= RX_FLAG_DECRYPTED; | |
1729 | else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) | |
1730 | rxdesc->flags |= RX_FLAG_MMIC_ERROR; | |
1731 | } | |
1732 | ||
95ea3627 ID |
1733 | /* |
1734 | * Obtain the status about this packet. | |
89993890 ID |
1735 | * When frame was received with an OFDM bitrate, |
1736 | * the signal is the PLCP value. If it was received with | |
1737 | * a CCK bitrate the signal is the rate in 100kbit/s. | |
95ea3627 | 1738 | */ |
181d6902 | 1739 | rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
906c110f | 1740 | rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1); |
181d6902 | 1741 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 1742 | |
19d30e02 ID |
1743 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
1744 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | |
6c6aa3c0 ID |
1745 | else |
1746 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; | |
19d30e02 ID |
1747 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1748 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
181d6902 | 1749 | |
2ae23854 | 1750 | /* |
70a96109 | 1751 | * Set skb pointers, and update frame information. |
2ae23854 | 1752 | */ |
70a96109 | 1753 | skb_pull(entry->skb, entry->queue->desc_size); |
2ae23854 | 1754 | skb_trim(entry->skb, rxdesc->size); |
95ea3627 ID |
1755 | } |
1756 | ||
1757 | /* | |
1758 | * Device probe functions. | |
1759 | */ | |
1760 | static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
1761 | { | |
1762 | u16 word; | |
1763 | u8 *mac; | |
1764 | s8 value; | |
1765 | ||
1766 | rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE); | |
1767 | ||
1768 | /* | |
1769 | * Start validation of the data that has been read. | |
1770 | */ | |
1771 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1772 | if (!is_valid_ether_addr(mac)) { | |
1773 | random_ether_addr(mac); | |
e174961c | 1774 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
95ea3627 ID |
1775 | } |
1776 | ||
1777 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1778 | if (word == 0xffff) { | |
1779 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
362f3b6b ID |
1780 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
1781 | ANTENNA_B); | |
1782 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, | |
1783 | ANTENNA_B); | |
95ea3627 ID |
1784 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); |
1785 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); | |
1786 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
1787 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226); | |
1788 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
1789 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); | |
1790 | } | |
1791 | ||
1792 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
1793 | if (word == 0xffff) { | |
1794 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0); | |
1795 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
1796 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); | |
1797 | } | |
1798 | ||
1799 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); | |
1800 | if (word == 0xffff) { | |
1801 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0); | |
1802 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0); | |
1803 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0); | |
1804 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0); | |
1805 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0); | |
1806 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0); | |
1807 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0); | |
1808 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0); | |
1809 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, | |
1810 | LED_MODE_DEFAULT); | |
1811 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); | |
1812 | EEPROM(rt2x00dev, "Led: 0x%04x\n", word); | |
1813 | } | |
1814 | ||
1815 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
1816 | if (word == 0xffff) { | |
1817 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
1818 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); | |
1819 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
1820 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); | |
1821 | } | |
1822 | ||
1823 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); | |
1824 | if (word == 0xffff) { | |
1825 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1826 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1827 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1828 | EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); | |
1829 | } else { | |
1830 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); | |
1831 | if (value < -10 || value > 10) | |
1832 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1833 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); | |
1834 | if (value < -10 || value > 10) | |
1835 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1836 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1837 | } | |
1838 | ||
1839 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); | |
1840 | if (word == 0xffff) { | |
1841 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1842 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1843 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
417f412f | 1844 | EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); |
95ea3627 ID |
1845 | } else { |
1846 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); | |
1847 | if (value < -10 || value > 10) | |
1848 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1849 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); | |
1850 | if (value < -10 || value > 10) | |
1851 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1852 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
1853 | } | |
1854 | ||
1855 | return 0; | |
1856 | } | |
1857 | ||
1858 | static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1859 | { | |
1860 | u32 reg; | |
1861 | u16 value; | |
1862 | u16 eeprom; | |
1863 | ||
1864 | /* | |
1865 | * Read EEPROM word for configuration. | |
1866 | */ | |
1867 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1868 | ||
1869 | /* | |
1870 | * Identify RF chipset. | |
1871 | */ | |
1872 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
0f829b1d | 1873 | rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); |
49e721ec GW |
1874 | rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), |
1875 | value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); | |
95ea3627 | 1876 | |
49e721ec | 1877 | if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) { |
95ea3627 ID |
1878 | ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); |
1879 | return -ENODEV; | |
1880 | } | |
1881 | ||
5122d898 GW |
1882 | if (!rt2x00_rf(rt2x00dev, RF5226) && |
1883 | !rt2x00_rf(rt2x00dev, RF2528) && | |
1884 | !rt2x00_rf(rt2x00dev, RF5225) && | |
1885 | !rt2x00_rf(rt2x00dev, RF2527)) { | |
95ea3627 ID |
1886 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
1887 | return -ENODEV; | |
1888 | } | |
1889 | ||
1890 | /* | |
1891 | * Identify default antenna configuration. | |
1892 | */ | |
addc81bd | 1893 | rt2x00dev->default_ant.tx = |
95ea3627 | 1894 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 1895 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
1896 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
1897 | ||
1898 | /* | |
1899 | * Read the Frame type. | |
1900 | */ | |
1901 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) | |
7dab73b3 | 1902 | __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); |
95ea3627 | 1903 | |
7396faf4 ID |
1904 | /* |
1905 | * Detect if this device has an hardware controlled radio. | |
1906 | */ | |
7396faf4 | 1907 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
7dab73b3 | 1908 | __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); |
7396faf4 | 1909 | |
95ea3627 ID |
1910 | /* |
1911 | * Read frequency offset. | |
1912 | */ | |
1913 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
1914 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
1915 | ||
1916 | /* | |
1917 | * Read external LNA informations. | |
1918 | */ | |
1919 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
1920 | ||
1921 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) { | |
7dab73b3 ID |
1922 | __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); |
1923 | __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); | |
95ea3627 ID |
1924 | } |
1925 | ||
1926 | /* | |
1927 | * Store led settings, for correct led behaviour. | |
1928 | */ | |
771fd565 | 1929 | #ifdef CONFIG_RT2X00_LIB_LEDS |
95ea3627 ID |
1930 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); |
1931 | ||
475433be ID |
1932 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
1933 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
1934 | if (value == LED_MODE_SIGNAL_STRENGTH) | |
1935 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual, | |
1936 | LED_TYPE_QUALITY); | |
a9450b70 ID |
1937 | |
1938 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); | |
1939 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, | |
95ea3627 ID |
1940 | rt2x00_get_field16(eeprom, |
1941 | EEPROM_LED_POLARITY_GPIO_0)); | |
a9450b70 | 1942 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, |
95ea3627 ID |
1943 | rt2x00_get_field16(eeprom, |
1944 | EEPROM_LED_POLARITY_GPIO_1)); | |
a9450b70 | 1945 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, |
95ea3627 ID |
1946 | rt2x00_get_field16(eeprom, |
1947 | EEPROM_LED_POLARITY_GPIO_2)); | |
a9450b70 | 1948 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, |
95ea3627 ID |
1949 | rt2x00_get_field16(eeprom, |
1950 | EEPROM_LED_POLARITY_GPIO_3)); | |
a9450b70 | 1951 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, |
95ea3627 ID |
1952 | rt2x00_get_field16(eeprom, |
1953 | EEPROM_LED_POLARITY_GPIO_4)); | |
a9450b70 | 1954 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, |
95ea3627 | 1955 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); |
a9450b70 | 1956 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, |
95ea3627 ID |
1957 | rt2x00_get_field16(eeprom, |
1958 | EEPROM_LED_POLARITY_RDY_G)); | |
a9450b70 | 1959 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, |
95ea3627 ID |
1960 | rt2x00_get_field16(eeprom, |
1961 | EEPROM_LED_POLARITY_RDY_A)); | |
771fd565 | 1962 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
1963 | |
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | /* | |
1968 | * RF value list for RF2528 | |
1969 | * Supports: 2.4 GHz | |
1970 | */ | |
1971 | static const struct rf_channel rf_vals_bg_2528[] = { | |
1972 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1973 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1974 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1975 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1976 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1977 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1978 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1979 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1980 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1981 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
1982 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
1983 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
1984 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
1985 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
1986 | }; | |
1987 | ||
1988 | /* | |
1989 | * RF value list for RF5226 | |
1990 | * Supports: 2.4 GHz & 5.2 GHz | |
1991 | */ | |
1992 | static const struct rf_channel rf_vals_5226[] = { | |
1993 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1994 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1995 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1996 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1997 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1998 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1999 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
2000 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
2001 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
2002 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
2003 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
2004 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
2005 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
2006 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
2007 | ||
2008 | /* 802.11 UNI / HyperLan 2 */ | |
2009 | { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 }, | |
2010 | { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 }, | |
2011 | { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b }, | |
2012 | { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 }, | |
2013 | { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b }, | |
2014 | { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 }, | |
2015 | { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 }, | |
2016 | { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b }, | |
2017 | ||
2018 | /* 802.11 HyperLan 2 */ | |
2019 | { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 }, | |
2020 | { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b }, | |
2021 | { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 }, | |
2022 | { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b }, | |
2023 | { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 }, | |
2024 | { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 }, | |
2025 | { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b }, | |
2026 | { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 }, | |
2027 | { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b }, | |
2028 | { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 }, | |
2029 | ||
2030 | /* 802.11 UNII */ | |
2031 | { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 }, | |
2032 | { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f }, | |
2033 | { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 }, | |
2034 | { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 }, | |
2035 | { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f }, | |
2036 | { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 }, | |
2037 | ||
2038 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2039 | { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b }, | |
2040 | { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 }, | |
2041 | { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b }, | |
2042 | { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 }, | |
2043 | }; | |
2044 | ||
2045 | /* | |
2046 | * RF value list for RF5225 & RF2527 | |
2047 | * Supports: 2.4 GHz & 5.2 GHz | |
2048 | */ | |
2049 | static const struct rf_channel rf_vals_5225_2527[] = { | |
2050 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
2051 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
2052 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
2053 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
2054 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
2055 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
2056 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
2057 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
2058 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
2059 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
2060 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
2061 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
2062 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
2063 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
2064 | ||
2065 | /* 802.11 UNI / HyperLan 2 */ | |
2066 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, | |
2067 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, | |
2068 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, | |
2069 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, | |
2070 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, | |
2071 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, | |
2072 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, | |
2073 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, | |
2074 | ||
2075 | /* 802.11 HyperLan 2 */ | |
2076 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, | |
2077 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, | |
2078 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, | |
2079 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, | |
2080 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, | |
2081 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, | |
2082 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, | |
2083 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, | |
2084 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, | |
2085 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, | |
2086 | ||
2087 | /* 802.11 UNII */ | |
2088 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, | |
2089 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, | |
2090 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, | |
2091 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, | |
2092 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, | |
2093 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, | |
2094 | ||
2095 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2096 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, | |
2097 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, | |
2098 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, | |
2099 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, | |
2100 | }; | |
2101 | ||
2102 | ||
8c5e7a5f | 2103 | static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
2104 | { |
2105 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
2106 | struct channel_info *info; |
2107 | char *tx_power; | |
95ea3627 ID |
2108 | unsigned int i; |
2109 | ||
2110 | /* | |
2111 | * Initialize all hw fields. | |
5a5b6ed6 HS |
2112 | * |
2113 | * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are | |
2114 | * capable of sending the buffered frames out after the DTIM | |
2115 | * transmission using rt2x00lib_beacondone. This will send out | |
2116 | * multicast and broadcast traffic immediately instead of buffering it | |
2117 | * infinitly and thus dropping it after some time. | |
95ea3627 ID |
2118 | */ |
2119 | rt2x00dev->hw->flags = | |
4be8c387 JB |
2120 | IEEE80211_HW_SIGNAL_DBM | |
2121 | IEEE80211_HW_SUPPORTS_PS | | |
2122 | IEEE80211_HW_PS_NULLFUNC_STACK; | |
95ea3627 | 2123 | |
14a3bf89 | 2124 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
2125 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
2126 | rt2x00_eeprom_addr(rt2x00dev, | |
2127 | EEPROM_MAC_ADDR_0)); | |
2128 | ||
95ea3627 ID |
2129 | /* |
2130 | * Initialize hw_mode information. | |
2131 | */ | |
31562e80 ID |
2132 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
2133 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
95ea3627 | 2134 | |
5122d898 | 2135 | if (rt2x00_rf(rt2x00dev, RF2528)) { |
95ea3627 ID |
2136 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528); |
2137 | spec->channels = rf_vals_bg_2528; | |
5122d898 | 2138 | } else if (rt2x00_rf(rt2x00dev, RF5226)) { |
31562e80 | 2139 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
2140 | spec->num_channels = ARRAY_SIZE(rf_vals_5226); |
2141 | spec->channels = rf_vals_5226; | |
5122d898 | 2142 | } else if (rt2x00_rf(rt2x00dev, RF2527)) { |
95ea3627 ID |
2143 | spec->num_channels = 14; |
2144 | spec->channels = rf_vals_5225_2527; | |
5122d898 | 2145 | } else if (rt2x00_rf(rt2x00dev, RF5225)) { |
31562e80 | 2146 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
2147 | spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527); |
2148 | spec->channels = rf_vals_5225_2527; | |
2149 | } | |
2150 | ||
8c5e7a5f ID |
2151 | /* |
2152 | * Create channel information array | |
2153 | */ | |
baeb2ffa | 2154 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
8c5e7a5f ID |
2155 | if (!info) |
2156 | return -ENOMEM; | |
95ea3627 | 2157 | |
8c5e7a5f ID |
2158 | spec->channels_info = info; |
2159 | ||
2160 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); | |
8d1331b3 ID |
2161 | for (i = 0; i < 14; i++) { |
2162 | info[i].max_power = MAX_TXPOWER; | |
2163 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
2164 | } | |
8c5e7a5f ID |
2165 | |
2166 | if (spec->num_channels > 14) { | |
2167 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); | |
8d1331b3 ID |
2168 | for (i = 14; i < spec->num_channels; i++) { |
2169 | info[i].max_power = MAX_TXPOWER; | |
2170 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
2171 | } | |
95ea3627 | 2172 | } |
8c5e7a5f ID |
2173 | |
2174 | return 0; | |
95ea3627 ID |
2175 | } |
2176 | ||
2177 | static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev) | |
2178 | { | |
2179 | int retval; | |
2180 | ||
2181 | /* | |
2182 | * Allocate eeprom data. | |
2183 | */ | |
2184 | retval = rt73usb_validate_eeprom(rt2x00dev); | |
2185 | if (retval) | |
2186 | return retval; | |
2187 | ||
2188 | retval = rt73usb_init_eeprom(rt2x00dev); | |
2189 | if (retval) | |
2190 | return retval; | |
2191 | ||
2192 | /* | |
2193 | * Initialize hw specifications. | |
2194 | */ | |
8c5e7a5f ID |
2195 | retval = rt73usb_probe_hw_mode(rt2x00dev); |
2196 | if (retval) | |
2197 | return retval; | |
95ea3627 | 2198 | |
1afcfd54 IP |
2199 | /* |
2200 | * This device has multiple filters for control frames, | |
2201 | * but has no a separate filter for PS Poll frames. | |
2202 | */ | |
7dab73b3 | 2203 | __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); |
1afcfd54 | 2204 | |
95ea3627 | 2205 | /* |
9404ef34 | 2206 | * This device requires firmware. |
95ea3627 | 2207 | */ |
7dab73b3 | 2208 | __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); |
008c4482 | 2209 | if (!modparam_nohwcrypt) |
7dab73b3 ID |
2210 | __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); |
2211 | __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); | |
1c0bcf89 | 2212 | __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); |
95ea3627 ID |
2213 | |
2214 | /* | |
2215 | * Set the rssi offset. | |
2216 | */ | |
2217 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
2218 | ||
2219 | return 0; | |
2220 | } | |
2221 | ||
2222 | /* | |
2223 | * IEEE80211 stack callback functions. | |
2224 | */ | |
2af0a570 ID |
2225 | static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
2226 | const struct ieee80211_tx_queue_params *params) | |
2227 | { | |
2228 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2229 | struct data_queue *queue; | |
2230 | struct rt2x00_field32 field; | |
2231 | int retval; | |
2232 | u32 reg; | |
5e790023 | 2233 | u32 offset; |
2af0a570 ID |
2234 | |
2235 | /* | |
2236 | * First pass the configuration through rt2x00lib, that will | |
2237 | * update the queue settings and validate the input. After that | |
2238 | * we are free to update the registers based on the value | |
2239 | * in the queue parameter. | |
2240 | */ | |
2241 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); | |
2242 | if (retval) | |
2243 | return retval; | |
2244 | ||
5e790023 ID |
2245 | /* |
2246 | * We only need to perform additional register initialization | |
2247 | * for WMM queues/ | |
2248 | */ | |
2249 | if (queue_idx >= 4) | |
2250 | return 0; | |
2251 | ||
11f818e0 | 2252 | queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
2af0a570 ID |
2253 | |
2254 | /* Update WMM TXOP register */ | |
5e790023 ID |
2255 | offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); |
2256 | field.bit_offset = (queue_idx & 1) * 16; | |
2257 | field.bit_mask = 0xffff << field.bit_offset; | |
2258 | ||
2259 | rt2x00usb_register_read(rt2x00dev, offset, ®); | |
2260 | rt2x00_set_field32(®, field, queue->txop); | |
2261 | rt2x00usb_register_write(rt2x00dev, offset, reg); | |
2af0a570 ID |
2262 | |
2263 | /* Update WMM registers */ | |
2264 | field.bit_offset = queue_idx * 4; | |
2265 | field.bit_mask = 0xf << field.bit_offset; | |
2266 | ||
0f829b1d | 2267 | rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, ®); |
2af0a570 | 2268 | rt2x00_set_field32(®, field, queue->aifs); |
0f829b1d | 2269 | rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg); |
2af0a570 | 2270 | |
0f829b1d | 2271 | rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, ®); |
2af0a570 | 2272 | rt2x00_set_field32(®, field, queue->cw_min); |
0f829b1d | 2273 | rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg); |
2af0a570 | 2274 | |
0f829b1d | 2275 | rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, ®); |
2af0a570 | 2276 | rt2x00_set_field32(®, field, queue->cw_max); |
0f829b1d | 2277 | rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg); |
2af0a570 ID |
2278 | |
2279 | return 0; | |
2280 | } | |
2281 | ||
95ea3627 ID |
2282 | static u64 rt73usb_get_tsf(struct ieee80211_hw *hw) |
2283 | { | |
2284 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2285 | u64 tsf; | |
2286 | u32 reg; | |
2287 | ||
0f829b1d | 2288 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, ®); |
95ea3627 | 2289 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; |
0f829b1d | 2290 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, ®); |
95ea3627 ID |
2291 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); |
2292 | ||
2293 | return tsf; | |
2294 | } | |
95ea3627 | 2295 | |
95ea3627 ID |
2296 | static const struct ieee80211_ops rt73usb_mac80211_ops = { |
2297 | .tx = rt2x00mac_tx, | |
4150c572 JB |
2298 | .start = rt2x00mac_start, |
2299 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
2300 | .add_interface = rt2x00mac_add_interface, |
2301 | .remove_interface = rt2x00mac_remove_interface, | |
2302 | .config = rt2x00mac_config, | |
3a643d24 | 2303 | .configure_filter = rt2x00mac_configure_filter, |
930c06f2 | 2304 | .set_tim = rt2x00mac_set_tim, |
906c110f | 2305 | .set_key = rt2x00mac_set_key, |
d8147f9d ID |
2306 | .sw_scan_start = rt2x00mac_sw_scan_start, |
2307 | .sw_scan_complete = rt2x00mac_sw_scan_complete, | |
95ea3627 | 2308 | .get_stats = rt2x00mac_get_stats, |
471b3efd | 2309 | .bss_info_changed = rt2x00mac_bss_info_changed, |
2af0a570 | 2310 | .conf_tx = rt73usb_conf_tx, |
95ea3627 | 2311 | .get_tsf = rt73usb_get_tsf, |
e47a5cdd | 2312 | .rfkill_poll = rt2x00mac_rfkill_poll, |
f44df18c | 2313 | .flush = rt2x00mac_flush, |
0ed7b3c0 ID |
2314 | .set_antenna = rt2x00mac_set_antenna, |
2315 | .get_antenna = rt2x00mac_get_antenna, | |
e7dee444 | 2316 | .get_ringparam = rt2x00mac_get_ringparam, |
95ea3627 ID |
2317 | }; |
2318 | ||
2319 | static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { | |
2320 | .probe_hw = rt73usb_probe_hw, | |
2321 | .get_firmware_name = rt73usb_get_firmware_name, | |
0cbe0064 | 2322 | .check_firmware = rt73usb_check_firmware, |
95ea3627 ID |
2323 | .load_firmware = rt73usb_load_firmware, |
2324 | .initialize = rt2x00usb_initialize, | |
2325 | .uninitialize = rt2x00usb_uninitialize, | |
798b7adb | 2326 | .clear_entry = rt2x00usb_clear_entry, |
95ea3627 | 2327 | .set_device_state = rt73usb_set_device_state, |
7396faf4 | 2328 | .rfkill_poll = rt73usb_rfkill_poll, |
95ea3627 ID |
2329 | .link_stats = rt73usb_link_stats, |
2330 | .reset_tuner = rt73usb_reset_tuner, | |
2331 | .link_tuner = rt73usb_link_tuner, | |
c965c74b | 2332 | .watchdog = rt2x00usb_watchdog, |
dbba306f ID |
2333 | .start_queue = rt73usb_start_queue, |
2334 | .kick_queue = rt2x00usb_kick_queue, | |
2335 | .stop_queue = rt73usb_stop_queue, | |
5be65609 | 2336 | .flush_queue = rt2x00usb_flush_queue, |
95ea3627 | 2337 | .write_tx_desc = rt73usb_write_tx_desc, |
bd88a781 | 2338 | .write_beacon = rt73usb_write_beacon, |
69cf36a4 | 2339 | .clear_beacon = rt73usb_clear_beacon, |
dd9fa2d2 | 2340 | .get_tx_data_len = rt73usb_get_tx_data_len, |
95ea3627 | 2341 | .fill_rxdone = rt73usb_fill_rxdone, |
906c110f ID |
2342 | .config_shared_key = rt73usb_config_shared_key, |
2343 | .config_pairwise_key = rt73usb_config_pairwise_key, | |
3a643d24 | 2344 | .config_filter = rt73usb_config_filter, |
6bb40dd1 | 2345 | .config_intf = rt73usb_config_intf, |
72810379 | 2346 | .config_erp = rt73usb_config_erp, |
e4ea1c40 | 2347 | .config_ant = rt73usb_config_ant, |
95ea3627 ID |
2348 | .config = rt73usb_config, |
2349 | }; | |
2350 | ||
181d6902 | 2351 | static const struct data_queue_desc rt73usb_queue_rx = { |
efd2f271 | 2352 | .entry_num = 32, |
181d6902 ID |
2353 | .data_size = DATA_FRAME_SIZE, |
2354 | .desc_size = RXD_DESC_SIZE, | |
b8be63ff | 2355 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2356 | }; |
2357 | ||
2358 | static const struct data_queue_desc rt73usb_queue_tx = { | |
efd2f271 | 2359 | .entry_num = 32, |
181d6902 ID |
2360 | .data_size = DATA_FRAME_SIZE, |
2361 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 2362 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2363 | }; |
2364 | ||
2365 | static const struct data_queue_desc rt73usb_queue_bcn = { | |
efd2f271 | 2366 | .entry_num = 4, |
181d6902 ID |
2367 | .data_size = MGMT_FRAME_SIZE, |
2368 | .desc_size = TXINFO_SIZE, | |
b8be63ff | 2369 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2370 | }; |
2371 | ||
95ea3627 | 2372 | static const struct rt2x00_ops rt73usb_ops = { |
04d0362e GW |
2373 | .name = KBUILD_MODNAME, |
2374 | .max_sta_intf = 1, | |
2375 | .max_ap_intf = 4, | |
2376 | .eeprom_size = EEPROM_SIZE, | |
2377 | .rf_size = RF_SIZE, | |
2378 | .tx_queues = NUM_TX_QUEUES, | |
e6218cc4 | 2379 | .extra_tx_headroom = TXD_DESC_SIZE, |
04d0362e GW |
2380 | .rx = &rt73usb_queue_rx, |
2381 | .tx = &rt73usb_queue_tx, | |
2382 | .bcn = &rt73usb_queue_bcn, | |
2383 | .lib = &rt73usb_rt2x00_ops, | |
2384 | .hw = &rt73usb_mac80211_ops, | |
95ea3627 | 2385 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
04d0362e | 2386 | .debugfs = &rt73usb_rt2x00debug, |
95ea3627 ID |
2387 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
2388 | }; | |
2389 | ||
2390 | /* | |
2391 | * rt73usb module information. | |
2392 | */ | |
2393 | static struct usb_device_id rt73usb_device_table[] = { | |
2394 | /* AboCom */ | |
e01ae27f GW |
2395 | { USB_DEVICE(0x07b8, 0xb21b) }, |
2396 | { USB_DEVICE(0x07b8, 0xb21c) }, | |
2397 | { USB_DEVICE(0x07b8, 0xb21d) }, | |
2398 | { USB_DEVICE(0x07b8, 0xb21e) }, | |
2399 | { USB_DEVICE(0x07b8, 0xb21f) }, | |
ef4bb70d | 2400 | /* AL */ |
e01ae27f | 2401 | { USB_DEVICE(0x14b2, 0x3c10) }, |
144d9ad9 | 2402 | /* Amigo */ |
e01ae27f GW |
2403 | { USB_DEVICE(0x148f, 0x9021) }, |
2404 | { USB_DEVICE(0x0eb0, 0x9021) }, | |
ef4bb70d | 2405 | /* AMIT */ |
e01ae27f | 2406 | { USB_DEVICE(0x18c5, 0x0002) }, |
95ea3627 | 2407 | /* Askey */ |
e01ae27f | 2408 | { USB_DEVICE(0x1690, 0x0722) }, |
95ea3627 | 2409 | /* ASUS */ |
e01ae27f GW |
2410 | { USB_DEVICE(0x0b05, 0x1723) }, |
2411 | { USB_DEVICE(0x0b05, 0x1724) }, | |
95ea3627 | 2412 | /* Belkin */ |
e01ae27f GW |
2413 | { USB_DEVICE(0x050d, 0x705a) }, |
2414 | { USB_DEVICE(0x050d, 0x905b) }, | |
2415 | { USB_DEVICE(0x050d, 0x905c) }, | |
95ea3627 | 2416 | /* Billionton */ |
e01ae27f GW |
2417 | { USB_DEVICE(0x1631, 0xc019) }, |
2418 | { USB_DEVICE(0x08dd, 0x0120) }, | |
95ea3627 | 2419 | /* Buffalo */ |
e01ae27f GW |
2420 | { USB_DEVICE(0x0411, 0x00d8) }, |
2421 | { USB_DEVICE(0x0411, 0x00d9) }, | |
2422 | { USB_DEVICE(0x0411, 0x00f4) }, | |
2423 | { USB_DEVICE(0x0411, 0x0116) }, | |
2424 | { USB_DEVICE(0x0411, 0x0119) }, | |
2425 | { USB_DEVICE(0x0411, 0x0137) }, | |
51b2853f | 2426 | /* CEIVA */ |
e01ae27f | 2427 | { USB_DEVICE(0x178d, 0x02be) }, |
95ea3627 | 2428 | /* CNet */ |
e01ae27f GW |
2429 | { USB_DEVICE(0x1371, 0x9022) }, |
2430 | { USB_DEVICE(0x1371, 0x9032) }, | |
95ea3627 | 2431 | /* Conceptronic */ |
e01ae27f | 2432 | { USB_DEVICE(0x14b2, 0x3c22) }, |
0a74892b | 2433 | /* Corega */ |
e01ae27f | 2434 | { USB_DEVICE(0x07aa, 0x002e) }, |
95ea3627 | 2435 | /* D-Link */ |
e01ae27f GW |
2436 | { USB_DEVICE(0x07d1, 0x3c03) }, |
2437 | { USB_DEVICE(0x07d1, 0x3c04) }, | |
2438 | { USB_DEVICE(0x07d1, 0x3c06) }, | |
2439 | { USB_DEVICE(0x07d1, 0x3c07) }, | |
ef4bb70d | 2440 | /* Edimax */ |
e01ae27f GW |
2441 | { USB_DEVICE(0x7392, 0x7318) }, |
2442 | { USB_DEVICE(0x7392, 0x7618) }, | |
ef4bb70d | 2443 | /* EnGenius */ |
e01ae27f | 2444 | { USB_DEVICE(0x1740, 0x3701) }, |
95ea3627 | 2445 | /* Gemtek */ |
e01ae27f | 2446 | { USB_DEVICE(0x15a9, 0x0004) }, |
95ea3627 | 2447 | /* Gigabyte */ |
e01ae27f GW |
2448 | { USB_DEVICE(0x1044, 0x8008) }, |
2449 | { USB_DEVICE(0x1044, 0x800a) }, | |
95ea3627 | 2450 | /* Huawei-3Com */ |
e01ae27f | 2451 | { USB_DEVICE(0x1472, 0x0009) }, |
95ea3627 | 2452 | /* Hercules */ |
e01ae27f GW |
2453 | { USB_DEVICE(0x06f8, 0xe002) }, |
2454 | { USB_DEVICE(0x06f8, 0xe010) }, | |
2455 | { USB_DEVICE(0x06f8, 0xe020) }, | |
95ea3627 | 2456 | /* Linksys */ |
e01ae27f GW |
2457 | { USB_DEVICE(0x13b1, 0x0020) }, |
2458 | { USB_DEVICE(0x13b1, 0x0023) }, | |
2459 | { USB_DEVICE(0x13b1, 0x0028) }, | |
95ea3627 | 2460 | /* MSI */ |
e01ae27f GW |
2461 | { USB_DEVICE(0x0db0, 0x4600) }, |
2462 | { USB_DEVICE(0x0db0, 0x6877) }, | |
2463 | { USB_DEVICE(0x0db0, 0x6874) }, | |
2464 | { USB_DEVICE(0x0db0, 0xa861) }, | |
2465 | { USB_DEVICE(0x0db0, 0xa874) }, | |
22720645 | 2466 | /* Ovislink */ |
e01ae27f | 2467 | { USB_DEVICE(0x1b75, 0x7318) }, |
95ea3627 | 2468 | /* Ralink */ |
e01ae27f GW |
2469 | { USB_DEVICE(0x04bb, 0x093d) }, |
2470 | { USB_DEVICE(0x148f, 0x2573) }, | |
2471 | { USB_DEVICE(0x148f, 0x2671) }, | |
2472 | { USB_DEVICE(0x0812, 0x3101) }, | |
95ea3627 | 2473 | /* Qcom */ |
e01ae27f GW |
2474 | { USB_DEVICE(0x18e8, 0x6196) }, |
2475 | { USB_DEVICE(0x18e8, 0x6229) }, | |
2476 | { USB_DEVICE(0x18e8, 0x6238) }, | |
ef4bb70d | 2477 | /* Samsung */ |
e01ae27f | 2478 | { USB_DEVICE(0x04e8, 0x4471) }, |
95ea3627 | 2479 | /* Senao */ |
e01ae27f | 2480 | { USB_DEVICE(0x1740, 0x7100) }, |
95ea3627 | 2481 | /* Sitecom */ |
e01ae27f GW |
2482 | { USB_DEVICE(0x0df6, 0x0024) }, |
2483 | { USB_DEVICE(0x0df6, 0x0027) }, | |
2484 | { USB_DEVICE(0x0df6, 0x002f) }, | |
2485 | { USB_DEVICE(0x0df6, 0x90ac) }, | |
2486 | { USB_DEVICE(0x0df6, 0x9712) }, | |
95ea3627 | 2487 | /* Surecom */ |
e01ae27f | 2488 | { USB_DEVICE(0x0769, 0x31f3) }, |
14344b81 | 2489 | /* Tilgin */ |
e01ae27f | 2490 | { USB_DEVICE(0x6933, 0x5001) }, |
ef4bb70d | 2491 | /* Philips */ |
e01ae27f | 2492 | { USB_DEVICE(0x0471, 0x200a) }, |
95ea3627 | 2493 | /* Planex */ |
e01ae27f GW |
2494 | { USB_DEVICE(0x2019, 0xab01) }, |
2495 | { USB_DEVICE(0x2019, 0xab50) }, | |
22720645 | 2496 | /* WideTell */ |
e01ae27f | 2497 | { USB_DEVICE(0x7167, 0x3840) }, |
ef4bb70d | 2498 | /* Zcom */ |
e01ae27f | 2499 | { USB_DEVICE(0x0cde, 0x001c) }, |
144d9ad9 | 2500 | /* ZyXEL */ |
e01ae27f | 2501 | { USB_DEVICE(0x0586, 0x3415) }, |
95ea3627 ID |
2502 | { 0, } |
2503 | }; | |
2504 | ||
2505 | MODULE_AUTHOR(DRV_PROJECT); | |
2506 | MODULE_VERSION(DRV_VERSION); | |
2507 | MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver."); | |
2508 | MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards"); | |
2509 | MODULE_DEVICE_TABLE(usb, rt73usb_device_table); | |
2510 | MODULE_FIRMWARE(FIRMWARE_RT2571); | |
2511 | MODULE_LICENSE("GPL"); | |
2512 | ||
e01ae27f GW |
2513 | static int rt73usb_probe(struct usb_interface *usb_intf, |
2514 | const struct usb_device_id *id) | |
2515 | { | |
2516 | return rt2x00usb_probe(usb_intf, &rt73usb_ops); | |
2517 | } | |
2518 | ||
95ea3627 | 2519 | static struct usb_driver rt73usb_driver = { |
2360157c | 2520 | .name = KBUILD_MODNAME, |
95ea3627 | 2521 | .id_table = rt73usb_device_table, |
e01ae27f | 2522 | .probe = rt73usb_probe, |
95ea3627 ID |
2523 | .disconnect = rt2x00usb_disconnect, |
2524 | .suspend = rt2x00usb_suspend, | |
2525 | .resume = rt2x00usb_resume, | |
2526 | }; | |
2527 | ||
2528 | static int __init rt73usb_init(void) | |
2529 | { | |
2530 | return usb_register(&rt73usb_driver); | |
2531 | } | |
2532 | ||
2533 | static void __exit rt73usb_exit(void) | |
2534 | { | |
2535 | usb_deregister(&rt73usb_driver); | |
2536 | } | |
2537 | ||
2538 | module_init(rt73usb_init); | |
2539 | module_exit(rt73usb_exit); |