include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-block.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
9c9a0d14
GW
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
4 <http://rt2x00.serialmonkey.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the
18 Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22/*
23 Module: rt2x00lib
24 Abstract: rt2x00 queue specific routines.
25 */
26
5a0e3ad6 27#include <linux/slab.h>
181d6902
ID
28#include <linux/kernel.h>
29#include <linux/module.h>
c4da0048 30#include <linux/dma-mapping.h>
181d6902
ID
31
32#include "rt2x00.h"
33#include "rt2x00lib.h"
34
c4da0048
GW
35struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
36 struct queue_entry *entry)
239c249d 37{
c4da0048
GW
38 struct sk_buff *skb;
39 struct skb_frame_desc *skbdesc;
2bb057d0
ID
40 unsigned int frame_size;
41 unsigned int head_size = 0;
42 unsigned int tail_size = 0;
239c249d
GW
43
44 /*
45 * The frame size includes descriptor size, because the
46 * hardware directly receive the frame into the skbuffer.
47 */
c4da0048 48 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
49
50 /*
ff352391
ID
51 * The payload should be aligned to a 4-byte boundary,
52 * this means we need at least 3 bytes for moving the frame
53 * into the correct offset.
239c249d 54 */
2bb057d0
ID
55 head_size = 4;
56
57 /*
58 * For IV/EIV/ICV assembly we must make sure there is
59 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 60 * and 8 bytes for ICV data as tailroon.
2bb057d0 61 */
2bb057d0
ID
62 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
63 head_size += 8;
9c3444d3 64 tail_size += 8;
2bb057d0 65 }
239c249d
GW
66
67 /*
68 * Allocate skbuffer.
69 */
2bb057d0 70 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
71 if (!skb)
72 return NULL;
73
2bb057d0
ID
74 /*
75 * Make sure we not have a frame with the requested bytes
76 * available in the head and tail.
77 */
78 skb_reserve(skb, head_size);
239c249d
GW
79 skb_put(skb, frame_size);
80
c4da0048
GW
81 /*
82 * Populate skbdesc.
83 */
84 skbdesc = get_skb_frame_desc(skb);
85 memset(skbdesc, 0, sizeof(*skbdesc));
86 skbdesc->entry = entry;
87
88 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
89 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
90 skb->data,
91 skb->len,
92 DMA_FROM_DEVICE);
93 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
94 }
95
239c249d
GW
96 return skb;
97}
30caa6e3 98
c4da0048 99void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 100{
c4da0048
GW
101 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
102
3ee54a07
ID
103 /*
104 * If device has requested headroom, we should make sure that
105 * is also mapped to the DMA so it can be used for transfering
106 * additional descriptor information to the hardware.
107 */
b59a52f1 108 skb_push(skb, rt2x00dev->ops->extra_tx_headroom);
3ee54a07
ID
109
110 skbdesc->skb_dma =
111 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
112
113 /*
114 * Restore data pointer to original location again.
115 */
b59a52f1 116 skb_pull(skb, rt2x00dev->ops->extra_tx_headroom);
3ee54a07 117
c4da0048
GW
118 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
119}
120EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
121
122void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
123{
124 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
125
126 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
127 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
128 DMA_FROM_DEVICE);
129 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
130 }
131
132 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
3ee54a07
ID
133 /*
134 * Add headroom to the skb length, it has been removed
135 * by the driver, but it was actually mapped to DMA.
136 */
137 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
b59a52f1 138 skb->len + rt2x00dev->ops->extra_tx_headroom,
c4da0048
GW
139 DMA_TO_DEVICE);
140 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
141 }
142}
c4da0048
GW
143
144void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
145{
9a613195
ID
146 if (!skb)
147 return;
148
61243d8e 149 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
150 dev_kfree_skb_any(skb);
151}
239c249d 152
daee6c09 153void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 154{
9f166171 155 unsigned int frame_length = skb->len;
daee6c09 156 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
157
158 if (!align)
159 return;
160
daee6c09
ID
161 skb_push(skb, align);
162 memmove(skb->data, skb->data + align, frame_length);
163 skb_trim(skb, frame_length);
164}
165
95d69aa0 166void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
daee6c09
ID
167{
168 unsigned int frame_length = skb->len;
95d69aa0 169 unsigned int align = ALIGN_SIZE(skb, header_length);
daee6c09
ID
170
171 if (!align)
172 return;
173
174 skb_push(skb, align);
175 memmove(skb->data, skb->data + align, frame_length);
176 skb_trim(skb, frame_length);
177}
178
179void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
180{
2e331462 181 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
182 unsigned int header_align = ALIGN_SIZE(skb, 0);
183 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 184 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 185
2e331462
GW
186 /*
187 * Adjust the header alignment if the payload needs to be moved more
188 * than the header.
189 */
190 if (payload_align > header_align)
191 header_align += 4;
192
193 /* There is nothing to do if no alignment is needed */
194 if (!header_align)
195 return;
daee6c09 196
2e331462
GW
197 /* Reserve the amount of space needed in front of the frame */
198 skb_push(skb, header_align);
199
200 /*
201 * Move the header.
202 */
203 memmove(skb->data, skb->data + header_align, header_length);
204
205 /* Move the payload, if present and if required */
206 if (payload_length && payload_align)
daee6c09 207 memmove(skb->data + header_length + l2pad,
a5186e99 208 skb->data + header_length + l2pad + payload_align,
2e331462
GW
209 payload_length);
210
211 /* Trim the skb to the correct size */
212 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
213}
214
daee6c09
ID
215void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
216{
77e73d18 217 unsigned int l2pad = L2PAD_SIZE(header_length);
daee6c09 218
354e39db 219 if (!l2pad)
daee6c09
ID
220 return;
221
222 memmove(skb->data + l2pad, skb->data, header_length);
223 skb_pull(skb, l2pad);
224}
225
7b40982e
ID
226static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
227 struct txentry_desc *txdesc)
228{
229 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
230 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
231 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
232 unsigned long irqflags;
233
234 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
235 unlikely(!tx_info->control.vif))
236 return;
237
238 /*
239 * Hardware should insert sequence counter.
240 * FIXME: We insert a software sequence counter first for
241 * hardware that doesn't support hardware sequence counting.
242 *
243 * This is wrong because beacons are not getting sequence
244 * numbers assigned properly.
245 *
246 * A secondary problem exists for drivers that cannot toggle
247 * sequence counting per-frame, since those will override the
248 * sequence counter given by mac80211.
249 */
250 spin_lock_irqsave(&intf->seqlock, irqflags);
251
252 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
253 intf->seqno += 0x10;
254 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
255 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
256
257 spin_unlock_irqrestore(&intf->seqlock, irqflags);
258
259 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
260}
261
262static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
263 struct txentry_desc *txdesc,
264 const struct rt2x00_rate *hwrate)
265{
266 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
267 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
268 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
269 unsigned int data_length;
270 unsigned int duration;
271 unsigned int residual;
272
273 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
274 data_length = entry->skb->len + 4;
275 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
276
277 /*
278 * PLCP setup
279 * Length calculation depends on OFDM/CCK rate.
280 */
281 txdesc->signal = hwrate->plcp;
282 txdesc->service = 0x04;
283
284 if (hwrate->flags & DEV_RATE_OFDM) {
285 txdesc->length_high = (data_length >> 6) & 0x3f;
286 txdesc->length_low = data_length & 0x3f;
287 } else {
288 /*
289 * Convert length to microseconds.
290 */
291 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
292 duration = GET_DURATION(data_length, hwrate->bitrate);
293
294 if (residual != 0) {
295 duration++;
296
297 /*
298 * Check if we need to set the Length Extension
299 */
300 if (hwrate->bitrate == 110 && residual <= 30)
301 txdesc->service |= 0x80;
302 }
303
304 txdesc->length_high = (duration >> 8) & 0xff;
305 txdesc->length_low = duration & 0xff;
306
307 /*
308 * When preamble is enabled we should set the
309 * preamble bit for the signal.
310 */
311 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
312 txdesc->signal |= 0x08;
313 }
314}
315
bd88a781
ID
316static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
317 struct txentry_desc *txdesc)
7050ec82 318{
2e92e6f2 319 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 320 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 321 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 322 struct ieee80211_rate *rate =
e039fa4a 323 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82 324 const struct rt2x00_rate *hwrate;
7050ec82
ID
325
326 memset(txdesc, 0, sizeof(*txdesc));
327
328 /*
329 * Initialize information from queue
330 */
331 txdesc->queue = entry->queue->qid;
332 txdesc->cw_min = entry->queue->cw_min;
333 txdesc->cw_max = entry->queue->cw_max;
334 txdesc->aifs = entry->queue->aifs;
335
9f166171
ID
336 /*
337 * Header and alignment information.
338 */
339 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
2e331462
GW
340 if (test_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags) &&
341 (entry->skb->len > txdesc->header_length))
77e73d18 342 txdesc->l2pad = L2PAD_SIZE(txdesc->header_length);
9f166171 343
7050ec82
ID
344 /*
345 * Check whether this frame is to be acked.
346 */
e039fa4a 347 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
348 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
349
350 /*
351 * Check if this is a RTS/CTS frame
352 */
ac104462
ID
353 if (ieee80211_is_rts(hdr->frame_control) ||
354 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 355 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 356 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 357 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 358 else
7050ec82 359 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 360 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 361 rate =
e039fa4a 362 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
363 }
364
365 /*
366 * Determine retry information.
367 */
e6a9854b 368 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 369 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
370 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
371
372 /*
373 * Check if more fragments are pending
374 */
267e8987
ID
375 if (ieee80211_has_morefrags(hdr->frame_control) ||
376 (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)) {
7050ec82
ID
377 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
378 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
379 }
380
381 /*
382 * Beacons and probe responses require the tsf timestamp
e81e0aef
AB
383 * to be inserted into the frame, except for a frame that has been injected
384 * through a monitor interface. This latter is needed for testing a
385 * monitor interface.
7050ec82 386 */
e81e0aef
AB
387 if ((ieee80211_is_beacon(hdr->frame_control) ||
388 ieee80211_is_probe_resp(hdr->frame_control)) &&
389 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
7050ec82
ID
390 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
391
392 /*
393 * Determine with what IFS priority this frame should be send.
394 * Set ifs to IFS_SIFS when the this is not the first fragment,
395 * or this fragment came after RTS/CTS.
396 */
7b40982e
ID
397 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
398 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
7050ec82
ID
399 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
400 txdesc->ifs = IFS_BACKOFF;
7b40982e 401 } else
7050ec82 402 txdesc->ifs = IFS_SIFS;
7050ec82 403
076f9582
ID
404 /*
405 * Determine rate modulation.
406 */
7050ec82 407 hwrate = rt2x00_get_rate(rate->hw_value);
076f9582 408 txdesc->rate_mode = RATE_MODE_CCK;
7b40982e 409 if (hwrate->flags & DEV_RATE_OFDM)
076f9582 410 txdesc->rate_mode = RATE_MODE_OFDM;
7050ec82 411
7b40982e
ID
412 /*
413 * Apply TX descriptor handling by components
414 */
415 rt2x00crypto_create_tx_descriptor(entry, txdesc);
35f00cfc 416 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
7b40982e
ID
417 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
418 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
7050ec82 419}
7050ec82 420
bd88a781
ID
421static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
422 struct txentry_desc *txdesc)
7050ec82 423{
b869767b
ID
424 struct data_queue *queue = entry->queue;
425 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
426
427 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
428
429 /*
430 * All processing on the frame has been completed, this means
431 * it is now ready to be dumped to userspace through debugfs.
432 */
433 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
434
435 /*
b869767b
ID
436 * Check if we need to kick the queue, there are however a few rules
437 * 1) Don't kick beacon queue
438 * 2) Don't kick unless this is the last in frame in a burst.
439 * When the burst flag is set, this frame is always followed
440 * by another frame which in some way are related to eachother.
441 * This is true for fragments, RTS or CTS-to-self frames.
442 * 3) Rule 2 can be broken when the available entries
443 * in the queue are less then a certain threshold.
7050ec82 444 */
b869767b
ID
445 if (entry->queue->qid == QID_BEACON)
446 return;
447
448 if (rt2x00queue_threshold(queue) ||
449 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
450 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 451}
7050ec82 452
7351c6bd
JB
453int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
454 bool local)
6db3786a 455{
e6a9854b 456 struct ieee80211_tx_info *tx_info;
6db3786a
ID
457 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
458 struct txentry_desc txdesc;
d74f5ba4 459 struct skb_frame_desc *skbdesc;
e6a9854b 460 u8 rate_idx, rate_flags;
6db3786a
ID
461
462 if (unlikely(rt2x00queue_full(queue)))
0e3de998 463 return -ENOBUFS;
6db3786a 464
0262ab0d 465 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
466 ERROR(queue->rt2x00dev,
467 "Arrived at non-free entry in the non-full queue %d.\n"
468 "Please file bug report to %s.\n",
469 queue->qid, DRV_PROJECT);
470 return -EINVAL;
471 }
472
473 /*
474 * Copy all TX descriptor information into txdesc,
475 * after that we are free to use the skb->cb array
476 * for our information.
477 */
478 entry->skb = skb;
479 rt2x00queue_create_tx_descriptor(entry, &txdesc);
480
d74f5ba4 481 /*
e6a9854b 482 * All information is retrieved from the skb->cb array,
2bb057d0 483 * now we should claim ownership of the driver part of that
e6a9854b 484 * array, preserving the bitrate index and flags.
d74f5ba4 485 */
e6a9854b
JB
486 tx_info = IEEE80211_SKB_CB(skb);
487 rate_idx = tx_info->control.rates[0].idx;
488 rate_flags = tx_info->control.rates[0].flags;
0e3de998 489 skbdesc = get_skb_frame_desc(skb);
d74f5ba4
ID
490 memset(skbdesc, 0, sizeof(*skbdesc));
491 skbdesc->entry = entry;
e6a9854b
JB
492 skbdesc->tx_rate_idx = rate_idx;
493 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 494
7351c6bd
JB
495 if (local)
496 skbdesc->flags |= SKBDESC_NOT_MAC80211;
497
2bb057d0
ID
498 /*
499 * When hardware encryption is supported, and this frame
500 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 501 * the frame so we can provide it to the driver separately.
2bb057d0
ID
502 */
503 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 504 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
3f787bd6 505 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
9eb4e21e 506 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 507 else
9eb4e21e 508 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 509 }
2bb057d0 510
93354cbb
ID
511 /*
512 * When DMA allocation is required we should guarentee to the
513 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
514 * However some drivers require L2 padding to pad the payload
515 * rather then the header. This could be a requirement for
516 * PCI and USB devices, while header alignment only is valid
517 * for PCI devices.
518 */
9f166171 519 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
daee6c09 520 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length);
93354cbb 521 else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
daee6c09 522 rt2x00queue_align_frame(entry->skb);
9f166171 523
2bb057d0
ID
524 /*
525 * It could be possible that the queue was corrupted and this
0e3de998
ID
526 * call failed. Since we always return NETDEV_TX_OK to mac80211,
527 * this frame will simply be dropped.
2bb057d0 528 */
6db3786a 529 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
0262ab0d 530 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 531 entry->skb = NULL;
0e3de998 532 return -EIO;
6db3786a
ID
533 }
534
d74f5ba4
ID
535 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
536 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
537
0262ab0d 538 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
539
540 rt2x00queue_index_inc(queue, Q_INDEX);
541 rt2x00queue_write_tx_descriptor(entry, &txdesc);
542
543 return 0;
544}
545
bd88a781 546int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
a2c9b652
ID
547 struct ieee80211_vif *vif,
548 const bool enable_beacon)
bd88a781
ID
549{
550 struct rt2x00_intf *intf = vif_to_intf(vif);
551 struct skb_frame_desc *skbdesc;
552 struct txentry_desc txdesc;
553 __le32 desc[16];
554
555 if (unlikely(!intf->beacon))
556 return -ENOBUFS;
557
17512dc3
IP
558 mutex_lock(&intf->beacon_skb_mutex);
559
560 /*
561 * Clean up the beacon skb.
562 */
563 rt2x00queue_free_skb(rt2x00dev, intf->beacon->skb);
564 intf->beacon->skb = NULL;
565
a2c9b652
ID
566 if (!enable_beacon) {
567 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_BEACON);
17512dc3 568 mutex_unlock(&intf->beacon_skb_mutex);
a2c9b652
ID
569 return 0;
570 }
571
bd88a781 572 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
17512dc3
IP
573 if (!intf->beacon->skb) {
574 mutex_unlock(&intf->beacon_skb_mutex);
bd88a781 575 return -ENOMEM;
17512dc3 576 }
bd88a781
ID
577
578 /*
579 * Copy all TX descriptor information into txdesc,
580 * after that we are free to use the skb->cb array
581 * for our information.
582 */
583 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
584
585 /*
586 * For the descriptor we use a local array from where the
587 * driver can move it to the correct location required for
588 * the hardware.
589 */
590 memset(desc, 0, sizeof(desc));
591
592 /*
593 * Fill in skb descriptor
594 */
595 skbdesc = get_skb_frame_desc(intf->beacon->skb);
596 memset(skbdesc, 0, sizeof(*skbdesc));
597 skbdesc->desc = desc;
598 skbdesc->desc_len = intf->beacon->queue->desc_size;
599 skbdesc->entry = intf->beacon;
600
601 /*
602 * Write TX descriptor into reserved room in front of the beacon.
603 */
604 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
605
606 /*
607 * Send beacon to hardware.
608 * Also enable beacon generation, which might have been disabled
609 * by the driver during the config_beacon() callback function.
610 */
611 rt2x00dev->ops->lib->write_beacon(intf->beacon);
612 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
613
17512dc3
IP
614 mutex_unlock(&intf->beacon_skb_mutex);
615
bd88a781
ID
616 return 0;
617}
618
181d6902 619struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 620 const enum data_queue_qid queue)
181d6902
ID
621{
622 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
623
a2c9b652
ID
624 if (queue == QID_RX)
625 return rt2x00dev->rx;
626
61448f88 627 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
628 return &rt2x00dev->tx[queue];
629
630 if (!rt2x00dev->bcn)
631 return NULL;
632
e58c6aca 633 if (queue == QID_BEACON)
181d6902 634 return &rt2x00dev->bcn[0];
e58c6aca 635 else if (queue == QID_ATIM && atim)
181d6902
ID
636 return &rt2x00dev->bcn[1];
637
638 return NULL;
639}
640EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
641
642struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
643 enum queue_index index)
644{
645 struct queue_entry *entry;
5f46c4d0 646 unsigned long irqflags;
181d6902
ID
647
648 if (unlikely(index >= Q_INDEX_MAX)) {
649 ERROR(queue->rt2x00dev,
650 "Entry requested from invalid index type (%d)\n", index);
651 return NULL;
652 }
653
5f46c4d0 654 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
655
656 entry = &queue->entries[queue->index[index]];
657
5f46c4d0 658 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
659
660 return entry;
661}
662EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
663
664void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
665{
5f46c4d0
ID
666 unsigned long irqflags;
667
181d6902
ID
668 if (unlikely(index >= Q_INDEX_MAX)) {
669 ERROR(queue->rt2x00dev,
670 "Index change on invalid index type (%d)\n", index);
671 return;
672 }
673
5f46c4d0 674 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
675
676 queue->index[index]++;
677 if (queue->index[index] >= queue->limit)
678 queue->index[index] = 0;
679
10b6b801
ID
680 if (index == Q_INDEX) {
681 queue->length++;
682 } else if (index == Q_INDEX_DONE) {
683 queue->length--;
55887511 684 queue->count++;
10b6b801 685 }
181d6902 686
5f46c4d0 687 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 688}
181d6902
ID
689
690static void rt2x00queue_reset(struct data_queue *queue)
691{
5f46c4d0
ID
692 unsigned long irqflags;
693
694 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
695
696 queue->count = 0;
697 queue->length = 0;
698 memset(queue->index, 0, sizeof(queue->index));
699
5f46c4d0 700 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
701}
702
a2c9b652
ID
703void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
704{
705 struct data_queue *queue;
706
707 txall_queue_for_each(rt2x00dev, queue)
708 rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, queue->qid);
709}
710
798b7adb 711void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
712{
713 struct data_queue *queue;
714 unsigned int i;
715
798b7adb 716 queue_for_each(rt2x00dev, queue) {
181d6902
ID
717 rt2x00queue_reset(queue);
718
9c0ab712
ID
719 for (i = 0; i < queue->limit; i++) {
720 queue->entries[i].flags = 0;
721
798b7adb 722 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
9c0ab712 723 }
181d6902
ID
724 }
725}
726
727static int rt2x00queue_alloc_entries(struct data_queue *queue,
728 const struct data_queue_desc *qdesc)
729{
730 struct queue_entry *entries;
731 unsigned int entry_size;
732 unsigned int i;
733
734 rt2x00queue_reset(queue);
735
736 queue->limit = qdesc->entry_num;
b869767b 737 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
738 queue->data_size = qdesc->data_size;
739 queue->desc_size = qdesc->desc_size;
740
741 /*
742 * Allocate all queue entries.
743 */
744 entry_size = sizeof(*entries) + qdesc->priv_size;
745 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
746 if (!entries)
747 return -ENOMEM;
748
749#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
750 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
751 ((__index) * (__psize)) )
181d6902
ID
752
753 for (i = 0; i < queue->limit; i++) {
754 entries[i].flags = 0;
755 entries[i].queue = queue;
756 entries[i].skb = NULL;
757 entries[i].entry_idx = i;
758 entries[i].priv_data =
759 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
760 sizeof(*entries), qdesc->priv_size);
761 }
762
763#undef QUEUE_ENTRY_PRIV_OFFSET
764
765 queue->entries = entries;
766
767 return 0;
768}
769
c4da0048
GW
770static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
771 struct data_queue *queue)
30caa6e3
GW
772{
773 unsigned int i;
774
775 if (!queue->entries)
776 return;
777
778 for (i = 0; i < queue->limit; i++) {
779 if (queue->entries[i].skb)
c4da0048 780 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
30caa6e3
GW
781 }
782}
783
c4da0048
GW
784static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
785 struct data_queue *queue)
30caa6e3
GW
786{
787 unsigned int i;
788 struct sk_buff *skb;
789
790 for (i = 0; i < queue->limit; i++) {
c4da0048 791 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 792 if (!skb)
61243d8e 793 return -ENOMEM;
30caa6e3
GW
794 queue->entries[i].skb = skb;
795 }
796
797 return 0;
30caa6e3
GW
798}
799
181d6902
ID
800int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
801{
802 struct data_queue *queue;
803 int status;
804
181d6902
ID
805 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
806 if (status)
807 goto exit;
808
809 tx_queue_for_each(rt2x00dev, queue) {
810 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
811 if (status)
812 goto exit;
813 }
814
815 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
816 if (status)
817 goto exit;
818
30caa6e3
GW
819 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
820 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
821 rt2x00dev->ops->atim);
822 if (status)
823 goto exit;
824 }
181d6902 825
c4da0048 826 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
181d6902
ID
827 if (status)
828 goto exit;
829
830 return 0;
831
832exit:
833 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
834
835 rt2x00queue_uninitialize(rt2x00dev);
836
837 return status;
838}
839
840void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
841{
842 struct data_queue *queue;
843
c4da0048 844 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 845
181d6902
ID
846 queue_for_each(rt2x00dev, queue) {
847 kfree(queue->entries);
848 queue->entries = NULL;
849 }
850}
851
8f539276
ID
852static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
853 struct data_queue *queue, enum data_queue_qid qid)
854{
855 spin_lock_init(&queue->lock);
856
857 queue->rt2x00dev = rt2x00dev;
858 queue->qid = qid;
2af0a570 859 queue->txop = 0;
8f539276
ID
860 queue->aifs = 2;
861 queue->cw_min = 5;
862 queue->cw_max = 10;
863}
864
181d6902
ID
865int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
866{
867 struct data_queue *queue;
868 enum data_queue_qid qid;
869 unsigned int req_atim =
870 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
871
872 /*
873 * We need the following queues:
874 * RX: 1
61448f88 875 * TX: ops->tx_queues
181d6902
ID
876 * Beacon: 1
877 * Atim: 1 (if required)
878 */
61448f88 879 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902
ID
880
881 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
882 if (!queue) {
883 ERROR(rt2x00dev, "Queue allocation failed.\n");
884 return -ENOMEM;
885 }
886
887 /*
888 * Initialize pointers
889 */
890 rt2x00dev->rx = queue;
891 rt2x00dev->tx = &queue[1];
61448f88 892 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
181d6902
ID
893
894 /*
895 * Initialize queue parameters.
896 * RX: qid = QID_RX
897 * TX: qid = QID_AC_BE + index
898 * TX: cw_min: 2^5 = 32.
899 * TX: cw_max: 2^10 = 1024.
565a019a
ID
900 * BCN: qid = QID_BEACON
901 * ATIM: qid = QID_ATIM
181d6902 902 */
8f539276 903 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 904
8f539276
ID
905 qid = QID_AC_BE;
906 tx_queue_for_each(rt2x00dev, queue)
907 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 908
565a019a 909 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 910 if (req_atim)
565a019a 911 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
181d6902
ID
912
913 return 0;
914}
915
916void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
917{
918 kfree(rt2x00dev->rx);
919 rt2x00dev->rx = NULL;
920 rt2x00dev->tx = NULL;
921 rt2x00dev->bcn = NULL;
922}