[linux-2.6-block.git] / drivers / net / wireless / rt2x00 / rt2x00pci.c

/*
	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt2x00pci
	Abstract: rt2x00 generic pci device routines.
 */

#include <linux/dma-mapping.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>

#include "rt2x00.h"
#include "rt2x00pci.h"

/*
 * Register access.
 */
int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
			   const unsigned int offset,
			   const struct rt2x00_field32 field,
			   u32 *reg)
{
	unsigned int i;

	if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
		return 0;

	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2x00pci_register_read(rt2x00dev, offset, reg);
		if (!rt2x00_get_field32(*reg, field))
			return 1;
		udelay(REGISTER_BUSY_DELAY);
	}

	ERROR(rt2x00dev, "Indirect register access failed: "
	      "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
	*reg = ~0;

	return 0;
}
EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);

bool rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
{
	struct data_queue *queue = rt2x00dev->rx;
	struct queue_entry *entry;
	struct queue_entry_priv_pci *entry_priv;
	struct skb_frame_desc *skbdesc;
	int max_rx = 16;

	while (--max_rx) {
		entry = rt2x00queue_get_entry(queue, Q_INDEX);
		entry_priv = entry->priv_data;

		if (rt2x00dev->ops->lib->get_entry_state(entry))
			break;

		/*
		 * Fill in desc fields of the skb descriptor
		 */
		skbdesc = get_skb_frame_desc(entry->skb);
		skbdesc->desc = entry_priv->desc;
		skbdesc->desc_len = entry->queue->desc_size;

		/*
		 * DMA is already done, notify rt2x00lib that
		 * it finished successfully.
		 */
		rt2x00lib_dmastart(entry);
		rt2x00lib_dmadone(entry);

		/*
		 * Send the frame to rt2x00lib for further processing.
		 */
		rt2x00lib_rxdone(entry, GFP_ATOMIC);
	}

	return !max_rx;
}
EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);

void rt2x00pci_flush_queue(struct data_queue *queue, bool drop)
{
	unsigned int i;

	for (i = 0; !rt2x00queue_empty(queue) && i < 10; i++)
		msleep(10);
}
EXPORT_SYMBOL_GPL(rt2x00pci_flush_queue);

/*
 * Device initialization handlers.
 */
static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
				     struct data_queue *queue)
{
	struct queue_entry_priv_pci *entry_priv;
	void *addr;
	dma_addr_t dma;
	unsigned int i;

	/*
	 * Allocate DMA memory for descriptor and buffer.
	 */
	addr = dma_alloc_coherent(rt2x00dev->dev,
				  queue->limit * queue->desc_size,
				  &dma, GFP_KERNEL | __GFP_ZERO);
	if (!addr)
		return -ENOMEM;

	/*
	 * Initialize all queue entries to contain valid addresses.
	 */
	for (i = 0; i < queue->limit; i++) {
		entry_priv = queue->entries[i].priv_data;
		entry_priv->desc = addr + i * queue->desc_size;
		entry_priv->desc_dma = dma + i * queue->desc_size;
	}

	return 0;
}

static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
				     struct data_queue *queue)
{
	struct queue_entry_priv_pci *entry_priv =
	    queue->entries[0].priv_data;

	if (entry_priv->desc)
		dma_free_coherent(rt2x00dev->dev,
				  queue->limit * queue->desc_size,
				  entry_priv->desc, entry_priv->desc_dma);
	entry_priv->desc = NULL;
}

int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
{
	struct data_queue *queue;
	int status;

	/*
	 * Allocate DMA
	 */
	queue_for_each(rt2x00dev, queue) {
		status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
		if (status)
			goto exit;
	}

	/*
	 * Register interrupt handler.
	 */
	status = request_irq(rt2x00dev->irq,
			     rt2x00dev->ops->lib->irq_handler,
			     IRQF_SHARED, rt2x00dev->name, rt2x00dev);
	if (status) {
		ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
		      rt2x00dev->irq, status);
		goto exit;
	}

	return 0;

exit:
	queue_for_each(rt2x00dev, queue)
		rt2x00pci_free_queue_dma(rt2x00dev, queue);

	return status;
}
EXPORT_SYMBOL_GPL(rt2x00pci_initialize);

void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
{
	struct data_queue *queue;

	/*
	 * Free irq line.
	 */
	free_irq(rt2x00dev->irq, rt2x00dev);

	/*
	 * Free DMA
	 */
	queue_for_each(rt2x00dev, queue)
		rt2x00pci_free_queue_dma(rt2x00dev, queue);
}
EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);

/*
 * PCI driver handlers.
 */
static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
{
	kfree(rt2x00dev->rf);
	rt2x00dev->rf = NULL;

	kfree(rt2x00dev->eeprom);
	rt2x00dev->eeprom = NULL;

	if (rt2x00dev->csr.base) {
		iounmap(rt2x00dev->csr.base);
		rt2x00dev->csr.base = NULL;
	}
}

static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
{
	struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);

	rt2x00dev->csr.base = pci_ioremap_bar(pci_dev, 0);
	if (!rt2x00dev->csr.base)
		goto exit;

	rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
	if (!rt2x00dev->eeprom)
		goto exit;

	rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
	if (!rt2x00dev->rf)
		goto exit;

	return 0;

exit:
	ERROR_PROBE("Failed to allocate registers.\n");

	rt2x00pci_free_reg(rt2x00dev);

	return -ENOMEM;
}

int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops)
{
	struct ieee80211_hw *hw;
	struct rt2x00_dev *rt2x00dev;
	int retval;
	u16 chip;

	retval = pci_enable_device(pci_dev);
	if (retval) {
		ERROR_PROBE("Enable device failed.\n");
		return retval;
	}

	retval = pci_request_regions(pci_dev, pci_name(pci_dev));
	if (retval) {
		ERROR_PROBE("PCI request regions failed.\n");
		goto exit_disable_device;
	}

	pci_set_master(pci_dev);

	if (pci_set_mwi(pci_dev))
		ERROR_PROBE("MWI not available.\n");

	if (dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
		ERROR_PROBE("PCI DMA not supported.\n");
		retval = -EIO;
		goto exit_release_regions;
	}

	hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
	if (!hw) {
		ERROR_PROBE("Failed to allocate hardware.\n");
		retval = -ENOMEM;
		goto exit_release_regions;
	}

	pci_set_drvdata(pci_dev, hw);

	rt2x00dev = hw->priv;
	rt2x00dev->dev = &pci_dev->dev;
	rt2x00dev->ops = ops;
	rt2x00dev->hw = hw;
	rt2x00dev->irq = pci_dev->irq;
	rt2x00dev->name = pci_name(pci_dev);

	if (pci_is_pcie(pci_dev))
		rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
	else
		rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);

	retval = rt2x00pci_alloc_reg(rt2x00dev);
	if (retval)
		goto exit_free_device;

	/*
	 * Because rt3290 chip use different efuse offset to read efuse data.
	 * So before read efuse it need to indicate it is the
	 * rt3290 or not.
	 */
	pci_read_config_word(pci_dev, PCI_DEVICE_ID, &chip);
	rt2x00dev->chip.rt = chip;

	retval = rt2x00lib_probe_dev(rt2x00dev);
	if (retval)
		goto exit_free_reg;

	return 0;

exit_free_reg:
	rt2x00pci_free_reg(rt2x00dev);

exit_free_device:
	ieee80211_free_hw(hw);

exit_release_regions:
	pci_release_regions(pci_dev);

exit_disable_device:
	pci_disable_device(pci_dev);

	pci_set_drvdata(pci_dev, NULL);

	return retval;
}
EXPORT_SYMBOL_GPL(rt2x00pci_probe);

void rt2x00pci_remove(struct pci_dev *pci_dev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	struct rt2x00_dev *rt2x00dev = hw->priv;

	/*
	 * Free all allocated data.
	 */
	rt2x00lib_remove_dev(rt2x00dev);
	rt2x00pci_free_reg(rt2x00dev);
	ieee80211_free_hw(hw);

	/*
	 * Free the PCI device data.
	 */
	pci_set_drvdata(pci_dev, NULL);
	pci_disable_device(pci_dev);
	pci_release_regions(pci_dev);
}
EXPORT_SYMBOL_GPL(rt2x00pci_remove);

#ifdef CONFIG_PM
int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	struct rt2x00_dev *rt2x00dev = hw->priv;
	int retval;

	retval = rt2x00lib_suspend(rt2x00dev, state);
	if (retval)
		return retval;

	pci_save_state(pci_dev);
	pci_disable_device(pci_dev);
	return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
}
EXPORT_SYMBOL_GPL(rt2x00pci_suspend);

int rt2x00pci_resume(struct pci_dev *pci_dev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	struct rt2x00_dev *rt2x00dev = hw->priv;

	if (pci_set_power_state(pci_dev, PCI_D0) ||
	    pci_enable_device(pci_dev)) {
		ERROR(rt2x00dev, "Failed to resume device.\n");
		return -EIO;
	}

	pci_restore_state(pci_dev);
	return rt2x00lib_resume(rt2x00dev);
}
EXPORT_SYMBOL_GPL(rt2x00pci_resume);
#endif /* CONFIG_PM */

/*
 * rt2x00pci module information.
 */
MODULE_AUTHOR(DRV_PROJECT);
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("rt2x00 pci library");
MODULE_LICENSE("GPL");
Commit	Line	Data
95ea3627	1	/*
9c9a0d14	2	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627 ID	3	<http://rt2x00.serialmonkey.com>
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the
	17	Free Software Foundation, Inc.,
	18	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	19	*/
	20
	21	/*
	22	Module: rt2x00pci
	23	Abstract: rt2x00 generic pci device routines.
	24	*/
	25
95ea3627 ID	26	#include <linux/dma-mapping.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/pci.h>
5a0e3ad6	30	#include <linux/slab.h>
95ea3627 ID	31
	32	#include "rt2x00.h"
	33	#include "rt2x00pci.h"
	34
c9c3b1a5 ID	35	/*
	36	* Register access.
	37	*/
	38	int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
	39	const unsigned int offset,
	40	const struct rt2x00_field32 field,
	41	u32 *reg)
	42	{
	43	unsigned int i;
	44
c70762f9 AB	45	if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
	46	return 0;
	47
c9c3b1a5 ID	48	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
	49	rt2x00pci_register_read(rt2x00dev, offset, reg);
	50	if (!rt2x00_get_field32(*reg, field))
	51	return 1;
	52	udelay(REGISTER_BUSY_DELAY);
	53	}
	54
	55	ERROR(rt2x00dev, "Indirect register access failed: "
	56	"offset=0x%.08x, value=0x%.08x\n", offset, *reg);
	57	*reg = ~0;
	58
	59	return 0;
	60	}
	61	EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);
	62
16638937	63	bool rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
95ea3627	64	{
181d6902 ID	65	struct data_queue *queue = rt2x00dev->rx;
181d6902 ID	66	struct queue_entry *entry;
b8be63ff	67	struct queue_entry_priv_pci *entry_priv;
c4da0048	68	struct skb_frame_desc *skbdesc;
16638937	69	int max_rx = 16;
95ea3627	70
16638937	71	while (--max_rx) {
181d6902	72	entry = rt2x00queue_get_entry(queue, Q_INDEX);
b8be63ff	73	entry_priv = entry->priv_data;
95ea3627	74
798b7adb	75	if (rt2x00dev->ops->lib->get_entry_state(entry))
95ea3627 ID	76	break;
95ea3627 ID	77
c4da0048 GW	78	/*
	79	* Fill in desc fields of the skb descriptor
	80	*/
	81	skbdesc = get_skb_frame_desc(entry->skb);
	82	skbdesc->desc = entry_priv->desc;
	83	skbdesc->desc_len = entry->queue->desc_size;
	84
64e7d723 ID	85	/*
	86	* DMA is already done, notify rt2x00lib that
	87	* it finished successfully.
	88	*/
	89	rt2x00lib_dmastart(entry);
	90	rt2x00lib_dmadone(entry);
	91
c4da0048 GW	92	/*
	93	* Send the frame to rt2x00lib for further processing.
	94	*/
88211021	95	rt2x00lib_rxdone(entry, GFP_ATOMIC);
95ea3627	96	}
16638937 HS	97
16638937 HS	98	return !max_rx;
95ea3627 ID	99	}
	100	EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
	101
152a5992 ID	102	void rt2x00pci_flush_queue(struct data_queue *queue, bool drop)
	103	{
	104	unsigned int i;
	105
	106	for (i = 0; !rt2x00queue_empty(queue) && i < 10; i++)
	107	msleep(10);
	108	}
	109	EXPORT_SYMBOL_GPL(rt2x00pci_flush_queue);
	110
95ea3627 ID	111	/*
	112	* Device initialization handlers.
	113	*/
181d6902 ID	114	static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
181d6902 ID	115	struct data_queue *queue)
95ea3627	116	{
b8be63ff	117	struct queue_entry_priv_pci *entry_priv;
30b3a23c ID	118	void *addr;
30b3a23c ID	119	dma_addr_t dma;
95ea3627 ID	120	unsigned int i;
	121
	122	/*
	123	* Allocate DMA memory for descriptor and buffer.
	124	*/
c4da0048 GW	125	addr = dma_alloc_coherent(rt2x00dev->dev,
c4da0048 GW	126	queue->limit * queue->desc_size,
1f9061d2	127	&dma, GFP_KERNEL \| __GFP_ZERO);
30b3a23c	128	if (!addr)
95ea3627 ID	129	return -ENOMEM;
	130
	131	/*
181d6902	132	* Initialize all queue entries to contain valid addresses.
95ea3627	133	*/
181d6902	134	for (i = 0; i < queue->limit; i++) {
b8be63ff	135	entry_priv = queue->entries[i].priv_data;
c4da0048 GW	136	entry_priv->desc = addr + i * queue->desc_size;
c4da0048 GW	137	entry_priv->desc_dma = dma + i * queue->desc_size;
95ea3627 ID	138	}
	139
	140	return 0;
	141	}
	142
181d6902 ID	143	static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
181d6902 ID	144	struct data_queue *queue)
95ea3627	145	{
b8be63ff ID	146	struct queue_entry_priv_pci *entry_priv =
b8be63ff ID	147	queue->entries[0].priv_data;
181d6902	148
c4da0048 GW	149	if (entry_priv->desc)
	150	dma_free_coherent(rt2x00dev->dev,
	151	queue->limit * queue->desc_size,
	152	entry_priv->desc, entry_priv->desc_dma);
	153	entry_priv->desc = NULL;
95ea3627 ID	154	}
	155
	156	int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
	157	{
181d6902	158	struct data_queue *queue;
95ea3627 ID	159	int status;
	160
	161	/*
	162	* Allocate DMA
	163	*/
181d6902 ID	164	queue_for_each(rt2x00dev, queue) {
181d6902 ID	165	status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
95ea3627 ID	166	if (status)
	167	goto exit;
	168	}
	169
	170	/*
	171	* Register interrupt handler.
	172	*/
e88399bc HS	173	status = request_irq(rt2x00dev->irq,
	174	rt2x00dev->ops->lib->irq_handler,
	175	IRQF_SHARED, rt2x00dev->name, rt2x00dev);
95ea3627 ID	176	if (status) {
95ea3627 ID	177	ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
440ddada	178	rt2x00dev->irq, status);
b30cdfc5	179	goto exit;
95ea3627 ID	180	}
	181
	182	return 0;
	183
	184	exit:
b30cdfc5 ID	185	queue_for_each(rt2x00dev, queue)
b30cdfc5 ID	186	rt2x00pci_free_queue_dma(rt2x00dev, queue);
95ea3627 ID	187
	188	return status;
	189	}
	190	EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
	191
	192	void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
	193	{
181d6902	194	struct data_queue *queue;
95ea3627 ID	195
	196	/*
	197	* Free irq line.
	198	*/
52a9bd2a	199	free_irq(rt2x00dev->irq, rt2x00dev);
95ea3627 ID	200
	201	/*
	202	* Free DMA
	203	*/
181d6902 ID	204	queue_for_each(rt2x00dev, queue)
181d6902 ID	205	rt2x00pci_free_queue_dma(rt2x00dev, queue);
95ea3627 ID	206	}
	207	EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
	208
	209	/*
	210	* PCI driver handlers.
	211	*/
	212	static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
	213	{
	214	kfree(rt2x00dev->rf);
	215	rt2x00dev->rf = NULL;
	216
	217	kfree(rt2x00dev->eeprom);
	218	rt2x00dev->eeprom = NULL;
	219
21795094 ID	220	if (rt2x00dev->csr.base) {
	221	iounmap(rt2x00dev->csr.base);
	222	rt2x00dev->csr.base = NULL;
95ea3627 ID	223	}
	224	}
	225
	226	static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
	227	{
14a3bf89	228	struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
95ea3627	229
275f165f	230	rt2x00dev->csr.base = pci_ioremap_bar(pci_dev, 0);
21795094	231	if (!rt2x00dev->csr.base)
95ea3627 ID	232	goto exit;
	233
	234	rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
	235	if (!rt2x00dev->eeprom)
	236	goto exit;
	237
	238	rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
	239	if (!rt2x00dev->rf)
	240	goto exit;
	241
	242	return 0;
	243
	244	exit:
	245	ERROR_PROBE("Failed to allocate registers.\n");
	246
	247	rt2x00pci_free_reg(rt2x00dev);
	248
	249	return -ENOMEM;
	250	}
	251
e01ae27f	252	int rt2x00pci_probe(struct pci_dev pci_dev, const struct rt2x00_ops ops)
95ea3627	253	{
95ea3627 ID	254	struct ieee80211_hw *hw;
	255	struct rt2x00_dev *rt2x00dev;
	256	int retval;
a89534ed	257	u16 chip;
95ea3627	258
47cb905d	259	retval = pci_enable_device(pci_dev);
95ea3627	260	if (retval) {
47cb905d	261	ERROR_PROBE("Enable device failed.\n");
95ea3627 ID	262	return retval;
	263	}
	264
47cb905d	265	retval = pci_request_regions(pci_dev, pci_name(pci_dev));
95ea3627	266	if (retval) {
47cb905d KV	267	ERROR_PROBE("PCI request regions failed.\n");
47cb905d KV	268	goto exit_disable_device;
95ea3627 ID	269	}
	270
	271	pci_set_master(pci_dev);
	272
	273	if (pci_set_mwi(pci_dev))
	274	ERROR_PROBE("MWI not available.\n");
	275
284901a9	276	if (dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
95ea3627 ID	277	ERROR_PROBE("PCI DMA not supported.\n");
95ea3627 ID	278	retval = -EIO;
47cb905d	279	goto exit_release_regions;
95ea3627 ID	280	}
	281
	282	hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
	283	if (!hw) {
	284	ERROR_PROBE("Failed to allocate hardware.\n");
	285	retval = -ENOMEM;
47cb905d	286	goto exit_release_regions;
95ea3627 ID	287	}
	288
	289	pci_set_drvdata(pci_dev, hw);
	290
	291	rt2x00dev = hw->priv;
14a3bf89	292	rt2x00dev->dev = &pci_dev->dev;
95ea3627 ID	293	rt2x00dev->ops = ops;
95ea3627 ID	294	rt2x00dev->hw = hw;
440ddada ID	295	rt2x00dev->irq = pci_dev->irq;
	296	rt2x00dev->name = pci_name(pci_dev);
	297
2cdb9a42	298	if (pci_is_pcie(pci_dev))
6e1fdd11 GW	299	rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
	300	else
	301	rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
2015d192	302
95ea3627 ID	303	retval = rt2x00pci_alloc_reg(rt2x00dev);
	304	if (retval)
	305	goto exit_free_device;
	306
a89534ed WH	307	/*
	308	* Because rt3290 chip use different efuse offset to read efuse data.
	309	* So before read efuse it need to indicate it is the
	310	* rt3290 or not.
	311	*/
	312	pci_read_config_word(pci_dev, PCI_DEVICE_ID, &chip);
	313	rt2x00dev->chip.rt = chip;
	314
95ea3627 ID	315	retval = rt2x00lib_probe_dev(rt2x00dev);
	316	if (retval)
	317	goto exit_free_reg;
	318
	319	return 0;
	320
	321	exit_free_reg:
	322	rt2x00pci_free_reg(rt2x00dev);
	323
	324	exit_free_device:
	325	ieee80211_free_hw(hw);
	326
95ea3627 ID	327	exit_release_regions:
	328	pci_release_regions(pci_dev);
	329
47cb905d KV	330	exit_disable_device:
	331	pci_disable_device(pci_dev);
	332
95ea3627 ID	333	pci_set_drvdata(pci_dev, NULL);
	334
	335	return retval;
	336	}
	337	EXPORT_SYMBOL_GPL(rt2x00pci_probe);
	338
	339	void rt2x00pci_remove(struct pci_dev *pci_dev)
	340	{
	341	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	342	struct rt2x00_dev *rt2x00dev = hw->priv;
	343
	344	/*
	345	* Free all allocated data.
	346	*/
	347	rt2x00lib_remove_dev(rt2x00dev);
	348	rt2x00pci_free_reg(rt2x00dev);
	349	ieee80211_free_hw(hw);
	350
	351	/*
	352	* Free the PCI device data.
	353	*/
	354	pci_set_drvdata(pci_dev, NULL);
	355	pci_disable_device(pci_dev);
	356	pci_release_regions(pci_dev);
	357	}
	358	EXPORT_SYMBOL_GPL(rt2x00pci_remove);
	359
	360	#ifdef CONFIG_PM
	361	int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
	362	{
	363	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	364	struct rt2x00_dev *rt2x00dev = hw->priv;
	365	int retval;
	366
	367	retval = rt2x00lib_suspend(rt2x00dev, state);
	368	if (retval)
	369	return retval;
	370
95ea3627 ID	371	pci_save_state(pci_dev);
	372	pci_disable_device(pci_dev);
	373	return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
	374	}
	375	EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
	376
	377	int rt2x00pci_resume(struct pci_dev *pci_dev)
	378	{
	379	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
	380	struct rt2x00_dev *rt2x00dev = hw->priv;
95ea3627 ID	381
95ea3627 ID	382	if (pci_set_power_state(pci_dev, PCI_D0) \|\|
1d3c16a8	383	pci_enable_device(pci_dev)) {
95ea3627 ID	384	ERROR(rt2x00dev, "Failed to resume device.\n");
	385	return -EIO;
	386	}
	387
1d3c16a8	388	pci_restore_state(pci_dev);
499a214c	389	return rt2x00lib_resume(rt2x00dev);
95ea3627 ID	390	}
	391	EXPORT_SYMBOL_GPL(rt2x00pci_resume);
	392	#endif /* CONFIG_PM */
	393
	394	/*
	395	* rt2x00pci module information.
	396	*/
	397	MODULE_AUTHOR(DRV_PROJECT);
	398	MODULE_VERSION(DRV_VERSION);
181d6902	399	MODULE_DESCRIPTION("rt2x00 pci library");
95ea3627	400	MODULE_LICENSE("GPL");