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1 | /* |
2 | Copyright (C) 2004 - 2009 rt2x00 SourceForge Project | |
3 | <http://rt2x00.serialmonkey.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2800pci | |
23 | Abstract: Data structures and registers for the rt2800pci module. | |
24 | Supported chipsets: RT2800E & RT2800ED. | |
25 | */ | |
26 | ||
27 | #ifndef RT2800PCI_H | |
28 | #define RT2800PCI_H | |
29 | ||
30 | /* | |
31 | * RF chip defines. | |
32 | * | |
33 | * RF2820 2.4G 2T3R | |
34 | * RF2850 2.4G/5G 2T3R | |
35 | * RF2720 2.4G 1T2R | |
36 | * RF2750 2.4G/5G 1T2R | |
37 | * RF3020 2.4G 1T1R | |
38 | * RF2020 2.4G B/G | |
39 | * RF3021 2.4G 1T2R | |
40 | * RF3022 2.4G 2T2R | |
41 | * RF3052 2.4G 2T2R | |
42 | */ | |
43 | #define RF2820 0x0001 | |
44 | #define RF2850 0x0002 | |
45 | #define RF2720 0x0003 | |
46 | #define RF2750 0x0004 | |
47 | #define RF3020 0x0005 | |
48 | #define RF2020 0x0006 | |
49 | #define RF3021 0x0007 | |
50 | #define RF3022 0x0008 | |
51 | #define RF3052 0x0009 | |
52 | ||
53 | /* | |
54 | * RT2860 version | |
55 | */ | |
56 | #define RT2860C_VERSION 0x28600100 | |
57 | #define RT2860D_VERSION 0x28600101 | |
58 | #define RT2880E_VERSION 0x28720200 | |
59 | #define RT2883_VERSION 0x28830300 | |
60 | #define RT3070_VERSION 0x30700200 | |
61 | ||
62 | /* | |
63 | * Signal information. | |
64 | * Default offset is required for RSSI <-> dBm conversion. | |
65 | */ | |
66 | #define DEFAULT_RSSI_OFFSET 120 /* FIXME */ | |
67 | ||
68 | /* | |
69 | * Register layout information. | |
70 | */ | |
71 | #define CSR_REG_BASE 0x1000 | |
72 | #define CSR_REG_SIZE 0x0800 | |
73 | #define EEPROM_BASE 0x0000 | |
74 | #define EEPROM_SIZE 0x0110 | |
75 | #define BBP_BASE 0x0000 | |
76 | #define BBP_SIZE 0x0080 | |
77 | #define RF_BASE 0x0004 | |
78 | #define RF_SIZE 0x0010 | |
79 | ||
80 | /* | |
81 | * Number of TX queues. | |
82 | */ | |
83 | #define NUM_TX_QUEUES 4 | |
84 | ||
85 | /* | |
86 | * PCI registers. | |
87 | */ | |
88 | ||
89 | /* | |
90 | * E2PROM_CSR: EEPROM control register. | |
91 | * RELOAD: Write 1 to reload eeprom content. | |
92 | * TYPE: 0: 93c46, 1:93c66. | |
93 | * LOAD_STATUS: 1:loading, 0:done. | |
94 | */ | |
95 | #define E2PROM_CSR 0x0004 | |
96 | #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) | |
97 | #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) | |
98 | #define E2PROM_CSR_DATA_IN FIELD32(0x00000004) | |
99 | #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) | |
100 | #define E2PROM_CSR_TYPE FIELD32(0x00000030) | |
101 | #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) | |
102 | #define E2PROM_CSR_RELOAD FIELD32(0x00000080) | |
103 | ||
104 | /* | |
105 | * INT_SOURCE_CSR: Interrupt source register. | |
106 | * Write one to clear corresponding bit. | |
107 | * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c | |
108 | */ | |
109 | #define INT_SOURCE_CSR 0x0200 | |
110 | #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) | |
111 | #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) | |
112 | #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) | |
113 | #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) | |
114 | #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) | |
115 | #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) | |
116 | #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) | |
117 | #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | |
118 | #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | |
119 | #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) | |
120 | #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) | |
121 | #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) | |
122 | #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) | |
123 | #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | |
124 | #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) | |
125 | #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) | |
126 | #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) | |
127 | #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) | |
128 | ||
129 | /* | |
130 | * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. | |
131 | */ | |
132 | #define INT_MASK_CSR 0x0204 | |
133 | #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) | |
134 | #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) | |
135 | #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) | |
136 | #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) | |
137 | #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) | |
138 | #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) | |
139 | #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) | |
140 | #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | |
141 | #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | |
142 | #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) | |
143 | #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) | |
144 | #define INT_MASK_CSR_TBTT FIELD32(0x00000800) | |
145 | #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) | |
146 | #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | |
147 | #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) | |
148 | #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) | |
149 | #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) | |
150 | #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) | |
151 | ||
152 | /* | |
153 | * WPDMA_GLO_CFG | |
154 | */ | |
155 | #define WPDMA_GLO_CFG 0x0208 | |
156 | #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) | |
157 | #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) | |
158 | #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) | |
159 | #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) | |
160 | #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) | |
161 | #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) | |
162 | #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) | |
163 | #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) | |
164 | #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) | |
165 | ||
166 | /* | |
167 | * WPDMA_RST_IDX | |
168 | */ | |
169 | #define WPDMA_RST_IDX 0x020c | |
170 | #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) | |
171 | #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) | |
172 | #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) | |
173 | #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) | |
174 | #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) | |
175 | #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) | |
176 | #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) | |
177 | ||
178 | /* | |
179 | * DELAY_INT_CFG | |
180 | */ | |
181 | #define DELAY_INT_CFG 0x0210 | |
182 | #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) | |
183 | #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) | |
184 | #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) | |
185 | #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) | |
186 | #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) | |
187 | #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) | |
188 | ||
189 | /* | |
190 | * WMM_AIFSN_CFG: Aifsn for each EDCA AC | |
191 | * AIFSN0: AC_BE | |
192 | * AIFSN1: AC_BK | |
193 | * AIFSN1: AC_VI | |
194 | * AIFSN1: AC_VO | |
195 | */ | |
196 | #define WMM_AIFSN_CFG 0x0214 | |
197 | #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) | |
198 | #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) | |
199 | #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) | |
200 | #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) | |
201 | ||
202 | /* | |
203 | * WMM_CWMIN_CSR: CWmin for each EDCA AC | |
204 | * CWMIN0: AC_BE | |
205 | * CWMIN1: AC_BK | |
206 | * CWMIN1: AC_VI | |
207 | * CWMIN1: AC_VO | |
208 | */ | |
209 | #define WMM_CWMIN_CFG 0x0218 | |
210 | #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) | |
211 | #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) | |
212 | #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) | |
213 | #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) | |
214 | ||
215 | /* | |
216 | * WMM_CWMAX_CSR: CWmax for each EDCA AC | |
217 | * CWMAX0: AC_BE | |
218 | * CWMAX1: AC_BK | |
219 | * CWMAX1: AC_VI | |
220 | * CWMAX1: AC_VO | |
221 | */ | |
222 | #define WMM_CWMAX_CFG 0x021c | |
223 | #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) | |
224 | #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) | |
225 | #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) | |
226 | #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) | |
227 | ||
228 | /* | |
229 | * AC_TXOP0: AC_BK/AC_BE TXOP register | |
230 | * AC0TXOP: AC_BK in unit of 32us | |
231 | * AC1TXOP: AC_BE in unit of 32us | |
232 | */ | |
233 | #define WMM_TXOP0_CFG 0x0220 | |
234 | #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) | |
235 | #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) | |
236 | ||
237 | /* | |
238 | * AC_TXOP1: AC_VO/AC_VI TXOP register | |
239 | * AC2TXOP: AC_VI in unit of 32us | |
240 | * AC3TXOP: AC_VO in unit of 32us | |
241 | */ | |
242 | #define WMM_TXOP1_CFG 0x0224 | |
243 | #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) | |
244 | #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) | |
245 | ||
246 | /* | |
247 | * GPIO_CTRL_CFG: | |
248 | */ | |
249 | #define GPIO_CTRL_CFG 0x0228 | |
250 | #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001) | |
251 | #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002) | |
252 | #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004) | |
253 | #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008) | |
254 | #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010) | |
255 | #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020) | |
256 | #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040) | |
257 | #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080) | |
258 | #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100) | |
259 | ||
260 | /* | |
261 | * MCU_CMD_CFG | |
262 | */ | |
263 | #define MCU_CMD_CFG 0x022c | |
264 | ||
265 | /* | |
266 | * AC_BK register offsets | |
267 | */ | |
268 | #define TX_BASE_PTR0 0x0230 | |
269 | #define TX_MAX_CNT0 0x0234 | |
270 | #define TX_CTX_IDX0 0x0238 | |
271 | #define TX_DTX_IDX0 0x023c | |
272 | ||
273 | /* | |
274 | * AC_BE register offsets | |
275 | */ | |
276 | #define TX_BASE_PTR1 0x0240 | |
277 | #define TX_MAX_CNT1 0x0244 | |
278 | #define TX_CTX_IDX1 0x0248 | |
279 | #define TX_DTX_IDX1 0x024c | |
280 | ||
281 | /* | |
282 | * AC_VI register offsets | |
283 | */ | |
284 | #define TX_BASE_PTR2 0x0250 | |
285 | #define TX_MAX_CNT2 0x0254 | |
286 | #define TX_CTX_IDX2 0x0258 | |
287 | #define TX_DTX_IDX2 0x025c | |
288 | ||
289 | /* | |
290 | * AC_VO register offsets | |
291 | */ | |
292 | #define TX_BASE_PTR3 0x0260 | |
293 | #define TX_MAX_CNT3 0x0264 | |
294 | #define TX_CTX_IDX3 0x0268 | |
295 | #define TX_DTX_IDX3 0x026c | |
296 | ||
297 | /* | |
298 | * HCCA register offsets | |
299 | */ | |
300 | #define TX_BASE_PTR4 0x0270 | |
301 | #define TX_MAX_CNT4 0x0274 | |
302 | #define TX_CTX_IDX4 0x0278 | |
303 | #define TX_DTX_IDX4 0x027c | |
304 | ||
305 | /* | |
306 | * MGMT register offsets | |
307 | */ | |
308 | #define TX_BASE_PTR5 0x0280 | |
309 | #define TX_MAX_CNT5 0x0284 | |
310 | #define TX_CTX_IDX5 0x0288 | |
311 | #define TX_DTX_IDX5 0x028c | |
312 | ||
313 | /* | |
314 | * Queue register offset macros | |
315 | */ | |
316 | #define TX_QUEUE_REG_OFFSET 0x10 | |
317 | #define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET) | |
318 | #define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET) | |
319 | #define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET) | |
320 | #define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET) | |
321 | ||
322 | /* | |
323 | * RX register offsets | |
324 | */ | |
325 | #define RX_BASE_PTR 0x0290 | |
326 | #define RX_MAX_CNT 0x0294 | |
327 | #define RX_CRX_IDX 0x0298 | |
328 | #define RX_DRX_IDX 0x029c | |
329 | ||
330 | /* | |
331 | * PBF_SYS_CTRL | |
332 | * HOST_RAM_WRITE: enable Host program ram write selection | |
333 | */ | |
334 | #define PBF_SYS_CTRL 0x0400 | |
335 | #define PBF_SYS_CTRL_READY FIELD32(0x00000080) | |
336 | #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) | |
337 | ||
338 | /* | |
339 | * HOST-MCU shared memory | |
340 | */ | |
341 | #define HOST_CMD_CSR 0x0404 | |
342 | #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) | |
343 | ||
344 | /* | |
345 | * PBF registers | |
346 | * Most are for debug. Driver doesn't touch PBF register. | |
347 | */ | |
348 | #define PBF_CFG 0x0408 | |
349 | #define PBF_MAX_PCNT 0x040c | |
350 | #define PBF_CTRL 0x0410 | |
351 | #define PBF_INT_STA 0x0414 | |
352 | #define PBF_INT_ENA 0x0418 | |
353 | ||
354 | /* | |
355 | * BCN_OFFSET0: | |
356 | */ | |
357 | #define BCN_OFFSET0 0x042c | |
358 | #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) | |
359 | #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) | |
360 | #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) | |
361 | #define BCN_OFFSET0_BCN3 FIELD32(0xff000000) | |
362 | ||
363 | /* | |
364 | * BCN_OFFSET1: | |
365 | */ | |
366 | #define BCN_OFFSET1 0x0430 | |
367 | #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) | |
368 | #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) | |
369 | #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) | |
370 | #define BCN_OFFSET1_BCN7 FIELD32(0xff000000) | |
371 | ||
372 | /* | |
373 | * PBF registers | |
374 | * Most are for debug. Driver doesn't touch PBF register. | |
375 | */ | |
376 | #define TXRXQ_PCNT 0x0438 | |
377 | #define PBF_DBG 0x043c | |
378 | ||
379 | /* | |
380 | * RF registers | |
381 | */ | |
382 | #define RF_CSR_CFG 0x0500 | |
383 | #define RF_CSR_CFG_DATA FIELD32(0x000000ff) | |
384 | #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00) | |
385 | #define RF_CSR_CFG_WRITE FIELD32(0x00010000) | |
386 | #define RF_CSR_CFG_BUSY FIELD32(0x00020000) | |
387 | ||
388 | /* | |
389 | * EFUSE_CSR: RT3090 EEPROM | |
390 | */ | |
391 | #define EFUSE_CTRL 0x0580 | |
392 | #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000) | |
393 | #define EFUSE_CTRL_MODE FIELD32(0x000000c0) | |
394 | #define EFUSE_CTRL_KICK FIELD32(0x40000000) | |
395 | ||
396 | /* | |
397 | * EFUSE_DATA0 | |
398 | */ | |
399 | #define EFUSE_DATA0 0x0590 | |
400 | ||
401 | /* | |
402 | * EFUSE_DATA1 | |
403 | */ | |
404 | #define EFUSE_DATA1 0x0594 | |
405 | ||
406 | /* | |
407 | * EFUSE_DATA2 | |
408 | */ | |
409 | #define EFUSE_DATA2 0x0598 | |
410 | ||
411 | /* | |
412 | * EFUSE_DATA3 | |
413 | */ | |
414 | #define EFUSE_DATA3 0x059c | |
415 | ||
416 | /* | |
417 | * MAC Control/Status Registers(CSR). | |
418 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
419 | */ | |
420 | ||
421 | /* | |
422 | * MAC_CSR0: ASIC revision number. | |
423 | * ASIC_REV: 0 | |
424 | * ASIC_VER: 2860 | |
425 | */ | |
426 | #define MAC_CSR0 0x1000 | |
427 | #define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff) | |
428 | #define MAC_CSR0_ASIC_VER FIELD32(0xffff0000) | |
429 | ||
430 | /* | |
431 | * MAC_SYS_CTRL: | |
432 | */ | |
433 | #define MAC_SYS_CTRL 0x1004 | |
434 | #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) | |
435 | #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) | |
436 | #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) | |
437 | #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) | |
438 | #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) | |
439 | #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) | |
440 | #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) | |
441 | #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) | |
442 | ||
443 | /* | |
444 | * MAC_ADDR_DW0: STA MAC register 0 | |
445 | */ | |
446 | #define MAC_ADDR_DW0 0x1008 | |
447 | #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) | |
448 | #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) | |
449 | #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) | |
450 | #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) | |
451 | ||
452 | /* | |
453 | * MAC_ADDR_DW1: STA MAC register 1 | |
454 | * UNICAST_TO_ME_MASK: | |
455 | * Used to mask off bits from byte 5 of the MAC address | |
456 | * to determine the UNICAST_TO_ME bit for RX frames. | |
457 | * The full mask is complemented by BSS_ID_MASK: | |
458 | * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK | |
459 | */ | |
460 | #define MAC_ADDR_DW1 0x100c | |
461 | #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) | |
462 | #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) | |
463 | #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) | |
464 | ||
465 | /* | |
466 | * MAC_BSSID_DW0: BSSID register 0 | |
467 | */ | |
468 | #define MAC_BSSID_DW0 0x1010 | |
469 | #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) | |
470 | #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) | |
471 | #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) | |
472 | #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) | |
473 | ||
474 | /* | |
475 | * MAC_BSSID_DW1: BSSID register 1 | |
476 | * BSS_ID_MASK: | |
477 | * 0: 1-BSSID mode (BSS index = 0) | |
478 | * 1: 2-BSSID mode (BSS index: Byte5, bit 0) | |
479 | * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) | |
480 | * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) | |
481 | * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the | |
482 | * BSSID. This will make sure that those bits will be ignored | |
483 | * when determining the MY_BSS of RX frames. | |
484 | */ | |
485 | #define MAC_BSSID_DW1 0x1014 | |
486 | #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) | |
487 | #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) | |
488 | #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) | |
489 | #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) | |
490 | ||
491 | /* | |
492 | * MAX_LEN_CFG: Maximum frame length register. | |
493 | * MAX_MPDU: rt2860b max 16k bytes | |
494 | * MAX_PSDU: Maximum PSDU length | |
495 | * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 | |
496 | */ | |
497 | #define MAX_LEN_CFG 0x1018 | |
498 | #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) | |
499 | #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) | |
500 | #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) | |
501 | #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) | |
502 | ||
503 | /* | |
504 | * BBP_CSR_CFG: BBP serial control register | |
505 | * VALUE: Register value to program into BBP | |
506 | * REG_NUM: Selected BBP register | |
507 | * READ_CONTROL: 0 write BBP, 1 read BBP | |
508 | * BUSY: ASIC is busy executing BBP commands | |
509 | * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks | |
510 | * BBP_RW_MODE: 0 serial, 1 paralell | |
511 | */ | |
512 | #define BBP_CSR_CFG 0x101c | |
513 | #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) | |
514 | #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) | |
515 | #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) | |
516 | #define BBP_CSR_CFG_BUSY FIELD32(0x00020000) | |
517 | #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) | |
518 | #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) | |
519 | ||
520 | /* | |
521 | * RF_CSR_CFG0: RF control register | |
522 | * REGID_AND_VALUE: Register value to program into RF | |
523 | * BITWIDTH: Selected RF register | |
524 | * STANDBYMODE: 0 high when standby, 1 low when standby | |
525 | * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate | |
526 | * BUSY: ASIC is busy executing RF commands | |
527 | */ | |
528 | #define RF_CSR_CFG0 0x1020 | |
529 | #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) | |
530 | #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) | |
531 | #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) | |
532 | #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) | |
533 | #define RF_CSR_CFG0_SEL FIELD32(0x40000000) | |
534 | #define RF_CSR_CFG0_BUSY FIELD32(0x80000000) | |
535 | ||
536 | /* | |
537 | * RF_CSR_CFG1: RF control register | |
538 | * REGID_AND_VALUE: Register value to program into RF | |
539 | * RFGAP: Gap between BB_CONTROL_RF and RF_LE | |
540 | * 0: 3 system clock cycle (37.5usec) | |
541 | * 1: 5 system clock cycle (62.5usec) | |
542 | */ | |
543 | #define RF_CSR_CFG1 0x1024 | |
544 | #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) | |
545 | #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) | |
546 | ||
547 | /* | |
548 | * RF_CSR_CFG2: RF control register | |
549 | * VALUE: Register value to program into RF | |
550 | * RFGAP: Gap between BB_CONTROL_RF and RF_LE | |
551 | * 0: 3 system clock cycle (37.5usec) | |
552 | * 1: 5 system clock cycle (62.5usec) | |
553 | */ | |
554 | #define RF_CSR_CFG2 0x1028 | |
555 | #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) | |
556 | ||
557 | /* | |
558 | * LED_CFG: LED control | |
559 | * color LED's: | |
560 | * 0: off | |
561 | * 1: blinking upon TX2 | |
562 | * 2: periodic slow blinking | |
563 | * 3: always on | |
564 | * LED polarity: | |
565 | * 0: active low | |
566 | * 1: active high | |
567 | */ | |
568 | #define LED_CFG 0x102c | |
569 | #define LED_CFG_ON_PERIOD FIELD32(0x000000ff) | |
570 | #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) | |
571 | #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) | |
572 | #define LED_CFG_R_LED_MODE FIELD32(0x03000000) | |
573 | #define LED_CFG_G_LED_MODE FIELD32(0x0c000000) | |
574 | #define LED_CFG_Y_LED_MODE FIELD32(0x30000000) | |
575 | #define LED_CFG_LED_POLAR FIELD32(0x40000000) | |
576 | ||
577 | /* | |
578 | * XIFS_TIME_CFG: MAC timing | |
579 | * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX | |
580 | * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX | |
581 | * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX | |
582 | * when MAC doesn't reference BBP signal BBRXEND | |
583 | * EIFS: unit 1us | |
584 | * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer | |
585 | * | |
586 | */ | |
587 | #define XIFS_TIME_CFG 0x1100 | |
588 | #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) | |
589 | #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) | |
590 | #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) | |
591 | #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) | |
592 | #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) | |
593 | ||
594 | /* | |
595 | * BKOFF_SLOT_CFG: | |
596 | */ | |
597 | #define BKOFF_SLOT_CFG 0x1104 | |
598 | #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) | |
599 | #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) | |
600 | ||
601 | /* | |
602 | * NAV_TIME_CFG: | |
603 | */ | |
604 | #define NAV_TIME_CFG 0x1108 | |
605 | #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) | |
606 | #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) | |
607 | #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) | |
608 | #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) | |
609 | ||
610 | /* | |
611 | * CH_TIME_CFG: count as channel busy | |
612 | */ | |
613 | #define CH_TIME_CFG 0x110c | |
614 | ||
615 | /* | |
616 | * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us | |
617 | */ | |
618 | #define PBF_LIFE_TIMER 0x1110 | |
619 | ||
620 | /* | |
621 | * BCN_TIME_CFG: | |
622 | * BEACON_INTERVAL: in unit of 1/16 TU | |
623 | * TSF_TICKING: Enable TSF auto counting | |
624 | * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode | |
625 | * BEACON_GEN: Enable beacon generator | |
626 | */ | |
627 | #define BCN_TIME_CFG 0x1114 | |
628 | #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) | |
629 | #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) | |
630 | #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) | |
631 | #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) | |
632 | #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) | |
633 | #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) | |
634 | ||
635 | /* | |
636 | * TBTT_SYNC_CFG: | |
637 | */ | |
638 | #define TBTT_SYNC_CFG 0x1118 | |
639 | ||
640 | /* | |
641 | * TSF_TIMER_DW0: Local lsb TSF timer, read-only | |
642 | */ | |
643 | #define TSF_TIMER_DW0 0x111c | |
644 | #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) | |
645 | ||
646 | /* | |
647 | * TSF_TIMER_DW1: Local msb TSF timer, read-only | |
648 | */ | |
649 | #define TSF_TIMER_DW1 0x1120 | |
650 | #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) | |
651 | ||
652 | /* | |
653 | * TBTT_TIMER: TImer remains till next TBTT, read-only | |
654 | */ | |
655 | #define TBTT_TIMER 0x1124 | |
656 | ||
657 | /* | |
658 | * INT_TIMER_CFG: | |
659 | */ | |
660 | #define INT_TIMER_CFG 0x1128 | |
661 | ||
662 | /* | |
663 | * INT_TIMER_EN: GP-timer and pre-tbtt Int enable | |
664 | */ | |
665 | #define INT_TIMER_EN 0x112c | |
666 | ||
667 | /* | |
668 | * CH_IDLE_STA: channel idle time | |
669 | */ | |
670 | #define CH_IDLE_STA 0x1130 | |
671 | ||
672 | /* | |
673 | * CH_BUSY_STA: channel busy time | |
674 | */ | |
675 | #define CH_BUSY_STA 0x1134 | |
676 | ||
677 | /* | |
678 | * MAC_STATUS_CFG: | |
679 | * BBP_RF_BUSY: When set to 0, BBP and RF are stable. | |
680 | * if 1 or higher one of the 2 registers is busy. | |
681 | */ | |
682 | #define MAC_STATUS_CFG 0x1200 | |
683 | #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) | |
684 | ||
685 | /* | |
686 | * PWR_PIN_CFG: | |
687 | */ | |
688 | #define PWR_PIN_CFG 0x1204 | |
689 | ||
690 | /* | |
691 | * AUTOWAKEUP_CFG: Manual power control / status register | |
692 | * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set | |
693 | * AUTOWAKE: 0:sleep, 1:awake | |
694 | */ | |
695 | #define AUTOWAKEUP_CFG 0x1208 | |
696 | #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) | |
697 | #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) | |
698 | #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) | |
699 | ||
700 | /* | |
701 | * EDCA_AC0_CFG: | |
702 | */ | |
703 | #define EDCA_AC0_CFG 0x1300 | |
704 | #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) | |
705 | #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) | |
706 | #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) | |
707 | #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) | |
708 | ||
709 | /* | |
710 | * EDCA_AC1_CFG: | |
711 | */ | |
712 | #define EDCA_AC1_CFG 0x1304 | |
713 | #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) | |
714 | #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) | |
715 | #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) | |
716 | #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) | |
717 | ||
718 | /* | |
719 | * EDCA_AC2_CFG: | |
720 | */ | |
721 | #define EDCA_AC2_CFG 0x1308 | |
722 | #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) | |
723 | #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) | |
724 | #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) | |
725 | #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) | |
726 | ||
727 | /* | |
728 | * EDCA_AC3_CFG: | |
729 | */ | |
730 | #define EDCA_AC3_CFG 0x130c | |
731 | #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) | |
732 | #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) | |
733 | #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) | |
734 | #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) | |
735 | ||
736 | /* | |
737 | * EDCA_TID_AC_MAP: | |
738 | */ | |
739 | #define EDCA_TID_AC_MAP 0x1310 | |
740 | ||
741 | /* | |
742 | * TX_PWR_CFG_0: | |
743 | */ | |
744 | #define TX_PWR_CFG_0 0x1314 | |
745 | #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) | |
746 | #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) | |
747 | #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) | |
748 | #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) | |
749 | #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) | |
750 | #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) | |
751 | #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) | |
752 | #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) | |
753 | ||
754 | /* | |
755 | * TX_PWR_CFG_1: | |
756 | */ | |
757 | #define TX_PWR_CFG_1 0x1318 | |
758 | #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) | |
759 | #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) | |
760 | #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) | |
761 | #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) | |
762 | #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) | |
763 | #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) | |
764 | #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) | |
765 | #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) | |
766 | ||
767 | /* | |
768 | * TX_PWR_CFG_2: | |
769 | */ | |
770 | #define TX_PWR_CFG_2 0x131c | |
771 | #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) | |
772 | #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) | |
773 | #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) | |
774 | #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) | |
775 | #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) | |
776 | #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) | |
777 | #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) | |
778 | #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) | |
779 | ||
780 | /* | |
781 | * TX_PWR_CFG_3: | |
782 | */ | |
783 | #define TX_PWR_CFG_3 0x1320 | |
784 | #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) | |
785 | #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) | |
786 | #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) | |
787 | #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) | |
788 | #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000) | |
789 | #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000) | |
790 | #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000) | |
791 | #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000) | |
792 | ||
793 | /* | |
794 | * TX_PWR_CFG_4: | |
795 | */ | |
796 | #define TX_PWR_CFG_4 0x1324 | |
797 | #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f) | |
798 | #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0) | |
799 | #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00) | |
800 | #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000) | |
801 | ||
802 | /* | |
803 | * TX_PIN_CFG: | |
804 | */ | |
805 | #define TX_PIN_CFG 0x1328 | |
806 | #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) | |
807 | #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) | |
808 | #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) | |
809 | #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) | |
810 | #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) | |
811 | #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) | |
812 | #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) | |
813 | #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) | |
814 | #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) | |
815 | #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) | |
816 | #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) | |
817 | #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) | |
818 | #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) | |
819 | #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) | |
820 | #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) | |
821 | #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) | |
822 | #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) | |
823 | #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) | |
824 | #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) | |
825 | #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) | |
826 | ||
827 | /* | |
828 | * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz | |
829 | */ | |
830 | #define TX_BAND_CFG 0x132c | |
831 | #define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001) | |
832 | #define TX_BAND_CFG_A FIELD32(0x00000002) | |
833 | #define TX_BAND_CFG_BG FIELD32(0x00000004) | |
834 | ||
835 | /* | |
836 | * TX_SW_CFG0: | |
837 | */ | |
838 | #define TX_SW_CFG0 0x1330 | |
839 | ||
840 | /* | |
841 | * TX_SW_CFG1: | |
842 | */ | |
843 | #define TX_SW_CFG1 0x1334 | |
844 | ||
845 | /* | |
846 | * TX_SW_CFG2: | |
847 | */ | |
848 | #define TX_SW_CFG2 0x1338 | |
849 | ||
850 | /* | |
851 | * TXOP_THRES_CFG: | |
852 | */ | |
853 | #define TXOP_THRES_CFG 0x133c | |
854 | ||
855 | /* | |
856 | * TXOP_CTRL_CFG: | |
857 | */ | |
858 | #define TXOP_CTRL_CFG 0x1340 | |
859 | ||
860 | /* | |
861 | * TX_RTS_CFG: | |
862 | * RTS_THRES: unit:byte | |
863 | * RTS_FBK_EN: enable rts rate fallback | |
864 | */ | |
865 | #define TX_RTS_CFG 0x1344 | |
866 | #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) | |
867 | #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) | |
868 | #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) | |
869 | ||
870 | /* | |
871 | * TX_TIMEOUT_CFG: | |
872 | * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us | |
873 | * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure | |
874 | * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. | |
875 | * it is recommended that: | |
876 | * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) | |
877 | */ | |
878 | #define TX_TIMEOUT_CFG 0x1348 | |
879 | #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) | |
880 | #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) | |
881 | #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) | |
882 | ||
883 | /* | |
884 | * TX_RTY_CFG: | |
885 | * SHORT_RTY_LIMIT: short retry limit | |
886 | * LONG_RTY_LIMIT: long retry limit | |
887 | * LONG_RTY_THRE: Long retry threshoold | |
888 | * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode | |
889 | * 0:expired by retry limit, 1: expired by mpdu life timer | |
890 | * AGG_RTY_MODE: Aggregate MPDU retry mode | |
891 | * 0:expired by retry limit, 1: expired by mpdu life timer | |
892 | * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable | |
893 | */ | |
894 | #define TX_RTY_CFG 0x134c | |
895 | #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) | |
896 | #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) | |
897 | #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) | |
898 | #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) | |
899 | #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) | |
900 | #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) | |
901 | ||
902 | /* | |
903 | * TX_LINK_CFG: | |
904 | * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us | |
905 | * MFB_ENABLE: TX apply remote MFB 1:enable | |
906 | * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable | |
907 | * 0: not apply remote remote unsolicit (MFS=7) | |
908 | * TX_MRQ_EN: MCS request TX enable | |
909 | * TX_RDG_EN: RDG TX enable | |
910 | * TX_CF_ACK_EN: Piggyback CF-ACK enable | |
911 | * REMOTE_MFB: remote MCS feedback | |
912 | * REMOTE_MFS: remote MCS feedback sequence number | |
913 | */ | |
914 | #define TX_LINK_CFG 0x1350 | |
915 | #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) | |
916 | #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) | |
917 | #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) | |
918 | #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) | |
919 | #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) | |
920 | #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) | |
921 | #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) | |
922 | #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) | |
923 | ||
924 | /* | |
925 | * HT_FBK_CFG0: | |
926 | */ | |
927 | #define HT_FBK_CFG0 0x1354 | |
928 | #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) | |
929 | #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) | |
930 | #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) | |
931 | #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) | |
932 | #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) | |
933 | #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) | |
934 | #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) | |
935 | #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) | |
936 | ||
937 | /* | |
938 | * HT_FBK_CFG1: | |
939 | */ | |
940 | #define HT_FBK_CFG1 0x1358 | |
941 | #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) | |
942 | #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) | |
943 | #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) | |
944 | #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) | |
945 | #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) | |
946 | #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) | |
947 | #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) | |
948 | #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) | |
949 | ||
950 | /* | |
951 | * LG_FBK_CFG0: | |
952 | */ | |
953 | #define LG_FBK_CFG0 0x135c | |
954 | #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) | |
955 | #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) | |
956 | #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) | |
957 | #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) | |
958 | #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) | |
959 | #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) | |
960 | #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) | |
961 | #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) | |
962 | ||
963 | /* | |
964 | * LG_FBK_CFG1: | |
965 | */ | |
966 | #define LG_FBK_CFG1 0x1360 | |
967 | #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) | |
968 | #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) | |
969 | #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) | |
970 | #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) | |
971 | ||
972 | /* | |
973 | * CCK_PROT_CFG: CCK Protection | |
974 | * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) | |
975 | * PROTECT_CTRL: Protection control frame type for CCK TX | |
976 | * 0:none, 1:RTS/CTS, 2:CTS-to-self | |
977 | * PROTECT_NAV: TXOP protection type for CCK TX | |
978 | * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect | |
979 | * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow | |
980 | * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow | |
981 | * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow | |
982 | * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow | |
983 | * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow | |
984 | * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow | |
985 | * RTS_TH_EN: RTS threshold enable on CCK TX | |
986 | */ | |
987 | #define CCK_PROT_CFG 0x1364 | |
988 | #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
989 | #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
990 | #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
991 | #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
992 | #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
993 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
994 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
995 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
996 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
997 | #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
998 | ||
999 | /* | |
1000 | * OFDM_PROT_CFG: OFDM Protection | |
1001 | */ | |
1002 | #define OFDM_PROT_CFG 0x1368 | |
1003 | #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1004 | #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1005 | #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1006 | #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1007 | #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1008 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1009 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1010 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1011 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1012 | #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1013 | ||
1014 | /* | |
1015 | * MM20_PROT_CFG: MM20 Protection | |
1016 | */ | |
1017 | #define MM20_PROT_CFG 0x136c | |
1018 | #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1019 | #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1020 | #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1021 | #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1022 | #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1023 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1024 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1025 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1026 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1027 | #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1028 | ||
1029 | /* | |
1030 | * MM40_PROT_CFG: MM40 Protection | |
1031 | */ | |
1032 | #define MM40_PROT_CFG 0x1370 | |
1033 | #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1034 | #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1035 | #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1036 | #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1037 | #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1038 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1039 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1040 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1041 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1042 | #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1043 | ||
1044 | /* | |
1045 | * GF20_PROT_CFG: GF20 Protection | |
1046 | */ | |
1047 | #define GF20_PROT_CFG 0x1374 | |
1048 | #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1049 | #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1050 | #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1051 | #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1052 | #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1053 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1054 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1055 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1056 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1057 | #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1058 | ||
1059 | /* | |
1060 | * GF40_PROT_CFG: GF40 Protection | |
1061 | */ | |
1062 | #define GF40_PROT_CFG 0x1378 | |
1063 | #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1064 | #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1065 | #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1066 | #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1067 | #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1068 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1069 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1070 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1071 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1072 | #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1073 | ||
1074 | /* | |
1075 | * EXP_CTS_TIME: | |
1076 | */ | |
1077 | #define EXP_CTS_TIME 0x137c | |
1078 | ||
1079 | /* | |
1080 | * EXP_ACK_TIME: | |
1081 | */ | |
1082 | #define EXP_ACK_TIME 0x1380 | |
1083 | ||
1084 | /* | |
1085 | * RX_FILTER_CFG: RX configuration register. | |
1086 | */ | |
1087 | #define RX_FILTER_CFG 0x1400 | |
1088 | #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) | |
1089 | #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) | |
1090 | #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) | |
1091 | #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) | |
1092 | #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) | |
1093 | #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) | |
1094 | #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) | |
1095 | #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) | |
1096 | #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) | |
1097 | #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) | |
1098 | #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) | |
1099 | #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) | |
1100 | #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) | |
1101 | #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) | |
1102 | #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) | |
1103 | #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) | |
1104 | #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) | |
1105 | ||
1106 | /* | |
1107 | * AUTO_RSP_CFG: | |
1108 | * AUTORESPONDER: 0: disable, 1: enable | |
1109 | * BAC_ACK_POLICY: 0:long, 1:short preamble | |
1110 | * CTS_40_MMODE: Response CTS 40MHz duplicate mode | |
1111 | * CTS_40_MREF: Response CTS 40MHz duplicate mode | |
1112 | * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble | |
1113 | * DUAL_CTS_EN: Power bit value in control frame | |
1114 | * ACK_CTS_PSM_BIT:Power bit value in control frame | |
1115 | */ | |
1116 | #define AUTO_RSP_CFG 0x1404 | |
1117 | #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) | |
1118 | #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) | |
1119 | #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) | |
1120 | #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) | |
1121 | #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) | |
1122 | #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) | |
1123 | #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) | |
1124 | ||
1125 | /* | |
1126 | * LEGACY_BASIC_RATE: | |
1127 | */ | |
1128 | #define LEGACY_BASIC_RATE 0x1408 | |
1129 | ||
1130 | /* | |
1131 | * HT_BASIC_RATE: | |
1132 | */ | |
1133 | #define HT_BASIC_RATE 0x140c | |
1134 | ||
1135 | /* | |
1136 | * HT_CTRL_CFG: | |
1137 | */ | |
1138 | #define HT_CTRL_CFG 0x1410 | |
1139 | ||
1140 | /* | |
1141 | * SIFS_COST_CFG: | |
1142 | */ | |
1143 | #define SIFS_COST_CFG 0x1414 | |
1144 | ||
1145 | /* | |
1146 | * RX_PARSER_CFG: | |
1147 | * Set NAV for all received frames | |
1148 | */ | |
1149 | #define RX_PARSER_CFG 0x1418 | |
1150 | ||
1151 | /* | |
1152 | * TX_SEC_CNT0: | |
1153 | */ | |
1154 | #define TX_SEC_CNT0 0x1500 | |
1155 | ||
1156 | /* | |
1157 | * RX_SEC_CNT0: | |
1158 | */ | |
1159 | #define RX_SEC_CNT0 0x1504 | |
1160 | ||
1161 | /* | |
1162 | * CCMP_FC_MUTE: | |
1163 | */ | |
1164 | #define CCMP_FC_MUTE 0x1508 | |
1165 | ||
1166 | /* | |
1167 | * TXOP_HLDR_ADDR0: | |
1168 | */ | |
1169 | #define TXOP_HLDR_ADDR0 0x1600 | |
1170 | ||
1171 | /* | |
1172 | * TXOP_HLDR_ADDR1: | |
1173 | */ | |
1174 | #define TXOP_HLDR_ADDR1 0x1604 | |
1175 | ||
1176 | /* | |
1177 | * TXOP_HLDR_ET: | |
1178 | */ | |
1179 | #define TXOP_HLDR_ET 0x1608 | |
1180 | ||
1181 | /* | |
1182 | * QOS_CFPOLL_RA_DW0: | |
1183 | */ | |
1184 | #define QOS_CFPOLL_RA_DW0 0x160c | |
1185 | ||
1186 | /* | |
1187 | * QOS_CFPOLL_RA_DW1: | |
1188 | */ | |
1189 | #define QOS_CFPOLL_RA_DW1 0x1610 | |
1190 | ||
1191 | /* | |
1192 | * QOS_CFPOLL_QC: | |
1193 | */ | |
1194 | #define QOS_CFPOLL_QC 0x1614 | |
1195 | ||
1196 | /* | |
1197 | * RX_STA_CNT0: RX PLCP error count & RX CRC error count | |
1198 | */ | |
1199 | #define RX_STA_CNT0 0x1700 | |
1200 | #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) | |
1201 | #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) | |
1202 | ||
1203 | /* | |
1204 | * RX_STA_CNT1: RX False CCA count & RX LONG frame count | |
1205 | */ | |
1206 | #define RX_STA_CNT1 0x1704 | |
1207 | #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) | |
1208 | #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) | |
1209 | ||
1210 | /* | |
1211 | * RX_STA_CNT2: | |
1212 | */ | |
1213 | #define RX_STA_CNT2 0x1708 | |
1214 | #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) | |
1215 | #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) | |
1216 | ||
1217 | /* | |
1218 | * TX_STA_CNT0: TX Beacon count | |
1219 | */ | |
1220 | #define TX_STA_CNT0 0x170c | |
1221 | #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) | |
1222 | #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) | |
1223 | ||
1224 | /* | |
1225 | * TX_STA_CNT1: TX tx count | |
1226 | */ | |
1227 | #define TX_STA_CNT1 0x1710 | |
1228 | #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) | |
1229 | #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) | |
1230 | ||
1231 | /* | |
1232 | * TX_STA_CNT2: TX tx count | |
1233 | */ | |
1234 | #define TX_STA_CNT2 0x1714 | |
1235 | #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) | |
1236 | #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) | |
1237 | ||
1238 | /* | |
1239 | * TX_STA_FIFO: TX Result for specific PID status fifo register | |
1240 | */ | |
1241 | #define TX_STA_FIFO 0x1718 | |
1242 | #define TX_STA_FIFO_VALID FIELD32(0x00000001) | |
1243 | #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) | |
1244 | #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) | |
1245 | #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) | |
1246 | #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) | |
1247 | #define TX_STA_FIFO_WCID FIELD32(0x0000ff00) | |
1248 | #define TX_STA_FIFO_MCS FIELD32(0x007f0000) | |
1249 | #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) | |
1250 | ||
1251 | /* | |
1252 | * TX_AGG_CNT: Debug counter | |
1253 | */ | |
1254 | #define TX_AGG_CNT 0x171c | |
1255 | #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) | |
1256 | #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) | |
1257 | ||
1258 | /* | |
1259 | * TX_AGG_CNT0: | |
1260 | */ | |
1261 | #define TX_AGG_CNT0 0x1720 | |
1262 | #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) | |
1263 | #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) | |
1264 | ||
1265 | /* | |
1266 | * TX_AGG_CNT1: | |
1267 | */ | |
1268 | #define TX_AGG_CNT1 0x1724 | |
1269 | #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) | |
1270 | #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) | |
1271 | ||
1272 | /* | |
1273 | * TX_AGG_CNT2: | |
1274 | */ | |
1275 | #define TX_AGG_CNT2 0x1728 | |
1276 | #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) | |
1277 | #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) | |
1278 | ||
1279 | /* | |
1280 | * TX_AGG_CNT3: | |
1281 | */ | |
1282 | #define TX_AGG_CNT3 0x172c | |
1283 | #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) | |
1284 | #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) | |
1285 | ||
1286 | /* | |
1287 | * TX_AGG_CNT4: | |
1288 | */ | |
1289 | #define TX_AGG_CNT4 0x1730 | |
1290 | #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) | |
1291 | #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) | |
1292 | ||
1293 | /* | |
1294 | * TX_AGG_CNT5: | |
1295 | */ | |
1296 | #define TX_AGG_CNT5 0x1734 | |
1297 | #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) | |
1298 | #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) | |
1299 | ||
1300 | /* | |
1301 | * TX_AGG_CNT6: | |
1302 | */ | |
1303 | #define TX_AGG_CNT6 0x1738 | |
1304 | #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) | |
1305 | #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) | |
1306 | ||
1307 | /* | |
1308 | * TX_AGG_CNT7: | |
1309 | */ | |
1310 | #define TX_AGG_CNT7 0x173c | |
1311 | #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) | |
1312 | #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) | |
1313 | ||
1314 | /* | |
1315 | * MPDU_DENSITY_CNT: | |
1316 | * TX_ZERO_DEL: TX zero length delimiter count | |
1317 | * RX_ZERO_DEL: RX zero length delimiter count | |
1318 | */ | |
1319 | #define MPDU_DENSITY_CNT 0x1740 | |
1320 | #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) | |
1321 | #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) | |
1322 | ||
1323 | /* | |
1324 | * Security key table memory. | |
1325 | * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry | |
1326 | * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry | |
1327 | * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry | |
1328 | * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry | |
1329 | * SHARED_KEY_TABLE_BASE: 32 bytes * 32-entry | |
1330 | * SHARED_KEY_MODE_BASE: 4 bits * 32-entry | |
1331 | */ | |
1332 | #define MAC_WCID_BASE 0x1800 | |
1333 | #define PAIRWISE_KEY_TABLE_BASE 0x4000 | |
1334 | #define MAC_IVEIV_TABLE_BASE 0x6000 | |
1335 | #define MAC_WCID_ATTRIBUTE_BASE 0x6800 | |
1336 | #define SHARED_KEY_TABLE_BASE 0x6c00 | |
1337 | #define SHARED_KEY_MODE_BASE 0x7000 | |
1338 | ||
1339 | #define MAC_WCID_ENTRY(__idx) \ | |
1340 | ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) ) | |
1341 | #define PAIRWISE_KEY_ENTRY(__idx) \ | |
1342 | ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) | |
1343 | #define MAC_IVEIV_ENTRY(__idx) \ | |
1344 | ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) ) | |
1345 | #define MAC_WCID_ATTR_ENTRY(__idx) \ | |
1346 | ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) ) | |
1347 | #define SHARED_KEY_ENTRY(__idx) \ | |
1348 | ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) | |
1349 | #define SHARED_KEY_MODE_ENTRY(__idx) \ | |
1350 | ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) ) | |
1351 | ||
1352 | struct mac_wcid_entry { | |
1353 | u8 mac[6]; | |
1354 | u8 reserved[2]; | |
1355 | } __attribute__ ((packed)); | |
1356 | ||
1357 | struct hw_key_entry { | |
1358 | u8 key[16]; | |
1359 | u8 tx_mic[8]; | |
1360 | u8 rx_mic[8]; | |
1361 | } __attribute__ ((packed)); | |
1362 | ||
1363 | struct mac_iveiv_entry { | |
1364 | u8 iv[8]; | |
1365 | } __attribute__ ((packed)); | |
1366 | ||
1367 | /* | |
1368 | * MAC_WCID_ATTRIBUTE: | |
1369 | */ | |
1370 | #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) | |
1371 | #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) | |
1372 | #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) | |
1373 | #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) | |
1374 | ||
1375 | /* | |
1376 | * SHARED_KEY_MODE: | |
1377 | */ | |
1378 | #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) | |
1379 | #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) | |
1380 | #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) | |
1381 | #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) | |
1382 | #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) | |
1383 | #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) | |
1384 | #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) | |
1385 | #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) | |
1386 | ||
1387 | /* | |
1388 | * HOST-MCU communication | |
1389 | */ | |
1390 | ||
1391 | /* | |
1392 | * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. | |
1393 | */ | |
1394 | #define H2M_MAILBOX_CSR 0x7010 | |
1395 | #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) | |
1396 | #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) | |
1397 | #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) | |
1398 | #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) | |
1399 | ||
1400 | /* | |
1401 | * H2M_MAILBOX_CID: | |
1402 | */ | |
1403 | #define H2M_MAILBOX_CID 0x7014 | |
1404 | #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) | |
1405 | #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) | |
1406 | #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) | |
1407 | #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) | |
1408 | ||
1409 | /* | |
1410 | * H2M_MAILBOX_STATUS: | |
1411 | */ | |
1412 | #define H2M_MAILBOX_STATUS 0x701c | |
1413 | ||
1414 | /* | |
1415 | * H2M_INT_SRC: | |
1416 | */ | |
1417 | #define H2M_INT_SRC 0x7024 | |
1418 | ||
1419 | /* | |
1420 | * H2M_BBP_AGENT: | |
1421 | */ | |
1422 | #define H2M_BBP_AGENT 0x7028 | |
1423 | ||
1424 | /* | |
1425 | * MCU_LEDCS: LED control for MCU Mailbox. | |
1426 | */ | |
1427 | #define MCU_LEDCS_LED_MODE FIELD8(0x1f) | |
1428 | #define MCU_LEDCS_POLARITY FIELD8(0x01) | |
1429 | ||
1430 | /* | |
1431 | * HW_CS_CTS_BASE: | |
1432 | * Carrier-sense CTS frame base address. | |
1433 | * It's where mac stores carrier-sense frame for carrier-sense function. | |
1434 | */ | |
1435 | #define HW_CS_CTS_BASE 0x7700 | |
1436 | ||
1437 | /* | |
1438 | * HW_DFS_CTS_BASE: | |
1439 | * FS CTS frame base address. It's where mac stores CTS frame for DFS. | |
1440 | */ | |
1441 | #define HW_DFS_CTS_BASE 0x7780 | |
1442 | ||
1443 | /* | |
1444 | * TXRX control registers - base address 0x3000 | |
1445 | */ | |
1446 | ||
1447 | /* | |
1448 | * TXRX_CSR1: | |
1449 | * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. | |
1450 | */ | |
1451 | #define TXRX_CSR1 0x77d0 | |
1452 | ||
1453 | /* | |
1454 | * HW_DEBUG_SETTING_BASE: | |
1455 | * since NULL frame won't be that long (256 byte) | |
1456 | * We steal 16 tail bytes to save debugging settings | |
1457 | */ | |
1458 | #define HW_DEBUG_SETTING_BASE 0x77f0 | |
1459 | #define HW_DEBUG_SETTING_BASE2 0x7770 | |
1460 | ||
1461 | /* | |
1462 | * HW_BEACON_BASE | |
1463 | * In order to support maximum 8 MBSS and its maximum length | |
1464 | * is 512 bytes for each beacon | |
1465 | * Three section discontinue memory segments will be used. | |
1466 | * 1. The original region for BCN 0~3 | |
1467 | * 2. Extract memory from FCE table for BCN 4~5 | |
1468 | * 3. Extract memory from Pair-wise key table for BCN 6~7 | |
1469 | * It occupied those memory of wcid 238~253 for BCN 6 | |
1470 | * and wcid 222~237 for BCN 7 | |
1471 | * | |
1472 | * IMPORTANT NOTE: Not sure why legacy driver does this, | |
1473 | * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. | |
1474 | */ | |
1475 | #define HW_BEACON_BASE0 0x7800 | |
1476 | #define HW_BEACON_BASE1 0x7a00 | |
1477 | #define HW_BEACON_BASE2 0x7c00 | |
1478 | #define HW_BEACON_BASE3 0x7e00 | |
1479 | #define HW_BEACON_BASE4 0x7200 | |
1480 | #define HW_BEACON_BASE5 0x7400 | |
1481 | #define HW_BEACON_BASE6 0x5dc0 | |
1482 | #define HW_BEACON_BASE7 0x5bc0 | |
1483 | ||
1484 | #define HW_BEACON_OFFSET(__index) \ | |
1485 | ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \ | |
1486 | (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \ | |
1487 | (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) ) | |
1488 | ||
1489 | /* | |
1490 | * 8051 firmware image. | |
1491 | */ | |
1492 | #define FIRMWARE_RT2860 "rt2860.bin" | |
1493 | #define FIRMWARE_IMAGE_BASE 0x2000 | |
1494 | ||
1495 | /* | |
1496 | * BBP registers. | |
1497 | * The wordsize of the BBP is 8 bits. | |
1498 | */ | |
1499 | ||
1500 | /* | |
1501 | * BBP 1: TX Antenna | |
1502 | */ | |
1503 | #define BBP1_TX_POWER FIELD8(0x07) | |
1504 | #define BBP1_TX_ANTENNA FIELD8(0x18) | |
1505 | ||
1506 | /* | |
1507 | * BBP 3: RX Antenna | |
1508 | */ | |
1509 | #define BBP3_RX_ANTENNA FIELD8(0x18) | |
1510 | #define BBP3_HT40_PLUS FIELD8(0x20) | |
1511 | ||
1512 | /* | |
1513 | * BBP 4: Bandwidth | |
1514 | */ | |
1515 | #define BBP4_TX_BF FIELD8(0x01) | |
1516 | #define BBP4_BANDWIDTH FIELD8(0x18) | |
1517 | ||
1518 | /* | |
1519 | * RFCSR registers | |
1520 | * The wordsize of the RFCSR is 8 bits. | |
1521 | */ | |
1522 | ||
1523 | /* | |
1524 | * RFCSR 6: | |
1525 | */ | |
1526 | #define RFCSR6_R FIELD8(0x03) | |
1527 | ||
1528 | /* | |
1529 | * RFCSR 7: | |
1530 | */ | |
1531 | #define RFCSR7_RF_TUNING FIELD8(0x01) | |
1532 | ||
1533 | /* | |
1534 | * RFCSR 12: | |
1535 | */ | |
1536 | #define RFCSR12_TX_POWER FIELD8(0x1f) | |
1537 | ||
1538 | /* | |
1539 | * RFCSR 22: | |
1540 | */ | |
1541 | #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) | |
1542 | ||
1543 | /* | |
1544 | * RFCSR 23: | |
1545 | */ | |
1546 | #define RFCSR23_FREQ_OFFSET FIELD8(0x7f) | |
1547 | ||
1548 | /* | |
1549 | * RFCSR 30: | |
1550 | */ | |
1551 | #define RFCSR30_RF_CALIBRATION FIELD8(0x80) | |
1552 | ||
1553 | /* | |
1554 | * RF registers | |
1555 | */ | |
1556 | ||
1557 | /* | |
1558 | * RF 2 | |
1559 | */ | |
1560 | #define RF2_ANTENNA_RX2 FIELD32(0x00000040) | |
1561 | #define RF2_ANTENNA_TX1 FIELD32(0x00004000) | |
1562 | #define RF2_ANTENNA_RX1 FIELD32(0x00020000) | |
1563 | ||
1564 | /* | |
1565 | * RF 3 | |
1566 | */ | |
1567 | #define RF3_TXPOWER_G FIELD32(0x00003e00) | |
1568 | #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) | |
1569 | #define RF3_TXPOWER_A FIELD32(0x00003c00) | |
1570 | ||
1571 | /* | |
1572 | * RF 4 | |
1573 | */ | |
1574 | #define RF4_TXPOWER_G FIELD32(0x000007c0) | |
1575 | #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) | |
1576 | #define RF4_TXPOWER_A FIELD32(0x00000780) | |
1577 | #define RF4_FREQ_OFFSET FIELD32(0x001f8000) | |
1578 | #define RF4_HT40 FIELD32(0x00200000) | |
1579 | ||
1580 | /* | |
1581 | * EEPROM content. | |
1582 | * The wordsize of the EEPROM is 16 bits. | |
1583 | */ | |
1584 | ||
1585 | /* | |
1586 | * EEPROM Version | |
1587 | */ | |
1588 | #define EEPROM_VERSION 0x0001 | |
1589 | #define EEPROM_VERSION_FAE FIELD16(0x00ff) | |
1590 | #define EEPROM_VERSION_VERSION FIELD16(0xff00) | |
1591 | ||
1592 | /* | |
1593 | * HW MAC address. | |
1594 | */ | |
1595 | #define EEPROM_MAC_ADDR_0 0x0002 | |
1596 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
1597 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
1598 | #define EEPROM_MAC_ADDR_1 0x0003 | |
1599 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | |
1600 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
1601 | #define EEPROM_MAC_ADDR_2 0x0004 | |
1602 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | |
1603 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
1604 | ||
1605 | /* | |
1606 | * EEPROM ANTENNA config | |
1607 | * RXPATH: 1: 1R, 2: 2R, 3: 3R | |
1608 | * TXPATH: 1: 1T, 2: 2T | |
1609 | */ | |
1610 | #define EEPROM_ANTENNA 0x001a | |
1611 | #define EEPROM_ANTENNA_RXPATH FIELD16(0x000f) | |
1612 | #define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0) | |
1613 | #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00) | |
1614 | ||
1615 | /* | |
1616 | * EEPROM NIC config | |
1617 | * CARDBUS_ACCEL: 0 - enable, 1 - disable | |
1618 | */ | |
1619 | #define EEPROM_NIC 0x001b | |
1620 | #define EEPROM_NIC_HW_RADIO FIELD16(0x0001) | |
1621 | #define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002) | |
1622 | #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004) | |
1623 | #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008) | |
1624 | #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010) | |
1625 | #define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020) | |
1626 | #define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040) | |
1627 | #define EEPROM_NIC_WPS_PBC FIELD16(0x0080) | |
1628 | #define EEPROM_NIC_BW40M_BG FIELD16(0x0100) | |
1629 | #define EEPROM_NIC_BW40M_A FIELD16(0x0200) | |
1630 | ||
1631 | /* | |
1632 | * EEPROM frequency | |
1633 | */ | |
1634 | #define EEPROM_FREQ 0x001d | |
1635 | #define EEPROM_FREQ_OFFSET FIELD16(0x00ff) | |
1636 | #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) | |
1637 | #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) | |
1638 | ||
1639 | /* | |
1640 | * EEPROM LED | |
1641 | * POLARITY_RDY_G: Polarity RDY_G setting. | |
1642 | * POLARITY_RDY_A: Polarity RDY_A setting. | |
1643 | * POLARITY_ACT: Polarity ACT setting. | |
1644 | * POLARITY_GPIO_0: Polarity GPIO0 setting. | |
1645 | * POLARITY_GPIO_1: Polarity GPIO1 setting. | |
1646 | * POLARITY_GPIO_2: Polarity GPIO2 setting. | |
1647 | * POLARITY_GPIO_3: Polarity GPIO3 setting. | |
1648 | * POLARITY_GPIO_4: Polarity GPIO4 setting. | |
1649 | * LED_MODE: Led mode. | |
1650 | */ | |
1651 | #define EEPROM_LED1 0x001e | |
1652 | #define EEPROM_LED2 0x001f | |
1653 | #define EEPROM_LED3 0x0020 | |
1654 | #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) | |
1655 | #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) | |
1656 | #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) | |
1657 | #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) | |
1658 | #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) | |
1659 | #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) | |
1660 | #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) | |
1661 | #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) | |
1662 | #define EEPROM_LED_LED_MODE FIELD16(0x1f00) | |
1663 | ||
1664 | /* | |
1665 | * EEPROM LNA | |
1666 | */ | |
1667 | #define EEPROM_LNA 0x0022 | |
1668 | #define EEPROM_LNA_BG FIELD16(0x00ff) | |
1669 | #define EEPROM_LNA_A0 FIELD16(0xff00) | |
1670 | ||
1671 | /* | |
1672 | * EEPROM RSSI BG offset | |
1673 | */ | |
1674 | #define EEPROM_RSSI_BG 0x0023 | |
1675 | #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) | |
1676 | #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) | |
1677 | ||
1678 | /* | |
1679 | * EEPROM RSSI BG2 offset | |
1680 | */ | |
1681 | #define EEPROM_RSSI_BG2 0x0024 | |
1682 | #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) | |
1683 | #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) | |
1684 | ||
1685 | /* | |
1686 | * EEPROM RSSI A offset | |
1687 | */ | |
1688 | #define EEPROM_RSSI_A 0x0025 | |
1689 | #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) | |
1690 | #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) | |
1691 | ||
1692 | /* | |
1693 | * EEPROM RSSI A2 offset | |
1694 | */ | |
1695 | #define EEPROM_RSSI_A2 0x0026 | |
1696 | #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) | |
1697 | #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) | |
1698 | ||
1699 | /* | |
1700 | * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. | |
1701 | * This is delta in 40MHZ. | |
1702 | * VALUE: Tx Power dalta value (MAX=4) | |
1703 | * TYPE: 1: Plus the delta value, 0: minus the delta value | |
1704 | * TXPOWER: Enable: | |
1705 | */ | |
1706 | #define EEPROM_TXPOWER_DELTA 0x0028 | |
1707 | #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f) | |
1708 | #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040) | |
1709 | #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080) | |
1710 | ||
1711 | /* | |
1712 | * EEPROM TXPOWER 802.11BG | |
1713 | */ | |
1714 | #define EEPROM_TXPOWER_BG1 0x0029 | |
1715 | #define EEPROM_TXPOWER_BG2 0x0030 | |
1716 | #define EEPROM_TXPOWER_BG_SIZE 7 | |
1717 | #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) | |
1718 | #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) | |
1719 | ||
1720 | /* | |
1721 | * EEPROM TXPOWER 802.11A | |
1722 | */ | |
1723 | #define EEPROM_TXPOWER_A1 0x003c | |
1724 | #define EEPROM_TXPOWER_A2 0x0053 | |
1725 | #define EEPROM_TXPOWER_A_SIZE 6 | |
1726 | #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) | |
1727 | #define EEPROM_TXPOWER_A_2 FIELD16(0xff00) | |
1728 | ||
1729 | /* | |
1730 | * EEPROM TXpower byrate: 20MHZ power | |
1731 | */ | |
1732 | #define EEPROM_TXPOWER_BYRATE 0x006f | |
1733 | ||
1734 | /* | |
1735 | * EEPROM BBP. | |
1736 | */ | |
1737 | #define EEPROM_BBP_START 0x0078 | |
1738 | #define EEPROM_BBP_SIZE 16 | |
1739 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
1740 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
1741 | ||
1742 | /* | |
1743 | * MCU mailbox commands. | |
1744 | */ | |
1745 | #define MCU_SLEEP 0x30 | |
1746 | #define MCU_WAKEUP 0x31 | |
1747 | #define MCU_RADIO_OFF 0x35 | |
1748 | #define MCU_CURRENT 0x36 | |
1749 | #define MCU_LED 0x50 | |
1750 | #define MCU_LED_STRENGTH 0x51 | |
1751 | #define MCU_LED_1 0x52 | |
1752 | #define MCU_LED_2 0x53 | |
1753 | #define MCU_LED_3 0x54 | |
1754 | #define MCU_RADAR 0x60 | |
1755 | #define MCU_BOOT_SIGNAL 0x72 | |
1756 | #define MCU_BBP_SIGNAL 0x80 | |
1757 | #define MCU_POWER_SAVE 0x83 | |
1758 | ||
1759 | /* | |
1760 | * MCU mailbox tokens | |
1761 | */ | |
1762 | #define TOKEN_WAKUP 3 | |
1763 | ||
1764 | /* | |
1765 | * DMA descriptor defines. | |
1766 | */ | |
1767 | #define TXD_DESC_SIZE ( 4 * sizeof(__le32) ) | |
1768 | #define TXWI_DESC_SIZE ( 4 * sizeof(__le32) ) | |
1769 | #define RXD_DESC_SIZE ( 4 * sizeof(__le32) ) | |
1770 | #define RXWI_DESC_SIZE ( 4 * sizeof(__le32) ) | |
1771 | ||
1772 | /* | |
1773 | * TX descriptor format for TX, PRIO and Beacon Ring. | |
1774 | */ | |
1775 | ||
1776 | /* | |
1777 | * Word0 | |
1778 | */ | |
1779 | #define TXD_W0_SD_PTR0 FIELD32(0xffffffff) | |
1780 | ||
1781 | /* | |
1782 | * Word1 | |
1783 | */ | |
1784 | #define TXD_W1_SD_LEN1 FIELD32(0x00003fff) | |
1785 | #define TXD_W1_LAST_SEC1 FIELD32(0x00004000) | |
1786 | #define TXD_W1_BURST FIELD32(0x00008000) | |
1787 | #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000) | |
1788 | #define TXD_W1_LAST_SEC0 FIELD32(0x40000000) | |
1789 | #define TXD_W1_DMA_DONE FIELD32(0x80000000) | |
1790 | ||
1791 | /* | |
1792 | * Word2 | |
1793 | */ | |
1794 | #define TXD_W2_SD_PTR1 FIELD32(0xffffffff) | |
1795 | ||
1796 | /* | |
1797 | * Word3 | |
1798 | * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI | |
1799 | * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler. | |
1800 | * 0:MGMT, 1:HCCA 2:EDCA | |
1801 | */ | |
1802 | #define TXD_W3_WIV FIELD32(0x01000000) | |
1803 | #define TXD_W3_QSEL FIELD32(0x06000000) | |
1804 | #define TXD_W3_TCO FIELD32(0x20000000) | |
1805 | #define TXD_W3_UCO FIELD32(0x40000000) | |
1806 | #define TXD_W3_ICO FIELD32(0x80000000) | |
1807 | ||
1808 | /* | |
1809 | * TX WI structure | |
1810 | */ | |
1811 | ||
1812 | /* | |
1813 | * Word0 | |
1814 | * FRAG: 1 To inform TKIP engine this is a fragment. | |
1815 | * MIMO_PS: The remote peer is in dynamic MIMO-PS mode | |
1816 | * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs | |
1817 | * BW: Channel bandwidth 20MHz or 40 MHz | |
1818 | * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED | |
1819 | */ | |
1820 | #define TXWI_W0_FRAG FIELD32(0x00000001) | |
1821 | #define TXWI_W0_MIMO_PS FIELD32(0x00000002) | |
1822 | #define TXWI_W0_CF_ACK FIELD32(0x00000004) | |
1823 | #define TXWI_W0_TS FIELD32(0x00000008) | |
1824 | #define TXWI_W0_AMPDU FIELD32(0x00000010) | |
1825 | #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) | |
1826 | #define TXWI_W0_TX_OP FIELD32(0x00000300) | |
1827 | #define TXWI_W0_MCS FIELD32(0x007f0000) | |
1828 | #define TXWI_W0_BW FIELD32(0x00800000) | |
1829 | #define TXWI_W0_SHORT_GI FIELD32(0x01000000) | |
1830 | #define TXWI_W0_STBC FIELD32(0x06000000) | |
1831 | #define TXWI_W0_IFS FIELD32(0x08000000) | |
1832 | #define TXWI_W0_PHYMODE FIELD32(0xc0000000) | |
1833 | ||
1834 | /* | |
1835 | * Word1 | |
1836 | */ | |
1837 | #define TXWI_W1_ACK FIELD32(0x00000001) | |
1838 | #define TXWI_W1_NSEQ FIELD32(0x00000002) | |
1839 | #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) | |
1840 | #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) | |
1841 | #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | |
1842 | #define TXWI_W1_PACKETID FIELD32(0xf0000000) | |
1843 | ||
1844 | /* | |
1845 | * Word2 | |
1846 | */ | |
1847 | #define TXWI_W2_IV FIELD32(0xffffffff) | |
1848 | ||
1849 | /* | |
1850 | * Word3 | |
1851 | */ | |
1852 | #define TXWI_W3_EIV FIELD32(0xffffffff) | |
1853 | ||
1854 | /* | |
1855 | * RX descriptor format for RX Ring. | |
1856 | */ | |
1857 | ||
1858 | /* | |
1859 | * Word0 | |
1860 | */ | |
1861 | #define RXD_W0_SDP0 FIELD32(0xffffffff) | |
1862 | ||
1863 | /* | |
1864 | * Word1 | |
1865 | */ | |
1866 | #define RXD_W1_SDL1 FIELD32(0x00003fff) | |
1867 | #define RXD_W1_SDL0 FIELD32(0x3fff0000) | |
1868 | #define RXD_W1_LS0 FIELD32(0x40000000) | |
1869 | #define RXD_W1_DMA_DONE FIELD32(0x80000000) | |
1870 | ||
1871 | /* | |
1872 | * Word2 | |
1873 | */ | |
1874 | #define RXD_W2_SDP1 FIELD32(0xffffffff) | |
1875 | ||
1876 | /* | |
1877 | * Word3 | |
1878 | * AMSDU: RX with 802.3 header, not 802.11 header. | |
1879 | * DECRYPTED: This frame is being decrypted. | |
1880 | */ | |
1881 | #define RXD_W3_BA FIELD32(0x00000001) | |
1882 | #define RXD_W3_DATA FIELD32(0x00000002) | |
1883 | #define RXD_W3_NULLDATA FIELD32(0x00000004) | |
1884 | #define RXD_W3_FRAG FIELD32(0x00000008) | |
1885 | #define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010) | |
1886 | #define RXD_W3_MULTICAST FIELD32(0x00000020) | |
1887 | #define RXD_W3_BROADCAST FIELD32(0x00000040) | |
1888 | #define RXD_W3_MY_BSS FIELD32(0x00000080) | |
1889 | #define RXD_W3_CRC_ERROR FIELD32(0x00000100) | |
1890 | #define RXD_W3_CIPHER_ERROR FIELD32(0x00000600) | |
1891 | #define RXD_W3_AMSDU FIELD32(0x00000800) | |
1892 | #define RXD_W3_HTC FIELD32(0x00001000) | |
1893 | #define RXD_W3_RSSI FIELD32(0x00002000) | |
1894 | #define RXD_W3_L2PAD FIELD32(0x00004000) | |
1895 | #define RXD_W3_AMPDU FIELD32(0x00008000) | |
1896 | #define RXD_W3_DECRYPTED FIELD32(0x00010000) | |
1897 | #define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000) | |
1898 | #define RXD_W3_PLCP_RSSI FIELD32(0x00040000) | |
1899 | ||
1900 | /* | |
1901 | * RX WI structure | |
1902 | */ | |
1903 | ||
1904 | /* | |
1905 | * Word0 | |
1906 | */ | |
1907 | #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) | |
1908 | #define RXWI_W0_KEY_INDEX FIELD32(0x00000300) | |
1909 | #define RXWI_W0_BSSID FIELD32(0x00001c00) | |
1910 | #define RXWI_W0_UDF FIELD32(0x0000e000) | |
1911 | #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | |
1912 | #define RXWI_W0_TID FIELD32(0xf0000000) | |
1913 | ||
1914 | /* | |
1915 | * Word1 | |
1916 | */ | |
1917 | #define RXWI_W1_FRAG FIELD32(0x0000000f) | |
1918 | #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) | |
1919 | #define RXWI_W1_MCS FIELD32(0x007f0000) | |
1920 | #define RXWI_W1_BW FIELD32(0x00800000) | |
1921 | #define RXWI_W1_SHORT_GI FIELD32(0x01000000) | |
1922 | #define RXWI_W1_STBC FIELD32(0x06000000) | |
1923 | #define RXWI_W1_PHYMODE FIELD32(0xc0000000) | |
1924 | ||
1925 | /* | |
1926 | * Word2 | |
1927 | */ | |
1928 | #define RXWI_W2_RSSI0 FIELD32(0x000000ff) | |
1929 | #define RXWI_W2_RSSI1 FIELD32(0x0000ff00) | |
1930 | #define RXWI_W2_RSSI2 FIELD32(0x00ff0000) | |
1931 | ||
1932 | /* | |
1933 | * Word3 | |
1934 | */ | |
1935 | #define RXWI_W3_SNR0 FIELD32(0x000000ff) | |
1936 | #define RXWI_W3_SNR1 FIELD32(0x0000ff00) | |
1937 | ||
1938 | /* | |
1939 | * Macros for converting txpower from EEPROM to mac80211 value | |
1940 | * and from mac80211 value to register value. | |
1941 | */ | |
1942 | #define MIN_G_TXPOWER 0 | |
1943 | #define MIN_A_TXPOWER -7 | |
1944 | #define MAX_G_TXPOWER 31 | |
1945 | #define MAX_A_TXPOWER 15 | |
1946 | #define DEFAULT_TXPOWER 5 | |
1947 | ||
1948 | #define TXPOWER_G_FROM_DEV(__txpower) \ | |
1949 | ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
1950 | ||
1951 | #define TXPOWER_G_TO_DEV(__txpower) \ | |
1952 | clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER) | |
1953 | ||
1954 | #define TXPOWER_A_FROM_DEV(__txpower) \ | |
1955 | ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
1956 | ||
1957 | #define TXPOWER_A_TO_DEV(__txpower) \ | |
1958 | clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER) | |
1959 | ||
1960 | #endif /* RT2800PCI_H */ |