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rt2x00: Remove superfluos empty line
[linux-2.6-block.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c
ID		 402
403 if (rt2x00_is_pci(rt2x00dev))
404 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
405
406 /*
407 * Disable DMA, will be reenabled later when enabling
408 * the radio.
409 */
410 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
412 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
417
418 /*
419 * Write firmware to the device.
420 */
421 rt2800_drv_write_firmware(rt2x00dev, data, len);
422
423 /*
424 * Wait for device to stabilize.
425 */
426 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
427 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
428 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
429 break;
430 msleep(1);
431 }
432
433 if (i == REGISTER_BUSY_COUNT) {
434 ERROR(rt2x00dev, "PBF system register not ready.\n");
435 return -EBUSY;
436 }
437
438 /*
439 * Initialize firmware.
440 */
441 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
442 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
443 msleep(1);
444
445 return 0;
446}
447EXPORT_SYMBOL_GPL(rt2800_load_firmware);
448
0c5879bc
ID		 449void rt2800_write_tx_data(struct queue_entry *entry,
450 struct txentry_desc *txdesc)
59679b91 451{
0c5879bc 452 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 453 u32 word;
454
455 /*
456 * Initialize TX Info descriptor
457 */
458 rt2x00_desc_read(txwi, 0, &word);
459 rt2x00_set_field32(&word, TXWI_W0_FRAG,
460 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 461 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
462 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 463 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
464 rt2x00_set_field32(&word, TXWI_W0_TS,
465 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
466 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
467 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
468 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
469 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
470 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
471 rt2x00_set_field32(&word, TXWI_W0_BW,
472 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
474 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
476 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
477 rt2x00_desc_write(txwi, 0, word);
478
479 rt2x00_desc_read(txwi, 1, &word);
480 rt2x00_set_field32(&word, TXWI_W1_ACK,
481 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
483 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
485 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
486 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
487 txdesc->key_idx : 0xff);
488 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
489 txdesc->length);
2b23cdaa 490 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 491 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 492 rt2x00_desc_write(txwi, 1, word);
493
494 /*
495 * Always write 0 to IV/EIV fields, hardware will insert the IV
496 * from the IVEIV register when TXD_W3_WIV is set to 0.
497 * When TXD_W3_WIV is set to 1 it will use the IV data
498 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
499 * crypto entry in the registers should be used to encrypt the frame.
500 */
501 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
502 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
503}
0c5879bc 504EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 505
ff6133be 506static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 507{
74861922
ID		 508 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
509 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
510 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
511 u16 eeprom;
512 u8 offset0;
513 u8 offset1;
514 u8 offset2;
515
e5ef5bad 516 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 517 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
518 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
519 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
520 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
521 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
522 } else {
523 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
524 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
525 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
526 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
527 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
528 }
529
530 /*
531 * Convert the value from the descriptor into the RSSI value
532 * If the value in the descriptor is 0, it is considered invalid
533 * and the default (extremely low) rssi value is assumed
534 */
535 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
536 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
537 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
538
539 /*
540 * mac80211 only accepts a single RSSI value. Calculating the
541 * average doesn't deliver a fair answer either since -60:-60 would
542 * be considered equally good as -50:-70 while the second is the one
543 * which gives less energy...
544 */
545 rssi0 = max(rssi0, rssi1);
546 return max(rssi0, rssi2);
547}
548
549void rt2800_process_rxwi(struct queue_entry *entry,
550 struct rxdone_entry_desc *rxdesc)
551{
552 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 553 u32 word;
554
555 rt2x00_desc_read(rxwi, 0, &word);
556
557 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
558 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
559
560 rt2x00_desc_read(rxwi, 1, &word);
561
562 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
563 rxdesc->flags |= RX_FLAG_SHORT_GI;
564
565 if (rt2x00_get_field32(word, RXWI_W1_BW))
566 rxdesc->flags |= RX_FLAG_40MHZ;
567
568 /*
569 * Detect RX rate, always use MCS as signal type.
570 */
571 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
572 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
573 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
574
575 /*
576 * Mask of 0x8 bit to remove the short preamble flag.
577 */
578 if (rxdesc->rate_mode == RATE_MODE_CCK)
579 rxdesc->signal &= ~0x8;
580
581 rt2x00_desc_read(rxwi, 2, &word);
582
74861922
ID		 583 /*
584 * Convert descriptor AGC value to RSSI value.
585 */
586 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 587
588 /*
589 * Remove RXWI descriptor from start of buffer.
590 */
74861922 591 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 592}
593EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
594
3613884d
ID		 595static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
596{
597 __le32 *txwi;
598 u32 word;
599 int wcid, ack, pid;
600 int tx_wcid, tx_ack, tx_pid;
601
602 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
603 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
604 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
605
606 /*
607 * This frames has returned with an IO error,
608 * so the status report is not intended for this
609 * frame.
610 */
611 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
612 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
613 return false;
614 }
615
616 /*
617 * Validate if this TX status report is intended for
618 * this entry by comparing the WCID/ACK/PID fields.
619 */
620 txwi = rt2800_drv_get_txwi(entry);
621
622 rt2x00_desc_read(txwi, 1, &word);
623 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
624 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
625 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
626
627 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
628 WARNING(entry->queue->rt2x00dev,
629 "TX status report missed for queue %d entry %d\n",
630 entry->queue->qid, entry->entry_idx);
631 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
632 return false;
633 }
634
635 return true;
636}
637
14433331
HS		 638void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
639{
640 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 641 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 642 struct txdone_entry_desc txdesc;
643 u32 word;
644 u16 mcs, real_mcs;
b34793ee 645 int aggr, ampdu;
14433331
HS		 646 __le32 *txwi;
647
648 /*
649 * Obtain the status about this packet.
650 */
651 txdesc.flags = 0;
652 txwi = rt2800_drv_get_txwi(entry);
653 rt2x00_desc_read(txwi, 0, &word);
b34793ee 654
14433331 655 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 656 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
657
14433331 658 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 659 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
660
661 /*
662 * If a frame was meant to be sent as a single non-aggregated MPDU
663 * but ended up in an aggregate the used tx rate doesn't correlate
664 * with the one specified in the TXWI as the whole aggregate is sent
665 * with the same rate.
666 *
667 * For example: two frames are sent to rt2x00, the first one sets
668 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
669 * and requests MCS15. If the hw aggregates both frames into one
670 * AMDPU the tx status for both frames will contain MCS7 although
671 * the frame was sent successfully.
672 *
673 * Hence, replace the requested rate with the real tx rate to not
674 * confuse the rate control algortihm by providing clearly wrong
675 * data.
676 */
677 if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
678 skbdesc->tx_rate_idx = real_mcs;
679 mcs = real_mcs;
680 }
14433331
HS		 681
682 /*
683 * Ralink has a retry mechanism using a global fallback
684 * table. We setup this fallback table to try the immediate
685 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
686 * always contains the MCS used for the last transmission, be
687 * it successful or not.
688 */
689 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
690 /*
691 * Transmission succeeded. The number of retries is
692 * mcs - real_mcs
693 */
694 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
695 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
696 } else {
697 /*
698 * Transmission failed. The number of retries is
699 * always 7 in this case (for a total number of 8
700 * frames sent).
701 */
702 __set_bit(TXDONE_FAILURE, &txdesc.flags);
703 txdesc.retry = rt2x00dev->long_retry;
704 }
705
706 /*
707 * the frame was retried at least once
708 * -> hw used fallback rates
709 */
710 if (txdesc.retry)
711 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
712
713 rt2x00lib_txdone(entry, &txdesc);
714}
715EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
716
96481b20
ID		 717void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
718{
719 struct data_queue *queue;
720 struct queue_entry *entry;
96481b20 721 u32 reg;
3613884d 722 u8 pid;
96481b20
ID		 723 int i;
724
725 /*
726 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
727 * at most X times and also stop processing once the TX_STA_FIFO_VALID
728 * flag is not set anymore.
729 *
730 * The legacy drivers use X=TX_RING_SIZE but state in a comment
731 * that the TX_STA_FIFO stack has a size of 16. We stick to our
732 * tx ring size for now.
733 */
efd2f271 734 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
96481b20
ID		 735 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
736 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
737 break;
738
96481b20
ID		 739 /*
740 * Skip this entry when it contains an invalid
741 * queue identication number.
742 */
bc8a979e 743 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
3613884d 744 if (pid >= QID_RX)
96481b20
ID		 745 continue;
746
3613884d 747 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 748 if (unlikely(!queue))
749 continue;
750
751 /*
752 * Inside each queue, we process each entry in a chronological
753 * order. We first check that the queue is not empty.
754 */
755 entry = NULL;
756 while (!rt2x00queue_empty(queue)) {
757 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 758 if (rt2800_txdone_entry_check(entry, reg))
96481b20 759 break;
96481b20
ID		 760 }
761
762 if (!entry || rt2x00queue_empty(queue))
763 break;
764
14433331 765 rt2800_txdone_entry(entry, reg);
96481b20
ID		 766 }
767}
768EXPORT_SYMBOL_GPL(rt2800_txdone);
769
f0194b2d
GW		 770void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
771{
772 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
774 unsigned int beacon_base;
739fd940 775 unsigned int padding_len;
d76dfc61 776 u32 orig_reg, reg;
f0194b2d
GW		 777
778 /*
779 * Disable beaconing while we are reloading the beacon data,
780 * otherwise we might be sending out invalid data.
781 */
782 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 783 orig_reg = reg;
f0194b2d
GW		 784 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
785 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
786
787 /*
788 * Add space for the TXWI in front of the skb.
789 */
790 skb_push(entry->skb, TXWI_DESC_SIZE);
791 memset(entry->skb, 0, TXWI_DESC_SIZE);
792
793 /*
794 * Register descriptor details in skb frame descriptor.
795 */
796 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
797 skbdesc->desc = entry->skb->data;
798 skbdesc->desc_len = TXWI_DESC_SIZE;
799
800 /*
801 * Add the TXWI for the beacon to the skb.
802 */
0c5879bc 803 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 804
805 /*
806 * Dump beacon to userspace through debugfs.
807 */
808 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
809
810 /*
739fd940 811 * Write entire beacon with TXWI and padding to register.
f0194b2d 812 */
739fd940 813 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 814 if (padding_len && skb_pad(entry->skb, padding_len)) {
815 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
816 /* skb freed by skb_pad() on failure */
817 entry->skb = NULL;
818 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
819 return;
820 }
821
f0194b2d 822 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 823 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
824 entry->skb->len + padding_len);
f0194b2d
GW		 825
826 /*
827 * Enable beaconing again.
828 */
f0194b2d
GW		 829 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
830 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
831
832 /*
833 * Clean up beacon skb.
834 */
835 dev_kfree_skb_any(entry->skb);
836 entry->skb = NULL;
837}
50e888ea 838EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 839
69cf36a4
HS		 840static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
841 unsigned int beacon_base)
fdb87251
HS		 842{
843 int i;
844
845 /*
846 * For the Beacon base registers we only need to clear
847 * the whole TXWI which (when set to 0) will invalidate
848 * the entire beacon.
849 */
850 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
851 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
852}
853
69cf36a4
HS		 854void rt2800_clear_beacon(struct queue_entry *entry)
855{
856 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
857 u32 reg;
858
859 /*
860 * Disable beaconing while we are reloading the beacon data,
861 * otherwise we might be sending out invalid data.
862 */
863 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
864 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
865 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
866
867 /*
868 * Clear beacon.
869 */
870 rt2800_clear_beacon_register(rt2x00dev,
871 HW_BEACON_OFFSET(entry->entry_idx));
872
873 /*
874 * Enabled beaconing again.
875 */
876 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
877 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
878}
879EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
880
f4450616
BZ		 881#ifdef CONFIG_RT2X00_LIB_DEBUGFS
882const struct rt2x00debug rt2800_rt2x00debug = {
883 .owner = THIS_MODULE,
884 .csr = {
885 .read = rt2800_register_read,
886 .write = rt2800_register_write,
887 .flags = RT2X00DEBUGFS_OFFSET,
888 .word_base = CSR_REG_BASE,
889 .word_size = sizeof(u32),
890 .word_count = CSR_REG_SIZE / sizeof(u32),
891 },
892 .eeprom = {
893 .read = rt2x00_eeprom_read,
894 .write = rt2x00_eeprom_write,
895 .word_base = EEPROM_BASE,
896 .word_size = sizeof(u16),
897 .word_count = EEPROM_SIZE / sizeof(u16),
898 },
899 .bbp = {
900 .read = rt2800_bbp_read,
901 .write = rt2800_bbp_write,
902 .word_base = BBP_BASE,
903 .word_size = sizeof(u8),
904 .word_count = BBP_SIZE / sizeof(u8),
905 },
906 .rf = {
907 .read = rt2x00_rf_read,
908 .write = rt2800_rf_write,
909 .word_base = RF_BASE,
910 .word_size = sizeof(u32),
911 .word_count = RF_SIZE / sizeof(u32),
912 },
913};
914EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
915#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
916
917int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
918{
919 u32 reg;
920
921 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
922 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
923}
924EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
925
926#ifdef CONFIG_RT2X00_LIB_LEDS
927static void rt2800_brightness_set(struct led_classdev *led_cdev,
928 enum led_brightness brightness)
929{
930 struct rt2x00_led *led =
931 container_of(led_cdev, struct rt2x00_led, led_dev);
932 unsigned int enabled = brightness != LED_OFF;
933 unsigned int bg_mode =
934 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
935 unsigned int polarity =
936 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
937 EEPROM_FREQ_LED_POLARITY);
938 unsigned int ledmode =
939 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
940 EEPROM_FREQ_LED_MODE);
941
942 if (led->type == LED_TYPE_RADIO) {
943 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
944 enabled ? 0x20 : 0);
945 } else if (led->type == LED_TYPE_ASSOC) {
946 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
947 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
948 } else if (led->type == LED_TYPE_QUALITY) {
949 /*
950 * The brightness is divided into 6 levels (0 - 5),
951 * The specs tell us the following levels:
952 * 0, 1 ,3, 7, 15, 31
953 * to determine the level in a simple way we can simply
954 * work with bitshifting:
955 * (1 << level) - 1
956 */
957 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
958 (1 << brightness / (LED_FULL / 6)) - 1,
959 polarity);
960 }
961}
962
963static int rt2800_blink_set(struct led_classdev *led_cdev,
964 unsigned long *delay_on, unsigned long *delay_off)
965{
966 struct rt2x00_led *led =
967 container_of(led_cdev, struct rt2x00_led, led_dev);
968 u32 reg;
969
970 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
971 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
972 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 973 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
974
975 return 0;
976}
977
b3579d6a 978static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 979 struct rt2x00_led *led, enum led_type type)
980{
981 led->rt2x00dev = rt2x00dev;
982 led->type = type;
983 led->led_dev.brightness_set = rt2800_brightness_set;
984 led->led_dev.blink_set = rt2800_blink_set;
985 led->flags = LED_INITIALIZED;
986}
f4450616
BZ		 987#endif /* CONFIG_RT2X00_LIB_LEDS */
988
989/*
990 * Configuration handlers.
991 */
992static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
993 struct rt2x00lib_crypto *crypto,
994 struct ieee80211_key_conf *key)
995{
996 struct mac_wcid_entry wcid_entry;
997 struct mac_iveiv_entry iveiv_entry;
998 u32 offset;
999 u32 reg;
1000
1001 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1002
e4a0ab34
ID		 1003 if (crypto->cmd == SET_KEY) {
1004 rt2800_register_read(rt2x00dev, offset, &reg);
1005 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1006 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1007 /*
1008 * Both the cipher as the BSS Idx numbers are split in a main
1009 * value of 3 bits, and a extended field for adding one additional
1010 * bit to the value.
1011 */
1012 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1013 (crypto->cipher & 0x7));
1014 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1015 (crypto->cipher & 0x8) >> 3);
1016 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1017 (crypto->bssidx & 0x7));
1018 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1019 (crypto->bssidx & 0x8) >> 3);
1020 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1021 rt2800_register_write(rt2x00dev, offset, reg);
1022 } else {
1023 rt2800_register_write(rt2x00dev, offset, 0);
1024 }
f4450616
BZ		 1025
1026 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1027
1028 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1029 if ((crypto->cipher == CIPHER_TKIP) ||
1030 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1031 (crypto->cipher == CIPHER_AES))
1032 iveiv_entry.iv[3] |= 0x20;
1033 iveiv_entry.iv[3] |= key->keyidx << 6;
1034 rt2800_register_multiwrite(rt2x00dev, offset,
1035 &iveiv_entry, sizeof(iveiv_entry));
1036
1037 offset = MAC_WCID_ENTRY(key->hw_key_idx);
1038
1039 memset(&wcid_entry, 0, sizeof(wcid_entry));
1040 if (crypto->cmd == SET_KEY)
10026f77 1041 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
f4450616
BZ		 1042 rt2800_register_multiwrite(rt2x00dev, offset,
1043 &wcid_entry, sizeof(wcid_entry));
1044}
1045
1046int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1047 struct rt2x00lib_crypto *crypto,
1048 struct ieee80211_key_conf *key)
1049{
1050 struct hw_key_entry key_entry;
1051 struct rt2x00_field32 field;
1052 u32 offset;
1053 u32 reg;
1054
1055 if (crypto->cmd == SET_KEY) {
1056 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1057
1058 memcpy(key_entry.key, crypto->key,
1059 sizeof(key_entry.key));
1060 memcpy(key_entry.tx_mic, crypto->tx_mic,
1061 sizeof(key_entry.tx_mic));
1062 memcpy(key_entry.rx_mic, crypto->rx_mic,
1063 sizeof(key_entry.rx_mic));
1064
1065 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1066 rt2800_register_multiwrite(rt2x00dev, offset,
1067 &key_entry, sizeof(key_entry));
1068 }
1069
1070 /*
1071 * The cipher types are stored over multiple registers
1072 * starting with SHARED_KEY_MODE_BASE each word will have
1073 * 32 bits and contains the cipher types for 2 bssidx each.
1074 * Using the correct defines correctly will cause overhead,
1075 * so just calculate the correct offset.
1076 */
1077 field.bit_offset = 4 * (key->hw_key_idx % 8);
1078 field.bit_mask = 0x7 << field.bit_offset;
1079
1080 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1081
1082 rt2800_register_read(rt2x00dev, offset, &reg);
1083 rt2x00_set_field32(&reg, field,
1084 (crypto->cmd == SET_KEY) * crypto->cipher);
1085 rt2800_register_write(rt2x00dev, offset, reg);
1086
1087 /*
1088 * Update WCID information
1089 */
1090 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1091
1092 return 0;
1093}
1094EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1095
1096int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1097 struct rt2x00lib_crypto *crypto,
1098 struct ieee80211_key_conf *key)
1099{
1100 struct hw_key_entry key_entry;
1101 u32 offset;
1102
1103 if (crypto->cmd == SET_KEY) {
1104 /*
1105 * 1 pairwise key is possible per AID, this means that the AID
1106 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1107 * last possible shared key entry.
2a0cfeb8
HS		 1108 *
1109 * Since parts of the pairwise key table might be shared with
1110 * the beacon frame buffers 6 & 7 we should only write into the
1111 * first 222 entries.
f4450616 1112 */
2a0cfeb8 1113 if (crypto->aid > (222 - 32))
f4450616
BZ		 1114 return -ENOSPC;
1115
1116 key->hw_key_idx = 32 + crypto->aid;
1117
1118 memcpy(key_entry.key, crypto->key,
1119 sizeof(key_entry.key));
1120 memcpy(key_entry.tx_mic, crypto->tx_mic,
1121 sizeof(key_entry.tx_mic));
1122 memcpy(key_entry.rx_mic, crypto->rx_mic,
1123 sizeof(key_entry.rx_mic));
1124
1125 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1126 rt2800_register_multiwrite(rt2x00dev, offset,
1127 &key_entry, sizeof(key_entry));
1128 }
1129
1130 /*
1131 * Update WCID information
1132 */
1133 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1134
1135 return 0;
1136}
1137EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1138
1139void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1140 const unsigned int filter_flags)
1141{
1142 u32 reg;
1143
1144 /*
1145 * Start configuration steps.
1146 * Note that the version error will always be dropped
1147 * and broadcast frames will always be accepted since
1148 * there is no filter for it at this time.
1149 */
1150 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1151 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1152 !(filter_flags & FIF_FCSFAIL));
1153 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1154 !(filter_flags & FIF_PLCPFAIL));
1155 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1156 !(filter_flags & FIF_PROMISC_IN_BSS));
1157 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1158 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1159 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1160 !(filter_flags & FIF_ALLMULTI));
1161 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1162 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1163 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1164 !(filter_flags & FIF_CONTROL));
1165 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1166 !(filter_flags & FIF_CONTROL));
1167 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1168 !(filter_flags & FIF_CONTROL));
1169 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1170 !(filter_flags & FIF_CONTROL));
1171 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1172 !(filter_flags & FIF_CONTROL));
1173 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1174 !(filter_flags & FIF_PSPOLL));
1175 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1176 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1177 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1178 !(filter_flags & FIF_CONTROL));
1179 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1180}
1181EXPORT_SYMBOL_GPL(rt2800_config_filter);
1182
1183void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1184 struct rt2x00intf_conf *conf, const unsigned int flags)
1185{
f4450616 1186 u32 reg;
fa8b4b22 1187 bool update_bssid = false;
f4450616
BZ		 1188
1189 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1190 /*
1191 * Enable synchronisation.
1192 */
1193 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1194 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616
BZ		 1195 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1196 }
1197
1198 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1199 if (flags & CONFIG_UPDATE_TYPE &&
1200 conf->sync == TSF_SYNC_AP_NONE) {
1201 /*
1202 * The BSSID register has to be set to our own mac
1203 * address in AP mode.
1204 */
1205 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1206 update_bssid = true;
1207 }
1208
c600c826
ID		 1209 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1210 reg = le32_to_cpu(conf->mac[1]);
1211 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1212 conf->mac[1] = cpu_to_le32(reg);
1213 }
f4450616
BZ		 1214
1215 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1216 conf->mac, sizeof(conf->mac));
1217 }
1218
fa8b4b22 1219 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1220 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1221 reg = le32_to_cpu(conf->bssid[1]);
1222 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1223 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1224 conf->bssid[1] = cpu_to_le32(reg);
1225 }
f4450616
BZ		 1226
1227 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1228 conf->bssid, sizeof(conf->bssid));
1229 }
1230}
1231EXPORT_SYMBOL_GPL(rt2800_config_intf);
1232
87c1915d
HS		 1233static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1234 struct rt2x00lib_erp *erp)
1235{
1236 bool any_sta_nongf = !!(erp->ht_opmode &
1237 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1238 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1239 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1240 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1241 u32 reg;
1242
1243 /* default protection rate for HT20: OFDM 24M */
1244 mm20_rate = gf20_rate = 0x4004;
1245
1246 /* default protection rate for HT40: duplicate OFDM 24M */
1247 mm40_rate = gf40_rate = 0x4084;
1248
1249 switch (protection) {
1250 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1251 /*
1252 * All STAs in this BSS are HT20/40 but there might be
1253 * STAs not supporting greenfield mode.
1254 * => Disable protection for HT transmissions.
1255 */
1256 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1257
1258 break;
1259 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1260 /*
1261 * All STAs in this BSS are HT20 or HT20/40 but there
1262 * might be STAs not supporting greenfield mode.
1263 * => Protect all HT40 transmissions.
1264 */
1265 mm20_mode = gf20_mode = 0;
1266 mm40_mode = gf40_mode = 2;
1267
1268 break;
1269 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1270 /*
1271 * Nonmember protection:
1272 * According to 802.11n we _should_ protect all
1273 * HT transmissions (but we don't have to).
1274 *
1275 * But if cts_protection is enabled we _shall_ protect
1276 * all HT transmissions using a CCK rate.
1277 *
1278 * And if any station is non GF we _shall_ protect
1279 * GF transmissions.
1280 *
1281 * We decide to protect everything
1282 * -> fall through to mixed mode.
1283 */
1284 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1285 /*
1286 * Legacy STAs are present
1287 * => Protect all HT transmissions.
1288 */
1289 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1290
1291 /*
1292 * If erp protection is needed we have to protect HT
1293 * transmissions with CCK 11M long preamble.
1294 */
1295 if (erp->cts_protection) {
1296 /* don't duplicate RTS/CTS in CCK mode */
1297 mm20_rate = mm40_rate = 0x0003;
1298 gf20_rate = gf40_rate = 0x0003;
1299 }
1300 break;
1301 };
1302
1303 /* check for STAs not supporting greenfield mode */
1304 if (any_sta_nongf)
1305 gf20_mode = gf40_mode = 2;
1306
1307 /* Update HT protection config */
1308 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1309 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1310 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1311 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1312
1313 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1314 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1315 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1316 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1317
1318 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1319 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1320 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1321 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1322
1323 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1324 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1325 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1326 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1327}
1328
02044643
HS		 1329void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1330 u32 changed)
f4450616
BZ		 1331{
1332 u32 reg;
1333
02044643
HS		 1334 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1335 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1336 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1337 !!erp->short_preamble);
1338 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1339 !!erp->short_preamble);
1340 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1341 }
f4450616 1342
02044643
HS		 1343 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1344 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1345 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1346 erp->cts_protection ? 2 : 0);
1347 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1348 }
f4450616 1349
02044643
HS		 1350 if (changed & BSS_CHANGED_BASIC_RATES) {
1351 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1352 erp->basic_rates);
1353 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1354 }
f4450616 1355
02044643
HS		 1356 if (changed & BSS_CHANGED_ERP_SLOT) {
1357 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1358 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1359 erp->slot_time);
1360 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1361
02044643
HS		 1362 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1363 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1364 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1365 }
f4450616 1366
02044643
HS		 1367 if (changed & BSS_CHANGED_BEACON_INT) {
1368 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1369 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1370 erp->beacon_int * 16);
1371 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1372 }
87c1915d
HS		 1373
1374 if (changed & BSS_CHANGED_HT)
1375 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1376}
1377EXPORT_SYMBOL_GPL(rt2800_config_erp);
1378
d96aa640
RJH		 1379static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1380 enum antenna ant)
1381{
1382 u32 reg;
1383 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1384 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1385
1386 if (rt2x00_is_pci(rt2x00dev)) {
1387 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1388 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1389 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1390 } else if (rt2x00_is_usb(rt2x00dev))
1391 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1392 eesk_pin, 0);
1393
1394 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1395 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD, 0);
1396 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1397 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1398}
1399
f4450616
BZ		 1400void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1401{
1402 u8 r1;
1403 u8 r3;
d96aa640 1404 u16 eeprom;
f4450616
BZ		 1405
1406 rt2800_bbp_read(rt2x00dev, 1, &r1);
1407 rt2800_bbp_read(rt2x00dev, 3, &r3);
1408
1409 /*
1410 * Configure the TX antenna.
1411 */
d96aa640 1412 switch (ant->tx_chain_num) {
f4450616
BZ		 1413 case 1:
1414 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1415 break;
1416 case 2:
1417 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1418 break;
1419 case 3:
e22557f2 1420 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1421 break;
1422 }
1423
1424 /*
1425 * Configure the RX antenna.
1426 */
d96aa640 1427 switch (ant->rx_chain_num) {
f4450616 1428 case 1:
d96aa640
RJH		 1429 if (rt2x00_rt(rt2x00dev, RT3070) ||
1430 rt2x00_rt(rt2x00dev, RT3090) ||
1431 rt2x00_rt(rt2x00dev, RT3390)) {
1432 rt2x00_eeprom_read(rt2x00dev,
1433 EEPROM_NIC_CONF1, &eeprom);
1434 if (rt2x00_get_field16(eeprom,
1435 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1436 rt2800_set_ant_diversity(rt2x00dev,
1437 rt2x00dev->default_ant.rx);
1438 }
f4450616
BZ		 1439 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1440 break;
1441 case 2:
1442 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1443 break;
1444 case 3:
1445 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1446 break;
1447 }
1448
1449 rt2800_bbp_write(rt2x00dev, 3, r3);
1450 rt2800_bbp_write(rt2x00dev, 1, r1);
1451}
1452EXPORT_SYMBOL_GPL(rt2800_config_ant);
1453
1454static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1455 struct rt2x00lib_conf *libconf)
1456{
1457 u16 eeprom;
1458 short lna_gain;
1459
1460 if (libconf->rf.channel <= 14) {
1461 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1462 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1463 } else if (libconf->rf.channel <= 64) {
1464 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1465 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1466 } else if (libconf->rf.channel <= 128) {
1467 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1468 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1469 } else {
1470 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1471 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1472 }
1473
1474 rt2x00dev->lna_gain = lna_gain;
1475}
1476
06855ef4
GW		 1477static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1478 struct ieee80211_conf *conf,
1479 struct rf_channel *rf,
1480 struct channel_info *info)
f4450616
BZ		 1481{
1482 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1483
d96aa640 1484 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1485 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1486
d96aa640 1487 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1488 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1489 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1490 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1491 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1492
1493 if (rf->channel > 14) {
1494 /*
1495 * When TX power is below 0, we should increase it by 7 to
1496 * make it a positive value (Minumum value is -7).
1497 * However this means that values between 0 and 7 have
1498 * double meaning, and we should set a 7DBm boost flag.
1499 */
1500 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1501 (info->default_power1 >= 0));
f4450616 1502
8d1331b3
ID		 1503 if (info->default_power1 < 0)
1504 info->default_power1 += 7;
f4450616 1505
8d1331b3 1506 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1507
1508 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1509 (info->default_power2 >= 0));
f4450616 1510
8d1331b3
ID		 1511 if (info->default_power2 < 0)
1512 info->default_power2 += 7;
f4450616 1513
8d1331b3 1514 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1515 } else {
8d1331b3
ID		 1516 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1517 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1518 }
1519
1520 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1521
1522 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1523 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1524 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1525 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1526
1527 udelay(200);
1528
1529 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1530 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1531 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1532 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1533
1534 udelay(200);
1535
1536 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1537 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1538 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1539 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1540}
1541
06855ef4
GW		 1542static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1543 struct ieee80211_conf *conf,
1544 struct rf_channel *rf,
1545 struct channel_info *info)
f4450616
BZ		 1546{
1547 u8 rfcsr;
1548
1549 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1550 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1551
1552 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1553 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1554 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1555
1556 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1557 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1558 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1559
5a673964 1560 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1561 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1562 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1563
f4450616
BZ		 1564 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1565 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1566 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1567
1568 rt2800_rfcsr_write(rt2x00dev, 24,
1569 rt2x00dev->calibration[conf_is_ht40(conf)]);
1570
71976907 1571 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1572 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1573 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1574}
1575
1576static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1577 struct ieee80211_conf *conf,
1578 struct rf_channel *rf,
1579 struct channel_info *info)
1580{
1581 u32 reg;
1582 unsigned int tx_pin;
1583 u8 bbp;
1584
46323e11 1585 if (rf->channel <= 14) {
8d1331b3
ID		 1586 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1587 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1588 } else {
8d1331b3
ID		 1589 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1590 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1591 }
1592
06855ef4
GW		 1593 if (rt2x00_rf(rt2x00dev, RF2020) ||
1594 rt2x00_rf(rt2x00dev, RF3020) ||
1595 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11 1596 rt2x00_rf(rt2x00dev, RF3022) ||
f93bc9b3
GW		 1597 rt2x00_rf(rt2x00dev, RF3052) ||
1598 rt2x00_rf(rt2x00dev, RF3320))
06855ef4 1599 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1600 else
06855ef4 1601 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1602
1603 /*
1604 * Change BBP settings
1605 */
1606 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1607 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1608 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1609 rt2800_bbp_write(rt2x00dev, 86, 0);
1610
1611 if (rf->channel <= 14) {
1612 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1613 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1614 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1615 } else {
1616 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1617 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1618 }
1619 } else {
1620 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1621
1622 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1623 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1624 else
1625 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1626 }
1627
1628 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1629 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1630 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1631 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1632 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1633
1634 tx_pin = 0;
1635
1636 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1637 if (rt2x00dev->default_ant.tx_chain_num == 2) {
f4450616
BZ		 1638 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1639 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1640 }
1641
1642 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1643 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 1644 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1645 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1646 }
1647
1648 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1649 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1650 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1651 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1652 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1653 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1654
1655 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1656
1657 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1658 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1659 rt2800_bbp_write(rt2x00dev, 4, bbp);
1660
1661 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1662 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1663 rt2800_bbp_write(rt2x00dev, 3, bbp);
1664
8d0c9b65 1665 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1666 if (conf_is_ht40(conf)) {
1667 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1668 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1669 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1670 } else {
1671 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1672 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1673 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1674 }
1675 }
1676
1677 msleep(1);
977206d7
HS		 1678
1679 /*
1680 * Clear channel statistic counters
1681 */
1682 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1683 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1684 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 1685}
1686
e90c54b2
RJH		 1687static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1688 enum ieee80211_band band)
1689{
1690 u16 eeprom;
1691 u8 comp_en;
1692 u8 comp_type;
1693 int comp_value;
1694
1695 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1696
1697 if (eeprom == 0xffff)
1698 return 0;
1699
1700 if (band == IEEE80211_BAND_2GHZ) {
1701 comp_en = rt2x00_get_field16(eeprom,
1702 EEPROM_TXPOWER_DELTA_ENABLE_2G);
1703 if (comp_en) {
1704 comp_type = rt2x00_get_field16(eeprom,
1705 EEPROM_TXPOWER_DELTA_TYPE_2G);
1706 comp_value = rt2x00_get_field16(eeprom,
1707 EEPROM_TXPOWER_DELTA_VALUE_2G);
1708 if (!comp_type)
1709 comp_value = -comp_value;
1710 }
1711 } else {
1712 comp_en = rt2x00_get_field16(eeprom,
1713 EEPROM_TXPOWER_DELTA_ENABLE_5G);
1714 if (comp_en) {
1715 comp_type = rt2x00_get_field16(eeprom,
1716 EEPROM_TXPOWER_DELTA_TYPE_5G);
1717 comp_value = rt2x00_get_field16(eeprom,
1718 EEPROM_TXPOWER_DELTA_VALUE_5G);
1719 if (!comp_type)
1720 comp_value = -comp_value;
1721 }
1722 }
1723
1724 return comp_value;
1725}
1726
1727static u8 rt2800_compesate_txpower(struct rt2x00_dev *rt2x00dev,
1728 int is_rate_b,
1729 enum ieee80211_band band,
1730 int power_level,
1731 u8 txpower)
1732{
1733 u32 reg;
1734 u16 eeprom;
1735 u8 criterion;
1736 u8 eirp_txpower;
1737 u8 eirp_txpower_criterion;
1738 u8 reg_limit;
1739 int bw_comp = 0;
1740
1741 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
1742 return txpower;
1743
1744 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1745 bw_comp = rt2800_get_txpower_bw_comp(rt2x00dev, band);
1746
1747 if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
1748 /*
1749 * Check if eirp txpower exceed txpower_limit.
1750 * We use OFDM 6M as criterion and its eirp txpower
1751 * is stored at EEPROM_EIRP_MAX_TX_POWER.
1752 * .11b data rate need add additional 4dbm
1753 * when calculating eirp txpower.
1754 */
1755 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1756 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
1757
1758 rt2x00_eeprom_read(rt2x00dev,
1759 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
1760
1761 if (band == IEEE80211_BAND_2GHZ)
1762 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1763 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
1764 else
1765 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1766 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
1767
1768 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
1769 (is_rate_b ? 4 : 0) + bw_comp;
1770
1771 reg_limit = (eirp_txpower > power_level) ?
1772 (eirp_txpower - power_level) : 0;
1773 } else
1774 reg_limit = 0;
1775
1776 return txpower + bw_comp - reg_limit;
1777}
1778
f4450616 1779static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
e90c54b2 1780 struct ieee80211_conf *conf)
f4450616 1781{
5e846004 1782 u8 txpower;
5e846004 1783 u16 eeprom;
e90c54b2 1784 int i, is_rate_b;
f4450616 1785 u32 reg;
f4450616 1786 u8 r1;
5e846004 1787 u32 offset;
e90c54b2
RJH		 1788 enum ieee80211_band band = conf->channel->band;
1789 int power_level = conf->power_level;
f4450616 1790
5e846004 1791 /*
e90c54b2 1792 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 1793 */
f4450616 1794 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 1795 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 1796 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 1797 offset = TX_PWR_CFG_0;
1798
1799 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1800 /* just to be safe */
1801 if (offset > TX_PWR_CFG_4)
1802 break;
1803
1804 rt2800_register_read(rt2x00dev, offset, &reg);
1805
1806 /* read the next four txpower values */
1807 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1808 &eeprom);
1809
e90c54b2
RJH		 1810 is_rate_b = i ? 0 : 1;
1811 /*
1812 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 1813 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 1814 * TX_PWR_CFG_4: unknown
1815 */
5e846004
HS		 1816 txpower = rt2x00_get_field16(eeprom,
1817 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2
RJH		 1818 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1819 power_level, txpower);
1820 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 1821
e90c54b2
RJH		 1822 /*
1823 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 1824 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 1825 * TX_PWR_CFG_4: unknown
1826 */
5e846004
HS		 1827 txpower = rt2x00_get_field16(eeprom,
1828 EEPROM_TXPOWER_BYRATE_RATE1);
e90c54b2
RJH		 1829 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1830 power_level, txpower);
1831 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 1832
e90c54b2
RJH		 1833 /*
1834 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 1835 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 1836 * TX_PWR_CFG_4: unknown
1837 */
5e846004
HS		 1838 txpower = rt2x00_get_field16(eeprom,
1839 EEPROM_TXPOWER_BYRATE_RATE2);
e90c54b2
RJH		 1840 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1841 power_level, txpower);
1842 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 1843
e90c54b2
RJH		 1844 /*
1845 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 1846 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 1847 * TX_PWR_CFG_4: unknown
1848 */
5e846004
HS		 1849 txpower = rt2x00_get_field16(eeprom,
1850 EEPROM_TXPOWER_BYRATE_RATE3);
e90c54b2
RJH		 1851 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1852 power_level, txpower);
1853 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 1854
1855 /* read the next four txpower values */
1856 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1857 &eeprom);
1858
e90c54b2
RJH		 1859 is_rate_b = 0;
1860 /*
1861 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 1862 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 1863 * TX_PWR_CFG_4: unknown
1864 */
5e846004
HS		 1865 txpower = rt2x00_get_field16(eeprom,
1866 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2
RJH		 1867 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1868 power_level, txpower);
1869 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 1870
e90c54b2
RJH		 1871 /*
1872 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 1873 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 1874 * TX_PWR_CFG_4: unknown
1875 */
5e846004
HS		 1876 txpower = rt2x00_get_field16(eeprom,
1877 EEPROM_TXPOWER_BYRATE_RATE1);
e90c54b2
RJH		 1878 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1879 power_level, txpower);
1880 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 1881
e90c54b2
RJH		 1882 /*
1883 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 1884 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 1885 * TX_PWR_CFG_4: unknown
1886 */
5e846004
HS		 1887 txpower = rt2x00_get_field16(eeprom,
1888 EEPROM_TXPOWER_BYRATE_RATE2);
e90c54b2
RJH		 1889 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1890 power_level, txpower);
1891 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 1892
e90c54b2
RJH		 1893 /*
1894 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 1895 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 1896 * TX_PWR_CFG_4: unknown
1897 */
5e846004
HS		 1898 txpower = rt2x00_get_field16(eeprom,
1899 EEPROM_TXPOWER_BYRATE_RATE3);
e90c54b2
RJH		 1900 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1901 power_level, txpower);
1902 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 1903
1904 rt2800_register_write(rt2x00dev, offset, reg);
1905
1906 /* next TX_PWR_CFG register */
1907 offset += 4;
1908 }
f4450616
BZ		 1909}
1910
1911static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1912 struct rt2x00lib_conf *libconf)
1913{
1914 u32 reg;
1915
1916 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1917 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1918 libconf->conf->short_frame_max_tx_count);
1919 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1920 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1921 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1922}
1923
1924static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1925 struct rt2x00lib_conf *libconf)
1926{
1927 enum dev_state state =
1928 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1929 STATE_SLEEP : STATE_AWAKE;
1930 u32 reg;
1931
1932 if (state == STATE_SLEEP) {
1933 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1934
1935 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1936 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1937 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1938 libconf->conf->listen_interval - 1);
1939 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1940 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1941
1942 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1943 } else {
f4450616
BZ		 1944 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1945 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1946 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1947 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1948 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1949
1950 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1951 }
1952}
1953
1954void rt2800_config(struct rt2x00_dev *rt2x00dev,
1955 struct rt2x00lib_conf *libconf,
1956 const unsigned int flags)
1957{
1958 /* Always recalculate LNA gain before changing configuration */
1959 rt2800_config_lna_gain(rt2x00dev, libconf);
1960
e90c54b2 1961 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 1962 rt2800_config_channel(rt2x00dev, libconf->conf,
1963 &libconf->rf, &libconf->channel);
e90c54b2
RJH		 1964 rt2800_config_txpower(rt2x00dev, libconf->conf);
1965 }
f4450616 1966 if (flags & IEEE80211_CONF_CHANGE_POWER)
e90c54b2 1967 rt2800_config_txpower(rt2x00dev, libconf->conf);
f4450616
BZ		 1968 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1969 rt2800_config_retry_limit(rt2x00dev, libconf);
1970 if (flags & IEEE80211_CONF_CHANGE_PS)
1971 rt2800_config_ps(rt2x00dev, libconf);
1972}
1973EXPORT_SYMBOL_GPL(rt2800_config);
1974
1975/*
1976 * Link tuning
1977 */
1978void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1979{
1980 u32 reg;
1981
1982 /*
1983 * Update FCS error count from register.
1984 */
1985 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1986 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1987}
1988EXPORT_SYMBOL_GPL(rt2800_link_stats);
1989
1990static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1991{
1992 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1993 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1994 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1995 rt2x00_rt(rt2x00dev, RT3090) ||
1996 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1997 return 0x1c + (2 * rt2x00dev->lna_gain);
1998 else
1999 return 0x2e + rt2x00dev->lna_gain;
2000 }
2001
2002 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2003 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2004 else
2005 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2006}
2007
2008static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2009 struct link_qual *qual, u8 vgc_level)
2010{
2011 if (qual->vgc_level != vgc_level) {
2012 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2013 qual->vgc_level = vgc_level;
2014 qual->vgc_level_reg = vgc_level;
2015 }
2016}
2017
2018void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2019{
2020 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2021}
2022EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2023
2024void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2025 const u32 count)
2026{
8d0c9b65 2027 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2028 return;
2029
2030 /*
2031 * When RSSI is better then -80 increase VGC level with 0x10
2032 */
2033 rt2800_set_vgc(rt2x00dev, qual,
2034 rt2800_get_default_vgc(rt2x00dev) +
2035 ((qual->rssi > -80) * 0x10));
2036}
2037EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2038
2039/*
2040 * Initialization functions.
2041 */
b9a07ae9 2042static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2043{
2044 u32 reg;
d5385bfc 2045 u16 eeprom;
fcf51541 2046 unsigned int i;
e3a896b9 2047 int ret;
fcf51541 2048
a9dce149
GW		 2049 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2050 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2051 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2052 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2053 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2054 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2055 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2056
e3a896b9
GW		 2057 ret = rt2800_drv_init_registers(rt2x00dev);
2058 if (ret)
2059 return ret;
fcf51541
BZ		 2060
2061 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2062 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2063 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2064 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2065 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2066 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2067
2068 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2069 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2070 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2071 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2072 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2073 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2074
2075 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2076 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2077
2078 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2079
2080 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2081 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2082 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2083 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2084 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2085 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2086 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2087 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2088
a9dce149
GW		 2089 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2090
2091 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2092 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2093 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2094 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2095
64522957 2096 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2097 rt2x00_rt(rt2x00dev, RT3090) ||
2098 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 2099 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2100 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 2101 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2102 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2103 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 2104 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2105 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2106 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2107 0x0000002c);
2108 else
2109 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2110 0x0000000f);
2111 } else {
2112 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2113 }
d5385bfc 2114 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2115 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2116
2117 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2118 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2119 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2120 } else {
2121 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2122 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2123 }
c295a81d
HS		 2124 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2125 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2126 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2127 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 2128 } else {
2129 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2130 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2131 }
2132
2133 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2134 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2135 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2136 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2137 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2138 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2139 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2140 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2141 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2142 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2143
2144 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2145 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2146 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2147 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2148 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2149
2150 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2151 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2152 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2153 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2154 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2155 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2156 else
2157 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2158 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2159 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2160 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2161
a9dce149
GW		 2162 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2163 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2164 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2165 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2166 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2167 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2168 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2169 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2170 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2171
fcf51541
BZ		 2172 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2173
a9dce149
GW		 2174 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2175 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2176 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2177 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2178 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2179 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2180 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2181 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2182
fcf51541
BZ		 2183 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2184 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2185 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2186 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2187 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2188 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2189 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2190 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2191 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2192
2193 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2194 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2195 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2196 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
2197 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2198 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2199 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2200 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2201 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2202 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2203 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2204 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2205
2206 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2207 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2208 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2209 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
2210 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2211 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2212 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2213 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2214 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2215 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2216 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2217 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2218
2219 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2220 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2221 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2222 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2223 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2224 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2225 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2226 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2227 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2228 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2229 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2230 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2231
2232 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2233 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2234 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
fcf51541
BZ		 2235 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2236 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2237 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2238 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2239 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2240 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2241 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2242 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2243 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2244
2245 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2246 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2247 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2248 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2249 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2250 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2251 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2252 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2253 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2254 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2255 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2256 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2257
2258 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2259 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2260 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2261 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2262 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2263 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2264 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2265 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2266 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2267 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2268 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2269 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2270
cea90e55 2271 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2272 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2273
2274 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2275 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2276 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2277 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2278 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2284 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2285 }
2286
961621ab
HS		 2287 /*
2288 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2289 * although it is reserved.
2290 */
2291 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2292 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2293 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2294 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2295 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2296 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2297 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2298 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2299 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2300 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2301 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2302 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2303
fcf51541
BZ		 2304 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2305
2306 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2307 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2308 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2309 IEEE80211_MAX_RTS_THRESHOLD);
2310 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2311 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2312
2313 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2314
a21c2ab4
HS		 2315 /*
2316 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2317 * time should be set to 16. However, the original Ralink driver uses
2318 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2319 * connection problems with 11g + CTS protection. Hence, use the same
2320 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2321 */
a9dce149 2322 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2323 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2324 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2325 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2326 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2327 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2328 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2329
fcf51541
BZ		 2330 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2331
2332 /*
2333 * ASIC will keep garbage value after boot, clear encryption keys.
2334 */
2335 for (i = 0; i < 4; i++)
2336 rt2800_register_write(rt2x00dev,
2337 SHARED_KEY_MODE_ENTRY(i), 0);
2338
2339 for (i = 0; i < 256; i++) {
f4e16e41 2340 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
fcf51541
BZ		 2341 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2342 wcid, sizeof(wcid));
2343
2344 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2345 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2346 }
2347
2348 /*
2349 * Clear all beacons
fcf51541 2350 */
69cf36a4
HS		 2351 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2352 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2353 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2354 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2355 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2356 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2357 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2358 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2359
cea90e55 2360 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2361 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2362 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2363 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 2364 } else if (rt2x00_is_pcie(rt2x00dev)) {
2365 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2366 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2367 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2368 }
2369
2370 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2371 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2372 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2373 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2374 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2375 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2376 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2377 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2378 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2379 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2380
2381 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2382 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2383 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2384 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2385 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2386 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2387 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2388 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2389 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2390 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2391
2392 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2393 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2394 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2395 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2396 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2397 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2398 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2399 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2400 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2401 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2402
2403 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2404 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2405 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2406 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2407 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2408 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2409
47ee3eb1
HS		 2410 /*
2411 * Do not force the BA window size, we use the TXWI to set it
2412 */
2413 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2414 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2415 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2416 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2417
fcf51541
BZ		 2418 /*
2419 * We must clear the error counters.
2420 * These registers are cleared on read,
2421 * so we may pass a useless variable to store the value.
2422 */
2423 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2424 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2425 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2426 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2427 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2428 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2429
9f926fb5
HS		 2430 /*
2431 * Setup leadtime for pre tbtt interrupt to 6ms
2432 */
2433 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2434 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2435 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2436
977206d7
HS		 2437 /*
2438 * Set up channel statistics timer
2439 */
2440 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2441 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2442 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2443 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2444 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2445 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2446 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2447
fcf51541
BZ		 2448 return 0;
2449}
fcf51541
BZ		 2450
2451static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2452{
2453 unsigned int i;
2454 u32 reg;
2455
2456 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2457 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2458 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2459 return 0;
2460
2461 udelay(REGISTER_BUSY_DELAY);
2462 }
2463
2464 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2465 return -EACCES;
2466}
2467
2468static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2469{
2470 unsigned int i;
2471 u8 value;
2472
2473 /*
2474 * BBP was enabled after firmware was loaded,
2475 * but we need to reactivate it now.
2476 */
2477 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2478 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2479 msleep(1);
2480
2481 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2482 rt2800_bbp_read(rt2x00dev, 0, &value);
2483 if ((value != 0xff) && (value != 0x00))
2484 return 0;
2485 udelay(REGISTER_BUSY_DELAY);
2486 }
2487
2488 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2489 return -EACCES;
2490}
2491
b9a07ae9 2492static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2493{
2494 unsigned int i;
2495 u16 eeprom;
2496 u8 reg_id;
2497 u8 value;
2498
2499 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2500 rt2800_wait_bbp_ready(rt2x00dev)))
2501 return -EACCES;
2502
baff8006
HS		 2503 if (rt2800_is_305x_soc(rt2x00dev))
2504 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2505
fcf51541
BZ		 2506 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2507 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2508
2509 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2510 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2511 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2512 } else {
2513 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2514 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2515 }
2516
fcf51541 2517 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2518
d5385bfc 2519 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2520 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2521 rt2x00_rt(rt2x00dev, RT3090) ||
2522 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2523 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2524 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2525 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2526 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2527 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2528 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2529 } else {
2530 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2531 }
2532
fcf51541
BZ		 2533 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2534 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2535
5ed8f458 2536 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2537 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2538 else
2539 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2540
fcf51541
BZ		 2541 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2542 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2543 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2544
d5385bfc 2545 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2546 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2547 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2548 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2549 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2550 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2551 else
2552 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2553
baff8006
HS		 2554 if (rt2800_is_305x_soc(rt2x00dev))
2555 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2556 else
2557 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2558 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2559
64522957 2560 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2561 rt2x00_rt(rt2x00dev, RT3090) ||
2562 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2563 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2564
38c8a566
RJH		 2565 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2566 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 2567 value |= 0x20;
38c8a566 2568 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 2569 value &= ~0x02;
fcf51541 2570
d5385bfc 2571 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2572 }
2573
fcf51541
BZ		 2574
2575 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2576 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2577
2578 if (eeprom != 0xffff && eeprom != 0x0000) {
2579 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2580 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2581 rt2800_bbp_write(rt2x00dev, reg_id, value);
2582 }
2583 }
2584
2585 return 0;
2586}
fcf51541
BZ		 2587
2588static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2589 bool bw40, u8 rfcsr24, u8 filter_target)
2590{
2591 unsigned int i;
2592 u8 bbp;
2593 u8 rfcsr;
2594 u8 passband;
2595 u8 stopband;
2596 u8 overtuned = 0;
2597
2598 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2599
2600 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2601 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2602 rt2800_bbp_write(rt2x00dev, 4, bbp);
2603
80d184e6
RJH		 2604 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2605 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2606 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2607
fcf51541
BZ		 2608 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2609 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2610 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2611
2612 /*
2613 * Set power & frequency of passband test tone
2614 */
2615 rt2800_bbp_write(rt2x00dev, 24, 0);
2616
2617 for (i = 0; i < 100; i++) {
2618 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2619 msleep(1);
2620
2621 rt2800_bbp_read(rt2x00dev, 55, &passband);
2622 if (passband)
2623 break;
2624 }
2625
2626 /*
2627 * Set power & frequency of stopband test tone
2628 */
2629 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2630
2631 for (i = 0; i < 100; i++) {
2632 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2633 msleep(1);
2634
2635 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2636
2637 if ((passband - stopband) <= filter_target) {
2638 rfcsr24++;
2639 overtuned += ((passband - stopband) == filter_target);
2640 } else
2641 break;
2642
2643 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2644 }
2645
2646 rfcsr24 -= !!overtuned;
2647
2648 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2649 return rfcsr24;
2650}
2651
b9a07ae9 2652static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2653{
2654 u8 rfcsr;
2655 u8 bbp;
8cdd15e0
GW		 2656 u32 reg;
2657 u16 eeprom;
fcf51541 2658
d5385bfc 2659 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2660 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2661 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2662 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2663 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2664 return 0;
2665
fcf51541
BZ		 2666 /*
2667 * Init RF calibration.
2668 */
2669 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2670 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2671 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2672 msleep(1);
2673 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2674 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2675
d5385bfc 2676 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2677 rt2x00_rt(rt2x00dev, RT3071) ||
2678 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2679 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2680 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2681 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 2682 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 2683 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2684 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2685 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2686 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2687 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2688 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2689 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2690 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2691 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2692 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2693 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2694 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2695 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2696 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2697 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2698 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2699 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2700 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2701 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2702 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2703 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2704 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2705 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2706 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2707 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2708 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2709 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2710 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2711 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2712 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2713 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2714 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2715 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2716 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2717 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2718 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2719 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2720 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2721 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2722 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2723 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2724 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2725 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2726 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2727 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2728 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2729 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2730 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2731 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2732 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2733 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2734 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2735 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2736 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2737 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2738 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2739 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2740 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2741 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2742 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2743 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2744 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2745 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2746 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2747 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2748 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2749 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2750 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2751 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2752 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2753 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2754 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2755 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2756 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2757 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2758 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2759 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2760 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2761 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2762 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2763 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2764 return 0;
8cdd15e0
GW		 2765 }
2766
2767 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2768 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2769 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2770 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2771 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2772 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2773 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 2774 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2775
d5385bfc
GW		 2776 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2777 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2778 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2779
d5385bfc
GW		 2780 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2781 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2782 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2783 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 2784 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2785 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2786 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2787 else
2788 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2789 }
2790 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 2791
2792 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2793 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2794 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 2795 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2796 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2797 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2798 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2799 }
2800
2801 /*
2802 * Set RX Filter calibration for 20MHz and 40MHz
2803 */
8cdd15e0
GW		 2804 if (rt2x00_rt(rt2x00dev, RT3070)) {
2805 rt2x00dev->calibration[0] =
2806 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2807 rt2x00dev->calibration[1] =
2808 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2809 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2810 rt2x00_rt(rt2x00dev, RT3090) ||
2811 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2812 rt2x00dev->calibration[0] =
2813 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2814 rt2x00dev->calibration[1] =
2815 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2816 }
fcf51541
BZ		 2817
2818 /*
2819 * Set back to initial state
2820 */
2821 rt2800_bbp_write(rt2x00dev, 24, 0);
2822
2823 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2824 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2825 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2826
2827 /*
2828 * set BBP back to BW20
2829 */
2830 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2831 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2832 rt2800_bbp_write(rt2x00dev, 4, bbp);
2833
d5385bfc 2834 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2835 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2836 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2837 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2838 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2839
2840 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2841 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2842 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2843
2844 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2845 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
80d184e6
RJH		 2846 if (rt2x00_rt(rt2x00dev, RT3070) ||
2847 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2848 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2849 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
80d184e6 2850 if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2851 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2852 }
8cdd15e0
GW		 2853 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2854 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2855 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2856 rt2x00_get_field16(eeprom,
2857 EEPROM_TXMIXER_GAIN_BG_VAL));
2858 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2859
64522957
GW		 2860 if (rt2x00_rt(rt2x00dev, RT3090)) {
2861 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2862
80d184e6 2863 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 2864 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2865 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 2866 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 2867 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 2868 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2869
2870 rt2800_bbp_write(rt2x00dev, 138, bbp);
2871 }
2872
2873 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2874 rt2x00_rt(rt2x00dev, RT3090) ||
2875 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2876 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2877 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2878 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2879 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2880 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2881 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2882 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2883
2884 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2885 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2886 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2887
2888 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2889 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2890 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2891
2892 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2893 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2894 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2895 }
2896
80d184e6 2897 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 2898 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 2899 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 2900 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2901 else
2902 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2903 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2904 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2905 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2906 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2907 }
2908
fcf51541
BZ		 2909 return 0;
2910}
b9a07ae9
ID		 2911
2912int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2913{
2914 u32 reg;
2915 u16 word;
2916
2917 /*
2918 * Initialize all registers.
2919 */
2920 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2921 rt2800_init_registers(rt2x00dev) ||
2922 rt2800_init_bbp(rt2x00dev) ||
2923 rt2800_init_rfcsr(rt2x00dev)))
2924 return -EIO;
2925
2926 /*
2927 * Send signal to firmware during boot time.
2928 */
2929 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2930
2931 if (rt2x00_is_usb(rt2x00dev) &&
2932 (rt2x00_rt(rt2x00dev, RT3070) ||
2933 rt2x00_rt(rt2x00dev, RT3071) ||
2934 rt2x00_rt(rt2x00dev, RT3572))) {
2935 udelay(200);
2936 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2937 udelay(10);
2938 }
2939
2940 /*
2941 * Enable RX.
2942 */
2943 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2944 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2945 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2946 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2947
2948 udelay(50);
2949
2950 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2951 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2952 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2953 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2954 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2955 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2956
2957 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2958 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2959 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2960 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2961
2962 /*
2963 * Initialize LED control
2964 */
38c8a566
RJH		 2965 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
2966 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 2967 word & 0xff, (word >> 8) & 0xff);
2968
38c8a566
RJH		 2969 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
2970 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 2971 word & 0xff, (word >> 8) & 0xff);
2972
38c8a566
RJH		 2973 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
2974 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 2975 word & 0xff, (word >> 8) & 0xff);
2976
2977 return 0;
2978}
2979EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2980
2981void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2982{
2983 u32 reg;
2984
2985 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2986 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
b9a07ae9 2987 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
b9a07ae9
ID		 2988 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2989
2990 /* Wait for DMA, ignore error */
2991 rt2800_wait_wpdma_ready(rt2x00dev);
2992
2993 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2994 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2995 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2996 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 2997}
2998EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2999
30e84034
BZ		 3000int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3001{
3002 u32 reg;
3003
3004 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3005
3006 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3007}
3008EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3009
3010static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3011{
3012 u32 reg;
3013
31a4cf1f
GW		 3014 mutex_lock(&rt2x00dev->csr_mutex);
3015
3016 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 3017 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3018 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3019 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 3020 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 3021
3022 /* Wait until the EEPROM has been loaded */
3023 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3024
3025 /* Apparently the data is read from end to start */
31a4cf1f
GW		 3026 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3027 (u32 *)&rt2x00dev->eeprom[i]);
3028 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3029 (u32 *)&rt2x00dev->eeprom[i + 2]);
3030 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3031 (u32 *)&rt2x00dev->eeprom[i + 4]);
3032 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3033 (u32 *)&rt2x00dev->eeprom[i + 6]);
3034
3035 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 3036}
3037
3038void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3039{
3040 unsigned int i;
3041
3042 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3043 rt2800_efuse_read(rt2x00dev, i);
3044}
3045EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3046
38bd7b8a
BZ		 3047int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3048{
3049 u16 word;
3050 u8 *mac;
3051 u8 default_lna_gain;
3052
3053 /*
3054 * Start validation of the data that has been read.
3055 */
3056 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3057 if (!is_valid_ether_addr(mac)) {
3058 random_ether_addr(mac);
3059 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3060 }
3061
38c8a566 3062 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 3063 if (word == 0xffff) {
38c8a566
RJH		 3064 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3065 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3066 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3067 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 3068 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 3069 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 3070 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 3071 /*
3072 * There is a max of 2 RX streams for RT28x0 series
3073 */
38c8a566
RJH		 3074 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3075 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3076 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 3077 }
3078
38c8a566 3079 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 3080 if (word == 0xffff) {
38c8a566
RJH		 3081 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3082 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3083 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3084 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3085 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3086 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3087 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3088 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3089 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3090 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3091 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3092 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3093 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3094 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3095 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3096 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 3097 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3098 }
3099
3100 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3101 if ((word & 0x00ff) == 0x00ff) {
3102 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 3103 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3104 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3105 }
3106 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 3107 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3108 LED_MODE_TXRX_ACTIVITY);
3109 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3110 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 3111 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3112 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3113 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 3114 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 3115 }
3116
3117 /*
3118 * During the LNA validation we are going to use
3119 * lna0 as correct value. Note that EEPROM_LNA
3120 * is never validated.
3121 */
3122 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3123 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3124
3125 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3126 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3127 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3128 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3129 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3130 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3131
3132 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3133 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3134 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3135 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3136 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3137 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3138 default_lna_gain);
3139 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3140
3141 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3142 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3143 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3144 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3145 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3146 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3147
3148 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3149 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3150 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3151 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3152 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3153 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3154 default_lna_gain);
3155 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3156
3157 return 0;
3158}
3159EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3160
3161int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3162{
3163 u32 reg;
3164 u16 value;
3165 u16 eeprom;
3166
3167 /*
3168 * Read EEPROM word for configuration.
3169 */
38c8a566 3170 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3171
3172 /*
3173 * Identify RF chipset.
3174 */
38c8a566 3175 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a
BZ		 3176 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3177
49e721ec
GW		 3178 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3179 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3180
3181 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 3182 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 3183 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 3184 !rt2x00_rt(rt2x00dev, RT3070) &&
3185 !rt2x00_rt(rt2x00dev, RT3071) &&
3186 !rt2x00_rt(rt2x00dev, RT3090) &&
3187 !rt2x00_rt(rt2x00dev, RT3390) &&
3188 !rt2x00_rt(rt2x00dev, RT3572)) {
3189 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3190 return -ENODEV;
f273fe55 3191 }
714fa663 3192
5122d898
GW		 3193 if (!rt2x00_rf(rt2x00dev, RF2820) &&
3194 !rt2x00_rf(rt2x00dev, RF2850) &&
3195 !rt2x00_rf(rt2x00dev, RF2720) &&
3196 !rt2x00_rf(rt2x00dev, RF2750) &&
3197 !rt2x00_rf(rt2x00dev, RF3020) &&
3198 !rt2x00_rf(rt2x00dev, RF2020) &&
3199 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265 3200 !rt2x00_rf(rt2x00dev, RF3022) &&
f93bc9b3
GW		 3201 !rt2x00_rf(rt2x00dev, RF3052) &&
3202 !rt2x00_rf(rt2x00dev, RF3320)) {
38bd7b8a
BZ		 3203 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3204 return -ENODEV;
3205 }
3206
3207 /*
3208 * Identify default antenna configuration.
3209 */
d96aa640 3210 rt2x00dev->default_ant.tx_chain_num =
38c8a566 3211 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 3212 rt2x00dev->default_ant.rx_chain_num =
38c8a566 3213 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 3214
d96aa640
RJH		 3215 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3216
3217 if (rt2x00_rt(rt2x00dev, RT3070) ||
3218 rt2x00_rt(rt2x00dev, RT3090) ||
3219 rt2x00_rt(rt2x00dev, RT3390)) {
3220 value = rt2x00_get_field16(eeprom,
3221 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3222 switch (value) {
3223 case 0:
3224 case 1:
3225 case 2:
3226 rt2x00dev->default_ant.tx = ANTENNA_A;
3227 rt2x00dev->default_ant.rx = ANTENNA_A;
3228 break;
3229 case 3:
3230 rt2x00dev->default_ant.tx = ANTENNA_A;
3231 rt2x00dev->default_ant.rx = ANTENNA_B;
3232 break;
3233 }
3234 } else {
3235 rt2x00dev->default_ant.tx = ANTENNA_A;
3236 rt2x00dev->default_ant.rx = ANTENNA_A;
3237 }
3238
38bd7b8a
BZ		 3239 /*
3240 * Read frequency offset and RF programming sequence.
3241 */
3242 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3243 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3244
3245 /*
3246 * Read external LNA informations.
3247 */
38c8a566 3248 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
38bd7b8a 3249
38c8a566 3250 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
38bd7b8a 3251 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
38c8a566 3252 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
38bd7b8a
BZ		 3253 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3254
3255 /*
3256 * Detect if this device has an hardware controlled radio.
3257 */
38c8a566 3258 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
38bd7b8a
BZ		 3259 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3260
3261 /*
3262 * Store led settings, for correct led behaviour.
3263 */
3264#ifdef CONFIG_RT2X00_LIB_LEDS
3265 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3266 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3267 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3268
3269 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3270#endif /* CONFIG_RT2X00_LIB_LEDS */
3271
e90c54b2
RJH		 3272 /*
3273 * Check if support EIRP tx power limit feature.
3274 */
3275 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3276
3277 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3278 EIRP_MAX_TX_POWER_LIMIT)
3279 __set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
3280
38bd7b8a
BZ		 3281 return 0;
3282}
3283EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3284
4da2933f 3285/*
55f9321a 3286 * RF value list for rt28xx
4da2933f
BZ		 3287 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3288 */
3289static const struct rf_channel rf_vals[] = {
3290 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3291 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3292 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3293 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3294 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3295 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3296 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3297 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3298 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3299 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3300 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3301 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3302 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3303 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3304
3305 /* 802.11 UNI / HyperLan 2 */
3306 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3307 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3308 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3309 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3310 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3311 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3312 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3313 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3314 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3315 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3316 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3317 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3318
3319 /* 802.11 HyperLan 2 */
3320 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3321 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3322 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3323 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3324 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3325 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3326 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3327 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3328 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3329 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3330 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3331 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3332 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3333 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3334 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3335 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3336
3337 /* 802.11 UNII */
3338 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3339 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3340 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3341 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3342 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3343 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3344 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3345 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3346 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3347 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3348 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3349
3350 /* 802.11 Japan */
3351 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3352 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3353 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3354 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3355 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3356 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3357 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3358};
3359
3360/*
55f9321a
ID		 3361 * RF value list for rt3xxx
3362 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 3363 */
55f9321a 3364static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 3365 {1, 241, 2, 2 },
3366 {2, 241, 2, 7 },
3367 {3, 242, 2, 2 },
3368 {4, 242, 2, 7 },
3369 {5, 243, 2, 2 },
3370 {6, 243, 2, 7 },
3371 {7, 244, 2, 2 },
3372 {8, 244, 2, 7 },
3373 {9, 245, 2, 2 },
3374 {10, 245, 2, 7 },
3375 {11, 246, 2, 2 },
3376 {12, 246, 2, 7 },
3377 {13, 247, 2, 2 },
3378 {14, 248, 2, 4 },
55f9321a
ID		 3379
3380 /* 802.11 UNI / HyperLan 2 */
3381 {36, 0x56, 0, 4},
3382 {38, 0x56, 0, 6},
3383 {40, 0x56, 0, 8},
3384 {44, 0x57, 0, 0},
3385 {46, 0x57, 0, 2},
3386 {48, 0x57, 0, 4},
3387 {52, 0x57, 0, 8},
3388 {54, 0x57, 0, 10},
3389 {56, 0x58, 0, 0},
3390 {60, 0x58, 0, 4},
3391 {62, 0x58, 0, 6},
3392 {64, 0x58, 0, 8},
3393
3394 /* 802.11 HyperLan 2 */
3395 {100, 0x5b, 0, 8},
3396 {102, 0x5b, 0, 10},
3397 {104, 0x5c, 0, 0},
3398 {108, 0x5c, 0, 4},
3399 {110, 0x5c, 0, 6},
3400 {112, 0x5c, 0, 8},
3401 {116, 0x5d, 0, 0},
3402 {118, 0x5d, 0, 2},
3403 {120, 0x5d, 0, 4},
3404 {124, 0x5d, 0, 8},
3405 {126, 0x5d, 0, 10},
3406 {128, 0x5e, 0, 0},
3407 {132, 0x5e, 0, 4},
3408 {134, 0x5e, 0, 6},
3409 {136, 0x5e, 0, 8},
3410 {140, 0x5f, 0, 0},
3411
3412 /* 802.11 UNII */
3413 {149, 0x5f, 0, 9},
3414 {151, 0x5f, 0, 11},
3415 {153, 0x60, 0, 1},
3416 {157, 0x60, 0, 5},
3417 {159, 0x60, 0, 7},
3418 {161, 0x60, 0, 9},
3419 {165, 0x61, 0, 1},
3420 {167, 0x61, 0, 3},
3421 {169, 0x61, 0, 5},
3422 {171, 0x61, 0, 7},
3423 {173, 0x61, 0, 9},
4da2933f
BZ		 3424};
3425
3426int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3427{
4da2933f
BZ		 3428 struct hw_mode_spec *spec = &rt2x00dev->spec;
3429 struct channel_info *info;
8d1331b3
ID		 3430 char *default_power1;
3431 char *default_power2;
4da2933f
BZ		 3432 unsigned int i;
3433 u16 eeprom;
3434
93b6bd26
GW		 3435 /*
3436 * Disable powersaving as default on PCI devices.
3437 */
cea90e55 3438 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3439 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3440
4da2933f
BZ		 3441 /*
3442 * Initialize all hw fields.
3443 */
3444 rt2x00dev->hw->flags =
4da2933f
BZ		 3445 IEEE80211_HW_SIGNAL_DBM |
3446 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3447 IEEE80211_HW_PS_NULLFUNC_STACK |
3448 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 3449 /*
3450 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3451 * unless we are capable of sending the buffered frames out after the
3452 * DTIM transmission using rt2x00lib_beacondone. This will send out
3453 * multicast and broadcast traffic immediately instead of buffering it
3454 * infinitly and thus dropping it after some time.
3455 */
3456 if (!rt2x00_is_usb(rt2x00dev))
3457 rt2x00dev->hw->flags |=
3458 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 3459
4da2933f
BZ		 3460 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3461 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3462 rt2x00_eeprom_addr(rt2x00dev,
3463 EEPROM_MAC_ADDR_0));
3464
3f2bee24
HS		 3465 /*
3466 * As rt2800 has a global fallback table we cannot specify
3467 * more then one tx rate per frame but since the hw will
3468 * try several rates (based on the fallback table) we should
ba3b9e5e 3469 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 3470 * we are going to try. Otherwise mac80211 will truncate our
3471 * reported tx rates and the rc algortihm will end up with
3472 * incorrect data.
3473 */
ba3b9e5e
HS		 3474 rt2x00dev->hw->max_rates = 1;
3475 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 3476 rt2x00dev->hw->max_rate_tries = 1;
3477
38c8a566 3478 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 3479
3480 /*
3481 * Initialize hw_mode information.
3482 */
3483 spec->supported_bands = SUPPORT_BAND_2GHZ;
3484 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3485
5122d898 3486 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3487 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3488 spec->num_channels = 14;
3489 spec->channels = rf_vals;
55f9321a
ID		 3490 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3491 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3492 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3493 spec->num_channels = ARRAY_SIZE(rf_vals);
3494 spec->channels = rf_vals;
5122d898
GW		 3495 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3496 rt2x00_rf(rt2x00dev, RF2020) ||
3497 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3
GW		 3498 rt2x00_rf(rt2x00dev, RF3022) ||
3499 rt2x00_rf(rt2x00dev, RF3320)) {
55f9321a
ID		 3500 spec->num_channels = 14;
3501 spec->channels = rf_vals_3x;
3502 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3503 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3504 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3505 spec->channels = rf_vals_3x;
4da2933f
BZ		 3506 }
3507
3508 /*
3509 * Initialize HT information.
3510 */
5122d898 3511 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3512 spec->ht.ht_supported = true;
3513 else
3514 spec->ht.ht_supported = false;
3515
4da2933f 3516 spec->ht.cap =
06443e46 3517 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3518 IEEE80211_HT_CAP_GRN_FLD |
3519 IEEE80211_HT_CAP_SGI_20 |
aa674631 3520 IEEE80211_HT_CAP_SGI_40;
22cabaa6 3521
38c8a566 3522 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 3523 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3524
aa674631 3525 spec->ht.cap |=
38c8a566 3526 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 3527 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3528
4da2933f
BZ		 3529 spec->ht.ampdu_factor = 3;
3530 spec->ht.ampdu_density = 4;
3531 spec->ht.mcs.tx_params =
3532 IEEE80211_HT_MCS_TX_DEFINED |
3533 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 3534 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 3535 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3536
38c8a566 3537 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 3538 case 3:
3539 spec->ht.mcs.rx_mask[2] = 0xff;
3540 case 2:
3541 spec->ht.mcs.rx_mask[1] = 0xff;
3542 case 1:
3543 spec->ht.mcs.rx_mask[0] = 0xff;
3544 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3545 break;
3546 }
3547
3548 /*
3549 * Create channel information array
3550 */
baeb2ffa 3551 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 3552 if (!info)
3553 return -ENOMEM;
3554
3555 spec->channels_info = info;
3556
8d1331b3
ID		 3557 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3558 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3559
3560 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 3561 info[i].default_power1 = default_power1[i];
3562 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 3563 }
3564
3565 if (spec->num_channels > 14) {
8d1331b3
ID		 3566 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3567 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3568
3569 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 3570 info[i].default_power1 = default_power1[i];
3571 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 3572 }
3573 }
3574
3575 return 0;
3576}
3577EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3578
2ce33995
BZ		 3579/*
3580 * IEEE80211 stack callback functions.
3581 */
e783619e
HS		 3582void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3583 u16 *iv16)
2ce33995
BZ		 3584{
3585 struct rt2x00_dev *rt2x00dev = hw->priv;
3586 struct mac_iveiv_entry iveiv_entry;
3587 u32 offset;
3588
3589 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3590 rt2800_register_multiread(rt2x00dev, offset,
3591 &iveiv_entry, sizeof(iveiv_entry));
3592
855da5e0
JL		 3593 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3594 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3595}
e783619e 3596EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3597
e783619e 3598int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3599{
3600 struct rt2x00_dev *rt2x00dev = hw->priv;
3601 u32 reg;
3602 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3603
3604 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3605 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3606 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3607
3608 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3609 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3610 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3611
3612 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3613 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3614 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3615
3616 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3617 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3618 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3619
3620 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3621 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3622 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3623
3624 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3625 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3626 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3627
3628 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3629 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3630 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3631
3632 return 0;
3633}
e783619e 3634EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3635
e783619e
HS		 3636int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3637 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3638{
3639 struct rt2x00_dev *rt2x00dev = hw->priv;
3640 struct data_queue *queue;
3641 struct rt2x00_field32 field;
3642 int retval;
3643 u32 reg;
3644 u32 offset;
3645
3646 /*
3647 * First pass the configuration through rt2x00lib, that will
3648 * update the queue settings and validate the input. After that
3649 * we are free to update the registers based on the value
3650 * in the queue parameter.
3651 */
3652 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3653 if (retval)
3654 return retval;
3655
3656 /*
3657 * We only need to perform additional register initialization
3658 * for WMM queues/
3659 */
3660 if (queue_idx >= 4)
3661 return 0;
3662
3663 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3664
3665 /* Update WMM TXOP register */
3666 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3667 field.bit_offset = (queue_idx & 1) * 16;
3668 field.bit_mask = 0xffff << field.bit_offset;
3669
3670 rt2800_register_read(rt2x00dev, offset, &reg);
3671 rt2x00_set_field32(&reg, field, queue->txop);
3672 rt2800_register_write(rt2x00dev, offset, reg);
3673
3674 /* Update WMM registers */
3675 field.bit_offset = queue_idx * 4;
3676 field.bit_mask = 0xf << field.bit_offset;
3677
3678 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3679 rt2x00_set_field32(&reg, field, queue->aifs);
3680 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3681
3682 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3683 rt2x00_set_field32(&reg, field, queue->cw_min);
3684 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3685
3686 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3687 rt2x00_set_field32(&reg, field, queue->cw_max);
3688 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3689
3690 /* Update EDCA registers */
3691 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3692
3693 rt2800_register_read(rt2x00dev, offset, &reg);
3694 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3695 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3696 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3697 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3698 rt2800_register_write(rt2x00dev, offset, reg);
3699
3700 return 0;
3701}
e783619e 3702EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3703
e783619e 3704u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3705{
3706 struct rt2x00_dev *rt2x00dev = hw->priv;
3707 u64 tsf;
3708 u32 reg;
3709
3710 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3711 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3712 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3713 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3714
3715 return tsf;
3716}
e783619e 3717EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3718
e783619e
HS		 3719int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3720 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 3721 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3722 u8 buf_size)
1df90809 3723{
1df90809
HS		 3724 int ret = 0;
3725
3726 switch (action) {
3727 case IEEE80211_AMPDU_RX_START:
3728 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 3729 /*
3730 * The hw itself takes care of setting up BlockAck mechanisms.
3731 * So, we only have to allow mac80211 to nagotiate a BlockAck
3732 * agreement. Once that is done, the hw will BlockAck incoming
3733 * AMPDUs without further setup.
3734 */
1df90809
HS		 3735 break;
3736 case IEEE80211_AMPDU_TX_START:
3737 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3738 break;
3739 case IEEE80211_AMPDU_TX_STOP:
3740 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3741 break;
3742 case IEEE80211_AMPDU_TX_OPERATIONAL:
3743 break;
3744 default:
4e9e58c6 3745 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3746 }
3747
3748 return ret;
3749}
e783619e 3750EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 3751
977206d7
HS		 3752int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
3753 struct survey_info *survey)
3754{
3755 struct rt2x00_dev *rt2x00dev = hw->priv;
3756 struct ieee80211_conf *conf = &hw->conf;
3757 u32 idle, busy, busy_ext;
3758
3759 if (idx != 0)
3760 return -ENOENT;
3761
3762 survey->channel = conf->channel;
3763
3764 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
3765 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
3766 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
3767
3768 if (idle || busy) {
3769 survey->filled = SURVEY_INFO_CHANNEL_TIME |
3770 SURVEY_INFO_CHANNEL_TIME_BUSY |
3771 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
3772
3773 survey->channel_time = (idle + busy) / 1000;
3774 survey->channel_time_busy = busy / 1000;
3775 survey->channel_time_ext_busy = busy_ext / 1000;
3776 }
3777
3778 return 0;
3779
3780}
3781EXPORT_SYMBOL_GPL(rt2800_get_survey);
3782
a5ea2f02
ID		 3783MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3784MODULE_VERSION(DRV_VERSION);
3785MODULE_DESCRIPTION("Ralink RT2800 library");
3786MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)