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95ea3627 | 1 | /* |
811aa9ca | 2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2500usb | |
23 | Abstract: Data structures and registers for the rt2500usb module. | |
24 | Supported chipsets: RT2570. | |
25 | */ | |
26 | ||
27 | #ifndef RT2500USB_H | |
28 | #define RT2500USB_H | |
29 | ||
30 | /* | |
31 | * RF chip defines. | |
32 | */ | |
33 | #define RF2522 0x0000 | |
34 | #define RF2523 0x0001 | |
35 | #define RF2524 0x0002 | |
36 | #define RF2525 0x0003 | |
37 | #define RF2525E 0x0005 | |
38 | #define RF5222 0x0010 | |
39 | ||
40 | /* | |
41 | * RT2570 version | |
42 | */ | |
43 | #define RT2570_VERSION_B 2 | |
44 | #define RT2570_VERSION_C 3 | |
45 | #define RT2570_VERSION_D 4 | |
46 | ||
47 | /* | |
48 | * Signal information. | |
49 | * Defaul offset is required for RSSI <-> dBm conversion. | |
50 | */ | |
95ea3627 ID |
51 | #define DEFAULT_RSSI_OFFSET 120 |
52 | ||
53 | /* | |
54 | * Register layout information. | |
55 | */ | |
56 | #define CSR_REG_BASE 0x0400 | |
57 | #define CSR_REG_SIZE 0x0100 | |
58 | #define EEPROM_BASE 0x0000 | |
59 | #define EEPROM_SIZE 0x006a | |
743b97ca | 60 | #define BBP_BASE 0x0000 |
95ea3627 | 61 | #define BBP_SIZE 0x0060 |
743b97ca | 62 | #define RF_BASE 0x0000 |
95ea3627 ID |
63 | #define RF_SIZE 0x0014 |
64 | ||
61448f88 GW |
65 | /* |
66 | * Number of TX queues. | |
67 | */ | |
68 | #define NUM_TX_QUEUES 2 | |
69 | ||
95ea3627 ID |
70 | /* |
71 | * Control/Status Registers(CSR). | |
72 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
73 | */ | |
74 | ||
75 | /* | |
76 | * MAC_CSR0: ASIC revision number. | |
77 | */ | |
78 | #define MAC_CSR0 0x0400 | |
79 | ||
80 | /* | |
81 | * MAC_CSR1: System control. | |
82 | * SOFT_RESET: Software reset, 1: reset, 0: normal. | |
83 | * BBP_RESET: Hardware reset, 1: reset, 0, release. | |
84 | * HOST_READY: Host ready after initialization. | |
85 | */ | |
86 | #define MAC_CSR1 0x0402 | |
87 | #define MAC_CSR1_SOFT_RESET FIELD16(0x00000001) | |
88 | #define MAC_CSR1_BBP_RESET FIELD16(0x00000002) | |
89 | #define MAC_CSR1_HOST_READY FIELD16(0x00000004) | |
90 | ||
91 | /* | |
92 | * MAC_CSR2: STA MAC register 0. | |
93 | */ | |
94 | #define MAC_CSR2 0x0404 | |
95 | #define MAC_CSR2_BYTE0 FIELD16(0x00ff) | |
96 | #define MAC_CSR2_BYTE1 FIELD16(0xff00) | |
97 | ||
98 | /* | |
99 | * MAC_CSR3: STA MAC register 1. | |
100 | */ | |
101 | #define MAC_CSR3 0x0406 | |
102 | #define MAC_CSR3_BYTE2 FIELD16(0x00ff) | |
103 | #define MAC_CSR3_BYTE3 FIELD16(0xff00) | |
104 | ||
105 | /* | |
106 | * MAC_CSR4: STA MAC register 2. | |
107 | */ | |
108 | #define MAC_CSR4 0X0408 | |
109 | #define MAC_CSR4_BYTE4 FIELD16(0x00ff) | |
110 | #define MAC_CSR4_BYTE5 FIELD16(0xff00) | |
111 | ||
112 | /* | |
113 | * MAC_CSR5: BSSID register 0. | |
114 | */ | |
115 | #define MAC_CSR5 0x040a | |
116 | #define MAC_CSR5_BYTE0 FIELD16(0x00ff) | |
117 | #define MAC_CSR5_BYTE1 FIELD16(0xff00) | |
118 | ||
119 | /* | |
120 | * MAC_CSR6: BSSID register 1. | |
121 | */ | |
122 | #define MAC_CSR6 0x040c | |
123 | #define MAC_CSR6_BYTE2 FIELD16(0x00ff) | |
124 | #define MAC_CSR6_BYTE3 FIELD16(0xff00) | |
125 | ||
126 | /* | |
127 | * MAC_CSR7: BSSID register 2. | |
128 | */ | |
129 | #define MAC_CSR7 0x040e | |
130 | #define MAC_CSR7_BYTE4 FIELD16(0x00ff) | |
131 | #define MAC_CSR7_BYTE5 FIELD16(0xff00) | |
132 | ||
133 | /* | |
134 | * MAC_CSR8: Max frame length. | |
135 | */ | |
136 | #define MAC_CSR8 0x0410 | |
137 | #define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff) | |
138 | ||
139 | /* | |
140 | * Misc MAC_CSR registers. | |
141 | * MAC_CSR9: Timer control. | |
142 | * MAC_CSR10: Slot time. | |
f5507ce9 | 143 | * MAC_CSR11: SIFS. |
95ea3627 ID |
144 | * MAC_CSR12: EIFS. |
145 | * MAC_CSR13: Power mode0. | |
146 | * MAC_CSR14: Power mode1. | |
147 | * MAC_CSR15: Power saving transition0 | |
148 | * MAC_CSR16: Power saving transition1 | |
149 | */ | |
150 | #define MAC_CSR9 0x0412 | |
151 | #define MAC_CSR10 0x0414 | |
152 | #define MAC_CSR11 0x0416 | |
153 | #define MAC_CSR12 0x0418 | |
154 | #define MAC_CSR13 0x041a | |
155 | #define MAC_CSR14 0x041c | |
156 | #define MAC_CSR15 0x041e | |
157 | #define MAC_CSR16 0x0420 | |
158 | ||
159 | /* | |
160 | * MAC_CSR17: Manual power control / status register. | |
161 | * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. | |
162 | * SET_STATE: Set state. Write 1 to trigger, self cleared. | |
163 | * BBP_DESIRE_STATE: BBP desired state. | |
164 | * RF_DESIRE_STATE: RF desired state. | |
165 | * BBP_CURRENT_STATE: BBP current state. | |
166 | * RF_CURRENT_STATE: RF current state. | |
167 | * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. | |
168 | */ | |
169 | #define MAC_CSR17 0x0422 | |
170 | #define MAC_CSR17_SET_STATE FIELD16(0x0001) | |
171 | #define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006) | |
172 | #define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018) | |
173 | #define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060) | |
174 | #define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180) | |
175 | #define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200) | |
176 | ||
177 | /* | |
178 | * MAC_CSR18: Wakeup timer register. | |
179 | * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU. | |
180 | * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup. | |
181 | * AUTO_WAKE: Enable auto wakeup / sleep mechanism. | |
182 | */ | |
183 | #define MAC_CSR18 0x0424 | |
184 | #define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff) | |
185 | #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00) | |
186 | #define MAC_CSR18_AUTO_WAKE FIELD16(0x8000) | |
187 | ||
188 | /* | |
189 | * MAC_CSR19: GPIO control register. | |
190 | */ | |
191 | #define MAC_CSR19 0x0426 | |
192 | ||
193 | /* | |
194 | * MAC_CSR20: LED control register. | |
195 | * ACTIVITY: 0: idle, 1: active. | |
196 | * LINK: 0: linkoff, 1: linkup. | |
197 | * ACTIVITY_POLARITY: 0: active low, 1: active high. | |
198 | */ | |
199 | #define MAC_CSR20 0x0428 | |
200 | #define MAC_CSR20_ACTIVITY FIELD16(0x0001) | |
201 | #define MAC_CSR20_LINK FIELD16(0x0002) | |
202 | #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004) | |
203 | ||
204 | /* | |
205 | * MAC_CSR21: LED control register. | |
206 | * ON_PERIOD: On period, default 70ms. | |
207 | * OFF_PERIOD: Off period, default 30ms. | |
208 | */ | |
209 | #define MAC_CSR21 0x042a | |
210 | #define MAC_CSR21_ON_PERIOD FIELD16(0x00ff) | |
211 | #define MAC_CSR21_OFF_PERIOD FIELD16(0xff00) | |
212 | ||
213 | /* | |
84263b0c | 214 | * MAC_CSR22: Collision window control register. |
95ea3627 ID |
215 | */ |
216 | #define MAC_CSR22 0x042c | |
217 | ||
218 | /* | |
219 | * Transmit related CSRs. | |
220 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
221 | */ | |
222 | ||
223 | /* | |
224 | * TXRX_CSR0: Security control register. | |
225 | */ | |
226 | #define TXRX_CSR0 0x0440 | |
227 | #define TXRX_CSR0_ALGORITHM FIELD16(0x0007) | |
228 | #define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8) | |
229 | #define TXRX_CSR0_KEY_ID FIELD16(0x1e00) | |
230 | ||
231 | /* | |
232 | * TXRX_CSR1: TX configuration. | |
233 | * ACK_TIMEOUT: ACK Timeout in unit of 1-us. | |
234 | * TSF_OFFSET: TSF offset in MAC header. | |
235 | * AUTO_SEQUENCE: Let ASIC control frame sequence number. | |
236 | */ | |
237 | #define TXRX_CSR1 0x0442 | |
238 | #define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff) | |
239 | #define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00) | |
240 | #define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000) | |
241 | ||
242 | /* | |
243 | * TXRX_CSR2: RX control. | |
244 | * DISABLE_RX: Disable rx engine. | |
245 | * DROP_CRC: Drop crc error. | |
246 | * DROP_PHYSICAL: Drop physical error. | |
247 | * DROP_CONTROL: Drop control frame. | |
248 | * DROP_NOT_TO_ME: Drop not to me unicast frame. | |
249 | * DROP_TODS: Drop frame tods bit is true. | |
250 | * DROP_VERSION_ERROR: Drop version error frame. | |
251 | * DROP_MCAST: Drop multicast frames. | |
252 | * DROP_BCAST: Drop broadcast frames. | |
253 | */ | |
254 | #define TXRX_CSR2 0x0444 | |
255 | #define TXRX_CSR2_DISABLE_RX FIELD16(0x0001) | |
256 | #define TXRX_CSR2_DROP_CRC FIELD16(0x0002) | |
257 | #define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004) | |
258 | #define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008) | |
259 | #define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010) | |
260 | #define TXRX_CSR2_DROP_TODS FIELD16(0x0020) | |
261 | #define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040) | |
262 | #define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200) | |
263 | #define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400) | |
264 | ||
265 | /* | |
266 | * RX BBP ID registers | |
267 | * TXRX_CSR3: CCK RX BBP ID. | |
268 | * TXRX_CSR4: OFDM RX BBP ID. | |
269 | */ | |
270 | #define TXRX_CSR3 0x0446 | |
271 | #define TXRX_CSR4 0x0448 | |
272 | ||
273 | /* | |
274 | * TXRX_CSR5: CCK TX BBP ID0. | |
275 | */ | |
276 | #define TXRX_CSR5 0x044a | |
277 | #define TXRX_CSR5_BBP_ID0 FIELD16(0x007f) | |
278 | #define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080) | |
279 | #define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00) | |
280 | #define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000) | |
281 | ||
282 | /* | |
283 | * TXRX_CSR6: CCK TX BBP ID1. | |
284 | */ | |
285 | #define TXRX_CSR6 0x044c | |
286 | #define TXRX_CSR6_BBP_ID0 FIELD16(0x007f) | |
287 | #define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080) | |
288 | #define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00) | |
289 | #define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000) | |
290 | ||
291 | /* | |
292 | * TXRX_CSR7: OFDM TX BBP ID0. | |
293 | */ | |
294 | #define TXRX_CSR7 0x044e | |
295 | #define TXRX_CSR7_BBP_ID0 FIELD16(0x007f) | |
296 | #define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080) | |
297 | #define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00) | |
298 | #define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000) | |
299 | ||
300 | /* | |
84263b0c | 301 | * TXRX_CSR8: OFDM TX BBP ID1. |
95ea3627 ID |
302 | */ |
303 | #define TXRX_CSR8 0x0450 | |
304 | #define TXRX_CSR8_BBP_ID0 FIELD16(0x007f) | |
305 | #define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080) | |
306 | #define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00) | |
307 | #define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000) | |
308 | ||
309 | /* | |
310 | * TXRX_CSR9: TX ACK time-out. | |
311 | */ | |
312 | #define TXRX_CSR9 0x0452 | |
313 | ||
314 | /* | |
315 | * TXRX_CSR10: Auto responder control. | |
316 | */ | |
317 | #define TXRX_CSR10 0x0454 | |
318 | #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004) | |
319 | ||
320 | /* | |
321 | * TXRX_CSR11: Auto responder basic rate. | |
322 | */ | |
323 | #define TXRX_CSR11 0x0456 | |
324 | ||
325 | /* | |
326 | * ACK/CTS time registers. | |
327 | */ | |
328 | #define TXRX_CSR12 0x0458 | |
329 | #define TXRX_CSR13 0x045a | |
330 | #define TXRX_CSR14 0x045c | |
331 | #define TXRX_CSR15 0x045e | |
332 | #define TXRX_CSR16 0x0460 | |
333 | #define TXRX_CSR17 0x0462 | |
334 | ||
335 | /* | |
336 | * TXRX_CSR18: Synchronization control register. | |
337 | */ | |
338 | #define TXRX_CSR18 0x0464 | |
339 | #define TXRX_CSR18_OFFSET FIELD16(0x000f) | |
340 | #define TXRX_CSR18_INTERVAL FIELD16(0xfff0) | |
341 | ||
342 | /* | |
343 | * TXRX_CSR19: Synchronization control register. | |
344 | * TSF_COUNT: Enable TSF auto counting. | |
345 | * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. | |
346 | * TBCN: Enable Tbcn with reload value. | |
347 | * BEACON_GEN: Enable beacon generator. | |
348 | */ | |
349 | #define TXRX_CSR19 0x0466 | |
350 | #define TXRX_CSR19_TSF_COUNT FIELD16(0x0001) | |
351 | #define TXRX_CSR19_TSF_SYNC FIELD16(0x0006) | |
352 | #define TXRX_CSR19_TBCN FIELD16(0x0008) | |
353 | #define TXRX_CSR19_BEACON_GEN FIELD16(0x0010) | |
354 | ||
355 | /* | |
356 | * TXRX_CSR20: Tx BEACON offset time control register. | |
357 | * OFFSET: In units of usec. | |
358 | * BCN_EXPECT_WINDOW: Default: 2^CWmin | |
359 | */ | |
360 | #define TXRX_CSR20 0x0468 | |
361 | #define TXRX_CSR20_OFFSET FIELD16(0x1fff) | |
362 | #define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000) | |
363 | ||
364 | /* | |
365 | * TXRX_CSR21 | |
366 | */ | |
367 | #define TXRX_CSR21 0x046a | |
368 | ||
369 | /* | |
370 | * Encryption related CSRs. | |
371 | * | |
372 | */ | |
373 | ||
374 | /* | |
84263b0c ID |
375 | * SEC_CSR0: Shared key 0, word 0 |
376 | * SEC_CSR1: Shared key 0, word 1 | |
377 | * SEC_CSR2: Shared key 0, word 2 | |
378 | * SEC_CSR3: Shared key 0, word 3 | |
379 | * SEC_CSR4: Shared key 0, word 4 | |
380 | * SEC_CSR5: Shared key 0, word 5 | |
381 | * SEC_CSR6: Shared key 0, word 6 | |
382 | * SEC_CSR7: Shared key 0, word 7 | |
95ea3627 ID |
383 | */ |
384 | #define SEC_CSR0 0x0480 | |
385 | #define SEC_CSR1 0x0482 | |
386 | #define SEC_CSR2 0x0484 | |
387 | #define SEC_CSR3 0x0486 | |
388 | #define SEC_CSR4 0x0488 | |
389 | #define SEC_CSR5 0x048a | |
390 | #define SEC_CSR6 0x048c | |
391 | #define SEC_CSR7 0x048e | |
392 | ||
393 | /* | |
84263b0c ID |
394 | * SEC_CSR8: Shared key 1, word 0 |
395 | * SEC_CSR9: Shared key 1, word 1 | |
396 | * SEC_CSR10: Shared key 1, word 2 | |
397 | * SEC_CSR11: Shared key 1, word 3 | |
398 | * SEC_CSR12: Shared key 1, word 4 | |
399 | * SEC_CSR13: Shared key 1, word 5 | |
400 | * SEC_CSR14: Shared key 1, word 6 | |
401 | * SEC_CSR15: Shared key 1, word 7 | |
95ea3627 ID |
402 | */ |
403 | #define SEC_CSR8 0x0490 | |
404 | #define SEC_CSR9 0x0492 | |
405 | #define SEC_CSR10 0x0494 | |
406 | #define SEC_CSR11 0x0496 | |
407 | #define SEC_CSR12 0x0498 | |
408 | #define SEC_CSR13 0x049a | |
409 | #define SEC_CSR14 0x049c | |
410 | #define SEC_CSR15 0x049e | |
411 | ||
412 | /* | |
84263b0c ID |
413 | * SEC_CSR16: Shared key 2, word 0 |
414 | * SEC_CSR17: Shared key 2, word 1 | |
415 | * SEC_CSR18: Shared key 2, word 2 | |
416 | * SEC_CSR19: Shared key 2, word 3 | |
417 | * SEC_CSR20: Shared key 2, word 4 | |
418 | * SEC_CSR21: Shared key 2, word 5 | |
419 | * SEC_CSR22: Shared key 2, word 6 | |
420 | * SEC_CSR23: Shared key 2, word 7 | |
95ea3627 ID |
421 | */ |
422 | #define SEC_CSR16 0x04a0 | |
423 | #define SEC_CSR17 0x04a2 | |
424 | #define SEC_CSR18 0X04A4 | |
425 | #define SEC_CSR19 0x04a6 | |
426 | #define SEC_CSR20 0x04a8 | |
427 | #define SEC_CSR21 0x04aa | |
428 | #define SEC_CSR22 0x04ac | |
429 | #define SEC_CSR23 0x04ae | |
430 | ||
431 | /* | |
84263b0c ID |
432 | * SEC_CSR24: Shared key 3, word 0 |
433 | * SEC_CSR25: Shared key 3, word 1 | |
434 | * SEC_CSR26: Shared key 3, word 2 | |
435 | * SEC_CSR27: Shared key 3, word 3 | |
436 | * SEC_CSR28: Shared key 3, word 4 | |
437 | * SEC_CSR29: Shared key 3, word 5 | |
438 | * SEC_CSR30: Shared key 3, word 6 | |
439 | * SEC_CSR31: Shared key 3, word 7 | |
95ea3627 ID |
440 | */ |
441 | #define SEC_CSR24 0x04b0 | |
442 | #define SEC_CSR25 0x04b2 | |
443 | #define SEC_CSR26 0x04b4 | |
444 | #define SEC_CSR27 0x04b6 | |
445 | #define SEC_CSR28 0x04b8 | |
446 | #define SEC_CSR29 0x04ba | |
447 | #define SEC_CSR30 0x04bc | |
448 | #define SEC_CSR31 0x04be | |
449 | ||
dddfb478 ID |
450 | #define KEY_ENTRY(__idx) \ |
451 | ( SEC_CSR0 + ((__idx) * 16) ) | |
452 | ||
95ea3627 ID |
453 | /* |
454 | * PHY control registers. | |
455 | */ | |
456 | ||
457 | /* | |
458 | * PHY_CSR0: RF switching timing control. | |
459 | */ | |
460 | #define PHY_CSR0 0x04c0 | |
461 | ||
462 | /* | |
463 | * PHY_CSR1: TX PA configuration. | |
464 | */ | |
465 | #define PHY_CSR1 0x04c2 | |
466 | ||
467 | /* | |
468 | * MAC configuration registers. | |
ddc827f9 ID |
469 | */ |
470 | ||
471 | /* | |
95ea3627 | 472 | * PHY_CSR2: TX MAC configuration. |
ddc827f9 ID |
473 | * NOTE: Both register fields are complete dummy, |
474 | * documentation and legacy drivers are unclear un | |
475 | * what this register means or what fields exists. | |
95ea3627 ID |
476 | */ |
477 | #define PHY_CSR2 0x04c4 | |
ddc827f9 ID |
478 | #define PHY_CSR2_LNA FIELD16(0x0002) |
479 | #define PHY_CSR2_LNA_MODE FIELD16(0x3000) | |
480 | ||
481 | /* | |
482 | * PHY_CSR3: RX MAC configuration. | |
483 | */ | |
95ea3627 ID |
484 | #define PHY_CSR3 0x04c6 |
485 | ||
486 | /* | |
487 | * PHY_CSR4: Interface configuration. | |
488 | */ | |
489 | #define PHY_CSR4 0x04c8 | |
490 | #define PHY_CSR4_LOW_RF_LE FIELD16(0x0001) | |
491 | ||
492 | /* | |
493 | * BBP pre-TX registers. | |
494 | * PHY_CSR5: BBP pre-TX CCK. | |
495 | */ | |
496 | #define PHY_CSR5 0x04ca | |
497 | #define PHY_CSR5_CCK FIELD16(0x0003) | |
498 | #define PHY_CSR5_CCK_FLIP FIELD16(0x0004) | |
499 | ||
500 | /* | |
501 | * BBP pre-TX registers. | |
502 | * PHY_CSR6: BBP pre-TX OFDM. | |
503 | */ | |
504 | #define PHY_CSR6 0x04cc | |
505 | #define PHY_CSR6_OFDM FIELD16(0x0003) | |
506 | #define PHY_CSR6_OFDM_FLIP FIELD16(0x0004) | |
507 | ||
508 | /* | |
509 | * PHY_CSR7: BBP access register 0. | |
510 | * BBP_DATA: BBP data. | |
511 | * BBP_REG_ID: BBP register ID. | |
512 | * BBP_READ_CONTROL: 0: write, 1: read. | |
513 | */ | |
514 | #define PHY_CSR7 0x04ce | |
515 | #define PHY_CSR7_DATA FIELD16(0x00ff) | |
516 | #define PHY_CSR7_REG_ID FIELD16(0x7f00) | |
517 | #define PHY_CSR7_READ_CONTROL FIELD16(0x8000) | |
518 | ||
519 | /* | |
520 | * PHY_CSR8: BBP access register 1. | |
521 | * BBP_BUSY: ASIC is busy execute BBP programming. | |
522 | */ | |
523 | #define PHY_CSR8 0x04d0 | |
524 | #define PHY_CSR8_BUSY FIELD16(0x0001) | |
525 | ||
526 | /* | |
527 | * PHY_CSR9: RF access register. | |
528 | * RF_VALUE: Register value + id to program into rf/if. | |
529 | */ | |
530 | #define PHY_CSR9 0x04d2 | |
531 | #define PHY_CSR9_RF_VALUE FIELD16(0xffff) | |
532 | ||
533 | /* | |
534 | * PHY_CSR10: RF access register. | |
535 | * RF_VALUE: Register value + id to program into rf/if. | |
536 | * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). | |
537 | * RF_IF_SELECT: Chip to program: 0: rf, 1: if. | |
538 | * RF_PLL_LD: Rf pll_ld status. | |
539 | * RF_BUSY: 1: asic is busy execute rf programming. | |
540 | */ | |
541 | #define PHY_CSR10 0x04d4 | |
542 | #define PHY_CSR10_RF_VALUE FIELD16(0x00ff) | |
543 | #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00) | |
544 | #define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000) | |
545 | #define PHY_CSR10_RF_PLL_LD FIELD16(0x4000) | |
546 | #define PHY_CSR10_RF_BUSY FIELD16(0x8000) | |
547 | ||
548 | /* | |
549 | * STA_CSR0: FCS error count. | |
550 | * FCS_ERROR: FCS error count, cleared when read. | |
551 | */ | |
552 | #define STA_CSR0 0x04e0 | |
553 | #define STA_CSR0_FCS_ERROR FIELD16(0xffff) | |
554 | ||
555 | /* | |
556 | * STA_CSR1: PLCP error count. | |
557 | */ | |
558 | #define STA_CSR1 0x04e2 | |
559 | ||
560 | /* | |
561 | * STA_CSR2: LONG error count. | |
562 | */ | |
563 | #define STA_CSR2 0x04e4 | |
564 | ||
565 | /* | |
566 | * STA_CSR3: CCA false alarm. | |
567 | * FALSE_CCA_ERROR: False CCA error count, cleared when read. | |
568 | */ | |
569 | #define STA_CSR3 0x04e6 | |
570 | #define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff) | |
571 | ||
572 | /* | |
573 | * STA_CSR4: RX FIFO overflow. | |
574 | */ | |
575 | #define STA_CSR4 0x04e8 | |
576 | ||
577 | /* | |
578 | * STA_CSR5: Beacon sent counter. | |
579 | */ | |
580 | #define STA_CSR5 0x04ea | |
581 | ||
582 | /* | |
583 | * Statistics registers | |
584 | */ | |
585 | #define STA_CSR6 0x04ec | |
586 | #define STA_CSR7 0x04ee | |
587 | #define STA_CSR8 0x04f0 | |
588 | #define STA_CSR9 0x04f2 | |
589 | #define STA_CSR10 0x04f4 | |
590 | ||
591 | /* | |
592 | * BBP registers. | |
593 | * The wordsize of the BBP is 8 bits. | |
594 | */ | |
595 | ||
596 | /* | |
597 | * R2: TX antenna control | |
598 | */ | |
599 | #define BBP_R2_TX_ANTENNA FIELD8(0x03) | |
600 | #define BBP_R2_TX_IQ_FLIP FIELD8(0x04) | |
601 | ||
602 | /* | |
603 | * R14: RX antenna control | |
604 | */ | |
605 | #define BBP_R14_RX_ANTENNA FIELD8(0x03) | |
606 | #define BBP_R14_RX_IQ_FLIP FIELD8(0x04) | |
607 | ||
608 | /* | |
609 | * RF registers. | |
610 | */ | |
611 | ||
612 | /* | |
613 | * RF 1 | |
614 | */ | |
615 | #define RF1_TUNER FIELD32(0x00020000) | |
616 | ||
617 | /* | |
618 | * RF 3 | |
619 | */ | |
620 | #define RF3_TUNER FIELD32(0x00000100) | |
621 | #define RF3_TXPOWER FIELD32(0x00003e00) | |
622 | ||
623 | /* | |
624 | * EEPROM contents. | |
625 | */ | |
626 | ||
627 | /* | |
628 | * HW MAC address. | |
629 | */ | |
630 | #define EEPROM_MAC_ADDR_0 0x0002 | |
631 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
632 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
633 | #define EEPROM_MAC_ADDR1 0x0003 | |
634 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | |
635 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
636 | #define EEPROM_MAC_ADDR_2 0x0004 | |
637 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | |
638 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
639 | ||
640 | /* | |
641 | * EEPROM antenna. | |
642 | * ANTENNA_NUM: Number of antenna's. | |
643 | * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
644 | * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
645 | * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd. | |
646 | * DYN_TXAGC: Dynamic TX AGC control. | |
647 | * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. | |
648 | * RF_TYPE: Rf_type of this adapter. | |
649 | */ | |
650 | #define EEPROM_ANTENNA 0x000b | |
651 | #define EEPROM_ANTENNA_NUM FIELD16(0x0003) | |
652 | #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) | |
653 | #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) | |
654 | #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0) | |
655 | #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200) | |
656 | #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) | |
657 | #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800) | |
658 | ||
659 | /* | |
660 | * EEPROM NIC config. | |
661 | * CARDBUS_ACCEL: 0: enable, 1: disable. | |
662 | * DYN_BBP_TUNE: 0: enable, 1: disable. | |
663 | * CCK_TX_POWER: CCK TX power compensation. | |
664 | */ | |
665 | #define EEPROM_NIC 0x000c | |
666 | #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001) | |
667 | #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002) | |
668 | #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c) | |
669 | ||
670 | /* | |
671 | * EEPROM geography. | |
672 | * GEO: Default geography setting for device. | |
673 | */ | |
674 | #define EEPROM_GEOGRAPHY 0x000d | |
675 | #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00) | |
676 | ||
677 | /* | |
678 | * EEPROM BBP. | |
679 | */ | |
680 | #define EEPROM_BBP_START 0x000e | |
681 | #define EEPROM_BBP_SIZE 16 | |
682 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
683 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
684 | ||
685 | /* | |
686 | * EEPROM TXPOWER | |
687 | */ | |
688 | #define EEPROM_TXPOWER_START 0x001e | |
689 | #define EEPROM_TXPOWER_SIZE 7 | |
690 | #define EEPROM_TXPOWER_1 FIELD16(0x00ff) | |
691 | #define EEPROM_TXPOWER_2 FIELD16(0xff00) | |
692 | ||
693 | /* | |
694 | * EEPROM Tuning threshold | |
695 | */ | |
696 | #define EEPROM_BBPTUNE 0x0030 | |
697 | #define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff) | |
698 | ||
699 | /* | |
700 | * EEPROM BBP R24 Tuning. | |
701 | */ | |
702 | #define EEPROM_BBPTUNE_R24 0x0031 | |
703 | #define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff) | |
704 | #define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00) | |
705 | ||
706 | /* | |
707 | * EEPROM BBP R25 Tuning. | |
708 | */ | |
709 | #define EEPROM_BBPTUNE_R25 0x0032 | |
710 | #define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff) | |
711 | #define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00) | |
712 | ||
713 | /* | |
714 | * EEPROM BBP R24 Tuning. | |
715 | */ | |
716 | #define EEPROM_BBPTUNE_R61 0x0033 | |
717 | #define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff) | |
718 | #define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00) | |
719 | ||
720 | /* | |
721 | * EEPROM BBP VGC Tuning. | |
722 | */ | |
723 | #define EEPROM_BBPTUNE_VGC 0x0034 | |
724 | #define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff) | |
6bb40dd1 | 725 | #define EEPROM_BBPTUNE_VGCLOWER FIELD16(0xff00) |
95ea3627 ID |
726 | |
727 | /* | |
728 | * EEPROM BBP R17 Tuning. | |
729 | */ | |
730 | #define EEPROM_BBPTUNE_R17 0x0035 | |
731 | #define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff) | |
732 | #define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00) | |
733 | ||
734 | /* | |
735 | * RSSI <-> dBm offset calibration | |
736 | */ | |
737 | #define EEPROM_CALIBRATE_OFFSET 0x0036 | |
738 | #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff) | |
739 | ||
740 | /* | |
741 | * DMA descriptor defines. | |
742 | */ | |
4bd7c452 ID |
743 | #define TXD_DESC_SIZE ( 5 * sizeof(__le32) ) |
744 | #define RXD_DESC_SIZE ( 4 * sizeof(__le32) ) | |
95ea3627 ID |
745 | |
746 | /* | |
747 | * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. | |
748 | */ | |
749 | ||
750 | /* | |
751 | * Word0 | |
752 | */ | |
753 | #define TXD_W0_PACKET_ID FIELD32(0x0000000f) | |
754 | #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0) | |
755 | #define TXD_W0_MORE_FRAG FIELD32(0x00000100) | |
756 | #define TXD_W0_ACK FIELD32(0x00000200) | |
757 | #define TXD_W0_TIMESTAMP FIELD32(0x00000400) | |
758 | #define TXD_W0_OFDM FIELD32(0x00000800) | |
759 | #define TXD_W0_NEW_SEQ FIELD32(0x00001000) | |
760 | #define TXD_W0_IFS FIELD32(0x00006000) | |
761 | #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) | |
762 | #define TXD_W0_CIPHER FIELD32(0x20000000) | |
763 | #define TXD_W0_KEY_ID FIELD32(0xc0000000) | |
764 | ||
765 | /* | |
766 | * Word1 | |
767 | */ | |
768 | #define TXD_W1_IV_OFFSET FIELD32(0x0000003f) | |
769 | #define TXD_W1_AIFS FIELD32(0x000000c0) | |
770 | #define TXD_W1_CWMIN FIELD32(0x00000f00) | |
771 | #define TXD_W1_CWMAX FIELD32(0x0000f000) | |
772 | ||
773 | /* | |
774 | * Word2: PLCP information | |
775 | */ | |
776 | #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff) | |
777 | #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00) | |
778 | #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000) | |
779 | #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000) | |
780 | ||
781 | /* | |
782 | * Word3 | |
783 | */ | |
784 | #define TXD_W3_IV FIELD32(0xffffffff) | |
785 | ||
786 | /* | |
787 | * Word4 | |
788 | */ | |
789 | #define TXD_W4_EIV FIELD32(0xffffffff) | |
790 | ||
791 | /* | |
792 | * RX descriptor format for RX Ring. | |
793 | */ | |
794 | ||
795 | /* | |
796 | * Word0 | |
797 | */ | |
798 | #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) | |
799 | #define RXD_W0_MULTICAST FIELD32(0x00000004) | |
800 | #define RXD_W0_BROADCAST FIELD32(0x00000008) | |
801 | #define RXD_W0_MY_BSS FIELD32(0x00000010) | |
802 | #define RXD_W0_CRC_ERROR FIELD32(0x00000020) | |
803 | #define RXD_W0_OFDM FIELD32(0x00000040) | |
804 | #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) | |
805 | #define RXD_W0_CIPHER FIELD32(0x00000100) | |
806 | #define RXD_W0_CIPHER_ERROR FIELD32(0x00000200) | |
807 | #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) | |
808 | ||
809 | /* | |
810 | * Word1 | |
811 | */ | |
812 | #define RXD_W1_RSSI FIELD32(0x000000ff) | |
813 | #define RXD_W1_SIGNAL FIELD32(0x0000ff00) | |
814 | ||
815 | /* | |
816 | * Word2 | |
817 | */ | |
818 | #define RXD_W2_IV FIELD32(0xffffffff) | |
819 | ||
820 | /* | |
821 | * Word3 | |
822 | */ | |
823 | #define RXD_W3_EIV FIELD32(0xffffffff) | |
824 | ||
825 | /* | |
de99ff82 ID |
826 | * Macro's for converting txpower from EEPROM to mac80211 value |
827 | * and from mac80211 value to register value. | |
95ea3627 ID |
828 | */ |
829 | #define MIN_TXPOWER 0 | |
830 | #define MAX_TXPOWER 31 | |
831 | #define DEFAULT_TXPOWER 24 | |
832 | ||
8c5e7a5f ID |
833 | #define TXPOWER_FROM_DEV(__txpower) \ |
834 | (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
835 | ||
836 | #define TXPOWER_TO_DEV(__txpower) \ | |
837 | clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER) | |
95ea3627 ID |
838 | |
839 | #endif /* RT2500USB_H */ |