Commit | Line | Data |
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95ea3627 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2500pci | |
23 | Abstract: rt2500pci device specific routines. | |
24 | Supported chipsets: RT2560. | |
25 | */ | |
26 | ||
95ea3627 ID |
27 | #include <linux/delay.h> |
28 | #include <linux/etherdevice.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/eeprom_93cx6.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
95ea3627 ID |
35 | |
36 | #include "rt2x00.h" | |
37 | #include "rt2x00pci.h" | |
38 | #include "rt2500pci.h" | |
39 | ||
40 | /* | |
41 | * Register access. | |
42 | * All access to the CSR registers will go through the methods | |
43 | * rt2x00pci_register_read and rt2x00pci_register_write. | |
44 | * BBP and RF register require indirect register access, | |
45 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
46 | * These indirect registers work with busy bits, | |
47 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
48 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
49 | * between each attampt. When the busy bit is still set at that time, | |
50 | * the access attempt is considered to have failed, | |
51 | * and we will print an error. | |
52 | */ | |
c9c3b1a5 ID |
53 | #define WAIT_FOR_BBP(__dev, __reg) \ |
54 | rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg)) | |
55 | #define WAIT_FOR_RF(__dev, __reg) \ | |
56 | rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg)) | |
95ea3627 | 57 | |
0e14f6d3 | 58 | static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
59 | const unsigned int word, const u8 value) |
60 | { | |
61 | u32 reg; | |
62 | ||
8ff48a8b ID |
63 | mutex_lock(&rt2x00dev->csr_mutex); |
64 | ||
95ea3627 | 65 | /* |
c9c3b1a5 ID |
66 | * Wait until the BBP becomes available, afterwards we |
67 | * can safely write the new data into the register. | |
95ea3627 | 68 | */ |
c9c3b1a5 ID |
69 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
70 | reg = 0; | |
71 | rt2x00_set_field32(®, BBPCSR_VALUE, value); | |
72 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); | |
73 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); | |
74 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); | |
75 | ||
76 | rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); | |
77 | } | |
8ff48a8b | 78 | |
8ff48a8b | 79 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
80 | } |
81 | ||
0e14f6d3 | 82 | static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
83 | const unsigned int word, u8 *value) |
84 | { | |
85 | u32 reg; | |
86 | ||
8ff48a8b ID |
87 | mutex_lock(&rt2x00dev->csr_mutex); |
88 | ||
95ea3627 | 89 | /* |
c9c3b1a5 ID |
90 | * Wait until the BBP becomes available, afterwards we |
91 | * can safely write the read request into the register. | |
92 | * After the data has been written, we wait until hardware | |
93 | * returns the correct value, if at any time the register | |
94 | * doesn't become available in time, reg will be 0xffffffff | |
95 | * which means we return 0xff to the caller. | |
95ea3627 | 96 | */ |
c9c3b1a5 ID |
97 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
98 | reg = 0; | |
99 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); | |
100 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); | |
101 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); | |
95ea3627 | 102 | |
c9c3b1a5 | 103 | rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); |
95ea3627 | 104 | |
c9c3b1a5 ID |
105 | WAIT_FOR_BBP(rt2x00dev, ®); |
106 | } | |
95ea3627 ID |
107 | |
108 | *value = rt2x00_get_field32(reg, BBPCSR_VALUE); | |
8ff48a8b ID |
109 | |
110 | mutex_unlock(&rt2x00dev->csr_mutex); | |
95ea3627 ID |
111 | } |
112 | ||
0e14f6d3 | 113 | static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
114 | const unsigned int word, const u32 value) |
115 | { | |
116 | u32 reg; | |
95ea3627 | 117 | |
8ff48a8b ID |
118 | mutex_lock(&rt2x00dev->csr_mutex); |
119 | ||
c9c3b1a5 ID |
120 | /* |
121 | * Wait until the RF becomes available, afterwards we | |
122 | * can safely write the new data into the register. | |
123 | */ | |
124 | if (WAIT_FOR_RF(rt2x00dev, ®)) { | |
125 | reg = 0; | |
126 | rt2x00_set_field32(®, RFCSR_VALUE, value); | |
127 | rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); | |
128 | rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); | |
129 | rt2x00_set_field32(®, RFCSR_BUSY, 1); | |
130 | ||
131 | rt2x00pci_register_write(rt2x00dev, RFCSR, reg); | |
132 | rt2x00_rf_write(rt2x00dev, word, value); | |
95ea3627 ID |
133 | } |
134 | ||
8ff48a8b | 135 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
136 | } |
137 | ||
138 | static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom) | |
139 | { | |
140 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
141 | u32 reg; | |
142 | ||
143 | rt2x00pci_register_read(rt2x00dev, CSR21, ®); | |
144 | ||
145 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); | |
146 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); | |
147 | eeprom->reg_data_clock = | |
148 | !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); | |
149 | eeprom->reg_chip_select = | |
150 | !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); | |
151 | } | |
152 | ||
153 | static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom) | |
154 | { | |
155 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
156 | u32 reg = 0; | |
157 | ||
158 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); | |
159 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); | |
160 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, | |
161 | !!eeprom->reg_data_clock); | |
162 | rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, | |
163 | !!eeprom->reg_chip_select); | |
164 | ||
165 | rt2x00pci_register_write(rt2x00dev, CSR21, reg); | |
166 | } | |
167 | ||
168 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
95ea3627 ID |
169 | static const struct rt2x00debug rt2500pci_rt2x00debug = { |
170 | .owner = THIS_MODULE, | |
171 | .csr = { | |
743b97ca ID |
172 | .read = rt2x00pci_register_read, |
173 | .write = rt2x00pci_register_write, | |
174 | .flags = RT2X00DEBUGFS_OFFSET, | |
175 | .word_base = CSR_REG_BASE, | |
95ea3627 ID |
176 | .word_size = sizeof(u32), |
177 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
178 | }, | |
179 | .eeprom = { | |
180 | .read = rt2x00_eeprom_read, | |
181 | .write = rt2x00_eeprom_write, | |
743b97ca | 182 | .word_base = EEPROM_BASE, |
95ea3627 ID |
183 | .word_size = sizeof(u16), |
184 | .word_count = EEPROM_SIZE / sizeof(u16), | |
185 | }, | |
186 | .bbp = { | |
187 | .read = rt2500pci_bbp_read, | |
188 | .write = rt2500pci_bbp_write, | |
743b97ca | 189 | .word_base = BBP_BASE, |
95ea3627 ID |
190 | .word_size = sizeof(u8), |
191 | .word_count = BBP_SIZE / sizeof(u8), | |
192 | }, | |
193 | .rf = { | |
194 | .read = rt2x00_rf_read, | |
195 | .write = rt2500pci_rf_write, | |
743b97ca | 196 | .word_base = RF_BASE, |
95ea3627 ID |
197 | .word_size = sizeof(u32), |
198 | .word_count = RF_SIZE / sizeof(u32), | |
199 | }, | |
200 | }; | |
201 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
202 | ||
95ea3627 ID |
203 | static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
204 | { | |
205 | u32 reg; | |
206 | ||
207 | rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®); | |
208 | return rt2x00_get_field32(reg, GPIOCSR_BIT0); | |
209 | } | |
95ea3627 | 210 | |
771fd565 | 211 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 212 | static void rt2500pci_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
213 | enum led_brightness brightness) |
214 | { | |
215 | struct rt2x00_led *led = | |
216 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
217 | unsigned int enabled = brightness != LED_OFF; | |
a9450b70 ID |
218 | u32 reg; |
219 | ||
220 | rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®); | |
221 | ||
a2e1d52a | 222 | if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) |
a9450b70 | 223 | rt2x00_set_field32(®, LEDCSR_LINK, enabled); |
a2e1d52a ID |
224 | else if (led->type == LED_TYPE_ACTIVITY) |
225 | rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); | |
a9450b70 ID |
226 | |
227 | rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); | |
228 | } | |
a2e1d52a ID |
229 | |
230 | static int rt2500pci_blink_set(struct led_classdev *led_cdev, | |
231 | unsigned long *delay_on, | |
232 | unsigned long *delay_off) | |
233 | { | |
234 | struct rt2x00_led *led = | |
235 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
236 | u32 reg; | |
237 | ||
238 | rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®); | |
239 | rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); | |
240 | rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); | |
241 | rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); | |
242 | ||
243 | return 0; | |
244 | } | |
475433be ID |
245 | |
246 | static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev, | |
247 | struct rt2x00_led *led, | |
248 | enum led_type type) | |
249 | { | |
250 | led->rt2x00dev = rt2x00dev; | |
251 | led->type = type; | |
252 | led->led_dev.brightness_set = rt2500pci_brightness_set; | |
253 | led->led_dev.blink_set = rt2500pci_blink_set; | |
254 | led->flags = LED_INITIALIZED; | |
255 | } | |
771fd565 | 256 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 257 | |
95ea3627 ID |
258 | /* |
259 | * Configuration handlers. | |
260 | */ | |
3a643d24 ID |
261 | static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev, |
262 | const unsigned int filter_flags) | |
263 | { | |
264 | u32 reg; | |
265 | ||
266 | /* | |
267 | * Start configuration steps. | |
268 | * Note that the version error will always be dropped | |
269 | * and broadcast frames will always be accepted since | |
270 | * there is no filter for it at this time. | |
271 | */ | |
272 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | |
273 | rt2x00_set_field32(®, RXCSR0_DROP_CRC, | |
274 | !(filter_flags & FIF_FCSFAIL)); | |
275 | rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, | |
276 | !(filter_flags & FIF_PLCPFAIL)); | |
277 | rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, | |
278 | !(filter_flags & FIF_CONTROL)); | |
279 | rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, | |
280 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
281 | rt2x00_set_field32(®, RXCSR0_DROP_TODS, | |
e0b005fa ID |
282 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
283 | !rt2x00dev->intf_ap_count); | |
3a643d24 ID |
284 | rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); |
285 | rt2x00_set_field32(®, RXCSR0_DROP_MCAST, | |
286 | !(filter_flags & FIF_ALLMULTI)); | |
287 | rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); | |
288 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | |
289 | } | |
290 | ||
6bb40dd1 ID |
291 | static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, |
292 | struct rt2x00_intf *intf, | |
293 | struct rt2x00intf_conf *conf, | |
294 | const unsigned int flags) | |
95ea3627 | 295 | { |
a2440830 | 296 | struct data_queue *queue = rt2x00dev->bcn; |
6bb40dd1 | 297 | unsigned int bcn_preload; |
95ea3627 ID |
298 | u32 reg; |
299 | ||
6bb40dd1 | 300 | if (flags & CONFIG_UPDATE_TYPE) { |
6bb40dd1 ID |
301 | /* |
302 | * Enable beacon config | |
303 | */ | |
bad13639 | 304 | bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20); |
6bb40dd1 ID |
305 | rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®); |
306 | rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); | |
307 | rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); | |
308 | rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); | |
95ea3627 | 309 | |
6bb40dd1 ID |
310 | /* |
311 | * Enable synchronisation. | |
312 | */ | |
313 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | |
6bb40dd1 ID |
314 | rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); |
315 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
316 | } | |
317 | ||
318 | if (flags & CONFIG_UPDATE_MAC) | |
319 | rt2x00pci_register_multiwrite(rt2x00dev, CSR3, | |
320 | conf->mac, sizeof(conf->mac)); | |
321 | ||
322 | if (flags & CONFIG_UPDATE_BSSID) | |
323 | rt2x00pci_register_multiwrite(rt2x00dev, CSR5, | |
324 | conf->bssid, sizeof(conf->bssid)); | |
95ea3627 ID |
325 | } |
326 | ||
3a643d24 | 327 | static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, |
02044643 HS |
328 | struct rt2x00lib_erp *erp, |
329 | u32 changed) | |
95ea3627 | 330 | { |
5c58ee51 | 331 | int preamble_mask; |
95ea3627 | 332 | u32 reg; |
95ea3627 | 333 | |
5c58ee51 ID |
334 | /* |
335 | * When short preamble is enabled, we should set bit 0x08 | |
336 | */ | |
02044643 HS |
337 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
338 | preamble_mask = erp->short_preamble << 3; | |
339 | ||
340 | rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); | |
341 | rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); | |
342 | rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); | |
343 | rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); | |
344 | rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); | |
345 | rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); | |
346 | ||
347 | rt2x00pci_register_read(rt2x00dev, ARCSR2, ®); | |
348 | rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); | |
349 | rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); | |
350 | rt2x00_set_field32(®, ARCSR2_LENGTH, | |
351 | GET_DURATION(ACK_SIZE, 10)); | |
352 | rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); | |
353 | ||
354 | rt2x00pci_register_read(rt2x00dev, ARCSR3, ®); | |
355 | rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); | |
356 | rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); | |
357 | rt2x00_set_field32(®, ARCSR2_LENGTH, | |
358 | GET_DURATION(ACK_SIZE, 20)); | |
359 | rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); | |
360 | ||
361 | rt2x00pci_register_read(rt2x00dev, ARCSR4, ®); | |
362 | rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); | |
363 | rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); | |
364 | rt2x00_set_field32(®, ARCSR2_LENGTH, | |
365 | GET_DURATION(ACK_SIZE, 55)); | |
366 | rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); | |
367 | ||
368 | rt2x00pci_register_read(rt2x00dev, ARCSR5, ®); | |
369 | rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); | |
370 | rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); | |
371 | rt2x00_set_field32(®, ARCSR2_LENGTH, | |
372 | GET_DURATION(ACK_SIZE, 110)); | |
373 | rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); | |
374 | } | |
375 | ||
376 | if (changed & BSS_CHANGED_BASIC_RATES) | |
377 | rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); | |
378 | ||
379 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
380 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); | |
381 | rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); | |
382 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); | |
383 | ||
384 | rt2x00pci_register_read(rt2x00dev, CSR18, ®); | |
385 | rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); | |
386 | rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); | |
387 | rt2x00pci_register_write(rt2x00dev, CSR18, reg); | |
388 | ||
389 | rt2x00pci_register_read(rt2x00dev, CSR19, ®); | |
390 | rt2x00_set_field32(®, CSR19_DIFS, erp->difs); | |
391 | rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); | |
392 | rt2x00pci_register_write(rt2x00dev, CSR19, reg); | |
393 | } | |
394 | ||
395 | if (changed & BSS_CHANGED_BEACON_INT) { | |
396 | rt2x00pci_register_read(rt2x00dev, CSR12, ®); | |
397 | rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, | |
398 | erp->beacon_int * 16); | |
399 | rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, | |
400 | erp->beacon_int * 16); | |
401 | rt2x00pci_register_write(rt2x00dev, CSR12, reg); | |
402 | } | |
403 | ||
95ea3627 ID |
404 | } |
405 | ||
e4ea1c40 ID |
406 | static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, |
407 | struct antenna_setup *ant) | |
95ea3627 | 408 | { |
e4ea1c40 ID |
409 | u32 reg; |
410 | u8 r14; | |
411 | u8 r2; | |
412 | ||
413 | /* | |
414 | * We should never come here because rt2x00lib is supposed | |
415 | * to catch this and send us the correct antenna explicitely. | |
416 | */ | |
417 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
418 | ant->tx == ANTENNA_SW_DIVERSITY); | |
419 | ||
420 | rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®); | |
421 | rt2500pci_bbp_read(rt2x00dev, 14, &r14); | |
422 | rt2500pci_bbp_read(rt2x00dev, 2, &r2); | |
423 | ||
424 | /* | |
425 | * Configure the TX antenna. | |
426 | */ | |
427 | switch (ant->tx) { | |
428 | case ANTENNA_A: | |
429 | rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0); | |
430 | rt2x00_set_field32(®, BBPCSR1_CCK, 0); | |
431 | rt2x00_set_field32(®, BBPCSR1_OFDM, 0); | |
432 | break; | |
433 | case ANTENNA_B: | |
434 | default: | |
435 | rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2); | |
436 | rt2x00_set_field32(®, BBPCSR1_CCK, 2); | |
437 | rt2x00_set_field32(®, BBPCSR1_OFDM, 2); | |
438 | break; | |
439 | } | |
440 | ||
441 | /* | |
442 | * Configure the RX antenna. | |
443 | */ | |
444 | switch (ant->rx) { | |
445 | case ANTENNA_A: | |
446 | rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0); | |
447 | break; | |
448 | case ANTENNA_B: | |
449 | default: | |
450 | rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2); | |
451 | break; | |
452 | } | |
453 | ||
454 | /* | |
455 | * RT2525E and RT5222 need to flip TX I/Q | |
456 | */ | |
5122d898 | 457 | if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) { |
e4ea1c40 ID |
458 | rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1); |
459 | rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); | |
460 | rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); | |
461 | ||
462 | /* | |
463 | * RT2525E does not need RX I/Q Flip. | |
464 | */ | |
5122d898 | 465 | if (rt2x00_rf(rt2x00dev, RF2525E)) |
e4ea1c40 ID |
466 | rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0); |
467 | } else { | |
468 | rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); | |
469 | rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); | |
470 | } | |
471 | ||
472 | rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg); | |
473 | rt2500pci_bbp_write(rt2x00dev, 14, r14); | |
474 | rt2500pci_bbp_write(rt2x00dev, 2, r2); | |
95ea3627 ID |
475 | } |
476 | ||
477 | static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev, | |
5c58ee51 | 478 | struct rf_channel *rf, const int txpower) |
95ea3627 | 479 | { |
95ea3627 ID |
480 | u8 r70; |
481 | ||
95ea3627 ID |
482 | /* |
483 | * Set TXpower. | |
484 | */ | |
5c58ee51 | 485 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); |
95ea3627 ID |
486 | |
487 | /* | |
488 | * Switch on tuning bits. | |
489 | * For RT2523 devices we do not need to update the R1 register. | |
490 | */ | |
5122d898 | 491 | if (!rt2x00_rf(rt2x00dev, RF2523)) |
5c58ee51 ID |
492 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); |
493 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); | |
95ea3627 ID |
494 | |
495 | /* | |
496 | * For RT2525 we should first set the channel to half band higher. | |
497 | */ | |
5122d898 | 498 | if (rt2x00_rf(rt2x00dev, RF2525)) { |
95ea3627 ID |
499 | static const u32 vals[] = { |
500 | 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a, | |
501 | 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a, | |
502 | 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a, | |
503 | 0x00080d2e, 0x00080d3a | |
504 | }; | |
505 | ||
5c58ee51 ID |
506 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); |
507 | rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]); | |
508 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); | |
509 | if (rf->rf4) | |
510 | rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); | |
95ea3627 ID |
511 | } |
512 | ||
5c58ee51 ID |
513 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); |
514 | rt2500pci_rf_write(rt2x00dev, 2, rf->rf2); | |
515 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); | |
516 | if (rf->rf4) | |
517 | rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); | |
95ea3627 ID |
518 | |
519 | /* | |
520 | * Channel 14 requires the Japan filter bit to be set. | |
521 | */ | |
522 | r70 = 0x46; | |
5c58ee51 | 523 | rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14); |
95ea3627 ID |
524 | rt2500pci_bbp_write(rt2x00dev, 70, r70); |
525 | ||
526 | msleep(1); | |
527 | ||
528 | /* | |
529 | * Switch off tuning bits. | |
530 | * For RT2523 devices we do not need to update the R1 register. | |
531 | */ | |
5122d898 | 532 | if (!rt2x00_rf(rt2x00dev, RF2523)) { |
5c58ee51 ID |
533 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); |
534 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); | |
95ea3627 ID |
535 | } |
536 | ||
5c58ee51 ID |
537 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); |
538 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); | |
95ea3627 ID |
539 | |
540 | /* | |
541 | * Clear false CRC during channel switch. | |
542 | */ | |
5c58ee51 | 543 | rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1); |
95ea3627 ID |
544 | } |
545 | ||
546 | static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev, | |
547 | const int txpower) | |
548 | { | |
549 | u32 rf3; | |
550 | ||
551 | rt2x00_rf_read(rt2x00dev, 3, &rf3); | |
552 | rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
553 | rt2500pci_rf_write(rt2x00dev, 3, rf3); | |
554 | } | |
555 | ||
e4ea1c40 ID |
556 | static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
557 | struct rt2x00lib_conf *libconf) | |
95ea3627 ID |
558 | { |
559 | u32 reg; | |
95ea3627 | 560 | |
e4ea1c40 ID |
561 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); |
562 | rt2x00_set_field32(®, CSR11_LONG_RETRY, | |
563 | libconf->conf->long_frame_max_tx_count); | |
564 | rt2x00_set_field32(®, CSR11_SHORT_RETRY, | |
565 | libconf->conf->short_frame_max_tx_count); | |
566 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); | |
95ea3627 ID |
567 | } |
568 | ||
7d7f19cc ID |
569 | static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev, |
570 | struct rt2x00lib_conf *libconf) | |
571 | { | |
572 | enum dev_state state = | |
573 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
574 | STATE_SLEEP : STATE_AWAKE; | |
575 | u32 reg; | |
576 | ||
577 | if (state == STATE_SLEEP) { | |
578 | rt2x00pci_register_read(rt2x00dev, CSR20, ®); | |
579 | rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, | |
6b347bff | 580 | (rt2x00dev->beacon_int - 20) * 16); |
7d7f19cc ID |
581 | rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, |
582 | libconf->conf->listen_interval - 1); | |
583 | ||
584 | /* We must first disable autowake before it can be enabled */ | |
585 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); | |
586 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); | |
587 | ||
588 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); | |
589 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); | |
5731858d GW |
590 | } else { |
591 | rt2x00pci_register_read(rt2x00dev, CSR20, ®); | |
592 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); | |
593 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); | |
7d7f19cc ID |
594 | } |
595 | ||
596 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
597 | } | |
598 | ||
95ea3627 | 599 | static void rt2500pci_config(struct rt2x00_dev *rt2x00dev, |
6bb40dd1 ID |
600 | struct rt2x00lib_conf *libconf, |
601 | const unsigned int flags) | |
95ea3627 | 602 | { |
e4ea1c40 | 603 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
5c58ee51 ID |
604 | rt2500pci_config_channel(rt2x00dev, &libconf->rf, |
605 | libconf->conf->power_level); | |
e4ea1c40 ID |
606 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
607 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) | |
5c58ee51 ID |
608 | rt2500pci_config_txpower(rt2x00dev, |
609 | libconf->conf->power_level); | |
e4ea1c40 ID |
610 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
611 | rt2500pci_config_retry_limit(rt2x00dev, libconf); | |
7d7f19cc ID |
612 | if (flags & IEEE80211_CONF_CHANGE_PS) |
613 | rt2500pci_config_ps(rt2x00dev, libconf); | |
95ea3627 ID |
614 | } |
615 | ||
95ea3627 ID |
616 | /* |
617 | * Link tuning | |
618 | */ | |
ebcf26da ID |
619 | static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev, |
620 | struct link_qual *qual) | |
95ea3627 ID |
621 | { |
622 | u32 reg; | |
623 | ||
624 | /* | |
625 | * Update FCS error count from register. | |
626 | */ | |
627 | rt2x00pci_register_read(rt2x00dev, CNT0, ®); | |
ebcf26da | 628 | qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); |
95ea3627 ID |
629 | |
630 | /* | |
631 | * Update False CCA count from register. | |
632 | */ | |
633 | rt2x00pci_register_read(rt2x00dev, CNT3, ®); | |
ebcf26da | 634 | qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); |
95ea3627 ID |
635 | } |
636 | ||
5352ff65 ID |
637 | static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev, |
638 | struct link_qual *qual, u8 vgc_level) | |
eb20b4e8 | 639 | { |
5352ff65 | 640 | if (qual->vgc_level_reg != vgc_level) { |
eb20b4e8 | 641 | rt2500pci_bbp_write(rt2x00dev, 17, vgc_level); |
223dcc26 | 642 | qual->vgc_level = vgc_level; |
5352ff65 | 643 | qual->vgc_level_reg = vgc_level; |
eb20b4e8 ID |
644 | } |
645 | } | |
646 | ||
5352ff65 ID |
647 | static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev, |
648 | struct link_qual *qual) | |
95ea3627 | 649 | { |
5352ff65 | 650 | rt2500pci_set_vgc(rt2x00dev, qual, 0x48); |
95ea3627 ID |
651 | } |
652 | ||
5352ff65 ID |
653 | static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, |
654 | struct link_qual *qual, const u32 count) | |
95ea3627 | 655 | { |
95ea3627 ID |
656 | /* |
657 | * To prevent collisions with MAC ASIC on chipsets | |
658 | * up to version C the link tuning should halt after 20 | |
6bb40dd1 | 659 | * seconds while being associated. |
95ea3627 | 660 | */ |
5122d898 | 661 | if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D && |
5352ff65 | 662 | rt2x00dev->intf_associated && count > 20) |
95ea3627 ID |
663 | return; |
664 | ||
95ea3627 ID |
665 | /* |
666 | * Chipset versions C and lower should directly continue | |
6bb40dd1 ID |
667 | * to the dynamic CCA tuning. Chipset version D and higher |
668 | * should go straight to dynamic CCA tuning when they | |
669 | * are not associated. | |
95ea3627 | 670 | */ |
5122d898 | 671 | if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D || |
6bb40dd1 | 672 | !rt2x00dev->intf_associated) |
95ea3627 ID |
673 | goto dynamic_cca_tune; |
674 | ||
675 | /* | |
676 | * A too low RSSI will cause too much false CCA which will | |
677 | * then corrupt the R17 tuning. To remidy this the tuning should | |
678 | * be stopped (While making sure the R17 value will not exceed limits) | |
679 | */ | |
5352ff65 ID |
680 | if (qual->rssi < -80 && count > 20) { |
681 | if (qual->vgc_level_reg >= 0x41) | |
682 | rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); | |
95ea3627 ID |
683 | return; |
684 | } | |
685 | ||
686 | /* | |
687 | * Special big-R17 for short distance | |
688 | */ | |
5352ff65 ID |
689 | if (qual->rssi >= -58) { |
690 | rt2500pci_set_vgc(rt2x00dev, qual, 0x50); | |
95ea3627 ID |
691 | return; |
692 | } | |
693 | ||
694 | /* | |
695 | * Special mid-R17 for middle distance | |
696 | */ | |
5352ff65 ID |
697 | if (qual->rssi >= -74) { |
698 | rt2500pci_set_vgc(rt2x00dev, qual, 0x41); | |
95ea3627 ID |
699 | return; |
700 | } | |
701 | ||
702 | /* | |
703 | * Leave short or middle distance condition, restore r17 | |
704 | * to the dynamic tuning range. | |
705 | */ | |
5352ff65 ID |
706 | if (qual->vgc_level_reg >= 0x41) { |
707 | rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); | |
95ea3627 ID |
708 | return; |
709 | } | |
710 | ||
711 | dynamic_cca_tune: | |
712 | ||
713 | /* | |
714 | * R17 is inside the dynamic tuning range, | |
715 | * start tuning the link based on the false cca counter. | |
716 | */ | |
223dcc26 | 717 | if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) |
5352ff65 | 718 | rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg); |
223dcc26 | 719 | else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) |
5352ff65 | 720 | rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg); |
95ea3627 ID |
721 | } |
722 | ||
5450b7e2 ID |
723 | /* |
724 | * Queue handlers. | |
725 | */ | |
726 | static void rt2500pci_start_queue(struct data_queue *queue) | |
727 | { | |
728 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
729 | u32 reg; | |
730 | ||
731 | switch (queue->qid) { | |
732 | case QID_RX: | |
733 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | |
734 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); | |
735 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | |
736 | break; | |
737 | case QID_BEACON: | |
16222a0d HS |
738 | /* |
739 | * Allow the tbtt tasklet to be scheduled. | |
740 | */ | |
741 | tasklet_enable(&rt2x00dev->tbtt_tasklet); | |
742 | ||
5450b7e2 ID |
743 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
744 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); | |
745 | rt2x00_set_field32(®, CSR14_TBCN, 1); | |
746 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); | |
747 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
748 | break; | |
749 | default: | |
750 | break; | |
751 | } | |
752 | } | |
753 | ||
754 | static void rt2500pci_kick_queue(struct data_queue *queue) | |
755 | { | |
756 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
757 | u32 reg; | |
758 | ||
759 | switch (queue->qid) { | |
f615e9a3 | 760 | case QID_AC_VO: |
5450b7e2 ID |
761 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); |
762 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); | |
763 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | |
764 | break; | |
f615e9a3 | 765 | case QID_AC_VI: |
5450b7e2 ID |
766 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); |
767 | rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); | |
768 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | |
769 | break; | |
770 | case QID_ATIM: | |
771 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | |
772 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); | |
773 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | |
774 | break; | |
775 | default: | |
776 | break; | |
777 | } | |
778 | } | |
779 | ||
780 | static void rt2500pci_stop_queue(struct data_queue *queue) | |
781 | { | |
782 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
783 | u32 reg; | |
784 | ||
785 | switch (queue->qid) { | |
f615e9a3 ID |
786 | case QID_AC_VO: |
787 | case QID_AC_VI: | |
5450b7e2 ID |
788 | case QID_ATIM: |
789 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | |
790 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); | |
791 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | |
792 | break; | |
793 | case QID_RX: | |
794 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | |
795 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); | |
796 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | |
797 | break; | |
798 | case QID_BEACON: | |
799 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | |
800 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); | |
801 | rt2x00_set_field32(®, CSR14_TBCN, 0); | |
802 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | |
803 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
16222a0d HS |
804 | |
805 | /* | |
806 | * Wait for possibly running tbtt tasklets. | |
807 | */ | |
808 | tasklet_disable(&rt2x00dev->tbtt_tasklet); | |
5450b7e2 ID |
809 | break; |
810 | default: | |
811 | break; | |
812 | } | |
813 | } | |
814 | ||
95ea3627 ID |
815 | /* |
816 | * Initialization functions. | |
817 | */ | |
798b7adb | 818 | static bool rt2500pci_get_entry_state(struct queue_entry *entry) |
95ea3627 | 819 | { |
b8be63ff | 820 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
95ea3627 ID |
821 | u32 word; |
822 | ||
798b7adb ID |
823 | if (entry->queue->qid == QID_RX) { |
824 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
825 | ||
826 | return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); | |
827 | } else { | |
828 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 | 829 | |
798b7adb ID |
830 | return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
831 | rt2x00_get_field32(word, TXD_W0_VALID)); | |
832 | } | |
95ea3627 ID |
833 | } |
834 | ||
798b7adb | 835 | static void rt2500pci_clear_entry(struct queue_entry *entry) |
95ea3627 | 836 | { |
b8be63ff | 837 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
798b7adb | 838 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
95ea3627 ID |
839 | u32 word; |
840 | ||
798b7adb ID |
841 | if (entry->queue->qid == QID_RX) { |
842 | rt2x00_desc_read(entry_priv->desc, 1, &word); | |
843 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); | |
844 | rt2x00_desc_write(entry_priv->desc, 1, word); | |
845 | ||
846 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
847 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); | |
848 | rt2x00_desc_write(entry_priv->desc, 0, word); | |
849 | } else { | |
850 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
851 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); | |
852 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); | |
853 | rt2x00_desc_write(entry_priv->desc, 0, word); | |
854 | } | |
95ea3627 ID |
855 | } |
856 | ||
181d6902 | 857 | static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) |
95ea3627 | 858 | { |
b8be63ff | 859 | struct queue_entry_priv_pci *entry_priv; |
95ea3627 ID |
860 | u32 reg; |
861 | ||
95ea3627 ID |
862 | /* |
863 | * Initialize registers. | |
864 | */ | |
865 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); | |
181d6902 ID |
866 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); |
867 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); | |
e74df4a7 | 868 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); |
181d6902 | 869 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
95ea3627 ID |
870 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
871 | ||
b8be63ff | 872 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
95ea3627 | 873 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); |
30b3a23c | 874 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, |
b8be63ff | 875 | entry_priv->desc_dma); |
95ea3627 ID |
876 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); |
877 | ||
b8be63ff | 878 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
95ea3627 | 879 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); |
30b3a23c | 880 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, |
b8be63ff | 881 | entry_priv->desc_dma); |
95ea3627 ID |
882 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
883 | ||
e74df4a7 | 884 | entry_priv = rt2x00dev->atim->entries[0].priv_data; |
95ea3627 | 885 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
30b3a23c | 886 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
b8be63ff | 887 | entry_priv->desc_dma); |
95ea3627 ID |
888 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
889 | ||
e74df4a7 | 890 | entry_priv = rt2x00dev->bcn->entries[0].priv_data; |
95ea3627 | 891 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
30b3a23c | 892 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
b8be63ff | 893 | entry_priv->desc_dma); |
95ea3627 ID |
894 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); |
895 | ||
896 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); | |
897 | rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); | |
181d6902 | 898 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); |
95ea3627 ID |
899 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); |
900 | ||
b8be63ff | 901 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
95ea3627 | 902 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); |
b8be63ff ID |
903 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, |
904 | entry_priv->desc_dma); | |
95ea3627 ID |
905 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
910 | static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev) | |
911 | { | |
912 | u32 reg; | |
913 | ||
914 | rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002); | |
915 | rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002); | |
916 | rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002); | |
917 | rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002); | |
918 | ||
919 | rt2x00pci_register_read(rt2x00dev, TIMECSR, ®); | |
920 | rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); | |
921 | rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); | |
922 | rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); | |
923 | rt2x00pci_register_write(rt2x00dev, TIMECSR, reg); | |
924 | ||
925 | rt2x00pci_register_read(rt2x00dev, CSR9, ®); | |
926 | rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, | |
927 | rt2x00dev->rx->data_size / 128); | |
928 | rt2x00pci_register_write(rt2x00dev, CSR9, reg); | |
929 | ||
930 | /* | |
931 | * Always use CWmin and CWmax set in descriptor. | |
932 | */ | |
933 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); | |
934 | rt2x00_set_field32(®, CSR11_CW_SELECT, 0); | |
935 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); | |
936 | ||
1f909162 ID |
937 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
938 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); | |
939 | rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); | |
940 | rt2x00_set_field32(®, CSR14_TBCN, 0); | |
941 | rt2x00_set_field32(®, CSR14_TCFP, 0); | |
942 | rt2x00_set_field32(®, CSR14_TATIMW, 0); | |
943 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | |
944 | rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); | |
945 | rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); | |
946 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
947 | ||
95ea3627 ID |
948 | rt2x00pci_register_write(rt2x00dev, CNT3, 0); |
949 | ||
950 | rt2x00pci_register_read(rt2x00dev, TXCSR8, ®); | |
951 | rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); | |
952 | rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); | |
953 | rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); | |
954 | rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); | |
955 | rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); | |
956 | rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); | |
957 | rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); | |
958 | rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); | |
959 | rt2x00pci_register_write(rt2x00dev, TXCSR8, reg); | |
960 | ||
961 | rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®); | |
962 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); | |
963 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); | |
964 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); | |
965 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); | |
966 | rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg); | |
967 | ||
968 | rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®); | |
969 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); | |
970 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); | |
971 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); | |
972 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); | |
973 | rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg); | |
974 | ||
975 | rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®); | |
976 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); | |
977 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); | |
978 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); | |
979 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); | |
980 | rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg); | |
981 | ||
982 | rt2x00pci_register_read(rt2x00dev, RXCSR3, ®); | |
983 | rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ | |
984 | rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); | |
985 | rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ | |
986 | rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); | |
987 | rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ | |
988 | rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); | |
989 | rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ | |
990 | rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); | |
991 | rt2x00pci_register_write(rt2x00dev, RXCSR3, reg); | |
992 | ||
993 | rt2x00pci_register_read(rt2x00dev, PCICSR, ®); | |
994 | rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); | |
995 | rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); | |
996 | rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); | |
997 | rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); | |
998 | rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); | |
999 | rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); | |
1000 | rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); | |
1001 | rt2x00pci_register_write(rt2x00dev, PCICSR, reg); | |
1002 | ||
1003 | rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); | |
1004 | ||
1005 | rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00); | |
1006 | rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0); | |
1007 | ||
1008 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
1009 | return -EBUSY; | |
1010 | ||
1011 | rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223); | |
1012 | rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518); | |
1013 | ||
1014 | rt2x00pci_register_read(rt2x00dev, MACCSR2, ®); | |
1015 | rt2x00_set_field32(®, MACCSR2_DELAY, 64); | |
1016 | rt2x00pci_register_write(rt2x00dev, MACCSR2, reg); | |
1017 | ||
1018 | rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®); | |
1019 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); | |
1020 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); | |
1021 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); | |
1022 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); | |
1023 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); | |
1024 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); | |
1025 | rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg); | |
1026 | ||
1027 | rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200); | |
1028 | ||
1029 | rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020); | |
1030 | ||
1031 | rt2x00pci_register_read(rt2x00dev, CSR1, ®); | |
1032 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); | |
1033 | rt2x00_set_field32(®, CSR1_BBP_RESET, 0); | |
1034 | rt2x00_set_field32(®, CSR1_HOST_READY, 0); | |
1035 | rt2x00pci_register_write(rt2x00dev, CSR1, reg); | |
1036 | ||
1037 | rt2x00pci_register_read(rt2x00dev, CSR1, ®); | |
1038 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); | |
1039 | rt2x00_set_field32(®, CSR1_HOST_READY, 1); | |
1040 | rt2x00pci_register_write(rt2x00dev, CSR1, reg); | |
1041 | ||
1042 | /* | |
1043 | * We must clear the FCS and FIFO error count. | |
1044 | * These registers are cleared on read, | |
1045 | * so we may pass a useless variable to store the value. | |
1046 | */ | |
1047 | rt2x00pci_register_read(rt2x00dev, CNT0, ®); | |
1048 | rt2x00pci_register_read(rt2x00dev, CNT4, ®); | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
2b08da3f | 1053 | static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1054 | { |
1055 | unsigned int i; | |
95ea3627 ID |
1056 | u8 value; |
1057 | ||
1058 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1059 | rt2500pci_bbp_read(rt2x00dev, 0, &value); | |
1060 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 1061 | return 0; |
95ea3627 ID |
1062 | udelay(REGISTER_BUSY_DELAY); |
1063 | } | |
1064 | ||
1065 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
1066 | return -EACCES; | |
2b08da3f ID |
1067 | } |
1068 | ||
1069 | static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1070 | { | |
1071 | unsigned int i; | |
1072 | u16 eeprom; | |
1073 | u8 reg_id; | |
1074 | u8 value; | |
1075 | ||
1076 | if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev))) | |
1077 | return -EACCES; | |
95ea3627 | 1078 | |
95ea3627 ID |
1079 | rt2500pci_bbp_write(rt2x00dev, 3, 0x02); |
1080 | rt2500pci_bbp_write(rt2x00dev, 4, 0x19); | |
1081 | rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); | |
1082 | rt2500pci_bbp_write(rt2x00dev, 15, 0x30); | |
1083 | rt2500pci_bbp_write(rt2x00dev, 16, 0xac); | |
1084 | rt2500pci_bbp_write(rt2x00dev, 18, 0x18); | |
1085 | rt2500pci_bbp_write(rt2x00dev, 19, 0xff); | |
1086 | rt2500pci_bbp_write(rt2x00dev, 20, 0x1e); | |
1087 | rt2500pci_bbp_write(rt2x00dev, 21, 0x08); | |
1088 | rt2500pci_bbp_write(rt2x00dev, 22, 0x08); | |
1089 | rt2500pci_bbp_write(rt2x00dev, 23, 0x08); | |
1090 | rt2500pci_bbp_write(rt2x00dev, 24, 0x70); | |
1091 | rt2500pci_bbp_write(rt2x00dev, 25, 0x40); | |
1092 | rt2500pci_bbp_write(rt2x00dev, 26, 0x08); | |
1093 | rt2500pci_bbp_write(rt2x00dev, 27, 0x23); | |
1094 | rt2500pci_bbp_write(rt2x00dev, 30, 0x10); | |
1095 | rt2500pci_bbp_write(rt2x00dev, 31, 0x2b); | |
1096 | rt2500pci_bbp_write(rt2x00dev, 32, 0xb9); | |
1097 | rt2500pci_bbp_write(rt2x00dev, 34, 0x12); | |
1098 | rt2500pci_bbp_write(rt2x00dev, 35, 0x50); | |
1099 | rt2500pci_bbp_write(rt2x00dev, 39, 0xc4); | |
1100 | rt2500pci_bbp_write(rt2x00dev, 40, 0x02); | |
1101 | rt2500pci_bbp_write(rt2x00dev, 41, 0x60); | |
1102 | rt2500pci_bbp_write(rt2x00dev, 53, 0x10); | |
1103 | rt2500pci_bbp_write(rt2x00dev, 54, 0x18); | |
1104 | rt2500pci_bbp_write(rt2x00dev, 56, 0x08); | |
1105 | rt2500pci_bbp_write(rt2x00dev, 57, 0x10); | |
1106 | rt2500pci_bbp_write(rt2x00dev, 58, 0x08); | |
1107 | rt2500pci_bbp_write(rt2x00dev, 61, 0x6d); | |
1108 | rt2500pci_bbp_write(rt2x00dev, 62, 0x10); | |
1109 | ||
95ea3627 ID |
1110 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
1111 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1112 | ||
1113 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1114 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1115 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
1116 | rt2500pci_bbp_write(rt2x00dev, reg_id, value); |
1117 | } | |
1118 | } | |
95ea3627 ID |
1119 | |
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | /* | |
1124 | * Device state switch handlers. | |
1125 | */ | |
95ea3627 ID |
1126 | static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
1127 | enum dev_state state) | |
1128 | { | |
b550911a | 1129 | int mask = (state == STATE_RADIO_IRQ_OFF); |
95ea3627 | 1130 | u32 reg; |
16222a0d | 1131 | unsigned long flags; |
95ea3627 ID |
1132 | |
1133 | /* | |
1134 | * When interrupts are being enabled, the interrupt registers | |
1135 | * should clear the register to assure a clean state. | |
1136 | */ | |
1137 | if (state == STATE_RADIO_IRQ_ON) { | |
1138 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); | |
1139 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); | |
16222a0d HS |
1140 | |
1141 | /* | |
1142 | * Enable tasklets. | |
1143 | */ | |
1144 | tasklet_enable(&rt2x00dev->txstatus_tasklet); | |
1145 | tasklet_enable(&rt2x00dev->rxdone_tasklet); | |
95ea3627 ID |
1146 | } |
1147 | ||
1148 | /* | |
1149 | * Only toggle the interrupts bits we are going to use. | |
1150 | * Non-checked interrupt bits are disabled by default. | |
1151 | */ | |
16222a0d HS |
1152 | spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); |
1153 | ||
95ea3627 ID |
1154 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1155 | rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); | |
1156 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); | |
1157 | rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); | |
1158 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); | |
1159 | rt2x00_set_field32(®, CSR8_RXDONE, mask); | |
1160 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | |
16222a0d HS |
1161 | |
1162 | spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); | |
1163 | ||
1164 | if (state == STATE_RADIO_IRQ_OFF) { | |
1165 | /* | |
1166 | * Ensure that all tasklets are finished. | |
1167 | */ | |
1168 | tasklet_disable(&rt2x00dev->txstatus_tasklet); | |
1169 | tasklet_disable(&rt2x00dev->rxdone_tasklet); | |
1170 | } | |
95ea3627 ID |
1171 | } |
1172 | ||
1173 | static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) | |
1174 | { | |
1175 | /* | |
1176 | * Initialize all registers. | |
1177 | */ | |
2b08da3f ID |
1178 | if (unlikely(rt2500pci_init_queues(rt2x00dev) || |
1179 | rt2500pci_init_registers(rt2x00dev) || | |
1180 | rt2500pci_init_bbp(rt2x00dev))) | |
95ea3627 | 1181 | return -EIO; |
95ea3627 | 1182 | |
95ea3627 ID |
1183 | return 0; |
1184 | } | |
1185 | ||
1186 | static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1187 | { | |
95ea3627 | 1188 | /* |
a2c9b652 | 1189 | * Disable power |
95ea3627 | 1190 | */ |
a2c9b652 | 1191 | rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0); |
95ea3627 ID |
1192 | } |
1193 | ||
1194 | static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, | |
1195 | enum dev_state state) | |
1196 | { | |
9655a6ec | 1197 | u32 reg, reg2; |
95ea3627 ID |
1198 | unsigned int i; |
1199 | char put_to_sleep; | |
1200 | char bbp_state; | |
1201 | char rf_state; | |
1202 | ||
1203 | put_to_sleep = (state != STATE_AWAKE); | |
1204 | ||
1205 | rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®); | |
1206 | rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); | |
1207 | rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); | |
1208 | rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); | |
1209 | rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); | |
1210 | rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); | |
1211 | ||
1212 | /* | |
1213 | * Device is not guaranteed to be in the requested state yet. | |
1214 | * We must wait until the register indicates that the | |
1215 | * device has entered the correct state. | |
1216 | */ | |
1217 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
9655a6ec GW |
1218 | rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®2); |
1219 | bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); | |
1220 | rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); | |
95ea3627 ID |
1221 | if (bbp_state == state && rf_state == state) |
1222 | return 0; | |
9655a6ec | 1223 | rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); |
95ea3627 ID |
1224 | msleep(10); |
1225 | } | |
1226 | ||
95ea3627 ID |
1227 | return -EBUSY; |
1228 | } | |
1229 | ||
1230 | static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1231 | enum dev_state state) | |
1232 | { | |
1233 | int retval = 0; | |
1234 | ||
1235 | switch (state) { | |
1236 | case STATE_RADIO_ON: | |
1237 | retval = rt2500pci_enable_radio(rt2x00dev); | |
1238 | break; | |
1239 | case STATE_RADIO_OFF: | |
1240 | rt2500pci_disable_radio(rt2x00dev); | |
1241 | break; | |
2b08da3f ID |
1242 | case STATE_RADIO_IRQ_ON: |
1243 | case STATE_RADIO_IRQ_OFF: | |
1244 | rt2500pci_toggle_irq(rt2x00dev, state); | |
95ea3627 ID |
1245 | break; |
1246 | case STATE_DEEP_SLEEP: | |
1247 | case STATE_SLEEP: | |
1248 | case STATE_STANDBY: | |
1249 | case STATE_AWAKE: | |
1250 | retval = rt2500pci_set_state(rt2x00dev, state); | |
1251 | break; | |
1252 | default: | |
1253 | retval = -ENOTSUPP; | |
1254 | break; | |
1255 | } | |
1256 | ||
2b08da3f ID |
1257 | if (unlikely(retval)) |
1258 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", | |
1259 | state, retval); | |
1260 | ||
95ea3627 ID |
1261 | return retval; |
1262 | } | |
1263 | ||
1264 | /* | |
1265 | * TX descriptor initialization | |
1266 | */ | |
93331458 | 1267 | static void rt2500pci_write_tx_desc(struct queue_entry *entry, |
61486e0f | 1268 | struct txentry_desc *txdesc) |
95ea3627 | 1269 | { |
93331458 ID |
1270 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
1271 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; | |
85b7a8b3 | 1272 | __le32 *txd = entry_priv->desc; |
95ea3627 ID |
1273 | u32 word; |
1274 | ||
1275 | /* | |
1276 | * Start writing the descriptor words. | |
1277 | */ | |
85b7a8b3 | 1278 | rt2x00_desc_read(txd, 1, &word); |
c4da0048 | 1279 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); |
85b7a8b3 | 1280 | rt2x00_desc_write(txd, 1, word); |
4de36fe5 | 1281 | |
95ea3627 ID |
1282 | rt2x00_desc_read(txd, 2, &word); |
1283 | rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); | |
2b23cdaa HS |
1284 | rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs); |
1285 | rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min); | |
1286 | rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max); | |
95ea3627 ID |
1287 | rt2x00_desc_write(txd, 2, word); |
1288 | ||
1289 | rt2x00_desc_read(txd, 3, &word); | |
26a1d07f HS |
1290 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); |
1291 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); | |
1292 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, | |
1293 | txdesc->u.plcp.length_low); | |
1294 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, | |
1295 | txdesc->u.plcp.length_high); | |
95ea3627 ID |
1296 | rt2x00_desc_write(txd, 3, word); |
1297 | ||
1298 | rt2x00_desc_read(txd, 10, &word); | |
1299 | rt2x00_set_field32(&word, TXD_W10_RTS, | |
181d6902 | 1300 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); |
95ea3627 ID |
1301 | rt2x00_desc_write(txd, 10, word); |
1302 | ||
e01f1ec3 GW |
1303 | /* |
1304 | * Writing TXD word 0 must the last to prevent a race condition with | |
1305 | * the device, whereby the device may take hold of the TXD before we | |
1306 | * finished updating it. | |
1307 | */ | |
95ea3627 ID |
1308 | rt2x00_desc_read(txd, 0, &word); |
1309 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); | |
1310 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1311 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
181d6902 | 1312 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
95ea3627 | 1313 | rt2x00_set_field32(&word, TXD_W0_ACK, |
181d6902 | 1314 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
95ea3627 | 1315 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
181d6902 | 1316 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
95ea3627 | 1317 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
076f9582 | 1318 | (txdesc->rate_mode == RATE_MODE_OFDM)); |
95ea3627 | 1319 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); |
2517794b | 1320 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); |
95ea3627 | 1321 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
61486e0f | 1322 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
df624ca5 | 1323 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); |
95ea3627 ID |
1324 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); |
1325 | rt2x00_desc_write(txd, 0, word); | |
85b7a8b3 GW |
1326 | |
1327 | /* | |
1328 | * Register descriptor details in skb frame descriptor. | |
1329 | */ | |
1330 | skbdesc->desc = txd; | |
1331 | skbdesc->desc_len = TXD_DESC_SIZE; | |
95ea3627 ID |
1332 | } |
1333 | ||
1334 | /* | |
1335 | * TX data initialization | |
1336 | */ | |
f224f4ef GW |
1337 | static void rt2500pci_write_beacon(struct queue_entry *entry, |
1338 | struct txentry_desc *txdesc) | |
bd88a781 ID |
1339 | { |
1340 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
bd88a781 ID |
1341 | u32 reg; |
1342 | ||
1343 | /* | |
1344 | * Disable beaconing while we are reloading the beacon data, | |
1345 | * otherwise we might be sending out invalid data. | |
1346 | */ | |
1347 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | |
bd88a781 ID |
1348 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); |
1349 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
1350 | ||
fa69560f | 1351 | rt2x00queue_map_txskb(entry); |
bd88a781 | 1352 | |
5c3b685c GW |
1353 | /* |
1354 | * Write the TX descriptor for the beacon. | |
1355 | */ | |
93331458 | 1356 | rt2500pci_write_tx_desc(entry, txdesc); |
5c3b685c GW |
1357 | |
1358 | /* | |
1359 | * Dump beacon to userspace through debugfs. | |
1360 | */ | |
1361 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
d61cb266 GW |
1362 | |
1363 | /* | |
1364 | * Enable beaconing again. | |
1365 | */ | |
d61cb266 GW |
1366 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); |
1367 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
bd88a781 ID |
1368 | } |
1369 | ||
95ea3627 ID |
1370 | /* |
1371 | * RX control handlers | |
1372 | */ | |
181d6902 ID |
1373 | static void rt2500pci_fill_rxdone(struct queue_entry *entry, |
1374 | struct rxdone_entry_desc *rxdesc) | |
95ea3627 | 1375 | { |
b8be63ff | 1376 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
95ea3627 ID |
1377 | u32 word0; |
1378 | u32 word2; | |
1379 | ||
b8be63ff ID |
1380 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
1381 | rt2x00_desc_read(entry_priv->desc, 2, &word2); | |
95ea3627 | 1382 | |
4150c572 | 1383 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 1384 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
4150c572 | 1385 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) |
181d6902 ID |
1386 | rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; |
1387 | ||
89993890 ID |
1388 | /* |
1389 | * Obtain the status about this packet. | |
1390 | * When frame was received with an OFDM bitrate, | |
1391 | * the signal is the PLCP value. If it was received with | |
1392 | * a CCK bitrate the signal is the rate in 100kbit/s. | |
1393 | */ | |
181d6902 ID |
1394 | rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); |
1395 | rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - | |
1396 | entry->queue->rt2x00dev->rssi_offset; | |
181d6902 | 1397 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 1398 | |
19d30e02 ID |
1399 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
1400 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | |
6c6aa3c0 ID |
1401 | else |
1402 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; | |
19d30e02 ID |
1403 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1404 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
95ea3627 ID |
1405 | } |
1406 | ||
1407 | /* | |
1408 | * Interrupt functions. | |
1409 | */ | |
181d6902 | 1410 | static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, |
e58c6aca | 1411 | const enum data_queue_qid queue_idx) |
95ea3627 | 1412 | { |
61c6e489 | 1413 | struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
b8be63ff | 1414 | struct queue_entry_priv_pci *entry_priv; |
181d6902 ID |
1415 | struct queue_entry *entry; |
1416 | struct txdone_entry_desc txdesc; | |
95ea3627 | 1417 | u32 word; |
95ea3627 | 1418 | |
181d6902 ID |
1419 | while (!rt2x00queue_empty(queue)) { |
1420 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); | |
b8be63ff ID |
1421 | entry_priv = entry->priv_data; |
1422 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 ID |
1423 | |
1424 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | |
1425 | !rt2x00_get_field32(word, TXD_W0_VALID)) | |
1426 | break; | |
1427 | ||
1428 | /* | |
1429 | * Obtain the status about this packet. | |
1430 | */ | |
fb55f4d1 ID |
1431 | txdesc.flags = 0; |
1432 | switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { | |
1433 | case 0: /* Success */ | |
1434 | case 1: /* Success with retry */ | |
1435 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | |
1436 | break; | |
1437 | case 2: /* Failure, excessive retries */ | |
1438 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); | |
1439 | /* Don't break, this is a failed frame! */ | |
1440 | default: /* Failure */ | |
1441 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | |
1442 | } | |
181d6902 | 1443 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); |
95ea3627 | 1444 | |
e513a0b6 | 1445 | rt2x00lib_txdone(entry, &txdesc); |
95ea3627 | 1446 | } |
95ea3627 ID |
1447 | } |
1448 | ||
7a5a681a HS |
1449 | static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, |
1450 | struct rt2x00_field32 irq_field) | |
95ea3627 | 1451 | { |
16222a0d | 1452 | u32 reg; |
95ea3627 ID |
1453 | |
1454 | /* | |
16222a0d HS |
1455 | * Enable a single interrupt. The interrupt mask register |
1456 | * access needs locking. | |
95ea3627 | 1457 | */ |
0aa13b2e | 1458 | spin_lock_irq(&rt2x00dev->irqmask_lock); |
95ea3627 | 1459 | |
16222a0d HS |
1460 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1461 | rt2x00_set_field32(®, irq_field, 0); | |
1462 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | |
95ea3627 | 1463 | |
0aa13b2e | 1464 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
16222a0d | 1465 | } |
95ea3627 | 1466 | |
16222a0d HS |
1467 | static void rt2500pci_txstatus_tasklet(unsigned long data) |
1468 | { | |
1469 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
1470 | u32 reg; | |
95ea3627 ID |
1471 | |
1472 | /* | |
16222a0d | 1473 | * Handle all tx queues. |
95ea3627 | 1474 | */ |
16222a0d HS |
1475 | rt2500pci_txdone(rt2x00dev, QID_ATIM); |
1476 | rt2500pci_txdone(rt2x00dev, QID_AC_VO); | |
1477 | rt2500pci_txdone(rt2x00dev, QID_AC_VI); | |
95ea3627 ID |
1478 | |
1479 | /* | |
16222a0d | 1480 | * Enable all TXDONE interrupts again. |
95ea3627 | 1481 | */ |
0aa13b2e | 1482 | spin_lock_irq(&rt2x00dev->irqmask_lock); |
95ea3627 | 1483 | |
16222a0d HS |
1484 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1485 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); | |
1486 | rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); | |
1487 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); | |
1488 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | |
78e256c9 | 1489 | |
0aa13b2e | 1490 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
16222a0d HS |
1491 | } |
1492 | ||
1493 | static void rt2500pci_tbtt_tasklet(unsigned long data) | |
1494 | { | |
1495 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
1496 | rt2x00lib_beacondone(rt2x00dev); | |
1497 | rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); | |
1498 | } | |
1499 | ||
1500 | static void rt2500pci_rxdone_tasklet(unsigned long data) | |
1501 | { | |
1502 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
16638937 HS |
1503 | if (rt2x00pci_rxdone(rt2x00dev)) |
1504 | tasklet_schedule(&rt2x00dev->rxdone_tasklet); | |
1505 | else | |
1506 | rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); | |
95ea3627 ID |
1507 | } |
1508 | ||
78e256c9 HS |
1509 | static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) |
1510 | { | |
1511 | struct rt2x00_dev *rt2x00dev = dev_instance; | |
16222a0d | 1512 | u32 reg, mask; |
78e256c9 HS |
1513 | |
1514 | /* | |
1515 | * Get the interrupt sources & saved to local variable. | |
1516 | * Write register value back to clear pending interrupts. | |
1517 | */ | |
1518 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); | |
1519 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); | |
1520 | ||
1521 | if (!reg) | |
1522 | return IRQ_NONE; | |
1523 | ||
1524 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) | |
1525 | return IRQ_HANDLED; | |
1526 | ||
16222a0d HS |
1527 | mask = reg; |
1528 | ||
1529 | /* | |
1530 | * Schedule tasklets for interrupt handling. | |
1531 | */ | |
1532 | if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) | |
1533 | tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); | |
1534 | ||
1535 | if (rt2x00_get_field32(reg, CSR7_RXDONE)) | |
1536 | tasklet_schedule(&rt2x00dev->rxdone_tasklet); | |
1537 | ||
1538 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || | |
1539 | rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || | |
1540 | rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { | |
1541 | tasklet_schedule(&rt2x00dev->txstatus_tasklet); | |
1542 | /* | |
1543 | * Mask out all txdone interrupts. | |
1544 | */ | |
1545 | rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); | |
1546 | rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); | |
1547 | rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); | |
1548 | } | |
1549 | ||
1550 | /* | |
1551 | * Disable all interrupts for which a tasklet was scheduled right now, | |
1552 | * the tasklet will reenable the appropriate interrupts. | |
1553 | */ | |
0aa13b2e | 1554 | spin_lock(&rt2x00dev->irqmask_lock); |
78e256c9 | 1555 | |
16222a0d HS |
1556 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1557 | reg |= mask; | |
1558 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | |
1559 | ||
0aa13b2e | 1560 | spin_unlock(&rt2x00dev->irqmask_lock); |
78e256c9 | 1561 | |
16222a0d | 1562 | return IRQ_HANDLED; |
78e256c9 HS |
1563 | } |
1564 | ||
95ea3627 ID |
1565 | /* |
1566 | * Device probe functions. | |
1567 | */ | |
1568 | static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
1569 | { | |
1570 | struct eeprom_93cx6 eeprom; | |
1571 | u32 reg; | |
1572 | u16 word; | |
1573 | u8 *mac; | |
1574 | ||
1575 | rt2x00pci_register_read(rt2x00dev, CSR21, ®); | |
1576 | ||
1577 | eeprom.data = rt2x00dev; | |
1578 | eeprom.register_read = rt2500pci_eepromregister_read; | |
1579 | eeprom.register_write = rt2500pci_eepromregister_write; | |
1580 | eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? | |
1581 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; | |
1582 | eeprom.reg_data_in = 0; | |
1583 | eeprom.reg_data_out = 0; | |
1584 | eeprom.reg_data_clock = 0; | |
1585 | eeprom.reg_chip_select = 0; | |
1586 | ||
1587 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, | |
1588 | EEPROM_SIZE / sizeof(u16)); | |
1589 | ||
1590 | /* | |
1591 | * Start validation of the data that has been read. | |
1592 | */ | |
1593 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1594 | if (!is_valid_ether_addr(mac)) { | |
1595 | random_ether_addr(mac); | |
e174961c | 1596 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
95ea3627 ID |
1597 | } |
1598 | ||
1599 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1600 | if (word == 0xffff) { | |
1601 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
362f3b6b ID |
1602 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
1603 | ANTENNA_SW_DIVERSITY); | |
1604 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, | |
1605 | ANTENNA_SW_DIVERSITY); | |
1606 | rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, | |
1607 | LED_MODE_DEFAULT); | |
95ea3627 ID |
1608 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); |
1609 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
1610 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522); | |
1611 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
1612 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); | |
1613 | } | |
1614 | ||
1615 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
1616 | if (word == 0xffff) { | |
1617 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); | |
1618 | rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0); | |
1619 | rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0); | |
1620 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
1621 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); | |
1622 | } | |
1623 | ||
1624 | rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word); | |
1625 | if (word == 0xffff) { | |
1626 | rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI, | |
1627 | DEFAULT_RSSI_OFFSET); | |
1628 | rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word); | |
1629 | EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word); | |
1630 | } | |
1631 | ||
1632 | return 0; | |
1633 | } | |
1634 | ||
1635 | static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1636 | { | |
1637 | u32 reg; | |
1638 | u16 value; | |
1639 | u16 eeprom; | |
1640 | ||
1641 | /* | |
1642 | * Read EEPROM word for configuration. | |
1643 | */ | |
1644 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1645 | ||
1646 | /* | |
1647 | * Identify RF chipset. | |
1648 | */ | |
1649 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
1650 | rt2x00pci_register_read(rt2x00dev, CSR0, ®); | |
49e721ec GW |
1651 | rt2x00_set_chip(rt2x00dev, RT2560, value, |
1652 | rt2x00_get_field32(reg, CSR0_REVISION)); | |
95ea3627 | 1653 | |
5122d898 GW |
1654 | if (!rt2x00_rf(rt2x00dev, RF2522) && |
1655 | !rt2x00_rf(rt2x00dev, RF2523) && | |
1656 | !rt2x00_rf(rt2x00dev, RF2524) && | |
1657 | !rt2x00_rf(rt2x00dev, RF2525) && | |
1658 | !rt2x00_rf(rt2x00dev, RF2525E) && | |
1659 | !rt2x00_rf(rt2x00dev, RF5222)) { | |
95ea3627 ID |
1660 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
1661 | return -ENODEV; | |
1662 | } | |
1663 | ||
1664 | /* | |
1665 | * Identify default antenna configuration. | |
1666 | */ | |
addc81bd | 1667 | rt2x00dev->default_ant.tx = |
95ea3627 | 1668 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 1669 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
1670 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
1671 | ||
1672 | /* | |
1673 | * Store led mode, for correct led behaviour. | |
1674 | */ | |
771fd565 | 1675 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a9450b70 ID |
1676 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); |
1677 | ||
475433be | 1678 | rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
3d3e451f ID |
1679 | if (value == LED_MODE_TXRX_ACTIVITY || |
1680 | value == LED_MODE_DEFAULT || | |
1681 | value == LED_MODE_ASUS) | |
475433be ID |
1682 | rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual, |
1683 | LED_TYPE_ACTIVITY); | |
771fd565 | 1684 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
1685 | |
1686 | /* | |
1687 | * Detect if this device has an hardware controlled radio. | |
1688 | */ | |
1689 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) | |
7dab73b3 | 1690 | __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); |
95ea3627 ID |
1691 | |
1692 | /* | |
1693 | * Check if the BBP tuning should be enabled. | |
1694 | */ | |
1695 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
27df2a9c | 1696 | if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE)) |
7dab73b3 | 1697 | __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); |
95ea3627 ID |
1698 | |
1699 | /* | |
1700 | * Read the RSSI <-> dBm offset information. | |
1701 | */ | |
1702 | rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom); | |
1703 | rt2x00dev->rssi_offset = | |
1704 | rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI); | |
1705 | ||
1706 | return 0; | |
1707 | } | |
1708 | ||
1709 | /* | |
1710 | * RF value list for RF2522 | |
1711 | * Supports: 2.4 GHz | |
1712 | */ | |
1713 | static const struct rf_channel rf_vals_bg_2522[] = { | |
1714 | { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 }, | |
1715 | { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 }, | |
1716 | { 3, 0x00002050, 0x000c2002, 0x00000101, 0 }, | |
1717 | { 4, 0x00002050, 0x000c2016, 0x00000101, 0 }, | |
1718 | { 5, 0x00002050, 0x000c202a, 0x00000101, 0 }, | |
1719 | { 6, 0x00002050, 0x000c203e, 0x00000101, 0 }, | |
1720 | { 7, 0x00002050, 0x000c2052, 0x00000101, 0 }, | |
1721 | { 8, 0x00002050, 0x000c2066, 0x00000101, 0 }, | |
1722 | { 9, 0x00002050, 0x000c207a, 0x00000101, 0 }, | |
1723 | { 10, 0x00002050, 0x000c208e, 0x00000101, 0 }, | |
1724 | { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 }, | |
1725 | { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 }, | |
1726 | { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 }, | |
1727 | { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 }, | |
1728 | }; | |
1729 | ||
1730 | /* | |
1731 | * RF value list for RF2523 | |
1732 | * Supports: 2.4 GHz | |
1733 | */ | |
1734 | static const struct rf_channel rf_vals_bg_2523[] = { | |
1735 | { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b }, | |
1736 | { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b }, | |
1737 | { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b }, | |
1738 | { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b }, | |
1739 | { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b }, | |
1740 | { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b }, | |
1741 | { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b }, | |
1742 | { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b }, | |
1743 | { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b }, | |
1744 | { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b }, | |
1745 | { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b }, | |
1746 | { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b }, | |
1747 | { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b }, | |
1748 | { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 }, | |
1749 | }; | |
1750 | ||
1751 | /* | |
1752 | * RF value list for RF2524 | |
1753 | * Supports: 2.4 GHz | |
1754 | */ | |
1755 | static const struct rf_channel rf_vals_bg_2524[] = { | |
1756 | { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b }, | |
1757 | { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b }, | |
1758 | { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b }, | |
1759 | { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b }, | |
1760 | { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b }, | |
1761 | { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b }, | |
1762 | { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b }, | |
1763 | { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b }, | |
1764 | { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b }, | |
1765 | { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b }, | |
1766 | { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b }, | |
1767 | { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b }, | |
1768 | { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b }, | |
1769 | { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 }, | |
1770 | }; | |
1771 | ||
1772 | /* | |
1773 | * RF value list for RF2525 | |
1774 | * Supports: 2.4 GHz | |
1775 | */ | |
1776 | static const struct rf_channel rf_vals_bg_2525[] = { | |
1777 | { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b }, | |
1778 | { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b }, | |
1779 | { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b }, | |
1780 | { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b }, | |
1781 | { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b }, | |
1782 | { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b }, | |
1783 | { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b }, | |
1784 | { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b }, | |
1785 | { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b }, | |
1786 | { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b }, | |
1787 | { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b }, | |
1788 | { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b }, | |
1789 | { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b }, | |
1790 | { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 }, | |
1791 | }; | |
1792 | ||
1793 | /* | |
1794 | * RF value list for RF2525e | |
1795 | * Supports: 2.4 GHz | |
1796 | */ | |
1797 | static const struct rf_channel rf_vals_bg_2525e[] = { | |
1798 | { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b }, | |
1799 | { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b }, | |
1800 | { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b }, | |
1801 | { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b }, | |
1802 | { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b }, | |
1803 | { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b }, | |
1804 | { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b }, | |
1805 | { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b }, | |
1806 | { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b }, | |
1807 | { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b }, | |
1808 | { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b }, | |
1809 | { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b }, | |
1810 | { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b }, | |
1811 | { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b }, | |
1812 | }; | |
1813 | ||
1814 | /* | |
1815 | * RF value list for RF5222 | |
1816 | * Supports: 2.4 GHz & 5.2 GHz | |
1817 | */ | |
1818 | static const struct rf_channel rf_vals_5222[] = { | |
1819 | { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b }, | |
1820 | { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b }, | |
1821 | { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b }, | |
1822 | { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b }, | |
1823 | { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b }, | |
1824 | { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b }, | |
1825 | { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b }, | |
1826 | { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b }, | |
1827 | { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b }, | |
1828 | { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b }, | |
1829 | { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b }, | |
1830 | { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b }, | |
1831 | { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b }, | |
1832 | { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b }, | |
1833 | ||
1834 | /* 802.11 UNI / HyperLan 2 */ | |
1835 | { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f }, | |
1836 | { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f }, | |
1837 | { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f }, | |
1838 | { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f }, | |
1839 | { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f }, | |
1840 | { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f }, | |
1841 | { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f }, | |
1842 | { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f }, | |
1843 | ||
1844 | /* 802.11 HyperLan 2 */ | |
1845 | { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f }, | |
1846 | { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f }, | |
1847 | { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f }, | |
1848 | { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f }, | |
1849 | { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f }, | |
1850 | { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f }, | |
1851 | { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f }, | |
1852 | { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f }, | |
1853 | { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f }, | |
1854 | { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f }, | |
1855 | ||
1856 | /* 802.11 UNII */ | |
1857 | { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f }, | |
1858 | { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 }, | |
1859 | { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 }, | |
1860 | { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 }, | |
1861 | { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 }, | |
1862 | }; | |
1863 | ||
8c5e7a5f | 1864 | static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1865 | { |
1866 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
1867 | struct channel_info *info; |
1868 | char *tx_power; | |
95ea3627 ID |
1869 | unsigned int i; |
1870 | ||
1871 | /* | |
1872 | * Initialize all hw fields. | |
1873 | */ | |
566bfe5a | 1874 | rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
4be8c387 JB |
1875 | IEEE80211_HW_SIGNAL_DBM | |
1876 | IEEE80211_HW_SUPPORTS_PS | | |
1877 | IEEE80211_HW_PS_NULLFUNC_STACK; | |
566bfe5a | 1878 | |
14a3bf89 | 1879 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
1880 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
1881 | rt2x00_eeprom_addr(rt2x00dev, | |
1882 | EEPROM_MAC_ADDR_0)); | |
1883 | ||
95ea3627 ID |
1884 | /* |
1885 | * Initialize hw_mode information. | |
1886 | */ | |
31562e80 ID |
1887 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
1888 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
95ea3627 | 1889 | |
5122d898 | 1890 | if (rt2x00_rf(rt2x00dev, RF2522)) { |
95ea3627 ID |
1891 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522); |
1892 | spec->channels = rf_vals_bg_2522; | |
5122d898 | 1893 | } else if (rt2x00_rf(rt2x00dev, RF2523)) { |
95ea3627 ID |
1894 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523); |
1895 | spec->channels = rf_vals_bg_2523; | |
5122d898 | 1896 | } else if (rt2x00_rf(rt2x00dev, RF2524)) { |
95ea3627 ID |
1897 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524); |
1898 | spec->channels = rf_vals_bg_2524; | |
5122d898 | 1899 | } else if (rt2x00_rf(rt2x00dev, RF2525)) { |
95ea3627 ID |
1900 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525); |
1901 | spec->channels = rf_vals_bg_2525; | |
5122d898 | 1902 | } else if (rt2x00_rf(rt2x00dev, RF2525E)) { |
95ea3627 ID |
1903 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e); |
1904 | spec->channels = rf_vals_bg_2525e; | |
5122d898 | 1905 | } else if (rt2x00_rf(rt2x00dev, RF5222)) { |
31562e80 | 1906 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
1907 | spec->num_channels = ARRAY_SIZE(rf_vals_5222); |
1908 | spec->channels = rf_vals_5222; | |
95ea3627 | 1909 | } |
8c5e7a5f ID |
1910 | |
1911 | /* | |
1912 | * Create channel information array | |
1913 | */ | |
baeb2ffa | 1914 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
8c5e7a5f ID |
1915 | if (!info) |
1916 | return -ENOMEM; | |
1917 | ||
1918 | spec->channels_info = info; | |
1919 | ||
1920 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); | |
8d1331b3 ID |
1921 | for (i = 0; i < 14; i++) { |
1922 | info[i].max_power = MAX_TXPOWER; | |
1923 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
1924 | } | |
8c5e7a5f ID |
1925 | |
1926 | if (spec->num_channels > 14) { | |
8d1331b3 ID |
1927 | for (i = 14; i < spec->num_channels; i++) { |
1928 | info[i].max_power = MAX_TXPOWER; | |
1929 | info[i].default_power1 = DEFAULT_TXPOWER; | |
1930 | } | |
8c5e7a5f ID |
1931 | } |
1932 | ||
1933 | return 0; | |
95ea3627 ID |
1934 | } |
1935 | ||
1936 | static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |
1937 | { | |
1938 | int retval; | |
1939 | ||
1940 | /* | |
1941 | * Allocate eeprom data. | |
1942 | */ | |
1943 | retval = rt2500pci_validate_eeprom(rt2x00dev); | |
1944 | if (retval) | |
1945 | return retval; | |
1946 | ||
1947 | retval = rt2500pci_init_eeprom(rt2x00dev); | |
1948 | if (retval) | |
1949 | return retval; | |
1950 | ||
1951 | /* | |
1952 | * Initialize hw specifications. | |
1953 | */ | |
8c5e7a5f ID |
1954 | retval = rt2500pci_probe_hw_mode(rt2x00dev); |
1955 | if (retval) | |
1956 | return retval; | |
95ea3627 ID |
1957 | |
1958 | /* | |
c4da0048 | 1959 | * This device requires the atim queue and DMA-mapped skbs. |
95ea3627 | 1960 | */ |
7dab73b3 ID |
1961 | __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); |
1962 | __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); | |
1963 | __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags); | |
95ea3627 ID |
1964 | |
1965 | /* | |
1966 | * Set the rssi offset. | |
1967 | */ | |
1968 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
1969 | ||
1970 | return 0; | |
1971 | } | |
1972 | ||
1973 | /* | |
1974 | * IEEE80211 stack callback functions. | |
1975 | */ | |
95ea3627 ID |
1976 | static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw) |
1977 | { | |
1978 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1979 | u64 tsf; | |
1980 | u32 reg; | |
1981 | ||
1982 | rt2x00pci_register_read(rt2x00dev, CSR17, ®); | |
1983 | tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; | |
1984 | rt2x00pci_register_read(rt2x00dev, CSR16, ®); | |
1985 | tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); | |
1986 | ||
1987 | return tsf; | |
1988 | } | |
1989 | ||
95ea3627 ID |
1990 | static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw) |
1991 | { | |
1992 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1993 | u32 reg; | |
1994 | ||
1995 | rt2x00pci_register_read(rt2x00dev, CSR15, ®); | |
1996 | return rt2x00_get_field32(reg, CSR15_BEACON_SENT); | |
1997 | } | |
1998 | ||
1999 | static const struct ieee80211_ops rt2500pci_mac80211_ops = { | |
2000 | .tx = rt2x00mac_tx, | |
4150c572 JB |
2001 | .start = rt2x00mac_start, |
2002 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
2003 | .add_interface = rt2x00mac_add_interface, |
2004 | .remove_interface = rt2x00mac_remove_interface, | |
2005 | .config = rt2x00mac_config, | |
3a643d24 | 2006 | .configure_filter = rt2x00mac_configure_filter, |
d8147f9d ID |
2007 | .sw_scan_start = rt2x00mac_sw_scan_start, |
2008 | .sw_scan_complete = rt2x00mac_sw_scan_complete, | |
95ea3627 | 2009 | .get_stats = rt2x00mac_get_stats, |
471b3efd | 2010 | .bss_info_changed = rt2x00mac_bss_info_changed, |
95ea3627 | 2011 | .conf_tx = rt2x00mac_conf_tx, |
95ea3627 | 2012 | .get_tsf = rt2500pci_get_tsf, |
95ea3627 | 2013 | .tx_last_beacon = rt2500pci_tx_last_beacon, |
e47a5cdd | 2014 | .rfkill_poll = rt2x00mac_rfkill_poll, |
f44df18c | 2015 | .flush = rt2x00mac_flush, |
0ed7b3c0 ID |
2016 | .set_antenna = rt2x00mac_set_antenna, |
2017 | .get_antenna = rt2x00mac_get_antenna, | |
e7dee444 | 2018 | .get_ringparam = rt2x00mac_get_ringparam, |
5f0dd296 | 2019 | .tx_frames_pending = rt2x00mac_tx_frames_pending, |
95ea3627 ID |
2020 | }; |
2021 | ||
2022 | static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { | |
2023 | .irq_handler = rt2500pci_interrupt, | |
16222a0d HS |
2024 | .txstatus_tasklet = rt2500pci_txstatus_tasklet, |
2025 | .tbtt_tasklet = rt2500pci_tbtt_tasklet, | |
2026 | .rxdone_tasklet = rt2500pci_rxdone_tasklet, | |
95ea3627 ID |
2027 | .probe_hw = rt2500pci_probe_hw, |
2028 | .initialize = rt2x00pci_initialize, | |
2029 | .uninitialize = rt2x00pci_uninitialize, | |
798b7adb ID |
2030 | .get_entry_state = rt2500pci_get_entry_state, |
2031 | .clear_entry = rt2500pci_clear_entry, | |
95ea3627 | 2032 | .set_device_state = rt2500pci_set_device_state, |
95ea3627 | 2033 | .rfkill_poll = rt2500pci_rfkill_poll, |
95ea3627 ID |
2034 | .link_stats = rt2500pci_link_stats, |
2035 | .reset_tuner = rt2500pci_reset_tuner, | |
2036 | .link_tuner = rt2500pci_link_tuner, | |
dbba306f ID |
2037 | .start_queue = rt2500pci_start_queue, |
2038 | .kick_queue = rt2500pci_kick_queue, | |
2039 | .stop_queue = rt2500pci_stop_queue, | |
152a5992 | 2040 | .flush_queue = rt2x00pci_flush_queue, |
95ea3627 | 2041 | .write_tx_desc = rt2500pci_write_tx_desc, |
bd88a781 | 2042 | .write_beacon = rt2500pci_write_beacon, |
95ea3627 | 2043 | .fill_rxdone = rt2500pci_fill_rxdone, |
3a643d24 | 2044 | .config_filter = rt2500pci_config_filter, |
6bb40dd1 | 2045 | .config_intf = rt2500pci_config_intf, |
72810379 | 2046 | .config_erp = rt2500pci_config_erp, |
e4ea1c40 | 2047 | .config_ant = rt2500pci_config_ant, |
95ea3627 ID |
2048 | .config = rt2500pci_config, |
2049 | }; | |
2050 | ||
181d6902 | 2051 | static const struct data_queue_desc rt2500pci_queue_rx = { |
efd2f271 | 2052 | .entry_num = 32, |
181d6902 ID |
2053 | .data_size = DATA_FRAME_SIZE, |
2054 | .desc_size = RXD_DESC_SIZE, | |
b8be63ff | 2055 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
2056 | }; |
2057 | ||
2058 | static const struct data_queue_desc rt2500pci_queue_tx = { | |
efd2f271 | 2059 | .entry_num = 32, |
181d6902 ID |
2060 | .data_size = DATA_FRAME_SIZE, |
2061 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 2062 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
2063 | }; |
2064 | ||
2065 | static const struct data_queue_desc rt2500pci_queue_bcn = { | |
efd2f271 | 2066 | .entry_num = 1, |
181d6902 ID |
2067 | .data_size = MGMT_FRAME_SIZE, |
2068 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 2069 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
2070 | }; |
2071 | ||
2072 | static const struct data_queue_desc rt2500pci_queue_atim = { | |
efd2f271 | 2073 | .entry_num = 8, |
181d6902 ID |
2074 | .data_size = DATA_FRAME_SIZE, |
2075 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 2076 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
2077 | }; |
2078 | ||
95ea3627 | 2079 | static const struct rt2x00_ops rt2500pci_ops = { |
04d0362e GW |
2080 | .name = KBUILD_MODNAME, |
2081 | .max_sta_intf = 1, | |
2082 | .max_ap_intf = 1, | |
2083 | .eeprom_size = EEPROM_SIZE, | |
2084 | .rf_size = RF_SIZE, | |
2085 | .tx_queues = NUM_TX_QUEUES, | |
e6218cc4 | 2086 | .extra_tx_headroom = 0, |
04d0362e GW |
2087 | .rx = &rt2500pci_queue_rx, |
2088 | .tx = &rt2500pci_queue_tx, | |
2089 | .bcn = &rt2500pci_queue_bcn, | |
2090 | .atim = &rt2500pci_queue_atim, | |
2091 | .lib = &rt2500pci_rt2x00_ops, | |
2092 | .hw = &rt2500pci_mac80211_ops, | |
95ea3627 | 2093 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
04d0362e | 2094 | .debugfs = &rt2500pci_rt2x00debug, |
95ea3627 ID |
2095 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
2096 | }; | |
2097 | ||
2098 | /* | |
2099 | * RT2500pci module information. | |
2100 | */ | |
a3aa1884 | 2101 | static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = { |
e01ae27f | 2102 | { PCI_DEVICE(0x1814, 0x0201) }, |
95ea3627 ID |
2103 | { 0, } |
2104 | }; | |
2105 | ||
2106 | MODULE_AUTHOR(DRV_PROJECT); | |
2107 | MODULE_VERSION(DRV_VERSION); | |
2108 | MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver."); | |
2109 | MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards"); | |
2110 | MODULE_DEVICE_TABLE(pci, rt2500pci_device_table); | |
2111 | MODULE_LICENSE("GPL"); | |
2112 | ||
e01ae27f GW |
2113 | static int rt2500pci_probe(struct pci_dev *pci_dev, |
2114 | const struct pci_device_id *id) | |
2115 | { | |
2116 | return rt2x00pci_probe(pci_dev, &rt2500pci_ops); | |
2117 | } | |
2118 | ||
95ea3627 | 2119 | static struct pci_driver rt2500pci_driver = { |
2360157c | 2120 | .name = KBUILD_MODNAME, |
95ea3627 | 2121 | .id_table = rt2500pci_device_table, |
e01ae27f | 2122 | .probe = rt2500pci_probe, |
95ea3627 ID |
2123 | .remove = __devexit_p(rt2x00pci_remove), |
2124 | .suspend = rt2x00pci_suspend, | |
2125 | .resume = rt2x00pci_resume, | |
2126 | }; | |
2127 | ||
2128 | static int __init rt2500pci_init(void) | |
2129 | { | |
2130 | return pci_register_driver(&rt2500pci_driver); | |
2131 | } | |
2132 | ||
2133 | static void __exit rt2500pci_exit(void) | |
2134 | { | |
2135 | pci_unregister_driver(&rt2500pci_driver); | |
2136 | } | |
2137 | ||
2138 | module_init(rt2500pci_init); | |
2139 | module_exit(rt2500pci_exit); |