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wifi: rtw89: refine scan function after chanctx
[linux-block.git] / drivers / net / wireless / realtek / rtw89 / fw.h
CommitLineData
e3ec7017
PKS		 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_FW_H__
6#define __RTW89_FW_H__
7
8#include "core.h"
9
10enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19};
20
21#define RTW89_GET_C2H_HDR_FUNC(info) \
22 u32_get_bits(info, GENMASK(6, 0))
23#define RTW89_GET_C2H_HDR_LEN(info) \
24 u32_get_bits(info, GENMASK(11, 8))
25
26#define RTW89_SET_H2CREG_HDR_FUNC(info, val) \
27 u32p_replace_bits(info, val, GENMASK(6, 0))
28#define RTW89_SET_H2CREG_HDR_LEN(info, val) \
29 u32p_replace_bits(info, val, GENMASK(11, 8))
30
31#define RTW89_H2CREG_MAX 4
32#define RTW89_C2HREG_MAX 4
33#define RTW89_C2HREG_HDR_LEN 2
34#define RTW89_H2CREG_HDR_LEN 2
35#define RTW89_C2H_TIMEOUT 1000000
36struct rtw89_mac_c2h_info {
37 u8 id;
38 u8 content_len;
39 u32 c2hreg[RTW89_C2HREG_MAX];
40};
41
42struct rtw89_mac_h2c_info {
43 u8 id;
44 u8 content_len;
45 u32 h2creg[RTW89_H2CREG_MAX];
46};
47
48enum rtw89_mac_h2c_type {
49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
51 RTW89_FWCMD_H2CREG_FUNC_FWERR,
52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN
55};
56
57enum rtw89_mac_c2h_type {
58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
64};
65
c7ad08c6
PKS		 66#define RTW89_GET_C2H_PHYCAP_FUNC(info) \
67 u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0))
68#define RTW89_GET_C2H_PHYCAP_ACK(info) \
69 u32_get_bits(*((const u32 *)(info)), BIT(7))
70#define RTW89_GET_C2H_PHYCAP_LEN(info) \
71 u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8))
72#define RTW89_GET_C2H_PHYCAP_SEQ(info) \
73 u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12))
74#define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \
75 u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16))
76#define RTW89_GET_C2H_PHYCAP_BW(info) \
77 u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24))
78#define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \
79 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0))
80#define RTW89_GET_C2H_PHYCAP_PROT(info) \
81 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8))
82#define RTW89_GET_C2H_PHYCAP_NIC(info) \
83 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16))
84#define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \
85 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24))
86#define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \
87 u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0))
88#define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \
89 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8))
90#define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \
91 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16))
e3ec7017
PKS		 92
93enum rtw89_fw_c2h_category {
94 RTW89_C2H_CAT_TEST,
95 RTW89_C2H_CAT_MAC,
96 RTW89_C2H_CAT_OUTSRC,
97};
98
99enum rtw89_fw_log_level {
100 RTW89_FW_LOG_LEVEL_OFF,
101 RTW89_FW_LOG_LEVEL_CRT,
102 RTW89_FW_LOG_LEVEL_SER,
103 RTW89_FW_LOG_LEVEL_WARN,
104 RTW89_FW_LOG_LEVEL_LOUD,
105 RTW89_FW_LOG_LEVEL_TR,
106};
107
108enum rtw89_fw_log_path {
109 RTW89_FW_LOG_LEVEL_UART,
110 RTW89_FW_LOG_LEVEL_C2H,
111 RTW89_FW_LOG_LEVEL_SNI,
112};
113
114enum rtw89_fw_log_comp {
115 RTW89_FW_LOG_COMP_VER,
116 RTW89_FW_LOG_COMP_INIT,
117 RTW89_FW_LOG_COMP_TASK,
118 RTW89_FW_LOG_COMP_CNS,
119 RTW89_FW_LOG_COMP_H2C,
120 RTW89_FW_LOG_COMP_C2H,
121 RTW89_FW_LOG_COMP_TX,
122 RTW89_FW_LOG_COMP_RX,
123 RTW89_FW_LOG_COMP_IPSEC,
124 RTW89_FW_LOG_COMP_TIMER,
125 RTW89_FW_LOG_COMP_DBGPKT,
126 RTW89_FW_LOG_COMP_PS,
127 RTW89_FW_LOG_COMP_ERROR,
128 RTW89_FW_LOG_COMP_WOWLAN,
129 RTW89_FW_LOG_COMP_SECURE_BOOT,
130 RTW89_FW_LOG_COMP_BTC,
131 RTW89_FW_LOG_COMP_BB,
132 RTW89_FW_LOG_COMP_TWT,
133 RTW89_FW_LOG_COMP_RF,
134 RTW89_FW_LOG_COMP_MCC = 20,
135};
136
89590777
PHH		 137enum rtw89_pkt_offload_op {
138 RTW89_PKT_OFLD_OP_ADD,
139 RTW89_PKT_OFLD_OP_DEL,
140 RTW89_PKT_OFLD_OP_READ,
141};
142
143enum rtw89_scanofld_notify_reason {
144 RTW89_SCAN_DWELL_NOTIFY,
145 RTW89_SCAN_PRE_TX_NOTIFY,
146 RTW89_SCAN_POST_TX_NOTIFY,
147 RTW89_SCAN_ENTER_CH_NOTIFY,
148 RTW89_SCAN_LEAVE_CH_NOTIFY,
149 RTW89_SCAN_END_SCAN_NOTIFY,
150};
151
152enum rtw89_chan_type {
153 RTW89_CHAN_OPERATE = 0,
154 RTW89_CHAN_ACTIVE,
155 RTW89_CHAN_DFS,
156};
157
f4a43c3b
DSY		 158enum rtw89_p2pps_action {
159 RTW89_P2P_ACT_INIT = 0,
160 RTW89_P2P_ACT_UPDATE = 1,
161 RTW89_P2P_ACT_REMOVE = 2,
162 RTW89_P2P_ACT_TERMINATE = 3,
163};
164
d2b6da24
PHH		 165enum rtw89_bcn_fltr_offload_mode {
166 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
167 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
168 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
169 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
170
171 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
172};
173
174enum rtw89_bcn_fltr_type {
175 RTW89_BCN_FLTR_BEACON_LOSS,
176 RTW89_BCN_FLTR_RSSI,
177 RTW89_BCN_FLTR_NOTIFY,
178};
179
180enum rtw89_bcn_fltr_rssi_event {
181 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
182 RTW89_BCN_FLTR_RSSI_HIGH,
183 RTW89_BCN_FLTR_RSSI_LOW,
184};
185
e3ec7017
PKS		 186#define FWDL_SECTION_MAX_NUM 10
187#define FWDL_SECTION_CHKSUM_LEN 8
188#define FWDL_SECTION_PER_PKT_LEN 2020
189
190struct rtw89_fw_hdr_section_info {
191 u8 redl;
192 const u8 *addr;
193 u32 len;
194 u32 dladdr;
18ddf102
PKS		 195 u32 mssc;
196 u8 type;
e3ec7017
PKS		 197};
198
199struct rtw89_fw_bin_info {
200 u8 section_num;
201 u32 hdr_len;
4feda7f3
PKS		 202 bool dynamic_hdr_en;
203 u32 dynamic_hdr_len;
e3ec7017
PKS		 204 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
205};
206
207struct rtw89_fw_macid_pause_grp {
208 __le32 pause_grp[4];
209 __le32 mask_grp[4];
210} __packed;
211
212struct rtw89_h2creg_sch_tx_en {
213 u8 func:7;
214 u8 ack:1;
215 u8 total_len:4;
216 u8 seq_num:4;
217 u16 tx_en:16;
218 u16 mask:16;
219 u8 band:1;
220 u16 rsvd:15;
221} __packed;
222
bd1056d4 223#define RTW89_H2C_MAX_SIZE 2048
89590777 224#define RTW89_CHANNEL_TIME 45
54997c24 225#define RTW89_CHANNEL_TIME_6G 20
89590777
PHH		 226#define RTW89_DFS_CHAN_TIME 105
227#define RTW89_OFF_CHAN_TIME 100
228#define RTW89_DWELL_TIME 20
08c93c0c 229#define RTW89_DWELL_TIME_6G 10
89590777
PHH		 230#define RTW89_SCAN_WIDTH 0
231#define RTW89_SCANOFLD_MAX_SSID 8
232#define RTW89_SCANOFLD_MAX_IE_LEN 512
233#define RTW89_SCANOFLD_PKT_NONE 0xFF
234#define RTW89_SCANOFLD_DEBUG_MASK 0x1F
3a1e7cb1 235#define RTW89_MAC_CHINFO_SIZE 24
bd1056d4
PHH		 236#define RTW89_SCAN_LIST_GUARD 4
237#define RTW89_SCAN_LIST_LIMIT \
238 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
89590777 239
d2b6da24
PHH		 240#define RTW89_BCN_LOSS_CNT 10
241
89590777
PHH		 242struct rtw89_mac_chinfo {
243 u8 period;
244 u8 dwell_time;
245 u8 central_ch;
246 u8 pri_ch;
247 u8 bw:3;
248 u8 notify_action:5;
249 u8 num_pkt:4;
250 u8 tx_pkt:1;
251 u8 pause_data:1;
252 u8 ch_band:2;
253 u8 probe_id;
254 u8 dfs_ch:1;
255 u8 tx_null:1;
256 u8 rand_seq_num:1;
257 u8 cfg_tx_pwr:1;
258 u8 rsvd0: 4;
259 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
260 u16 tx_pwr_idx;
261 u8 rsvd1;
262 struct list_head list;
c6aa9a9c 263 bool is_psc;
89590777
PHH		 264};
265
266struct rtw89_scan_option {
267 bool enable;
268 bool target_ch_mode;
269};
270
271struct rtw89_pktofld_info {
272 struct list_head list;
273 u8 id;
c6aa9a9c
PHH		 274
275 /* Below fields are for 6 GHz RNR use only */
276 u8 ssid[IEEE80211_MAX_SSID_LEN];
277 u8 ssid_len;
278 u8 bssid[ETH_ALEN];
279 u16 channel_6ghz;
89590777
PHH		 280};
281
00224aa7
PKS		 282static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val)
283{
284 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0));
285}
286
287static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val)
288{
289 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1));
290}
291
292static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val)
293{
294 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6));
295}
296
297static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val)
298{
299 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
300}
301
302static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val)
303{
304 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16));
305}
306
307static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val)
308{
309 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17));
310}
311
312static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val)
313{
314 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18));
315}
316
317static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val)
318{
319 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20));
320}
321
322static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val)
323{
324 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21));
325}
326
327static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val)
328{
329 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22));
330}
331
332static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val)
333{
334 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23));
335}
336
337static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val)
338{
339 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24));
340}
341
342static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val)
343{
344 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27));
345}
346
347static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val)
348{
349 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30));
350}
351
352static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val)
353{
354 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31));
355}
356
357static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val)
358{
359 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0));
360}
361
362static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val)
363{
364 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8));
365}
366
367static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val)
368{
369 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16));
370}
371
372static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val)
373{
374 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24));
375}
376
377static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val)
378{
379 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0));
380}
381
382static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val)
383{
384 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31));
385}
386
387static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val)
388{
389 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0));
390}
391
392static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val)
393{
394 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8));
395}
396
397static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val)
398{
399 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9));
400}
401
402static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val)
403{
404 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10));
405}
406
0891b366
KCC		 407static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val)
408{
409 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11));
410}
411
412static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val)
413{
414 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12));
415}
416
00224aa7
PKS		 417static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val)
418{
419 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16));
420}
421
422static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val)
423{
424 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24));
425}
426
427static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val)
428{
429 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26));
430}
431
432static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val)
433{
434 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29));
435}
436
437static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
438{
439 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
440}
441
442static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
443{
444 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
445}
446
447static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
448{
449 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
450}
451
452static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
453{
454 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
455}
456
457static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
458{
459 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
460}
461
462static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
463{
464 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
465}
466
467static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
468{
469 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
470}
471
472static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
473{
474 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
475}
476
477static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
478{
479 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
480}
481
482static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
483{
484 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
485}
486
487static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
488{
489 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
490}
491
492static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
493{
494 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
495}
496
497static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
498{
499 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
500}
501
502static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
503{
504 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
505}
506
507static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
508{
509 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
510}
e3ec7017
PKS		 511#define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
512#define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
513#define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
514#define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
515
18ddf102
PKS		 516#define FWDL_SECURITY_SECTION_TYPE 9
517#define FWDL_SECURITY_SIGLEN 512
518
519#define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \
520 le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0))
521#define GET_FWSECTION_HDR_SECTIONTYPE(fwhdr) \
522 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(27, 24))
e3ec7017 523#define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \
321e763c 524 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0))
e3ec7017 525#define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \
321e763c 526 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28))
e3ec7017 527#define GET_FWSECTION_HDR_REDL(fwhdr) \
321e763c 528 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29))
18ddf102
PKS		 529#define GET_FWSECTION_HDR_MSSC(fwhdr) \
530 le32_get_bits(*((const __le32 *)(fwhdr) + 2), GENMASK(31, 0))
e3ec7017
PKS		 531
532#define GET_FW_HDR_MAJOR_VERSION(fwhdr) \
321e763c 533 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0))
e3ec7017 534#define GET_FW_HDR_MINOR_VERSION(fwhdr) \
321e763c 535 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8))
e3ec7017 536#define GET_FW_HDR_SUBVERSION(fwhdr) \
321e763c 537 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16))
e3ec7017 538#define GET_FW_HDR_SUBINDEX(fwhdr) \
321e763c 539 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24))
4feda7f3
PKS		 540#define GET_FW_HDR_LEN(fwhdr) \
541 le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16))
e3ec7017 542#define GET_FW_HDR_MONTH(fwhdr) \
321e763c 543 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0))
e3ec7017 544#define GET_FW_HDR_DATE(fwhdr) \
321e763c 545 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8))
e3ec7017 546#define GET_FW_HDR_HOUR(fwhdr) \
321e763c 547 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16))
e3ec7017 548#define GET_FW_HDR_MIN(fwhdr) \
321e763c 549 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24))
e3ec7017 550#define GET_FW_HDR_YEAR(fwhdr) \
321e763c 551 le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0))
e3ec7017 552#define GET_FW_HDR_SEC_NUM(fwhdr) \
321e763c 553 le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8))
4feda7f3
PKS		 554#define GET_FW_HDR_DYN_HDR(fwhdr) \
555 le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16))
e3ec7017 556#define GET_FW_HDR_CMD_VERSERION(fwhdr) \
321e763c 557 le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24))
4feda7f3
PKS		 558
559#define GET_FW_DYNHDR_LEN(fwdynhdr) \
560 le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0))
561#define GET_FW_DYNHDR_COUNT(fwdynhdr) \
562 le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0))
563
5737b451
PKS		 564static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
565{
566 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
567}
e3ec7017 568
00224aa7
PKS		 569static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
570{
571 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
572}
573
574static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
575{
576 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
577}
e3ec7017 578#define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
00224aa7
PKS		 579static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
580{
581 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
582 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
583 GENMASK(8, 0));
584}
e3ec7017 585#define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
00224aa7
PKS		 586static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
587{
588 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
589 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
590 BIT(9));
591}
e3ec7017 592#define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
00224aa7
PKS		 593static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
594{
595 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
596 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
597 GENMASK(11, 10));
598}
e3ec7017 599#define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
00224aa7
PKS		 600static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
601{
602 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
603 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
604 GENMASK(14, 12));
605}
e3ec7017 606#define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
00224aa7
PKS		 607static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
608{
609 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
610 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
611 BIT(15));
612}
e3ec7017 613#define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
00224aa7
PKS		 614static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
615{
616 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
617 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
618 GENMASK(19, 16));
619}
e3ec7017 620#define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
00224aa7
PKS		 621static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
622{
623 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
624 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
625 BIT(20));
626}
e3ec7017 627#define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
00224aa7
PKS		 628static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
629{
630 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
631 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
632 BIT(21));
633}
e3ec7017 634#define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
00224aa7
PKS		 635static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
636{
637 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
638 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
639 BIT(22));
640}
e3ec7017 641#define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
00224aa7
PKS		 642static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
643{
644 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
645 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
646 BIT(23));
647}
e3ec7017 648#define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
00224aa7
PKS		 649static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
650{
651 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
652 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
653 BIT(25));
654}
e3ec7017 655#define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
00224aa7
PKS		 656static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
657{
658 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
659 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
660 BIT(26));
661}
e3ec7017 662#define SET_CMC_TBL_MASK_TRYRATE BIT(0)
00224aa7
PKS		 663static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
664{
665 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
666 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
667 BIT(27));
668}
e3ec7017 669#define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
00224aa7
PKS		 670static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
671{
672 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
673 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
674 GENMASK(31, 28));
675}
e3ec7017 676#define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
00224aa7
PKS		 677static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
678{
679 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
680 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
681 GENMASK(8, 0));
682}
e3ec7017 683#define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
00224aa7
PKS		 684static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
685{
686 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
687 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
688 BIT(9));
689}
e3ec7017 690#define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
00224aa7
PKS		 691static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
692{
693 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
694 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
695 BIT(10));
696}
e3ec7017 697#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
00224aa7
PKS		 698static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
699{
700 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
701 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
702 BIT(11));
703}
e3ec7017 704#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
00224aa7
PKS		 705static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
706{
707 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
708 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
709 GENMASK(15, 12));
710}
e3ec7017 711#define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
00224aa7
PKS		 712static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
713{
714 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
715 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
716 GENMASK(24, 16));
717}
e3ec7017 718#define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
00224aa7
PKS		 719static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
720{
721 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
722 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
723 BIT(27));
724}
e3ec7017 725#define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
00224aa7
PKS		 726static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
727{
728 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
729 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
730 GENMASK(31, 28));
731}
e3ec7017 732#define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
00224aa7
PKS		 733static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
734{
735 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
736 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
737 GENMASK(5, 0));
738}
e3ec7017 739#define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
00224aa7
PKS		 740static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
741{
742 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
743 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
744 BIT(6));
745}
e3ec7017 746#define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
00224aa7
PKS		 747static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
748{
749 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
750 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
751 BIT(7));
752}
e3ec7017 753#define SET_CMC_TBL_MASK_RTS_EN BIT(0)
00224aa7
PKS		 754static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
755{
756 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
757 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
758 BIT(8));
759}
e3ec7017 760#define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
00224aa7
PKS		 761static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
762{
763 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
764 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
765 BIT(9));
766}
e3ec7017 767#define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
00224aa7
PKS		 768static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
769{
770 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
771 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
772 GENMASK(11, 10));
773}
e3ec7017 774#define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
00224aa7
PKS		 775static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
776{
777 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
778 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
779 BIT(12));
780}
e3ec7017 781#define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
00224aa7
PKS		 782static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
783{
784 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
785 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
786 GENMASK(14, 13));
787}
e3ec7017 788#define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
00224aa7
PKS		 789static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
790{
791 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
792 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
793 GENMASK(26, 16));
794}
e3ec7017 795#define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
00224aa7
PKS		 796static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
797{
798 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
799 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
800 BIT(27));
801}
e3ec7017 802#define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
00224aa7
PKS		 803static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
804{
805 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
806 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
807 GENMASK(31, 28));
808}
e3ec7017 809#define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
00224aa7
PKS		 810static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
811{
812 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
813 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
814 GENMASK(7, 0));
815}
e3ec7017 816#define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
00224aa7
PKS		 817static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
818{
819 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
820 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
821 GENMASK(9, 8));
822}
e3ec7017 823#define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
00224aa7
PKS		 824static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
825{
826 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
827 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
828 GENMASK(18, 16));
829}
e3ec7017 830#define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
00224aa7
PKS		 831static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
832{
833 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
834 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
835 GENMASK(21, 19));
836}
e3ec7017 837#define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
00224aa7
PKS		 838static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
839{
840 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
841 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
842 GENMASK(24, 22));
843}
e3ec7017 844#define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
00224aa7
PKS		 845static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
846{
847 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
848 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
849 GENMASK(27, 25));
850}
e3ec7017 851#define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
00224aa7
PKS		 852static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
853{
854 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
855 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
856 GENMASK(31, 28));
857}
e3ec7017 858#define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
00224aa7
PKS		 859static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
860{
861 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
862 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
863 GENMASK(2, 0));
864}
e3ec7017 865#define SET_CMC_TBL_MASK_BMC BIT(0)
00224aa7
PKS		 866static inline void SET_CMC_TBL_BMC(void *table, u32 val)
867{
868 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
869 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
870 BIT(3));
871}
e3ec7017 872#define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
00224aa7
PKS		 873static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
874{
875 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
876 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
877 GENMASK(7, 4));
878}
e3ec7017 879#define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
00224aa7
PKS		 880static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
881{
882 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
883 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
884 BIT(8));
885}
e3ec7017 886#define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
00224aa7
PKS		 887static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
888{
889 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
890 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
891 GENMASK(11, 9));
892}
e3ec7017 893#define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
00224aa7
PKS		 894static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
895{
896 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
897 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
898 BIT(12));
899}
e3ec7017 900#define SET_CMC_TBL_MASK_DATA_ER BIT(0)
00224aa7
PKS		 901static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
902{
903 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
904 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
905 BIT(13));
906}
e3ec7017 907#define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
00224aa7
PKS		 908static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
909{
910 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
911 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
912 BIT(14));
913}
e3ec7017 914#define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
00224aa7
PKS		 915static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
916{
917 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
918 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
919 BIT(15));
920}
e3ec7017 921#define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
00224aa7
PKS		 922static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
923{
924 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
925 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
926 BIT(16));
927}
e3ec7017 928#define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
00224aa7
PKS		 929static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
930{
931 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
932 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
933 BIT(17));
934}
e3ec7017 935#define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
00224aa7
PKS		 936static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
937{
938 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
939 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
940 BIT(18));
941}
e3ec7017 942#define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
00224aa7
PKS		 943static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
944{
945 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
946 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
947 BIT(19));
948}
e3ec7017 949#define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
00224aa7
PKS		 950static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
951{
952 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
953 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
954 BIT(20));
955}
e3ec7017 956#define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
00224aa7
PKS		 957static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
958{
959 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
960 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
961 BIT(21));
962}
e3ec7017 963#define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
00224aa7
PKS		 964static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
965{
966 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
967 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
968 BIT(27));
969}
e3ec7017 970#define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
00224aa7
PKS		 971static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
972{
973 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
974 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
975 GENMASK(31, 28));
976}
e3ec7017 977#define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
00224aa7
PKS		 978static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
979{
980 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
981 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
982 GENMASK(8, 0));
983}
e3ec7017 984#define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
00224aa7
PKS		 985static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
986{
987 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
988 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
989 BIT(12));
990}
e3ec7017 991#define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
00224aa7
PKS		 992static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
993{
994 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
995 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
996 BIT(13));
997}
e3ec7017 998#define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
00224aa7
PKS		 999static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1000{
1001 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1002 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1003 GENMASK(19, 16));
1004}
e3ec7017 1005#define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
00224aa7
PKS		 1006static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1007{
1008 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1009 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1010 GENMASK(21, 20));
1011}
e3ec7017 1012#define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
00224aa7
PKS		 1013static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1014{
1015 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1016 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1017 GENMASK(23, 22));
1018}
e3ec7017 1019#define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
00224aa7
PKS		 1020static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1021{
1022 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1023 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1024 GENMASK(25, 24));
1025}
e3ec7017 1026#define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
00224aa7
PKS		 1027static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1028{
1029 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1030 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1031 GENMASK(27, 26));
1032}
e3ec7017 1033#define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
00224aa7
PKS		 1034static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1035{
1036 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1037 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1038 BIT(28));
1039}
e3ec7017 1040#define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
00224aa7
PKS		 1041static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1042{
1043 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1044 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1045 BIT(29));
1046}
e3ec7017 1047#define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
00224aa7
PKS		 1048static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1049{
1050 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1051 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1052 BIT(30));
1053}
e3ec7017 1054#define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
00224aa7
PKS		 1055static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1056{
1057 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1058 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1059 BIT(31));
1060}
aa7f148b
PKS		 1061
1062#define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
1063static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1064{
1065 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1066 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1067 GENMASK(1, 0));
1068}
1069
1070static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1071{
1072 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1073 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1074 GENMASK(3, 2));
1075}
1076
1077static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1078{
1079 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1080 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1081 GENMASK(5, 4));
1082}
1083
1084static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1085{
1086 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1087 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1088 GENMASK(7, 6));
1089}
1090
e3ec7017 1091#define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
00224aa7
PKS		 1092static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1093{
1094 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1095 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1096 GENMASK(7, 0));
1097}
e3ec7017 1098#define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
00224aa7
PKS		 1099static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1100{
1101 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1102 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1103 GENMASK(16, 8));
1104}
e3ec7017 1105#define SET_CMC_TBL_MASK_ULDL BIT(0)
00224aa7
PKS		 1106static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1107{
1108 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1109 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1110 BIT(17));
1111}
e3ec7017 1112#define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
00224aa7
PKS		 1113static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1114{
1115 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1116 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1117 GENMASK(19, 18));
1118}
00224aa7
PKS		 1119static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1120{
1121 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1122 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1123 GENMASK(21, 20));
1124}
1125
1126static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1127{
1128 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1129 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1130 GENMASK(23, 22));
1131}
e3ec7017 1132#define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
00224aa7
PKS		 1133static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1134{
1135 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1136 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1137 GENMASK(27, 24));
1138}
1139
1140static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1141{
1142 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1143 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1144 GENMASK(31, 30));
1145}
e3ec7017 1146#define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
00224aa7
PKS		 1147static inline void SET_CMC_TBL_NC(void *table, u32 val)
1148{
1149 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1150 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1151 GENMASK(2, 0));
1152}
e3ec7017 1153#define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
00224aa7
PKS		 1154static inline void SET_CMC_TBL_NR(void *table, u32 val)
1155{
1156 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1157 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1158 GENMASK(5, 3));
1159}
e3ec7017 1160#define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
00224aa7
PKS		 1161static inline void SET_CMC_TBL_NG(void *table, u32 val)
1162{
1163 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1164 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1165 GENMASK(7, 6));
1166}
e3ec7017 1167#define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
00224aa7
PKS		 1168static inline void SET_CMC_TBL_CB(void *table, u32 val)
1169{
1170 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1171 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1172 GENMASK(9, 8));
1173}
e3ec7017 1174#define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
00224aa7
PKS		 1175static inline void SET_CMC_TBL_CS(void *table, u32 val)
1176{
1177 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1178 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1179 GENMASK(11, 10));
1180}
e3ec7017 1181#define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
00224aa7
PKS		 1182static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1183{
1184 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1185 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1186 BIT(12));
1187}
e3ec7017 1188#define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
00224aa7
PKS		 1189static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1190{
1191 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1192 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1193 BIT(13));
1194}
e3ec7017 1195#define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
00224aa7
PKS		 1196static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1197{
1198 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1199 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1200 BIT(14));
1201}
e3ec7017 1202#define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
00224aa7
PKS		 1203static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1204{
1205 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1206 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1207 BIT(15));
1208}
e3ec7017 1209#define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
00224aa7
PKS		 1210static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1211{
1212 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1213 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1214 GENMASK(24, 16));
1215}
e3ec7017 1216#define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
00224aa7
PKS		 1217static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1218{
1219 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1220 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1221 GENMASK(27, 25));
1222}
aa7f148b
PKS		 1223
1224static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
00224aa7 1225{
aa7f148b
PKS		 1226 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1227 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1228 GENMASK(29, 28));
00224aa7 1229}
aa7f148b 1230
e3ec7017 1231#define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
00224aa7
PKS		 1232static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1233{
1234 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1235 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1236 GENMASK(31, 30));
1237}
1238
04b5983e
PKS		 1239static inline void SET_DCTL_MACID_V1(void *table, u32 val)
1240{
1241 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
1242}
1243
1244static inline void SET_DCTL_OPERATION_V1(void *table, u32 val)
1245{
1246 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
1247}
1248
1249#define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0)
1250static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val)
1251{
1252 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0));
1253 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1,
1254 GENMASK(7, 0));
1255}
1256
1257#define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0)
1258static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val)
1259{
1260 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8));
1261 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID,
1262 GENMASK(14, 8));
1263}
1264
1265#define SET_DCTL_MASK_QOS_DATA BIT(0)
1266static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val)
1267{
1268 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
1269 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA,
1270 BIT(15));
1271}
1272
1273#define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0)
1274static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val)
1275{
1276 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16));
1277 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L,
1278 GENMASK(31, 16));
1279}
1280
1281#define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0)
1282static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val)
1283{
1284 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0));
1285 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H,
1286 GENMASK(31, 0));
1287}
1288
1289#define SET_DCTL_MASK_SEQ0 GENMASK(11, 0)
1290static inline void SET_DCTL_SEQ0_V1(void *table, u32 val)
1291{
1292 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0));
1293 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0,
1294 GENMASK(11, 0));
1295}
1296
1297#define SET_DCTL_MASK_SEQ1 GENMASK(11, 0)
1298static inline void SET_DCTL_SEQ1_V1(void *table, u32 val)
1299{
1300 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12));
1301 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1,
1302 GENMASK(23, 12));
1303}
1304
1305#define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0)
1306static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val)
1307{
1308 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24));
1309 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN,
1310 GENMASK(26, 24));
1311}
1312
1313#define SET_DCTL_MASK_STA_AMSDU_EN BIT(0)
1314static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val)
1315{
1316 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
1317 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN,
1318 BIT(27));
1319}
1320
1321#define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0)
1322static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val)
1323{
1324 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28));
1325 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN,
1326 BIT(28));
1327}
1328
1329#define SET_DCTL_MASK_WITH_LLC BIT(0)
1330static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val)
1331{
1332 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29));
1333 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC,
1334 BIT(29));
1335}
1336
1337#define SET_DCTL_MASK_SEQ2 GENMASK(11, 0)
1338static inline void SET_DCTL_SEQ2_V1(void *table, u32 val)
1339{
1340 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0));
1341 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2,
1342 GENMASK(11, 0));
1343}
1344
1345#define SET_DCTL_MASK_SEQ3 GENMASK(11, 0)
1346static inline void SET_DCTL_SEQ3_V1(void *table, u32 val)
1347{
1348 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12));
1349 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3,
1350 GENMASK(23, 12));
1351}
1352
1353#define SET_DCTL_MASK_TGT_IND GENMASK(3, 0)
1354static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val)
1355{
1356 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24));
1357 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND,
1358 GENMASK(27, 24));
1359}
1360
1361#define SET_DCTL_MASK_TGT_IND_EN BIT(0)
1362static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val)
1363{
1364 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28));
1365 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN,
1366 BIT(28));
1367}
1368
1369#define SET_DCTL_MASK_HTC_LB GENMASK(2, 0)
1370static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val)
1371{
1372 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29));
1373 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB,
1374 GENMASK(31, 29));
1375}
1376
1377#define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0)
1378static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val)
1379{
1380 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0));
1381 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN,
1382 GENMASK(4, 0));
1383}
1384
1385#define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0)
1386static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val)
1387{
1388 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5));
1389 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID,
1390 BIT(5));
1391}
1392
1393#define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0)
1394static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val)
1395{
1396 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6));
1397 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL,
1398 GENMASK(7, 6));
1399}
1400
1401#define SET_DCTL_MASK_HTC_ORDER BIT(0)
1402static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val)
1403{
1404 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1405 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER,
1406 BIT(8));
1407}
1408
1409#define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0)
1410static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val)
1411{
1412 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9));
1413 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID,
1414 GENMASK(10, 9));
1415}
1416
1417#define SET_DCTL_MASK_WAPI BIT(0)
1418static inline void SET_DCTL_WAPI_V1(void *table, u32 val)
1419{
1420 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1421 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI,
1422 BIT(15));
1423}
1424
1425#define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0)
1426static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val)
1427{
1428 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16));
1429 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE,
1430 GENMASK(17, 16));
1431}
1432
1433#define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0)
1434static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val)
1435{
1436 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18));
1437 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1438 GENMASK(19, 18));
1439}
1440
1441static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val)
1442{
1443 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20));
1444 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1445 GENMASK(21, 20));
1446}
1447
1448static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val)
1449{
1450 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22));
1451 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1452 GENMASK(23, 22));
1453}
1454
1455static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val)
1456{
1457 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24));
1458 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1459 GENMASK(25, 24));
1460}
1461
1462static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val)
1463{
1464 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26));
1465 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1466 GENMASK(27, 26));
1467}
1468
1469static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val)
1470{
1471 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28));
1472 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1473 GENMASK(29, 28));
1474}
1475
1476static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val)
1477{
1478 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30));
1479 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1480 GENMASK(31, 30));
1481}
1482
1483#define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0)
1484static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val)
1485{
1486 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0));
1487 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID,
1488 GENMASK(7, 0));
1489}
1490
1491#define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0)
1492static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val)
1493{
1494 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8));
1495 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1496 GENMASK(15, 8));
1497}
1498
1499static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val)
1500{
1501 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16));
1502 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1503 GENMASK(23, 16));
1504}
1505
1506static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val)
1507{
1508 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24));
1509 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1510 GENMASK(31, 24));
1511}
1512
1513static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val)
1514{
1515 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1516 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1517 GENMASK(7, 0));
1518}
1519
1520static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val)
1521{
1522 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8));
1523 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1524 GENMASK(15, 8));
1525}
1526
1527static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val)
1528{
1529 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16));
1530 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1531 GENMASK(23, 16));
1532}
1533
1534static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val)
1535{
1536 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24));
1537 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1538 GENMASK(31, 24));
1539}
1540
f7e76d13
PKS		 1541static inline void SET_BCN_UPD_PORT(void *h2c, u32 val)
1542{
1543 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1544}
1545
1546static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val)
1547{
1548 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1549}
1550
1551static inline void SET_BCN_UPD_BAND(void *h2c, u32 val)
1552{
1553 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1554}
1555
1556static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val)
1557{
1558 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24));
1559}
1560
1561static inline void SET_BCN_UPD_MACID(void *h2c, u32 val)
1562{
1563 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1564}
1565
1566static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val)
1567{
1568 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8));
1569}
1570
1571static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val)
1572{
1573 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10));
1574}
1575
1576static inline void SET_BCN_UPD_RATE(void *h2c, u32 val)
1577{
1578 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12));
1579}
1580
1581static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val)
1582{
1583 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21));
1584}
1585
1586static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val)
1587{
1588 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0));
1589}
1590
1591static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val)
1592{
1593 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1));
1594}
1595
1596static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val)
1597{
1598 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5));
1599}
1600
1601static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val)
1602{
1603 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7));
1604}
1605
1606static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val)
1607{
1608 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9));
1609}
1610
1611static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val)
1612{
1613 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11));
1614}
1615
1616static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val)
1617{
1618 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13));
1619}
1620
1621static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val)
1622{
1623 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14));
1624}
1625
1626static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val)
1627{
1628 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15));
1629}
1630
1631static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val)
1632{
1633 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16));
1634}
1635
1636static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val)
1637{
1638 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17));
1639}
1640
00224aa7
PKS		 1641static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1642{
1643 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1644}
1645
1646static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1647{
1648 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1649}
1650
1651static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1652{
1653 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1654}
1655
1656static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1657{
1658 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1659}
1660
1661static inline void SET_JOININFO_MACID(void *h2c, u32 val)
1662{
1663 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1664}
1665
1666static inline void SET_JOININFO_OP(void *h2c, u32 val)
1667{
1668 le32p_replace_bits((__le32 *)h2c, val, BIT(8));
1669}
1670
1671static inline void SET_JOININFO_BAND(void *h2c, u32 val)
1672{
1673 le32p_replace_bits((__le32 *)h2c, val, BIT(9));
1674}
1675
1676static inline void SET_JOININFO_WMM(void *h2c, u32 val)
1677{
1678 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10));
1679}
1680
1681static inline void SET_JOININFO_TGR(void *h2c, u32 val)
1682{
1683 le32p_replace_bits((__le32 *)h2c, val, BIT(12));
1684}
1685
1686static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val)
1687{
1688 le32p_replace_bits((__le32 *)h2c, val, BIT(13));
1689}
1690
1691static inline void SET_JOININFO_DLBW(void *h2c, u32 val)
1692{
1693 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14));
1694}
1695
1696static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val)
1697{
1698 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16));
1699}
1700
1701static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val)
1702{
1703 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18));
1704}
1705
1706static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val)
1707{
1708 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21));
1709}
1710
1711static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val)
1712{
1713 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24));
1714}
1715
1716static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val)
1717{
1718 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26));
1719}
1720
1721static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val)
1722{
1723 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30));
1724}
1725
1726static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1727{
1728 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1729}
1730
1731static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1732{
1733 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1734}
1735
1736static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1737{
1738 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1739}
1740
1741static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1742{
1743 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1744}
1745
1746static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1747{
1748 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1749}
1750
1751static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1752{
1753 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1754}
1755
1756static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1757{
1758 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1759}
1760
1761static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1762{
1763 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1764}
1765
1766static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1767{
1768 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1769}
1770
1771static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1772{
1773 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1774}
1775
1776static inline void SET_BA_CAM_VALID(void *h2c, u32 val)
1777{
1778 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1779}
1780
1781static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val)
1782{
1783 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1784}
1785
1786static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val)
1787{
1788 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2));
1789}
1790
1791static inline void SET_BA_CAM_TID(void *h2c, u32 val)
1792{
1793 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4));
1794}
1795
1796static inline void SET_BA_CAM_MACID(void *h2c, u32 val)
1797{
1798 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1799}
1800
1801static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val)
1802{
1803 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1804}
1805
1806static inline void SET_BA_CAM_SSN(void *h2c, u32 val)
1807{
1808 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20));
1809}
1810
3ffbb5a8
PKS		 1811static inline void SET_BA_CAM_UID(void *h2c, u32 val)
1812{
1813 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0));
1814}
1815
1816static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val)
1817{
1818 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8));
1819}
1820
1821static inline void SET_BA_CAM_BAND(void *h2c, u32 val)
1822{
1823 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9));
1824}
1825
1826static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val)
1827{
1828 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28));
1829}
1830
00224aa7
PKS		 1831static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1832{
1833 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1834}
1835
1836static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1837{
1838 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1839}
1840
1841static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1842{
1843 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1844}
1845
1846static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1847{
1848 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1849}
1850
1851static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1852{
1853 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1854}
1855
1856static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1857{
1858 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1859}
1860
1861static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1862{
1863 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1864}
1865
1866static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1867{
1868 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1869}
1870
1871static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1872{
1873 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1874}
1875
1876static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1877{
1878 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1879}
e3ec7017 1880
edb89629
ZZY		 1881static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1882{
1883 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1884}
1885
9a785583
ZZY		 1886static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1887{
1888 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1889}
1890
1891static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1892{
1893 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1894}
1895
1896static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1897{
1898 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1899}
1900
1901static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1902{
1903 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1904}
1905
1906static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1907{
1908 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1909}
1910
1911static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1912{
1913 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1914}
1915
41d56769
CKC		 1916static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1917{
1918 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1919}
1920
1921static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1922{
1923 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1924}
1925
1926static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1927{
1928 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1929}
1930
1931static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1932{
1933 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1934}
1935
ee88d748
CYL		 1936static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1937{
1938 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1939}
1940
1941static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1942{
1943 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1944}
1945
1946static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1947{
1948 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1949}
1950
1951static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1952{
1953 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1954}
1955
1956static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1957{
1958 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1959}
1960
1961static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1962{
1963 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1964}
1965
1966static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1967{
1968 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1969}
1970
1971static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1972{
1973 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1974}
1975
1976static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1977{
1978 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1979}
1980
1981static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1982{
1983 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1984}
1985
1986static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1987{
1988 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1989}
1990
1991static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val)
1992{
1993 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1994}
1995
1996static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val)
1997{
1998 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1999}
2000
2001static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val)
2002{
2003 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2004}
2005
2006static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val)
2007{
2008 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2009}
2010
2011static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val)
2012{
2013 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
2014}
2015
2016static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val)
2017{
2018 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
2019}
2020
2021static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val)
2022{
2023 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2024}
2025
2026static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val)
2027{
2028 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
2029}
2030
2031static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
2032{
2033 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2034}
2035
2036static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
2037{
2038 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2039}
2040
2041static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2042{
2043 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2044}
2045
2046static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2047{
2048 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2049}
2050
2051static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2052{
2053 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2054}
2055
2056static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2057{
2058 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2059}
2060
2061static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2062{
2063 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2064}
2065
2066static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2067{
2068 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2069}
2070
2071static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2072{
2073 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2074}
2075
d2b68e95
CYL		 2076static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2077{
2078 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2079}
2080
2081static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2082{
2083 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2084}
2085
2086static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2087{
2088 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2089}
2090
2091static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2092{
2093 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2094}
2095
2096static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2097{
2098 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2099}
2100
2101static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2102{
2103 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2104}
2105
2106static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2107{
2108 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2109}
2110
2111static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2112{
2113 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2114}
2115
2116static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2117{
2118 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2119}
2120
2121static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2122{
2123 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2124}
2125
2126static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2127{
2128 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2129}
2130
2131static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2132{
2133 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2134}
2135
2136static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2137{
2138 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2139}
2140
e3ec7017
PKS		 2141enum rtw89_btc_btf_h2c_class {
2142 BTFC_SET = 0x10,
2143 BTFC_GET = 0x11,
2144 BTFC_FW_EVENT = 0x12,
2145};
2146
2147enum rtw89_btc_btf_set {
2148 SET_REPORT_EN = 0x0,
2149 SET_SLOT_TABLE,
2150 SET_MREG_TABLE,
2151 SET_CX_POLICY,
2152 SET_GPIO_DBG,
2153 SET_DRV_INFO,
2154 SET_DRV_EVENT,
2155 SET_BT_WREG_ADDR,
2156 SET_BT_WREG_VAL,
2157 SET_BT_RREG_ADDR,
2158 SET_BT_WL_CH_INFO,
2159 SET_BT_INFO_REPORT,
2160 SET_BT_IGNORE_WLAN_ACT,
2161 SET_BT_TX_PWR,
2162 SET_BT_LNA_CONSTRAIN,
2163 SET_BT_GOLDEN_RX_RANGE,
2164 SET_BT_PSD_REPORT,
2165 SET_H2C_TEST,
2166 SET_MAX1,
2167};
2168
2169enum rtw89_btc_cxdrvinfo {
2170 CXDRVINFO_INIT = 0,
2171 CXDRVINFO_ROLE,
2172 CXDRVINFO_DBCC,
2173 CXDRVINFO_SMAP,
2174 CXDRVINFO_RFK,
2175 CXDRVINFO_RUN,
2176 CXDRVINFO_CTRL,
2177 CXDRVINFO_SCAN,
a2c0ce5d 2178 CXDRVINFO_TRX, /* WL traffic to WL fw */
e3ec7017
PKS		 2179 CXDRVINFO_MAX,
2180};
2181
89590777
PHH		 2182enum rtw89_scan_mode {
2183 RTW89_SCAN_IMMEDIATE,
2184};
2185
2186enum rtw89_scan_type {
2187 RTW89_SCAN_ONCE,
2188};
2189
00224aa7
PKS		 2190static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2191{
2192 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2193}
2194
2195static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2196{
2197 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2198}
2199
c0fea064
PKS		 2200struct rtw89_h2c_cxhdr {
2201 u8 type;
2202 u8 len;
2203} __packed;
00224aa7 2204
c0fea064
PKS		 2205#define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2206
2207struct rtw89_h2c_cxinit {
2208 struct rtw89_h2c_cxhdr hdr;
2209 u8 ant_type;
2210 u8 ant_num;
2211 u8 ant_iso;
2212 u8 ant_info;
2213 u8 mod_rfe;
2214 u8 mod_cv;
2215 u8 mod_info;
2216 u8 mod_adie_kt;
2217 u8 wl_gch;
2218 u8 info;
2219 u8 rsvd;
2220 u8 rsvd1;
2221} __packed;
00224aa7 2222
c0fea064
PKS		 2223#define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2224#define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2225#define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2226#define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2227
2228#define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2229#define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2230#define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2231#define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2232
2233#define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2234#define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2235#define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2236#define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2237#define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
00224aa7
PKS		 2238
2239static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2240{
2241 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2242}
2243
2244static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2245{
2246 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2247}
2248
2249static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2250{
2251 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2252}
2253
2254static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2255{
2256 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2257}
2258
2259static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2260{
2261 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2262}
2263
2264static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2265{
2266 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2267}
2268
2269static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2270{
2271 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2272}
2273
2274static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2275{
2276 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2277}
2278
2279static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2280{
2281 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2282}
2283
2284static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2285{
2286 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2287}
2288
2289static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2290{
2291 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2292}
2293
2294static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2295{
2296 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2297}
2298
2299static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2300{
2301 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2302}
2303
2304static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2305{
2306 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2307}
2308
e390cf2e 2309static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
00224aa7 2310{
e390cf2e 2311 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
00224aa7
PKS		 2312}
2313
e390cf2e 2314static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
00224aa7 2315{
e390cf2e 2316 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
00224aa7
PKS		 2317}
2318
e390cf2e 2319static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
00224aa7 2320{
e390cf2e 2321 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
00224aa7
PKS		 2322}
2323
e390cf2e 2324static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
00224aa7 2325{
e390cf2e 2326 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
00224aa7
PKS		 2327}
2328
e390cf2e 2329static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
00224aa7 2330{
e390cf2e 2331 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
00224aa7
PKS		 2332}
2333
e390cf2e 2334static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
00224aa7 2335{
e390cf2e 2336 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
00224aa7
PKS		 2337}
2338
e390cf2e 2339static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
00224aa7 2340{
e390cf2e 2341 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
00224aa7
PKS		 2342}
2343
e390cf2e 2344static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
00224aa7 2345{
e390cf2e 2346 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
00224aa7
PKS		 2347}
2348
e390cf2e 2349static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
00224aa7 2350{
e390cf2e 2351 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
00224aa7
PKS		 2352}
2353
e390cf2e 2354static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
00224aa7 2355{
e390cf2e 2356 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
00224aa7
PKS		 2357}
2358
e390cf2e 2359static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
00224aa7 2360{
e390cf2e 2361 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
00224aa7
PKS		 2362}
2363
e390cf2e 2364static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
00224aa7 2365{
e390cf2e 2366 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
00224aa7
PKS		 2367}
2368
e390cf2e 2369static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
00224aa7 2370{
e390cf2e
CTK		 2371 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2372}
2373
2374static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2375{
2376 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2377}
2378
5049964c
CTK		 2379static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2380{
2381 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2382}
2383
2384static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2385{
2386 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2387}
2388
2389static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2390{
2391 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2392}
2393
2394static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2395{
2396 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2397}
2398
2399static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2400{
2401 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2402}
2403
2404static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2405{
2406 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2407}
2408
2409static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2410{
2411 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2412}
2413
2414static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2415{
2416 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2417}
2418
2419static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2420{
2421 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2422}
2423
2424static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2425{
2426 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2427}
2428
e390cf2e
CTK		 2429static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2430{
2431 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2432}
2433
2434static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2435{
2436 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2437}
2438
2439static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2440{
2441 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2442}
2443
2444static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2445{
2446 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2447}
2448
2449static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2450{
2451 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2452}
2453
2454static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2455{
2456 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
00224aa7
PKS		 2457}
2458
2459static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2460{
2461 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2462}
2463
2464static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2465{
2466 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2467}
2468
2469static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2470{
2471 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2472}
2473
2474static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2475{
2476 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2477}
2478
a2c0ce5d
CTK		 2479static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2480{
2481 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2482}
2483
2484static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2485{
2486 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2487}
2488
2489static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2490{
2491 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2492}
2493
2494static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2495{
2496 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2497}
2498
2499static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2500{
2501 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2502}
2503
2504static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2505{
2506 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2507}
2508
2509static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2510{
2511 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2512}
2513
2514static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2515{
2516 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2517}
2518
2519static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2520{
2521 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2522}
2523
2524static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2525{
2526 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2527}
2528
2529static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2530{
2531 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2532}
2533
2534static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2535{
2536 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2537}
2538
2539static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2540{
2541 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2542}
2543
2544static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2545{
2546 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2547}
2548
2549static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2550{
2551 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2552}
2553
2554static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2555{
2556 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2557}
2558
2559static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2560{
2561 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2562}
2563
00224aa7
PKS		 2564static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2565{
2566 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2567}
2568
2569static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2570{
2571 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2572}
2573
2574static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2575{
2576 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2577}
2578
2579static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2580{
2581 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2582}
2583
2584static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2585{
2586 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2587}
e3ec7017 2588
89590777
PHH		 2589static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2590{
2591 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2592}
2593
2594static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2595{
2596 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2597}
2598
2599static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2600{
2601 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2602}
2603
2604static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val)
2605{
2606 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2607}
2608
2609static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val)
2610{
2611 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2612}
2613
2614static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val)
2615{
2616 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2617}
2618
2619static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val)
2620{
2621 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2622}
2623
2624static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val)
2625{
2626 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16));
2627}
2628
2629static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val)
2630{
2631 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24));
2632}
2633
2634static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val)
2635{
2636 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0));
2637}
2638
2639static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val)
2640{
2641 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3));
2642}
2643
2644static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val)
2645{
2646 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8));
2647}
2648
2649static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val)
2650{
2651 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12));
2652}
2653
2654static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val)
2655{
2656 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13));
2657}
2658
2659static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val)
2660{
2661 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14));
2662}
2663
2664static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val)
2665{
2666 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
2667}
2668
2669static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val)
2670{
2671 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24));
2672}
2673
2674static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val)
2675{
2676 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25));
2677}
2678
2679static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val)
2680{
2681 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26));
2682}
2683
2684static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val)
2685{
2686 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27));
2687}
2688
2689static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val)
2690{
2691 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0));
2692}
2693
2694static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val)
2695{
2696 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8));
2697}
2698
2699static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val)
2700{
2701 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2702}
2703
2704static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val)
2705{
2706 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24));
2707}
2708
2709static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val)
2710{
2711 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0));
2712}
2713
2714static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val)
2715{
2716 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8));
2717}
2718
2719static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val)
2720{
2721 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16));
2722}
2723
2724static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val)
2725{
2726 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24));
2727}
2728
2729static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val)
2730{
2731 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0));
2732}
2733
2734static inline void RTW89_SET_FWCMD_SCANOFLD_MACID(void *cmd, u32 val)
2735{
2736 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2737}
2738
2739static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void *cmd, u32 val)
2740{
2741 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2742}
2743
2744static inline void RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void *cmd, u32 val)
2745{
2746 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(18, 16));
2747}
2748
2749static inline void RTW89_SET_FWCMD_SCANOFLD_BAND(void *cmd, u32 val)
2750{
2751 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, BIT(19));
2752}
2753
2754static inline void RTW89_SET_FWCMD_SCANOFLD_OPERATION(void *cmd, u32 val)
2755{
2756 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(21, 20));
2757}
2758
2759static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void *cmd, u32 val)
2760{
2761 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 22));
2762}
2763
2764static inline void RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void *cmd, u32 val)
2765{
2766 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(0));
2767}
2768
2769static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void *cmd, u32 val)
2770{
2771 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(1));
2772}
2773
2774static inline void RTW89_SET_FWCMD_SCANOFLD_START_MODE(void *cmd, u32 val)
2775{
2776 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(2));
2777}
2778
2779static inline void RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void *cmd, u32 val)
2780{
2781 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(4, 3));
2782}
2783
2784static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void *cmd, u32 val)
2785{
2786 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 5));
2787}
2788
2789static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void *cmd, u32 val)
2790{
2791 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 8));
2792}
2793
2794static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void *cmd,
2795 u32 val)
2796{
2797 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
2798}
2799
2800static inline void RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void *cmd, u32 val)
2801{
2802 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(31, 24));
2803}
2804
2805static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void *cmd, u32 val)
2806{
2807 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 0));
2808}
2809
2810static inline void RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void *cmd, u32 val)
2811{
2812 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2813}
2814
2815static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void *cmd, u32 val)
2816{
2817 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 0));
2818}
2819
2820static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void *cmd, u32 val)
2821{
2822 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(31, 0));
2823}
2824
f4a43c3b
DSY		 2825static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2826{
2827 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2828}
2829
2830static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2831{
2832 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2833}
2834
2835static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2836{
2837 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2838}
2839
2840static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2841{
2842 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2843}
2844
2845static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2846{
2847 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2848}
2849
2850static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2851{
2852 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2853}
2854
2855static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2856{
2857 *((__le32 *)cmd + 1) = val;
2858}
2859
2860static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2861{
2862 *((__le32 *)cmd + 2) = val;
2863}
2864
2865static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2866{
2867 *((__le32 *)cmd + 3) = val;
2868}
2869
2870static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2871{
2872 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2873}
2874
2875static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2876{
2877 u8 ctwnd;
2878
2879 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2880 return;
2881 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2882 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2883}
2884
2885static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2886{
2887 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2888}
2889
2890static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2891{
2892 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2893}
2894
2895static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2896{
2897 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2898}
2899
2900static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2901{
2902 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2903}
2904
c008c4b0
ZZY		 2905enum rtw89_fw_mcc_c2h_rpt_cfg {
2906 RTW89_FW_MCC_C2H_RPT_OFF = 0,
2907 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
2908 RTW89_FW_MCC_C2H_RPT_ALL = 2,
2909};
2910
2911struct rtw89_fw_mcc_add_req {
2912 u8 macid;
2913 u8 central_ch_seg0;
2914 u8 central_ch_seg1;
2915 u8 primary_ch;
2916 enum rtw89_bandwidth bandwidth: 4;
2917 u32 group: 2;
2918 u32 c2h_rpt: 2;
2919 u32 dis_tx_null: 1;
2920 u32 dis_sw_retry: 1;
2921 u32 in_curr_ch: 1;
2922 u32 sw_retry_count: 3;
2923 u32 tx_null_early: 4;
2924 u32 btc_in_2g: 1;
2925 u32 pta_en: 1;
2926 u32 rfk_by_pass: 1;
2927 u32 ch_band_type: 2;
2928 u32 rsvd0: 9;
2929 u32 duration;
2930 u8 courtesy_en;
2931 u8 courtesy_num;
2932 u8 courtesy_target;
2933 u8 rsvd1;
2934};
2935
2936static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2937{
2938 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2939}
2940
2941static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2942{
2943 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2944}
2945
2946static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2947{
2948 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2949}
2950
2951static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2952{
2953 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2954}
2955
2956static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2957{
2958 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2959}
2960
2961static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2962{
2963 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2964}
2965
2966static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2967{
2968 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2969}
2970
2971static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2972{
2973 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2974}
2975
2976static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2977{
2978 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2979}
2980
2981static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2982{
2983 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2984}
2985
2986static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2987{
2988 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2989}
2990
2991static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2992{
2993 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2994}
2995
2996static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2997{
2998 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2999}
3000
3001static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
3002{
3003 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3004}
3005
3006static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3007{
3008 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3009}
3010
3011static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3012{
3013 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3014}
3015
3016static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3017{
3018 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3019}
3020
3021static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3022{
3023 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3024}
3025
3026static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3027{
3028 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3029}
3030
3031static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3032{
3033 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3034}
3035
3036struct rtw89_fw_mcc_start_req {
3037 u32 group: 2;
3038 u32 btc_in_group: 1;
3039 u32 old_group_action: 2;
3040 u32 old_group: 2;
3041 u32 rsvd0: 9;
3042 u32 notify_cnt: 3;
3043 u32 rsvd1: 2;
3044 u32 notify_rxdbg_en: 1;
3045 u32 rsvd2: 2;
3046 u32 macid: 8;
3047 u32 tsf_low;
3048 u32 tsf_high;
3049};
3050
3051static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3052{
3053 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3054}
3055
3056static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3057{
3058 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3059}
3060
3061static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3062{
3063 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3064}
3065
3066static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3067{
3068 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3069}
3070
3071static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3072{
3073 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3074}
3075
3076static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3077{
3078 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3079}
3080
3081static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3082{
3083 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3084}
3085
3086static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3087{
3088 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3089}
3090
3091static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3092{
3093 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3094}
3095
3096static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3097{
3098 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3099}
3100
3101static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3102{
3103 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3104}
3105
3106static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3107{
3108 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3109}
3110
3111static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3112{
3113 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3114}
3115
3116static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3117{
3118 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3119}
3120
3121static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3122{
3123 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3124}
3125
3126struct rtw89_fw_mcc_tsf_req {
3127 u8 group: 2;
3128 u8 rsvd0: 6;
3129 u8 macid_x;
3130 u8 macid_y;
3131 u8 rsvd1;
3132};
3133
3134static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3135{
3136 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3137}
3138
3139static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3140{
3141 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3142}
3143
3144static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3145{
3146 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3147}
3148
3149static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3150{
3151 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3152}
3153
3154static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3155{
3156 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3157}
3158
3159static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3160{
3161 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3162}
3163
3164static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3165 u8 *bitmap, u8 len)
3166{
3167 memcpy((__le32 *)cmd + 1, bitmap, len);
3168}
3169
3170static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3171{
3172 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3173}
3174
3175static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3176{
3177 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3178}
3179
3180static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3181{
3182 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3183}
3184
3185static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3186{
3187 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3188}
3189
3190struct rtw89_fw_mcc_duration {
3191 u32 group: 2;
3192 u32 btc_in_group: 1;
3193 u32 rsvd0: 5;
3194 u32 start_macid: 8;
3195 u32 macid_x: 8;
3196 u32 macid_y: 8;
3197 u32 start_tsf_low;
3198 u32 start_tsf_high;
3199 u32 duration_x;
3200 u32 duration_y;
3201};
3202
3203static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3204{
3205 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3206}
3207
3208static
3209inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3210{
3211 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3212}
3213
3214static
3215inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3216{
3217 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3218}
3219
3220static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3221{
3222 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3223}
3224
3225static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3226{
3227 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3228}
3229
3230static
3231inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3232{
3233 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3234}
3235
3236static
3237inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3238{
3239 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3240}
3241
3242static
3243inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3244{
3245 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3246}
3247
3248static
3249inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3250{
3251 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3252}
3253
e3ec7017
PKS		 3254#define RTW89_C2H_HEADER_LEN 8
3255
3256#define RTW89_GET_C2H_CATEGORY(c2h) \
321e763c 3257 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0))
e3ec7017 3258#define RTW89_GET_C2H_CLASS(c2h) \
321e763c 3259 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2))
e3ec7017 3260#define RTW89_GET_C2H_FUNC(c2h) \
321e763c 3261 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8))
e3ec7017 3262#define RTW89_GET_C2H_LEN(c2h) \
321e763c 3263 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0))
e3ec7017 3264
860e8263
ZZY		 3265struct rtw89_fw_c2h_attr {
3266 u8 category;
3267 u8 class;
3268 u8 func;
3269 u16 len;
3270};
3271
3272static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3273{
3274 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3275
3276 return (struct rtw89_fw_c2h_attr *)skb->cb;
3277}
3278
e3ec7017
PKS		 3279#define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2)
3280#define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN)
3281
3282#define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \
321e763c 3283 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
e3ec7017 3284#define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \
321e763c 3285 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
e3ec7017 3286#define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \
321e763c 3287 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
e3ec7017 3288#define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \
321e763c 3289 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
e3ec7017 3290#define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \
321e763c 3291 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
e3ec7017
PKS		 3292
3293#define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
321e763c 3294 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
e3ec7017 3295#define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
321e763c 3296 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
e3ec7017 3297#define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
321e763c 3298 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
e3ec7017 3299#define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
321e763c 3300 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
e3ec7017 3301
d2b6da24
PHH		 3302struct rtw89_c2h_mac_bcnfltr_rpt {
3303 __le32 w0;
3304 __le32 w1;
3305 __le32 w2;
3306} __packed;
3307
3308#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3309#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3310#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3311#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3312
e3ec7017 3313#define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \
321e763c 3314 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0))
e3ec7017 3315#define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \
321e763c 3316 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
e3ec7017 3317#define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \
321e763c 3318 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0))
e3ec7017 3319#define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \
321e763c 3320 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8))
e3ec7017 3321#define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \
321e763c 3322 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10))
e3ec7017 3323#define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \
321e763c 3324 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13))
e3ec7017
PKS		 3325
3326/* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3327 * HT-new: [6:5]: NA, [4:0]: MCS
3328 */
3329#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3330#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3331#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3332#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3333 FIELD_PREP(GENMASK(2, 0), mcs))
3334
89590777
PHH		 3335#define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3336 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3337#define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3338 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3339#define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3340 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3341
3342#define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \
3343 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3344#define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \
3345 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16))
3346#define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \
3347 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20))
3a1e7cb1
PHH		 3348#define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \
3349 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
89590777
PHH		 3350#define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \
3351 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0))
3352#define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \
3353 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4))
3354#define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
3355 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
3356
ef9dff4c 3357#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
24d72944 3358 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
ef9dff4c 3359#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
24d72944 3360 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
ef9dff4c
ZZY		 3361
3362#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
24d72944 3363 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
ef9dff4c 3364#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
24d72944 3365 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
ef9dff4c 3366#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
24d72944 3367 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
ef9dff4c
ZZY		 3368
3369struct rtw89_mac_mcc_tsf_rpt {
3370 u32 macid_x;
3371 u32 macid_y;
3372 u32 tsf_x_low;
3373 u32 tsf_x_high;
3374 u32 tsf_y_low;
3375 u32 tsf_y_high;
3376};
3377
3378static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3379
3380#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
24d72944 3381 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
ef9dff4c 3382#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
24d72944 3383 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
ef9dff4c 3384#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
24d72944 3385 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
ef9dff4c 3386#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
24d72944 3387 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
ef9dff4c 3388#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
24d72944 3389 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
ef9dff4c 3390#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
24d72944 3391 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
ef9dff4c 3392#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
24d72944 3393 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
ef9dff4c
ZZY		 3394
3395#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
24d72944 3396 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
ef9dff4c 3397#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
24d72944 3398 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
ef9dff4c 3399#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
24d72944 3400 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
ef9dff4c 3401#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
24d72944 3402 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
ef9dff4c 3403#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
24d72944 3404 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
ef9dff4c 3405
d2b6da24
PHH		 3406struct rtw89_h2c_bcnfltr {
3407 __le32 w0;
3408} __packed;
3409
3410#define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3411#define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3412#define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3413#define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3414#define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3415#define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3416#define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3417#define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3418
3419struct rtw89_h2c_ofld_rssi {
3420 __le32 w0;
3421 __le32 w1;
3422} __packed;
3423
3424#define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3425#define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3426#define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3427
e3ec7017
PKS		 3428#define RTW89_FW_HDR_SIZE 32
3429#define RTW89_FW_SECTION_HDR_SIZE 16
3430
3431#define RTW89_MFW_SIG 0xFF
3432
3433struct rtw89_mfw_info {
3434 u8 cv;
3435 u8 type; /* enum rtw89_fw_type */
3436 u8 mp;
3437 u8 rsvd;
3438 __le32 shift;
3439 __le32 size;
3440 u8 rsvd2[4];
3441} __packed;
3442
3443struct rtw89_mfw_hdr {
3444 u8 sig; /* RTW89_MFW_SIG */
3445 u8 fw_nr;
deebea35
ZZY		 3446 u8 rsvd0[2];
3447 struct {
3448 u8 major;
3449 u8 minor;
3450 u8 sub;
3451 u8 idx;
3452 } ver;
3453 u8 rsvd1[8];
e3ec7017
PKS		 3454 struct rtw89_mfw_info info[];
3455} __packed;
3456
3457struct fwcmd_hdr {
3458 __le32 hdr0;
3459 __le32 hdr1;
3460};
3461
3ddfe3bd
ZZY		 3462union rtw89_compat_fw_hdr {
3463 struct rtw89_mfw_hdr mfw_hdr;
3464 u8 fw_hdr[RTW89_FW_HDR_SIZE];
3465};
3466
3467static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3468{
3469 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3470
3471 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3472 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3473 else
3474 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3475}
3476
ffde7f34
PKS		 3477static inline void rtw89_fw_get_filename(char *buf, size_t size,
3478 const char *fw_basename, int fw_format)
3479{
3480 if (fw_format <= 0)
3481 snprintf(buf, size, "%s.bin", fw_basename);
3482 else
3483 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3484}
3485
e3ec7017
PKS		 3486#define RTW89_H2C_RF_PAGE_SIZE 500
3487#define RTW89_H2C_RF_PAGE_NUM 3
3488struct rtw89_fw_h2c_rf_reg_info {
3489 enum rtw89_rf_path rf_path;
3490 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3491 u16 curr_idx;
3492};
3493
3494#define H2C_SEC_CAM_LEN 24
3495
3496#define H2C_HEADER_LEN 8
3497#define H2C_HDR_CAT GENMASK(1, 0)
3498#define H2C_HDR_CLASS GENMASK(7, 2)
3499#define H2C_HDR_FUNC GENMASK(15, 8)
3500#define H2C_HDR_DEL_TYPE GENMASK(19, 16)
3501#define H2C_HDR_H2C_SEQ GENMASK(31, 24)
3502#define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
3503#define H2C_HDR_REC_ACK BIT(14)
3504#define H2C_HDR_DONE_ACK BIT(15)
3505
3506#define FWCMD_TYPE_H2C 0
3507
edb89629
ZZY		 3508#define H2C_CAT_TEST 0x0
3509
3510/* CLASS 5 - FW STATUS TEST */
3511#define H2C_CL_FW_STATUS_TEST 0x5
3512#define H2C_FUNC_CPU_EXCEPTION 0x1
3513
e3ec7017
PKS		 3514#define H2C_CAT_MAC 0x1
3515
3516/* CLASS 0 - FW INFO */
3517#define H2C_CL_FW_INFO 0x0
3518#define H2C_FUNC_LOG_CFG 0x0
3519#define H2C_FUNC_MAC_GENERAL_PKT 0x1
3520
ee88d748
CYL		 3521/* CLASS 1 - WOW */
3522#define H2C_CL_MAC_WOW 0x1
3523#define H2C_FUNC_KEEP_ALIVE 0x0
3524#define H2C_FUNC_DISCONNECT_DETECT 0x1
3525#define H2C_FUNC_WOW_GLOBAL 0x2
3526#define H2C_FUNC_WAKEUP_CTRL 0x8
3527#define H2C_FUNC_WOW_CAM_UPD 0xC
3528
e3ec7017
PKS		 3529/* CLASS 2 - PS */
3530#define H2C_CL_MAC_PS 0x2
3531#define H2C_FUNC_MAC_LPS_PARM 0x0
f4a43c3b 3532#define H2C_FUNC_P2P_ACT 0x1
e3ec7017
PKS		 3533
3534/* CLASS 3 - FW download */
3535#define H2C_CL_MAC_FWDL 0x3
3536#define H2C_FUNC_MAC_FWHDR_DL 0x0
3537
3538/* CLASS 5 - Frame Exchange */
3539#define H2C_CL_MAC_FR_EXCHG 0x5
3540#define H2C_FUNC_MAC_CCTLINFO_UD 0x2
f7e76d13 3541#define H2C_FUNC_MAC_BCN_UPD 0x5
04b5983e 3542#define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
aa7f148b 3543#define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
e3ec7017
PKS		 3544
3545/* CLASS 6 - Address CAM */
3546#define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
3547#define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
3548
3549/* CLASS 8 - Media Status Report */
3550#define H2C_CL_MAC_MEDIA_RPT 0x8
3551#define H2C_FUNC_MAC_JOININFO 0x0
3552#define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
3553
3554/* CLASS 9 - FW offload */
3555#define H2C_CL_MAC_FW_OFLD 0x9
89590777 3556#define H2C_FUNC_PACKET_OFLD 0x1
e3ec7017
PKS		 3557#define H2C_FUNC_MAC_MACID_PAUSE 0x8
3558#define H2C_FUNC_USR_EDCA 0xF
f4a43c3b 3559#define H2C_FUNC_TSF32_TOGL 0x10
e3ec7017 3560#define H2C_FUNC_OFLD_CFG 0x14
89590777
PHH		 3561#define H2C_FUNC_ADD_SCANOFLD_CH 0x16
3562#define H2C_FUNC_SCANOFLD 0x17
9a785583 3563#define H2C_FUNC_PKT_DROP 0x1b
d2b6da24
PHH		 3564#define H2C_FUNC_CFG_BCNFLTR 0x1e
3565#define H2C_FUNC_OFLD_RSSI 0x1f
e3ec7017
PKS		 3566
3567/* CLASS 10 - Security CAM */
3568#define H2C_CL_MAC_SEC_CAM 0xa
3569#define H2C_FUNC_MAC_SEC_UPD 0x1
3570
3571/* CLASS 12 - BA CAM */
3572#define H2C_CL_BA_CAM 0xc
3573#define H2C_FUNC_MAC_BA_CAM 0x0
3574
ef9dff4c
ZZY		 3575/* CLASS 14 - MCC */
3576#define H2C_CL_MCC 0xe
3577enum rtw89_mcc_h2c_func {
3578 H2C_FUNC_ADD_MCC = 0x0,
3579 H2C_FUNC_START_MCC = 0x1,
3580 H2C_FUNC_STOP_MCC = 0x2,
3581 H2C_FUNC_DEL_MCC_GROUP = 0x3,
3582 H2C_FUNC_RESET_MCC_GROUP = 0x4,
3583 H2C_FUNC_MCC_REQ_TSF = 0x5,
3584 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
3585 H2C_FUNC_MCC_SYNC = 0x7,
3586 H2C_FUNC_MCC_SET_DURATION = 0x8,
3587
3588 NUM_OF_RTW89_MCC_H2C_FUNC,
3589};
3590
3591#define RTW89_MCC_WAIT_COND(group, func) \
3592 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
3593
e3ec7017
PKS		 3594#define H2C_CAT_OUTSRC 0x2
3595
3596#define H2C_CL_OUTSRC_RA 0x1
3597#define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
3598
3599#define H2C_CL_OUTSRC_RF_REG_A 0x8
3600#define H2C_CL_OUTSRC_RF_REG_B 0x9
16b44ed0
PKS		 3601#define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
3602#define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
3603
3604struct rtw89_fw_h2c_rf_get_mccch {
3605 __le32 ch_0;
3606 __le32 ch_1;
3607 __le32 band_0;
3608 __le32 band_1;
3609 __le32 current_channel;
3610 __le32 current_band_type;
3611} __packed;
e3ec7017 3612
9f8004bf
ZZY		 3613#define RTW89_FW_RSVD_PLE_SIZE 0x800
3614
e77d3f8b 3615#define RTW89_WCPU_BASE_MASK GENMASK(27, 0)
f5e24684
ZZY		 3616
3617#define RTW89_FW_BACKTRACE_INFO_SIZE 8
3618#define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
3619 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
3620
3621#define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
3622#define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
3623
e3ec7017
PKS		 3624int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
3625int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
13eb07e0
ZZY		 3626const struct firmware *
3627rtw89_early_fw_feature_recognize(struct device *device,
3628 const struct rtw89_chip_info *chip,
ffde7f34
PKS		 3629 struct rtw89_fw_info *early_fw,
3630 int *used_fw_format);
e3ec7017 3631int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type);
b80ad23a 3632void rtw89_load_firmware_work(struct work_struct *work);
e3ec7017
PKS		 3633void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
3634int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
3635void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3636 u8 type, u8 cat, u8 class, u8 func,
3637 bool rack, bool dack, u32 len);
742c470b
PKS		 3638int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
3639 struct rtw89_vif *rtwvif);
e3ec7017
PKS		 3640int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
3641 struct ieee80211_vif *vif,
3642 struct ieee80211_sta *sta);
3643int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
3644 struct rtw89_sta *rtwsta);
5a8e06e4
PKS		 3645int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
3646 struct rtw89_sta *rtwsta);
f7e76d13
PKS		 3647int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
3648 struct rtw89_vif *rtwvif);
e45a9e62 3649int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
40822e07 3650 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
04b5983e
PKS		 3651int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
3652 struct rtw89_vif *rtwvif,
3653 struct rtw89_sta *rtwsta);
e3ec7017
PKS		 3654void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
3655void rtw89_fw_c2h_work(struct work_struct *work);
8b252070
PKS		 3656int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
3657 struct rtw89_vif *rtwvif,
ff66964a 3658 struct rtw89_sta *rtwsta,
8b252070 3659 enum rtw89_upd_mode upd_mode);
e3ec7017 3660int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
742c470b 3661 struct rtw89_sta *rtwsta, bool dis_conn);
e3ec7017
PKS		 3662int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
3663 bool pause);
3664int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3665 u8 ac, u32 val);
3666int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
d2b6da24
PHH		 3667int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
3668 struct ieee80211_vif *vif,
3669 bool connect);
3670int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
3671 struct rtw89_rx_phy_ppdu *phy_ppdu);
e3ec7017
PKS		 3672int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
3673int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev);
3674int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev);
e390cf2e 3675int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev);
5049964c 3676int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev);
e3ec7017 3677int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev);
a2c0ce5d 3678int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev);
e3ec7017 3679int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev);
89590777
PHH		 3680int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
3681int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
3682 struct sk_buff *skb_ofld);
3683int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
3684 struct list_head *chan_list);
3685int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
3686 struct rtw89_scan_option *opt,
3687 struct rtw89_vif *vif);
e3ec7017
PKS		 3688int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
3689 struct rtw89_fw_h2c_rf_reg_info *info,
3690 u16 len, u8 page);
16b44ed0 3691int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
e3ec7017
PKS		 3692int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
3693 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
3694 bool rack, bool dack);
3695int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
3696void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
3697void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
5c12bb66
CYL		 3698int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3699 u8 macid);
3700void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
3701 struct rtw89_vif *rtwvif, bool notify_fw);
3702void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
3ffbb5a8
PKS		 3703int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3704 bool valid, struct ieee80211_ampdu_params *params);
8b1b4730 3705void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev);
3ffbb5a8 3706
e3ec7017
PKS		 3707int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
3708 struct rtw89_lps_parm *lps_param);
a95bd62e
PKS		 3709struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
3710struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
e3ec7017
PKS		 3711int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
3712 struct rtw89_mac_h2c_info *h2c_info,
3713 struct rtw89_mac_c2h_info *c2h_info);
3714int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
3715void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
89590777
PHH		 3716void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3717 struct ieee80211_scan_request *req);
3718void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3719 bool aborted);
3720int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3721 bool enable);
89590777 3722void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
edb89629 3723int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
9a785583
ZZY		 3724int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
3725 const struct rtw89_pkt_drop_params *params);
f4a43c3b
DSY		 3726int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3727 struct ieee80211_p2p_noa_desc *desc,
3728 u8 act, u8 noa_id);
3729int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3730 bool en);
ee88d748
CYL		 3731int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3732 bool enable);
3733int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3734 struct rtw89_vif *rtwvif, bool enable);
3735int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3736 bool enable);
3737int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
3738 struct rtw89_vif *rtwvif, bool enable);
3739int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3740 bool enable);
3741int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3742 struct rtw89_vif *rtwvif, bool enable);
d2b68e95
CYL		 3743int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
3744 struct rtw89_wow_cam_info *cam_info);
c008c4b0
ZZY		 3745int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
3746 const struct rtw89_fw_mcc_add_req *p);
3747int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
3748 const struct rtw89_fw_mcc_start_req *p);
3749int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3750 bool prev_groups);
3751int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
3752 bool prev_groups);
3753int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
3754int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
3755 const struct rtw89_fw_mcc_tsf_req *req,
3756 struct rtw89_mac_mcc_tsf_rpt *rpt);
3757int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3758 u8 *bitmap);
3759int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
3760 u8 target, u8 offset);
3761int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
3762 const struct rtw89_fw_mcc_duration *p);
3763
8b1b4730
PKS		 3764static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
3765{
3766 const struct rtw89_chip_info *chip = rtwdev->chip;
3767
3768 if (chip->bacam_v1)
3769 rtw89_fw_h2c_init_ba_cam_v1(rtwdev);
3770}
3771
e3ec7017 3772#endif
Linux 6.x block layer and io_uring tree(s)