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wifi: rtw89: introduce entity mode and its recalculated prototype
[linux-block.git] / drivers / net / wireless / realtek / rtw89 / core.h
CommitLineData
e3ec7017
PKS		 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_CORE_H__
6#define __RTW89_CORE_H__
7
8#include <linux/average.h>
9#include <linux/bitfield.h>
10#include <linux/firmware.h>
11#include <linux/iopoll.h>
12#include <linux/workqueue.h>
13#include <net/mac80211.h>
14
15struct rtw89_dev;
4a9e48ac 16struct rtw89_pci_info;
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PKS		 17
18extern const struct ieee80211_ops rtw89_ops;
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PKS		 19
20#define MASKBYTE0 0xff
21#define MASKBYTE1 0xff00
22#define MASKBYTE2 0xff0000
23#define MASKBYTE3 0xff000000
24#define MASKBYTE4 0xff00000000ULL
25#define MASKHWORD 0xffff0000
26#define MASKLWORD 0x0000ffff
27#define MASKDWORD 0xffffffff
28#define RFREG_MASK 0xfffff
29#define INV_RF_DATA 0xffffffff
30
31#define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
679955d5 32#define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
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PKS		 33#define CFO_TRACK_MAX_USER 64
34#define MAX_RSSI 110
35#define RSSI_FACTOR 1
36#define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
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PKS		 37
38#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
39#define RTW89_HTC_VARIANT_HE 3
40#define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
41#define RTW89_HTC_VARIANT_HE_CID_OM 1
42#define RTW89_HTC_VARIANT_HE_CID_CAS 6
43#define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
44
45#define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
46enum htc_om_channel_width {
47 HTC_OM_CHANNEL_WIDTH_20 = 0,
48 HTC_OM_CHANNEL_WIDTH_40 = 1,
49 HTC_OM_CHANNEL_WIDTH_80 = 2,
50 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
51};
52#define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
53#define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
54#define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
55#define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
56#define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
57#define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
58
5165f168
PHH		 59#define RTW89_TF_PAD GENMASK(11, 0)
60#define RTW89_TF_BASIC_USER_INFO_SZ 6
61
62#define RTW89_GET_TF_USER_INFO_AID12(data) \
63 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
64#define RTW89_GET_TF_USER_INFO_RUA(data) \
65 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
66#define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
67 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
68
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PKS		 69enum rtw89_subband {
70 RTW89_CH_2G = 0,
71 RTW89_CH_5G_BAND_1 = 1,
72 /* RTW89_CH_5G_BAND_2 = 2, unused */
73 RTW89_CH_5G_BAND_3 = 3,
74 RTW89_CH_5G_BAND_4 = 4,
75
8e438ad4
ZZY		 76 RTW89_CH_6G_BAND_IDX0, /* Low */
77 RTW89_CH_6G_BAND_IDX1, /* Low */
78 RTW89_CH_6G_BAND_IDX2, /* Mid */
79 RTW89_CH_6G_BAND_IDX3, /* Mid */
80 RTW89_CH_6G_BAND_IDX4, /* High */
81 RTW89_CH_6G_BAND_IDX5, /* High */
82 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
83 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
84
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PKS		 85 RTW89_SUBBAND_NR,
86};
87
e6b17cbd
PKS		 88enum rtw89_gain_offset {
89 RTW89_GAIN_OFFSET_2G_CCK,
90 RTW89_GAIN_OFFSET_2G_OFDM,
91 RTW89_GAIN_OFFSET_5G_LOW,
92 RTW89_GAIN_OFFSET_5G_MID,
93 RTW89_GAIN_OFFSET_5G_HIGH,
94
95 RTW89_GAIN_OFFSET_NR,
96};
97
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PKS		 98enum rtw89_hci_type {
99 RTW89_HCI_TYPE_PCIE,
100 RTW89_HCI_TYPE_USB,
101 RTW89_HCI_TYPE_SDIO,
102};
103
104enum rtw89_core_chip_id {
105 RTL8852A,
106 RTL8852B,
107 RTL8852C,
108};
109
110enum rtw89_cv {
111 CHIP_CAV,
112 CHIP_CBV,
113 CHIP_CCV,
114 CHIP_CDV,
115 CHIP_CEV,
116 CHIP_CFV,
117 CHIP_CV_MAX,
118 CHIP_CV_INVALID = CHIP_CV_MAX,
119};
120
121enum rtw89_core_tx_type {
122 RTW89_CORE_TX_TYPE_DATA,
123 RTW89_CORE_TX_TYPE_MGMT,
124 RTW89_CORE_TX_TYPE_FWCMD,
125};
126
127enum rtw89_core_rx_type {
128 RTW89_CORE_RX_TYPE_WIFI = 0,
129 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
130 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
131 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
132 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
133 RTW89_CORE_RX_TYPE_SS2FW = 5,
134 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
135 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
136 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
137 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
138 RTW89_CORE_RX_TYPE_C2H = 10,
139 RTW89_CORE_RX_TYPE_CSI = 11,
140 RTW89_CORE_RX_TYPE_CQI = 12,
a95bd62e
PKS		 141 RTW89_CORE_RX_TYPE_H2C = 13,
142 RTW89_CORE_RX_TYPE_FWDL = 14,
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PKS		 143};
144
145enum rtw89_txq_flags {
146 RTW89_TXQ_F_AMPDU = 0,
147 RTW89_TXQ_F_BLOCK_BA = 1,
679955d5 148 RTW89_TXQ_F_FORBID_BA = 2,
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PKS		 149};
150
151enum rtw89_net_type {
152 RTW89_NET_TYPE_NO_LINK = 0,
153 RTW89_NET_TYPE_AD_HOC = 1,
154 RTW89_NET_TYPE_INFRA = 2,
155 RTW89_NET_TYPE_AP_MODE = 3,
156};
157
158enum rtw89_wifi_role {
159 RTW89_WIFI_ROLE_NONE,
160 RTW89_WIFI_ROLE_STATION,
161 RTW89_WIFI_ROLE_AP,
162 RTW89_WIFI_ROLE_AP_VLAN,
163 RTW89_WIFI_ROLE_ADHOC,
164 RTW89_WIFI_ROLE_ADHOC_MASTER,
165 RTW89_WIFI_ROLE_MESH_POINT,
166 RTW89_WIFI_ROLE_MONITOR,
167 RTW89_WIFI_ROLE_P2P_DEVICE,
168 RTW89_WIFI_ROLE_P2P_CLIENT,
169 RTW89_WIFI_ROLE_P2P_GO,
170 RTW89_WIFI_ROLE_NAN,
171 RTW89_WIFI_ROLE_MLME_MAX
172};
173
174enum rtw89_upd_mode {
8b252070
PKS		 175 RTW89_ROLE_CREATE,
176 RTW89_ROLE_REMOVE,
177 RTW89_ROLE_TYPE_CHANGE,
178 RTW89_ROLE_INFO_CHANGE,
179 RTW89_ROLE_CON_DISCONN
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PKS		 180};
181
182enum rtw89_self_role {
183 RTW89_SELF_ROLE_CLIENT,
184 RTW89_SELF_ROLE_AP,
185 RTW89_SELF_ROLE_AP_CLIENT
186};
187
188enum rtw89_msk_sO_el {
189 RTW89_NO_MSK,
190 RTW89_SMA,
191 RTW89_TMA,
192 RTW89_BSSID
193};
194
195enum rtw89_sch_tx_sel {
196 RTW89_SCH_TX_SEL_ALL,
197 RTW89_SCH_TX_SEL_HIQ,
198 RTW89_SCH_TX_SEL_MG0,
199 RTW89_SCH_TX_SEL_MACID,
200};
201
202/* RTW89_ADDR_CAM_SEC_NONE : not enabled
203 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
204 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
205 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
206 */
207enum rtw89_add_cam_sec_mode {
208 RTW89_ADDR_CAM_SEC_NONE = 0,
209 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
210 RTW89_ADDR_CAM_SEC_NORMAL = 2,
211 RTW89_ADDR_CAM_SEC_4GROUP = 3,
212};
213
214enum rtw89_sec_key_type {
215 RTW89_SEC_KEY_TYPE_NONE = 0,
216 RTW89_SEC_KEY_TYPE_WEP40 = 1,
217 RTW89_SEC_KEY_TYPE_WEP104 = 2,
218 RTW89_SEC_KEY_TYPE_TKIP = 3,
219 RTW89_SEC_KEY_TYPE_WAPI = 4,
220 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
221 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
222 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
223 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
224 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
225 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
226};
227
228enum rtw89_port {
229 RTW89_PORT_0 = 0,
230 RTW89_PORT_1 = 1,
231 RTW89_PORT_2 = 2,
232 RTW89_PORT_3 = 3,
233 RTW89_PORT_4 = 4,
234 RTW89_PORT_NUM
235};
236
237enum rtw89_band {
238 RTW89_BAND_2G = 0,
239 RTW89_BAND_5G = 1,
0237f65a 240 RTW89_BAND_6G = 2,
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PKS		 241 RTW89_BAND_MAX,
242};
243
244enum rtw89_hw_rate {
245 RTW89_HW_RATE_CCK1 = 0x0,
246 RTW89_HW_RATE_CCK2 = 0x1,
247 RTW89_HW_RATE_CCK5_5 = 0x2,
248 RTW89_HW_RATE_CCK11 = 0x3,
249 RTW89_HW_RATE_OFDM6 = 0x4,
250 RTW89_HW_RATE_OFDM9 = 0x5,
251 RTW89_HW_RATE_OFDM12 = 0x6,
252 RTW89_HW_RATE_OFDM18 = 0x7,
253 RTW89_HW_RATE_OFDM24 = 0x8,
254 RTW89_HW_RATE_OFDM36 = 0x9,
255 RTW89_HW_RATE_OFDM48 = 0xA,
256 RTW89_HW_RATE_OFDM54 = 0xB,
257 RTW89_HW_RATE_MCS0 = 0x80,
258 RTW89_HW_RATE_MCS1 = 0x81,
259 RTW89_HW_RATE_MCS2 = 0x82,
260 RTW89_HW_RATE_MCS3 = 0x83,
261 RTW89_HW_RATE_MCS4 = 0x84,
262 RTW89_HW_RATE_MCS5 = 0x85,
263 RTW89_HW_RATE_MCS6 = 0x86,
264 RTW89_HW_RATE_MCS7 = 0x87,
265 RTW89_HW_RATE_MCS8 = 0x88,
266 RTW89_HW_RATE_MCS9 = 0x89,
267 RTW89_HW_RATE_MCS10 = 0x8A,
268 RTW89_HW_RATE_MCS11 = 0x8B,
269 RTW89_HW_RATE_MCS12 = 0x8C,
270 RTW89_HW_RATE_MCS13 = 0x8D,
271 RTW89_HW_RATE_MCS14 = 0x8E,
272 RTW89_HW_RATE_MCS15 = 0x8F,
273 RTW89_HW_RATE_MCS16 = 0x90,
274 RTW89_HW_RATE_MCS17 = 0x91,
275 RTW89_HW_RATE_MCS18 = 0x92,
276 RTW89_HW_RATE_MCS19 = 0x93,
277 RTW89_HW_RATE_MCS20 = 0x94,
278 RTW89_HW_RATE_MCS21 = 0x95,
279 RTW89_HW_RATE_MCS22 = 0x96,
280 RTW89_HW_RATE_MCS23 = 0x97,
281 RTW89_HW_RATE_MCS24 = 0x98,
282 RTW89_HW_RATE_MCS25 = 0x99,
283 RTW89_HW_RATE_MCS26 = 0x9A,
284 RTW89_HW_RATE_MCS27 = 0x9B,
285 RTW89_HW_RATE_MCS28 = 0x9C,
286 RTW89_HW_RATE_MCS29 = 0x9D,
287 RTW89_HW_RATE_MCS30 = 0x9E,
288 RTW89_HW_RATE_MCS31 = 0x9F,
289 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
290 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
291 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
292 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
293 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
294 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
295 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
296 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
297 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
298 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
299 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
300 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
301 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
302 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
303 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
304 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
305 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
306 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
307 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
308 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
309 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
310 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
311 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
312 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
313 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
314 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
315 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
316 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
317 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
318 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
319 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
320 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
321 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
322 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
323 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
324 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
325 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
326 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
327 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
328 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
329 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
330 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
331 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
332 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
333 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
334 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
335 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
336 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
337 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
338 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
339 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
340 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
341 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
342 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
343 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
344 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
345 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
346 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
347 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
348 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
349 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
350 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
351 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
352 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
353 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
354 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
355 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
356 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
357 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
358 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
359 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
360 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
361 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
362 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
363 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
364 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
365 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
366 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
367 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
368 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
369 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
370 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
371 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
372 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
373 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
374 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
375 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
376 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
377 RTW89_HW_RATE_NR,
378
379 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
380 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
381};
382
383/* 2G channels,
384 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
385 */
386#define RTW89_2G_CH_NUM 14
387
388/* 5G channels,
389 * 36, 38, 40, 42, 44, 46, 48, 50,
390 * 52, 54, 56, 58, 60, 62, 64,
391 * 100, 102, 104, 106, 108, 110, 112, 114,
392 * 116, 118, 120, 122, 124, 126, 128, 130,
393 * 132, 134, 136, 138, 140, 142, 144,
394 * 149, 151, 153, 155, 157, 159, 161, 163,
395 * 165, 167, 169, 171, 173, 175, 177
396 */
397#define RTW89_5G_CH_NUM 53
398
ac74f016
ZZY		 399/* 6G channels,
400 * 1, 3, 5, 7, 9, 11, 13, 15,
401 * 17, 19, 21, 23, 25, 27, 29, 33,
402 * 35, 37, 39, 41, 43, 45, 47, 49,
403 * 51, 53, 55, 57, 59, 61, 65, 67,
404 * 69, 71, 73, 75, 77, 79, 81, 83,
405 * 85, 87, 89, 91, 93, 97, 99, 101,
406 * 103, 105, 107, 109, 111, 113, 115, 117,
407 * 119, 121, 123, 125, 129, 131, 133, 135,
408 * 137, 139, 141, 143, 145, 147, 149, 151,
409 * 153, 155, 157, 161, 163, 165, 167, 169,
410 * 171, 173, 175, 177, 179, 181, 183, 185,
411 * 187, 189, 193, 195, 197, 199, 201, 203,
412 * 205, 207, 209, 211, 213, 215, 217, 219,
413 * 221, 225, 227, 229, 231, 233, 235, 237,
414 * 239, 241, 243, 245, 247, 249, 251, 253,
415 */
416#define RTW89_6G_CH_NUM 120
417
e3ec7017
PKS		 418enum rtw89_rate_section {
419 RTW89_RS_CCK,
420 RTW89_RS_OFDM,
421 RTW89_RS_MCS, /* for HT/VHT/HE */
422 RTW89_RS_HEDCM,
423 RTW89_RS_OFFSET,
424 RTW89_RS_MAX,
425 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
342475ac 426 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
e3ec7017
PKS		 427};
428
429enum rtw89_rate_max {
430 RTW89_RATE_CCK_MAX = 4,
431 RTW89_RATE_OFDM_MAX = 8,
432 RTW89_RATE_MCS_MAX = 12,
433 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */
434 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
435};
436
437enum rtw89_nss {
438 RTW89_NSS_1 = 0,
439 RTW89_NSS_2 = 1,
440 /* HE DCM only support 1ss and 2ss */
441 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1,
442 RTW89_NSS_3 = 2,
443 RTW89_NSS_4 = 3,
444 RTW89_NSS_MAX,
445};
446
447enum rtw89_ntx {
448 RTW89_1TX = 0,
449 RTW89_2TX = 1,
450 RTW89_NTX_NUM,
451};
452
453enum rtw89_beamforming_type {
454 RTW89_NONBF = 0,
455 RTW89_BF = 1,
456 RTW89_BF_NUM,
457};
458
459enum rtw89_regulation_type {
460 RTW89_WW = 0,
461 RTW89_ETSI = 1,
462 RTW89_FCC = 2,
463 RTW89_MKK = 3,
464 RTW89_NA = 4,
465 RTW89_IC = 5,
466 RTW89_KCC = 6,
54257714
ZZY		 467 RTW89_ACMA = 7,
468 RTW89_NCC = 8,
469 RTW89_MEXICO = 9,
470 RTW89_CHILE = 10,
e3ec7017
PKS		 471 RTW89_UKRAINE = 11,
472 RTW89_CN = 12,
54257714 473 RTW89_QATAR = 13,
5a0e776b 474 RTW89_UK = 14,
e3ec7017
PKS		 475 RTW89_REGD_NUM,
476};
477
e3ec7017
PKS		 478struct rtw89_txpwr_byrate {
479 s8 cck[RTW89_RATE_CCK_MAX];
480 s8 ofdm[RTW89_RATE_OFDM_MAX];
481 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];
482 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];
483 s8 offset[RTW89_RATE_OFFSET_MAX];
484};
485
486enum rtw89_bandwidth_section_num {
487 RTW89_BW20_SEC_NUM = 8,
488 RTW89_BW40_SEC_NUM = 4,
489 RTW89_BW80_SEC_NUM = 2,
490};
491
492struct rtw89_txpwr_limit {
493 s8 cck_20m[RTW89_BF_NUM];
494 s8 cck_40m[RTW89_BF_NUM];
495 s8 ofdm[RTW89_BF_NUM];
496 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
497 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
498 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
499 s8 mcs_160m[RTW89_BF_NUM];
500 s8 mcs_40m_0p5[RTW89_BF_NUM];
501 s8 mcs_40m_2p5[RTW89_BF_NUM];
502};
503
504#define RTW89_RU_SEC_NUM 8
505
506struct rtw89_txpwr_limit_ru {
507 s8 ru26[RTW89_RU_SEC_NUM];
508 s8 ru52[RTW89_RU_SEC_NUM];
509 s8 ru106[RTW89_RU_SEC_NUM];
510};
511
512struct rtw89_rate_desc {
513 enum rtw89_nss nss;
514 enum rtw89_rate_section rs;
515 u8 idx;
516};
517
518#define PHY_STS_HDR_LEN 8
519#define RF_PATH_MAX 4
520#define RTW89_MAX_PPDU_CNT 8
521struct rtw89_rx_phy_ppdu {
522 u8 *buf;
523 u32 len;
524 u8 rssi_avg;
525 s8 rssi[RF_PATH_MAX];
526 u8 mac_id;
eb4e52b3
PHH		 527 u8 chan_idx;
528 u8 ie;
529 u16 rate;
e3ec7017
PKS		 530 bool to_self;
531 bool valid;
532};
533
534enum rtw89_mac_idx {
535 RTW89_MAC_0 = 0,
536 RTW89_MAC_1 = 1,
537};
538
539enum rtw89_phy_idx {
540 RTW89_PHY_0 = 0,
541 RTW89_PHY_1 = 1,
542 RTW89_PHY_MAX
543};
544
cbb145b9
ZZY		 545enum rtw89_sub_entity_idx {
546 RTW89_SUB_ENTITY_0 = 0,
547
548 NUM_OF_RTW89_SUB_ENTITY,
549};
550
e3ec7017
PKS		 551enum rtw89_rf_path {
552 RF_PATH_A = 0,
553 RF_PATH_B = 1,
554 RF_PATH_C = 2,
555 RF_PATH_D = 3,
556 RF_PATH_AB,
557 RF_PATH_AC,
558 RF_PATH_AD,
559 RF_PATH_BC,
560 RF_PATH_BD,
561 RF_PATH_CD,
562 RF_PATH_ABC,
563 RF_PATH_ABD,
564 RF_PATH_ACD,
565 RF_PATH_BCD,
566 RF_PATH_ABCD,
567};
568
569enum rtw89_rf_path_bit {
570 RF_A = BIT(0),
571 RF_B = BIT(1),
572 RF_C = BIT(2),
573 RF_D = BIT(3),
574
575 RF_AB = (RF_A | RF_B),
576 RF_AC = (RF_A | RF_C),
577 RF_AD = (RF_A | RF_D),
578 RF_BC = (RF_B | RF_C),
579 RF_BD = (RF_B | RF_D),
580 RF_CD = (RF_C | RF_D),
581
582 RF_ABC = (RF_A | RF_B | RF_C),
583 RF_ABD = (RF_A | RF_B | RF_D),
584 RF_ACD = (RF_A | RF_C | RF_D),
585 RF_BCD = (RF_B | RF_C | RF_D),
586
587 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
588};
589
590enum rtw89_bandwidth {
591 RTW89_CHANNEL_WIDTH_20 = 0,
592 RTW89_CHANNEL_WIDTH_40 = 1,
593 RTW89_CHANNEL_WIDTH_80 = 2,
594 RTW89_CHANNEL_WIDTH_160 = 3,
595 RTW89_CHANNEL_WIDTH_80_80 = 4,
596 RTW89_CHANNEL_WIDTH_5 = 5,
597 RTW89_CHANNEL_WIDTH_10 = 6,
598};
599
600enum rtw89_ps_mode {
601 RTW89_PS_MODE_NONE = 0,
602 RTW89_PS_MODE_RFOFF = 1,
603 RTW89_PS_MODE_CLK_GATED = 2,
604 RTW89_PS_MODE_PWR_GATED = 3,
605};
606
e3ec7017 607#define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
94b70caf 608#define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
ac74f016 609#define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
aa7f148b 610#define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
e3ec7017
PKS		 611
612enum rtw89_ru_bandwidth {
613 RTW89_RU26 = 0,
614 RTW89_RU52 = 1,
615 RTW89_RU106 = 2,
616 RTW89_RU_NUM,
617};
618
619enum rtw89_sc_offset {
620 RTW89_SC_DONT_CARE = 0,
621 RTW89_SC_20_UPPER = 1,
622 RTW89_SC_20_LOWER = 2,
623 RTW89_SC_20_UPMOST = 3,
624 RTW89_SC_20_LOWEST = 4,
e715f10f
PKS		 625 RTW89_SC_20_UP2X = 5,
626 RTW89_SC_20_LOW2X = 6,
627 RTW89_SC_20_UP3X = 7,
628 RTW89_SC_20_LOW3X = 8,
e3ec7017
PKS		 629 RTW89_SC_40_UPPER = 9,
630 RTW89_SC_40_LOWER = 10,
631};
632
3e5831ca
ZZY		 633struct rtw89_chan {
634 u8 channel;
3e5831ca
ZZY		 635 u8 primary_channel;
636 enum rtw89_band band_type;
637 enum rtw89_bandwidth band_width;
bb8152b3
ZZY		 638
639 /* The follow-up are derived from the above. We must ensure that it
640 * is assigned correctly in rtw89_chan_create() if new one is added.
641 */
642 u32 freq;
3e5831ca
ZZY		 643 enum rtw89_subband subband_type;
644 enum rtw89_sc_offset pri_ch_idx;
e3ec7017
PKS		 645};
646
cbb145b9
ZZY		 647struct rtw89_chan_rcd {
648 u8 prev_primary_channel;
649 enum rtw89_band prev_band_type;
650};
651
e3ec7017 652struct rtw89_channel_help_params {
d780f926 653 u32 tx_en;
e3ec7017
PKS		 654};
655
656struct rtw89_port_reg {
657 u32 port_cfg;
658 u32 tbtt_prohib;
659 u32 bcn_area;
660 u32 bcn_early;
661 u32 tbtt_early;
662 u32 tbtt_agg;
663 u32 bcn_space;
664 u32 bcn_forcetx;
665 u32 bcn_err_cnt;
666 u32 bcn_err_flag;
667 u32 dtim_ctrl;
668 u32 tbtt_shift;
669 u32 bcn_cnt_tmr;
670 u32 tsftr_l;
671 u32 tsftr_h;
672};
673
674struct rtw89_txwd_body {
675 __le32 dword0;
676 __le32 dword1;
677 __le32 dword2;
678 __le32 dword3;
679 __le32 dword4;
680 __le32 dword5;
681} __packed;
682
f59acdde
PKS		 683struct rtw89_txwd_body_v1 {
684 __le32 dword0;
685 __le32 dword1;
686 __le32 dword2;
687 __le32 dword3;
688 __le32 dword4;
689 __le32 dword5;
690 __le32 dword6;
691 __le32 dword7;
692} __packed;
693
e3ec7017
PKS		 694struct rtw89_txwd_info {
695 __le32 dword0;
696 __le32 dword1;
697 __le32 dword2;
698 __le32 dword3;
699 __le32 dword4;
700 __le32 dword5;
701} __packed;
702
703struct rtw89_rx_desc_info {
704 u16 pkt_size;
705 u8 pkt_type;
706 u8 drv_info_size;
707 u8 shift;
708 u8 wl_hd_iv_len;
709 bool long_rxdesc;
710 bool bb_sel;
711 bool mac_info_valid;
712 u16 data_rate;
713 u8 gi_ltf;
714 u8 bw;
715 u32 free_run_cnt;
716 u8 user_id;
717 bool sr_en;
718 u8 ppdu_cnt;
719 u8 ppdu_type;
720 bool icv_err;
721 bool crc32_err;
722 bool hw_dec;
723 bool sw_dec;
724 bool addr1_match;
725 u8 frag;
726 u16 seq;
727 u8 frame_type;
728 u8 rx_pl_id;
729 bool addr_cam_valid;
730 u8 addr_cam_id;
731 u8 sec_cam_id;
732 u8 mac_id;
733 u16 offset;
734 bool ready;
735};
736
737struct rtw89_rxdesc_short {
738 __le32 dword0;
739 __le32 dword1;
740 __le32 dword2;
741 __le32 dword3;
742} __packed;
743
744struct rtw89_rxdesc_long {
745 __le32 dword0;
746 __le32 dword1;
747 __le32 dword2;
748 __le32 dword3;
749 __le32 dword4;
750 __le32 dword5;
751 __le32 dword6;
752 __le32 dword7;
753} __packed;
754
755struct rtw89_tx_desc_info {
756 u16 pkt_size;
757 u8 wp_offset;
9eecaec2 758 u8 mac_id;
e3ec7017
PKS		 759 u8 qsel;
760 u8 ch_dma;
761 u8 hdr_llc_len;
762 bool is_bmc;
763 bool en_wd_info;
764 bool wd_page;
765 bool use_rate;
766 bool dis_data_fb;
767 bool tid_indicate;
768 bool agg_en;
769 bool bk;
770 u8 ampdu_density;
771 u8 ampdu_num;
772 bool sec_en;
6d5b5d62 773 u8 addr_info_nr;
79a6c9a4 774 u8 sec_keyid;
e3ec7017
PKS		 775 u8 sec_type;
776 u8 sec_cam_idx;
79a6c9a4 777 u8 sec_seq[6];
e3ec7017
PKS		 778 u16 data_rate;
779 u16 data_retry_lowest_rate;
780 bool fw_dl;
781 u16 seq;
782 bool a_ctrl_bsr;
91644020
PKS		 783 u8 hw_ssn_sel;
784#define RTW89_MGMT_HW_SSN_SEL 1
785 u8 hw_seq_mode;
786#define RTW89_MGMT_HW_SEQ_MODE 1
11d261f2 787 bool hiq;
9eecaec2 788 u8 port;
e3ec7017
PKS		 789};
790
791struct rtw89_core_tx_request {
792 enum rtw89_core_tx_type tx_type;
793
794 struct sk_buff *skb;
795 struct ieee80211_vif *vif;
796 struct ieee80211_sta *sta;
797 struct rtw89_tx_desc_info desc_info;
798};
799
800struct rtw89_txq {
801 struct list_head list;
802 unsigned long flags;
803 int wait_cnt;
804};
805
806struct rtw89_mac_ax_gnt {
807 u8 gnt_bt_sw_en;
808 u8 gnt_bt;
809 u8 gnt_wl_sw_en;
810 u8 gnt_wl;
811};
812
813#define RTW89_MAC_AX_COEX_GNT_NR 2
814struct rtw89_mac_ax_coex_gnt {
815 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
816};
817
818enum rtw89_btc_ncnt {
819 BTC_NCNT_POWER_ON = 0x0,
820 BTC_NCNT_POWER_OFF,
821 BTC_NCNT_INIT_COEX,
822 BTC_NCNT_SCAN_START,
823 BTC_NCNT_SCAN_FINISH,
824 BTC_NCNT_SPECIAL_PACKET,
825 BTC_NCNT_SWITCH_BAND,
826 BTC_NCNT_RFK_TIMEOUT,
827 BTC_NCNT_SHOW_COEX_INFO,
828 BTC_NCNT_ROLE_INFO,
829 BTC_NCNT_CONTROL,
830 BTC_NCNT_RADIO_STATE,
831 BTC_NCNT_CUSTOMERIZE,
832 BTC_NCNT_WL_RFK,
833 BTC_NCNT_WL_STA,
834 BTC_NCNT_FWINFO,
835 BTC_NCNT_TIMER,
836 BTC_NCNT_NUM
837};
838
839enum rtw89_btc_btinfo {
840 BTC_BTINFO_L0 = 0,
841 BTC_BTINFO_L1,
842 BTC_BTINFO_L2,
843 BTC_BTINFO_L3,
844 BTC_BTINFO_H0,
845 BTC_BTINFO_H1,
846 BTC_BTINFO_H2,
847 BTC_BTINFO_H3,
848 BTC_BTINFO_MAX
849};
850
851enum rtw89_btc_dcnt {
852 BTC_DCNT_RUN = 0x0,
853 BTC_DCNT_CX_RUNINFO,
854 BTC_DCNT_RPT,
855 BTC_DCNT_RPT_FREEZE,
856 BTC_DCNT_CYCLE,
857 BTC_DCNT_CYCLE_FREEZE,
858 BTC_DCNT_W1,
859 BTC_DCNT_W1_FREEZE,
860 BTC_DCNT_B1,
861 BTC_DCNT_B1_FREEZE,
862 BTC_DCNT_TDMA_NONSYNC,
863 BTC_DCNT_SLOT_NONSYNC,
864 BTC_DCNT_BTCNT_FREEZE,
865 BTC_DCNT_WL_SLOT_DRIFT,
866 BTC_DCNT_WL_STA_LAST,
867 BTC_DCNT_NUM,
868};
869
870enum rtw89_btc_wl_state_cnt {
871 BTC_WCNT_SCANAP = 0x0,
872 BTC_WCNT_DHCP,
873 BTC_WCNT_EAPOL,
874 BTC_WCNT_ARP,
875 BTC_WCNT_SCBDUPDATE,
876 BTC_WCNT_RFK_REQ,
877 BTC_WCNT_RFK_GO,
878 BTC_WCNT_RFK_REJECT,
879 BTC_WCNT_RFK_TIMEOUT,
880 BTC_WCNT_CH_UPDATE,
881 BTC_WCNT_NUM
882};
883
884enum rtw89_btc_bt_state_cnt {
885 BTC_BCNT_RETRY = 0x0,
886 BTC_BCNT_REINIT,
887 BTC_BCNT_REENABLE,
888 BTC_BCNT_SCBDREAD,
889 BTC_BCNT_RELINK,
890 BTC_BCNT_IGNOWL,
891 BTC_BCNT_INQPAG,
892 BTC_BCNT_INQ,
893 BTC_BCNT_PAGE,
894 BTC_BCNT_ROLESW,
895 BTC_BCNT_AFH,
896 BTC_BCNT_INFOUPDATE,
897 BTC_BCNT_INFOSAME,
898 BTC_BCNT_SCBDUPDATE,
899 BTC_BCNT_HIPRI_TX,
900 BTC_BCNT_HIPRI_RX,
901 BTC_BCNT_LOPRI_TX,
902 BTC_BCNT_LOPRI_RX,
8c7e9ceb 903 BTC_BCNT_POLUT,
e3ec7017
PKS		 904 BTC_BCNT_RATECHG,
905 BTC_BCNT_NUM
906};
907
908enum rtw89_btc_bt_profile {
909 BTC_BT_NOPROFILE = 0,
910 BTC_BT_HFP = BIT(0),
911 BTC_BT_HID = BIT(1),
912 BTC_BT_A2DP = BIT(2),
913 BTC_BT_PAN = BIT(3),
914 BTC_PROFILE_MAX = 4,
915};
916
917struct rtw89_btc_ant_info {
918 u8 type; /* shared, dedicated */
919 u8 num;
920 u8 isolation;
921
922 u8 single_pos: 1;/* Single antenna at S0 or S1 */
923 u8 diversity: 1;
924};
925
926enum rtw89_tfc_dir {
927 RTW89_TFC_UL,
928 RTW89_TFC_DL,
929};
930
931struct rtw89_btc_wl_smap {
932 u32 busy: 1;
933 u32 scan: 1;
934 u32 connecting: 1;
935 u32 roaming: 1;
936 u32 _4way: 1;
937 u32 rf_off: 1;
938 u32 lps: 1;
939 u32 ips: 1;
940 u32 init_ok: 1;
941 u32 traffic_dir : 2;
942 u32 rf_off_pre: 1;
943 u32 lps_pre: 1;
944};
945
946enum rtw89_tfc_lv {
947 RTW89_TFC_IDLE,
948 RTW89_TFC_ULTRA_LOW,
949 RTW89_TFC_LOW,
950 RTW89_TFC_MID,
951 RTW89_TFC_HIGH,
952};
953
954#define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
955DECLARE_EWMA(tp, 10, 2);
956
957struct rtw89_traffic_stats {
958 /* units in bytes */
959 u64 tx_unicast;
960 u64 rx_unicast;
961 u32 tx_avg_len;
962 u32 rx_avg_len;
963
964 /* count for packets */
965 u64 tx_cnt;
966 u64 rx_cnt;
967
968 /* units in Mbps */
969 u32 tx_throughput;
970 u32 rx_throughput;
971 u32 tx_throughput_raw;
972 u32 rx_throughput_raw;
5165f168
PHH		 973
974 u32 rx_tf_acc;
975 u32 rx_tf_periodic;
976
e3ec7017
PKS		 977 enum rtw89_tfc_lv tx_tfc_lv;
978 enum rtw89_tfc_lv rx_tfc_lv;
979 struct ewma_tp tx_ewma_tp;
980 struct ewma_tp rx_ewma_tp;
981
982 u16 tx_rate;
983 u16 rx_rate;
984};
985
986struct rtw89_btc_statistic {
987 u8 rssi; /* 0%~110% (dBm = rssi -110) */
988 struct rtw89_traffic_stats traffic;
989};
990
991#define BTC_WL_RSSI_THMAX 4
992
993struct rtw89_btc_wl_link_info {
994 struct rtw89_btc_statistic stat;
995 enum rtw89_tfc_dir dir;
996 u8 rssi_state[BTC_WL_RSSI_THMAX];
997 u8 mac_addr[ETH_ALEN];
998 u8 busy;
999 u8 ch;
1000 u8 bw;
1001 u8 band;
1002 u8 role;
1003 u8 pid;
1004 u8 phy;
1005 u8 dtim_period;
1006 u8 mode;
1007
1008 u8 mac_id;
1009 u8 tx_retry;
1010
1011 u32 bcn_period;
1012 u32 busy_t;
1013 u32 tx_time;
1014 u32 client_cnt;
1015 u32 rx_rate_drop_cnt;
1016
1017 u32 active: 1;
1018 u32 noa: 1;
1019 u32 client_ps: 1;
1020 u32 connected: 2;
1021};
1022
1023union rtw89_btc_wl_state_map {
1024 u32 val;
1025 struct rtw89_btc_wl_smap map;
1026};
1027
1028struct rtw89_btc_bt_hfp_desc {
1029 u32 exist: 1;
1030 u32 type: 2;
1031 u32 rsvd: 29;
1032};
1033
1034struct rtw89_btc_bt_hid_desc {
1035 u32 exist: 1;
1036 u32 slot_info: 2;
1037 u32 pair_cnt: 2;
1038 u32 type: 8;
1039 u32 rsvd: 19;
1040};
1041
1042struct rtw89_btc_bt_a2dp_desc {
1043 u8 exist: 1;
1044 u8 exist_last: 1;
1045 u8 play_latency: 1;
1046 u8 type: 3;
1047 u8 active: 1;
1048 u8 sink: 1;
1049
1050 u8 bitpool;
1051 u16 vendor_id;
1052 u32 device_name;
1053 u32 flush_time;
1054};
1055
1056struct rtw89_btc_bt_pan_desc {
1057 u32 exist: 1;
1058 u32 type: 1;
1059 u32 active: 1;
1060 u32 rsvd: 29;
1061};
1062
1063struct rtw89_btc_bt_rfk_info {
1064 u32 run: 1;
1065 u32 req: 1;
1066 u32 timeout: 1;
1067 u32 rsvd: 29;
1068};
1069
1070union rtw89_btc_bt_rfk_info_map {
1071 u32 val;
1072 struct rtw89_btc_bt_rfk_info map;
1073};
1074
1075struct rtw89_btc_bt_ver_info {
1076 u32 fw_coex; /* match with which coex_ver */
1077 u32 fw;
1078};
1079
1080struct rtw89_btc_bool_sta_chg {
1081 u32 now: 1;
1082 u32 last: 1;
1083 u32 remain: 1;
1084 u32 srvd: 29;
1085};
1086
1087struct rtw89_btc_u8_sta_chg {
1088 u8 now;
1089 u8 last;
1090 u8 remain;
1091 u8 rsvd;
1092};
1093
1094struct rtw89_btc_wl_scan_info {
1095 u8 band[RTW89_PHY_MAX];
1096 u8 phy_map;
1097 u8 rsvd;
1098};
1099
1100struct rtw89_btc_wl_dbcc_info {
1101 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1102 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1103 u8 real_band[RTW89_PHY_MAX];
1104 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1105};
1106
1107struct rtw89_btc_wl_active_role {
1108 u8 connected: 1;
1109 u8 pid: 3;
1110 u8 phy: 1;
1111 u8 noa: 1;
1112 u8 band: 2;
1113
1114 u8 client_ps: 1;
1115 u8 bw: 7;
1116
1117 u8 role;
1118 u8 ch;
1119
1120 u16 tx_lvl;
1121 u16 rx_lvl;
1122 u16 tx_rate;
1123 u16 rx_rate;
1124};
1125
1126struct rtw89_btc_wl_role_info_bpos {
1127 u16 none: 1;
1128 u16 station: 1;
1129 u16 ap: 1;
1130 u16 vap: 1;
1131 u16 adhoc: 1;
1132 u16 adhoc_master: 1;
1133 u16 mesh: 1;
1134 u16 moniter: 1;
1135 u16 p2p_device: 1;
1136 u16 p2p_gc: 1;
1137 u16 p2p_go: 1;
1138 u16 nan: 1;
1139};
1140
1141union rtw89_btc_wl_role_info_map {
1142 u16 val;
1143 struct rtw89_btc_wl_role_info_bpos role;
1144};
1145
1146struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1147 u8 connect_cnt;
1148 u8 link_mode;
1149 union rtw89_btc_wl_role_info_map role_map;
20d9fc88 1150 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
e3ec7017
PKS		 1151};
1152
1153struct rtw89_btc_wl_ver_info {
1154 u32 fw_coex; /* match with which coex_ver */
1155 u32 fw;
1156 u32 mac;
1157 u32 bb;
1158 u32 rf;
1159};
1160
1161struct rtw89_btc_wl_afh_info {
1162 u8 en;
1163 u8 ch;
1164 u8 bw;
1165 u8 rsvd;
1166} __packed;
1167
1168struct rtw89_btc_wl_rfk_info {
1169 u32 state: 2;
1170 u32 path_map: 4;
1171 u32 phy_map: 2;
1172 u32 band: 2;
1173 u32 type: 8;
1174 u32 rsvd: 14;
1175};
1176
1177struct rtw89_btc_bt_smap {
1178 u32 connect: 1;
1179 u32 ble_connect: 1;
1180 u32 acl_busy: 1;
1181 u32 sco_busy: 1;
1182 u32 mesh_busy: 1;
1183 u32 inq_pag: 1;
1184};
1185
1186union rtw89_btc_bt_state_map {
1187 u32 val;
1188 struct rtw89_btc_bt_smap map;
1189};
1190
1191#define BTC_BT_RSSI_THMAX 4
1192#define BTC_BT_AFH_GROUP 12
1193
1194struct rtw89_btc_bt_link_info {
1195 struct rtw89_btc_u8_sta_chg profile_cnt;
1196 struct rtw89_btc_bool_sta_chg multi_link;
1197 struct rtw89_btc_bool_sta_chg relink;
1198 struct rtw89_btc_bt_hfp_desc hfp_desc;
1199 struct rtw89_btc_bt_hid_desc hid_desc;
1200 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1201 struct rtw89_btc_bt_pan_desc pan_desc;
1202 union rtw89_btc_bt_state_map status;
1203
1204 u8 sut_pwr_level[BTC_PROFILE_MAX];
1205 u8 golden_rx_shift[BTC_PROFILE_MAX];
1206 u8 rssi_state[BTC_BT_RSSI_THMAX];
1207 u8 afh_map[BTC_BT_AFH_GROUP];
1208
1209 u32 role_sw: 1;
1210 u32 slave_role: 1;
1211 u32 afh_update: 1;
1212 u32 cqddr: 1;
1213 u32 rssi: 8;
1214 u32 tx_3m: 1;
1215 u32 rsvd: 19;
1216};
1217
1218struct rtw89_btc_3rdcx_info {
1219 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1220 u8 hw_coex;
1221 u16 rsvd;
1222};
1223
1224struct rtw89_btc_dm_emap {
1225 u32 init: 1;
1226 u32 pta_owner: 1;
1227 u32 wl_rfk_timeout: 1;
1228 u32 bt_rfk_timeout: 1;
1229
1230 u32 wl_fw_hang: 1;
1231 u32 offload_mismatch: 1;
1232 u32 cycle_hang: 1;
1233 u32 w1_hang: 1;
1234
1235 u32 b1_hang: 1;
1236 u32 tdma_no_sync: 1;
1237 u32 wl_slot_drift: 1;
1238};
1239
1240union rtw89_btc_dm_error_map {
1241 u32 val;
1242 struct rtw89_btc_dm_emap map;
1243};
1244
1245struct rtw89_btc_rf_para {
1246 u32 tx_pwr_freerun;
1247 u32 rx_gain_freerun;
1248 u32 tx_pwr_perpkt;
1249 u32 rx_gain_perpkt;
1250};
1251
1252struct rtw89_btc_wl_info {
20d9fc88 1253 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
e3ec7017
PKS		 1254 struct rtw89_btc_wl_rfk_info rfk_info;
1255 struct rtw89_btc_wl_ver_info ver_info;
1256 struct rtw89_btc_wl_afh_info afh_info;
1257 struct rtw89_btc_wl_role_info role_info;
1258 struct rtw89_btc_wl_scan_info scan_info;
1259 struct rtw89_btc_wl_dbcc_info dbcc_info;
1260 struct rtw89_btc_rf_para rf_para;
1261 union rtw89_btc_wl_state_map status;
1262
1263 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1264 u8 rssi_level;
1265
1266 u32 scbd;
1267};
1268
1269struct rtw89_btc_module {
1270 struct rtw89_btc_ant_info ant;
1271 u8 rfe_type;
1272 u8 cv;
1273
1274 u8 bt_solo: 1;
1275 u8 bt_pos: 1;
1276 u8 switch_type: 1;
1277
1278 u8 rsvd;
1279};
1280
1281#define RTW89_BTC_DM_MAXSTEP 30
1282#define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1283
1284struct rtw89_btc_dm_step {
1285 u16 step[RTW89_BTC_DM_MAXSTEP];
1286 u8 step_pos;
1287 bool step_ov;
1288};
1289
1290struct rtw89_btc_init_info {
1291 struct rtw89_btc_module module;
1292 u8 wl_guard_ch;
1293
1294 u8 wl_only: 1;
1295 u8 wl_init_ok: 1;
1296 u8 dbcc_en: 1;
1297 u8 cx_other: 1;
1298 u8 bt_only: 1;
1299
1300 u16 rsvd;
1301};
1302
1303struct rtw89_btc_wl_tx_limit_para {
1304 u16 enable;
1305 u32 tx_time; /* unit: us */
1306 u16 tx_retry;
1307};
1308
1309struct rtw89_btc_bt_scan_info {
1310 u16 win;
1311 u16 intvl;
1312 u32 enable: 1;
1313 u32 interlace: 1;
1314 u32 rsvd: 30;
1315};
1316
1317enum rtw89_btc_bt_scan_type {
1318 BTC_SCAN_INQ = 0,
1319 BTC_SCAN_PAGE,
1320 BTC_SCAN_BLE,
1321 BTC_SCAN_INIT,
1322 BTC_SCAN_TV,
1323 BTC_SCAN_ADV,
1324 BTC_SCAN_MAX1,
1325};
1326
1327struct rtw89_btc_bt_info {
1328 struct rtw89_btc_bt_link_info link_info;
1329 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1];
1330 struct rtw89_btc_bt_ver_info ver_info;
1331 struct rtw89_btc_bool_sta_chg enable;
1332 struct rtw89_btc_bool_sta_chg inq_pag;
1333 struct rtw89_btc_rf_para rf_para;
1334 union rtw89_btc_bt_rfk_info_map rfk_info;
1335
1336 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1337
1338 u32 scbd;
1339 u32 feature;
1340
1341 u32 mbx_avl: 1;
1342 u32 whql_test: 1;
1343 u32 igno_wl: 1;
1344 u32 reinit: 1;
1345 u32 ble_scan_en: 1;
1346 u32 btg_type: 1;
1347 u32 inq: 1;
1348 u32 pag: 1;
1349 u32 run_patch_code: 1;
1350 u32 hi_lna_rx: 1;
1351 u32 rsvd: 22;
1352};
1353
1354struct rtw89_btc_cx {
1355 struct rtw89_btc_wl_info wl;
1356 struct rtw89_btc_bt_info bt;
1357 struct rtw89_btc_3rdcx_info other;
1358 u32 state_map;
1359 u32 cnt_bt[BTC_BCNT_NUM];
1360 u32 cnt_wl[BTC_WCNT_NUM];
1361};
1362
1363struct rtw89_btc_fbtc_tdma {
1364 u8 type;
1365 u8 rxflctrl;
1366 u8 txpause;
1367 u8 wtgle_n;
1368 u8 leak_n;
1369 u8 ext_ctrl;
1370 u8 rsvd0;
1371 u8 rsvd1;
1372} __packed;
1373
1374#define CXMREG_MAX 30
1375#define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1376#define BTCRPT_VER 1
1377#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1378
1379enum rtw89_btc_bt_rfk_counter {
1380 BTC_BCNT_RFK_REQ = 0,
1381 BTC_BCNT_RFK_GO = 1,
1382 BTC_BCNT_RFK_REJECT = 2,
1383 BTC_BCNT_RFK_FAIL = 3,
1384 BTC_BCNT_RFK_TIMEOUT = 4,
1385 BTC_BCNT_RFK_MAX
1386};
1387
1388struct rtw89_btc_fbtc_rpt_ctrl {
1389 u16 fver;
1390 u16 rpt_cnt; /* tmr counters */
1391 u32 wl_fw_coex_ver; /* match which driver's coex version */
1392 u32 wl_fw_cx_offload;
1393 u32 wl_fw_ver;
1394 u32 rpt_enable;
1395 u32 rpt_para; /* ms */
1396 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1397 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1398 u32 mb_recv_cnt; /* fw recv mailbox counter */
1399 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1400 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1401 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1402 u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX];
1403 u32 c2h_cnt; /* fw send c2h counter */
1404 u32 h2c_cnt; /* fw recv h2c counter */
1405} __packed;
1406
1407enum rtw89_fbtc_ext_ctrl_type {
1408 CXECTL_OFF = 0x0, /* tdma off */
1409 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1410 CXECTL_EXT = 0x2,
1411 CXECTL_MAX
1412};
1413
1414union rtw89_btc_fbtc_rxflct {
1415 u8 val;
1416 u8 type: 3;
1417 u8 tgln_n: 5;
1418};
1419
1420enum rtw89_btc_cxst_state {
1421 CXST_OFF = 0x0,
1422 CXST_B2W = 0x1,
1423 CXST_W1 = 0x2,
1424 CXST_W2 = 0x3,
1425 CXST_W2B = 0x4,
1426 CXST_B1 = 0x5,
1427 CXST_B2 = 0x6,
1428 CXST_B3 = 0x7,
1429 CXST_B4 = 0x8,
1430 CXST_LK = 0x9,
1431 CXST_BLK = 0xa,
1432 CXST_E2G = 0xb,
1433 CXST_E5G = 0xc,
1434 CXST_EBT = 0xd,
1435 CXST_ENULL = 0xe,
1436 CXST_WLK = 0xf,
1437 CXST_W1FDD = 0x10,
1438 CXST_B1FDD = 0x11,
1439 CXST_MAX = 0x12,
1440};
1441
1442enum {
1443 CXBCN_ALL = 0x0,
1444 CXBCN_ALL_OK,
1445 CXBCN_BT_SLOT,
1446 CXBCN_BT_OK,
1447 CXBCN_MAX
1448};
1449
1450enum btc_slot_type {
1451 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
1452 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
1453 CXSTYPE_NUM,
1454};
1455
1456enum { /* TIME */
1457 CXT_BT = 0x0,
1458 CXT_WL = 0x1,
1459 CXT_MAX
1460};
1461
1462enum { /* TIME-A2DP */
1463 CXT_FLCTRL_OFF = 0x0,
1464 CXT_FLCTRL_ON = 0x1,
1465 CXT_FLCTRL_MAX
1466};
1467
1468enum { /* STEP TYPE */
1469 CXSTEP_NONE = 0x0,
1470 CXSTEP_EVNT = 0x1,
1471 CXSTEP_SLOT = 0x2,
1472 CXSTEP_MAX,
1473};
1474
1475#define FCXGPIODBG_VER 1
1476#define BTC_DBG_MAX1 32
1477struct rtw89_btc_fbtc_gpio_dbg {
1478 u8 fver;
1479 u8 rsvd;
1480 u16 rsvd2;
1481 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
1482 u32 pre_state; /* the debug signal is 1 or 0 */
1483 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
1484} __packed;
1485
1486#define FCXMREG_VER 1
1487struct rtw89_btc_fbtc_mreg_val {
1488 u8 fver;
1489 u8 reg_num;
1490 __le16 rsvd;
1491 __le32 mreg_val[CXMREG_MAX];
1492} __packed;
1493
1494#define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
1495 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
1496 .offset = cpu_to_le32(__offset), }
1497
1498struct rtw89_btc_fbtc_mreg {
1499 __le16 type;
1500 __le16 bytes;
1501 __le32 offset;
1502} __packed;
1503
1504struct rtw89_btc_fbtc_slot {
1505 __le16 dur;
1506 __le32 cxtbl;
1507 __le16 cxtype;
1508} __packed;
1509
1510#define FCXSLOTS_VER 1
1511struct rtw89_btc_fbtc_slots {
1512 u8 fver;
1513 u8 tbl_num;
1514 __le16 rsvd;
1515 __le32 update_map;
1516 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1517} __packed;
1518
1519#define FCXSTEP_VER 2
1520struct rtw89_btc_fbtc_step {
1521 u8 type;
1522 u8 val;
1523 __le16 difft;
1524} __packed;
1525
1526struct rtw89_btc_fbtc_steps {
1527 u8 fver;
1528 u8 rsvd;
1529 __le16 cnt;
1530 __le16 pos_old;
1531 __le16 pos_new;
1532 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
1533} __packed;
1534
1535#define FCXCYSTA_VER 2
1536struct rtw89_btc_fbtc_cysta { /* statistics for cycles */
1537 u8 fver;
1538 u8 rsvd;
1539 __le16 cycles; /* total cycle number */
1540 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
1541 __le16 a2dpept; /* a2dp empty cnt */
1542 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
1543 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
1544 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
1545 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
1546 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
1547 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
1548 __le16 tavg_a2dpept; /* avg a2dp empty time */
1549 __le16 tmax_a2dpept; /* max a2dp empty time */
1550 __le16 tavg_lk; /* avg leak-slot time */
1551 __le16 tmax_lk; /* max leak-slot time */
1552 __le32 slot_cnt[CXST_MAX]; /* slot count */
1553 __le32 bcn_cnt[CXBCN_MAX];
1554 __le32 leakrx_cnt; /* the rximr occur at leak slot */
1555 __le32 collision_cnt; /* counter for event/timer occur at same time */
1556 __le32 skip_cnt;
1557 __le32 exception;
1558 __le32 except_cnt;
1559 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
1560} __packed;
1561
1562#define FCXNULLSTA_VER 1
1563struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */
1564 u8 fver;
1565 u8 rsvd;
1566 __le16 rsvd2;
1567 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
1568 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
1569 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
1570} __packed;
1571
1572#define FCX_BTVER_VER 1
1573struct rtw89_btc_fbtc_btver {
1574 u8 fver;
1575 u8 rsvd;
1576 __le16 rsvd2;
1577 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
1578 __le32 fw_ver;
1579 __le32 feature;
1580} __packed;
1581
1582#define FCX_BTSCAN_VER 1
1583struct rtw89_btc_fbtc_btscan {
1584 u8 fver;
1585 u8 rsvd;
1586 __le16 rsvd2;
1587 u8 scan[6];
1588} __packed;
1589
1590#define FCX_BTAFH_VER 1
1591struct rtw89_btc_fbtc_btafh {
1592 u8 fver;
1593 u8 rsvd;
1594 __le16 rsvd2;
1595 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
1596 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
1597 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
1598} __packed;
1599
1600#define FCX_BTDEVINFO_VER 1
1601struct rtw89_btc_fbtc_btdevinfo {
1602 u8 fver;
1603 u8 rsvd;
1604 __le16 vendor_id;
1605 __le32 dev_name; /* only 24 bits valid */
1606 __le32 flush_time;
1607} __packed;
1608
1609#define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
1610struct rtw89_btc_rf_trx_para {
1611 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
1612 u32 wl_rx_gain; /* rx gain table index (TBD.) */
1613 u8 bt_tx_power; /* decrease Tx power (dB) */
1614 u8 bt_rx_gain; /* LNA constrain level */
1615};
1616
1617struct rtw89_btc_dm {
1618 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1619 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
1620 struct rtw89_btc_fbtc_tdma tdma;
1621 struct rtw89_btc_fbtc_tdma tdma_now;
1622 struct rtw89_mac_ax_coex_gnt gnt;
1623 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
1624 struct rtw89_btc_rf_trx_para rf_trx_para;
1625 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
1626 struct rtw89_btc_dm_step dm_step;
1627 union rtw89_btc_dm_error_map error;
1628 u32 cnt_dm[BTC_DCNT_NUM];
1629 u32 cnt_notify[BTC_NCNT_NUM];
1630
1631 u32 update_slot_map;
1632 u32 set_ant_path;
1633
1634 u32 wl_only: 1;
1635 u32 wl_fw_cx_offload: 1;
1636 u32 freerun: 1;
1637 u32 wl_ps_ctrl: 2;
1638 u32 wl_mimo_ps: 1;
1639 u32 leak_ap: 1;
1640 u32 noisy_level: 3;
1641 u32 coex_info_map: 8;
1642 u32 bt_only: 1;
1643 u32 wl_btg_rx: 1;
1644 u32 trx_para_level: 8;
1645 u32 wl_stb_chg: 1;
1646 u32 rsvd: 3;
1647
1648 u16 slot_dur[CXST_MAX];
1649
1650 u8 run_reason;
1651 u8 run_action;
1652};
1653
1654struct rtw89_btc_ctrl {
1655 u32 manual: 1;
1656 u32 igno_bt: 1;
1657 u32 always_freerun: 1;
1658 u32 trace_step: 16;
1659 u32 rsvd: 12;
1660};
1661
1662struct rtw89_btc_dbg {
1663 /* cmd "rb" */
1664 bool rb_done;
1665 u32 rb_val;
1666};
1667
1668#define FCXTDMA_VER 1
1669
1670enum rtw89_btc_btf_fw_event {
1671 BTF_EVNT_RPT = 0,
1672 BTF_EVNT_BT_INFO = 1,
1673 BTF_EVNT_BT_SCBD = 2,
1674 BTF_EVNT_BT_REG = 3,
1675 BTF_EVNT_CX_RUNINFO = 4,
1676 BTF_EVNT_BT_PSD = 5,
1677 BTF_EVNT_BUF_OVERFLOW,
1678 BTF_EVNT_C2H_LOOPBACK,
1679 BTF_EVNT_MAX,
1680};
1681
1682enum btf_fw_event_report {
1683 BTC_RPT_TYPE_CTRL = 0x0,
1684 BTC_RPT_TYPE_TDMA,
1685 BTC_RPT_TYPE_SLOT,
1686 BTC_RPT_TYPE_CYSTA,
1687 BTC_RPT_TYPE_STEP,
1688 BTC_RPT_TYPE_NULLSTA,
1689 BTC_RPT_TYPE_MREG,
1690 BTC_RPT_TYPE_GPIO_DBG,
1691 BTC_RPT_TYPE_BT_VER,
1692 BTC_RPT_TYPE_BT_SCAN,
1693 BTC_RPT_TYPE_BT_AFH,
1694 BTC_RPT_TYPE_BT_DEVICE,
1695 BTC_RPT_TYPE_TEST,
1696 BTC_RPT_TYPE_MAX = 31
1697};
1698
1699enum rtw_btc_btf_reg_type {
1700 REG_MAC = 0x0,
1701 REG_BB = 0x1,
1702 REG_RF = 0x2,
1703 REG_BT_RF = 0x3,
1704 REG_BT_MODEM = 0x4,
1705 REG_BT_BLUEWIZE = 0x5,
1706 REG_BT_VENDOR = 0x6,
1707 REG_BT_LE = 0x7,
1708 REG_MAX_TYPE,
1709};
1710
1711struct rtw89_btc_rpt_cmn_info {
1712 u32 rx_cnt;
1713 u32 rx_len;
1714 u32 req_len; /* expected rsp len */
1715 u8 req_fver; /* expected rsp fver */
1716 u8 rsp_fver; /* fver from fw */
1717 u8 valid;
1718} __packed;
1719
1720struct rtw89_btc_report_ctrl_state {
1721 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1722 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */
1723};
1724
1725struct rtw89_btc_rpt_fbtc_tdma {
1726 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1727 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */
1728};
1729
1730struct rtw89_btc_rpt_fbtc_slots {
1731 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1732 struct rtw89_btc_fbtc_slots finfo; /* info from fw */
1733};
1734
1735struct rtw89_btc_rpt_fbtc_cysta {
1736 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1737 struct rtw89_btc_fbtc_cysta finfo; /* info from fw */
1738};
1739
1740struct rtw89_btc_rpt_fbtc_step {
1741 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1742 struct rtw89_btc_fbtc_steps finfo; /* info from fw */
1743};
1744
1745struct rtw89_btc_rpt_fbtc_nullsta {
1746 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1747 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */
1748};
1749
1750struct rtw89_btc_rpt_fbtc_mreg {
1751 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1752 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
1753};
1754
1755struct rtw89_btc_rpt_fbtc_gpio_dbg {
1756 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1757 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
1758};
1759
1760struct rtw89_btc_rpt_fbtc_btver {
1761 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1762 struct rtw89_btc_fbtc_btver finfo; /* info from fw */
1763};
1764
1765struct rtw89_btc_rpt_fbtc_btscan {
1766 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1767 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */
1768};
1769
1770struct rtw89_btc_rpt_fbtc_btafh {
1771 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1772 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */
1773};
1774
1775struct rtw89_btc_rpt_fbtc_btdev {
1776 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1777 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
1778};
1779
1780enum rtw89_btc_btfre_type {
1781 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
1782 BTFRE_UNDEF_TYPE,
1783 BTFRE_EXCEPTION,
1784 BTFRE_MAX,
1785};
1786
1787struct rtw89_btc_btf_fwinfo {
1788 u32 cnt_c2h;
1789 u32 cnt_h2c;
1790 u32 cnt_h2c_fail;
1791 u32 event[BTF_EVNT_MAX];
1792
1793 u32 err[BTFRE_MAX];
1794 u32 len_mismch;
1795 u32 fver_mismch;
1796 u32 rpt_en_map;
1797
1798 struct rtw89_btc_report_ctrl_state rpt_ctrl;
1799 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
1800 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
1801 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
1802 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
1803 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
1804 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
1805 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
1806 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
1807 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
1808 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
1809 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
1810};
1811
1812#define RTW89_BTC_POLICY_MAXLEN 512
1813
1814struct rtw89_btc {
1815 struct rtw89_btc_cx cx;
1816 struct rtw89_btc_dm dm;
1817 struct rtw89_btc_ctrl ctrl;
1818 struct rtw89_btc_module mdinfo;
1819 struct rtw89_btc_btf_fwinfo fwinfo;
1820 struct rtw89_btc_dbg dbg;
1821
1822 struct work_struct eapol_notify_work;
1823 struct work_struct arp_notify_work;
1824 struct work_struct dhcp_notify_work;
1825 struct work_struct icmp_notify_work;
1826
1827 u32 bt_req_len;
1828
1829 u8 policy[RTW89_BTC_POLICY_MAXLEN];
1830 u16 policy_len;
1831 u16 policy_type;
1832 bool bt_req_en;
1833 bool update_policy_force;
1834 bool lps;
1835};
1836
1837enum rtw89_ra_mode {
1838 RTW89_RA_MODE_CCK = BIT(0),
1839 RTW89_RA_MODE_OFDM = BIT(1),
1840 RTW89_RA_MODE_HT = BIT(2),
1841 RTW89_RA_MODE_VHT = BIT(3),
1842 RTW89_RA_MODE_HE = BIT(4),
1843};
1844
1845enum rtw89_ra_report_mode {
1846 RTW89_RA_RPT_MODE_LEGACY,
1847 RTW89_RA_RPT_MODE_HT,
1848 RTW89_RA_RPT_MODE_VHT,
1849 RTW89_RA_RPT_MODE_HE,
1850};
1851
1852enum rtw89_dig_noisy_level {
1853 RTW89_DIG_NOISY_LEVEL0 = -1,
1854 RTW89_DIG_NOISY_LEVEL1 = 0,
1855 RTW89_DIG_NOISY_LEVEL2 = 1,
1856 RTW89_DIG_NOISY_LEVEL3 = 2,
1857 RTW89_DIG_NOISY_LEVEL_MAX = 3,
1858};
1859
1860enum rtw89_gi_ltf {
1861 RTW89_GILTF_LGI_4XHE32 = 0,
1862 RTW89_GILTF_SGI_4XHE08 = 1,
1863 RTW89_GILTF_2XHE16 = 2,
1864 RTW89_GILTF_2XHE08 = 3,
1865 RTW89_GILTF_1XHE16 = 4,
1866 RTW89_GILTF_1XHE08 = 5,
1867 RTW89_GILTF_MAX
1868};
1869
1870enum rtw89_rx_frame_type {
1871 RTW89_RX_TYPE_MGNT = 0,
1872 RTW89_RX_TYPE_CTRL = 1,
1873 RTW89_RX_TYPE_DATA = 2,
1874 RTW89_RX_TYPE_RSVD = 3,
1875};
1876
1877struct rtw89_ra_info {
1878 u8 is_dis_ra:1;
1879 /* Bit0 : CCK
1880 * Bit1 : OFDM
1881 * Bit2 : HT
1882 * Bit3 : VHT
1883 * Bit4 : HE
1884 */
1885 u8 mode_ctrl:5;
1886 u8 bw_cap:2;
1887 u8 macid;
1888 u8 dcm_cap:1;
1889 u8 er_cap:1;
1890 u8 init_rate_lv:2;
1891 u8 upd_all:1;
1892 u8 en_sgi:1;
1893 u8 ldpc_cap:1;
1894 u8 stbc_cap:1;
1895 u8 ss_num:3;
1896 u8 giltf:3;
1897 u8 upd_bw_nss_mask:1;
1898 u8 upd_mask:1;
1899 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
1900 /* BFee CSI */
1901 u8 band_num;
1902 u8 ra_csi_rate_en:1;
1903 u8 fixed_csi_rate_en:1;
1904 u8 cr_tbl_sel:1;
1905 u8 rsvd2:5;
1906 u8 csi_mcs_ss_idx;
1907 u8 csi_mode:2;
1908 u8 csi_gi_ltf:3;
1909 u8 csi_bw:3;
1910};
1911
1912#define RTW89_PPDU_MAX_USR 4
1913#define RTW89_PPDU_MAC_INFO_USR_SIZE 4
1914#define RTW89_PPDU_MAC_INFO_SIZE 8
1915#define RTW89_PPDU_MAC_RX_CNT_SIZE 96
1916
1917#define RTW89_MAX_RX_AGG_NUM 64
1918#define RTW89_MAX_TX_AGG_NUM 128
1919
1920struct rtw89_ampdu_params {
1921 u16 agg_num;
1922 bool amsdu;
1923};
1924
1925struct rtw89_ra_report {
1926 struct rate_info txrate;
1927 u32 bit_rate;
1928 u16 hw_rate;
1929};
1930
1931DECLARE_EWMA(rssi, 10, 16);
1932
3ffbb5a8
PKS		 1933#define RTW89_BA_CAM_NUM 2
1934
1935struct rtw89_ba_cam_entry {
1936 u8 tid;
1937};
1938
e3ec7017
PKS		 1939#define RTW89_MAX_ADDR_CAM_NUM 128
1940#define RTW89_MAX_BSSID_CAM_NUM 20
1941#define RTW89_MAX_SEC_CAM_NUM 128
1942#define RTW89_SEC_CAM_IN_ADDR_CAM 7
1943
1944struct rtw89_addr_cam_entry {
1945 u8 addr_cam_idx;
1946 u8 offset;
1947 u8 len;
1948 u8 valid : 1;
1949 u8 addr_mask : 6;
1950 u8 wapi : 1;
1951 u8 mask_sel : 2;
1952 u8 bssid_cam_idx: 6;
e3ec7017
PKS		 1953
1954 u8 sec_ent_mode;
1955 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
1956 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
1957 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
1958 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
1959};
1960
1961struct rtw89_bssid_cam_entry {
1962 u8 bssid[ETH_ALEN];
1963 u8 phy_idx;
1964 u8 bssid_cam_idx;
1965 u8 offset;
1966 u8 len;
1967 u8 valid : 1;
1968 u8 num;
1969};
1970
1971struct rtw89_sec_cam_entry {
1972 u8 sec_cam_idx;
1973 u8 offset;
1974 u8 len;
1975 u8 type : 4;
1976 u8 ext_key : 1;
1977 u8 spp_mode : 1;
1978 /* 256 bits */
1979 u8 key[32];
1980};
1981
2ab856cc
PKS		 1982struct rtw89_sta {
1983 u8 mac_id;
1984 bool disassoc;
1985 struct rtw89_vif *rtwvif;
1986 struct rtw89_ra_info ra;
1987 struct rtw89_ra_report ra_report;
1988 int max_agg_wait;
1989 u8 prev_rssi;
1990 struct ewma_rssi avg_rssi;
1991 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
1992 struct ieee80211_rx_status rx_status;
1993 u16 rx_hw_rate;
1994 __le32 htc_template;
7312100d 1995 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
39913cc8 1996 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
2ab856cc
PKS		 1997
1998 bool use_cfg_mask;
1999 struct cfg80211_bitrate_mask mask;
2000
2001 bool cctl_tx_time;
2002 u32 ampdu_max_time:4;
2003 bool cctl_tx_retry_limit;
2004 u32 data_tx_cnt_lmt:6;
2005
2006 DECLARE_BITMAP(ba_cam_map, RTW89_BA_CAM_NUM);
2007 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_BA_CAM_NUM];
2008};
2009
e3ec7017
PKS		 2010struct rtw89_efuse {
2011 bool valid;
2012 u8 xtal_cap;
2013 u8 addr[ETH_ALEN];
2014 u8 rfe_type;
2015 char country_code[2];
2016};
2017
2018struct rtw89_phy_rate_pattern {
2019 u64 ra_mask;
2020 u16 rate;
2021 u8 ra_mode;
2022 bool enable;
2023};
2024
2025struct rtw89_vif {
2026 struct list_head list;
d62816b4 2027 struct rtw89_dev *rtwdev;
e3ec7017
PKS		 2028 u8 mac_id;
2029 u8 port;
2030 u8 mac_addr[ETH_ALEN];
2031 u8 bssid[ETH_ALEN];
2032 u8 phy_idx;
2033 u8 mac_idx;
2034 u8 net_type;
2035 u8 wifi_role;
2036 u8 self_role;
2037 u8 wmm;
2038 u8 bcn_hit_cond;
2039 u8 hit_rule;
2040 bool trigger;
2041 bool lsig_txop;
2042 u8 tgt_ind;
2043 u8 frm_tgt_ind;
2044 bool wowlan_pattern;
2045 bool wowlan_uc;
2046 bool wowlan_magic;
2047 bool is_hesta;
2048 bool last_a_ctrl;
d62816b4 2049 struct work_struct update_beacon_work;
e3ec7017
PKS		 2050 struct rtw89_addr_cam_entry addr_cam;
2051 struct rtw89_bssid_cam_entry bssid_cam;
2052 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
2053 struct rtw89_traffic_stats stats;
2054 struct rtw89_phy_rate_pattern rate_pattern;
89590777
PHH		 2055 struct cfg80211_scan_request *scan_req;
2056 struct ieee80211_scan_ies *scan_ies;
e3ec7017
PKS		 2057};
2058
2059enum rtw89_lv1_rcvy_step {
2060 RTW89_LV1_RCVY_STEP_1,
2061 RTW89_LV1_RCVY_STEP_2,
2062};
2063
2064struct rtw89_hci_ops {
2065 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
2066 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
2067 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
2068 void (*reset)(struct rtw89_dev *rtwdev);
2069 int (*start)(struct rtw89_dev *rtwdev);
2070 void (*stop)(struct rtw89_dev *rtwdev);
52edbb9f
PKS		 2071 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
2072 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
e3ec7017
PKS		 2073 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
2074
2075 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
2076 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
2077 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
2078 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
2079 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
2080 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
2081
2082 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
2083 int (*mac_post_init)(struct rtw89_dev *rtwdev);
2084 int (*deinit)(struct rtw89_dev *rtwdev);
2085
2086 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
2087 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
2088 void (*dump_err_status)(struct rtw89_dev *rtwdev);
2089 int (*napi_poll)(struct napi_struct *napi, int budget);
14f9f479
ZZY		 2090
2091 /* Deal with locks inside recovery_start and recovery_complete callbacks
2092 * by hci instance, and handle things which need to consider under SER.
2093 * e.g. turn on/off interrupts except for the one for halt notification.
2094 */
2095 void (*recovery_start)(struct rtw89_dev *rtwdev);
2096 void (*recovery_complete)(struct rtw89_dev *rtwdev);
e3ec7017
PKS		 2097};
2098
2099struct rtw89_hci_info {
2100 const struct rtw89_hci_ops *ops;
2101 enum rtw89_hci_type type;
2102 u32 rpwm_addr;
2103 u32 cpwm_addr;
52edbb9f 2104 bool paused;
e3ec7017
PKS		 2105};
2106
2107struct rtw89_chip_ops {
61ebeecb
PKS		 2108 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
2109 void (*disable_bb_rf)(struct rtw89_dev *rtwdev);
e3ec7017
PKS		 2110 void (*bb_reset)(struct rtw89_dev *rtwdev,
2111 enum rtw89_phy_idx phy_idx);
2112 void (*bb_sethw)(struct rtw89_dev *rtwdev);
2113 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
2114 u32 addr, u32 mask);
2115 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
2116 u32 addr, u32 mask, u32 data);
2117 void (*set_channel)(struct rtw89_dev *rtwdev,
ce57e55c
ZZY		 2118 const struct rtw89_chan *chan,
2119 enum rtw89_mac_idx mac_idx,
2120 enum rtw89_phy_idx phy_idx);
e3ec7017 2121 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
ce57e55c
ZZY		 2122 struct rtw89_channel_help_params *p,
2123 const struct rtw89_chan *chan,
2124 enum rtw89_mac_idx mac_idx,
2125 enum rtw89_phy_idx phy_idx);
e3ec7017
PKS		 2126 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
2127 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
2128 void (*fem_setup)(struct rtw89_dev *rtwdev);
2129 void (*rfk_init)(struct rtw89_dev *rtwdev);
2130 void (*rfk_channel)(struct rtw89_dev *rtwdev);
010d0051
ZZY		 2131 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
2132 enum rtw89_phy_idx phy_idx);
e3ec7017
PKS		 2133 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
2134 void (*rfk_track)(struct rtw89_dev *rtwdev);
2135 void (*power_trim)(struct rtw89_dev *rtwdev);
07ef5f2f
ZZY		 2136 void (*set_txpwr)(struct rtw89_dev *rtwdev,
2137 const struct rtw89_chan *chan,
2138 enum rtw89_phy_idx phy_idx);
2139 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
2140 enum rtw89_phy_idx phy_idx);
e3ec7017
PKS		 2141 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
2142 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
2143 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
2144 void (*query_ppdu)(struct rtw89_dev *rtwdev,
2145 struct rtw89_rx_phy_ppdu *phy_ppdu,
2146 struct ieee80211_rx_status *status);
2147 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
cd89a471 2148 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
e3ec7017 2149 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
a9ffae8d 2150 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
2a7e54db
PKS		 2151 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
2152 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
f59acdde
PKS		 2153 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
2154 struct rtw89_tx_desc_info *desc_info,
2155 void *txdesc);
a95bd62e
PKS		 2156 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
2157 struct rtw89_tx_desc_info *desc_info,
2158 void *txdesc);
feed6541
CYL		 2159 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
2160 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
2161 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
de7ba639
PKS		 2162 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
2163 u32 *tx_en, enum rtw89_sch_tx_sel sel);
2164 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
0a6f299b
PKS		 2165 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
2166 struct rtw89_vif *rtwvif,
2167 struct rtw89_sta *rtwsta);
e3ec7017
PKS		 2168
2169 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
2170 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
2171 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
2172 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
2173 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
2174 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev);
2175 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
2176 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
2177};
2178
2179enum rtw89_dma_ch {
2180 RTW89_DMA_ACH0 = 0,
2181 RTW89_DMA_ACH1 = 1,
2182 RTW89_DMA_ACH2 = 2,
2183 RTW89_DMA_ACH3 = 3,
2184 RTW89_DMA_ACH4 = 4,
2185 RTW89_DMA_ACH5 = 5,
2186 RTW89_DMA_ACH6 = 6,
2187 RTW89_DMA_ACH7 = 7,
2188 RTW89_DMA_B0MG = 8,
2189 RTW89_DMA_B0HI = 9,
2190 RTW89_DMA_B1MG = 10,
2191 RTW89_DMA_B1HI = 11,
2192 RTW89_DMA_H2C = 12,
2193 RTW89_DMA_CH_NUM = 13
2194};
2195
2196enum rtw89_qta_mode {
2197 RTW89_QTA_SCC,
2198 RTW89_QTA_DLFW,
2199
2200 /* keep last */
2201 RTW89_QTA_INVALID,
2202};
2203
2204struct rtw89_hfc_ch_cfg {
2205 u16 min;
2206 u16 max;
2207#define grp_0 0
2208#define grp_1 1
2209#define grp_num 2
2210 u8 grp;
2211};
2212
2213struct rtw89_hfc_ch_info {
2214 u16 aval;
2215 u16 used;
2216};
2217
2218struct rtw89_hfc_pub_cfg {
2219 u16 grp0;
2220 u16 grp1;
2221 u16 pub_max;
2222 u16 wp_thrd;
2223};
2224
2225struct rtw89_hfc_pub_info {
2226 u16 g0_used;
2227 u16 g1_used;
2228 u16 g0_aval;
2229 u16 g1_aval;
2230 u16 pub_aval;
2231 u16 wp_aval;
2232};
2233
2234struct rtw89_hfc_prec_cfg {
2235 u16 ch011_prec;
2236 u16 h2c_prec;
2237 u16 wp_ch07_prec;
2238 u16 wp_ch811_prec;
2239 u8 ch011_full_cond;
2240 u8 h2c_full_cond;
2241 u8 wp_ch07_full_cond;
2242 u8 wp_ch811_full_cond;
2243};
2244
2245struct rtw89_hfc_param {
2246 bool en;
2247 bool h2c_en;
2248 u8 mode;
2249 const struct rtw89_hfc_ch_cfg *ch_cfg;
2250 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
2251 struct rtw89_hfc_pub_cfg pub_cfg;
2252 struct rtw89_hfc_pub_info pub_info;
2253 struct rtw89_hfc_prec_cfg prec_cfg;
2254};
2255
2256struct rtw89_hfc_param_ini {
2257 const struct rtw89_hfc_ch_cfg *ch_cfg;
2258 const struct rtw89_hfc_pub_cfg *pub_cfg;
2259 const struct rtw89_hfc_prec_cfg *prec_cfg;
2260 u8 mode;
2261};
2262
2263struct rtw89_dle_size {
2264 u16 pge_size;
2265 u16 lnk_pge_num;
2266 u16 unlnk_pge_num;
2267};
2268
2269struct rtw89_wde_quota {
2270 u16 hif;
2271 u16 wcpu;
2272 u16 pkt_in;
2273 u16 cpu_io;
2274};
2275
2276struct rtw89_ple_quota {
2277 u16 cma0_tx;
2278 u16 cma1_tx;
2279 u16 c2h;
2280 u16 h2c;
2281 u16 wcpu;
2282 u16 mpdu_proc;
2283 u16 cma0_dma;
2284 u16 cma1_dma;
2285 u16 bb_rpt;
2286 u16 wd_rel;
2287 u16 cpu_io;
79d099e0 2288 u16 tx_rpt;
e3ec7017
PKS		 2289};
2290
2291struct rtw89_dle_mem {
2292 enum rtw89_qta_mode mode;
2293 const struct rtw89_dle_size *wde_size;
2294 const struct rtw89_dle_size *ple_size;
2295 const struct rtw89_wde_quota *wde_min_qt;
2296 const struct rtw89_wde_quota *wde_max_qt;
2297 const struct rtw89_ple_quota *ple_min_qt;
2298 const struct rtw89_ple_quota *ple_max_qt;
2299};
2300
2301struct rtw89_reg_def {
2302 u32 addr;
2303 u32 mask;
2304};
2305
2306struct rtw89_reg2_def {
2307 u32 addr;
2308 u32 data;
2309};
2310
2311struct rtw89_reg3_def {
2312 u32 addr;
2313 u32 mask;
2314 u32 data;
2315};
2316
2317struct rtw89_reg5_def {
2318 u8 flag; /* recognized by parsers */
2319 u8 path;
2320 u32 addr;
2321 u32 mask;
2322 u32 data;
2323};
2324
2325struct rtw89_phy_table {
2326 const struct rtw89_reg2_def *regs;
2327 u32 n_regs;
2328 enum rtw89_rf_path rf_path;
2a5f2b32
PKS		 2329 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
2330 enum rtw89_rf_path rf_path, void *data);
e3ec7017
PKS		 2331};
2332
2333struct rtw89_txpwr_table {
2334 const void *data;
2335 u32 size;
2336 void (*load)(struct rtw89_dev *rtwdev,
2337 const struct rtw89_txpwr_table *tbl);
2338};
2339
ab8a5671
PKS		 2340struct rtw89_page_regs {
2341 u32 hci_fc_ctrl;
2342 u32 ch_page_ctrl;
2343 u32 ach_page_ctrl;
2344 u32 ach_page_info;
2345 u32 pub_page_info3;
2346 u32 pub_page_ctrl1;
2347 u32 pub_page_ctrl2;
2348 u32 pub_page_info1;
2349 u32 pub_page_info2;
2350 u32 wp_page_ctrl1;
2351 u32 wp_page_ctrl2;
2352 u32 wp_page_info1;
2353};
2354
eeadcd2a
CYL		 2355struct rtw89_imr_info {
2356 u32 wdrls_imr_set;
2357 u32 wsec_imr_reg;
2358 u32 wsec_imr_set;
2359 u32 mpdu_tx_imr_set;
2360 u32 mpdu_rx_imr_set;
2361 u32 sta_sch_imr_set;
2362 u32 txpktctl_imr_b0_reg;
2363 u32 txpktctl_imr_b0_clr;
2364 u32 txpktctl_imr_b0_set;
2365 u32 txpktctl_imr_b1_reg;
2366 u32 txpktctl_imr_b1_clr;
2367 u32 txpktctl_imr_b1_set;
2368 u32 wde_imr_clr;
2369 u32 wde_imr_set;
2370 u32 ple_imr_clr;
2371 u32 ple_imr_set;
2372 u32 host_disp_imr_clr;
2373 u32 host_disp_imr_set;
2374 u32 cpu_disp_imr_clr;
2375 u32 cpu_disp_imr_set;
2376 u32 other_disp_imr_clr;
2377 u32 other_disp_imr_set;
2378 u32 bbrpt_chinfo_err_imr_reg;
2379 u32 bbrpt_err_imr_set;
2380 u32 bbrpt_dfs_err_imr_reg;
d86369e9
CYL		 2381 u32 ptcl_imr_clr;
2382 u32 ptcl_imr_set;
2383 u32 cdma_imr_0_reg;
2384 u32 cdma_imr_0_clr;
2385 u32 cdma_imr_0_set;
2386 u32 cdma_imr_1_reg;
2387 u32 cdma_imr_1_clr;
2388 u32 cdma_imr_1_set;
2389 u32 phy_intf_imr_reg;
2390 u32 phy_intf_imr_clr;
2391 u32 phy_intf_imr_set;
2392 u32 rmac_imr_reg;
2393 u32 rmac_imr_clr;
2394 u32 rmac_imr_set;
2395 u32 tmac_imr_reg;
2396 u32 tmac_imr_clr;
2397 u32 tmac_imr_set;
eeadcd2a
CYL		 2398};
2399
e3ec7017
PKS		 2400struct rtw89_chip_info {
2401 enum rtw89_core_chip_id chip_id;
2402 const struct rtw89_chip_ops *ops;
2403 const char *fw_name;
2404 u32 fifo_size;
2405 u16 max_amsdu_limit;
2406 bool dis_2g_40m_ul_ofdma;
9f8004bf 2407 u32 rsvd_ple_ofst;
e3ec7017
PKS		 2408 const struct rtw89_hfc_param_ini *hfc_param_ini;
2409 const struct rtw89_dle_mem *dle_mem;
2410 u32 rf_base_addr[2];
0237f65a 2411 u8 support_bands;
d221270a 2412 bool support_bw160;
79a6c9a4 2413 bool hw_sec_hdr;
e3ec7017
PKS		 2414 u8 rf_path_num;
2415 u8 tx_nss;
2416 u8 rx_nss;
2417 u8 acam_num;
2418 u8 bcam_num;
2419 u8 scam_num;
2420
2421 u8 sec_ctrl_efuse_size;
2422 u32 physical_efuse_size;
2423 u32 logical_efuse_size;
2424 u32 limit_efuse_size;
bdfbf06c
PKS		 2425 u32 dav_phy_efuse_size;
2426 u32 dav_log_efuse_size;
e3ec7017
PKS		 2427 u32 phycap_addr;
2428 u32 phycap_size;
2429
2430 const struct rtw89_pwr_cfg * const *pwr_on_seq;
2431 const struct rtw89_pwr_cfg * const *pwr_off_seq;
2432 const struct rtw89_phy_table *bb_table;
eefad995 2433 const struct rtw89_phy_table *bb_gain_table;
e3ec7017
PKS		 2434 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
2435 const struct rtw89_phy_table *nctl_table;
2436 const struct rtw89_txpwr_table *byr_table;
2437 const struct rtw89_phy_dig_gain_table *dig_table;
c7845551 2438 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
e3ec7017
PKS		 2439 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
2440 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2441 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2442 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
2443 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2444 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
ac74f016
ZZY		 2445 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
2446 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2447 [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
e3ec7017
PKS		 2448 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2449 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2450 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2451 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
ac74f016
ZZY		 2452 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2453 [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
e3ec7017
PKS		 2454
2455 u8 txpwr_factor_rf;
2456 u8 txpwr_factor_mac;
2457
2458 u32 para_ver;
2459 u32 wlcx_desired;
2460 u8 btcx_desired;
2461 u8 scbd;
2462 u8 mailbox;
2463
2464 u8 afh_guard_ch;
2465 const u8 *wl_rssi_thres;
2466 const u8 *bt_rssi_thres;
2467 u8 rssi_tol;
2468
2469 u8 mon_reg_num;
2470 const struct rtw89_btc_fbtc_mreg *mon_reg;
2471 u8 rf_para_ulink_num;
2472 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
2473 u8 rf_para_dlink_num;
2474 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
2475 u8 ps_mode_supported;
52edbb9f 2476 u8 low_power_hci_modes;
2af64b4a 2477
aa7f148b 2478 u32 h2c_cctl_func_id;
2af64b4a 2479 u32 hci_func_en_addr;
a95bd62e 2480 u32 h2c_desc_size;
f59acdde 2481 u32 txwd_body_size;
e8955811
PKS		 2482 u32 h2c_ctrl_reg;
2483 const u32 *h2c_regs;
2484 u32 c2h_ctrl_reg;
2485 const u32 *c2h_regs;
ab8a5671 2486 const struct rtw89_page_regs *page_regs;
b7379148
YHZ		 2487 const struct rtw89_reg_def *dcfo_comp;
2488 u8 dcfo_comp_sft;
eeadcd2a 2489 const struct rtw89_imr_info *imr_info;
e3ec7017
PKS		 2490};
2491
4a9e48ac
PKS		 2492union rtw89_bus_info {
2493 const struct rtw89_pci_info *pci;
2494};
2495
861e58c8
ZZY		 2496struct rtw89_driver_info {
2497 const struct rtw89_chip_info *chip;
4a9e48ac 2498 union rtw89_bus_info bus;
861e58c8
ZZY		 2499};
2500
e3ec7017
PKS		 2501enum rtw89_hcifc_mode {
2502 RTW89_HCIFC_POH = 0,
2503 RTW89_HCIFC_STF = 1,
2504 RTW89_HCIFC_SDIO = 2,
2505
2506 /* keep last */
2507 RTW89_HCIFC_MODE_INVALID,
2508};
2509
2510struct rtw89_dle_info {
2511 enum rtw89_qta_mode qta_mode;
2512 u16 wde_pg_size;
2513 u16 ple_pg_size;
2514 u16 c0_rx_qta;
2515 u16 c1_rx_qta;
2516};
2517
2518enum rtw89_host_rpr_mode {
2519 RTW89_RPR_MODE_POH = 0,
2520 RTW89_RPR_MODE_STF
2521};
2522
2523struct rtw89_mac_info {
2524 struct rtw89_dle_info dle_info;
2525 struct rtw89_hfc_param hfc_param;
2526 enum rtw89_qta_mode qta_mode;
2527 u8 rpwm_seq_num;
2528 u8 cpwm_seq_num;
2529};
2530
2531enum rtw89_fw_type {
2532 RTW89_FW_NORMAL = 1,
2533 RTW89_FW_WOWLAN = 3,
2534};
2535
11fe4ccd
ZZY		 2536enum rtw89_fw_feature {
2537 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
2538 RTW89_FW_FEATURE_SCAN_OFFLOAD,
2539 RTW89_FW_FEATURE_TX_WAKE,
edb89629 2540 RTW89_FW_FEATURE_CRASH_TRIGGER,
11fe4ccd
ZZY		 2541};
2542
e3ec7017
PKS		 2543struct rtw89_fw_suit {
2544 const u8 *data;
2545 u32 size;
2546 u8 major_ver;
2547 u8 minor_ver;
2548 u8 sub_ver;
2549 u8 sub_idex;
2550 u16 build_year;
2551 u16 build_mon;
2552 u16 build_date;
2553 u16 build_hour;
2554 u16 build_min;
2555 u8 cmd_ver;
2556};
2557
2558#define RTW89_FW_VER_CODE(major, minor, sub, idx) \
2559 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
2560#define RTW89_FW_SUIT_VER_CODE(s) \
2561 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
2562
2563struct rtw89_fw_info {
2564 const struct firmware *firmware;
2565 struct rtw89_dev *rtwdev;
2566 struct completion completion;
2567 u8 h2c_seq;
2568 u8 rec_seq;
2569 struct rtw89_fw_suit normal;
2570 struct rtw89_fw_suit wowlan;
2571 bool fw_log_enable;
11fe4ccd 2572 u32 feature_map;
e3ec7017
PKS		 2573};
2574
11fe4ccd
ZZY		 2575#define RTW89_CHK_FW_FEATURE(_feat, _fw) \
2576 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
2577
2578#define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
2579 ((_fw)->feature_map |= BIT(_fw_feature))
2580
e3ec7017
PKS		 2581struct rtw89_cam_info {
2582 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
2583 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
2584 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
2585};
2586
2587enum rtw89_sar_sources {
2588 RTW89_SAR_SOURCE_NONE,
2589 RTW89_SAR_SOURCE_COMMON,
2590
2591 RTW89_SAR_SOURCE_NR,
2592};
2593
425671f0
ZZY		 2594enum rtw89_sar_subband {
2595 RTW89_SAR_2GHZ_SUBBAND,
2596 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
2597 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
2598 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */
2599 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
2600 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
2601 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
2602 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
2603 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
2604 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
2605
2606 RTW89_SAR_SUBBAND_NR,
2607};
2608
e3ec7017 2609struct rtw89_sar_cfg_common {
425671f0
ZZY		 2610 bool set[RTW89_SAR_SUBBAND_NR];
2611 s32 cfg[RTW89_SAR_SUBBAND_NR];
e3ec7017
PKS		 2612};
2613
2614struct rtw89_sar_info {
2615 /* used to decide how to acces SAR cfg union */
2616 enum rtw89_sar_sources src;
2617
2618 /* reserved for different knids of SAR cfg struct.
2619 * supposed that a single cfg struct cannot handle various SAR sources.
2620 */
2621 union {
2622 struct rtw89_sar_cfg_common cfg_common;
2623 };
2624};
2625
7cf674ff
ZZY		 2626enum rtw89_entity_mode {
2627 RTW89_ENTITY_MODE_SCC,
2628};
2629
e3ec7017
PKS		 2630struct rtw89_hal {
2631 u32 rx_fltr;
2632 u8 cv;
e3ec7017
PKS		 2633 u32 sw_amsdu_max_size;
2634 u32 antenna_tx;
2635 u32 antenna_rx;
2636 u8 tx_nss;
2637 u8 rx_nss;
1c2423de 2638 bool support_cckpd;
1e6f0d2a 2639 bool support_igi;
967439c7 2640
494399b2
ZZY		 2641 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
2642 struct cfg80211_chan_def chandef[NUM_OF_RTW89_SUB_ENTITY];
2643
967439c7 2644 bool entity_active;
7cf674ff 2645 enum rtw89_entity_mode entity_mode;
cbb145b9
ZZY		 2646
2647 struct rtw89_chan chan[NUM_OF_RTW89_SUB_ENTITY];
2648 struct rtw89_chan_rcd chan_rcd[NUM_OF_RTW89_SUB_ENTITY];
e3ec7017
PKS		 2649};
2650
2651#define RTW89_MAX_MAC_ID_NUM 128
89590777 2652#define RTW89_MAX_PKT_OFLD_NUM 255
e3ec7017
PKS		 2653
2654enum rtw89_flags {
2655 RTW89_FLAG_POWERON,
2656 RTW89_FLAG_FW_RDY,
2657 RTW89_FLAG_RUNNING,
2658 RTW89_FLAG_BFEE_MON,
2659 RTW89_FLAG_BFEE_EN,
2660 RTW89_FLAG_NAPI_RUNNING,
2661 RTW89_FLAG_LEISURE_PS,
2662 RTW89_FLAG_LOW_POWER_MODE,
2663 RTW89_FLAG_INACTIVE_PS,
edb89629 2664 RTW89_FLAG_RESTART_TRIGGER,
e3ec7017
PKS		 2665
2666 NUM_OF_RTW89_FLAGS,
2667};
2668
2669struct rtw89_pkt_stat {
2670 u16 beacon_nr;
2671 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
2672};
2673
2674DECLARE_EWMA(thermal, 4, 4);
2675
2676struct rtw89_phy_stat {
2677 struct ewma_thermal avg_thermal[RF_PATH_MAX];
2678 struct rtw89_pkt_stat cur_pkt_stat;
2679 struct rtw89_pkt_stat last_pkt_stat;
2680};
2681
2682#define RTW89_DACK_PATH_NR 2
2683#define RTW89_DACK_IDX_NR 2
2684#define RTW89_DACK_MSBK_NR 16
2685struct rtw89_dack_info {
2686 bool dack_done;
2687 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
2688 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2689 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2690 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2691 u32 dack_cnt;
2692 bool addck_timeout[RTW89_DACK_PATH_NR];
2693 bool dadck_timeout[RTW89_DACK_PATH_NR];
2694 bool msbk_timeout[RTW89_DACK_PATH_NR];
2695};
2696
2697#define RTW89_IQK_CHS_NR 2
2698#define RTW89_IQK_PATH_NR 4
16b44ed0
PKS		 2699
2700struct rtw89_mcc_info {
2701 u8 ch[RTW89_IQK_CHS_NR];
2702 u8 band[RTW89_IQK_CHS_NR];
2703 u8 table_idx;
2704};
2705
fb8177d7
PKS		 2706struct rtw89_lck_info {
2707 u8 thermal[RF_PATH_MAX];
2708};
2709
e3d365ff
PKS		 2710struct rtw89_rx_dck_info {
2711 u8 thermal[RF_PATH_MAX];
2712};
2713
e3ec7017
PKS		 2714struct rtw89_iqk_info {
2715 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2716 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2da8109d 2717 bool lok_fail[RTW89_IQK_PATH_NR];
e3ec7017
PKS		 2718 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2719 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2720 u32 iqk_fail_cnt;
2721 bool is_iqk_init;
2722 u32 iqk_channel[RTW89_IQK_CHS_NR];
2723 u8 iqk_band[RTW89_IQK_PATH_NR];
2724 u8 iqk_ch[RTW89_IQK_PATH_NR];
2725 u8 iqk_bw[RTW89_IQK_PATH_NR];
2726 u8 kcount;
2727 u8 iqk_times;
2728 u8 version;
2729 u32 nb_txcfir[RTW89_IQK_PATH_NR];
2730 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
2731 u32 bp_txkresult[RTW89_IQK_PATH_NR];
2732 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
2733 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
2734 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
2735 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
2736 bool is_nbiqk;
2737 bool iqk_fft_en;
2738 bool iqk_xym_en;
2739 bool iqk_sram_en;
2740 bool iqk_cfir_en;
2741 u8 thermal[RTW89_IQK_PATH_NR];
2742 bool thermal_rek_en;
2743 u32 syn1to2;
2744 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2745 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
2da8109d
PKS		 2746 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2747 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
e3ec7017
PKS		 2748};
2749
2750#define RTW89_DPK_RF_PATH 2
2751#define RTW89_DPK_AVG_THERMAL_NUM 8
2752#define RTW89_DPK_BKUP_NUM 2
2753struct rtw89_dpk_bkup_para {
2754 enum rtw89_band band;
2755 enum rtw89_bandwidth bw;
2756 u8 ch;
2757 bool path_ok;
da4cea16 2758 u8 mdpd_en;
e3ec7017
PKS		 2759 u8 txagc_dpk;
2760 u8 ther_dpk;
2761 u8 gs;
2762 u16 pwsf;
2763};
2764
2765struct rtw89_dpk_info {
2766 bool is_dpk_enable;
2767 bool is_dpk_reload_en;
da4cea16
PKS		 2768 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2769 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2770 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2771 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
e3ec7017 2772 u8 cur_idx[RTW89_DPK_RF_PATH];
da4cea16 2773 u8 cur_k_set;
e3ec7017
PKS		 2774 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2775};
2776
2777struct rtw89_fem_info {
2778 bool elna_2g;
2779 bool elna_5g;
2780 bool epa_2g;
2781 bool epa_5g;
da4cea16 2782 bool epa_6g;
e3ec7017
PKS		 2783};
2784
2785struct rtw89_phy_ch_info {
2786 u8 rssi_min;
2787 u16 rssi_min_macid;
2788 u8 pre_rssi_min;
2789 u8 rssi_max;
2790 u16 rssi_max_macid;
2791 u8 rxsc_160;
2792 u8 rxsc_80;
2793 u8 rxsc_40;
2794 u8 rxsc_20;
2795 u8 rxsc_l;
2796 u8 is_noisy;
2797};
2798
2799struct rtw89_agc_gaincode_set {
2800 u8 lna_idx;
2801 u8 tia_idx;
2802 u8 rxb_idx;
2803};
2804
2805#define IGI_RSSI_TH_NUM 5
2806#define FA_TH_NUM 4
2807#define LNA_GAIN_NUM 7
2808#define TIA_GAIN_NUM 2
2809struct rtw89_dig_info {
2810 struct rtw89_agc_gaincode_set cur_gaincode;
2811 bool force_gaincode_idx_en;
2812 struct rtw89_agc_gaincode_set force_gaincode;
2813 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
2814 u16 fa_th[FA_TH_NUM];
2815 u8 igi_rssi;
2816 u8 igi_fa_rssi;
2817 u8 fa_rssi_ofst;
2818 u8 dyn_igi_max;
2819 u8 dyn_igi_min;
2820 bool dyn_pd_th_en;
2821 u8 dyn_pd_th_max;
2822 u8 pd_low_th_ofst;
2823 u8 ib_pbk;
2824 s8 ib_pkpwr;
2825 s8 lna_gain_a[LNA_GAIN_NUM];
2826 s8 lna_gain_g[LNA_GAIN_NUM];
2827 s8 *lna_gain;
2828 s8 tia_gain_a[TIA_GAIN_NUM];
2829 s8 tia_gain_g[TIA_GAIN_NUM];
2830 s8 *tia_gain;
2831 bool is_linked_pre;
2832 bool bypass_dig;
2833};
2834
2835enum rtw89_multi_cfo_mode {
2836 RTW89_PKT_BASED_AVG_MODE = 0,
2837 RTW89_ENTRY_BASED_AVG_MODE = 1,
2838 RTW89_TP_BASED_AVG_MODE = 2,
2839};
2840
2841enum rtw89_phy_cfo_status {
2842 RTW89_PHY_DCFO_STATE_NORMAL = 0,
2843 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
bc013052 2844 RTW89_PHY_DCFO_STATE_HOLD = 2,
e3ec7017
PKS		 2845 RTW89_PHY_DCFO_STATE_MAX
2846};
2847
bc013052
EH		 2848enum rtw89_phy_cfo_ul_ofdma_acc_mode {
2849 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
2850 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
2851};
2852
e3ec7017
PKS		 2853struct rtw89_cfo_tracking_info {
2854 u16 cfo_timer_ms;
2855 bool cfo_trig_by_timer_en;
2856 enum rtw89_phy_cfo_status phy_cfo_status;
bc013052 2857 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
e3ec7017
PKS		 2858 u8 phy_cfo_trk_cnt;
2859 bool is_adjust;
2860 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
2861 bool apply_compensation;
2862 u8 crystal_cap;
2863 u8 crystal_cap_default;
2864 u8 def_x_cap;
2865 s8 x_cap_ofst;
2866 u32 sta_cfo_tolerance;
2867 s32 cfo_tail[CFO_TRACK_MAX_USER];
2868 u16 cfo_cnt[CFO_TRACK_MAX_USER];
2869 s32 cfo_avg_pre;
2870 s32 cfo_avg[CFO_TRACK_MAX_USER];
2871 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
2872 u32 packet_count;
2873 u32 packet_count_pre;
2874 s32 residual_cfo_acc;
2875 u8 phy_cfotrk_state;
2876 u8 phy_cfotrk_cnt;
a9e06f2e
YTC		 2877 bool divergence_lock_en;
2878 u8 x_cap_lb;
2879 u8 x_cap_ub;
2880 u8 lock_cnt;
e3ec7017
PKS		 2881};
2882
2883/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
2884#define TSSI_TRIM_CH_GROUP_NUM 8
a82174c6 2885#define TSSI_TRIM_CH_GROUP_NUM_6G 16
e3ec7017
PKS		 2886
2887#define TSSI_CCK_CH_GROUP_NUM 6
2888#define TSSI_MCS_2G_CH_GROUP_NUM 5
2889#define TSSI_MCS_5G_CH_GROUP_NUM 14
a82174c6 2890#define TSSI_MCS_6G_CH_GROUP_NUM 32
e3ec7017
PKS		 2891#define TSSI_MCS_CH_GROUP_NUM \
2892 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
2893
2894struct rtw89_tssi_info {
2895 u8 thermal[RF_PATH_MAX];
2896 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
a82174c6 2897 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
e3ec7017
PKS		 2898 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
2899 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
a82174c6 2900 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
e3ec7017
PKS		 2901 s8 extra_ofst[RF_PATH_MAX];
2902 bool tssi_tracking_check[RF_PATH_MAX];
2903 u8 default_txagc_offset[RF_PATH_MAX];
2904 u32 base_thermal[RF_PATH_MAX];
2905};
2906
2907struct rtw89_power_trim_info {
2908 bool pg_thermal_trim;
2909 bool pg_pa_bias_trim;
2910 u8 thermal_trim[RF_PATH_MAX];
2911 u8 pa_bias_trim[RF_PATH_MAX];
2912};
2913
2914struct rtw89_regulatory {
2915 char alpha2[3];
2916 u8 txpwr_regd[RTW89_BAND_MAX];
2917};
2918
2919enum rtw89_ifs_clm_application {
2920 RTW89_IFS_CLM_INIT = 0,
2921 RTW89_IFS_CLM_BACKGROUND = 1,
2922 RTW89_IFS_CLM_ACS = 2,
2923 RTW89_IFS_CLM_DIG = 3,
2924 RTW89_IFS_CLM_TDMA_DIG = 4,
2925 RTW89_IFS_CLM_DBG = 5,
2926 RTW89_IFS_CLM_DBG_MANUAL = 6
2927};
2928
2929enum rtw89_env_racing_lv {
2930 RTW89_RAC_RELEASE = 0,
2931 RTW89_RAC_LV_1 = 1,
2932 RTW89_RAC_LV_2 = 2,
2933 RTW89_RAC_LV_3 = 3,
2934 RTW89_RAC_LV_4 = 4,
2935 RTW89_RAC_MAX_NUM = 5
2936};
2937
2938struct rtw89_ccx_para_info {
2939 enum rtw89_env_racing_lv rac_lv;
2940 u16 mntr_time;
2941 u8 nhm_manual_th_ofst;
2942 u8 nhm_manual_th0;
2943 enum rtw89_ifs_clm_application ifs_clm_app;
2944 u32 ifs_clm_manual_th_times;
2945 u32 ifs_clm_manual_th0;
2946 u8 fahm_manual_th_ofst;
2947 u8 fahm_manual_th0;
2948 u8 fahm_numer_opt;
2949 u8 fahm_denom_opt;
2950};
2951
2952enum rtw89_ccx_edcca_opt_sc_idx {
2953 RTW89_CCX_EDCCA_SEG0_P0 = 0,
2954 RTW89_CCX_EDCCA_SEG0_S1 = 1,
2955 RTW89_CCX_EDCCA_SEG0_S2 = 2,
2956 RTW89_CCX_EDCCA_SEG0_S3 = 3,
2957 RTW89_CCX_EDCCA_SEG1_P0 = 4,
2958 RTW89_CCX_EDCCA_SEG1_S1 = 5,
2959 RTW89_CCX_EDCCA_SEG1_S2 = 6,
2960 RTW89_CCX_EDCCA_SEG1_S3 = 7
2961};
2962
2963enum rtw89_ccx_edcca_opt_bw_idx {
2964 RTW89_CCX_EDCCA_BW20_0 = 0,
2965 RTW89_CCX_EDCCA_BW20_1 = 1,
2966 RTW89_CCX_EDCCA_BW20_2 = 2,
2967 RTW89_CCX_EDCCA_BW20_3 = 3,
2968 RTW89_CCX_EDCCA_BW20_4 = 4,
2969 RTW89_CCX_EDCCA_BW20_5 = 5,
2970 RTW89_CCX_EDCCA_BW20_6 = 6,
2971 RTW89_CCX_EDCCA_BW20_7 = 7
2972};
2973
2974#define RTW89_NHM_TH_NUM 11
2975#define RTW89_FAHM_TH_NUM 11
2976#define RTW89_NHM_RPT_NUM 12
2977#define RTW89_FAHM_RPT_NUM 12
2978#define RTW89_IFS_CLM_NUM 4
2979struct rtw89_env_monitor_info {
2980 u32 ccx_trigger_time;
2981 u64 start_time;
2982 u8 ccx_rpt_stamp;
2983 u8 ccx_watchdog_result;
2984 bool ccx_ongoing;
2985 u8 ccx_rac_lv;
2986 bool ccx_manual_ctrl;
2987 u8 ccx_pre_rssi;
2988 u16 clm_mntr_time;
2989 u16 nhm_mntr_time;
2990 u16 ifs_clm_mntr_time;
2991 enum rtw89_ifs_clm_application ifs_clm_app;
2992 u16 fahm_mntr_time;
2993 u16 edcca_clm_mntr_time;
2994 u16 ccx_period;
2995 u8 ccx_unit_idx;
2996 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;
2997 u8 nhm_th[RTW89_NHM_TH_NUM];
2998 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
2999 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
3000 u8 fahm_numer_opt;
3001 u8 fahm_denom_opt;
3002 u8 fahm_th[RTW89_FAHM_TH_NUM];
3003 u16 clm_result;
3004 u16 nhm_result[RTW89_NHM_RPT_NUM];
3005 u8 nhm_wgt[RTW89_NHM_RPT_NUM];
3006 u16 nhm_tx_cnt;
3007 u16 nhm_cca_cnt;
3008 u16 nhm_idle_cnt;
3009 u16 ifs_clm_tx;
3010 u16 ifs_clm_edcca_excl_cca;
3011 u16 ifs_clm_ofdmfa;
3012 u16 ifs_clm_ofdmcca_excl_fa;
3013 u16 ifs_clm_cckfa;
3014 u16 ifs_clm_cckcca_excl_fa;
3015 u16 ifs_clm_total_ifs;
3016 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
3017 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
3018 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
3019 u16 fahm_result[RTW89_FAHM_RPT_NUM];
3020 u16 fahm_denom_result;
3021 u16 edcca_clm_result;
3022 u8 clm_ratio;
3023 u8 nhm_rpt[RTW89_NHM_RPT_NUM];
3024 u8 nhm_tx_ratio;
3025 u8 nhm_cca_ratio;
3026 u8 nhm_idle_ratio;
3027 u8 nhm_ratio;
3028 u16 nhm_result_sum;
3029 u8 nhm_pwr;
3030 u8 ifs_clm_tx_ratio;
3031 u8 ifs_clm_edcca_excl_cca_ratio;
3032 u8 ifs_clm_cck_fa_ratio;
3033 u8 ifs_clm_ofdm_fa_ratio;
3034 u8 ifs_clm_cck_cca_excl_fa_ratio;
3035 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
3036 u16 ifs_clm_cck_fa_permil;
3037 u16 ifs_clm_ofdm_fa_permil;
3038 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
3039 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
3040 u8 fahm_rpt[RTW89_FAHM_RPT_NUM];
3041 u16 fahm_result_sum;
3042 u8 fahm_ratio;
3043 u8 fahm_denom_ratio;
3044 u8 fahm_pwr;
3045 u8 edcca_clm_ratio;
3046};
3047
3048enum rtw89_ser_rcvy_step {
3049 RTW89_SER_DRV_STOP_TX,
3050 RTW89_SER_DRV_STOP_RX,
3051 RTW89_SER_DRV_STOP_RUN,
3052 RTW89_SER_HAL_STOP_DMA,
3053 RTW89_NUM_OF_SER_FLAGS
3054};
3055
3056struct rtw89_ser {
3057 u8 state;
3058 u8 alarm_event;
3059
3060 struct work_struct ser_hdl_work;
3061 struct delayed_work ser_alarm_work;
af5175ac
JP		 3062 const struct state_ent *st_tbl;
3063 const struct event_ent *ev_tbl;
e3ec7017
PKS		 3064 struct list_head msg_q;
3065 spinlock_t msg_q_lock; /* lock when read/write ser msg */
3066 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
3067};
3068
3069enum rtw89_mac_ax_ps_mode {
3070 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
3071 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
3072 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
3073 RTW89_MAC_AX_PS_MODE_MAX = 3,
3074};
3075
3076enum rtw89_last_rpwm_mode {
3077 RTW89_LAST_RPWM_PS = 0x0,
3078 RTW89_LAST_RPWM_ACTIVE = 0x6,
3079};
3080
3081struct rtw89_lps_parm {
3082 u8 macid;
3083 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
3084 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
3085};
3086
3087struct rtw89_ppdu_sts_info {
3088 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
3089 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
3090};
3091
3092struct rtw89_early_h2c {
3093 struct list_head list;
3094 u8 *h2c;
3095 u16 h2c_len;
3096};
3097
89590777
PHH		 3098struct rtw89_hw_scan_info {
3099 struct ieee80211_vif *scanning_vif;
3100 struct list_head pkt_list[NUM_NL80211_BANDS];
3101 u8 op_pri_ch;
3102 u8 op_chan;
3103 u8 op_bw;
3104 u8 op_band;
3105};
3106
e885871e
ZZY		 3107enum rtw89_phy_bb_gain_band {
3108 RTW89_BB_GAIN_BAND_2G = 0,
3109 RTW89_BB_GAIN_BAND_5G_L = 1,
3110 RTW89_BB_GAIN_BAND_5G_M = 2,
3111 RTW89_BB_GAIN_BAND_5G_H = 3,
3112 RTW89_BB_GAIN_BAND_6G_L = 4,
3113 RTW89_BB_GAIN_BAND_6G_M = 5,
3114 RTW89_BB_GAIN_BAND_6G_H = 6,
3115 RTW89_BB_GAIN_BAND_6G_UH = 7,
3116
3117 RTW89_BB_GAIN_BAND_NR,
3118};
3119
3120enum rtw89_phy_bb_rxsc_num {
3121 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
3122 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
3123 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
3124};
3125
3126struct rtw89_phy_bb_gain_info {
3127 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3128 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
3129 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3130 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3131 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3132 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
3133 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
3134 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3135 [RTW89_BB_RXSC_NUM_40];
3136 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3137 [RTW89_BB_RXSC_NUM_80];
3138 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3139 [RTW89_BB_RXSC_NUM_160];
3140};
3141
e6b17cbd
PKS		 3142struct rtw89_phy_efuse_gain {
3143 bool offset_valid;
3144 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
3145 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
3146};
3147
e3ec7017
PKS		 3148struct rtw89_dev {
3149 struct ieee80211_hw *hw;
3150 struct device *dev;
3151
3152 bool dbcc_en;
89590777 3153 struct rtw89_hw_scan_info scan_info;
e3ec7017 3154 const struct rtw89_chip_info *chip;
4a9e48ac 3155 const struct rtw89_pci_info *pci_info;
e3ec7017
PKS		 3156 struct rtw89_hal hal;
3157 struct rtw89_mac_info mac;
3158 struct rtw89_fw_info fw;
3159 struct rtw89_hci_info hci;
3160 struct rtw89_efuse efuse;
3161 struct rtw89_traffic_stats stats;
3162
3163 /* ensures exclusive access from mac80211 callbacks */
3164 struct mutex mutex;
3165 struct list_head rtwvifs_list;
3166 /* used to protect rf read write */
3167 struct mutex rf_mutex;
3168 struct workqueue_struct *txq_wq;
3169 struct work_struct txq_work;
3170 struct delayed_work txq_reinvoke_work;
679955d5 3171 /* used to protect ba_list and forbid_ba_list */
e3ec7017
PKS		 3172 spinlock_t ba_lock;
3173 /* txqs to setup ba session */
3174 struct list_head ba_list;
679955d5
KCC		 3175 /* txqs to forbid ba session */
3176 struct list_head forbid_ba_list;
e3ec7017 3177 struct work_struct ba_work;
7bfd05ff
CYL		 3178 /* used to protect rpwm */
3179 spinlock_t rpwm_lock;
e3ec7017
PKS		 3180
3181 struct rtw89_cam_info cam_info;
3182
3183 struct sk_buff_head c2h_queue;
3184 struct work_struct c2h_work;
89590777 3185 struct work_struct ips_work;
e3ec7017
PKS		 3186
3187 struct list_head early_h2c_list;
3188
3189 struct rtw89_ser ser;
3190
20d9fc88 3191 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
e3ec7017
PKS		 3192 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
3193 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
89590777 3194 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
e3ec7017
PKS		 3195
3196 struct rtw89_phy_stat phystat;
3197 struct rtw89_dack_info dack;
3198 struct rtw89_iqk_info iqk;
3199 struct rtw89_dpk_info dpk;
16b44ed0 3200 struct rtw89_mcc_info mcc;
fb8177d7 3201 struct rtw89_lck_info lck;
e3d365ff 3202 struct rtw89_rx_dck_info rx_dck;
e3ec7017
PKS		 3203 bool is_tssi_mode[RF_PATH_MAX];
3204 bool is_bt_iqk_timeout;
3205
3206 struct rtw89_fem_info fem;
3207 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];
3208 struct rtw89_tssi_info tssi;
3209 struct rtw89_power_trim_info pwr_trim;
3210
3211 struct rtw89_cfo_tracking_info cfo_tracking;
3212 struct rtw89_env_monitor_info env_monitor;
3213 struct rtw89_dig_info dig;
3214 struct rtw89_phy_ch_info ch_info;
e885871e 3215 struct rtw89_phy_bb_gain_info bb_gain;
e6b17cbd 3216 struct rtw89_phy_efuse_gain efuse_gain;
e885871e 3217
e3ec7017
PKS		 3218 struct delayed_work track_work;
3219 struct delayed_work coex_act1_work;
3220 struct delayed_work coex_bt_devinfo_work;
3221 struct delayed_work coex_rfk_chk_work;
3222 struct delayed_work cfo_track_work;
679955d5 3223 struct delayed_work forbid_ba_work;
e3ec7017
PKS		 3224 struct rtw89_ppdu_sts_info ppdu_sts;
3225 u8 total_sta_assoc;
3226 bool scanning;
3227
3228 const struct rtw89_regulatory *regd;
3229 struct rtw89_sar_info sar;
3230
3231 struct rtw89_btc btc;
3232 enum rtw89_ps_mode ps_mode;
3233 bool lps_enabled;
3234
3235 /* napi structure */
3236 struct net_device netdev;
3237 struct napi_struct napi;
3238 int napi_budget_countdown;
3239
3240 /* HCI related data, keep last */
2e2f63a1 3241 u8 priv[] __aligned(sizeof(void *));
e3ec7017
PKS		 3242};
3243
3244static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
3245 struct rtw89_core_tx_request *tx_req)
3246{
3247 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
3248}
3249
3250static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
3251{
3252 rtwdev->hci.ops->reset(rtwdev);
3253}
3254
3255static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
3256{
3257 return rtwdev->hci.ops->start(rtwdev);
3258}
3259
3260static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
3261{
3262 rtwdev->hci.ops->stop(rtwdev);
3263}
3264
3265static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
3266{
3267 return rtwdev->hci.ops->deinit(rtwdev);
3268}
3269
52edbb9f
PKS		 3270static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
3271{
3272 rtwdev->hci.ops->pause(rtwdev, pause);
3273}
3274
3275static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
3276{
3277 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
3278}
3279
e3ec7017
PKS		 3280static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
3281{
3282 rtwdev->hci.ops->recalc_int_mit(rtwdev);
3283}
3284
3285static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
3286{
3287 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
3288}
3289
3290static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
3291{
3292 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
3293}
3294
3295static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
3296 bool drop)
3297{
fc5f311f
PKS		 3298 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
3299 return;
3300
e3ec7017
PKS		 3301 if (rtwdev->hci.ops->flush_queues)
3302 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
3303}
3304
14f9f479
ZZY		 3305static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
3306{
3307 if (rtwdev->hci.ops->recovery_start)
3308 rtwdev->hci.ops->recovery_start(rtwdev);
3309}
3310
3311static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
3312{
3313 if (rtwdev->hci.ops->recovery_complete)
3314 rtwdev->hci.ops->recovery_complete(rtwdev);
3315}
3316
e3ec7017
PKS		 3317static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
3318{
3319 return rtwdev->hci.ops->read8(rtwdev, addr);
3320}
3321
3322static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
3323{
3324 return rtwdev->hci.ops->read16(rtwdev, addr);
3325}
3326
3327static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
3328{
3329 return rtwdev->hci.ops->read32(rtwdev, addr);
3330}
3331
3332static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
3333{
3334 rtwdev->hci.ops->write8(rtwdev, addr, data);
3335}
3336
3337static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
3338{
3339 rtwdev->hci.ops->write16(rtwdev, addr, data);
3340}
3341
3342static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
3343{
3344 rtwdev->hci.ops->write32(rtwdev, addr, data);
3345}
3346
3347static inline void
3348rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
3349{
3350 u8 val;
3351
3352 val = rtw89_read8(rtwdev, addr);
3353 rtw89_write8(rtwdev, addr, val | bit);
3354}
3355
3356static inline void
3357rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
3358{
3359 u16 val;
3360
3361 val = rtw89_read16(rtwdev, addr);
3362 rtw89_write16(rtwdev, addr, val | bit);
3363}
3364
3365static inline void
3366rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
3367{
3368 u32 val;
3369
3370 val = rtw89_read32(rtwdev, addr);
3371 rtw89_write32(rtwdev, addr, val | bit);
3372}
3373
3374static inline void
3375rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
3376{
3377 u8 val;
3378
3379 val = rtw89_read8(rtwdev, addr);
3380 rtw89_write8(rtwdev, addr, val & ~bit);
3381}
3382
3383static inline void
3384rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
3385{
3386 u16 val;
3387
3388 val = rtw89_read16(rtwdev, addr);
3389 rtw89_write16(rtwdev, addr, val & ~bit);
3390}
3391
3392static inline void
3393rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
3394{
3395 u32 val;
3396
3397 val = rtw89_read32(rtwdev, addr);
3398 rtw89_write32(rtwdev, addr, val & ~bit);
3399}
3400
3401static inline u32
3402rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3403{
3404 u32 shift = __ffs(mask);
3405 u32 orig;
3406 u32 ret;
3407
3408 orig = rtw89_read32(rtwdev, addr);
3409 ret = (orig & mask) >> shift;
3410
3411 return ret;
3412}
3413
3414static inline u16
3415rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3416{
3417 u32 shift = __ffs(mask);
3418 u32 orig;
3419 u32 ret;
3420
3421 orig = rtw89_read16(rtwdev, addr);
3422 ret = (orig & mask) >> shift;
3423
3424 return ret;
3425}
3426
3427static inline u8
3428rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3429{
3430 u32 shift = __ffs(mask);
3431 u32 orig;
3432 u32 ret;
3433
3434 orig = rtw89_read8(rtwdev, addr);
3435 ret = (orig & mask) >> shift;
3436
3437 return ret;
3438}
3439
3440static inline void
3441rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
3442{
3443 u32 shift = __ffs(mask);
3444 u32 orig;
3445 u32 set;
3446
3447 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
3448
3449 orig = rtw89_read32(rtwdev, addr);
3450 set = (orig & ~mask) | ((data << shift) & mask);
3451 rtw89_write32(rtwdev, addr, set);
3452}
3453
3454static inline void
3455rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
3456{
3457 u32 shift;
3458 u16 orig, set;
3459
3460 mask &= 0xffff;
3461 shift = __ffs(mask);
3462
3463 orig = rtw89_read16(rtwdev, addr);
3464 set = (orig & ~mask) | ((data << shift) & mask);
3465 rtw89_write16(rtwdev, addr, set);
3466}
3467
3468static inline void
3469rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
3470{
3471 u32 shift;
3472 u8 orig, set;
3473
3474 mask &= 0xff;
3475 shift = __ffs(mask);
3476
3477 orig = rtw89_read8(rtwdev, addr);
3478 set = (orig & ~mask) | ((data << shift) & mask);
3479 rtw89_write8(rtwdev, addr, set);
3480}
3481
3482static inline u32
3483rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3484 u32 addr, u32 mask)
3485{
3486 u32 val;
3487
3488 mutex_lock(&rtwdev->rf_mutex);
3489 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
3490 mutex_unlock(&rtwdev->rf_mutex);
3491
3492 return val;
3493}
3494
3495static inline void
3496rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3497 u32 addr, u32 mask, u32 data)
3498{
3499 mutex_lock(&rtwdev->rf_mutex);
3500 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
3501 mutex_unlock(&rtwdev->rf_mutex);
3502}
3503
3504static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
3505{
3506 void *p = rtwtxq;
3507
3508 return container_of(p, struct ieee80211_txq, drv_priv);
3509}
3510
3511static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
3512 struct ieee80211_txq *txq)
3513{
3514 struct rtw89_txq *rtwtxq;
3515
3516 if (!txq)
3517 return;
3518
3519 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3520 INIT_LIST_HEAD(&rtwtxq->list);
3521}
3522
3523static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
3524{
3525 void *p = rtwvif;
3526
3527 return container_of(p, struct ieee80211_vif, drv_priv);
3528}
3529
3530static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
3531{
3532 void *p = rtwsta;
3533
3534 return container_of(p, struct ieee80211_sta, drv_priv);
3535}
3536
40822e07
PKS		 3537static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
3538{
3539 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
3540}
3541
3542static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
3543{
3544 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
3545}
3546
167044af
PKS		 3547static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
3548{
3549 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
3550 return RATE_INFO_BW_160;
3551 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
3552 return RATE_INFO_BW_80;
3553 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
3554 return RATE_INFO_BW_40;
3555 else
3556 return RATE_INFO_BW_20;
3557}
3558
a06d2dd7
ZZY		 3559static inline
3560enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
3561{
3562 switch (hw_band) {
3563 default:
3564 case RTW89_BAND_2G:
3565 return NL80211_BAND_2GHZ;
3566 case RTW89_BAND_5G:
3567 return NL80211_BAND_5GHZ;
3568 case RTW89_BAND_6G:
3569 return NL80211_BAND_6GHZ;
3570 }
3571}
3572
e715f10f
PKS		 3573static inline
3574enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
3575{
3576 switch (width) {
3577 default:
3578 WARN(1, "Not support bandwidth %d\n", width);
3579 fallthrough;
3580 case NL80211_CHAN_WIDTH_20_NOHT:
3581 case NL80211_CHAN_WIDTH_20:
3582 return RTW89_CHANNEL_WIDTH_20;
3583 case NL80211_CHAN_WIDTH_40:
3584 return RTW89_CHANNEL_WIDTH_40;
3585 case NL80211_CHAN_WIDTH_80:
3586 return RTW89_CHANNEL_WIDTH_80;
3587 case NL80211_CHAN_WIDTH_160:
3588 return RTW89_CHANNEL_WIDTH_160;
3589 }
3590}
3591
2ab856cc
PKS		 3592static inline
3593struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
3594 struct rtw89_sta *rtwsta)
3595{
7312100d
PKS		 3596 if (rtwsta) {
3597 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
3598
3599 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
3600 return &rtwsta->addr_cam;
3601 }
2ab856cc 3602 return &rtwvif->addr_cam;
39913cc8
PKS		 3603}
3604
3605static inline
3606struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
3607 struct rtw89_sta *rtwsta)
3608{
3609 if (rtwsta) {
3610 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
3611
3612 if (sta->tdls)
3613 return &rtwsta->bssid_cam;
3614 }
3615 return &rtwvif->bssid_cam;
2ab856cc
PKS		 3616}
3617
e3ec7017
PKS		 3618static inline
3619void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
ce57e55c
ZZY		 3620 struct rtw89_channel_help_params *p,
3621 const struct rtw89_chan *chan,
3622 enum rtw89_mac_idx mac_idx,
3623 enum rtw89_phy_idx phy_idx)
e3ec7017 3624{
ce57e55c
ZZY		 3625 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
3626 mac_idx, phy_idx);
e3ec7017
PKS		 3627}
3628
3629static inline
3630void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
ce57e55c
ZZY		 3631 struct rtw89_channel_help_params *p,
3632 const struct rtw89_chan *chan,
3633 enum rtw89_mac_idx mac_idx,
3634 enum rtw89_phy_idx phy_idx)
e3ec7017 3635{
ce57e55c
ZZY		 3636 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
3637 mac_idx, phy_idx);
e3ec7017
PKS		 3638}
3639
494399b2
ZZY		 3640static inline
3641const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
3642 enum rtw89_sub_entity_idx idx)
3643{
3644 struct rtw89_hal *hal = &rtwdev->hal;
3645
3646 return &hal->chandef[idx];
3647}
3648
cbb145b9
ZZY		 3649static inline
3650const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
3651 enum rtw89_sub_entity_idx idx)
3652{
3653 struct rtw89_hal *hal = &rtwdev->hal;
3654
3655 return &hal->chan[idx];
3656}
3657
3658static inline
3659const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
3660 enum rtw89_sub_entity_idx idx)
3661{
3662 struct rtw89_hal *hal = &rtwdev->hal;
3663
3664 return &hal->chan_rcd[idx];
3665}
3666
e3ec7017
PKS		 3667static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
3668{
3669 const struct rtw89_chip_info *chip = rtwdev->chip;
3670
3671 if (chip->ops->fem_setup)
3672 chip->ops->fem_setup(rtwdev);
3673}
3674
3675static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
3676{
3677 const struct rtw89_chip_info *chip = rtwdev->chip;
3678
3679 if (chip->ops->bb_sethw)
3680 chip->ops->bb_sethw(rtwdev);
3681}
3682
3683static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
3684{
3685 const struct rtw89_chip_info *chip = rtwdev->chip;
3686
3687 if (chip->ops->rfk_init)
3688 chip->ops->rfk_init(rtwdev);
3689}
3690
3691static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
3692{
3693 const struct rtw89_chip_info *chip = rtwdev->chip;
3694
3695 if (chip->ops->rfk_channel)
3696 chip->ops->rfk_channel(rtwdev);
3697}
3698
010d0051
ZZY		 3699static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
3700 enum rtw89_phy_idx phy_idx)
e3ec7017
PKS		 3701{
3702 const struct rtw89_chip_info *chip = rtwdev->chip;
3703
3704 if (chip->ops->rfk_band_changed)
010d0051 3705 chip->ops->rfk_band_changed(rtwdev, phy_idx);
e3ec7017
PKS		 3706}
3707
3708static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
3709{
3710 const struct rtw89_chip_info *chip = rtwdev->chip;
3711
3712 if (chip->ops->rfk_scan)
3713 chip->ops->rfk_scan(rtwdev, start);
3714}
3715
3716static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
3717{
3718 const struct rtw89_chip_info *chip = rtwdev->chip;
3719
3720 if (chip->ops->rfk_track)
3721 chip->ops->rfk_track(rtwdev);
3722}
3723
3724static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
3725{
3726 const struct rtw89_chip_info *chip = rtwdev->chip;
3727
3728 if (chip->ops->set_txpwr_ctrl)
07ef5f2f 3729 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
e3ec7017
PKS		 3730}
3731
e3ec7017
PKS		 3732static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
3733{
3734 const struct rtw89_chip_info *chip = rtwdev->chip;
3735
3736 if (chip->ops->power_trim)
3737 chip->ops->power_trim(rtwdev);
3738}
3739
3740static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
3741 enum rtw89_phy_idx phy_idx)
3742{
3743 const struct rtw89_chip_info *chip = rtwdev->chip;
3744
3745 if (chip->ops->init_txpwr_unit)
3746 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
3747}
3748
3749static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
3750 enum rtw89_rf_path rf_path)
3751{
3752 const struct rtw89_chip_info *chip = rtwdev->chip;
3753
3754 if (!chip->ops->get_thermal)
3755 return 0x10;
3756
3757 return chip->ops->get_thermal(rtwdev, rf_path);
3758}
3759
3760static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
3761 struct rtw89_rx_phy_ppdu *phy_ppdu,
3762 struct ieee80211_rx_status *status)
3763{
3764 const struct rtw89_chip_info *chip = rtwdev->chip;
3765
3766 if (chip->ops->query_ppdu)
3767 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
3768}
3769
3770static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
3771 bool bt_en)
3772{
3773 const struct rtw89_chip_info *chip = rtwdev->chip;
3774
3775 if (chip->ops->bb_ctrl_btc_preagc)
3776 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
3777}
3778
cd89a471
PKS		 3779static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
3780{
3781 const struct rtw89_chip_info *chip = rtwdev->chip;
3782
3783 if (chip->ops->cfg_txrx_path)
3784 chip->ops->cfg_txrx_path(rtwdev);
3785}
3786
e3ec7017
PKS		 3787static inline
3788void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
3789 struct ieee80211_vif *vif)
3790{
3791 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3792 const struct rtw89_chip_info *chip = rtwdev->chip;
3793
f276e20b 3794 if (!vif->bss_conf.he_support || !vif->cfg.assoc)
e3ec7017
PKS		 3795 return;
3796
3797 if (chip->ops->set_txpwr_ul_tb_offset)
3798 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
3799}
3800
3801static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
3802 const struct rtw89_txpwr_table *tbl)
3803{
3804 tbl->load(rtwdev, tbl);
3805}
3806
3807static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
3808{
3809 return rtwdev->regd->txpwr_regd[band];
3810}
3811
3812static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
3813{
3814 const struct rtw89_chip_info *chip = rtwdev->chip;
3815
3816 if (chip->ops->ctrl_btg)
3817 chip->ops->ctrl_btg(rtwdev, btg);
3818}
3819
f59acdde
PKS		 3820static inline
3821void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
3822 struct rtw89_tx_desc_info *desc_info,
3823 void *txdesc)
3824{
3825 const struct rtw89_chip_info *chip = rtwdev->chip;
3826
3827 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
3828}
3829
a95bd62e
PKS		 3830static inline
3831void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
3832 struct rtw89_tx_desc_info *desc_info,
3833 void *txdesc)
3834{
3835 const struct rtw89_chip_info *chip = rtwdev->chip;
3836
3837 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
3838}
3839
feed6541
CYL		 3840static inline
3841void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
3842 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
3843{
3844 const struct rtw89_chip_info *chip = rtwdev->chip;
3845
3846 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
3847}
3848
3849static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
3850{
3851 const struct rtw89_chip_info *chip = rtwdev->chip;
3852
3853 chip->ops->cfg_ctrl_path(rtwdev, wl);
3854}
3855
de7ba639
PKS		 3856static inline
3857int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
3858 u32 *tx_en, enum rtw89_sch_tx_sel sel)
3859{
3860 const struct rtw89_chip_info *chip = rtwdev->chip;
3861
3862 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
3863}
3864
3865static inline
3866int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
3867{
3868 const struct rtw89_chip_info *chip = rtwdev->chip;
3869
3870 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
3871}
3872
0a6f299b
PKS		 3873static inline
3874int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
3875 struct rtw89_vif *rtwvif,
3876 struct rtw89_sta *rtwsta)
3877{
3878 const struct rtw89_chip_info *chip = rtwdev->chip;
3879
3880 if (!chip->ops->h2c_dctl_sec_cam)
3881 return 0;
3882 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
3883}
3884
e3ec7017
PKS		 3885static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
3886{
3887 __le16 fc = hdr->frame_control;
3888
3889 if (ieee80211_has_tods(fc))
3890 return hdr->addr1;
3891 else if (ieee80211_has_fromds(fc))
3892 return hdr->addr2;
3893 else
3894 return hdr->addr3;
3895}
3896
3897static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
3898{
046d2e7c
S		 3899 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
3900 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
3901 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
3902 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
3903 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
3904 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
e3ec7017
PKS		 3905 return true;
3906 return false;
3907}
3908
3909static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
3910 enum rtw89_fw_type type)
3911{
3912 struct rtw89_fw_info *fw_info = &rtwdev->fw;
3913
3914 if (type == RTW89_FW_WOWLAN)
3915 return &fw_info->wowlan;
3916 return &fw_info->normal;
3917}
3918
3919int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3920 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
3921int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
3922 struct sk_buff *skb, bool fwdl);
3923void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
3924void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
3925 struct rtw89_tx_desc_info *desc_info,
3926 void *txdesc);
f59acdde
PKS		 3927void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
3928 struct rtw89_tx_desc_info *desc_info,
3929 void *txdesc);
a95bd62e
PKS		 3930void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
3931 struct rtw89_tx_desc_info *desc_info,
3932 void *txdesc);
e3ec7017
PKS		 3933void rtw89_core_rx(struct rtw89_dev *rtwdev,
3934 struct rtw89_rx_desc_info *desc_info,
3935 struct sk_buff *skb);
3936void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
3937 struct rtw89_rx_desc_info *desc_info,
3938 u8 *data, u32 data_offset);
3939void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
3940void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
3941void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
3942void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
3943int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
3944 struct ieee80211_vif *vif,
3945 struct ieee80211_sta *sta);
3946int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
3947 struct ieee80211_vif *vif,
3948 struct ieee80211_sta *sta);
3949int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
3950 struct ieee80211_vif *vif,
3951 struct ieee80211_sta *sta);
3952int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
3953 struct ieee80211_vif *vif,
3954 struct ieee80211_sta *sta);
3955int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
3956 struct ieee80211_vif *vif,
3957 struct ieee80211_sta *sta);
3958int rtw89_core_init(struct rtw89_dev *rtwdev);
3959void rtw89_core_deinit(struct rtw89_dev *rtwdev);
3960int rtw89_core_register(struct rtw89_dev *rtwdev);
3961void rtw89_core_unregister(struct rtw89_dev *rtwdev);
967439c7 3962void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
a88b6cc4 3963void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
e3ec7017
PKS		 3964void rtw89_set_channel(struct rtw89_dev *rtwdev);
3965u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
3966void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
3967void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
3ffbb5a8
PKS		 3968int rtw89_core_acquire_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
3969int rtw89_core_release_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
e3ec7017
PKS		 3970void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
3971int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
9a3a593c 3972bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
e3ec7017
PKS		 3973int rtw89_regd_init(struct rtw89_dev *rtwdev,
3974 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
3975void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
3976void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3977 struct rtw89_traffic_stats *stats);
3978int rtw89_core_start(struct rtw89_dev *rtwdev);
3979void rtw89_core_stop(struct rtw89_dev *rtwdev);
d62816b4 3980void rtw89_core_update_beacon_work(struct work_struct *work);
89590777
PHH		 3981void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3982 const u8 *mac_addr, bool hw_scan);
3983void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
3984 struct ieee80211_vif *vif, bool hw_scan);
e3ec7017
PKS		 3985
3986#endif
Linux 6.x block layer and io_uring tree(s)