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wifi: rtw88: set pkg_type correctly for specific rtw8821c variants
[linux-block.git] / drivers / net / wireless / realtek / rtw88 / rtw8821c.c
CommitLineData
769a29ce
TEH		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include "main.h"
6#include "coex.h"
7#include "fw.h"
8#include "tx.h"
9#include "rx.h"
10#include "phy.h"
11#include "rtw8821c.h"
12#include "rtw8821c_table.h"
13#include "mac.h"
14#include "reg.h"
15#include "debug.h"
16#include "bf.h"
f8509c38 17#include "regd.h"
769a29ce 18
b0d3016f
GFF		 19static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
22
769a29ce
TEH		 23static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
24 struct rtw8821c_efuse *map)
25{
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
27}
28
aff5ffd7
SH		 29static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse,
30 struct rtw8821c_efuse *map)
31{
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
33}
34
64e9d564
MB		 35static void rtw8821cs_efuse_parsing(struct rtw_efuse *efuse,
36 struct rtw8821c_efuse *map)
37{
38 ether_addr_copy(efuse->addr, map->s.mac_addr);
39}
40
5d6651fe
GFF		 41enum rtw8821ce_rf_set {
42 SWITCH_TO_BTG,
43 SWITCH_TO_WLG,
44 SWITCH_TO_WLA,
45 SWITCH_TO_BT,
46};
47
769a29ce
TEH		 48static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
49{
97c75e1a 50 struct rtw_hal *hal = &rtwdev->hal;
769a29ce
TEH		 51 struct rtw_efuse *efuse = &rtwdev->efuse;
52 struct rtw8821c_efuse *map;
53 int i;
54
55 map = (struct rtw8821c_efuse *)log_map;
56
14705f96 57 efuse->rfe_option = map->rfe_option & 0x1f;
769a29ce
TEH		 58 efuse->rf_board_option = map->rf_board_option;
59 efuse->crystal_cap = map->xtal_k;
60 efuse->pa_type_2g = map->pa_type;
61 efuse->pa_type_5g = map->pa_type;
62 efuse->lna_type_2g = map->lna_type_2g[0];
63 efuse->lna_type_5g = map->lna_type_5g[0];
64 efuse->channel_plan = map->channel_plan;
65 efuse->country_code[0] = map->country_code[0];
66 efuse->country_code[1] = map->country_code[1];
67 efuse->bt_setting = map->rf_bt_setting;
68 efuse->regd = map->rf_board_option & 0x7;
69 efuse->thermal_meter[0] = map->thermal_meter;
70 efuse->thermal_meter_k = map->thermal_meter;
71 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
72 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
73
97c75e1a
SH		 74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0;
75
769a29ce
TEH		 76 for (i = 0; i < 4; i++)
77 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
78
5db4943a
GFF		 79 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
80 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
81
769a29ce
TEH		 82 switch (rtw_hci_type(rtwdev)) {
83 case RTW_HCI_TYPE_PCIE:
84 rtw8821ce_efuse_parsing(efuse, map);
85 break;
aff5ffd7
SH		 86 case RTW_HCI_TYPE_USB:
87 rtw8821cu_efuse_parsing(efuse, map);
88 break;
64e9d564
MB		 89 case RTW_HCI_TYPE_SDIO:
90 rtw8821cs_efuse_parsing(efuse, map);
91 break;
769a29ce
TEH		 92 default:
93 /* unsupported now */
94 return -ENOTSUPP;
95 }
96
97 return 0;
98}
99
3a431282
TEH		 100static const u32 rtw8821c_txscale_tbl[] = {
101 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
102 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
103 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
104 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
105};
106
8f8b8aa6 107static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
3a431282
TEH		 108{
109 u8 i = 0;
110 u32 swing, table_value;
111
112 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
113 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {
114 table_value = rtw8821c_txscale_tbl[i];
115 if (swing == table_value)
116 break;
117 }
118
119 return i;
120}
121
122static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
123{
124 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
125 u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
126
127 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl))
128 dm_info->default_ofdm_index = 24;
129 else
130 dm_info->default_ofdm_index = swing_idx;
131
132 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
133 dm_info->delta_power_index[RF_PATH_A] = 0;
134 dm_info->delta_power_index_last[RF_PATH_A] = 0;
135 dm_info->pwr_trk_triggered = false;
136 dm_info->pwr_trk_init_trigger = true;
137 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
138}
139
5f4eab88
TEH		 140static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev)
141{
142 rtw_bf_phy_init(rtwdev);
143 /* Grouping bitmap parameters */
144 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
145}
146
769a29ce
TEH		 147static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
148{
90f4b549 149 struct rtw_hal *hal = &rtwdev->hal;
769a29ce
TEH		 150 u8 crystal_cap, val;
151
152 /* power on BB/RF domain */
153 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
154 val |= BIT_FEN_PCIEA;
155 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
156
157 /* toggle BB reset */
158 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
159 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
160 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
161 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
162 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
163 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
164
165 rtw_write8(rtwdev, REG_RF_CTRL,
166 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
167 usleep_range(10, 11);
168 rtw_write8(rtwdev, REG_WLRF1 + 3,
169 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
170 usleep_range(10, 11);
171
172 /* pre init before header files config */
173 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
174
175 rtw_phy_load_tables(rtwdev);
176
177 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
178 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
179 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
180 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
181
182 /* post init after header files config */
183 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
90f4b549
PKS		 184 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
185 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
186 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
769a29ce
TEH		 187
188 rtw_phy_init(rtwdev);
11fcb119 189 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
3a431282
TEH		 190
191 rtw8821c_pwrtrack_init(rtwdev);
5f4eab88
TEH		 192
193 rtw8821c_phy_bf_init(rtwdev);
769a29ce
TEH		 194}
195
196static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
197{
198 u32 value32;
199 u16 pre_txcnt;
200
201 /* protocol configuration */
202 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
203 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
204 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
205 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
206 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
207 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
208 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
209 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
210 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
211 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
212 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
213 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
214 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
215 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
216 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
217 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
218
219 /* EDCA configuration */
220 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
221 rtw_write16(rtwdev, REG_TXPAUSE, 0);
222 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
223 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
224 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
225 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
226 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
227 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
228 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
229
230 /* Set beacon cotnrol - enable TSF and other related functions */
231 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
232
233 /* Set send beacon related registers */
234 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
235 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
236 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
237 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
238
239 /* WMAC configuration */
240 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
241 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
242 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
243 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
244 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
245 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
246 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
247 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
a3fd1f9a
CYL		 248 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
249 BIT_DIS_CHK_VHTSIGB_CRC);
769a29ce
TEH		 250 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
251 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
252
253 return 0;
254}
255
256static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
257{
258 u8 ldo_pwr;
259
260 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
261 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
262 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
263}
264
5d6651fe
GFF		 265static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set)
266{
267 u32 reg;
268
269 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
270 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
271
272 reg = rtw_read32(rtwdev, REG_RFECTL);
273 switch (rf_set) {
274 case SWITCH_TO_BTG:
275 reg |= B_BTG_SWITCH;
276 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH |
277 B_WLA_SWITCH);
278 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
279 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
280 break;
281 case SWITCH_TO_WLG:
282 reg |= B_WL_SWITCH | B_WLG_SWITCH;
283 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH);
284 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
285 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
286 break;
287 case SWITCH_TO_WLA:
288 reg |= B_WL_SWITCH | B_WLA_SWITCH;
289 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH);
290 break;
291 case SWITCH_TO_BT:
292 default:
293 break;
294 }
295
296 rtw_write32(rtwdev, REG_RFECTL, reg);
297}
298
58eb40c9
TEH		 299static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
300{
301 u32 rf_reg18;
302
303 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
304
305 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
306 RF18_BW_MASK);
307
308 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
309 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
310
311 if (channel >= 100 && channel <= 140)
312 rf_reg18 |= RF18_RFSI_GE;
313 else if (channel > 140)
314 rf_reg18 |= RF18_RFSI_GT;
315
316 switch (bw) {
317 case RTW_CHANNEL_WIDTH_5:
318 case RTW_CHANNEL_WIDTH_10:
319 case RTW_CHANNEL_WIDTH_20:
320 default:
321 rf_reg18 |= RF18_BW_20M;
322 break;
323 case RTW_CHANNEL_WIDTH_40:
324 rf_reg18 |= RF18_BW_40M;
325 break;
326 case RTW_CHANNEL_WIDTH_80:
327 rf_reg18 |= RF18_BW_80M;
328 break;
329 }
330
331 if (channel <= 14) {
5d6651fe
GFF		 332 if (rtwdev->efuse.rfe_option == 0)
333 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG);
b789e3fe
GFF		 334 else if (rtwdev->efuse.rfe_option == 2 ||
335 rtwdev->efuse.rfe_option == 4)
5d6651fe 336 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG);
58eb40c9
TEH		 337 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
338 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
339 } else {
5d6651fe 340 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA);
58eb40c9
TEH		 341 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
342 }
343
344 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
345
346 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
347 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
348}
349
350static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
351{
352 if (bw == RTW_CHANNEL_WIDTH_40) {
353 /* RX DFIR for BW40 */
354 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
355 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
356 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
357 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
358 } else if (bw == RTW_CHANNEL_WIDTH_80) {
359 /* RX DFIR for BW80 */
360 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
361 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
362 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
363 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
364 } else {
365 /* RX DFIR for BW20, BW10 and BW5 */
366 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
367 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
368 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
369 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
370 }
371}
372
373static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
374 u8 primary_ch_idx)
375{
90f4b549 376 struct rtw_hal *hal = &rtwdev->hal;
58eb40c9
TEH		 377 u32 val32;
378
379 if (channel <= 14) {
380 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
381 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
382 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
383 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
384
385 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
386 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
387 if (channel == 14) {
388 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
389 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
390 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
391 } else {
392 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
90f4b549 393 hal->ch_param[0]);
58eb40c9 394 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
90f4b549 395 hal->ch_param[1] & MASKLWORD);
58eb40c9 396 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
90f4b549 397 hal->ch_param[2]);
58eb40c9
TEH		 398 }
399 } else if (channel > 35) {
400 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
401 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
402 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
403 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
404
405 if (channel >= 36 && channel <= 64)
406 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
407 else if (channel >= 100 && channel <= 144)
408 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
409 else if (channel >= 149)
410 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
411
412 if (channel >= 36 && channel <= 48)
413 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
414 else if (channel >= 52 && channel <= 64)
415 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
416 else if (channel >= 100 && channel <= 116)
417 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
418 else if (channel >= 118 && channel <= 177)
419 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
420 }
421
422 switch (bw) {
423 case RTW_CHANNEL_WIDTH_20:
424 default:
425 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
426 val32 &= 0xffcffc00;
427 val32 |= 0x10010000;
428 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
429
430 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
431 break;
432 case RTW_CHANNEL_WIDTH_40:
433 if (primary_ch_idx == 1)
434 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
435 else
436 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
437
438 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
439 val32 &= 0xff3ff300;
440 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
441 RTW_CHANNEL_WIDTH_40;
442 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
443
444 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
445 break;
446 case RTW_CHANNEL_WIDTH_80:
447 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
448 val32 &= 0xfcffcf00;
449 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
450 RTW_CHANNEL_WIDTH_80;
451 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
452
453 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
454 break;
455 case RTW_CHANNEL_WIDTH_5:
456 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
457 val32 &= 0xefcefc00;
458 val32 |= 0x200240;
459 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
460
461 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
462 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
463 break;
464 case RTW_CHANNEL_WIDTH_10:
465 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
466 val32 &= 0xefcefc00;
467 val32 |= 0x300380;
468 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
469
470 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
471 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
472 break;
473 }
474}
475
476static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
477{
478 struct rtw_efuse efuse = rtwdev->efuse;
479 u8 tx_bb_swing;
480 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
481
482 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
483 efuse.tx_bb_swing_setting_5g;
484 if (tx_bb_swing > 9)
485 tx_bb_swing = 0;
486
487 return swing2setting[(tx_bb_swing / 3)];
488}
489
490static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
491 u8 bw, u8 primary_ch_idx)
492{
493 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
494 rtw8821c_get_bb_swing(rtwdev, channel));
3a431282 495 rtw8821c_pwrtrack_init(rtwdev);
58eb40c9
TEH		 496}
497
498static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
499 u8 primary_chan_idx)
500{
501 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
502 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
503 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
504 rtw8821c_set_channel_rf(rtwdev, channel, bw);
505 rtw8821c_set_channel_rxdfir(rtwdev, bw);
506}
507
b0d3016f
GFF		 508static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
509{
510 struct rtw_efuse *efuse = &rtwdev->efuse;
511 const s8 *lna_gain_table;
512 int lna_gain_table_size;
513 s8 rx_pwr_all = 0;
514 s8 lna_gain = 0;
515
516 if (efuse->rfe_option == 0) {
517 lna_gain_table = lna_gain_table_0;
518 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0);
519 } else {
520 lna_gain_table = lna_gain_table_1;
521 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1);
522 }
523
524 if (lna_idx >= lna_gain_table_size) {
a0061be4 525 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
b0d3016f
GFF		 526 return -120;
527 }
528
529 lna_gain = lna_gain_table[lna_idx];
530 rx_pwr_all = lna_gain - 2 * vga_idx;
531
532 return rx_pwr_all;
533}
534
d1904061
TEH		 535static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
536 struct rtw_rx_pkt_stat *pkt_stat)
537{
ece31c93 538 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
b0d3016f
GFF		 539 s8 rx_power;
540 u8 lna_idx = 0;
541 u8 vga_idx = 0;
d1904061 542
b0d3016f
GFF		 543 vga_idx = GET_PHY_STAT_P0_VGA(phy_status);
544 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) |
545 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status));
546 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
547
548 pkt_stat->rx_power[RF_PATH_A] = rx_power;
d1904061 549 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
ece31c93 550 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
d1904061 551 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
b0d3016f 552 pkt_stat->signal_power = rx_power;
d1904061
TEH		 553}
554
555static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
556 struct rtw_rx_pkt_stat *pkt_stat)
557{
ece31c93 558 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
d1904061
TEH		 559 u8 rxsc, bw;
560 s8 min_rx_power = -120;
561
562 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
563 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
564 else
565 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
566
567 if (rxsc >= 1 && rxsc <= 8)
568 bw = RTW_CHANNEL_WIDTH_20;
569 else if (rxsc >= 9 && rxsc <= 12)
570 bw = RTW_CHANNEL_WIDTH_40;
571 else if (rxsc >= 13)
572 bw = RTW_CHANNEL_WIDTH_80;
573 else
574 bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
575
576 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
577 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
ece31c93 578 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
d1904061
TEH		 579 pkt_stat->bw = bw;
580 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
581 min_rx_power);
582}
583
584static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
585 struct rtw_rx_pkt_stat *pkt_stat)
586{
587 u8 page;
588
589 page = *phy_status & 0xf;
590
591 switch (page) {
592 case 0:
593 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
594 break;
595 case 1:
596 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
597 break;
598 default:
599 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
600 return;
601 }
602}
603
604static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
605 struct rtw_rx_pkt_stat *pkt_stat,
606 struct ieee80211_rx_status *rx_status)
607{
608 struct ieee80211_hdr *hdr;
609 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
610 u8 *phy_status = NULL;
611
612 memset(pkt_stat, 0, sizeof(*pkt_stat));
613
614 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
615 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
616 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
559f6cb3
GFF		 617 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
618 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
d1904061
TEH		 619 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
620 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
621 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
622 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
623 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
624 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
625 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
626 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
627
628 /* drv_info_sz is in unit of 8-bytes */
629 pkt_stat->drv_info_sz *= 8;
630
631 /* c2h cmd pkt's rx/phy status is not interested */
632 if (pkt_stat->is_c2h)
633 return;
634
635 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
636 pkt_stat->drv_info_sz);
637 if (pkt_stat->phy_status) {
638 phy_status = rx_desc + desc_sz + pkt_stat->shift;
639 query_phy_status(rtwdev, phy_status, pkt_stat);
640 }
641
642 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
643}
644
ad5f411b
TEH		 645static void
646rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
647{
648 struct rtw_hal *hal = &rtwdev->hal;
649 static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
650 static u32 phy_pwr_idx;
651 u8 rate, rate_idx, pwr_index, shift;
652 int j;
653
654 for (j = 0; j < rtw_rate_size[rs]; j++) {
655 rate = rtw_rate_section[rs][j];
656 pwr_index = hal->tx_pwr_tbl[path][rate];
657 shift = rate & 0x3;
658 phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
659 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {
660 rate_idx = rate & 0xfc;
661 rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
662 phy_pwr_idx);
663 phy_pwr_idx = 0;
664 }
665 }
666}
667
668static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
669{
670 struct rtw_hal *hal = &rtwdev->hal;
671 int rs, path;
672
673 for (path = 0; path < hal->rf_path_num; path++) {
674 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
675 if (rs == RTW_RATE_SECTION_HT_2S ||
676 rs == RTW_RATE_SECTION_VHT_2S)
677 continue;
678 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs);
679 }
680 }
681}
682
96036123
TEH		 683static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
684{
685 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
686 u32 cck_enable;
687 u32 cck_fa_cnt;
688 u32 ofdm_fa_cnt;
689 u32 crc32_cnt;
690 u32 cca32_cnt;
691
692 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
693 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
694 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
695
696 dm_info->cck_fa_cnt = cck_fa_cnt;
697 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
698 if (cck_enable)
699 dm_info->total_fa_cnt += cck_fa_cnt;
700 dm_info->total_fa_cnt = ofdm_fa_cnt;
701
702 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
703 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
704 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
705
706 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
707 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
708 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
709
710 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
711 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
712 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
713
714 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
715 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
716 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
717
718 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
719 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
720 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
721 if (cck_enable) {
722 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
723 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
724 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
725 }
726
727 rtw_write32_set(rtwdev, REG_FAS, BIT(17));
728 rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
729 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
730 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
731 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
732 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
733}
734
1a94d93e
TEH		 735static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
736{
737 static int do_iqk_cnt;
738 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
739 u32 rf_reg, iqk_fail_mask;
740 int counter;
741 bool reload;
742
743 if (rtw_is_assoc(rtwdev))
744 para.segment_iqk = 1;
745
746 rtw_fw_do_iqk(rtwdev, &para);
747
748 for (counter = 0; counter < 300; counter++) {
749 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
750 if (rf_reg == 0xabcde)
751 break;
752 msleep(20);
753 }
754 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
755
756 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
757 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
758 rtw_dbg(rtwdev, RTW_DBG_PHY,
759 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
760 counter, reload, ++do_iqk_cnt, iqk_fail_mask);
761}
762
763static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
764{
765 rtw8821c_do_iqk(rtwdev);
766}
767
7b080e08
PCC		 768/* for coex */
769static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev)
770{
771 /* enable TBTT nterrupt */
772 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
773
774 /* BT report packet sample rate */
3f3fef5f 775 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
7b080e08
PCC		 776
777 /* enable BT counter statistics */
778 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);
779
780 /* enable PTA (3-wire function form BT side) */
781 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
782 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
783
784 /* enable PTA (tx/rx signal form WiFi side) */
785 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
786 /* wl tx signal to PTA not case EDCCA */
787 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
788 /* GNT_BT=1 while select both */
789 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
790
791 /* beacon queue always hi-pri */
792 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
793 BCN_PRI_EN);
794}
795
796static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
797 u8 pos_type)
798{
799 struct rtw_coex *coex = &rtwdev->coex;
800 struct rtw_coex_dm *coex_dm = &coex->dm;
801 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
802 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type;
803 bool polarity_inverse;
804 u8 regval = 0;
805
806 if (switch_status == coex_dm->cur_switch_status)
807 return;
808
b789e3fe
GFF		 809 if (coex_rfe->wlg_at_btg) {
810 ctrl_type = COEX_SWITCH_CTRL_BY_BBSW;
811
812 if (coex_rfe->ant_switch_polarity)
813 pos_type = COEX_SWITCH_TO_WLA;
814 else
815 pos_type = COEX_SWITCH_TO_WLG_BT;
816 }
817
7b080e08
PCC		 818 coex_dm->cur_switch_status = switch_status;
819
820 if (coex_rfe->ant_switch_diversity &&
821 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
822 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
823
824 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
825
826 switch (ctrl_type) {
827 default:
828 case COEX_SWITCH_CTRL_BY_BBSW:
829 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
830 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
831 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
832 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
833 DPDT_CTRL_PIN);
834
835 if (pos_type == COEX_SWITCH_TO_WLG_BT) {
836 if (coex_rfe->rfe_module_type != 0x4 &&
837 coex_rfe->rfe_module_type != 0x2)
838 regval = 0x3;
839 else
840 regval = (!polarity_inverse ? 0x2 : 0x1);
841 } else if (pos_type == COEX_SWITCH_TO_WLG) {
842 regval = (!polarity_inverse ? 0x2 : 0x1);
843 } else {
844 regval = (!polarity_inverse ? 0x1 : 0x2);
845 }
846
adba838a
GFF		 847 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
848 regval);
7b080e08
PCC		 849 break;
850 case COEX_SWITCH_CTRL_BY_PTA:
851 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
852 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
853 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
854 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
855 PTA_CTRL_PIN);
856
857 regval = (!polarity_inverse ? 0x2 : 0x1);
adba838a
GFF		 858 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
859 regval);
7b080e08
PCC		 860 break;
861 case COEX_SWITCH_CTRL_BY_ANTDIV:
862 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
863 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
864 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
865 ANTDIC_CTRL_PIN);
866 break;
867 case COEX_SWITCH_CTRL_BY_MAC:
868 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
869
870 regval = (!polarity_inverse ? 0x0 : 0x1);
871 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
872 regval);
873 break;
874 case COEX_SWITCH_CTRL_BY_FW:
875 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
876 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
877 break;
878 case COEX_SWITCH_CTRL_BY_BT:
879 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
880 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
881 break;
882 }
883
884 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) {
adba838a
GFF		 885 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
886 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
7b080e08 887 } else {
adba838a
GFF		 888 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
889 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
7b080e08
PCC		 890 }
891}
892
893static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
894{}
895
896static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
897{
898 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
899 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
900 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
901 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
902 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
903 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
904}
905
906static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
907{
908 struct rtw_coex *coex = &rtwdev->coex;
909 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
910 struct rtw_efuse *efuse = &rtwdev->efuse;
911
912 coex_rfe->rfe_module_type = efuse->rfe_option;
913 coex_rfe->ant_switch_polarity = 0;
914 coex_rfe->ant_switch_exist = true;
915 coex_rfe->wlg_at_btg = false;
916
917 switch (coex_rfe->rfe_module_type) {
918 case 0:
919 case 8:
920 case 1:
921 case 9: /* 1-Ant, Main, WLG */
922 default: /* 2-Ant, DPDT, WLG */
923 break;
924 case 2:
925 case 10: /* 1-Ant, Main, BTG */
926 case 7:
927 case 15: /* 2-Ant, DPDT, BTG */
928 coex_rfe->wlg_at_btg = true;
929 break;
930 case 3:
931 case 11: /* 1-Ant, Aux, WLG */
932 coex_rfe->ant_switch_polarity = 1;
933 break;
934 case 4:
935 case 12: /* 1-Ant, Aux, BTG */
936 coex_rfe->wlg_at_btg = true;
937 coex_rfe->ant_switch_polarity = 1;
938 break;
939 case 5:
940 case 13: /* 2-Ant, no switch, WLG */
941 case 6:
942 case 14: /* 2-Ant, no antenna switch, WLG */
943 coex_rfe->ant_switch_exist = false;
944 break;
945 }
946}
947
948static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
949{
950 struct rtw_coex *coex = &rtwdev->coex;
951 struct rtw_coex_dm *coex_dm = &coex->dm;
952 struct rtw_efuse *efuse = &rtwdev->efuse;
953 bool share_ant = efuse->share_ant;
954
955 if (share_ant)
956 return;
957
958 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
959 return;
960
961 coex_dm->cur_wl_pwr_lvl = wl_pwr;
962}
963
964static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
965{}
966
3a431282
TEH		 967static void
968rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
969 s8 pwr_idx_offset_lower,
970 s8 *txagc_idx, u8 *swing_idx)
971{
972 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
973 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];
974 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
975 u8 swing_lower_bound = 0;
976 u8 max_pwr_idx_offset = 0xf;
977 s8 agc_index = 0;
978 u8 swing_index = dm_info->default_ofdm_index;
979
980 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset);
981 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);
982
983 if (delta_pwr_idx >= 0) {
984 if (delta_pwr_idx <= pwr_idx_offset) {
985 agc_index = delta_pwr_idx;
986 swing_index = dm_info->default_ofdm_index;
987 } else if (delta_pwr_idx > pwr_idx_offset) {
988 agc_index = pwr_idx_offset;
989 swing_index = dm_info->default_ofdm_index +
990 delta_pwr_idx - pwr_idx_offset;
991 swing_index = min_t(u8, swing_index, swing_upper_bound);
992 }
993 } else if (delta_pwr_idx < 0) {
994 if (delta_pwr_idx >= pwr_idx_offset_lower) {
995 agc_index = delta_pwr_idx;
996 swing_index = dm_info->default_ofdm_index;
997 } else if (delta_pwr_idx < pwr_idx_offset_lower) {
998 if (dm_info->default_ofdm_index >
999 (pwr_idx_offset_lower - delta_pwr_idx))
1000 swing_index = dm_info->default_ofdm_index +
1001 delta_pwr_idx - pwr_idx_offset_lower;
1002 else
1003 swing_index = swing_lower_bound;
1004
1005 agc_index = pwr_idx_offset_lower;
1006 }
1007 }
1008
1009 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) {
1010 rtw_warn(rtwdev, "swing index overflow\n");
1011 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;
1012 }
1013
1014 *txagc_idx = agc_index;
1015 *swing_idx = swing_index;
1016}
1017
1018static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
1019 s8 pwr_idx_offset_lower)
1020{
1021 s8 txagc_idx;
1022 u8 swing_idx;
1023
1024 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower,
1025 &txagc_idx, &swing_idx);
1026 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);
1027 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
1028 rtw8821c_txscale_tbl[swing_idx]);
1029}
1030
1031static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev)
1032{
1033 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1034 u8 pwr_idx_offset, tx_pwr_idx;
1035 s8 pwr_idx_offset_lower;
1036 u8 channel = rtwdev->hal.current_channel;
1037 u8 band_width = rtwdev->hal.current_band_width;
f8509c38 1038 u8 regd = rtw_regd_get(rtwdev);
3a431282
TEH		 1039 u8 tx_rate = dm_info->tx_rate;
1040 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1041
1042 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate,
1043 band_width, channel, regd);
1044
1045 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1046
1047 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1048 pwr_idx_offset_lower = 0 - tx_pwr_idx;
1049
1050 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower);
1051}
1052
1053static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev)
1054{
1055 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1056 struct rtw_swing_table swing_table;
1057 u8 thermal_value, delta;
1058
1059 rtw_phy_config_swing_table(rtwdev, &swing_table);
1060
1061 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1062 return;
1063
1064 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1065
1066 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1067
1068 if (dm_info->pwr_trk_init_trigger)
1069 dm_info->pwr_trk_init_trigger = false;
1070 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1071 RF_PATH_A))
1072 goto iqk;
1073
1074 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1075
1076 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1077
1078 dm_info->delta_power_index[RF_PATH_A] =
1079 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A,
1080 RF_PATH_A, delta);
1081 if (dm_info->delta_power_index[RF_PATH_A] ==
1082 dm_info->delta_power_index_last[RF_PATH_A])
1083 goto iqk;
1084 else
1085 dm_info->delta_power_index_last[RF_PATH_A] =
1086 dm_info->delta_power_index[RF_PATH_A];
1087 rtw8821c_pwrtrack_set(rtwdev);
1088
1089iqk:
1090 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1091 rtw8821c_do_iqk(rtwdev);
1092}
1093
1094static void rtw8821c_pwr_track(struct rtw_dev *rtwdev)
1095{
1096 struct rtw_efuse *efuse = &rtwdev->efuse;
1097 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1098
1099 if (efuse->power_track_type != 0)
1100 return;
1101
1102 if (!dm_info->pwr_trk_triggered) {
1103 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1104 GENMASK(17, 16), 0x03);
1105 dm_info->pwr_trk_triggered = true;
1106 return;
1107 }
1108
1109 rtw8821c_phy_pwrtrack(rtwdev);
1110 dm_info->pwr_trk_triggered = false;
1111}
1112
5f4eab88
TEH		 1113static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev,
1114 struct rtw_vif *vif,
1115 struct rtw_bfee *bfee, bool enable)
1116{
1117 if (enable)
1118 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1119 else
1120 rtw_bf_remove_bfee_su(rtwdev, bfee);
1121}
1122
1123static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1124 struct rtw_vif *vif,
1125 struct rtw_bfee *bfee, bool enable)
1126{
1127 if (enable)
1128 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1129 else
1130 rtw_bf_remove_bfee_mu(rtwdev, bfee);
1131}
1132
1133static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1134 struct rtw_bfee *bfee, bool enable)
1135{
1136 if (bfee->role == RTW_BFEE_SU)
1137 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1138 else if (bfee->role == RTW_BFEE_MU)
1139 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1140 else
1141 rtw_warn(rtwdev, "wrong bfee role\n");
1142}
1143
11fcb119
TEH		 1144static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1145{
1146 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1147 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
760bb2ab 1148 u8 cck_n_rx;
11fcb119 1149
760bb2ab
PKS		 1150 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1151 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1152
11fcb119
TEH		 1153 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1154 return;
1155
760bb2ab
PKS		 1156 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1157 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1158 rtw_dbg(rtwdev, RTW_DBG_PHY,
1159 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1160 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1161 dm_info->cck_pd_default + new_lvl * 2,
1162 pd[new_lvl], dm_info->cck_fa_avg);
1163
11fcb119
TEH		 1164 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1165
11fcb119
TEH		 1166 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1167 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1168 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1169 dm_info->cck_pd_default + new_lvl * 2);
1170}
1171
aff5ffd7
SH		 1172static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev,
1173 struct rtw_tx_pkt_info *pkt_info,
1174 u8 *txdesc)
1175{
1176 fill_txdesc_checksum_common(txdesc, 16);
1177}
1178
769a29ce
TEH		 1179static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
1180 {0x0086,
1181 RTW_PWR_CUT_ALL_MSK,
1182 RTW_PWR_INTF_SDIO_MSK,
1183 RTW_PWR_ADDR_SDIO,
1184 RTW_PWR_CMD_WRITE, BIT(0), 0},
1185 {0x0086,
1186 RTW_PWR_CUT_ALL_MSK,
1187 RTW_PWR_INTF_SDIO_MSK,
1188 RTW_PWR_ADDR_SDIO,
1189 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1190 {0x004A,
1191 RTW_PWR_CUT_ALL_MSK,
1192 RTW_PWR_INTF_USB_MSK,
1193 RTW_PWR_ADDR_MAC,
1194 RTW_PWR_CMD_WRITE, BIT(0), 0},
1195 {0x0005,
1196 RTW_PWR_CUT_ALL_MSK,
1197 RTW_PWR_INTF_ALL_MSK,
1198 RTW_PWR_ADDR_MAC,
1199 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1200 {0x0300,
1201 RTW_PWR_CUT_ALL_MSK,
1202 RTW_PWR_INTF_PCI_MSK,
1203 RTW_PWR_ADDR_MAC,
1204 RTW_PWR_CMD_WRITE, 0xFF, 0},
1205 {0x0301,
1206 RTW_PWR_CUT_ALL_MSK,
1207 RTW_PWR_INTF_PCI_MSK,
1208 RTW_PWR_ADDR_MAC,
1209 RTW_PWR_CMD_WRITE, 0xFF, 0},
1210 {0xFFFF,
1211 RTW_PWR_CUT_ALL_MSK,
1212 RTW_PWR_INTF_ALL_MSK,
1213 0,
1214 RTW_PWR_CMD_END, 0, 0},
1215};
1216
1217static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = {
1218 {0x0020,
1219 RTW_PWR_CUT_ALL_MSK,
1220 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1221 RTW_PWR_ADDR_MAC,
1222 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1223 {0x0001,
1224 RTW_PWR_CUT_ALL_MSK,
1225 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1226 RTW_PWR_ADDR_MAC,
1227 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1228 {0x0000,
1229 RTW_PWR_CUT_ALL_MSK,
1230 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1231 RTW_PWR_ADDR_MAC,
1232 RTW_PWR_CMD_WRITE, BIT(5), 0},
1233 {0x0005,
1234 RTW_PWR_CUT_ALL_MSK,
1235 RTW_PWR_INTF_ALL_MSK,
1236 RTW_PWR_ADDR_MAC,
1237 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1238 {0x0075,
1239 RTW_PWR_CUT_ALL_MSK,
1240 RTW_PWR_INTF_PCI_MSK,
1241 RTW_PWR_ADDR_MAC,
1242 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1243 {0x0006,
1244 RTW_PWR_CUT_ALL_MSK,
1245 RTW_PWR_INTF_ALL_MSK,
1246 RTW_PWR_ADDR_MAC,
1247 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1248 {0x0075,
1249 RTW_PWR_CUT_ALL_MSK,
1250 RTW_PWR_INTF_PCI_MSK,
1251 RTW_PWR_ADDR_MAC,
1252 RTW_PWR_CMD_WRITE, BIT(0), 0},
1253 {0x0006,
1254 RTW_PWR_CUT_ALL_MSK,
1255 RTW_PWR_INTF_ALL_MSK,
1256 RTW_PWR_ADDR_MAC,
1257 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1258 {0x0005,
1259 RTW_PWR_CUT_ALL_MSK,
1260 RTW_PWR_INTF_ALL_MSK,
1261 RTW_PWR_ADDR_MAC,
1262 RTW_PWR_CMD_WRITE, BIT(7), 0},
1263 {0x0005,
1264 RTW_PWR_CUT_ALL_MSK,
1265 RTW_PWR_INTF_ALL_MSK,
1266 RTW_PWR_ADDR_MAC,
1267 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1268 {0x10C3,
1269 RTW_PWR_CUT_ALL_MSK,
1270 RTW_PWR_INTF_USB_MSK,
1271 RTW_PWR_ADDR_MAC,
1272 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1273 {0x0005,
1274 RTW_PWR_CUT_ALL_MSK,
1275 RTW_PWR_INTF_ALL_MSK,
1276 RTW_PWR_ADDR_MAC,
1277 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1278 {0x0005,
1279 RTW_PWR_CUT_ALL_MSK,
1280 RTW_PWR_INTF_ALL_MSK,
1281 RTW_PWR_ADDR_MAC,
1282 RTW_PWR_CMD_POLLING, BIT(0), 0},
1283 {0x0020,
1284 RTW_PWR_CUT_ALL_MSK,
1285 RTW_PWR_INTF_ALL_MSK,
1286 RTW_PWR_ADDR_MAC,
1287 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1288 {0x0074,
1289 RTW_PWR_CUT_ALL_MSK,
1290 RTW_PWR_INTF_PCI_MSK,
1291 RTW_PWR_ADDR_MAC,
1292 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1293 {0x0022,
1294 RTW_PWR_CUT_ALL_MSK,
1295 RTW_PWR_INTF_PCI_MSK,
1296 RTW_PWR_ADDR_MAC,
1297 RTW_PWR_CMD_WRITE, BIT(1), 0},
1298 {0x0062,
1299 RTW_PWR_CUT_ALL_MSK,
1300 RTW_PWR_INTF_PCI_MSK,
1301 RTW_PWR_ADDR_MAC,
1302 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1303 (BIT(7) | BIT(6) | BIT(5))},
1304 {0x0061,
1305 RTW_PWR_CUT_ALL_MSK,
1306 RTW_PWR_INTF_PCI_MSK,
1307 RTW_PWR_ADDR_MAC,
1308 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1309 {0x007C,
1310 RTW_PWR_CUT_ALL_MSK,
1311 RTW_PWR_INTF_ALL_MSK,
1312 RTW_PWR_ADDR_MAC,
1313 RTW_PWR_CMD_WRITE, BIT(1), 0},
1314 {0xFFFF,
1315 RTW_PWR_CUT_ALL_MSK,
1316 RTW_PWR_INTF_ALL_MSK,
1317 0,
1318 RTW_PWR_CMD_END, 0, 0},
1319};
1320
1321static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = {
1322 {0x0093,
1323 RTW_PWR_CUT_ALL_MSK,
1324 RTW_PWR_INTF_ALL_MSK,
1325 RTW_PWR_ADDR_MAC,
1326 RTW_PWR_CMD_WRITE, BIT(3), 0},
1327 {0x001F,
1328 RTW_PWR_CUT_ALL_MSK,
1329 RTW_PWR_INTF_ALL_MSK,
1330 RTW_PWR_ADDR_MAC,
1331 RTW_PWR_CMD_WRITE, 0xFF, 0},
1332 {0x0049,
1333 RTW_PWR_CUT_ALL_MSK,
1334 RTW_PWR_INTF_ALL_MSK,
1335 RTW_PWR_ADDR_MAC,
1336 RTW_PWR_CMD_WRITE, BIT(1), 0},
1337 {0x0006,
1338 RTW_PWR_CUT_ALL_MSK,
1339 RTW_PWR_INTF_ALL_MSK,
1340 RTW_PWR_ADDR_MAC,
1341 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1342 {0x0002,
1343 RTW_PWR_CUT_ALL_MSK,
1344 RTW_PWR_INTF_ALL_MSK,
1345 RTW_PWR_ADDR_MAC,
1346 RTW_PWR_CMD_WRITE, BIT(1), 0},
1347 {0x10C3,
1348 RTW_PWR_CUT_ALL_MSK,
1349 RTW_PWR_INTF_USB_MSK,
1350 RTW_PWR_ADDR_MAC,
1351 RTW_PWR_CMD_WRITE, BIT(0), 0},
1352 {0x0005,
1353 RTW_PWR_CUT_ALL_MSK,
1354 RTW_PWR_INTF_ALL_MSK,
1355 RTW_PWR_ADDR_MAC,
1356 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1357 {0x0005,
1358 RTW_PWR_CUT_ALL_MSK,
1359 RTW_PWR_INTF_ALL_MSK,
1360 RTW_PWR_ADDR_MAC,
1361 RTW_PWR_CMD_POLLING, BIT(1), 0},
1362 {0x0020,
1363 RTW_PWR_CUT_ALL_MSK,
1364 RTW_PWR_INTF_ALL_MSK,
1365 RTW_PWR_ADDR_MAC,
1366 RTW_PWR_CMD_WRITE, BIT(3), 0},
1367 {0x0000,
1368 RTW_PWR_CUT_ALL_MSK,
1369 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1370 RTW_PWR_ADDR_MAC,
1371 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1372 {0xFFFF,
1373 RTW_PWR_CUT_ALL_MSK,
1374 RTW_PWR_INTF_ALL_MSK,
1375 0,
1376 RTW_PWR_CMD_END, 0, 0},
1377};
1378
1379static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = {
1380 {0x0007,
1381 RTW_PWR_CUT_ALL_MSK,
1382 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1383 RTW_PWR_ADDR_MAC,
1384 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1385 {0x0067,
1386 RTW_PWR_CUT_ALL_MSK,
1387 RTW_PWR_INTF_ALL_MSK,
1388 RTW_PWR_ADDR_MAC,
1389 RTW_PWR_CMD_WRITE, BIT(5), 0},
1390 {0x0005,
1391 RTW_PWR_CUT_ALL_MSK,
1392 RTW_PWR_INTF_PCI_MSK,
1393 RTW_PWR_ADDR_MAC,
1394 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1395 {0x004A,
1396 RTW_PWR_CUT_ALL_MSK,
1397 RTW_PWR_INTF_USB_MSK,
1398 RTW_PWR_ADDR_MAC,
1399 RTW_PWR_CMD_WRITE, BIT(0), 0},
1400 {0x0067,
1401 RTW_PWR_CUT_ALL_MSK,
1402 RTW_PWR_INTF_SDIO_MSK,
1403 RTW_PWR_ADDR_MAC,
1404 RTW_PWR_CMD_WRITE, BIT(5), 0},
1405 {0x0067,
1406 RTW_PWR_CUT_ALL_MSK,
1407 RTW_PWR_INTF_SDIO_MSK,
1408 RTW_PWR_ADDR_MAC,
1409 RTW_PWR_CMD_WRITE, BIT(4), 0},
1410 {0x004F,
1411 RTW_PWR_CUT_ALL_MSK,
1412 RTW_PWR_INTF_SDIO_MSK,
1413 RTW_PWR_ADDR_MAC,
1414 RTW_PWR_CMD_WRITE, BIT(0), 0},
1415 {0x0067,
1416 RTW_PWR_CUT_ALL_MSK,
1417 RTW_PWR_INTF_SDIO_MSK,
1418 RTW_PWR_ADDR_MAC,
1419 RTW_PWR_CMD_WRITE, BIT(1), 0},
1420 {0x0046,
1421 RTW_PWR_CUT_ALL_MSK,
1422 RTW_PWR_INTF_SDIO_MSK,
1423 RTW_PWR_ADDR_MAC,
1424 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1425 {0x0067,
1426 RTW_PWR_CUT_ALL_MSK,
1427 RTW_PWR_INTF_SDIO_MSK,
1428 RTW_PWR_ADDR_MAC,
1429 RTW_PWR_CMD_WRITE, BIT(2), 0},
1430 {0x0046,
1431 RTW_PWR_CUT_ALL_MSK,
1432 RTW_PWR_INTF_SDIO_MSK,
1433 RTW_PWR_ADDR_MAC,
1434 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1435 {0x0062,
1436 RTW_PWR_CUT_ALL_MSK,
1437 RTW_PWR_INTF_SDIO_MSK,
1438 RTW_PWR_ADDR_MAC,
1439 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1440 {0x0081,
1441 RTW_PWR_CUT_ALL_MSK,
1442 RTW_PWR_INTF_ALL_MSK,
1443 RTW_PWR_ADDR_MAC,
1444 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1445 {0x0005,
1446 RTW_PWR_CUT_ALL_MSK,
1447 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1448 RTW_PWR_ADDR_MAC,
1449 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1450 {0x0086,
1451 RTW_PWR_CUT_ALL_MSK,
1452 RTW_PWR_INTF_SDIO_MSK,
1453 RTW_PWR_ADDR_SDIO,
1454 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1455 {0x0086,
1456 RTW_PWR_CUT_ALL_MSK,
1457 RTW_PWR_INTF_SDIO_MSK,
1458 RTW_PWR_ADDR_SDIO,
1459 RTW_PWR_CMD_POLLING, BIT(1), 0},
1460 {0x0090,
1461 RTW_PWR_CUT_ALL_MSK,
1462 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1463 RTW_PWR_ADDR_MAC,
1464 RTW_PWR_CMD_WRITE, BIT(1), 0},
1465 {0x0044,
1466 RTW_PWR_CUT_ALL_MSK,
1467 RTW_PWR_INTF_SDIO_MSK,
1468 RTW_PWR_ADDR_SDIO,
1469 RTW_PWR_CMD_WRITE, 0xFF, 0},
1470 {0x0040,
1471 RTW_PWR_CUT_ALL_MSK,
1472 RTW_PWR_INTF_SDIO_MSK,
1473 RTW_PWR_ADDR_SDIO,
1474 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1475 {0x0041,
1476 RTW_PWR_CUT_ALL_MSK,
1477 RTW_PWR_INTF_SDIO_MSK,
1478 RTW_PWR_ADDR_SDIO,
1479 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1480 {0x0042,
1481 RTW_PWR_CUT_ALL_MSK,
1482 RTW_PWR_INTF_SDIO_MSK,
1483 RTW_PWR_ADDR_SDIO,
1484 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1485 {0xFFFF,
1486 RTW_PWR_CUT_ALL_MSK,
1487 RTW_PWR_INTF_ALL_MSK,
1488 0,
1489 RTW_PWR_CMD_END, 0, 0},
1490};
1491
1492static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = {
1493 trans_carddis_to_cardemu_8821c,
1494 trans_cardemu_to_act_8821c,
1495 NULL
1496};
1497
1498static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = {
1499 trans_act_to_cardemu_8821c,
1500 trans_cardemu_to_carddis_8821c,
1501 NULL
1502};
1503
1504static const struct rtw_intf_phy_para usb2_param_8821c[] = {
1505 {0xFFFF, 0x00,
1506 RTW_IP_SEL_PHY,
1507 RTW_INTF_PHY_CUT_ALL,
1508 RTW_INTF_PHY_PLATFORM_ALL},
1509};
1510
1511static const struct rtw_intf_phy_para usb3_param_8821c[] = {
1512 {0xFFFF, 0x0000,
1513 RTW_IP_SEL_PHY,
1514 RTW_INTF_PHY_CUT_ALL,
1515 RTW_INTF_PHY_PLATFORM_ALL},
1516};
1517
1518static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = {
1519 {0x0009, 0x6380,
1520 RTW_IP_SEL_PHY,
1521 RTW_INTF_PHY_CUT_ALL,
1522 RTW_INTF_PHY_PLATFORM_ALL},
1523 {0xFFFF, 0x0000,
1524 RTW_IP_SEL_PHY,
1525 RTW_INTF_PHY_CUT_ALL,
1526 RTW_INTF_PHY_PLATFORM_ALL},
1527};
1528
1529static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = {
1530 {0xFFFF, 0x0000,
1531 RTW_IP_SEL_PHY,
1532 RTW_INTF_PHY_CUT_ALL,
1533 RTW_INTF_PHY_PLATFORM_ALL},
1534};
1535
1536static const struct rtw_intf_phy_para_table phy_para_table_8821c = {
1537 .usb2_para = usb2_param_8821c,
1538 .usb3_para = usb3_param_8821c,
1539 .gen1_para = pcie_gen1_param_8821c,
1540 .gen2_para = pcie_gen2_param_8821c,
1541 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c),
1542 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c),
1543 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c),
1544 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c),
1545};
1546
1547static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
1548 [0] = RTW_DEF_RFE(8821c, 0, 0),
5d6651fe 1549 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
b789e3fe 1550 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
e109e361 1551 [6] = RTW_DEF_RFE(8821c, 0, 0),
769a29ce
TEH		 1552};
1553
6cf2086f
TEH		 1554static struct rtw_hw_reg rtw8821c_dig[] = {
1555 [0] = { .addr = 0xc50, .mask = 0x7f },
1556};
1557
769a29ce
TEH		 1558static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1559 .ctrl = LTECOEX_ACCESS_CTRL,
1560 .wdata = LTECOEX_WRITE_DATA,
1561 .rdata = LTECOEX_READ_DATA,
1562};
1563
1564static struct rtw_page_table page_table_8821c[] = {
1565 /* not sure what [0] stands for */
1566 {16, 16, 16, 14, 1},
1567 {16, 16, 16, 14, 1},
1568 {16, 16, 0, 0, 1},
1569 {16, 16, 16, 0, 1},
1570 {16, 16, 16, 14, 1},
1571};
1572
1573static struct rtw_rqpn rqpn_table_8821c[] = {
1574 /* not sure what [0] stands for */
1575 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1576 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1577 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1578 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1579 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1580 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1581 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1582 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1583 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1584 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1585 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1586 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1587 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1588 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1589 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1590};
1591
1592static struct rtw_prioq_addrs prioq_addrs_8821c = {
1593 .prio[RTW_DMA_MAPPING_EXTRA] = {
1594 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
1595 },
1596 .prio[RTW_DMA_MAPPING_LOW] = {
1597 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
1598 },
1599 .prio[RTW_DMA_MAPPING_NORMAL] = {
1600 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
1601 },
1602 .prio[RTW_DMA_MAPPING_HIGH] = {
1603 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
1604 },
1605 .wsize = true,
1606};
1607
1608static struct rtw_chip_ops rtw8821c_ops = {
1609 .phy_set_param = rtw8821c_phy_set_param,
1610 .read_efuse = rtw8821c_read_efuse,
d1904061 1611 .query_rx_desc = rtw8821c_query_rx_desc,
58eb40c9 1612 .set_channel = rtw8821c_set_channel,
769a29ce
TEH		 1613 .mac_init = rtw8821c_mac_init,
1614 .read_rf = rtw_phy_read_rf,
1615 .write_rf = rtw_phy_write_rf_reg_sipi,
1616 .set_antenna = NULL,
ad5f411b 1617 .set_tx_power_index = rtw8821c_set_tx_power_index,
769a29ce 1618 .cfg_ldo25 = rtw8821c_cfg_ldo25,
96036123 1619 .false_alarm_statistics = rtw8821c_false_alarm_statistics,
1a94d93e 1620 .phy_calibration = rtw8821c_phy_calibration,
11fcb119 1621 .cck_pd_set = rtw8821c_phy_cck_pd_set,
3a431282 1622 .pwr_track = rtw8821c_pwr_track,
5f4eab88
TEH		 1623 .config_bfee = rtw8821c_bf_config_bfee,
1624 .set_gid_table = rtw_bf_set_gid_table,
1625 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
aff5ffd7 1626 .fill_txdesc_checksum = rtw8821c_fill_txdesc_checksum,
7b080e08
PCC		 1627
1628 .coex_set_init = rtw8821c_coex_cfg_init,
1629 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch,
1630 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix,
1631 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug,
1632 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type,
1633 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power,
1634 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain,
1635};
1636
1637/* rssi in percentage % (dbm = % - 100) */
1638static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40};
1639static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101};
1640
1641/* Shared-Antenna Coex Table */
1642static const struct coex_table_para table_sant_8821c[] = {
1643 {0x55555555, 0x55555555}, /* case-0 */
1644 {0x55555555, 0x55555555},
1645 {0x66555555, 0x66555555},
1646 {0xaaaaaaaa, 0xaaaaaaaa},
1647 {0x5a5a5a5a, 0x5a5a5a5a},
1648 {0xfafafafa, 0xfafafafa}, /* case-5 */
1649 {0x6a5a5555, 0xaaaaaaaa},
1650 {0x6a5a56aa, 0x6a5a56aa},
1651 {0x6a5a5a5a, 0x6a5a5a5a},
1652 {0x66555555, 0x5a5a5a5a},
1653 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1654 {0x66555555, 0xaaaaaaaa},
1655 {0x66555555, 0x6a5a5aaa},
1656 {0x66555555, 0x6aaa6aaa},
1657 {0x66555555, 0x6a5a5aaa},
1658 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1659 {0xffff55ff, 0xfafafafa},
1660 {0xffff55ff, 0x6afa5afa},
1661 {0xaaffffaa, 0xfafafafa},
1662 {0xaa5555aa, 0x5a5a5a5a},
1663 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1664 {0xaa5555aa, 0xaaaaaaaa},
1665 {0xffffffff, 0x55555555},
1666 {0xffffffff, 0x5a5a5a5a},
1667 {0xffffffff, 0x5a5a5a5a},
1668 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1669 {0x55555555, 0x5a5a5a5a},
1670 {0x55555555, 0xaaaaaaaa},
1671 {0x66555555, 0x6a5a6a5a},
1672 {0x66556655, 0x66556655},
1673 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1674 {0xffffffff, 0x5aaa5aaa},
1675 {0x56555555, 0x5a5a5aaa}
1676};
1677
1678/* Non-Shared-Antenna Coex Table */
1679static const struct coex_table_para table_nsant_8821c[] = {
1680 {0xffffffff, 0xffffffff}, /* case-100 */
1681 {0xffff55ff, 0xfafafafa},
1682 {0x66555555, 0x66555555},
1683 {0xaaaaaaaa, 0xaaaaaaaa},
1684 {0x5a5a5a5a, 0x5a5a5a5a},
1685 {0xffffffff, 0xffffffff}, /* case-105 */
1686 {0x5afa5afa, 0x5afa5afa},
1687 {0x55555555, 0xfafafafa},
1688 {0x66555555, 0xfafafafa},
1689 {0x66555555, 0x5a5a5a5a},
1690 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1691 {0x66555555, 0xaaaaaaaa},
1692 {0xffff55ff, 0xfafafafa},
1693 {0xffff55ff, 0x5afa5afa},
1694 {0xffff55ff, 0xaaaaaaaa},
1695 {0xffff55ff, 0xffff55ff}, /* case-115 */
1696 {0xaaffffaa, 0x5afa5afa},
1697 {0xaaffffaa, 0xaaaaaaaa},
1698 {0xffffffff, 0xfafafafa},
1699 {0xffff55ff, 0xfafafafa},
1700 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1701 {0xffff55ff, 0x5afa5afa},
1702 {0xffff55ff, 0x5afa5afa},
1703 {0x55ff55ff, 0x55ff55ff}
1704};
1705
1706/* Shared-Antenna TDMA */
1707static const struct coex_tdma_para tdma_sant_8821c[] = {
1708 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1709 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1710 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1711 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1712 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1713 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1714 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1715 { {0x61, 0x35, 0x03, 0x11, 0x10} },
1716 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1717 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1718 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1719 { {0x61, 0x08, 0x03, 0x11, 0x15} },
1720 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1721 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1722 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1723 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1724 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1725 { {0x51, 0x3a, 0x03, 0x11, 0x50} },
1726 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1727 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1728 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1729 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1730 { {0x51, 0x08, 0x03, 0x30, 0x54} },
1731 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1732 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1733 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1734 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1735 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1736};
1737
1738/* Non-Shared-Antenna TDMA */
1739static const struct coex_tdma_para tdma_nsant_8821c[] = {
1740 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1741 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1742 { {0x61, 0x25, 0x03, 0x11, 0x11} },
1743 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1744 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1745 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1746 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1747 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1748 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1749 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1750 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1751 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1752 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1753 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1754 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1755 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1756 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1757 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1758 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1759 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1760 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1761 { {0x51, 0x10, 0x03, 0x10, 0x50} }
3a431282
TEH		 1762};
1763
7b080e08
PCC		 1764static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1765
1766/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1767static const struct coex_rf_para rf_para_tx_8821c[] = {
1768 {0, 0, false, 7}, /* for normal */
1769 {0, 20, false, 7}, /* for WL-CPT */
1770 {8, 17, true, 4},
1771 {7, 18, true, 4},
1772 {6, 19, true, 4},
1773 {5, 20, true, 4}
1774};
1775
1776static const struct coex_rf_para rf_para_rx_8821c[] = {
1777 {0, 0, false, 7}, /* for normal */
1778 {0, 20, false, 7}, /* for WL-CPT */
1779 {3, 24, true, 5},
1780 {2, 26, true, 5},
1781 {1, 27, true, 5},
1782 {0, 28, true, 5}
1783};
1784
1785static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c));
1786
3a431282
TEH		 1787static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = {
1788 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1789 11, 11, 12, 12, 12, 12, 12},
1790 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1791 11, 12, 12, 12, 12, 12, 12, 12},
1792 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1793 11, 12, 12, 12, 12, 12, 12},
1794};
1795
1796static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = {
1797 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1798 12, 12, 12, 12, 12, 12, 12},
1799 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1800 12, 12, 12, 12, 12, 12, 12, 12},
1801 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1802 11, 12, 12, 12, 12, 12, 12, 12},
1803};
1804
1805static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = {
1806 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1807 11, 11, 12, 12, 12, 12, 12},
1808 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1809 11, 12, 12, 12, 12, 12, 12, 12},
1810 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1811 11, 12, 12, 12, 12, 12, 12},
1812};
1813
1814static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = {
1815 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1816 12, 12, 12, 12, 12, 12, 12},
1817 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1818 12, 12, 12, 12, 12, 12, 12, 12},
1819 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1820 11, 12, 12, 12, 12, 12, 12, 12},
1821};
1822
1823static const u8 rtw8821c_pwrtrk_2gb_n[] = {
1824 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1825 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1826};
1827
1828static const u8 rtw8821c_pwrtrk_2gb_p[] = {
1829 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1830 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1831};
1832
1833static const u8 rtw8821c_pwrtrk_2ga_n[] = {
1834 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1835 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1836};
1837
1838static const u8 rtw8821c_pwrtrk_2ga_p[] = {
1839 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1840 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1841};
1842
1843static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = {
1844 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1845 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1846};
1847
1848static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = {
1849 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1850 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1851};
1852
1853static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = {
1854 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1855 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1856};
1857
1858static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = {
1859 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1860 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1861};
1862
9de6959f 1863static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = {
3a431282
TEH		 1864 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1865 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1],
1866 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2],
1867 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1868 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1],
1869 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2],
1870 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1871 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1],
1872 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2],
1873 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1874 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1],
1875 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2],
1876 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n,
1877 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p,
1878 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n,
1879 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p,
1880 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n,
1881 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p,
1882 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n,
1883 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p,
769a29ce
TEH		 1884};
1885
7b080e08
PCC		 1886static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = {
1887 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1888 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1889 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1890 {0, 0, RTW_REG_DOMAIN_NL},
1891 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1892 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1893 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1894 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1895 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1896 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1897 {0, 0, RTW_REG_DOMAIN_NL},
1898 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1899 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1900 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1901 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1902 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1903 {0, 0, RTW_REG_DOMAIN_NL},
1904 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1905 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1906 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1907 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1908 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1909};
1910
89d8f53f 1911const struct rtw_chip_info rtw8821c_hw_spec = {
769a29ce
TEH		 1912 .ops = &rtw8821c_ops,
1913 .id = RTW_CHIP_TYPE_8821C,
1914 .fw_name = "rtw88/rtw8821c_fw.bin",
1915 .wlan_cpu = RTW_WCPU_11AC,
1916 .tx_pkt_desc_sz = 48,
1917 .tx_buf_desc_sz = 16,
1918 .rx_pkt_desc_sz = 24,
1919 .rx_buf_desc_sz = 8,
1920 .phy_efuse_size = 512,
1921 .log_efuse_size = 512,
1922 .ptct_efuse_size = 96,
1923 .txff_size = 65536,
1924 .rxff_size = 16384,
ffa71c54 1925 .rsvd_drv_pg_num = 8,
769a29ce
TEH		 1926 .txgi_factor = 1,
1927 .is_pwr_by_rate_dec = true,
1928 .max_power_index = 0x3f,
1929 .csi_buf_pg_num = 0,
1930 .band = RTW_BAND_2G | RTW_BAND_5G,
d2eb7cb9 1931 .page_size = TX_PAGE_SIZE,
6cf2086f 1932 .dig_min = 0x1c,
769a29ce
TEH		 1933 .ht_supported = true,
1934 .vht_supported = true,
1935 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
1936 .sys_func_en = 0xD8,
1937 .pwr_on_seq = card_enable_flow_8821c,
1938 .pwr_off_seq = card_disable_flow_8821c,
1939 .page_table = page_table_8821c,
1940 .rqpn_table = rqpn_table_8821c,
1941 .prioq_addrs = &prioq_addrs_8821c,
1942 .intf_table = &phy_para_table_8821c,
6cf2086f 1943 .dig = rtw8821c_dig,
769a29ce
TEH		 1944 .rf_base_addr = {0x2800, 0x2c00},
1945 .rf_sipi_addr = {0xc90, 0xe90},
1946 .ltecoex_addr = &rtw8821c_ltecoex_addr,
1947 .mac_tbl = &rtw8821c_mac_tbl,
1948 .agc_tbl = &rtw8821c_agc_tbl,
1949 .bb_tbl = &rtw8821c_bb_tbl,
1950 .rf_tbl = {&rtw8821c_rf_a_tbl},
1951 .rfe_defs = rtw8821c_rfe_defs,
1952 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
1953 .rx_ldpc = false,
3a431282
TEH		 1954 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl,
1955 .iqk_threshold = 8,
5f4eab88
TEH		 1956 .bfer_su_max_num = 2,
1957 .bfer_mu_max_num = 1,
1d6d131d 1958 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2,
d2eb7cb9 1959 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
7b080e08
PCC		 1960
1961 .coex_para_ver = 0x19092746,
1962 .bt_desired_ver = 0x46,
1963 .scbd_support = true,
1964 .new_scbd10_def = false,
1a74daed 1965 .ble_hid_profile_support = false,
0c496a7d 1966 .wl_mimo_ps_support = false,
7b080e08
PCC		 1967 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
1968 .bt_rssi_type = COEX_BTRSSI_RATIO,
1969 .ant_isolation = 15,
1970 .rssi_tolerance = 2,
1971 .wl_rssi_step = wl_rssi_step_8821c,
1972 .bt_rssi_step = bt_rssi_step_8821c,
1973 .table_sant_num = ARRAY_SIZE(table_sant_8821c),
1974 .table_sant = table_sant_8821c,
1975 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c),
1976 .table_nsant = table_nsant_8821c,
1977 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c),
1978 .tdma_sant = tdma_sant_8821c,
1979 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c),
1980 .tdma_nsant = tdma_nsant_8821c,
1981 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c),
1982 .wl_rf_para_tx = rf_para_tx_8821c,
1983 .wl_rf_para_rx = rf_para_rx_8821c,
1984 .bt_afh_span_bw20 = 0x24,
1985 .bt_afh_span_bw40 = 0x36,
1986 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c),
1987 .afh_5g = afh_5g_8821c,
1988
1989 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c),
1990 .coex_info_hw_regs = coex_info_hw_regs_8821c,
769a29ce
TEH		 1991};
1992EXPORT_SYMBOL(rtw8821c_hw_spec);
1993
1994MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin");
1995
1996MODULE_AUTHOR("Realtek Corporation");
1997MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver");
1998MODULE_LICENSE("Dual BSD/GPL");
Linux 6.x block layer and io_uring tree(s)