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811853da PKS |
1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* Copyright(c) 2018-2019 Realtek Corporation | |
3 | */ | |
4 | ||
5 | #ifndef __RTW8723D_H__ | |
6 | #define __RTW8723D_H__ | |
7 | ||
1d229e88 PKS |
8 | enum rtw8723d_path { |
9 | PATH_S1, | |
10 | PATH_S0, | |
11 | PATH_NR, | |
12 | }; | |
13 | ||
14 | enum rtw8723d_iqk_round { | |
15 | IQK_ROUND_0, | |
16 | IQK_ROUND_1, | |
17 | IQK_ROUND_2, | |
18 | IQK_ROUND_HYBRID, | |
19 | IQK_ROUND_SIZE, | |
20 | IQK_ROUND_INVALID = 0xff, | |
21 | }; | |
22 | ||
23 | enum rtw8723d_iqk_result { | |
24 | IQK_S1_TX_X, | |
25 | IQK_S1_TX_Y, | |
26 | IQK_S1_RX_X, | |
27 | IQK_S1_RX_Y, | |
28 | IQK_S0_TX_X, | |
29 | IQK_S0_TX_Y, | |
30 | IQK_S0_RX_X, | |
31 | IQK_S0_RX_Y, | |
32 | IQK_NR, | |
33 | IQK_SX_NR = IQK_NR / PATH_NR, | |
34 | }; | |
35 | ||
ab0a031e PKS |
36 | struct rtw8723de_efuse { |
37 | u8 mac_addr[ETH_ALEN]; /* 0xd0 */ | |
38 | u8 vender_id[2]; | |
39 | u8 device_id[2]; | |
40 | u8 sub_vender_id[2]; | |
41 | u8 sub_device_id[2]; | |
42 | }; | |
43 | ||
87caeef0 SH |
44 | struct rtw8723du_efuse { |
45 | u8 res4[48]; /* 0xd0 */ | |
46 | u8 vender_id[2]; /* 0x100 */ | |
47 | u8 product_id[2]; /* 0x102 */ | |
48 | u8 usb_option; /* 0x104 */ | |
2e1b3ae3 | 49 | u8 res5[2]; /* 0x105 */ |
87caeef0 SH |
50 | u8 mac_addr[ETH_ALEN]; /* 0x107 */ |
51 | }; | |
52 | ||
9be20a82 MB |
53 | struct rtw8723ds_efuse { |
54 | u8 res4[0x4a]; /* 0xd0 */ | |
55 | u8 mac_addr[ETH_ALEN]; /* 0x11a */ | |
56 | }; | |
57 | ||
ab0a031e PKS |
58 | struct rtw8723d_efuse { |
59 | __le16 rtl_id; | |
60 | u8 rsvd[2]; | |
61 | u8 afe; | |
62 | u8 rsvd1[11]; | |
63 | ||
64 | /* power index for four RF paths */ | |
65 | struct rtw_txpwr_idx txpwr_idx_table[4]; | |
66 | ||
67 | u8 channel_plan; /* 0xb8 */ | |
68 | u8 xtal_k; | |
69 | u8 thermal_meter; | |
70 | u8 iqk_lck; | |
71 | u8 pa_type; /* 0xbc */ | |
72 | u8 lna_type_2g[2]; /* 0xbd */ | |
73 | u8 lna_type_5g[2]; | |
74 | u8 rf_board_option; | |
75 | u8 rf_feature_option; | |
76 | u8 rf_bt_setting; | |
77 | u8 eeprom_version; | |
78 | u8 eeprom_customer_id; | |
79 | u8 tx_bb_swing_setting_2g; | |
80 | u8 res_c7; | |
81 | u8 tx_pwr_calibrate_rate; | |
82 | u8 rf_antenna_option; /* 0xc9 */ | |
83 | u8 rfe_option; | |
84 | u8 country_code[2]; | |
85 | u8 res[3]; | |
87caeef0 SH |
86 | union { |
87 | struct rtw8723de_efuse e; | |
88 | struct rtw8723du_efuse u; | |
9be20a82 | 89 | struct rtw8723ds_efuse s; |
87caeef0 | 90 | }; |
ab0a031e PKS |
91 | }; |
92 | ||
e36db29c LF |
93 | extern const struct rtw_chip_info rtw8723d_hw_spec; |
94 | ||
158441a2 PKS |
95 | /* phy status page0 */ |
96 | #define GET_PHY_STAT_P0_PWDB(phy_stat) \ | |
97 | le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) | |
98 | ||
99 | /* phy status page1 */ | |
100 | #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \ | |
101 | le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) | |
102 | #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \ | |
103 | le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16)) | |
104 | #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \ | |
105 | le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28)) | |
106 | #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \ | |
107 | le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8)) | |
108 | #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \ | |
109 | le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12)) | |
110 | #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \ | |
111 | le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0)) | |
112 | #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \ | |
113 | le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0)) | |
114 | #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ | |
115 | le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) | |
116 | ||
1d229e88 PKS |
117 | static inline s32 iqkxy_to_s32(s32 val) |
118 | { | |
119 | /* val is Q10.8 */ | |
120 | return sign_extend32(val, 9); | |
121 | } | |
122 | ||
123 | static inline s32 iqk_mult(s32 x, s32 y, s32 *ext) | |
124 | { | |
125 | /* x, y and return value are Q10.8 */ | |
126 | s32 t; | |
127 | ||
128 | t = x * y; | |
129 | if (ext) | |
130 | *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */ | |
131 | ||
132 | return (t >> 8); /* Q.16 --> Q.8 */ | |
133 | } | |
134 | ||
608d2a08 PKS |
135 | #define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing) |
136 | #define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing) | |
137 | #define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing) | |
138 | #define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing) | |
139 | #define RTW_DEF_OFDM_SWING_INDEX 28 | |
140 | #define RTW_DEF_CCK_SWING_INDEX 28 | |
141 | ||
1d229e88 PKS |
142 | #define MAX_TOLERANCE 5 |
143 | #define IQK_TX_X_ERR 0x142 | |
144 | #define IQK_TX_Y_ERR 0x42 | |
145 | #define IQK_RX_X_UPPER 0x11a | |
146 | #define IQK_RX_X_LOWER 0xe6 | |
147 | #define IQK_RX_Y_LMT 0x1a | |
148 | #define IQK_TX_OK BIT(0) | |
149 | #define IQK_RX_OK BIT(1) | |
150 | #define PATH_IQK_RETRY 2 | |
151 | ||
5f028a9c PKS |
152 | #define SPUR_THRES 0x16 |
153 | #define CCK_DFIR_NR 3 | |
154 | #define DIS_3WIRE 0xccf000c0 | |
155 | #define EN_3WIRE 0xccc000c0 | |
156 | #define START_PSD 0x400000 | |
157 | #define FREQ_CH13 0xfccd | |
158 | #define FREQ_CH14 0xff9a | |
159 | #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0) | |
160 | #define RFCFGCH_BW_MASK (BIT(11) | BIT(10)) | |
161 | #define RFCFGCH_BW_20M (BIT(11) | BIT(10)) | |
162 | #define RFCFGCH_BW_40M BIT(10) | |
163 | #define BIT_MASK_RFMOD BIT(0) | |
f71eb7f6 | 164 | #define BIT_LCK BIT(15) |
5f028a9c | 165 | |
d1391c49 | 166 | #define REG_GPIO_INTM 0x0048 |
1d229e88 | 167 | #define REG_BTG_SEL 0x0067 |
efad6611 | 168 | #define BIT_MASK_BTG_WL BIT(7) |
1d229e88 | 169 | #define REG_LTECOEX_PATH_CONTROL 0x0070 |
7e149368 PKS |
170 | #define REG_LTECOEX_CTRL 0x07c0 |
171 | #define REG_LTECOEX_WRITE_DATA 0x07c4 | |
172 | #define REG_LTECOEX_READ_DATA 0x07c8 | |
5f028a9c | 173 | #define REG_PSDFN 0x0808 |
1d229e88 | 174 | #define REG_BB_PWR_SAV1_11N 0x0874 |
d1391c49 | 175 | #define REG_ANA_PARAM1 0x0880 |
5f028a9c PKS |
176 | #define REG_ANALOG_P4 0x088c |
177 | #define REG_PSDRPT 0x08b4 | |
178 | #define REG_FPGA1_RFMOD 0x0900 | |
1d229e88 | 179 | #define REG_BB_SEL_BTG 0x0948 |
5f028a9c PKS |
180 | #define REG_BBRX_DFIR 0x0954 |
181 | #define BIT_MASK_RXBB_DFIR GENMASK(27, 24) | |
182 | #define BIT_RXBB_DFIR_EN BIT(19) | |
183 | #define REG_CCK0_SYS 0x0a00 | |
184 | #define BIT_CCK_SIDE_BAND BIT(4) | |
1d229e88 | 185 | #define REG_CCK_ANT_SEL_11N 0x0a04 |
8f0cb24c | 186 | #define REG_PWRTH 0x0a08 |
439d4a97 PKS |
187 | #define REG_CCK_FA_RST_11N 0x0a2c |
188 | #define BIT_MASK_CCK_CNT_KEEP BIT(12) | |
189 | #define BIT_MASK_CCK_CNT_EN BIT(13) | |
190 | #define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN) | |
191 | #define BIT_MASK_CCK_FA_KEEP BIT(14) | |
192 | #define BIT_MASK_CCK_FA_EN BIT(15) | |
193 | #define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN) | |
194 | #define REG_CCK_FA_LSB_11N 0x0a5c | |
195 | #define REG_CCK_FA_MSB_11N 0x0a58 | |
196 | #define REG_CCK_CCA_CNT_11N 0x0a60 | |
197 | #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0) | |
198 | #define BIT_MASK_CCK_FA_LSB GENMASK(15, 8) | |
8f0cb24c PKS |
199 | #define REG_PWRTH2 0x0aa8 |
200 | #define REG_CSRATIO 0x0aaa | |
439d4a97 PKS |
201 | #define REG_OFDM_FA_HOLDC_11N 0x0c00 |
202 | #define BIT_MASK_OFDM_FA_KEEP BIT(31) | |
1d229e88 PKS |
203 | #define REG_BB_RX_PATH_11N 0x0c04 |
204 | #define REG_TRMUX_11N 0x0c08 | |
439d4a97 PKS |
205 | #define REG_OFDM_FA_RSTC_11N 0x0c0c |
206 | #define BIT_MASK_OFDM_FA_RST BIT(31) | |
1d229e88 PKS |
207 | #define REG_A_RXIQI 0x0c14 |
208 | #define BIT_MASK_RXIQ_S1_X 0x000003FF | |
209 | #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00 | |
210 | #define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F) | |
5f028a9c PKS |
211 | #define REG_OFDM0_RXDSP 0x0c40 |
212 | #define BIT_MASK_RXDSP GENMASK(28, 24) | |
213 | #define BIT_EN_RXDSP BIT(9) | |
1d229e88 PKS |
214 | #define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c |
215 | #define BIT_MASK_OFDM0_EXT_A BIT(31) | |
216 | #define BIT_MASK_OFDM0_EXT_C BIT(29) | |
217 | #define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28)) | |
218 | #define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28)) | |
75e69fb1 PKS |
219 | #define REG_OFDM0_XAAGC1 0x0c50 |
220 | #define REG_OFDM0_XBAGC1 0x0c58 | |
d1391c49 | 221 | #define REG_AGCRSSI 0x0c78 |
1d229e88 PKS |
222 | #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80 |
223 | #define BIT_MASK_TXIQ_ELM_A 0x03ff | |
224 | #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \ | |
225 | ((a) & 0x03ff)) | |
226 | #define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16) | |
227 | #define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F) | |
228 | #define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22) | |
229 | #define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94 | |
230 | #define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6) | |
231 | #define REG_RXIQK_MATRIX_LSB_11N 0x0ca0 | |
232 | #define BIT_MASK_RXIQ_S1_Y2 0xF0000000 | |
233 | #define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF) | |
234 | #define REG_TXIQ_AB_S0 0x0cd0 | |
235 | #define BIT_MASK_TXIQ_A_S0 0x000007FE | |
236 | #define BIT_MASK_TXIQ_A_EXT_S0 BIT(0) | |
237 | #define BIT_MASK_TXIQ_B_S0 0x0007E000 | |
238 | #define REG_TXIQ_CD_S0 0x0cd4 | |
239 | #define BIT_MASK_TXIQ_C_S0 0x000007FE | |
240 | #define BIT_MASK_TXIQ_C_EXT_S0 BIT(0) | |
241 | #define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13) | |
242 | #define BIT_MASK_TXIQ_D_EXT_S0 BIT(12) | |
243 | #define REG_RXIQ_AB_S0 0x0cd8 | |
244 | #define BIT_MASK_RXIQ_X_S0 0x000003FF | |
245 | #define BIT_MASK_RXIQ_Y_S0 0x003FF000 | |
439d4a97 PKS |
246 | #define REG_OFDM_FA_TYPE1_11N 0x0cf0 |
247 | #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0) | |
248 | #define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16) | |
249 | #define REG_OFDM_FA_RSTD_11N 0x0d00 | |
250 | #define BIT_MASK_OFDM_FA_RST1 BIT(27) | |
251 | #define BIT_MASK_OFDM_FA_KEEP1 BIT(31) | |
f71eb7f6 PKS |
252 | #define REG_CTX 0x0d03 |
253 | #define BIT_MASK_CTX_TYPE GENMASK(6, 4) | |
5f028a9c PKS |
254 | #define REG_OFDM1_CFOTRK 0x0d2c |
255 | #define BIT_EN_CFOTRK BIT(28) | |
256 | #define REG_OFDM1_CSI1 0x0d40 | |
257 | #define REG_OFDM1_CSI2 0x0d44 | |
258 | #define REG_OFDM1_CSI3 0x0d48 | |
259 | #define REG_OFDM1_CSI4 0x0d4c | |
439d4a97 PKS |
260 | #define REG_OFDM_FA_TYPE2_11N 0x0da0 |
261 | #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0) | |
262 | #define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16) | |
263 | #define REG_OFDM_FA_TYPE3_11N 0x0da4 | |
264 | #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0) | |
265 | #define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16) | |
266 | #define REG_OFDM_FA_TYPE4_11N 0x0da8 | |
267 | #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0) | |
1d229e88 PKS |
268 | #define REG_FPGA0_IQK_11N 0x0e28 |
269 | #define BIT_MASK_IQK_MOD 0xffffff00 | |
270 | #define EN_IQK 0x808000 | |
271 | #define RST_IQK 0x000000 | |
272 | #define REG_TXIQK_TONE_A_11N 0x0e30 | |
273 | #define REG_RXIQK_TONE_A_11N 0x0e34 | |
274 | #define REG_TXIQK_PI_A_11N 0x0e38 | |
275 | #define REG_RXIQK_PI_A_11N 0x0e3c | |
276 | #define REG_TXIQK_11N 0x0e40 | |
277 | #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y)) | |
278 | #define REG_RXIQK_11N 0x0e44 | |
279 | #define REG_IQK_AGC_PTS_11N 0x0e48 | |
280 | #define REG_IQK_AGC_RSP_11N 0x0e4c | |
281 | #define REG_TX_IQK_TONE_B 0x0e50 | |
282 | #define REG_RX_IQK_TONE_B 0x0e54 | |
283 | #define REG_IQK_RES_TX 0x0e94 | |
284 | #define BIT_MASK_RES_TX GENMASK(25, 16) | |
285 | #define REG_IQK_RES_TY 0x0e9c | |
286 | #define BIT_MASK_RES_TY GENMASK(25, 16) | |
287 | #define REG_IQK_RES_RX 0x0ea4 | |
288 | #define BIT_MASK_RES_RX GENMASK(25, 16) | |
289 | #define REG_IQK_RES_RY 0x0eac | |
290 | #define BIT_IQK_TX_FAIL BIT(28) | |
291 | #define BIT_IQK_RX_FAIL BIT(27) | |
292 | #define BIT_IQK_DONE BIT(26) | |
293 | #define BIT_MASK_RES_RY GENMASK(25, 16) | |
439d4a97 PKS |
294 | #define REG_PAGE_F_RST_11N 0x0f14 |
295 | #define BIT_MASK_F_RST_ALL BIT(16) | |
296 | #define REG_IGI_C_11N 0x0f84 | |
297 | #define REG_IGI_D_11N 0x0f88 | |
298 | #define REG_HT_CRC32_CNT_11N 0x0f90 | |
299 | #define BIT_MASK_HT_CRC_OK GENMASK(15, 0) | |
300 | #define BIT_MASK_HT_CRC_ERR GENMASK(31, 16) | |
301 | #define REG_OFDM_CRC32_CNT_11N 0x0f94 | |
302 | #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0) | |
303 | #define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16) | |
304 | #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8 | |
75e69fb1 | 305 | |
811853da | 306 | #endif |