Commit | Line | Data |
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e3037485 YHC |
1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
2 | /* Copyright(c) 2018-2019 Realtek Corporation | |
3 | */ | |
4 | ||
7b80f3e4 ZZY |
5 | #include <linux/devcoredump.h> |
6 | ||
e3037485 YHC |
7 | #include "main.h" |
8 | #include "regd.h" | |
9 | #include "fw.h" | |
10 | #include "ps.h" | |
11 | #include "sec.h" | |
12 | #include "mac.h" | |
4136214f | 13 | #include "coex.h" |
e3037485 YHC |
14 | #include "phy.h" |
15 | #include "reg.h" | |
16 | #include "efuse.h" | |
3745d3e5 | 17 | #include "tx.h" |
e3037485 | 18 | #include "debug.h" |
0bd95573 | 19 | #include "bf.h" |
8704d0be | 20 | #include "sar.h" |
a5d25f9f | 21 | #include "sdio.h" |
e3037485 | 22 | |
fc3ac64a CYL |
23 | bool rtw_disable_lps_deep_mode; |
24 | EXPORT_SYMBOL(rtw_disable_lps_deep_mode); | |
0bd95573 | 25 | bool rtw_bf_support = true; |
e3037485 YHC |
26 | unsigned int rtw_debug_mask; |
27 | EXPORT_SYMBOL(rtw_debug_mask); | |
7285eb96 ZZY |
28 | /* EDCCA is enabled during normal behavior. For debugging purpose in |
29 | * a noisy environment, it can be disabled via edcca debugfs. Because | |
30 | * all rtw88 devices will probably be affected if environment is noisy, | |
31 | * rtw_edcca_enabled is just declared by driver instead of by device. | |
32 | * So, turning it off will take effect for all rtw88 devices before | |
33 | * there is a tough reason to maintain rtw_edcca_enabled by device. | |
34 | */ | |
35 | bool rtw_edcca_enabled = true; | |
e3037485 | 36 | |
fc3ac64a | 37 | module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); |
0bd95573 | 38 | module_param_named(support_bf, rtw_bf_support, bool, 0644); |
e3037485 YHC |
39 | module_param_named(debug_mask, rtw_debug_mask, uint, 0644); |
40 | ||
fc3ac64a | 41 | MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); |
0bd95573 | 42 | MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); |
e3037485 YHC |
43 | MODULE_PARM_DESC(debug_mask, "Debugging mask"); |
44 | ||
45 | static struct ieee80211_channel rtw_channeltable_2g[] = { | |
46 | {.center_freq = 2412, .hw_value = 1,}, | |
47 | {.center_freq = 2417, .hw_value = 2,}, | |
48 | {.center_freq = 2422, .hw_value = 3,}, | |
49 | {.center_freq = 2427, .hw_value = 4,}, | |
50 | {.center_freq = 2432, .hw_value = 5,}, | |
51 | {.center_freq = 2437, .hw_value = 6,}, | |
52 | {.center_freq = 2442, .hw_value = 7,}, | |
53 | {.center_freq = 2447, .hw_value = 8,}, | |
54 | {.center_freq = 2452, .hw_value = 9,}, | |
55 | {.center_freq = 2457, .hw_value = 10,}, | |
56 | {.center_freq = 2462, .hw_value = 11,}, | |
57 | {.center_freq = 2467, .hw_value = 12,}, | |
58 | {.center_freq = 2472, .hw_value = 13,}, | |
59 | {.center_freq = 2484, .hw_value = 14,}, | |
60 | }; | |
61 | ||
62 | static struct ieee80211_channel rtw_channeltable_5g[] = { | |
63 | {.center_freq = 5180, .hw_value = 36,}, | |
64 | {.center_freq = 5200, .hw_value = 40,}, | |
65 | {.center_freq = 5220, .hw_value = 44,}, | |
66 | {.center_freq = 5240, .hw_value = 48,}, | |
67 | {.center_freq = 5260, .hw_value = 52,}, | |
68 | {.center_freq = 5280, .hw_value = 56,}, | |
69 | {.center_freq = 5300, .hw_value = 60,}, | |
70 | {.center_freq = 5320, .hw_value = 64,}, | |
71 | {.center_freq = 5500, .hw_value = 100,}, | |
72 | {.center_freq = 5520, .hw_value = 104,}, | |
73 | {.center_freq = 5540, .hw_value = 108,}, | |
74 | {.center_freq = 5560, .hw_value = 112,}, | |
75 | {.center_freq = 5580, .hw_value = 116,}, | |
76 | {.center_freq = 5600, .hw_value = 120,}, | |
77 | {.center_freq = 5620, .hw_value = 124,}, | |
78 | {.center_freq = 5640, .hw_value = 128,}, | |
79 | {.center_freq = 5660, .hw_value = 132,}, | |
80 | {.center_freq = 5680, .hw_value = 136,}, | |
81 | {.center_freq = 5700, .hw_value = 140,}, | |
5e388841 | 82 | {.center_freq = 5720, .hw_value = 144,}, |
e3037485 YHC |
83 | {.center_freq = 5745, .hw_value = 149,}, |
84 | {.center_freq = 5765, .hw_value = 153,}, | |
85 | {.center_freq = 5785, .hw_value = 157,}, | |
86 | {.center_freq = 5805, .hw_value = 161,}, | |
87 | {.center_freq = 5825, .hw_value = 165, | |
88 | .flags = IEEE80211_CHAN_NO_HT40MINUS}, | |
89 | }; | |
90 | ||
91 | static struct ieee80211_rate rtw_ratetable[] = { | |
92 | {.bitrate = 10, .hw_value = 0x00,}, | |
93 | {.bitrate = 20, .hw_value = 0x01,}, | |
94 | {.bitrate = 55, .hw_value = 0x02,}, | |
95 | {.bitrate = 110, .hw_value = 0x03,}, | |
96 | {.bitrate = 60, .hw_value = 0x04,}, | |
97 | {.bitrate = 90, .hw_value = 0x05,}, | |
98 | {.bitrate = 120, .hw_value = 0x06,}, | |
99 | {.bitrate = 180, .hw_value = 0x07,}, | |
100 | {.bitrate = 240, .hw_value = 0x08,}, | |
101 | {.bitrate = 360, .hw_value = 0x09,}, | |
102 | {.bitrate = 480, .hw_value = 0x0a,}, | |
103 | {.bitrate = 540, .hw_value = 0x0b,}, | |
104 | }; | |
105 | ||
d16836cd PHH |
106 | static const struct ieee80211_iface_limit rtw_iface_limits[] = { |
107 | { | |
108 | .max = 1, | |
109 | .types = BIT(NL80211_IFTYPE_STATION), | |
110 | }, | |
111 | { | |
112 | .max = 1, | |
113 | .types = BIT(NL80211_IFTYPE_AP), | |
114 | } | |
115 | }; | |
116 | ||
117 | static const struct ieee80211_iface_combination rtw_iface_combs[] = { | |
118 | { | |
119 | .limits = rtw_iface_limits, | |
120 | .n_limits = ARRAY_SIZE(rtw_iface_limits), | |
121 | .max_interfaces = 2, | |
122 | .num_different_channels = 1, | |
123 | } | |
124 | }; | |
125 | ||
699c7730 TEH |
126 | u16 rtw_desc_to_bitrate(u8 desc_rate) |
127 | { | |
128 | struct ieee80211_rate rate; | |
129 | ||
130 | if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) | |
131 | return 0; | |
132 | ||
133 | rate = rtw_ratetable[desc_rate]; | |
134 | ||
135 | return rate.bitrate; | |
136 | } | |
137 | ||
e3037485 YHC |
138 | static struct ieee80211_supported_band rtw_band_2ghz = { |
139 | .band = NL80211_BAND_2GHZ, | |
140 | ||
141 | .channels = rtw_channeltable_2g, | |
142 | .n_channels = ARRAY_SIZE(rtw_channeltable_2g), | |
143 | ||
144 | .bitrates = rtw_ratetable, | |
145 | .n_bitrates = ARRAY_SIZE(rtw_ratetable), | |
146 | ||
147 | .ht_cap = {0}, | |
148 | .vht_cap = {0}, | |
149 | }; | |
150 | ||
151 | static struct ieee80211_supported_band rtw_band_5ghz = { | |
152 | .band = NL80211_BAND_5GHZ, | |
153 | ||
154 | .channels = rtw_channeltable_5g, | |
155 | .n_channels = ARRAY_SIZE(rtw_channeltable_5g), | |
156 | ||
157 | /* 5G has no CCK rates */ | |
158 | .bitrates = rtw_ratetable + 4, | |
159 | .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, | |
160 | ||
161 | .ht_cap = {0}, | |
162 | .vht_cap = {0}, | |
163 | }; | |
164 | ||
165 | struct rtw_watch_dog_iter_data { | |
0bd95573 | 166 | struct rtw_dev *rtwdev; |
e3037485 | 167 | struct rtw_vif *rtwvif; |
e3037485 YHC |
168 | }; |
169 | ||
0bd95573 TEH |
170 | static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) |
171 | { | |
172 | struct rtw_bf_info *bf_info = &rtwdev->bf_info; | |
0bd95573 TEH |
173 | u8 fix_rate_enable = 0; |
174 | u8 new_csi_rate_idx; | |
175 | ||
176 | if (rtwvif->bfee.role != RTW_BFEE_SU && | |
177 | rtwvif->bfee.role != RTW_BFEE_MU) | |
178 | return; | |
179 | ||
93ae973f PKS |
180 | rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, |
181 | bf_info->cur_csi_rpt_rate, | |
182 | fix_rate_enable, &new_csi_rate_idx); | |
0bd95573 TEH |
183 | |
184 | if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) | |
185 | bf_info->cur_csi_rpt_rate = new_csi_rate_idx; | |
186 | } | |
187 | ||
8986f0a9 | 188 | static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif) |
e3037485 YHC |
189 | { |
190 | struct rtw_watch_dog_iter_data *iter_data = data; | |
191 | struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; | |
192 | ||
bcde60e5 | 193 | if (vif->type == NL80211_IFTYPE_STATION) |
f276e20b | 194 | if (vif->cfg.assoc) |
e3037485 | 195 | iter_data->rtwvif = rtwvif; |
e3037485 | 196 | |
0bd95573 TEH |
197 | rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); |
198 | ||
e3037485 YHC |
199 | rtwvif->stats.tx_unicast = 0; |
200 | rtwvif->stats.rx_unicast = 0; | |
201 | rtwvif->stats.tx_cnt = 0; | |
202 | rtwvif->stats.rx_cnt = 0; | |
203 | } | |
204 | ||
205 | /* process TX/RX statistics periodically for hardware, | |
206 | * the information helps hardware to enhance performance | |
207 | */ | |
208 | static void rtw_watch_dog_work(struct work_struct *work) | |
209 | { | |
210 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, | |
211 | watch_dog_work.work); | |
082a36dc | 212 | struct rtw_traffic_stats *stats = &rtwdev->stats; |
e3037485 | 213 | struct rtw_watch_dog_iter_data data = {}; |
3c519605 | 214 | bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); |
002a5db9 | 215 | u32 tx_unicast_mbps, rx_unicast_mbps; |
bcde60e5 | 216 | bool ps_active; |
e3037485 | 217 | |
d3e20fd1 YHC |
218 | mutex_lock(&rtwdev->mutex); |
219 | ||
3c519605 | 220 | if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) |
d3e20fd1 | 221 | goto unlock; |
e3037485 YHC |
222 | |
223 | ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, | |
224 | RTW_WATCH_DOG_DELAY_TIME); | |
225 | ||
4136214f | 226 | if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) |
3c519605 | 227 | set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); |
4136214f | 228 | else |
3c519605 | 229 | clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); |
4136214f | 230 | |
3c519605 | 231 | if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) |
d8350768 | 232 | rtw_coex_wl_status_change_notify(rtwdev, 0); |
4136214f | 233 | |
082a36dc TSL |
234 | if (stats->tx_cnt > RTW_LPS_THRESHOLD || |
235 | stats->rx_cnt > RTW_LPS_THRESHOLD) | |
bcde60e5 YHC |
236 | ps_active = true; |
237 | else | |
238 | ps_active = false; | |
239 | ||
002a5db9 BS |
240 | tx_unicast_mbps = stats->tx_unicast >> RTW_TP_SHIFT; |
241 | rx_unicast_mbps = stats->rx_unicast >> RTW_TP_SHIFT; | |
242 | ||
243 | ewma_tp_add(&stats->tx_ewma_tp, tx_unicast_mbps); | |
244 | ewma_tp_add(&stats->rx_ewma_tp, rx_unicast_mbps); | |
082a36dc TSL |
245 | stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); |
246 | stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); | |
247 | ||
e3037485 | 248 | /* reset tx/rx statictics */ |
082a36dc TSL |
249 | stats->tx_unicast = 0; |
250 | stats->rx_unicast = 0; | |
251 | stats->tx_cnt = 0; | |
252 | stats->rx_cnt = 0; | |
e3037485 | 253 | |
37ba5de2 YHC |
254 | if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) |
255 | goto unlock; | |
256 | ||
257 | /* make sure BB/RF is working for dynamic mech */ | |
258 | rtw_leave_lps(rtwdev); | |
c2c0de23 CTK |
259 | rtw_coex_wl_status_check(rtwdev); |
260 | rtw_coex_query_bt_hid_list(rtwdev); | |
37ba5de2 YHC |
261 | |
262 | rtw_phy_dynamic_mechanism(rtwdev); | |
263 | ||
002a5db9 BS |
264 | rtw_hci_dynamic_rx_agg(rtwdev, |
265 | tx_unicast_mbps >= 1 || rx_unicast_mbps >= 1); | |
266 | ||
0bd95573 | 267 | data.rtwdev = rtwdev; |
313f6dc7 MB |
268 | /* rtw_iterate_vifs internally uses an atomic iterator which is needed |
269 | * to avoid taking local->iflist_mtx mutex | |
270 | */ | |
271 | rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data); | |
e3037485 YHC |
272 | |
273 | /* fw supports only one station associated to enter lps, if there are | |
274 | * more than two stations associated to the AP, then we can not enter | |
275 | * lps, because fw does not handle the overlapped beacon interval | |
bcde60e5 | 276 | * |
3918dd01 PKS |
277 | * rtw_recalc_lps() iterate vifs and determine if driver can enter |
278 | * ps by vif->type and vif->cfg.ps, all we need to do here is to | |
bcde60e5 YHC |
279 | * get that vif and check if device is having traffic more than the |
280 | * threshold. | |
e3037485 | 281 | */ |
cd96e22b | 282 | if (rtwdev->ps_enabled && data.rtwvif && !ps_active && |
5ec69129 | 283 | !rtwdev->beacon_loss && !rtwdev->ap_active) |
3d391c06 | 284 | rtw_enter_lps(rtwdev, data.rtwvif->port); |
e3037485 YHC |
285 | |
286 | rtwdev->watch_dog_cnt++; | |
d3e20fd1 YHC |
287 | |
288 | unlock: | |
289 | mutex_unlock(&rtwdev->mutex); | |
e3037485 YHC |
290 | } |
291 | ||
292 | static void rtw_c2h_work(struct work_struct *work) | |
293 | { | |
294 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); | |
295 | struct sk_buff *skb, *tmp; | |
296 | ||
297 | skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { | |
298 | skb_unlink(skb, &rtwdev->c2h_queue); | |
299 | rtw_fw_c2h_cmd_handle(rtwdev, skb); | |
300 | dev_kfree_skb_any(skb); | |
301 | } | |
302 | } | |
303 | ||
c17f2716 PHH |
304 | static void rtw_ips_work(struct work_struct *work) |
305 | { | |
306 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); | |
307 | ||
308 | mutex_lock(&rtwdev->mutex); | |
29ed2d76 PHH |
309 | if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) |
310 | rtw_enter_ips(rtwdev); | |
c17f2716 PHH |
311 | mutex_unlock(&rtwdev->mutex); |
312 | } | |
313 | ||
bcafcb95 PKS |
314 | static void rtw_sta_rc_work(struct work_struct *work) |
315 | { | |
316 | struct rtw_sta_info *si = container_of(work, struct rtw_sta_info, | |
317 | rc_work); | |
318 | struct rtw_dev *rtwdev = si->rtwdev; | |
319 | ||
320 | mutex_lock(&rtwdev->mutex); | |
321 | rtw_update_sta_info(rtwdev, si, true); | |
322 | mutex_unlock(&rtwdev->mutex); | |
323 | } | |
324 | ||
5c831644 TEH |
325 | int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, |
326 | struct ieee80211_vif *vif) | |
327 | { | |
328 | struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; | |
28c11c29 | 329 | struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; |
5c831644 TEH |
330 | int i; |
331 | ||
902cb7b1 PKS |
332 | if (vif->type == NL80211_IFTYPE_STATION) { |
333 | si->mac_id = rtwvif->mac_id; | |
334 | } else { | |
335 | si->mac_id = rtw_acquire_macid(rtwdev); | |
336 | if (si->mac_id >= RTW_MAX_MAC_ID_NUM) | |
337 | return -ENOSPC; | |
338 | } | |
5c831644 | 339 | |
bcafcb95 | 340 | si->rtwdev = rtwdev; |
5c831644 TEH |
341 | si->sta = sta; |
342 | si->vif = vif; | |
343 | si->init_ra_lv = 1; | |
344 | ewma_rssi_init(&si->avg_rssi); | |
345 | for (i = 0; i < ARRAY_SIZE(sta->txq); i++) | |
346 | rtw_txq_init(rtwdev, sta->txq[i]); | |
bcafcb95 | 347 | INIT_WORK(&si->rc_work, rtw_sta_rc_work); |
5c831644 | 348 | |
c1edc864 | 349 | rtw_update_sta_info(rtwdev, si, true); |
5c831644 TEH |
350 | rtw_fw_media_status_report(rtwdev, si->mac_id, true); |
351 | ||
352 | rtwdev->sta_cnt++; | |
cd96e22b | 353 | rtwdev->beacon_loss = false; |
a0061be4 PKS |
354 | rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", |
355 | sta->addr, si->mac_id); | |
5c831644 TEH |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
360 | void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, | |
361 | bool fw_exist) | |
362 | { | |
363 | struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; | |
902cb7b1 | 364 | struct ieee80211_vif *vif = si->vif; |
5c831644 TEH |
365 | int i; |
366 | ||
bcafcb95 PKS |
367 | cancel_work_sync(&si->rc_work); |
368 | ||
902cb7b1 PKS |
369 | if (vif->type != NL80211_IFTYPE_STATION) |
370 | rtw_release_macid(rtwdev, si->mac_id); | |
5c831644 TEH |
371 | if (fw_exist) |
372 | rtw_fw_media_status_report(rtwdev, si->mac_id, false); | |
373 | ||
374 | for (i = 0; i < ARRAY_SIZE(sta->txq); i++) | |
375 | rtw_txq_cleanup(rtwdev, sta->txq[i]); | |
376 | ||
377 | kfree(si->mask); | |
378 | ||
379 | rtwdev->sta_cnt--; | |
a0061be4 PKS |
380 | rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", |
381 | sta->addr, si->mac_id); | |
5c831644 TEH |
382 | } |
383 | ||
7b80f3e4 ZZY |
384 | struct rtw_fwcd_hdr { |
385 | u32 item; | |
386 | u32 size; | |
387 | u32 padding1; | |
388 | u32 padding2; | |
389 | } __packed; | |
390 | ||
391 | static int rtw_fwcd_prep(struct rtw_dev *rtwdev) | |
392 | { | |
dcbf179c | 393 | const struct rtw_chip_info *chip = rtwdev->chip; |
7b80f3e4 ZZY |
394 | struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; |
395 | const struct rtw_fwcd_segs *segs = chip->fwcd_segs; | |
396 | u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); | |
397 | u8 i; | |
398 | ||
399 | if (segs) { | |
400 | prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); | |
401 | ||
402 | for (i = 0; i < segs->num; i++) | |
403 | prep_size += segs->segs[i]; | |
404 | } | |
405 | ||
406 | desc->data = vmalloc(prep_size); | |
407 | if (!desc->data) | |
408 | return -ENOMEM; | |
409 | ||
410 | desc->size = prep_size; | |
411 | desc->next = desc->data; | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) | |
417 | { | |
418 | struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; | |
419 | struct rtw_fwcd_hdr *hdr; | |
420 | u8 *next; | |
421 | ||
422 | if (!desc->data) { | |
423 | rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); | |
424 | return NULL; | |
425 | } | |
426 | ||
427 | next = desc->next + sizeof(struct rtw_fwcd_hdr); | |
428 | if (next - desc->data + size > desc->size) { | |
429 | rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); | |
430 | return NULL; | |
431 | } | |
432 | ||
433 | hdr = (struct rtw_fwcd_hdr *)(desc->next); | |
434 | hdr->item = item; | |
435 | hdr->size = size; | |
436 | hdr->padding1 = 0x01234567; | |
437 | hdr->padding2 = 0x89abcdef; | |
438 | desc->next = next + size; | |
439 | ||
440 | return next; | |
441 | } | |
442 | ||
443 | static void rtw_fwcd_dump(struct rtw_dev *rtwdev) | |
444 | { | |
445 | struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; | |
446 | ||
447 | rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); | |
448 | ||
449 | /* Data will be freed after lifetime of device coredump. After calling | |
450 | * dev_coredump, data is supposed to be handled by the device coredump | |
451 | * framework. Note that a new dump will be discarded if a previous one | |
452 | * hasn't been released yet. | |
453 | */ | |
454 | dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); | |
455 | } | |
456 | ||
457 | static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) | |
458 | { | |
459 | struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; | |
460 | ||
461 | if (free_self) { | |
462 | rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); | |
463 | vfree(desc->data); | |
464 | } | |
465 | ||
466 | desc->data = NULL; | |
467 | desc->next = NULL; | |
468 | } | |
469 | ||
470 | static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) | |
714f71f9 TEH |
471 | { |
472 | u32 size = rtwdev->chip->fw_rxff_size; | |
473 | u32 *buf; | |
474 | u8 seq; | |
714f71f9 | 475 | |
7b80f3e4 | 476 | buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); |
714f71f9 | 477 | if (!buf) |
7b80f3e4 | 478 | return -ENOMEM; |
714f71f9 TEH |
479 | |
480 | if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { | |
481 | rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); | |
7b80f3e4 | 482 | return -EINVAL; |
714f71f9 TEH |
483 | } |
484 | ||
485 | if (GET_FW_DUMP_LEN(buf) == 0) { | |
486 | rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); | |
7b80f3e4 | 487 | return -EINVAL; |
714f71f9 TEH |
488 | } |
489 | ||
490 | seq = GET_FW_DUMP_SEQ(buf); | |
7b80f3e4 | 491 | if (seq > 0) { |
714f71f9 TEH |
492 | rtw_dbg(rtwdev, RTW_DBG_FW, |
493 | "fw crash dump's seq is wrong: %d\n", seq); | |
7b80f3e4 | 494 | return -EINVAL; |
714f71f9 TEH |
495 | } |
496 | ||
7b80f3e4 | 497 | return 0; |
714f71f9 TEH |
498 | } |
499 | ||
13ce240a | 500 | int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, |
7b80f3e4 | 501 | u32 fwcd_item) |
13ce240a ZZY |
502 | { |
503 | u32 rxff = rtwdev->chip->fw_rxff_size; | |
504 | u32 dump_size, done_size = 0; | |
505 | u8 *buf; | |
506 | int ret; | |
507 | ||
7b80f3e4 | 508 | buf = rtw_fwcd_next(rtwdev, fwcd_item, size); |
13ce240a ZZY |
509 | if (!buf) |
510 | return -ENOMEM; | |
511 | ||
512 | while (size) { | |
513 | dump_size = size > rxff ? rxff : size; | |
514 | ||
515 | ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, | |
516 | dump_size); | |
517 | if (ret) { | |
518 | rtw_err(rtwdev, | |
519 | "ddma fw 0x%x [+0x%x] to fw fifo fail\n", | |
520 | ocp_src, done_size); | |
7b80f3e4 | 521 | return ret; |
13ce240a ZZY |
522 | } |
523 | ||
524 | ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, | |
525 | dump_size, (u32 *)(buf + done_size)); | |
526 | if (ret) { | |
527 | rtw_err(rtwdev, | |
528 | "dump fw 0x%x [+0x%x] from fw fifo fail\n", | |
529 | ocp_src, done_size); | |
7b80f3e4 | 530 | return ret; |
13ce240a ZZY |
531 | } |
532 | ||
533 | size -= dump_size; | |
534 | done_size += dump_size; | |
535 | } | |
536 | ||
7b80f3e4 | 537 | return 0; |
13ce240a ZZY |
538 | } |
539 | EXPORT_SYMBOL(rtw_dump_fw); | |
540 | ||
7b80f3e4 | 541 | int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) |
13ce240a ZZY |
542 | { |
543 | u8 *buf; | |
544 | u32 i; | |
545 | ||
546 | if (addr & 0x3) { | |
547 | WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); | |
548 | return -EINVAL; | |
549 | } | |
550 | ||
7b80f3e4 | 551 | buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); |
13ce240a ZZY |
552 | if (!buf) |
553 | return -ENOMEM; | |
554 | ||
555 | for (i = 0; i < size; i += 4) | |
556 | *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); | |
557 | ||
13ce240a ZZY |
558 | return 0; |
559 | } | |
560 | EXPORT_SYMBOL(rtw_dump_reg); | |
561 | ||
5c831644 TEH |
562 | void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, |
563 | struct ieee80211_bss_conf *conf) | |
564 | { | |
f276e20b JB |
565 | struct ieee80211_vif *vif = NULL; |
566 | ||
567 | if (conf) | |
568 | vif = container_of(conf, struct ieee80211_vif, bss_conf); | |
569 | ||
570 | if (conf && vif->cfg.assoc) { | |
571 | rtwvif->aid = vif->cfg.aid; | |
5c831644 TEH |
572 | rtwvif->net_type = RTW_NET_MGD_LINKED; |
573 | } else { | |
574 | rtwvif->aid = 0; | |
575 | rtwvif->net_type = RTW_NET_NO_LINK; | |
576 | } | |
577 | } | |
578 | ||
579 | static void rtw_reset_key_iter(struct ieee80211_hw *hw, | |
580 | struct ieee80211_vif *vif, | |
581 | struct ieee80211_sta *sta, | |
582 | struct ieee80211_key_conf *key, | |
583 | void *data) | |
584 | { | |
585 | struct rtw_dev *rtwdev = (struct rtw_dev *)data; | |
586 | struct rtw_sec_desc *sec = &rtwdev->sec; | |
587 | ||
588 | rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); | |
589 | } | |
590 | ||
591 | static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) | |
592 | { | |
593 | struct rtw_dev *rtwdev = (struct rtw_dev *)data; | |
594 | ||
595 | if (rtwdev->sta_cnt == 0) { | |
596 | rtw_warn(rtwdev, "sta count before reset should not be 0\n"); | |
597 | return; | |
598 | } | |
599 | rtw_sta_remove(rtwdev, sta, false); | |
600 | } | |
601 | ||
602 | static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
603 | { | |
604 | struct rtw_dev *rtwdev = (struct rtw_dev *)data; | |
605 | struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; | |
606 | ||
607 | rtw_bf_disassoc(rtwdev, vif, NULL); | |
608 | rtw_vif_assoc_changed(rtwvif, NULL); | |
609 | rtw_txq_cleanup(rtwdev, vif->txq); | |
902cb7b1 PKS |
610 | |
611 | rtw_release_macid(rtwdev, rtwvif->mac_id); | |
5c831644 TEH |
612 | } |
613 | ||
614 | void rtw_fw_recovery(struct rtw_dev *rtwdev) | |
615 | { | |
616 | if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) | |
617 | ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); | |
618 | } | |
619 | ||
13ce240a | 620 | static void __fw_recovery_work(struct rtw_dev *rtwdev) |
5c831644 | 621 | { |
7b80f3e4 | 622 | int ret = 0; |
714f71f9 | 623 | |
13ce240a | 624 | set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); |
6cd4b59d | 625 | clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); |
7b80f3e4 ZZY |
626 | |
627 | ret = rtw_fwcd_prep(rtwdev); | |
628 | if (ret) | |
629 | goto free; | |
630 | ret = rtw_fw_dump_crash_log(rtwdev); | |
631 | if (ret) | |
632 | goto free; | |
633 | ret = rtw_chip_dump_fw_crash(rtwdev); | |
634 | if (ret) | |
635 | goto free; | |
636 | ||
637 | rtw_fwcd_dump(rtwdev); | |
638 | free: | |
639 | rtw_fwcd_free(rtwdev, !!ret); | |
640 | rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); | |
5c831644 | 641 | |
13ce240a | 642 | WARN(1, "firmware crash, start reset and recover\n"); |
5c831644 | 643 | |
5c831644 TEH |
644 | rcu_read_lock(); |
645 | rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); | |
646 | rcu_read_unlock(); | |
647 | rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); | |
648 | rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); | |
f0e741e4 | 649 | bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM); |
5c831644 | 650 | rtw_enter_ips(rtwdev); |
13ce240a ZZY |
651 | } |
652 | ||
653 | static void rtw_fw_recovery_work(struct work_struct *work) | |
654 | { | |
655 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, | |
656 | fw_recovery_work); | |
5c831644 | 657 | |
13ce240a ZZY |
658 | mutex_lock(&rtwdev->mutex); |
659 | __fw_recovery_work(rtwdev); | |
5c831644 TEH |
660 | mutex_unlock(&rtwdev->mutex); |
661 | ||
662 | ieee80211_restart_hw(rtwdev->hw); | |
663 | } | |
664 | ||
46ebb174 YHC |
665 | struct rtw_txq_ba_iter_data { |
666 | }; | |
667 | ||
668 | static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) | |
669 | { | |
670 | struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; | |
671 | int ret; | |
672 | u8 tid; | |
673 | ||
674 | tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); | |
675 | while (tid != IEEE80211_NUM_TIDS) { | |
676 | clear_bit(tid, si->tid_ba); | |
677 | ret = ieee80211_start_tx_ba_session(sta, tid, 0); | |
678 | if (ret == -EINVAL) { | |
679 | struct ieee80211_txq *txq; | |
680 | struct rtw_txq *rtwtxq; | |
681 | ||
682 | txq = sta->txq[tid]; | |
683 | rtwtxq = (struct rtw_txq *)txq->drv_priv; | |
684 | set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); | |
685 | } | |
686 | ||
687 | tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); | |
688 | } | |
689 | } | |
690 | ||
691 | static void rtw_txq_ba_work(struct work_struct *work) | |
692 | { | |
693 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); | |
694 | struct rtw_txq_ba_iter_data data; | |
695 | ||
696 | rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); | |
697 | } | |
698 | ||
10d162b2 PHH |
699 | void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) |
700 | { | |
701 | if (IS_CH_2G_BAND(channel)) | |
702 | pkt_stat->band = NL80211_BAND_2GHZ; | |
703 | else if (IS_CH_5G_BAND(channel)) | |
704 | pkt_stat->band = NL80211_BAND_5GHZ; | |
705 | else | |
706 | return; | |
707 | ||
708 | pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); | |
709 | } | |
710 | EXPORT_SYMBOL(rtw_set_rx_freq_band); | |
711 | ||
f2217968 PHH |
712 | void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) |
713 | { | |
714 | rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); | |
715 | rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); | |
716 | } | |
717 | ||
341dd1f7 CKC |
718 | void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, |
719 | u8 primary_channel, enum rtw_supported_band band, | |
720 | enum rtw_bandwidth bandwidth) | |
721 | { | |
722 | enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band); | |
723 | struct rtw_hal *hal = &rtwdev->hal; | |
724 | u8 *cch_by_bw = hal->cch_by_bw; | |
725 | u32 center_freq, primary_freq; | |
726 | enum rtw_sar_bands sar_band; | |
727 | u8 primary_channel_idx; | |
728 | ||
729 | center_freq = ieee80211_channel_to_frequency(center_channel, nl_band); | |
730 | primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band); | |
731 | ||
732 | /* assign the center channel used while 20M bw is selected */ | |
733 | cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel; | |
734 | ||
735 | /* assign the center channel used while current bw is selected */ | |
736 | cch_by_bw[bandwidth] = center_channel; | |
737 | ||
738 | switch (bandwidth) { | |
739 | case RTW_CHANNEL_WIDTH_20: | |
4ffb4d25 | 740 | default: |
341dd1f7 CKC |
741 | primary_channel_idx = RTW_SC_DONT_CARE; |
742 | break; | |
743 | case RTW_CHANNEL_WIDTH_40: | |
744 | if (primary_freq > center_freq) | |
745 | primary_channel_idx = RTW_SC_20_UPPER; | |
746 | else | |
747 | primary_channel_idx = RTW_SC_20_LOWER; | |
748 | break; | |
749 | case RTW_CHANNEL_WIDTH_80: | |
750 | if (primary_freq > center_freq) { | |
751 | if (primary_freq - center_freq == 10) | |
752 | primary_channel_idx = RTW_SC_20_UPPER; | |
753 | else | |
754 | primary_channel_idx = RTW_SC_20_UPMOST; | |
755 | ||
756 | /* assign the center channel used | |
757 | * while 40M bw is selected | |
758 | */ | |
759 | cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4; | |
760 | } else { | |
761 | if (center_freq - primary_freq == 10) | |
762 | primary_channel_idx = RTW_SC_20_LOWER; | |
763 | else | |
764 | primary_channel_idx = RTW_SC_20_LOWEST; | |
765 | ||
766 | /* assign the center channel used | |
767 | * while 40M bw is selected | |
768 | */ | |
769 | cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4; | |
770 | } | |
771 | break; | |
341dd1f7 CKC |
772 | } |
773 | ||
774 | switch (center_channel) { | |
775 | case 1 ... 14: | |
776 | sar_band = RTW_SAR_BAND_0; | |
777 | break; | |
778 | case 36 ... 64: | |
779 | sar_band = RTW_SAR_BAND_1; | |
780 | break; | |
781 | case 100 ... 144: | |
782 | sar_band = RTW_SAR_BAND_3; | |
783 | break; | |
784 | case 149 ... 177: | |
785 | sar_band = RTW_SAR_BAND_4; | |
786 | break; | |
787 | default: | |
788 | WARN(1, "unknown ch(%u) to SAR band\n", center_channel); | |
789 | sar_band = RTW_SAR_BAND_0; | |
790 | break; | |
791 | } | |
792 | ||
793 | hal->current_primary_channel_index = primary_channel_idx; | |
794 | hal->current_band_width = bandwidth; | |
795 | hal->primary_channel = primary_channel; | |
796 | hal->current_channel = center_channel; | |
797 | hal->current_band_type = band; | |
798 | hal->sar_band = sar_band; | |
799 | } | |
800 | ||
e3037485 YHC |
801 | void rtw_get_channel_params(struct cfg80211_chan_def *chandef, |
802 | struct rtw_channel_params *chan_params) | |
803 | { | |
804 | struct ieee80211_channel *channel = chandef->chan; | |
805 | enum nl80211_chan_width width = chandef->width; | |
806 | u32 primary_freq, center_freq; | |
807 | u8 center_chan; | |
808 | u8 bandwidth = RTW_CHANNEL_WIDTH_20; | |
e3037485 YHC |
809 | |
810 | center_chan = channel->hw_value; | |
811 | primary_freq = channel->center_freq; | |
812 | center_freq = chandef->center_freq1; | |
813 | ||
814 | switch (width) { | |
815 | case NL80211_CHAN_WIDTH_20_NOHT: | |
816 | case NL80211_CHAN_WIDTH_20: | |
817 | bandwidth = RTW_CHANNEL_WIDTH_20; | |
e3037485 YHC |
818 | break; |
819 | case NL80211_CHAN_WIDTH_40: | |
820 | bandwidth = RTW_CHANNEL_WIDTH_40; | |
341dd1f7 | 821 | if (primary_freq > center_freq) |
e3037485 | 822 | center_chan -= 2; |
341dd1f7 | 823 | else |
e3037485 | 824 | center_chan += 2; |
e3037485 YHC |
825 | break; |
826 | case NL80211_CHAN_WIDTH_80: | |
827 | bandwidth = RTW_CHANNEL_WIDTH_80; | |
828 | if (primary_freq > center_freq) { | |
341dd1f7 | 829 | if (primary_freq - center_freq == 10) |
e3037485 | 830 | center_chan -= 2; |
341dd1f7 | 831 | else |
e3037485 | 832 | center_chan -= 6; |
e3037485 | 833 | } else { |
341dd1f7 | 834 | if (center_freq - primary_freq == 10) |
e3037485 | 835 | center_chan += 2; |
341dd1f7 | 836 | else |
e3037485 | 837 | center_chan += 6; |
e3037485 YHC |
838 | } |
839 | break; | |
840 | default: | |
841 | center_chan = 0; | |
842 | break; | |
843 | } | |
844 | ||
845 | chan_params->center_chan = center_chan; | |
846 | chan_params->bandwidth = bandwidth; | |
341dd1f7 | 847 | chan_params->primary_chan = channel->hw_value; |
e3037485 YHC |
848 | } |
849 | ||
850 | void rtw_set_channel(struct rtw_dev *rtwdev) | |
851 | { | |
dcbf179c | 852 | const struct rtw_chip_info *chip = rtwdev->chip; |
e3037485 YHC |
853 | struct ieee80211_hw *hw = rtwdev->hw; |
854 | struct rtw_hal *hal = &rtwdev->hal; | |
e3037485 | 855 | struct rtw_channel_params ch_param; |
341dd1f7 | 856 | u8 center_chan, primary_chan, bandwidth, band; |
e3037485 YHC |
857 | |
858 | rtw_get_channel_params(&hw->conf.chandef, &ch_param); | |
859 | if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) | |
860 | return; | |
861 | ||
862 | center_chan = ch_param.center_chan; | |
341dd1f7 | 863 | primary_chan = ch_param.primary_chan; |
e3037485 | 864 | bandwidth = ch_param.bandwidth; |
341dd1f7 | 865 | band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; |
8704d0be | 866 | |
341dd1f7 | 867 | rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth); |
93f68a86 | 868 | |
96fbb84d PHH |
869 | if (rtwdev->scan_info.op_chan) |
870 | rtw_store_op_chan(rtwdev, true); | |
871 | ||
341dd1f7 CKC |
872 | chip->ops->set_channel(rtwdev, center_chan, bandwidth, |
873 | hal->current_primary_channel_index); | |
e3037485 | 874 | |
4136214f YHC |
875 | if (hal->current_band_type == RTW_BAND_5G) { |
876 | rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); | |
877 | } else { | |
3c519605 | 878 | if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) |
4136214f YHC |
879 | rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); |
880 | else | |
881 | rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); | |
882 | } | |
883 | ||
e3037485 | 884 | rtw_phy_set_tx_power_level(rtwdev, center_chan); |
7a242fb6 PKS |
885 | |
886 | /* if the channel isn't set for scanning, we will do RF calibration | |
887 | * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration | |
888 | * during scanning on each channel takes too long. | |
889 | */ | |
890 | if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) | |
891 | rtwdev->need_rfk = true; | |
892 | } | |
893 | ||
894 | void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) | |
895 | { | |
dcbf179c | 896 | const struct rtw_chip_info *chip = rtwdev->chip; |
7a242fb6 PKS |
897 | |
898 | if (rtwdev->need_rfk) { | |
899 | rtwdev->need_rfk = false; | |
900 | chip->ops->phy_calibration(rtwdev); | |
901 | } | |
e3037485 YHC |
902 | } |
903 | ||
904 | static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) | |
905 | { | |
906 | int i; | |
907 | ||
908 | for (i = 0; i < ETH_ALEN; i++) | |
909 | rtw_write8(rtwdev, start + i, addr[i]); | |
910 | } | |
911 | ||
912 | void rtw_vif_port_config(struct rtw_dev *rtwdev, | |
913 | struct rtw_vif *rtwvif, | |
914 | u32 config) | |
915 | { | |
916 | u32 addr, mask; | |
917 | ||
918 | if (config & PORT_SET_MAC_ADDR) { | |
919 | addr = rtwvif->conf->mac_addr.addr; | |
920 | rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); | |
921 | } | |
922 | if (config & PORT_SET_BSSID) { | |
923 | addr = rtwvif->conf->bssid.addr; | |
924 | rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); | |
925 | } | |
926 | if (config & PORT_SET_NET_TYPE) { | |
927 | addr = rtwvif->conf->net_type.addr; | |
928 | mask = rtwvif->conf->net_type.mask; | |
929 | rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); | |
930 | } | |
931 | if (config & PORT_SET_AID) { | |
932 | addr = rtwvif->conf->aid.addr; | |
933 | mask = rtwvif->conf->aid.mask; | |
934 | rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); | |
935 | } | |
6fabdc4a CYL |
936 | if (config & PORT_SET_BCN_CTRL) { |
937 | addr = rtwvif->conf->bcn_ctrl.addr; | |
938 | mask = rtwvif->conf->bcn_ctrl.mask; | |
939 | rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); | |
940 | } | |
e3037485 YHC |
941 | } |
942 | ||
943 | static u8 hw_bw_cap_to_bitamp(u8 bw_cap) | |
944 | { | |
945 | u8 bw = 0; | |
946 | ||
947 | switch (bw_cap) { | |
948 | case EFUSE_HW_CAP_IGNORE: | |
949 | case EFUSE_HW_CAP_SUPP_BW80: | |
950 | bw |= BIT(RTW_CHANNEL_WIDTH_80); | |
5466aff8 | 951 | fallthrough; |
e3037485 YHC |
952 | case EFUSE_HW_CAP_SUPP_BW40: |
953 | bw |= BIT(RTW_CHANNEL_WIDTH_40); | |
5466aff8 | 954 | fallthrough; |
e3037485 YHC |
955 | default: |
956 | bw |= BIT(RTW_CHANNEL_WIDTH_20); | |
957 | break; | |
958 | } | |
959 | ||
960 | return bw; | |
961 | } | |
962 | ||
963 | static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) | |
964 | { | |
dcbf179c | 965 | const struct rtw_chip_info *chip = rtwdev->chip; |
e3037485 YHC |
966 | struct rtw_hal *hal = &rtwdev->hal; |
967 | ||
968 | if (hw_ant_num == EFUSE_HW_CAP_IGNORE || | |
969 | hw_ant_num >= hal->rf_path_num) | |
970 | return; | |
971 | ||
972 | switch (hw_ant_num) { | |
973 | case 1: | |
974 | hal->rf_type = RF_1T1R; | |
975 | hal->rf_path_num = 1; | |
e0c27cdb PKS |
976 | if (!chip->fix_rf_phy_num) |
977 | hal->rf_phy_num = hal->rf_path_num; | |
e3037485 YHC |
978 | hal->antenna_tx = BB_PATH_A; |
979 | hal->antenna_rx = BB_PATH_A; | |
980 | break; | |
981 | default: | |
982 | WARN(1, "invalid hw configuration from efuse\n"); | |
983 | break; | |
984 | } | |
985 | } | |
986 | ||
987 | static u64 get_vht_ra_mask(struct ieee80211_sta *sta) | |
988 | { | |
989 | u64 ra_mask = 0; | |
046d2e7c | 990 | u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); |
e3037485 YHC |
991 | u8 vht_mcs_cap; |
992 | int i, nss; | |
993 | ||
994 | /* 4SS, every two bits for MCS7/8/9 */ | |
995 | for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { | |
996 | vht_mcs_cap = mcs_map & 0x3; | |
997 | switch (vht_mcs_cap) { | |
998 | case 2: /* MCS9 */ | |
b85bd9a1 | 999 | ra_mask |= 0x3ffULL << nss; |
e3037485 YHC |
1000 | break; |
1001 | case 1: /* MCS8 */ | |
b85bd9a1 | 1002 | ra_mask |= 0x1ffULL << nss; |
e3037485 YHC |
1003 | break; |
1004 | case 0: /* MCS7 */ | |
b85bd9a1 | 1005 | ra_mask |= 0x0ffULL << nss; |
e3037485 YHC |
1006 | break; |
1007 | default: | |
1008 | break; | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | return ra_mask; | |
1013 | } | |
1014 | ||
1015 | static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) | |
1016 | { | |
1017 | u8 rate_id = 0; | |
1018 | ||
1019 | switch (wireless_set) { | |
1020 | case WIRELESS_CCK: | |
1021 | rate_id = RTW_RATEID_B_20M; | |
1022 | break; | |
1023 | case WIRELESS_OFDM: | |
1024 | rate_id = RTW_RATEID_G; | |
1025 | break; | |
1026 | case WIRELESS_CCK | WIRELESS_OFDM: | |
1027 | rate_id = RTW_RATEID_BG; | |
1028 | break; | |
1029 | case WIRELESS_OFDM | WIRELESS_HT: | |
1030 | if (tx_num == 1) | |
1031 | rate_id = RTW_RATEID_GN_N1SS; | |
1032 | else if (tx_num == 2) | |
1033 | rate_id = RTW_RATEID_GN_N2SS; | |
1034 | else if (tx_num == 3) | |
1035 | rate_id = RTW_RATEID_ARFR5_N_3SS; | |
1036 | break; | |
1037 | case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: | |
1038 | if (bw_mode == RTW_CHANNEL_WIDTH_40) { | |
1039 | if (tx_num == 1) | |
1040 | rate_id = RTW_RATEID_BGN_40M_1SS; | |
1041 | else if (tx_num == 2) | |
1042 | rate_id = RTW_RATEID_BGN_40M_2SS; | |
1043 | else if (tx_num == 3) | |
1044 | rate_id = RTW_RATEID_ARFR5_N_3SS; | |
1045 | else if (tx_num == 4) | |
1046 | rate_id = RTW_RATEID_ARFR7_N_4SS; | |
1047 | } else { | |
1048 | if (tx_num == 1) | |
1049 | rate_id = RTW_RATEID_BGN_20M_1SS; | |
1050 | else if (tx_num == 2) | |
1051 | rate_id = RTW_RATEID_BGN_20M_2SS; | |
1052 | else if (tx_num == 3) | |
1053 | rate_id = RTW_RATEID_ARFR5_N_3SS; | |
1054 | else if (tx_num == 4) | |
1055 | rate_id = RTW_RATEID_ARFR7_N_4SS; | |
1056 | } | |
1057 | break; | |
1058 | case WIRELESS_OFDM | WIRELESS_VHT: | |
1059 | if (tx_num == 1) | |
1060 | rate_id = RTW_RATEID_ARFR1_AC_1SS; | |
1061 | else if (tx_num == 2) | |
1062 | rate_id = RTW_RATEID_ARFR0_AC_2SS; | |
1063 | else if (tx_num == 3) | |
1064 | rate_id = RTW_RATEID_ARFR4_AC_3SS; | |
1065 | else if (tx_num == 4) | |
1066 | rate_id = RTW_RATEID_ARFR6_AC_4SS; | |
1067 | break; | |
1068 | case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: | |
1069 | if (bw_mode >= RTW_CHANNEL_WIDTH_80) { | |
1070 | if (tx_num == 1) | |
1071 | rate_id = RTW_RATEID_ARFR1_AC_1SS; | |
1072 | else if (tx_num == 2) | |
1073 | rate_id = RTW_RATEID_ARFR0_AC_2SS; | |
1074 | else if (tx_num == 3) | |
1075 | rate_id = RTW_RATEID_ARFR4_AC_3SS; | |
1076 | else if (tx_num == 4) | |
1077 | rate_id = RTW_RATEID_ARFR6_AC_4SS; | |
1078 | } else { | |
1079 | if (tx_num == 1) | |
1080 | rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; | |
1081 | else if (tx_num == 2) | |
1082 | rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; | |
1083 | else if (tx_num == 3) | |
1084 | rate_id = RTW_RATEID_ARFR4_AC_3SS; | |
1085 | else if (tx_num == 4) | |
1086 | rate_id = RTW_RATEID_ARFR6_AC_4SS; | |
1087 | } | |
1088 | break; | |
1089 | default: | |
1090 | break; | |
1091 | } | |
1092 | ||
1093 | return rate_id; | |
1094 | } | |
1095 | ||
1096 | #define RA_MASK_CCK_RATES 0x0000f | |
1097 | #define RA_MASK_OFDM_RATES 0x00ff0 | |
237b47ef NC |
1098 | #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) |
1099 | #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) | |
1100 | #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) | |
e3037485 YHC |
1101 | #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ |
1102 | RA_MASK_HT_RATES_2SS | \ | |
1103 | RA_MASK_HT_RATES_3SS) | |
237b47ef NC |
1104 | #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) |
1105 | #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) | |
1106 | #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) | |
e3037485 YHC |
1107 | #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ |
1108 | RA_MASK_VHT_RATES_2SS | \ | |
1109 | RA_MASK_VHT_RATES_3SS) | |
9eb071f8 | 1110 | #define RA_MASK_CCK_IN_BG 0x00005 |
e3037485 YHC |
1111 | #define RA_MASK_CCK_IN_HT 0x00005 |
1112 | #define RA_MASK_CCK_IN_VHT 0x00005 | |
1113 | #define RA_MASK_OFDM_IN_VHT 0x00010 | |
1114 | #define RA_MASK_OFDM_IN_HT_2G 0x00010 | |
1115 | #define RA_MASK_OFDM_IN_HT_5G 0x00030 | |
1116 | ||
9eb071f8 CHL |
1117 | static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) |
1118 | { | |
1119 | u8 rssi_level = si->rssi_level; | |
1120 | ||
1121 | if (wireless_set == WIRELESS_CCK) | |
1122 | return 0xffffffffffffffffULL; | |
1123 | ||
1124 | if (rssi_level == 0) | |
1125 | return 0xffffffffffffffffULL; | |
1126 | else if (rssi_level == 1) | |
1127 | return 0xfffffffffffffff0ULL; | |
1128 | else if (rssi_level == 2) | |
1129 | return 0xffffffffffffefe0ULL; | |
1130 | else if (rssi_level == 3) | |
1131 | return 0xffffffffffffcfc0ULL; | |
1132 | else if (rssi_level == 4) | |
1133 | return 0xffffffffffff8f80ULL; | |
1134 | else | |
1135 | return 0xffffffffffff0f00ULL; | |
1136 | } | |
1137 | ||
1138 | static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) | |
1139 | { | |
1140 | if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) | |
1141 | ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); | |
1142 | ||
1143 | if (ra_mask == 0) | |
1144 | ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); | |
1145 | ||
1146 | return ra_mask; | |
1147 | } | |
1148 | ||
1149 | static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, | |
1150 | u64 ra_mask, bool is_vht_enable) | |
f39e9bd4 TEH |
1151 | { |
1152 | struct rtw_hal *hal = &rtwdev->hal; | |
1153 | const struct cfg80211_bitrate_mask *mask = si->mask; | |
5c70e971 | 1154 | u64 cfg_mask = GENMASK_ULL(63, 0); |
9eb071f8 | 1155 | u8 band; |
f39e9bd4 TEH |
1156 | |
1157 | if (!si->use_cfg_mask) | |
1158 | return ra_mask; | |
1159 | ||
1160 | band = hal->current_band_type; | |
1161 | if (band == RTW_BAND_2G) { | |
1162 | band = NL80211_BAND_2GHZ; | |
1163 | cfg_mask = mask->control[band].legacy; | |
1164 | } else if (band == RTW_BAND_5G) { | |
1165 | band = NL80211_BAND_5GHZ; | |
1166 | cfg_mask = u64_encode_bits(mask->control[band].legacy, | |
1167 | RA_MASK_OFDM_RATES); | |
1168 | } | |
1169 | ||
1170 | if (!is_vht_enable) { | |
1171 | if (ra_mask & RA_MASK_HT_RATES_1SS) | |
1172 | cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], | |
1173 | RA_MASK_HT_RATES_1SS); | |
1174 | if (ra_mask & RA_MASK_HT_RATES_2SS) | |
1175 | cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], | |
1176 | RA_MASK_HT_RATES_2SS); | |
1177 | } else { | |
1178 | if (ra_mask & RA_MASK_VHT_RATES_1SS) | |
1179 | cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], | |
1180 | RA_MASK_VHT_RATES_1SS); | |
1181 | if (ra_mask & RA_MASK_VHT_RATES_2SS) | |
1182 | cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], | |
1183 | RA_MASK_VHT_RATES_2SS); | |
1184 | } | |
1185 | ||
1186 | ra_mask &= cfg_mask; | |
1187 | ||
1188 | return ra_mask; | |
1189 | } | |
1190 | ||
c1edc864 PHH |
1191 | void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, |
1192 | bool reset_ra_mask) | |
e3037485 | 1193 | { |
48308726 | 1194 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; |
e3037485 YHC |
1195 | struct ieee80211_sta *sta = si->sta; |
1196 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
1197 | struct rtw_hal *hal = &rtwdev->hal; | |
e3037485 YHC |
1198 | u8 wireless_set; |
1199 | u8 bw_mode; | |
1200 | u8 rate_id; | |
1201 | u8 rf_type = RF_1T1R; | |
1202 | u8 stbc_en = 0; | |
1203 | u8 ldpc_en = 0; | |
1204 | u8 tx_num = 1; | |
1205 | u64 ra_mask = 0; | |
9eb071f8 | 1206 | u64 ra_mask_bak = 0; |
e3037485 YHC |
1207 | bool is_vht_enable = false; |
1208 | bool is_support_sgi = false; | |
1209 | ||
046d2e7c | 1210 | if (sta->deflink.vht_cap.vht_supported) { |
e3037485 YHC |
1211 | is_vht_enable = true; |
1212 | ra_mask |= get_vht_ra_mask(sta); | |
046d2e7c | 1213 | if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) |
e3037485 | 1214 | stbc_en = VHT_STBC_EN; |
046d2e7c | 1215 | if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) |
e3037485 | 1216 | ldpc_en = VHT_LDPC_EN; |
046d2e7c S |
1217 | } else if (sta->deflink.ht_cap.ht_supported) { |
1218 | ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | | |
1219 | (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); | |
1220 | if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) | |
e3037485 | 1221 | stbc_en = HT_STBC_EN; |
046d2e7c | 1222 | if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) |
e3037485 | 1223 | ldpc_en = HT_LDPC_EN; |
e3037485 YHC |
1224 | } |
1225 | ||
04e00ac9 | 1226 | if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) |
35a68fa5 PKS |
1227 | ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; |
1228 | ||
e3037485 | 1229 | if (hal->current_band_type == RTW_BAND_5G) { |
046d2e7c | 1230 | ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; |
9eb071f8 | 1231 | ra_mask_bak = ra_mask; |
046d2e7c | 1232 | if (sta->deflink.vht_cap.vht_supported) { |
e3037485 YHC |
1233 | ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; |
1234 | wireless_set = WIRELESS_OFDM | WIRELESS_VHT; | |
046d2e7c | 1235 | } else if (sta->deflink.ht_cap.ht_supported) { |
e3037485 YHC |
1236 | ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; |
1237 | wireless_set = WIRELESS_OFDM | WIRELESS_HT; | |
1238 | } else { | |
1239 | wireless_set = WIRELESS_OFDM; | |
1240 | } | |
48308726 | 1241 | dm_info->rrsr_val_init = RRSR_INIT_5G; |
e3037485 | 1242 | } else if (hal->current_band_type == RTW_BAND_2G) { |
046d2e7c | 1243 | ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; |
9eb071f8 | 1244 | ra_mask_bak = ra_mask; |
046d2e7c | 1245 | if (sta->deflink.vht_cap.vht_supported) { |
e3037485 YHC |
1246 | ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | |
1247 | RA_MASK_OFDM_IN_VHT; | |
1248 | wireless_set = WIRELESS_CCK | WIRELESS_OFDM | | |
1249 | WIRELESS_HT | WIRELESS_VHT; | |
046d2e7c | 1250 | } else if (sta->deflink.ht_cap.ht_supported) { |
e3037485 YHC |
1251 | ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | |
1252 | RA_MASK_OFDM_IN_HT_2G; | |
1253 | wireless_set = WIRELESS_CCK | WIRELESS_OFDM | | |
1254 | WIRELESS_HT; | |
046d2e7c | 1255 | } else if (sta->deflink.supp_rates[0] <= 0xf) { |
e3037485 YHC |
1256 | wireless_set = WIRELESS_CCK; |
1257 | } else { | |
9eb071f8 | 1258 | ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; |
e3037485 YHC |
1259 | wireless_set = WIRELESS_CCK | WIRELESS_OFDM; |
1260 | } | |
48308726 | 1261 | dm_info->rrsr_val_init = RRSR_INIT_2G; |
e3037485 YHC |
1262 | } else { |
1263 | rtw_err(rtwdev, "Unknown band type\n"); | |
9eb071f8 | 1264 | ra_mask_bak = ra_mask; |
e3037485 YHC |
1265 | wireless_set = 0; |
1266 | } | |
1267 | ||
046d2e7c | 1268 | switch (sta->deflink.bandwidth) { |
e3037485 YHC |
1269 | case IEEE80211_STA_RX_BW_80: |
1270 | bw_mode = RTW_CHANNEL_WIDTH_80; | |
046d2e7c S |
1271 | is_support_sgi = sta->deflink.vht_cap.vht_supported && |
1272 | (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); | |
e3037485 YHC |
1273 | break; |
1274 | case IEEE80211_STA_RX_BW_40: | |
1275 | bw_mode = RTW_CHANNEL_WIDTH_40; | |
046d2e7c S |
1276 | is_support_sgi = sta->deflink.ht_cap.ht_supported && |
1277 | (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); | |
e3037485 YHC |
1278 | break; |
1279 | default: | |
1280 | bw_mode = RTW_CHANNEL_WIDTH_20; | |
046d2e7c S |
1281 | is_support_sgi = sta->deflink.ht_cap.ht_supported && |
1282 | (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); | |
e3037485 YHC |
1283 | break; |
1284 | } | |
1285 | ||
046d2e7c | 1286 | if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { |
e3037485 YHC |
1287 | tx_num = 2; |
1288 | rf_type = RF_2T2R; | |
046d2e7c | 1289 | } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { |
e3037485 YHC |
1290 | tx_num = 2; |
1291 | rf_type = RF_2T2R; | |
1292 | } | |
1293 | ||
1294 | rate_id = get_rate_id(wireless_set, bw_mode, tx_num); | |
1295 | ||
9eb071f8 CHL |
1296 | ra_mask &= rtw_rate_mask_rssi(si, wireless_set); |
1297 | ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); | |
1298 | ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); | |
e3037485 YHC |
1299 | |
1300 | si->bw_mode = bw_mode; | |
1301 | si->stbc_en = stbc_en; | |
1302 | si->ldpc_en = ldpc_en; | |
1303 | si->rf_type = rf_type; | |
e3037485 YHC |
1304 | si->sgi_enable = is_support_sgi; |
1305 | si->vht_enable = is_vht_enable; | |
1306 | si->ra_mask = ra_mask; | |
1307 | si->rate_id = rate_id; | |
1308 | ||
c1edc864 | 1309 | rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); |
e3037485 YHC |
1310 | } |
1311 | ||
c8e5695e CYL |
1312 | static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) |
1313 | { | |
dcbf179c | 1314 | const struct rtw_chip_info *chip = rtwdev->chip; |
c8e5695e | 1315 | struct rtw_fw_state *fw; |
0e735a4c | 1316 | int ret = 0; |
c8e5695e CYL |
1317 | |
1318 | fw = &rtwdev->fw; | |
1319 | wait_for_completion(&fw->completion); | |
1320 | if (!fw->firmware) | |
0e735a4c | 1321 | ret = -EINVAL; |
c8e5695e CYL |
1322 | |
1323 | if (chip->wow_fw_name) { | |
1324 | fw = &rtwdev->wow_fw; | |
1325 | wait_for_completion(&fw->completion); | |
1326 | if (!fw->firmware) | |
0e735a4c | 1327 | ret = -EINVAL; |
c8e5695e CYL |
1328 | } |
1329 | ||
0e735a4c | 1330 | return ret; |
c8e5695e CYL |
1331 | } |
1332 | ||
fc3ac64a CYL |
1333 | static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, |
1334 | struct rtw_fw_state *fw) | |
1335 | { | |
dcbf179c | 1336 | const struct rtw_chip_info *chip = rtwdev->chip; |
fc3ac64a CYL |
1337 | |
1338 | if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || | |
1339 | !fw->feature) | |
1340 | return LPS_DEEP_MODE_NONE; | |
1341 | ||
1342 | if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && | |
9a711831 | 1343 | rtw_fw_feature_check(fw, FW_FEATURE_PG)) |
fc3ac64a CYL |
1344 | return LPS_DEEP_MODE_PG; |
1345 | ||
1346 | if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && | |
9a711831 | 1347 | rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) |
fc3ac64a CYL |
1348 | return LPS_DEEP_MODE_LCLK; |
1349 | ||
1350 | return LPS_DEEP_MODE_NONE; | |
1351 | } | |
1352 | ||
e3037485 YHC |
1353 | static int rtw_power_on(struct rtw_dev *rtwdev) |
1354 | { | |
dcbf179c | 1355 | const struct rtw_chip_info *chip = rtwdev->chip; |
e3037485 | 1356 | struct rtw_fw_state *fw = &rtwdev->fw; |
4136214f | 1357 | bool wifi_only; |
e3037485 YHC |
1358 | int ret; |
1359 | ||
1360 | ret = rtw_hci_setup(rtwdev); | |
1361 | if (ret) { | |
1362 | rtw_err(rtwdev, "failed to setup hci\n"); | |
1363 | goto err; | |
1364 | } | |
1365 | ||
1366 | /* power on MAC before firmware downloaded */ | |
1367 | ret = rtw_mac_power_on(rtwdev); | |
1368 | if (ret) { | |
1369 | rtw_err(rtwdev, "failed to power on mac\n"); | |
1370 | goto err; | |
1371 | } | |
1372 | ||
c8e5695e CYL |
1373 | ret = rtw_wait_firmware_completion(rtwdev); |
1374 | if (ret) { | |
1375 | rtw_err(rtwdev, "failed to wait firmware completion\n"); | |
1376 | goto err_off; | |
e3037485 YHC |
1377 | } |
1378 | ||
1379 | ret = rtw_download_firmware(rtwdev, fw); | |
1380 | if (ret) { | |
1381 | rtw_err(rtwdev, "failed to download firmware\n"); | |
1382 | goto err_off; | |
1383 | } | |
1384 | ||
1385 | /* config mac after firmware downloaded */ | |
1386 | ret = rtw_mac_init(rtwdev); | |
1387 | if (ret) { | |
1388 | rtw_err(rtwdev, "failed to configure mac\n"); | |
1389 | goto err_off; | |
1390 | } | |
1391 | ||
1392 | chip->ops->phy_set_param(rtwdev); | |
1393 | ||
1394 | ret = rtw_hci_start(rtwdev); | |
1395 | if (ret) { | |
1396 | rtw_err(rtwdev, "failed to start hci\n"); | |
1397 | goto err_off; | |
1398 | } | |
1399 | ||
0b8dc6ab YHC |
1400 | /* send H2C after HCI has started */ |
1401 | rtw_fw_send_general_info(rtwdev); | |
1402 | rtw_fw_send_phydm_info(rtwdev); | |
1403 | ||
4136214f YHC |
1404 | wifi_only = !rtwdev->efuse.btcoex; |
1405 | rtw_coex_power_on_setting(rtwdev); | |
1406 | rtw_coex_init_hw_config(rtwdev, wifi_only); | |
1407 | ||
e3037485 YHC |
1408 | return 0; |
1409 | ||
1410 | err_off: | |
1411 | rtw_mac_power_off(rtwdev); | |
1412 | ||
1413 | err: | |
1414 | return ret; | |
1415 | } | |
1416 | ||
a853d234 CYL |
1417 | void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) |
1418 | { | |
1419 | if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) | |
1420 | return; | |
1421 | ||
1422 | if (start) { | |
1423 | rtw_fw_scan_notify(rtwdev, true); | |
1424 | } else { | |
1425 | reinit_completion(&rtwdev->fw_scan_density); | |
1426 | rtw_fw_scan_notify(rtwdev, false); | |
1427 | if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, | |
1428 | SCAN_NOTIFY_TIMEOUT)) | |
1429 | rtw_warn(rtwdev, "firmware failed to report density after scan\n"); | |
1430 | } | |
1431 | } | |
1432 | ||
10d162b2 PHH |
1433 | void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, |
1434 | const u8 *mac_addr, bool hw_scan) | |
1435 | { | |
1436 | u32 config = 0; | |
1437 | int ret = 0; | |
1438 | ||
1439 | rtw_leave_lps(rtwdev); | |
1440 | ||
29ed2d76 | 1441 | if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { |
10d162b2 PHH |
1442 | ret = rtw_leave_ips(rtwdev); |
1443 | if (ret) { | |
1444 | rtw_err(rtwdev, "failed to leave idle state\n"); | |
1445 | return; | |
1446 | } | |
1447 | } | |
1448 | ||
1449 | ether_addr_copy(rtwvif->mac_addr, mac_addr); | |
1450 | config |= PORT_SET_MAC_ADDR; | |
1451 | rtw_vif_port_config(rtwdev, rtwvif, config); | |
1452 | ||
1453 | rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); | |
1454 | rtw_core_fw_scan_notify(rtwdev, true); | |
1455 | ||
1456 | set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); | |
1457 | set_bit(RTW_FLAG_SCANNING, rtwdev->flags); | |
1458 | } | |
1459 | ||
c17f2716 PHH |
1460 | void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, |
1461 | bool hw_scan) | |
10d162b2 | 1462 | { |
32621eb6 | 1463 | struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; |
10d162b2 PHH |
1464 | u32 config = 0; |
1465 | ||
32621eb6 PHH |
1466 | if (!rtwvif) |
1467 | return; | |
1468 | ||
10d162b2 PHH |
1469 | clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); |
1470 | clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); | |
1471 | ||
1472 | rtw_core_fw_scan_notify(rtwdev, false); | |
1473 | ||
1474 | ether_addr_copy(rtwvif->mac_addr, vif->addr); | |
1475 | config |= PORT_SET_MAC_ADDR; | |
1476 | rtw_vif_port_config(rtwdev, rtwvif, config); | |
1477 | ||
1478 | rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); | |
c17f2716 | 1479 | |
29ed2d76 | 1480 | if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) |
c17f2716 | 1481 | ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); |
10d162b2 PHH |
1482 | } |
1483 | ||
e3037485 YHC |
1484 | int rtw_core_start(struct rtw_dev *rtwdev) |
1485 | { | |
1486 | int ret; | |
1487 | ||
1488 | ret = rtw_power_on(rtwdev); | |
1489 | if (ret) | |
1490 | return ret; | |
1491 | ||
1492 | rtw_sec_enable_sec_engine(rtwdev); | |
1493 | ||
fc3ac64a CYL |
1494 | rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); |
1495 | rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); | |
1496 | ||
e3037485 YHC |
1497 | /* rcr reset after powered on */ |
1498 | rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); | |
1499 | ||
1500 | ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, | |
1501 | RTW_WATCH_DOG_DELAY_TIME); | |
1502 | ||
3c519605 | 1503 | set_bit(RTW_FLAG_RUNNING, rtwdev->flags); |
e3037485 YHC |
1504 | |
1505 | return 0; | |
1506 | } | |
1507 | ||
1508 | static void rtw_power_off(struct rtw_dev *rtwdev) | |
1509 | { | |
fc83c616 | 1510 | rtw_hci_stop(rtwdev); |
5b492c7d | 1511 | rtw_coex_power_off_setting(rtwdev); |
e3037485 YHC |
1512 | rtw_mac_power_off(rtwdev); |
1513 | } | |
1514 | ||
1515 | void rtw_core_stop(struct rtw_dev *rtwdev) | |
1516 | { | |
4136214f YHC |
1517 | struct rtw_coex *coex = &rtwdev->coex; |
1518 | ||
3c519605 YHC |
1519 | clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); |
1520 | clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); | |
e3037485 | 1521 | |
6eab0ba9 YHC |
1522 | mutex_unlock(&rtwdev->mutex); |
1523 | ||
1524 | cancel_work_sync(&rtwdev->c2h_work); | |
7711fe71 | 1525 | cancel_work_sync(&rtwdev->update_beacon_work); |
e3037485 | 1526 | cancel_delayed_work_sync(&rtwdev->watch_dog_work); |
4136214f YHC |
1527 | cancel_delayed_work_sync(&coex->bt_relink_work); |
1528 | cancel_delayed_work_sync(&coex->bt_reenable_work); | |
1529 | cancel_delayed_work_sync(&coex->defreeze_work); | |
001a3c90 ZZY |
1530 | cancel_delayed_work_sync(&coex->wl_remain_work); |
1531 | cancel_delayed_work_sync(&coex->bt_remain_work); | |
150ce8e3 | 1532 | cancel_delayed_work_sync(&coex->wl_connecting_work); |
8e6947dc CTK |
1533 | cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); |
1534 | cancel_delayed_work_sync(&coex->wl_ccklock_work); | |
e3037485 | 1535 | |
6eab0ba9 YHC |
1536 | mutex_lock(&rtwdev->mutex); |
1537 | ||
e3037485 YHC |
1538 | rtw_power_off(rtwdev); |
1539 | } | |
1540 | ||
1541 | static void rtw_init_ht_cap(struct rtw_dev *rtwdev, | |
1542 | struct ieee80211_sta_ht_cap *ht_cap) | |
1543 | { | |
dcbf179c | 1544 | const struct rtw_chip_info *chip = rtwdev->chip; |
e3037485 YHC |
1545 | struct rtw_efuse *efuse = &rtwdev->efuse; |
1546 | ||
1547 | ht_cap->ht_supported = true; | |
1548 | ht_cap->cap = 0; | |
1549 | ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | | |
1550 | IEEE80211_HT_CAP_MAX_AMSDU | | |
e3037485 | 1551 | (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); |
3ac14439 PKS |
1552 | |
1553 | if (rtw_chip_has_rx_ldpc(rtwdev)) | |
1554 | ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
81a68a14 PHH |
1555 | if (rtw_chip_has_tx_stbc(rtwdev)) |
1556 | ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; | |
3ac14439 | 1557 | |
e3037485 YHC |
1558 | if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) |
1559 | ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
1560 | IEEE80211_HT_CAP_DSSSCCK40 | | |
1561 | IEEE80211_HT_CAP_SGI_40; | |
1562 | ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; | |
1d6d131d | 1563 | ht_cap->ampdu_density = chip->ampdu_density; |
e3037485 YHC |
1564 | ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
1565 | if (efuse->hw_cap.nss > 1) { | |
1566 | ht_cap->mcs.rx_mask[0] = 0xFF; | |
1567 | ht_cap->mcs.rx_mask[1] = 0xFF; | |
1568 | ht_cap->mcs.rx_mask[4] = 0x01; | |
1569 | ht_cap->mcs.rx_highest = cpu_to_le16(300); | |
1570 | } else { | |
1571 | ht_cap->mcs.rx_mask[0] = 0xFF; | |
1572 | ht_cap->mcs.rx_mask[1] = 0x00; | |
1573 | ht_cap->mcs.rx_mask[4] = 0x01; | |
1574 | ht_cap->mcs.rx_highest = cpu_to_le16(150); | |
1575 | } | |
1576 | } | |
1577 | ||
1578 | static void rtw_init_vht_cap(struct rtw_dev *rtwdev, | |
1579 | struct ieee80211_sta_vht_cap *vht_cap) | |
1580 | { | |
1581 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
1582 | u16 mcs_map; | |
1583 | __le16 highest; | |
1584 | ||
1585 | if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && | |
1586 | efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) | |
1587 | return; | |
1588 | ||
1589 | vht_cap->vht_supported = true; | |
1590 | vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | | |
e3037485 | 1591 | IEEE80211_VHT_CAP_SHORT_GI_80 | |
e3037485 YHC |
1592 | IEEE80211_VHT_CAP_RXSTBC_1 | |
1593 | IEEE80211_VHT_CAP_HTC_VHT | | |
1594 | IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | | |
1595 | 0; | |
d47e7371 TEH |
1596 | if (rtwdev->hal.rf_path_num > 1) |
1597 | vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; | |
0bd95573 TEH |
1598 | vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | |
1599 | IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; | |
1600 | vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << | |
1601 | IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); | |
1602 | ||
3ac14439 PKS |
1603 | if (rtw_chip_has_rx_ldpc(rtwdev)) |
1604 | vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; | |
1605 | ||
e3037485 YHC |
1606 | mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | |
1607 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | | |
1608 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | | |
1609 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | | |
1610 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | | |
1611 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | | |
1612 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; | |
1613 | if (efuse->hw_cap.nss > 1) { | |
1614 | highest = cpu_to_le16(780); | |
1615 | mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; | |
1616 | } else { | |
1617 | highest = cpu_to_le16(390); | |
1618 | mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; | |
1619 | } | |
1620 | ||
1621 | vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); | |
1622 | vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); | |
1623 | vht_cap->vht_mcs.rx_highest = highest; | |
1624 | vht_cap->vht_mcs.tx_highest = highest; | |
1625 | } | |
1626 | ||
d2eb7cb9 PHH |
1627 | static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev) |
1628 | { | |
1629 | u16 len; | |
1630 | ||
1631 | len = rtwdev->chip->max_scan_ie_len; | |
1632 | ||
1633 | if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) && | |
1634 | rtwdev->chip->id == RTW_CHIP_TYPE_8822C) | |
1635 | len = IEEE80211_MAX_DATA_LEN; | |
1636 | else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM)) | |
1637 | len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE; | |
1638 | ||
1639 | return len; | |
1640 | } | |
1641 | ||
e3037485 | 1642 | static void rtw_set_supported_band(struct ieee80211_hw *hw, |
dcbf179c | 1643 | const struct rtw_chip_info *chip) |
e3037485 YHC |
1644 | { |
1645 | struct rtw_dev *rtwdev = hw->priv; | |
1646 | struct ieee80211_supported_band *sband; | |
1647 | ||
1648 | if (chip->band & RTW_BAND_2G) { | |
1649 | sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); | |
1650 | if (!sband) | |
1651 | goto err_out; | |
1652 | if (chip->ht_supported) | |
1653 | rtw_init_ht_cap(rtwdev, &sband->ht_cap); | |
1654 | hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; | |
1655 | } | |
1656 | ||
1657 | if (chip->band & RTW_BAND_5G) { | |
1658 | sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); | |
1659 | if (!sband) | |
1660 | goto err_out; | |
1661 | if (chip->ht_supported) | |
1662 | rtw_init_ht_cap(rtwdev, &sband->ht_cap); | |
1663 | if (chip->vht_supported) | |
1664 | rtw_init_vht_cap(rtwdev, &sband->vht_cap); | |
1665 | hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; | |
1666 | } | |
1667 | ||
1668 | return; | |
1669 | ||
1670 | err_out: | |
1671 | rtw_err(rtwdev, "failed to set supported band\n"); | |
e3037485 YHC |
1672 | } |
1673 | ||
1674 | static void rtw_unset_supported_band(struct ieee80211_hw *hw, | |
dcbf179c | 1675 | const struct rtw_chip_info *chip) |
e3037485 YHC |
1676 | { |
1677 | kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); | |
1678 | kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); | |
1679 | } | |
1680 | ||
04e00ac9 CYL |
1681 | static void rtw_vif_smps_iter(void *data, u8 *mac, |
1682 | struct ieee80211_vif *vif) | |
1683 | { | |
1684 | struct rtw_dev *rtwdev = (struct rtw_dev *)data; | |
1685 | ||
f276e20b | 1686 | if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) |
04e00ac9 CYL |
1687 | return; |
1688 | ||
1689 | if (rtwdev->hal.txrx_1ss) | |
e9aac179 | 1690 | ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC); |
04e00ac9 | 1691 | else |
e9aac179 | 1692 | ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF); |
04e00ac9 CYL |
1693 | } |
1694 | ||
1695 | void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) | |
1696 | { | |
dcbf179c | 1697 | const struct rtw_chip_info *chip = rtwdev->chip; |
04e00ac9 CYL |
1698 | struct rtw_hal *hal = &rtwdev->hal; |
1699 | ||
1700 | if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) | |
1701 | return; | |
1702 | ||
1703 | rtwdev->hal.txrx_1ss = txrx_1ss; | |
1704 | if (txrx_1ss) | |
1705 | chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); | |
1706 | else | |
1707 | chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, | |
1708 | hal->antenna_rx, false); | |
1709 | rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); | |
1710 | } | |
1711 | ||
a9594960 CYL |
1712 | static void __update_firmware_feature(struct rtw_dev *rtwdev, |
1713 | struct rtw_fw_state *fw) | |
1714 | { | |
1715 | u32 feature; | |
1716 | const struct rtw_fw_hdr *fw_hdr = | |
1717 | (const struct rtw_fw_hdr *)fw->firmware->data; | |
1718 | ||
1719 | feature = le32_to_cpu(fw_hdr->feature); | |
1720 | fw->feature = feature & FW_FEATURE_SIG ? feature : 0; | |
d2eb7cb9 PHH |
1721 | |
1722 | if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C && | |
1723 | RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13)) | |
1724 | fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM; | |
a9594960 CYL |
1725 | } |
1726 | ||
15d2fcc6 PKS |
1727 | static void __update_firmware_info(struct rtw_dev *rtwdev, |
1728 | struct rtw_fw_state *fw) | |
1729 | { | |
1730 | const struct rtw_fw_hdr *fw_hdr = | |
1731 | (const struct rtw_fw_hdr *)fw->firmware->data; | |
1732 | ||
1733 | fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); | |
1734 | fw->version = le16_to_cpu(fw_hdr->version); | |
1735 | fw->sub_version = fw_hdr->subversion; | |
1736 | fw->sub_index = fw_hdr->subindex; | |
a9594960 CYL |
1737 | |
1738 | __update_firmware_feature(rtwdev, fw); | |
15d2fcc6 PKS |
1739 | } |
1740 | ||
1741 | static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, | |
1742 | struct rtw_fw_state *fw) | |
1743 | { | |
1744 | struct rtw_fw_hdr_legacy *legacy = | |
1745 | (struct rtw_fw_hdr_legacy *)fw->firmware->data; | |
1746 | ||
1747 | fw->h2c_version = 0; | |
1748 | fw->version = le16_to_cpu(legacy->version); | |
1749 | fw->sub_version = legacy->subversion1; | |
1750 | fw->sub_index = legacy->subversion2; | |
1751 | } | |
1752 | ||
1753 | static void update_firmware_info(struct rtw_dev *rtwdev, | |
1754 | struct rtw_fw_state *fw) | |
1755 | { | |
1756 | if (rtw_chip_wcpu_11n(rtwdev)) | |
1757 | __update_firmware_info_legacy(rtwdev, fw); | |
1758 | else | |
1759 | __update_firmware_info(rtwdev, fw); | |
1760 | } | |
1761 | ||
e3037485 YHC |
1762 | static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) |
1763 | { | |
c8e5695e CYL |
1764 | struct rtw_fw_state *fw = context; |
1765 | struct rtw_dev *rtwdev = fw->rtwdev; | |
e3037485 | 1766 | |
f530c196 | 1767 | if (!firmware || !firmware->data) { |
e3037485 | 1768 | rtw_err(rtwdev, "failed to request firmware\n"); |
21c60a28 | 1769 | complete_all(&fw->completion); |
f530c196 YHC |
1770 | return; |
1771 | } | |
e3037485 YHC |
1772 | |
1773 | fw->firmware = firmware; | |
15d2fcc6 | 1774 | update_firmware_info(rtwdev, fw); |
e3037485 | 1775 | complete_all(&fw->completion); |
5195b904 | 1776 | |
1d896604 SH |
1777 | rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n", |
1778 | fw->type == RTW_WOWLAN_FW ? "WOW " : "", | |
5195b904 | 1779 | fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); |
e3037485 YHC |
1780 | } |
1781 | ||
c8e5695e | 1782 | static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) |
e3037485 | 1783 | { |
c8e5695e CYL |
1784 | const char *fw_name; |
1785 | struct rtw_fw_state *fw; | |
e3037485 YHC |
1786 | int ret; |
1787 | ||
c8e5695e CYL |
1788 | switch (type) { |
1789 | case RTW_WOWLAN_FW: | |
1790 | fw = &rtwdev->wow_fw; | |
1791 | fw_name = rtwdev->chip->wow_fw_name; | |
1792 | break; | |
1793 | ||
1794 | case RTW_NORMAL_FW: | |
1795 | fw = &rtwdev->fw; | |
1796 | fw_name = rtwdev->chip->fw_name; | |
1797 | break; | |
1798 | ||
1799 | default: | |
1800 | rtw_warn(rtwdev, "unsupported firmware type\n"); | |
1801 | return -ENOENT; | |
1802 | } | |
1803 | ||
1d896604 | 1804 | fw->type = type; |
c8e5695e | 1805 | fw->rtwdev = rtwdev; |
e3037485 YHC |
1806 | init_completion(&fw->completion); |
1807 | ||
1808 | ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, | |
c8e5695e | 1809 | GFP_KERNEL, fw, rtw_load_firmware_cb); |
e3037485 | 1810 | if (ret) { |
c8e5695e | 1811 | rtw_err(rtwdev, "failed to async firmware request\n"); |
e3037485 YHC |
1812 | return ret; |
1813 | } | |
1814 | ||
1815 | return 0; | |
1816 | } | |
1817 | ||
1818 | static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) | |
1819 | { | |
dcbf179c | 1820 | const struct rtw_chip_info *chip = rtwdev->chip; |
e3037485 YHC |
1821 | struct rtw_hal *hal = &rtwdev->hal; |
1822 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
e3037485 YHC |
1823 | |
1824 | switch (rtw_hci_type(rtwdev)) { | |
1825 | case RTW_HCI_TYPE_PCIE: | |
1826 | rtwdev->hci.rpwm_addr = 0x03d9; | |
27e117e4 | 1827 | rtwdev->hci.cpwm_addr = 0x03da; |
e3037485 | 1828 | break; |
a5d25f9f MB |
1829 | case RTW_HCI_TYPE_SDIO: |
1830 | rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1; | |
1831 | rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2; | |
1832 | break; | |
a82dfd33 SH |
1833 | case RTW_HCI_TYPE_USB: |
1834 | rtwdev->hci.rpwm_addr = 0xfe58; | |
1835 | rtwdev->hci.cpwm_addr = 0xfe57; | |
1836 | break; | |
e3037485 YHC |
1837 | default: |
1838 | rtw_err(rtwdev, "unsupported hci type\n"); | |
1839 | return -EINVAL; | |
1840 | } | |
1841 | ||
e3037485 | 1842 | hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); |
e3037485 YHC |
1843 | hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); |
1844 | hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; | |
1845 | if (hal->chip_version & BIT_RF_TYPE_ID) { | |
1846 | hal->rf_type = RF_2T2R; | |
1847 | hal->rf_path_num = 2; | |
1848 | hal->antenna_tx = BB_PATH_AB; | |
1849 | hal->antenna_rx = BB_PATH_AB; | |
1850 | } else { | |
1851 | hal->rf_type = RF_1T1R; | |
1852 | hal->rf_path_num = 1; | |
1853 | hal->antenna_tx = BB_PATH_A; | |
1854 | hal->antenna_rx = BB_PATH_A; | |
1855 | } | |
e0c27cdb PKS |
1856 | hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : |
1857 | hal->rf_path_num; | |
e3037485 | 1858 | |
e3037485 YHC |
1859 | efuse->physical_size = chip->phy_efuse_size; |
1860 | efuse->logical_size = chip->log_efuse_size; | |
1861 | efuse->protect_size = chip->ptct_efuse_size; | |
1862 | ||
1863 | /* default use ack */ | |
1864 | rtwdev->hal.rcr |= BIT_VHT_DACK; | |
1865 | ||
0bd95573 TEH |
1866 | hal->bfee_sts_cap = 3; |
1867 | ||
4a7ea943 | 1868 | return 0; |
e3037485 YHC |
1869 | } |
1870 | ||
1871 | static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) | |
1872 | { | |
1873 | struct rtw_fw_state *fw = &rtwdev->fw; | |
1874 | int ret; | |
1875 | ||
1876 | ret = rtw_hci_setup(rtwdev); | |
1877 | if (ret) { | |
1878 | rtw_err(rtwdev, "failed to setup hci\n"); | |
1879 | goto err; | |
1880 | } | |
1881 | ||
1882 | ret = rtw_mac_power_on(rtwdev); | |
1883 | if (ret) { | |
1884 | rtw_err(rtwdev, "failed to power on mac\n"); | |
1885 | goto err; | |
1886 | } | |
1887 | ||
1888 | rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); | |
1889 | ||
1890 | wait_for_completion(&fw->completion); | |
1891 | if (!fw->firmware) { | |
1892 | ret = -EINVAL; | |
1893 | rtw_err(rtwdev, "failed to load firmware\n"); | |
1894 | goto err; | |
1895 | } | |
1896 | ||
1897 | ret = rtw_download_firmware(rtwdev, fw); | |
1898 | if (ret) { | |
1899 | rtw_err(rtwdev, "failed to download firmware\n"); | |
1900 | goto err_off; | |
1901 | } | |
1902 | ||
1903 | return 0; | |
1904 | ||
1905 | err_off: | |
1906 | rtw_mac_power_off(rtwdev); | |
1907 | ||
1908 | err: | |
1909 | return ret; | |
1910 | } | |
1911 | ||
1912 | static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) | |
1913 | { | |
1914 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
1915 | u8 hw_feature[HW_FEATURE_LEN]; | |
1916 | u8 id; | |
1917 | u8 bw; | |
1918 | int i; | |
1919 | ||
1920 | id = rtw_read8(rtwdev, REG_C2HEVT); | |
1921 | if (id != C2H_HW_FEATURE_REPORT) { | |
1922 | rtw_err(rtwdev, "failed to read hw feature report\n"); | |
1923 | return -EBUSY; | |
1924 | } | |
1925 | ||
1926 | for (i = 0; i < HW_FEATURE_LEN; i++) | |
1927 | hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); | |
1928 | ||
1929 | rtw_write8(rtwdev, REG_C2HEVT, 0); | |
1930 | ||
1931 | bw = GET_EFUSE_HW_CAP_BW(hw_feature); | |
1932 | efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); | |
1933 | efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); | |
1934 | efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); | |
1935 | efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); | |
1936 | efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); | |
1937 | ||
1938 | rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); | |
1939 | ||
4f5bb7ff PKS |
1940 | if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || |
1941 | efuse->hw_cap.nss > rtwdev->hal.rf_path_num) | |
e3037485 YHC |
1942 | efuse->hw_cap.nss = rtwdev->hal.rf_path_num; |
1943 | ||
1944 | rtw_dbg(rtwdev, RTW_DBG_EFUSE, | |
1945 | "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", | |
1946 | efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, | |
1947 | efuse->hw_cap.ant_num, efuse->hw_cap.nss); | |
1948 | ||
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) | |
1953 | { | |
1954 | rtw_hci_stop(rtwdev); | |
1955 | rtw_mac_power_off(rtwdev); | |
1956 | } | |
1957 | ||
1958 | static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) | |
1959 | { | |
1960 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
1961 | int ret; | |
1962 | ||
1963 | mutex_lock(&rtwdev->mutex); | |
1964 | ||
1965 | /* power on mac to read efuse */ | |
1966 | ret = rtw_chip_efuse_enable(rtwdev); | |
1967 | if (ret) | |
f4268729 | 1968 | goto out_unlock; |
e3037485 YHC |
1969 | |
1970 | ret = rtw_parse_efuse_map(rtwdev); | |
1971 | if (ret) | |
f4268729 | 1972 | goto out_disable; |
e3037485 YHC |
1973 | |
1974 | ret = rtw_dump_hw_feature(rtwdev); | |
1975 | if (ret) | |
f4268729 | 1976 | goto out_disable; |
e3037485 YHC |
1977 | |
1978 | ret = rtw_check_supported_rfe(rtwdev); | |
1979 | if (ret) | |
f4268729 | 1980 | goto out_disable; |
e3037485 YHC |
1981 | |
1982 | if (efuse->crystal_cap == 0xff) | |
1983 | efuse->crystal_cap = 0; | |
1984 | if (efuse->pa_type_2g == 0xff) | |
1985 | efuse->pa_type_2g = 0; | |
1986 | if (efuse->pa_type_5g == 0xff) | |
1987 | efuse->pa_type_5g = 0; | |
1988 | if (efuse->lna_type_2g == 0xff) | |
1989 | efuse->lna_type_2g = 0; | |
1990 | if (efuse->lna_type_5g == 0xff) | |
1991 | efuse->lna_type_5g = 0; | |
1992 | if (efuse->channel_plan == 0xff) | |
1993 | efuse->channel_plan = 0x7f; | |
4136214f YHC |
1994 | if (efuse->rf_board_option == 0xff) |
1995 | efuse->rf_board_option = 0; | |
e3037485 YHC |
1996 | if (efuse->bt_setting & BIT(0)) |
1997 | efuse->share_ant = true; | |
1998 | if (efuse->regd == 0xff) | |
1999 | efuse->regd = 0; | |
58eb40c9 TEH |
2000 | if (efuse->tx_bb_swing_setting_2g == 0xff) |
2001 | efuse->tx_bb_swing_setting_2g = 0; | |
2002 | if (efuse->tx_bb_swing_setting_5g == 0xff) | |
2003 | efuse->tx_bb_swing_setting_5g = 0; | |
e3037485 | 2004 | |
4136214f | 2005 | efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; |
e3037485 YHC |
2006 | efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; |
2007 | efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; | |
2008 | efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; | |
8fbcaa30 | 2009 | efuse->ext_lna_5g = efuse->lna_type_5g & BIT(3) ? 1 : 0; |
e3037485 | 2010 | |
0a999d82 CM |
2011 | if (!is_valid_ether_addr(efuse->addr)) { |
2012 | eth_random_addr(efuse->addr); | |
2013 | dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n"); | |
2014 | } | |
2015 | ||
f4268729 | 2016 | out_disable: |
e3037485 YHC |
2017 | rtw_chip_efuse_disable(rtwdev); |
2018 | ||
f4268729 | 2019 | out_unlock: |
e3037485 YHC |
2020 | mutex_unlock(&rtwdev->mutex); |
2021 | return ret; | |
2022 | } | |
2023 | ||
2024 | static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) | |
2025 | { | |
2026 | struct rtw_hal *hal = &rtwdev->hal; | |
2027 | const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); | |
2028 | ||
2029 | if (!rfe_def) | |
2030 | return -ENODEV; | |
2031 | ||
97c75e1a | 2032 | rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type); |
e3037485 | 2033 | |
0d350f0a | 2034 | rtw_phy_init_tx_power(rtwdev); |
e3037485 YHC |
2035 | rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); |
2036 | rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); | |
2037 | rtw_phy_tx_power_by_rate_config(hal); | |
2038 | rtw_phy_tx_power_limit_config(hal); | |
2039 | ||
2040 | return 0; | |
2041 | } | |
2042 | ||
2043 | int rtw_chip_info_setup(struct rtw_dev *rtwdev) | |
2044 | { | |
2045 | int ret; | |
2046 | ||
2047 | ret = rtw_chip_parameter_setup(rtwdev); | |
2048 | if (ret) { | |
2049 | rtw_err(rtwdev, "failed to setup chip parameters\n"); | |
2050 | goto err_out; | |
2051 | } | |
2052 | ||
2053 | ret = rtw_chip_efuse_info_setup(rtwdev); | |
2054 | if (ret) { | |
2055 | rtw_err(rtwdev, "failed to setup chip efuse info\n"); | |
2056 | goto err_out; | |
2057 | } | |
2058 | ||
2059 | ret = rtw_chip_board_info_setup(rtwdev); | |
2060 | if (ret) { | |
2061 | rtw_err(rtwdev, "failed to setup chip board info\n"); | |
2062 | goto err_out; | |
2063 | } | |
2064 | ||
2065 | return 0; | |
2066 | ||
2067 | err_out: | |
2068 | return ret; | |
2069 | } | |
2070 | EXPORT_SYMBOL(rtw_chip_info_setup); | |
2071 | ||
082a36dc TSL |
2072 | static void rtw_stats_init(struct rtw_dev *rtwdev) |
2073 | { | |
2074 | struct rtw_traffic_stats *stats = &rtwdev->stats; | |
2075 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; | |
2076 | int i; | |
2077 | ||
2078 | ewma_tp_init(&stats->tx_ewma_tp); | |
2079 | ewma_tp_init(&stats->rx_ewma_tp); | |
2080 | ||
2081 | for (i = 0; i < RTW_EVM_NUM; i++) | |
2082 | ewma_evm_init(&dm_info->ewma_evm[i]); | |
2083 | for (i = 0; i < RTW_SNR_NUM; i++) | |
2084 | ewma_snr_init(&dm_info->ewma_snr[i]); | |
2085 | } | |
2086 | ||
e3037485 YHC |
2087 | int rtw_core_init(struct rtw_dev *rtwdev) |
2088 | { | |
dcbf179c | 2089 | const struct rtw_chip_info *chip = rtwdev->chip; |
4136214f | 2090 | struct rtw_coex *coex = &rtwdev->coex; |
e3037485 YHC |
2091 | int ret; |
2092 | ||
2093 | INIT_LIST_HEAD(&rtwdev->rsvd_page_list); | |
3745d3e5 | 2094 | INIT_LIST_HEAD(&rtwdev->txqs); |
e3037485 YHC |
2095 | |
2096 | timer_setup(&rtwdev->tx_report.purge_timer, | |
2097 | rtw_tx_report_purge_timer, 0); | |
fe101716 | 2098 | rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); |
42bbf810 WD |
2099 | if (!rtwdev->tx_wq) { |
2100 | rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n"); | |
2101 | return -ENOMEM; | |
2102 | } | |
e3037485 YHC |
2103 | |
2104 | INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); | |
4136214f YHC |
2105 | INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); |
2106 | INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); | |
2107 | INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); | |
001a3c90 ZZY |
2108 | INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); |
2109 | INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); | |
150ce8e3 | 2110 | INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); |
8e6947dc CTK |
2111 | INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, |
2112 | rtw_coex_bt_multi_link_remain_work); | |
2113 | INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); | |
fe101716 | 2114 | INIT_WORK(&rtwdev->tx_work, rtw_tx_work); |
e3037485 | 2115 | INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); |
c17f2716 | 2116 | INIT_WORK(&rtwdev->ips_work, rtw_ips_work); |
5c831644 | 2117 | INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); |
7711fe71 | 2118 | INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); |
46ebb174 | 2119 | INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); |
e3037485 | 2120 | skb_queue_head_init(&rtwdev->c2h_queue); |
4136214f | 2121 | skb_queue_head_init(&rtwdev->coex.queue); |
e3037485 YHC |
2122 | skb_queue_head_init(&rtwdev->tx_report.queue); |
2123 | ||
3745d3e5 | 2124 | spin_lock_init(&rtwdev->txq_lock); |
e3037485 YHC |
2125 | spin_lock_init(&rtwdev->tx_report.q_lock); |
2126 | ||
2127 | mutex_init(&rtwdev->mutex); | |
2128 | mutex_init(&rtwdev->hal.tx_power_mutex); | |
2129 | ||
4136214f | 2130 | init_waitqueue_head(&rtwdev->coex.wait); |
f31e039f | 2131 | init_completion(&rtwdev->lps_leave_check); |
a853d234 | 2132 | init_completion(&rtwdev->fw_scan_density); |
4136214f | 2133 | |
e3037485 YHC |
2134 | rtwdev->sec.total_cam_num = 32; |
2135 | rtwdev->hal.current_channel = 1; | |
1379e620 | 2136 | rtwdev->dm_info.fix_rate = U8_MAX; |
e3037485 | 2137 | |
082a36dc TSL |
2138 | rtw_stats_init(rtwdev); |
2139 | ||
e3037485 YHC |
2140 | /* default rx filter setting */ |
2141 | rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | | |
c1afb267 | 2142 | BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | |
e3037485 YHC |
2143 | BIT_AB | BIT_AM | BIT_APM; |
2144 | ||
c8e5695e | 2145 | ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); |
e3037485 YHC |
2146 | if (ret) { |
2147 | rtw_warn(rtwdev, "no firmware loaded\n"); | |
b0ea758b | 2148 | goto out; |
e3037485 YHC |
2149 | } |
2150 | ||
c8e5695e CYL |
2151 | if (chip->wow_fw_name) { |
2152 | ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); | |
2153 | if (ret) { | |
2154 | rtw_warn(rtwdev, "no wow firmware loaded\n"); | |
ac4bac99 AF |
2155 | wait_for_completion(&rtwdev->fw.completion); |
2156 | if (rtwdev->fw.firmware) | |
2157 | release_firmware(rtwdev->fw.firmware); | |
b0ea758b | 2158 | goto out; |
c8e5695e CYL |
2159 | } |
2160 | } | |
fc3ac64a | 2161 | |
e3037485 | 2162 | return 0; |
b0ea758b YY |
2163 | |
2164 | out: | |
2165 | destroy_workqueue(rtwdev->tx_wq); | |
2166 | return ret; | |
e3037485 YHC |
2167 | } |
2168 | EXPORT_SYMBOL(rtw_core_init); | |
2169 | ||
2170 | void rtw_core_deinit(struct rtw_dev *rtwdev) | |
2171 | { | |
2172 | struct rtw_fw_state *fw = &rtwdev->fw; | |
c8e5695e | 2173 | struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; |
e3037485 YHC |
2174 | struct rtw_rsvd_page *rsvd_pkt, *tmp; |
2175 | unsigned long flags; | |
2176 | ||
ecda9cda AF |
2177 | rtw_wait_firmware_completion(rtwdev); |
2178 | ||
e3037485 YHC |
2179 | if (fw->firmware) |
2180 | release_firmware(fw->firmware); | |
2181 | ||
c8e5695e CYL |
2182 | if (wow_fw->firmware) |
2183 | release_firmware(wow_fw->firmware); | |
2184 | ||
fe101716 | 2185 | destroy_workqueue(rtwdev->tx_wq); |
634fcbca | 2186 | timer_delete_sync(&rtwdev->tx_report.purge_timer); |
e3037485 YHC |
2187 | spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); |
2188 | skb_queue_purge(&rtwdev->tx_report.queue); | |
2189 | spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); | |
634fcbca DA |
2190 | skb_queue_purge(&rtwdev->coex.queue); |
2191 | skb_queue_purge(&rtwdev->c2h_queue); | |
e3037485 | 2192 | |
895c096d YHC |
2193 | list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, |
2194 | build_list) { | |
2195 | list_del(&rsvd_pkt->build_list); | |
e3037485 YHC |
2196 | kfree(rsvd_pkt); |
2197 | } | |
2198 | ||
2199 | mutex_destroy(&rtwdev->mutex); | |
2200 | mutex_destroy(&rtwdev->hal.tx_power_mutex); | |
2201 | } | |
2202 | EXPORT_SYMBOL(rtw_core_deinit); | |
2203 | ||
2204 | int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) | |
2205 | { | |
a54b7a7c | 2206 | bool sta_mode_only = rtwdev->hci.type == RTW_HCI_TYPE_SDIO; |
297bcf82 | 2207 | struct rtw_hal *hal = &rtwdev->hal; |
e3037485 YHC |
2208 | int max_tx_headroom = 0; |
2209 | int ret; | |
2210 | ||
e3037485 YHC |
2211 | max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; |
2212 | ||
02461d93 MB |
2213 | if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) |
2214 | max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN; | |
2215 | ||
e3037485 YHC |
2216 | hw->extra_tx_headroom = max_tx_headroom; |
2217 | hw->queues = IEEE80211_NUM_ACS; | |
3745d3e5 | 2218 | hw->txq_data_size = sizeof(struct rtw_txq); |
e3037485 YHC |
2219 | hw->sta_data_size = sizeof(struct rtw_sta_info); |
2220 | hw->vif_data_size = sizeof(struct rtw_vif); | |
2221 | ||
2222 | ieee80211_hw_set(hw, SIGNAL_DBM); | |
2223 | ieee80211_hw_set(hw, RX_INCLUDES_FCS); | |
2224 | ieee80211_hw_set(hw, AMPDU_AGGREGATION); | |
2225 | ieee80211_hw_set(hw, MFP_CAPABLE); | |
2226 | ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); | |
2227 | ieee80211_hw_set(hw, SUPPORTS_PS); | |
2228 | ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); | |
e6fec313 | 2229 | ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); |
970cad9f | 2230 | ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); |
46ebb174 | 2231 | ieee80211_hw_set(hw, HAS_RATE_CONTROL); |
127eef1d | 2232 | ieee80211_hw_set(hw, TX_AMSDU); |
10d162b2 | 2233 | ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); |
e3037485 | 2234 | |
a54b7a7c PKS |
2235 | if (sta_mode_only) |
2236 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
2237 | else | |
2238 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | | |
2239 | BIT(NL80211_IFTYPE_AP) | | |
2ccb8e6c | 2240 | BIT(NL80211_IFTYPE_ADHOC); |
297bcf82 YHC |
2241 | hw->wiphy->available_antennas_tx = hal->antenna_tx; |
2242 | hw->wiphy->available_antennas_rx = hal->antenna_rx; | |
e3037485 YHC |
2243 | |
2244 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | | |
2245 | WIPHY_FLAG_TDLS_EXTERNAL_SETUP; | |
2246 | ||
44cc4c63 | 2247 | hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; |
10d162b2 | 2248 | hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; |
d2eb7cb9 | 2249 | hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev); |
44cc4c63 | 2250 | |
a54b7a7c | 2251 | if (!sta_mode_only && rtwdev->chip->id == RTW_CHIP_TYPE_8822C) { |
d16836cd PHH |
2252 | hw->wiphy->iface_combinations = rtw_iface_combs; |
2253 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs); | |
2254 | } | |
2255 | ||
5dc32b8a | 2256 | wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); |
10d162b2 PHH |
2257 | wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); |
2258 | wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); | |
5dc32b8a | 2259 | |
44bc17f7 CYL |
2260 | #ifdef CONFIG_PM |
2261 | hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; | |
b6c12908 | 2262 | hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; |
44bc17f7 | 2263 | #endif |
e3037485 YHC |
2264 | rtw_set_supported_band(hw, rtwdev->chip); |
2265 | SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); | |
2266 | ||
8704d0be ZZY |
2267 | hw->wiphy->sar_capa = &rtw_sar_capa; |
2268 | ||
8d4fb399 ZZY |
2269 | ret = rtw_regd_init(rtwdev); |
2270 | if (ret) { | |
2271 | rtw_err(rtwdev, "failed to init regd\n"); | |
2272 | return ret; | |
2273 | } | |
e3037485 YHC |
2274 | |
2275 | ret = ieee80211_register_hw(hw); | |
2276 | if (ret) { | |
2277 | rtw_err(rtwdev, "failed to register hw\n"); | |
2278 | return ret; | |
2279 | } | |
2280 | ||
8d4fb399 ZZY |
2281 | ret = rtw_regd_hint(rtwdev); |
2282 | if (ret) { | |
2283 | rtw_err(rtwdev, "failed to hint regd\n"); | |
2284 | return ret; | |
2285 | } | |
e3037485 YHC |
2286 | |
2287 | rtw_debugfs_init(rtwdev); | |
2288 | ||
0bd95573 TEH |
2289 | rtwdev->bf_info.bfer_mu_cnt = 0; |
2290 | rtwdev->bf_info.bfer_su_cnt = 0; | |
2291 | ||
e3037485 YHC |
2292 | return 0; |
2293 | } | |
2294 | EXPORT_SYMBOL(rtw_register_hw); | |
2295 | ||
2296 | void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) | |
2297 | { | |
dcbf179c | 2298 | const struct rtw_chip_info *chip = rtwdev->chip; |
e3037485 YHC |
2299 | |
2300 | ieee80211_unregister_hw(hw); | |
2301 | rtw_unset_supported_band(hw, chip); | |
8db6c1ca | 2302 | rtw_debugfs_deinit(rtwdev); |
e3037485 YHC |
2303 | } |
2304 | EXPORT_SYMBOL(rtw_unregister_hw); | |
2305 | ||
ccf73f6e PHH |
2306 | static |
2307 | void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, | |
2308 | const struct rtw_hw_reg *reg2, u8 nbytes) | |
2309 | { | |
2310 | u8 i; | |
2311 | ||
2312 | for (i = 0; i < nbytes; i++) { | |
2313 | u8 v1 = rtw_read8(rtwdev, reg1->addr + i); | |
2314 | u8 v2 = rtw_read8(rtwdev, reg2->addr + i); | |
2315 | ||
2316 | rtw_write8(rtwdev, reg1->addr + i, v2); | |
2317 | rtw_write8(rtwdev, reg2->addr + i, v1); | |
2318 | } | |
2319 | } | |
2320 | ||
2321 | static | |
2322 | void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, | |
2323 | const struct rtw_hw_reg *reg2) | |
2324 | { | |
2325 | u32 v1, v2; | |
2326 | ||
2327 | v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask); | |
2328 | v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask); | |
2329 | rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1); | |
2330 | rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2); | |
2331 | } | |
2332 | ||
2333 | struct rtw_iter_port_switch_data { | |
2334 | struct rtw_dev *rtwdev; | |
2335 | struct rtw_vif *rtwvif_ap; | |
2336 | }; | |
2337 | ||
8986f0a9 | 2338 | static void rtw_port_switch_iter(void *data, struct ieee80211_vif *vif) |
ccf73f6e PHH |
2339 | { |
2340 | struct rtw_iter_port_switch_data *iter_data = data; | |
2341 | struct rtw_dev *rtwdev = iter_data->rtwdev; | |
2342 | struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv; | |
2343 | struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap; | |
2344 | const struct rtw_hw_reg *reg1, *reg2; | |
2345 | ||
2346 | if (rtwvif_target->port != RTW_PORT_0) | |
2347 | return; | |
2348 | ||
2349 | rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n", | |
2350 | rtwvif_ap->port, rtwvif_target->port); | |
2351 | ||
28c11c29 PHH |
2352 | /* Leave LPS so the value swapped are not in PS mode */ |
2353 | rtw_leave_lps(rtwdev); | |
2354 | ||
ccf73f6e PHH |
2355 | reg1 = &rtwvif_ap->conf->net_type; |
2356 | reg2 = &rtwvif_target->conf->net_type; | |
2357 | rtw_swap_reg_mask(rtwdev, reg1, reg2); | |
2358 | ||
2359 | reg1 = &rtwvif_ap->conf->mac_addr; | |
2360 | reg2 = &rtwvif_target->conf->mac_addr; | |
2361 | rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); | |
2362 | ||
2363 | reg1 = &rtwvif_ap->conf->bssid; | |
2364 | reg2 = &rtwvif_target->conf->bssid; | |
2365 | rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); | |
2366 | ||
2367 | reg1 = &rtwvif_ap->conf->bcn_ctrl; | |
2368 | reg2 = &rtwvif_target->conf->bcn_ctrl; | |
2369 | rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1); | |
2370 | ||
2371 | swap(rtwvif_target->port, rtwvif_ap->port); | |
2372 | swap(rtwvif_target->conf, rtwvif_ap->conf); | |
28c11c29 PHH |
2373 | |
2374 | rtw_fw_default_port(rtwdev, rtwvif_target); | |
ccf73f6e PHH |
2375 | } |
2376 | ||
2377 | void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) | |
2378 | { | |
2379 | struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; | |
2380 | struct rtw_iter_port_switch_data iter_data; | |
2381 | ||
2382 | if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0) | |
2383 | return; | |
2384 | ||
2385 | iter_data.rtwdev = rtwdev; | |
2386 | iter_data.rtwvif_ap = rtwvif; | |
2387 | rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data); | |
2388 | } | |
2389 | ||
8986f0a9 | 2390 | static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif) |
96fbb84d PHH |
2391 | { |
2392 | struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; | |
2393 | bool *active = data; | |
2394 | ||
2395 | if (*active) | |
2396 | return; | |
2397 | ||
2398 | if (vif->type != NL80211_IFTYPE_STATION) | |
2399 | return; | |
2400 | ||
2401 | if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid)) | |
2402 | *active = true; | |
2403 | } | |
2404 | ||
2405 | bool rtw_core_check_sta_active(struct rtw_dev *rtwdev) | |
2406 | { | |
2407 | bool sta_active = false; | |
2408 | ||
2409 | rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active); | |
2410 | ||
2411 | return rtwdev->ap_active || sta_active; | |
2412 | } | |
2413 | ||
2414 | void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable) | |
2415 | { | |
2416 | if (!rtwdev->ap_active) | |
2417 | return; | |
2418 | ||
ad6741b1 | 2419 | if (enable) { |
96fbb84d | 2420 | rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); |
ad6741b1 PHH |
2421 | rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); |
2422 | } else { | |
96fbb84d | 2423 | rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); |
ad6741b1 PHH |
2424 | rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); |
2425 | } | |
96fbb84d PHH |
2426 | } |
2427 | ||
e3037485 YHC |
2428 | MODULE_AUTHOR("Realtek Corporation"); |
2429 | MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); | |
2430 | MODULE_LICENSE("Dual BSD/GPL"); |