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networking: introduce and use skb_put_data()
[linux-block.git] / drivers / net / wireless / realtek / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
a8d76066 3 * Copyright(c) 2009-2012 Realtek Corporation.
0c817338
LF		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
0c817338
LF		 14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
0c817338 26#include "wifi.h"
d273bb20 27#include "core.h"
0c817338
LF		 28#include "pci.h"
29#include "base.h"
30#include "ps.h"
c7cfe38e 31#include "efuse.h"
38506ece 32#include <linux/interrupt.h>
d273bb20 33#include <linux/export.h>
f11bbfd8 34#include <linux/kmemleak.h>
6f334c2b
LF		 35#include <linux/module.h>
36
37MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
38MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
39MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
40MODULE_LICENSE("GPL");
41MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
0c817338
LF		 42
43static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38506ece
LF		 44 INTEL_VENDOR_ID,
45 ATI_VENDOR_ID,
46 AMD_VENDOR_ID,
47 SIS_VENDOR_ID
0c817338
LF		 48};
49
c7cfe38e
C		 50static const u8 ac_to_hwq[] = {
51 VO_QUEUE,
52 VI_QUEUE,
53 BE_QUEUE,
54 BK_QUEUE
55};
56
d3bb1429 57static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
c7cfe38e
C		 58 struct sk_buff *skb)
59{
60 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 61 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 62 u8 queue_index = skb_get_queue_mapping(skb);
63
64 if (unlikely(ieee80211_is_beacon(fc)))
65 return BEACON_QUEUE;
26634c4b 66 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
c7cfe38e
C		 67 return MGNT_QUEUE;
68 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
69 if (ieee80211_is_nullfunc(fc))
70 return HIGH_QUEUE;
71
72 return ac_to_hwq[queue_index];
73}
74
0c817338
LF		 75/* Update PCI dependent default settings*/
76static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
77{
78 struct rtl_priv *rtlpriv = rtl_priv(hw);
79 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
80 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
81 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
82 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 83 u8 init_aspm;
0c817338
LF		 84
85 ppsc->reg_rfps_level = 0;
3db1cd5c 86 ppsc->support_aspm = false;
0c817338
LF		 87
88 /*Update PCI ASPM setting */
89 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
90 switch (rtlpci->const_pci_aspm) {
91 case 0:
92 /*No ASPM */
93 break;
94
95 case 1:
96 /*ASPM dynamically enabled/disable. */
97 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
98 break;
99
100 case 2:
101 /*ASPM with Clock Req dynamically enabled/disable. */
102 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
103 RT_RF_OFF_LEVL_CLK_REQ);
104 break;
105
106 case 3:
107 /*
108 * Always enable ASPM and Clock Req
109 * from initialization to halt.
110 * */
111 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
112 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
113 RT_RF_OFF_LEVL_CLK_REQ);
114 break;
115
116 case 4:
117 /*
118 * Always enable ASPM without Clock Req
119 * from initialization to halt.
120 * */
121 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
122 RT_RF_OFF_LEVL_CLK_REQ);
123 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
124 break;
125 }
126
127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
128
129 /*Update Radio OFF setting */
130 switch (rtlpci->const_hwsw_rfoff_d3) {
131 case 1:
132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
134 break;
135
136 case 2:
137 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
140 break;
141
142 case 3:
143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
144 break;
145 }
146
147 /*Set HW definition to determine if it supports ASPM. */
148 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 149 case 0:{
150 /*Not support ASPM. */
151 bool support_aspm = false;
152 ppsc->support_aspm = support_aspm;
153 break;
154 }
155 case 1:{
156 /*Support ASPM. */
157 bool support_aspm = true;
158 bool support_backdoor = true;
159 ppsc->support_aspm = support_aspm;
160
161 /*if (priv->oem_id == RT_CID_TOSHIBA &&
162 !priv->ndis_adapter.amd_l1_patch)
163 support_backdoor = false; */
164
165 ppsc->support_backdoor = support_backdoor;
166
167 break;
168 }
0c817338
LF		 169 case 2:
170 /*ASPM value set by chipset. */
c7cfe38e
C		 171 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
172 bool support_aspm = true;
173 ppsc->support_aspm = support_aspm;
174 }
0c817338
LF		 175 break;
176 default:
b03d968b
LF		 177 pr_err("switch case %#x not processed\n",
178 rtlpci->const_support_pciaspm);
0c817338
LF		 179 break;
180 }
c7cfe38e
C		 181
182 /* toshiba aspm issue, toshiba will set aspm selfly
183 * so we should not set aspm in driver */
184 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
185 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
186 init_aspm == 0x43)
187 ppsc->support_aspm = false;
188}
189
0c817338
LF		 190static bool _rtl_pci_platform_switch_device_pci_aspm(
191 struct ieee80211_hw *hw,
192 u8 value)
193{
194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 195 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
196
197 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
198 value |= 0x40;
0c817338 199
0c817338
LF		 200 pci_write_config_byte(rtlpci->pdev, 0x80, value);
201
32473284 202 return false;
0c817338
LF		 203}
204
205/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
1d73c51a 206static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
0c817338
LF		 207{
208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 209 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 210
0c817338 211 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 212
c7cfe38e
C		 213 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
214 udelay(100);
0c817338
LF		 215}
216
217/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
218static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
219{
220 struct rtl_priv *rtlpriv = rtl_priv(hw);
221 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
222 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
223 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
224 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 225 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
226 /*Retrieve original configuration settings. */
227 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
228 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
229 pcibridge_linkctrlreg;
230 u16 aspmlevel = 0;
32473284 231 u8 tmp_u1b = 0;
0c817338 232
c7cfe38e
C		 233 if (!ppsc->support_aspm)
234 return;
235
0c817338
LF		 236 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
237 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 238 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 239
240 return;
241 }
242
243 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
244 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
245 _rtl_pci_switch_clk_req(hw, 0x0);
246 }
247
32473284
LF		 248 /*for promising device will in L0 state after an I/O. */
249 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 250
251 /*Set corresponding value. */
252 aspmlevel |= BIT(0) | BIT(1);
253 linkctrl_reg &= ~aspmlevel;
254 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
255
256 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
257 udelay(50);
258
259 /*4 Disable Pci Bridge ASPM */
886e14b6
LF		 260 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
261 pcibridge_linkctrlreg);
0c817338
LF		 262
263 udelay(50);
0c817338
LF		 264}
265
266/*
267 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
268 *power saving We should follow the sequence to enable
269 *RTL8192SE first then enable Pci Bridge ASPM
270 *or the system will show bluescreen.
271 */
272static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
273{
274 struct rtl_priv *rtlpriv = rtl_priv(hw);
275 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
276 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
277 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338 278 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 279 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
280 u16 aspmlevel;
281 u8 u_pcibridge_aspmsetting;
282 u8 u_device_aspmsetting;
283
c7cfe38e
C		 284 if (!ppsc->support_aspm)
285 return;
286
0c817338
LF		 287 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
288 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 289 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 290 return;
291 }
292
293 /*4 Enable Pci Bridge ASPM */
0c817338
LF		 294
295 u_pcibridge_aspmsetting =
296 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
297 rtlpci->const_hostpci_aspm_setting;
298
299 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
300 u_pcibridge_aspmsetting &= ~BIT(0);
301
886e14b6
LF		 302 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
303 u_pcibridge_aspmsetting);
0c817338
LF		 304
305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
26634c4b 306 "PlatformEnableASPM(): Write reg[%x] = %x\n",
f30d7507
JP		 307 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
308 u_pcibridge_aspmsetting);
0c817338
LF		 309
310 udelay(50);
311
312 /*Get ASPM level (with/without Clock Req) */
313 aspmlevel = rtlpci->const_devicepci_aspm_setting;
314 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
315
316 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
317 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
318
319 u_device_aspmsetting |= aspmlevel;
320
321 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
322
323 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
324 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
325 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
326 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
327 }
c7cfe38e 328 udelay(100);
0c817338
LF		 329}
330
331static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
332{
886e14b6 333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338
LF		 334
335 bool status = false;
336 u8 offset_e0;
337 unsigned offset_e4;
338
886e14b6 339 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
0c817338 340
886e14b6 341 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
0c817338
LF		 342
343 if (offset_e0 == 0xA0) {
886e14b6 344 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
0c817338
LF		 345 if (offset_e4 & BIT(23))
346 status = true;
347 }
348
349 return status;
350}
351
26634c4b
LF		 352static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
353 struct rtl_priv **buddy_priv)
354{
355 struct rtl_priv *rtlpriv = rtl_priv(hw);
356 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
357 bool find_buddy_priv = false;
37c52934 358 struct rtl_priv *tpriv;
26634c4b
LF		 359 struct rtl_pci_priv *tpcipriv = NULL;
360
361 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
362 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
363 list) {
37c52934
LF		 364 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
365 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
366 "pcipriv->ndis_adapter.funcnumber %x\n",
367 pcipriv->ndis_adapter.funcnumber);
368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
369 "tpcipriv->ndis_adapter.funcnumber %x\n",
370 tpcipriv->ndis_adapter.funcnumber);
371
372 if ((pcipriv->ndis_adapter.busnumber ==
373 tpcipriv->ndis_adapter.busnumber) &&
374 (pcipriv->ndis_adapter.devnumber ==
375 tpcipriv->ndis_adapter.devnumber) &&
376 (pcipriv->ndis_adapter.funcnumber !=
377 tpcipriv->ndis_adapter.funcnumber)) {
378 find_buddy_priv = true;
379 break;
26634c4b
LF		 380 }
381 }
382 }
383
384 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
385 "find_buddy_priv %d\n", find_buddy_priv);
386
387 if (find_buddy_priv)
388 *buddy_priv = tpriv;
389
390 return find_buddy_priv;
391}
392
d3bb1429 393static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 394{
395 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
886e14b6 396 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
0c817338 397 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
0c817338 398 u8 linkctrl_reg;
c7cfe38e 399 u8 num4bbytes;
0c817338 400
c7cfe38e 401 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 402
403 /*Read Link Control Register */
886e14b6 404 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
0c817338
LF		 405
406 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
407}
408
409static void rtl_pci_parse_configuration(struct pci_dev *pdev,
410 struct ieee80211_hw *hw)
411{
412 struct rtl_priv *rtlpriv = rtl_priv(hw);
413 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
414
415 u8 tmp;
332badc3 416 u16 linkctrl_reg;
0c817338
LF		 417
418 /*Link Control Register */
332badc3
JL		 419 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
420 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
0c817338 421
f30d7507
JP		 422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
423 pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 424
425 pci_read_config_byte(pdev, 0x98, &tmp);
426 tmp |= BIT(4);
427 pci_write_config_byte(pdev, 0x98, tmp);
428
429 tmp = 0x17;
430 pci_write_config_byte(pdev, 0x70f, tmp);
431}
432
c7cfe38e 433static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 434{
435 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
436
437 _rtl_pci_update_default_setting(hw);
438
439 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
440 /*Always enable ASPM & Clock Req. */
441 rtl_pci_enable_aspm(hw);
442 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
443 }
444
445}
446
0c817338
LF		 447static void _rtl_pci_io_handler_init(struct device *dev,
448 struct ieee80211_hw *hw)
449{
450 struct rtl_priv *rtlpriv = rtl_priv(hw);
451
452 rtlpriv->io.dev = dev;
453
454 rtlpriv->io.write8_async = pci_write8_async;
455 rtlpriv->io.write16_async = pci_write16_async;
456 rtlpriv->io.write32_async = pci_write32_async;
457
458 rtlpriv->io.read8_sync = pci_read8_sync;
459 rtlpriv->io.read16_sync = pci_read16_sync;
460 rtlpriv->io.read32_sync = pci_read32_sync;
461
462}
463
c7cfe38e
C		 464static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
465 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
466{
467 struct rtl_priv *rtlpriv = rtl_priv(hw);
468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
26634c4b 469 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
c7cfe38e 470 struct sk_buff *next_skb;
26634c4b 471 u8 additionlen = FCS_LEN;
c7cfe38e
C		 472
473 /* here open is 4, wep/tkip is 8, aes is 12*/
474 if (info->control.hw_key)
475 additionlen += info->control.hw_key->icv_len;
476
477 /* The most skb num is 6 */
478 tcb_desc->empkt_num = 0;
479 spin_lock_bh(&rtlpriv->locks.waitq_lock);
480 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
481 struct ieee80211_tx_info *next_info;
482
483 next_info = IEEE80211_SKB_CB(next_skb);
484 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
485 tcb_desc->empkt_len[tcb_desc->empkt_num] =
486 next_skb->len + additionlen;
487 tcb_desc->empkt_num++;
488 } else {
489 break;
490 }
491
492 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
493 next_skb))
494 break;
495
26634c4b 496 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
c7cfe38e
C		 497 break;
498 }
499 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
500
501 return true;
502}
503
504/* just for early mode now */
505static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
506{
507 struct rtl_priv *rtlpriv = rtl_priv(hw);
508 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
509 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
510 struct sk_buff *skb = NULL;
511 struct ieee80211_tx_info *info = NULL;
26634c4b 512 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
fb914ebf 513 int tid;
c7cfe38e
C		 514
515 if (!rtlpriv->rtlhal.earlymode_enable)
516 return;
517
26634c4b
LF		 518 if (rtlpriv->dm.supp_phymode_switch &&
519 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
520 (rtlpriv->buddy_priv &&
521 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
522 return;
c7cfe38e
C		 523 /* we juse use em for BE/BK/VI/VO */
524 for (tid = 7; tid >= 0; tid--) {
2a00def4 525 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
c7cfe38e
C		 526 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
527 while (!mac->act_scanning &&
528 rtlpriv->psc.rfpwr_state == ERFON) {
529 struct rtl_tcb_desc tcb_desc;
530 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
531
532 spin_lock_bh(&rtlpriv->locks.waitq_lock);
533 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
26634c4b
LF		 534 (ring->entries - skb_queue_len(&ring->queue) >
535 rtlhal->max_earlymode_num)) {
c7cfe38e
C		 536 skb = skb_dequeue(&mac->skb_waitq[tid]);
537 } else {
538 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
539 break;
540 }
541 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
542
543 /* Some macaddr can't do early mode. like
544 * multicast/broadcast/no_qos data */
545 info = IEEE80211_SKB_CB(skb);
546 if (info->flags & IEEE80211_TX_CTL_AMPDU)
547 _rtl_update_earlymode_info(hw, skb,
548 &tcb_desc, tid);
549
36323f81 550 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
c7cfe38e
C		 551 }
552 }
553}
554
555
0c817338
LF		 556static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
557{
558 struct rtl_priv *rtlpriv = rtl_priv(hw);
559 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
560
561 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
562
563 while (skb_queue_len(&ring->queue)) {
0c817338
LF		 564 struct sk_buff *skb;
565 struct ieee80211_tx_info *info;
c7cfe38e
C		 566 __le16 fc;
567 u8 tid;
38506ece 568 u8 *entry;
0c817338 569
38506ece
LF		 570 if (rtlpriv->use_new_trx_flow)
571 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
572 else
573 entry = (u8 *)(&ring->desc[ring->idx]);
0c817338 574
d0311314
TT		 575 if (rtlpriv->cfg->ops->get_available_desc &&
576 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) {
577 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG,
578 "no available desc!\n");
579 return;
580 }
581
38506ece 582 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
0c817338
LF		 583 return;
584 ring->idx = (ring->idx + 1) % ring->entries;
585
586 skb = __skb_dequeue(&ring->queue);
587 pci_unmap_single(rtlpci->pdev,
d3bb1429 588 rtlpriv->cfg->ops->
38506ece 589 get_desc((u8 *)entry, true,
d3bb1429 590 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 591 skb->len, PCI_DMA_TODEVICE);
592
c7cfe38e
C		 593 /* remove early mode header */
594 if (rtlpriv->rtlhal.earlymode_enable)
595 skb_pull(skb, EM_HDR_LEN);
596
0c817338 597 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
f30d7507
JP		 598 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
599 ring->idx,
600 skb_queue_len(&ring->queue),
38506ece 601 *(u16 *)(skb->data + 22));
0c817338 602
c7cfe38e
C		 603 if (prio == TXCMD_QUEUE) {
604 dev_kfree_skb(skb);
605 goto tx_status_ok;
606
607 }
608
609 /* for sw LPS, just after NULL skb send out, we can
26634c4b
LF		 610 * sure AP knows we are sleeping, we should not let
611 * rf sleep
612 */
c7cfe38e
C		 613 fc = rtl_get_fc(skb);
614 if (ieee80211_is_nullfunc(fc)) {
615 if (ieee80211_has_pm(fc)) {
9c050440 616 rtlpriv->mac80211.offchan_delay = true;
3db1cd5c 617 rtlpriv->psc.state_inap = true;
c7cfe38e 618 } else {
3db1cd5c 619 rtlpriv->psc.state_inap = false;
c7cfe38e
C		 620 }
621 }
26634c4b
LF		 622 if (ieee80211_is_action(fc)) {
623 struct ieee80211_mgmt *action_frame =
624 (struct ieee80211_mgmt *)skb->data;
625 if (action_frame->u.action.u.ht_smps.action ==
626 WLAN_HT_ACTION_SMPS) {
627 dev_kfree_skb(skb);
628 goto tx_status_ok;
629 }
630 }
c7cfe38e
C		 631
632 /* update tid tx pkt num */
633 tid = rtl_get_tid(skb);
634 if (tid <= 7)
635 rtlpriv->link_info.tidtx_inperiod[tid]++;
636
0c817338
LF		 637 info = IEEE80211_SKB_CB(skb);
638 ieee80211_tx_info_clear_status(info);
639
640 info->flags |= IEEE80211_TX_STAT_ACK;
641 /*info->status.rates[0].count = 1; */
642
643 ieee80211_tx_status_irqsafe(hw, skb);
644
d0311314 645 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
0c817338 646
d0311314 647 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
4f4378de 648 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
f30d7507
JP		 649 prio, ring->idx,
650 skb_queue_len(&ring->queue));
0c817338
LF		 651
652 ieee80211_wake_queue(hw,
653 skb_get_queue_mapping
654 (skb));
655 }
c7cfe38e 656tx_status_ok:
0c817338
LF		 657 skb = NULL;
658 }
659
660 if (((rtlpriv->link_info.num_rx_inperiod +
ba9f93f8
LF		 661 rtlpriv->link_info.num_tx_inperiod) > 8) ||
662 (rtlpriv->link_info.num_rx_inperiod > 2))
663 rtl_lps_leave(hw);
0c817338
LF		 664}
665
38506ece 666static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
e9538cf4
LF		 667 struct sk_buff *new_skb, u8 *entry,
668 int rxring_idx, int desc_idx)
fd854772
MM		 669{
670 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece
LF		 671 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
672 u32 bufferaddress;
673 u8 tmp_one = 1;
674 struct sk_buff *skb;
675
e9538cf4
LF		 676 if (likely(new_skb)) {
677 skb = new_skb;
678 goto remap;
679 }
38506ece
LF		 680 skb = dev_alloc_skb(rtlpci->rxbuffersize);
681 if (!skb)
682 return 0;
38506ece 683
e9538cf4 684remap:
38506ece
LF		 685 /* just set skb->cb to mapping addr for pci_unmap_single use */
686 *((dma_addr_t *)skb->cb) =
687 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
688 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
689 bufferaddress = *((dma_addr_t *)skb->cb);
690 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
691 return 0;
e9538cf4 692 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
38506ece
LF		 693 if (rtlpriv->use_new_trx_flow) {
694 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
695 HW_DESC_RX_PREPARE,
696 (u8 *)&bufferaddress);
fd854772 697 } else {
38506ece
LF		 698 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
699 HW_DESC_RXBUFF_ADDR,
700 (u8 *)&bufferaddress);
701 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
702 HW_DESC_RXPKT_LEN,
703 (u8 *)&rtlpci->rxbuffersize);
704 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
705 HW_DESC_RXOWN,
706 (u8 *)&tmp_one);
fd854772 707 }
38506ece
LF		 708 return 1;
709}
fd854772 710
38506ece
LF		 711/* inorder to receive 8K AMSDU we have set skb to
712 * 9100bytes in init rx ring, but if this packet is
713 * not a AMSDU, this large packet will be sent to
714 * TCP/IP directly, this cause big packet ping fail
715 * like: "ping -s 65507", so here we will realloc skb
716 * based on the true size of packet, Mac80211
717 * Probably will do it better, but does not yet.
718 *
719 * Some platform will fail when alloc skb sometimes.
720 * in this condition, we will send the old skb to
721 * mac80211 directly, this will not cause any other
722 * issues, but only this packet will be lost by TCP/IP
723 */
724static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
725 struct sk_buff *skb,
726 struct ieee80211_rx_status rx_status)
727{
728 if (unlikely(!rtl_action_proc(hw, skb, false))) {
729 dev_kfree_skb_any(skb);
730 } else {
731 struct sk_buff *uskb = NULL;
732 u8 *pdata;
733
734 uskb = dev_alloc_skb(skb->len + 128);
735 if (likely(uskb)) {
736 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
737 sizeof(rx_status));
59ae1d12 738 pdata = skb_put_data(uskb, skb->data, skb->len);
38506ece
LF		 739 dev_kfree_skb_any(skb);
740 ieee80211_rx_irqsafe(hw, uskb);
741 } else {
742 ieee80211_rx_irqsafe(hw, skb);
743 }
fd854772 744 }
38506ece 745}
fd854772 746
38506ece
LF		 747/*hsisr interrupt handler*/
748static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
749{
750 struct rtl_priv *rtlpriv = rtl_priv(hw);
751 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
fd854772 752
38506ece
LF		 753 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
754 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
755 rtlpci->sys_irq_mask);
fd854772
MM		 756}
757
0c817338
LF		 758static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
759{
760 struct rtl_priv *rtlpriv = rtl_priv(hw);
761 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece 762 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
0c817338
LF		 763 struct ieee80211_rx_status rx_status = { 0 };
764 unsigned int count = rtlpci->rxringcount;
765 u8 own;
766 u8 tmp_one;
38506ece
LF		 767 bool unicast = false;
768 u8 hw_queue = 0;
769 unsigned int rx_remained_cnt;
0c817338
LF		 770 struct rtl_stats stats = {
771 .signal = 0,
0c817338
LF		 772 .rate = 0,
773 };
774
775 /*RX NORMAL PKT */
776 while (count--) {
38506ece
LF		 777 struct ieee80211_hdr *hdr;
778 __le16 fc;
779 u16 len;
780 /*rx buffer descriptor */
781 struct rtl_rx_buffer_desc *buffer_desc = NULL;
782 /*if use new trx flow, it means wifi info */
783 struct rtl_rx_desc *pdesc = NULL;
0c817338 784 /*rx pkt */
38506ece
LF		 785 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
786 rtlpci->rx_ring[rxring_idx].idx];
e9538cf4 787 struct sk_buff *new_skb;
38506ece
LF		 788
789 if (rtlpriv->use_new_trx_flow) {
790 rx_remained_cnt =
791 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
792 hw_queue);
d0311314 793 if (rx_remained_cnt == 0)
38506ece 794 return;
f99551a2
LF		 795 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
796 rtlpci->rx_ring[rxring_idx].idx];
797 pdesc = (struct rtl_rx_desc *)skb->data;
38506ece
LF		 798 } else { /* rx descriptor */
799 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
800 rtlpci->rx_ring[rxring_idx].idx];
801
802 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
803 false,
804 HW_DESC_OWN);
805 if (own) /* wait data to be filled by hardware */
806 return;
807 }
6633d649 808
38506ece
LF		 809 /* Reaching this point means: data is filled already
810 * AAAAAAttention !!!
811 * We can NOT access 'skb' before 'pci_unmap_single'
812 */
813 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
814 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
815
e9538cf4
LF		 816 /* get a new skb - if fail, old one will be reused */
817 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
aeb2d2a4 818 if (unlikely(!new_skb))
e9538cf4 819 goto no_new;
38506ece 820 memset(&rx_status , 0 , sizeof(rx_status));
2c333366 821 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
38506ece 822 &rx_status, (u8 *)pdesc, skb);
2c333366 823
38506ece
LF		 824 if (rtlpriv->use_new_trx_flow)
825 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
826 (u8 *)buffer_desc,
827 hw_queue);
8db8ddf1 828
38506ece
LF		 829 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false,
830 HW_DESC_RXPKT_LEN);
2c333366 831
38506ece
LF		 832 if (skb->end - skb->tail > len) {
833 skb_put(skb, len);
834 if (rtlpriv->use_new_trx_flow)
835 skb_reserve(skb, stats.rx_drvinfo_size +
836 stats.rx_bufshift + 24);
837 else
838 skb_reserve(skb, stats.rx_drvinfo_size +
839 stats.rx_bufshift);
38506ece
LF		 840 } else {
841 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
842 "skb->end - skb->tail = %d, len is %d\n",
843 skb->end - skb->tail, len);
d0311314
TT		 844 dev_kfree_skb_any(skb);
845 goto new_trx_end;
38506ece
LF		 846 }
847 /* handle command packet here */
d1cd5ba4 848 if (rtlpriv->cfg->ops->rx_command_packet &&
ce254243 849 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) {
38506ece 850 dev_kfree_skb_any(skb);
d0311314 851 goto new_trx_end;
38506ece 852 }
2c333366
MM		 853
854 /*
855 * NOTICE This can not be use for mac80211,
856 * this is done in mac80211 code,
38506ece 857 * if done here sec DHCP will fail
2c333366
MM		 858 * skb_trim(skb, skb->len - 4);
859 */
860
38506ece
LF		 861 hdr = rtl_get_hdr(skb);
862 fc = rtl_get_fc(skb);
863
864 if (!stats.crc && !stats.hwerror) {
865 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
866 sizeof(rx_status));
867
868 if (is_broadcast_ether_addr(hdr->addr1)) {
869 ;/*TODO*/
870 } else if (is_multicast_ether_addr(hdr->addr1)) {
871 ;/*TODO*/
872 } else {
873 unicast = true;
874 rtlpriv->stats.rxbytesunicast += skb->len;
875 }
cad737df 876 rtl_is_special_data(hw, skb, false, true);
0c817338 877
38506ece
LF		 878 if (ieee80211_is_data(fc)) {
879 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
880 if (unicast)
881 rtlpriv->link_info.num_rx_inperiod++;
882 }
883 /* static bcn for roaming */
884 rtl_beacon_statistic(hw, skb);
885 rtl_p2p_info(hw, (void *)skb->data, skb->len);
886 /* for sw lps */
887 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
888 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
889 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
890 (rtlpriv->rtlhal.current_bandtype ==
891 BAND_ON_2_4G) &&
892 (ieee80211_is_beacon(fc) ||
893 ieee80211_is_probe_resp(fc))) {
894 dev_kfree_skb_any(skb);
895 } else {
896 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
897 }
898 } else {
899 dev_kfree_skb_any(skb);
900 }
d0311314 901new_trx_end:
38506ece
LF		 902 if (rtlpriv->use_new_trx_flow) {
903 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
904 rtlpci->rx_ring[hw_queue].next_rx_rp %=
905 RTL_PCI_MAX_RX_COUNT;
906
907 rx_remained_cnt--;
908 rtl_write_word(rtlpriv, 0x3B4,
909 rtlpci->rx_ring[hw_queue].next_rx_rp);
910 }
2c333366 911 if (((rtlpriv->link_info.num_rx_inperiod +
a269913c 912 rtlpriv->link_info.num_tx_inperiod) > 8) ||
ba9f93f8
LF		 913 (rtlpriv->link_info.num_rx_inperiod > 2))
914 rtl_lps_leave(hw);
e9538cf4
LF		 915 skb = new_skb;
916no_new:
38506ece 917 if (rtlpriv->use_new_trx_flow) {
e9538cf4 918 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
38506ece 919 rxring_idx,
e9538cf4 920 rtlpci->rx_ring[rxring_idx].idx);
38506ece 921 } else {
e9538cf4
LF		 922 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
923 rxring_idx,
38506ece 924 rtlpci->rx_ring[rxring_idx].idx);
38506ece
LF		 925 if (rtlpci->rx_ring[rxring_idx].idx ==
926 rtlpci->rxringcount - 1)
927 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
928 false,
929 HW_DESC_RXERO,
930 (u8 *)&tmp_one);
931 }
932 rtlpci->rx_ring[rxring_idx].idx =
933 (rtlpci->rx_ring[rxring_idx].idx + 1) %
934 rtlpci->rxringcount;
0c817338 935 }
0c817338
LF		 936}
937
0c817338
LF		 938static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
939{
940 struct ieee80211_hw *hw = dev_id;
38506ece 941 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338 942 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 943 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 944 unsigned long flags;
945 u32 inta = 0;
946 u32 intb = 0;
de2e56ce 947 irqreturn_t ret = IRQ_HANDLED;
0c817338 948
38506ece
LF		 949 if (rtlpci->irq_enabled == 0)
950 return ret;
951
952 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags);
953 rtlpriv->cfg->ops->disable_interrupt(hw);
0c817338
LF		 954
955 /*read ISR: 4/8bytes */
956 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
957
958 /*Shared IRQ or HW disappared */
0529c6b8 959 if (!inta || inta == 0xffff)
0c817338
LF		 960 goto done;
961
962 /*<1> beacon related */
963 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
964 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 965 "beacon ok interrupt!\n");
0c817338
LF		 966 }
967
968 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
969 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 970 "beacon err interrupt!\n");
0c817338
LF		 971 }
972
973 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
f30d7507 974 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
0c817338
LF		 975 }
976
e6deaf81 977 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
0c817338 978 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 979 "prepare beacon for interrupt!\n");
0c817338
LF		 980 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
981 }
982
38506ece
LF		 983 /*<2> Tx related */
984 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
f30d7507 985 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
0c817338
LF		 986
987 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
988 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 989 "Manage ok interrupt!\n");
0c817338
LF		 990 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
991 }
992
993 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
994 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 995 "HIGH_QUEUE ok interrupt!\n");
0c817338
LF		 996 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
997 }
998
999 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
1000 rtlpriv->link_info.num_tx_inperiod++;
1001
1002 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1003 "BK Tx OK interrupt!\n");
0c817338
LF		 1004 _rtl_pci_tx_isr(hw, BK_QUEUE);
1005 }
1006
1007 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1008 rtlpriv->link_info.num_tx_inperiod++;
1009
1010 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1011 "BE TX OK interrupt!\n");
0c817338
LF		 1012 _rtl_pci_tx_isr(hw, BE_QUEUE);
1013 }
1014
1015 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1016 rtlpriv->link_info.num_tx_inperiod++;
1017
1018 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1019 "VI TX OK interrupt!\n");
0c817338
LF		 1020 _rtl_pci_tx_isr(hw, VI_QUEUE);
1021 }
1022
1023 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1024 rtlpriv->link_info.num_tx_inperiod++;
1025
1026 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1027 "Vo TX OK interrupt!\n");
0c817338
LF		 1028 _rtl_pci_tx_isr(hw, VO_QUEUE);
1029 }
1030
c7cfe38e
C		 1031 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1032 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1033 rtlpriv->link_info.num_tx_inperiod++;
1034
1035 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1036 "CMD TX OK interrupt!\n");
c7cfe38e
C		 1037 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1038 }
1039 }
1040
38506ece 1041 /*<3> Rx related */
0c817338 1042 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
f30d7507 1043 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
c7cfe38e 1044 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1045 }
1046
1047 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1048 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 1049 "rx descriptor unavailable!\n");
c7cfe38e 1050 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1051 }
1052
38506ece 1053 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
f30d7507 1054 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
c7cfe38e 1055 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1056 }
1057
38506ece 1058 /*<4> fw related*/
26634c4b
LF		 1059 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1060 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1061 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1062 "firmware interrupt!\n");
1063 queue_delayed_work(rtlpriv->works.rtl_wq,
1064 &rtlpriv->works.fwevt_wq, 0);
1065 }
1066 }
1067
38506ece
LF		 1068 /*<5> hsisr related*/
1069 /* Only 8188EE & 8723BE Supported.
1070 * If Other ICs Come in, System will corrupt,
1071 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1072 * are not initialized
1073 */
1074 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1075 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1076 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1077 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1078 "hsisr interrupt!\n");
1079 _rtl_pci_hs_interrupt(hw);
1080 }
1081 }
1082
c7cfe38e
C		 1083 if (rtlpriv->rtlhal.earlymode_enable)
1084 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1085
0c817338 1086done:
38506ece 1087 rtlpriv->cfg->ops->enable_interrupt(hw);
0c817338 1088 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
de2e56ce 1089 return ret;
0c817338
LF		 1090}
1091
1092static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1093{
c7cfe38e 1094 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 1095}
1096
1097static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1098{
1099 struct rtl_priv *rtlpriv = rtl_priv(hw);
1100 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1101 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 1102 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 1103 struct ieee80211_hdr *hdr = NULL;
1104 struct ieee80211_tx_info *info = NULL;
1105 struct sk_buff *pskb = NULL;
1106 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 1107 struct rtl_tcb_desc tcb_desc;
f3355dd9
LF		 1108 /*This is for new trx flow*/
1109 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
0c817338 1110 u8 temp_one = 1;
be0b5e63 1111 u8 *entry;
0c817338 1112
c7cfe38e 1113 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 1114 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1115 pskb = __skb_dequeue(&ring->queue);
be0b5e63
LF		 1116 if (rtlpriv->use_new_trx_flow)
1117 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1118 else
1119 entry = (u8 *)(&ring->desc[ring->idx]);
1120 if (pskb) {
1121 pci_unmap_single(rtlpci->pdev,
1122 rtlpriv->cfg->ops->get_desc(
1123 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1124 pskb->len, PCI_DMA_TODEVICE);
0c817338 1125 kfree_skb(pskb);
be0b5e63 1126 }
0c817338
LF		 1127
1128 /*NB: the beacon data buffer must be 32-bit aligned. */
1129 pskb = ieee80211_beacon_get(hw, mac->vif);
1130 if (pskb == NULL)
1131 return;
c7cfe38e 1132 hdr = rtl_get_hdr(pskb);
0c817338 1133 info = IEEE80211_SKB_CB(pskb);
0c817338 1134 pdesc = &ring->desc[0];
38506ece
LF		 1135 if (rtlpriv->use_new_trx_flow)
1136 pbuffer_desc = &ring->buffer_desc[0];
1137
1138 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
f3355dd9
LF		 1139 (u8 *)pbuffer_desc, info, NULL, pskb,
1140 BEACON_QUEUE, &tcb_desc);
0c817338
LF		 1141
1142 __skb_queue_tail(&ring->queue, pskb);
1143
fb6eaf2c
LF		 1144 if (rtlpriv->use_new_trx_flow) {
1145 temp_one = 4;
1146 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1147 HW_DESC_OWN, (u8 *)&temp_one);
1148 } else {
1149 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1150 &temp_one);
1151 }
0c817338
LF		 1152 return;
1153}
1154
1155static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1156{
1157 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece
LF		 1158 struct rtl_priv *rtlpriv = rtl_priv(hw);
1159 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
0c817338 1160 u8 i;
38506ece
LF		 1161 u16 desc_num;
1162
1163 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1164 desc_num = TX_DESC_NUM_92E;
1165 else
1166 desc_num = RT_TXDESC_NUM;
0c817338
LF		 1167
1168 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
38506ece 1169 rtlpci->txringcount[i] = desc_num;
0c817338
LF		 1170
1171 /*
1172 *we just alloc 2 desc for beacon queue,
1173 *because we just need first desc in hw beacon.
1174 */
1175 rtlpci->txringcount[BEACON_QUEUE] = 2;
1176
38506ece 1177 /*BE queue need more descriptor for performance
0c817338
LF		 1178 *consideration or, No more tx desc will happen,
1179 *and may cause mac80211 mem leakage.
1180 */
38506ece
LF		 1181 if (!rtl_priv(hw)->use_new_trx_flow)
1182 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
0c817338
LF		 1183
1184 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1185 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1186}
1187
1188static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1189 struct pci_dev *pdev)
1190{
1191 struct rtl_priv *rtlpriv = rtl_priv(hw);
1192 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1194 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 1195
1196 rtlpci->up_first_time = true;
1197 rtlpci->being_init_adapter = false;
1198
1199 rtlhal->hw = hw;
1200 rtlpci->pdev = pdev;
1201
0c817338
LF		 1202 /*Tx/Rx related var */
1203 _rtl_pci_init_trx_var(hw);
1204
37c52934
LF		 1205 /*IBSS*/
1206 mac->beacon_interval = 100;
0c817338 1207
c7cfe38e
C		 1208 /*AMPDU*/
1209 mac->min_space_cfg = 0;
0c817338
LF		 1210 mac->max_mss_density = 0;
1211 /*set sane AMPDU defaults */
1212 mac->current_ampdu_density = 7;
1213 mac->current_ampdu_factor = 3;
1214
8d0d43e3
PKS		 1215 /*Retry Limit*/
1216 mac->retry_short = 7;
1217 mac->retry_long = 7;
1218
c7cfe38e 1219 /*QOS*/
2cddad3c 1220 rtlpci->acm_method = EACMWAY2_SW;
0c817338
LF		 1221
1222 /*task */
1223 tasklet_init(&rtlpriv->works.irq_tasklet,
1224 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1225 (unsigned long)hw);
1226 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1227 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1228 (unsigned long)hw);
a269913c
LF		 1229 INIT_WORK(&rtlpriv->works.lps_change_work,
1230 rtl_lps_change_work_callback);
0c817338
LF		 1231}
1232
1233static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1234 unsigned int prio, unsigned int entries)
1235{
1236 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1237 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece
LF		 1238 struct rtl_tx_buffer_desc *buffer_desc;
1239 struct rtl_tx_desc *desc;
1240 dma_addr_t buffer_desc_dma, desc_dma;
0c817338
LF		 1241 u32 nextdescaddress;
1242 int i;
1243
38506ece
LF		 1244 /* alloc tx buffer desc for new trx flow*/
1245 if (rtlpriv->use_new_trx_flow) {
1246 buffer_desc =
1247 pci_zalloc_consistent(rtlpci->pdev,
1248 sizeof(*buffer_desc) * entries,
1249 &buffer_desc_dma);
1250
1251 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
b03d968b
LF		 1252 pr_err("Cannot allocate TX ring (prio = %d)\n",
1253 prio);
38506ece
LF		 1254 return -ENOMEM;
1255 }
1256
1257 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1258 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1259
1260 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1261 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1262 rtlpci->tx_ring[prio].avl_desc = entries;
1263 }
1264
1265 /* alloc dma for this ring */
1266 desc = pci_zalloc_consistent(rtlpci->pdev,
1267 sizeof(*desc) * entries, &desc_dma);
1268
1269 if (!desc || (unsigned long)desc & 0xFF) {
b03d968b 1270 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
0c817338
LF		 1271 return -ENOMEM;
1272 }
1273
38506ece
LF		 1274 rtlpci->tx_ring[prio].desc = desc;
1275 rtlpci->tx_ring[prio].dma = desc_dma;
1276
0c817338
LF		 1277 rtlpci->tx_ring[prio].idx = 0;
1278 rtlpci->tx_ring[prio].entries = entries;
1279 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1280
f30d7507 1281 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
38506ece
LF		 1282 prio, desc);
1283
1284 /* init every desc in this ring */
1285 if (!rtlpriv->use_new_trx_flow) {
1286 for (i = 0; i < entries; i++) {
1287 nextdescaddress = (u32)desc_dma +
1288 ((i + 1) % entries) *
1289 sizeof(*desc);
1290
1291 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1292 true,
1293 HW_DESC_TX_NEXTDESC_ADDR,
1294 (u8 *)&nextdescaddress);
1295 }
0c817338 1296 }
0c817338
LF		 1297 return 0;
1298}
1299
38506ece 1300static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
0c817338
LF		 1301{
1302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1303 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece 1304 int i;
0c817338 1305
38506ece
LF		 1306 if (rtlpriv->use_new_trx_flow) {
1307 struct rtl_rx_buffer_desc *entry = NULL;
1308 /* alloc dma for this ring */
1309 rtlpci->rx_ring[rxring_idx].buffer_desc =
1310 pci_zalloc_consistent(rtlpci->pdev,
1311 sizeof(*rtlpci->rx_ring[rxring_idx].
1312 buffer_desc) *
1313 rtlpci->rxringcount,
1314 &rtlpci->rx_ring[rxring_idx].dma);
1315 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1316 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
b03d968b 1317 pr_err("Cannot allocate RX ring\n");
0c817338
LF		 1318 return -ENOMEM;
1319 }
1320
38506ece
LF		 1321 /* init every desc in this ring */
1322 rtlpci->rx_ring[rxring_idx].idx = 0;
1323 for (i = 0; i < rtlpci->rxringcount; i++) {
1324 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
e9538cf4 1325 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
38506ece
LF		 1326 rxring_idx, i))
1327 return -ENOMEM;
1328 }
1329 } else {
1330 struct rtl_rx_desc *entry = NULL;
1331 u8 tmp_one = 1;
1332 /* alloc dma for this ring */
1333 rtlpci->rx_ring[rxring_idx].desc =
1334 pci_zalloc_consistent(rtlpci->pdev,
1335 sizeof(*rtlpci->rx_ring[rxring_idx].
1336 desc) * rtlpci->rxringcount,
1337 &rtlpci->rx_ring[rxring_idx].dma);
1338 if (!rtlpci->rx_ring[rxring_idx].desc ||
1339 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
b03d968b 1340 pr_err("Cannot allocate RX ring\n");
38506ece
LF		 1341 return -ENOMEM;
1342 }
0c817338 1343
38506ece
LF		 1344 /* init every desc in this ring */
1345 rtlpci->rx_ring[rxring_idx].idx = 0;
0019a2c9 1346
0c817338 1347 for (i = 0; i < rtlpci->rxringcount; i++) {
38506ece 1348 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
e9538cf4 1349 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
38506ece
LF		 1350 rxring_idx, i))
1351 return -ENOMEM;
0c817338
LF		 1352 }
1353
f3355dd9 1354 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
2c208890 1355 HW_DESC_RXERO, &tmp_one);
0c817338
LF		 1356 }
1357 return 0;
1358}
1359
1360static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1361 unsigned int prio)
1362{
1363 struct rtl_priv *rtlpriv = rtl_priv(hw);
1364 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1365 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1366
38506ece 1367 /* free every desc in this ring */
0c817338 1368 while (skb_queue_len(&ring->queue)) {
38506ece 1369 u8 *entry;
0c817338
LF		 1370 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1371
38506ece
LF		 1372 if (rtlpriv->use_new_trx_flow)
1373 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1374 else
1375 entry = (u8 *)(&ring->desc[ring->idx]);
1376
0c817338 1377 pci_unmap_single(rtlpci->pdev,
d3bb1429 1378 rtlpriv->cfg->
38506ece 1379 ops->get_desc((u8 *)entry, true,
d3bb1429 1380 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1381 skb->len, PCI_DMA_TODEVICE);
1382 kfree_skb(skb);
1383 ring->idx = (ring->idx + 1) % ring->entries;
1384 }
1385
38506ece
LF		 1386 /* free dma of this ring */
1387 pci_free_consistent(rtlpci->pdev,
1388 sizeof(*ring->desc) * ring->entries,
1389 ring->desc, ring->dma);
1390 ring->desc = NULL;
1391 if (rtlpriv->use_new_trx_flow) {
7f66c2f9 1392 pci_free_consistent(rtlpci->pdev,
caea2172 1393 sizeof(*ring->buffer_desc) * ring->entries,
38506ece 1394 ring->buffer_desc, ring->buffer_desc_dma);
caea2172 1395 ring->buffer_desc = NULL;
7f66c2f9 1396 }
0c817338
LF		 1397}
1398
38506ece 1399static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
0c817338 1400{
38506ece
LF		 1401 struct rtl_priv *rtlpriv = rtl_priv(hw);
1402 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1403 int i;
0c817338 1404
38506ece
LF		 1405 /* free every desc in this ring */
1406 for (i = 0; i < rtlpci->rxringcount; i++) {
1407 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
0c817338 1408
38506ece
LF		 1409 if (!skb)
1410 continue;
1411 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1412 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1413 kfree_skb(skb);
1414 }
1415
1416 /* free dma of this ring */
1417 if (rtlpriv->use_new_trx_flow) {
1418 pci_free_consistent(rtlpci->pdev,
1419 sizeof(*rtlpci->rx_ring[rxring_idx].
1420 buffer_desc) * rtlpci->rxringcount,
1421 rtlpci->rx_ring[rxring_idx].buffer_desc,
1422 rtlpci->rx_ring[rxring_idx].dma);
1423 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1424 } else {
1425 pci_free_consistent(rtlpci->pdev,
1426 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1427 rtlpci->rxringcount,
1428 rtlpci->rx_ring[rxring_idx].desc,
1429 rtlpci->rx_ring[rxring_idx].dma);
1430 rtlpci->rx_ring[rxring_idx].desc = NULL;
0c817338
LF		 1431 }
1432}
1433
1434static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1435{
1436 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1437 int ret;
38506ece 1438 int i, rxring_idx;
0c817338 1439
38506ece
LF		 1440 /* rxring_idx 0:RX_MPDU_QUEUE
1441 * rxring_idx 1:RX_CMD_QUEUE
1442 */
1443 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1444 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1445 if (ret)
1446 return ret;
1447 }
0c817338
LF		 1448
1449 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1450 ret = _rtl_pci_init_tx_ring(hw, i,
1451 rtlpci->txringcount[i]);
1452 if (ret)
1453 goto err_free_rings;
1454 }
1455
1456 return 0;
1457
1458err_free_rings:
38506ece
LF		 1459 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1460 _rtl_pci_free_rx_ring(hw, rxring_idx);
0c817338
LF		 1461
1462 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
38506ece
LF		 1463 if (rtlpci->tx_ring[i].desc ||
1464 rtlpci->tx_ring[i].buffer_desc)
0c817338
LF		 1465 _rtl_pci_free_tx_ring(hw, i);
1466
1467 return 1;
1468}
1469
1470static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1471{
38506ece 1472 u32 i, rxring_idx;
0c817338
LF		 1473
1474 /*free rx rings */
38506ece
LF		 1475 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1476 _rtl_pci_free_rx_ring(hw, rxring_idx);
0c817338
LF		 1477
1478 /*free tx rings */
1479 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1480 _rtl_pci_free_tx_ring(hw, i);
1481
1482 return 0;
1483}
1484
1485int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1486{
1487 struct rtl_priv *rtlpriv = rtl_priv(hw);
1488 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece 1489 int i, rxring_idx;
0c817338
LF		 1490 unsigned long flags;
1491 u8 tmp_one = 1;
38506ece
LF		 1492 u32 bufferaddress;
1493 /* rxring_idx 0:RX_MPDU_QUEUE */
1494 /* rxring_idx 1:RX_CMD_QUEUE */
1495 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1496 /* force the rx_ring[RX_MPDU_QUEUE/
1497 * RX_CMD_QUEUE].idx to the first one
1498 *new trx flow, do nothing
1499 */
1500 if (!rtlpriv->use_new_trx_flow &&
1501 rtlpci->rx_ring[rxring_idx].desc) {
0c817338
LF		 1502 struct rtl_rx_desc *entry = NULL;
1503
38506ece 1504 rtlpci->rx_ring[rxring_idx].idx = 0;
0c817338 1505 for (i = 0; i < rtlpci->rxringcount; i++) {
38506ece
LF		 1506 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1507 bufferaddress =
1508 rtlpriv->cfg->ops->get_desc((u8 *)entry,
1509 false , HW_DESC_RXBUFF_ADDR);
1510 memset((u8 *)entry , 0 ,
1511 sizeof(*rtlpci->rx_ring
1512 [rxring_idx].desc));/*clear one entry*/
1513 if (rtlpriv->use_new_trx_flow) {
1514 rtlpriv->cfg->ops->set_desc(hw,
1515 (u8 *)entry, false,
1516 HW_DESC_RX_PREPARE,
1517 (u8 *)&bufferaddress);
1518 } else {
1519 rtlpriv->cfg->ops->set_desc(hw,
1520 (u8 *)entry, false,
1521 HW_DESC_RXBUFF_ADDR,
1522 (u8 *)&bufferaddress);
1523 rtlpriv->cfg->ops->set_desc(hw,
1524 (u8 *)entry, false,
1525 HW_DESC_RXPKT_LEN,
1526 (u8 *)&rtlpci->rxbuffersize);
1527 rtlpriv->cfg->ops->set_desc(hw,
1528 (u8 *)entry, false,
1529 HW_DESC_RXOWN,
1530 (u8 *)&tmp_one);
1531 }
0c817338 1532 }
38506ece
LF		 1533 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1534 HW_DESC_RXERO, (u8 *)&tmp_one);
0c817338 1535 }
38506ece 1536 rtlpci->rx_ring[rxring_idx].idx = 0;
0c817338
LF		 1537 }
1538
1539 /*
1540 *after reset, release previous pending packet,
1541 *and force the tx idx to the first one
1542 */
38506ece 1543 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1544 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
38506ece
LF		 1545 if (rtlpci->tx_ring[i].desc ||
1546 rtlpci->tx_ring[i].buffer_desc) {
0c817338
LF		 1547 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1548
1549 while (skb_queue_len(&ring->queue)) {
38506ece
LF		 1550 u8 *entry;
1551 struct sk_buff *skb =
1552 __skb_dequeue(&ring->queue);
1553 if (rtlpriv->use_new_trx_flow)
1554 entry = (u8 *)(&ring->buffer_desc
1555 [ring->idx]);
1556 else
1557 entry = (u8 *)(&ring->desc[ring->idx]);
0c817338
LF		 1558
1559 pci_unmap_single(rtlpci->pdev,
d3bb1429 1560 rtlpriv->cfg->ops->
0c817338
LF		 1561 get_desc((u8 *)
1562 entry,
1563 true,
d3bb1429 1564 HW_DESC_TXBUFF_ADDR),
0c817338 1565 skb->len, PCI_DMA_TODEVICE);
cf968937 1566 dev_kfree_skb_irq(skb);
38506ece 1567 ring->idx = (ring->idx + 1) % ring->entries;
0c817338
LF		 1568 }
1569 ring->idx = 0;
1570 }
1571 }
38506ece 1572 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1573
0c817338
LF		 1574 return 0;
1575}
1576
c7cfe38e 1577static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
36323f81 1578 struct ieee80211_sta *sta,
c7cfe38e 1579 struct sk_buff *skb)
0c817338 1580{
c7cfe38e 1581 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e
C		 1582 struct rtl_sta_info *sta_entry = NULL;
1583 u8 tid = rtl_get_tid(skb);
0f015453 1584 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 1585
1586 if (!sta)
1587 return false;
1588 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1589
1590 if (!rtlpriv->rtlhal.earlymode_enable)
1591 return false;
0f015453
LF		 1592 if (ieee80211_is_nullfunc(fc))
1593 return false;
1594 if (ieee80211_is_qos_nullfunc(fc))
1595 return false;
1596 if (ieee80211_is_pspoll(fc))
1597 return false;
c7cfe38e
C		 1598 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1599 return false;
1600 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1601 return false;
1602 if (tid > 7)
1603 return false;
1604
1605 /* maybe every tid should be checked */
1606 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1607 return false;
1608
1609 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1610 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1611 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1612
c7cfe38e 1613 return true;
0c817338
LF		 1614}
1615
36323f81
TH		 1616static int rtl_pci_tx(struct ieee80211_hw *hw,
1617 struct ieee80211_sta *sta,
1618 struct sk_buff *skb,
1619 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1620{
1621 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1622 struct rtl_sta_info *sta_entry = NULL;
0c817338
LF		 1623 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1624 struct rtl8192_tx_ring *ring;
1625 struct rtl_tx_desc *pdesc;
f3355dd9 1626 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
38506ece 1627 u16 idx;
c7cfe38e 1628 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1629 unsigned long flags;
c7cfe38e
C		 1630 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1631 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1632 u8 *pda_addr = hdr->addr1;
1633 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1634 /*ssn */
0c817338
LF		 1635 u8 tid = 0;
1636 u16 seq_number = 0;
1637 u8 own;
1638 u8 temp_one = 1;
1639
0f015453
LF		 1640 if (ieee80211_is_mgmt(fc))
1641 rtl_tx_mgmt_proc(hw, skb);
c7cfe38e
C		 1642
1643 if (rtlpriv->psc.sw_ps_enabled) {
1644 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1645 !ieee80211_has_pm(fc))
1646 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1647 }
0c817338 1648
c7cfe38e 1649 rtl_action_proc(hw, skb, true);
0c817338
LF		 1650
1651 if (is_multicast_ether_addr(pda_addr))
1652 rtlpriv->stats.txbytesmulticast += skb->len;
1653 else if (is_broadcast_ether_addr(pda_addr))
1654 rtlpriv->stats.txbytesbroadcast += skb->len;
1655 else
1656 rtlpriv->stats.txbytesunicast += skb->len;
1657
1658 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1659 ring = &rtlpci->tx_ring[hw_queue];
38506ece
LF		 1660 if (hw_queue != BEACON_QUEUE) {
1661 if (rtlpriv->use_new_trx_flow)
1662 idx = ring->cur_tx_wp;
1663 else
1664 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1665 ring->entries;
1666 } else {
0c817338 1667 idx = 0;
38506ece 1668 }
0c817338
LF		 1669
1670 pdesc = &ring->desc[idx];
f3355dd9
LF		 1671 if (rtlpriv->use_new_trx_flow) {
1672 ptx_bd_desc = &ring->buffer_desc[idx];
1673 } else {
1674 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
1675 true, HW_DESC_OWN);
0c817338 1676
f3355dd9
LF		 1677 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1678 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
4f4378de 1679 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
f3355dd9
LF		 1680 hw_queue, ring->idx, idx,
1681 skb_queue_len(&ring->queue));
0c817338 1682
f3355dd9
LF		 1683 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1684 flags);
1685 return skb->len;
1686 }
0c817338
LF		 1687 }
1688
d0311314
TT		 1689 if (rtlpriv->cfg->ops->get_available_desc &&
1690 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1691 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1692 "get_available_desc fail\n");
1693 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1694 flags);
1695 return skb->len;
1696 }
1697
0c817338 1698 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1699 tid = rtl_get_tid(skb);
1700 if (sta) {
1701 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1702 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1703 IEEE80211_SCTL_SEQ) >> 4;
1704 seq_number += 1;
1705
1706 if (!ieee80211_has_morefrags(hdr->frame_control))
1707 sta_entry->tids[tid].seq_number = seq_number;
1708 }
0c817338
LF		 1709 }
1710
1711 if (ieee80211_is_data(fc))
1712 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1713
c7cfe38e 1714 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
f3355dd9 1715 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
0c817338
LF		 1716
1717 __skb_queue_tail(&ring->queue, skb);
1718
f3355dd9
LF		 1719 if (rtlpriv->use_new_trx_flow) {
1720 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
9cb76aa9 1721 HW_DESC_OWN, &hw_queue);
f3355dd9
LF		 1722 } else {
1723 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
9cb76aa9 1724 HW_DESC_OWN, &temp_one);
f3355dd9 1725 }
0c817338
LF		 1726
1727 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1728 hw_queue != BEACON_QUEUE) {
0c817338 1729 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
4f4378de 1730 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
f30d7507
JP		 1731 hw_queue, ring->idx, idx,
1732 skb_queue_len(&ring->queue));
0c817338
LF		 1733
1734 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1735 }
1736
1737 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1738
1739 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1740
1741 return 0;
1742}
1743
38506ece 1744static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
c7cfe38e
C		 1745{
1746 struct rtl_priv *rtlpriv = rtl_priv(hw);
1747 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1748 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
26634c4b 1749 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e
C		 1750 u16 i = 0;
1751 int queue_id;
1752 struct rtl8192_tx_ring *ring;
1753
26634c4b
LF		 1754 if (mac->skip_scan)
1755 return;
1756
c7cfe38e
C		 1757 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1758 u32 queue_len;
38506ece
LF		 1759
1760 if (((queues >> queue_id) & 0x1) == 0) {
1761 queue_id--;
1762 continue;
1763 }
c7cfe38e
C		 1764 ring = &pcipriv->dev.tx_ring[queue_id];
1765 queue_len = skb_queue_len(&ring->queue);
1766 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1767 queue_id == TXCMD_QUEUE) {
1768 queue_id--;
1769 continue;
1770 } else {
1771 msleep(20);
1772 i++;
1773 }
1774
1775 /* we just wait 1s for all queues */
1776 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1777 is_hal_stop(rtlhal) || i >= 200)
1778 return;
1779 }
1780}
1781
d3bb1429 1782static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1783{
1784 struct rtl_priv *rtlpriv = rtl_priv(hw);
1785 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1786
1787 _rtl_pci_deinit_trx_ring(hw);
1788
1789 synchronize_irq(rtlpci->pdev->irq);
1790 tasklet_kill(&rtlpriv->works.irq_tasklet);
a269913c 1791 cancel_work_sync(&rtlpriv->works.lps_change_work);
0c817338
LF		 1792
1793 flush_workqueue(rtlpriv->works.rtl_wq);
1794 destroy_workqueue(rtlpriv->works.rtl_wq);
1795
1796}
1797
d3bb1429 1798static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338 1799{
0c817338
LF		 1800 int err;
1801
1802 _rtl_pci_init_struct(hw, pdev);
1803
1804 err = _rtl_pci_init_trx_ring(hw);
1805 if (err) {
b03d968b 1806 pr_err("tx ring initialization failed\n");
12325280 1807 return err;
0c817338
LF		 1808 }
1809
12325280 1810 return 0;
0c817338
LF		 1811}
1812
d3bb1429 1813static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1814{
1815 struct rtl_priv *rtlpriv = rtl_priv(hw);
1816 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1817 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1818 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
8d0d43e3 1819 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
0c817338
LF		 1820
1821 int err;
1822
1823 rtl_pci_reset_trx_ring(hw);
1824
1825 rtlpci->driver_is_goingto_unload = false;
08054200
LF		 1826 if (rtlpriv->cfg->ops->get_btc_status &&
1827 rtlpriv->cfg->ops->get_btc_status()) {
38506ece
LF		 1828 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
1829 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
1830 }
0c817338
LF		 1831 err = rtlpriv->cfg->ops->hw_init(hw);
1832 if (err) {
1833 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507 1834 "Failed to config hardware!\n");
0c817338
LF		 1835 return err;
1836 }
8d0d43e3
PKS		 1837 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1838 &rtlmac->retry_long);
0c817338
LF		 1839
1840 rtlpriv->cfg->ops->enable_interrupt(hw);
f30d7507 1841 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
0c817338
LF		 1842
1843 rtl_init_rx_config(hw);
1844
fb914ebf 1845 /*should be after adapter start and interrupt enable. */
0c817338
LF		 1846 set_hal_start(rtlhal);
1847
1848 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1849
1850 rtlpci->up_first_time = false;
1851
38506ece 1852 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n");
0c817338
LF		 1853 return 0;
1854}
1855
d3bb1429 1856static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1857{
1858 struct rtl_priv *rtlpriv = rtl_priv(hw);
1859 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1860 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1861 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1862 unsigned long flags;
1863 u8 RFInProgressTimeOut = 0;
1864
38506ece
LF		 1865 if (rtlpriv->cfg->ops->get_btc_status())
1866 rtlpriv->btcoexist.btc_ops->btc_halt_notify();
1867
0c817338 1868 /*
fb914ebf 1869 *should be before disable interrupt&adapter
0c817338
LF		 1870 *and will do it immediately.
1871 */
1872 set_hal_stop(rtlhal);
1873
9278db62 1874 rtlpci->driver_is_goingto_unload = true;
0c817338 1875 rtlpriv->cfg->ops->disable_interrupt(hw);
a269913c 1876 cancel_work_sync(&rtlpriv->works.lps_change_work);
0c817338
LF		 1877
1878 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1879 while (ppsc->rfchange_inprogress) {
1880 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1881 if (RFInProgressTimeOut > 100) {
1882 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1883 break;
1884 }
1885 mdelay(1);
1886 RFInProgressTimeOut++;
1887 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1888 }
1889 ppsc->rfchange_inprogress = true;
1890 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1891
0c817338 1892 rtlpriv->cfg->ops->hw_disable(hw);
b0302aba
LF		 1893 /* some things are not needed if firmware not available */
1894 if (!rtlpriv->max_fw_size)
1895 return;
0c817338
LF		 1896 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1897
1898 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1899 ppsc->rfchange_inprogress = false;
1900 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1901
1902 rtl_pci_enable_aspm(hw);
1903}
1904
1905static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1906 struct ieee80211_hw *hw)
1907{
1908 struct rtl_priv *rtlpriv = rtl_priv(hw);
1909 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1911 struct pci_dev *bridge_pdev = pdev->bus->self;
1912 u16 venderid;
1913 u16 deviceid;
c7cfe38e 1914 u8 revisionid;
0c817338
LF		 1915 u16 irqline;
1916 u8 tmp;
1917
fc7707a4 1918 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
0c817338
LF		 1919 venderid = pdev->vendor;
1920 deviceid = pdev->device;
c7cfe38e 1921 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1922 pci_read_config_word(pdev, 0x3C, &irqline);
1923
fa7ccfb1
LF		 1924 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1925 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1926 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1927 * the correct driver is r8192e_pci, thus this routine should
1928 * return false.
1929 */
1930 if (deviceid == RTL_PCI_8192SE_DID &&
1931 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1932 return false;
1933
0c817338
LF		 1934 if (deviceid == RTL_PCI_8192_DID ||
1935 deviceid == RTL_PCI_0044_DID ||
1936 deviceid == RTL_PCI_0047_DID ||
1937 deviceid == RTL_PCI_8192SE_DID ||
1938 deviceid == RTL_PCI_8174_DID ||
1939 deviceid == RTL_PCI_8173_DID ||
1940 deviceid == RTL_PCI_8172_DID ||
1941 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1942 switch (revisionid) {
0c817338
LF		 1943 case RTL_PCI_REVISION_ID_8192PCIE:
1944 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1945 "8192 PCI-E is found - vid/did=%x/%x\n",
1946 venderid, deviceid);
0c817338 1947 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
0f015453 1948 return false;
0c817338
LF		 1949 case RTL_PCI_REVISION_ID_8192SE:
1950 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1951 "8192SE is found - vid/did=%x/%x\n",
1952 venderid, deviceid);
0c817338
LF		 1953 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1954 break;
1955 default:
1956 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1957 "Err: Unknown device - vid/did=%x/%x\n",
1958 venderid, deviceid);
0c817338
LF		 1959 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1960 break;
1961
1962 }
0f015453
LF		 1963 } else if (deviceid == RTL_PCI_8723AE_DID) {
1964 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1965 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1966 "8723AE PCI-E is found - "
1967 "vid/did=%x/%x\n", venderid, deviceid);
0c817338
LF		 1968 } else if (deviceid == RTL_PCI_8192CET_DID ||
1969 deviceid == RTL_PCI_8192CE_DID ||
1970 deviceid == RTL_PCI_8191CE_DID ||
1971 deviceid == RTL_PCI_8188CE_DID) {
1972 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1973 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1974 "8192C PCI-E is found - vid/did=%x/%x\n",
1975 venderid, deviceid);
c7cfe38e
C		 1976 } else if (deviceid == RTL_PCI_8192DE_DID ||
1977 deviceid == RTL_PCI_8192DE_DID2) {
1978 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1979 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1980 "8192D PCI-E is found - vid/did=%x/%x\n",
1981 venderid, deviceid);
5c69177d
LF		 1982 } else if (deviceid == RTL_PCI_8188EE_DID) {
1983 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1984 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1985 "Find adapter, Hardware type is 8188EE\n");
38506ece
LF		 1986 } else if (deviceid == RTL_PCI_8723BE_DID) {
1987 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1988 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1989 "Find adapter, Hardware type is 8723BE\n");
1990 } else if (deviceid == RTL_PCI_8192EE_DID) {
1991 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1992 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1993 "Find adapter, Hardware type is 8192EE\n");
1994 } else if (deviceid == RTL_PCI_8821AE_DID) {
1995 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1996 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1997 "Find adapter, Hardware type is 8821AE\n");
1998 } else if (deviceid == RTL_PCI_8812AE_DID) {
1999 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
2000 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
2001 "Find adapter, Hardware type is 8812AE\n");
0c817338
LF		 2002 } else {
2003 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 2004 "Err: Unknown device - vid/did=%x/%x\n",
2005 venderid, deviceid);
0c817338
LF		 2006
2007 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
2008 }
2009
c7cfe38e
C		 2010 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
2011 if (revisionid == 0 || revisionid == 1) {
2012 if (revisionid == 0) {
f30d7507
JP		 2013 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2014 "Find 92DE MAC0\n");
c7cfe38e
C		 2015 rtlhal->interfaceindex = 0;
2016 } else if (revisionid == 1) {
2017 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 2018 "Find 92DE MAC1\n");
c7cfe38e
C		 2019 rtlhal->interfaceindex = 1;
2020 }
2021 } else {
2022 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 2023 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
2024 venderid, deviceid, revisionid);
c7cfe38e
C		 2025 rtlhal->interfaceindex = 0;
2026 }
2027 }
38506ece
LF		 2028
2029 /* 92ee use new trx flow */
2030 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
2031 rtlpriv->use_new_trx_flow = true;
2032 else
2033 rtlpriv->use_new_trx_flow = false;
2034
0c817338
LF		 2035 /*find bus info */
2036 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2037 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2038 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2039
38506ece
LF		 2040 /*find bridge info */
2041 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
26634c4b
LF		 2042 /* some ARM have no bridge_pdev and will crash here
2043 * so we should check if bridge_pdev is NULL
2044 */
b6b67df3
LF		 2045 if (bridge_pdev) {
2046 /*find bridge info if available */
2047 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2048 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2049 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2050 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2051 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2052 "Pci Bridge Vendor is found index: %d\n",
2053 tmp);
b6b67df3
LF		 2054 break;
2055 }
0c817338
LF		 2056 }
2057 }
2058
2059 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2060 PCI_BRIDGE_VENDOR_UNKNOWN) {
2061 pcipriv->ndis_adapter.pcibridge_busnum =
2062 bridge_pdev->bus->number;
2063 pcipriv->ndis_adapter.pcibridge_devnum =
2064 PCI_SLOT(bridge_pdev->devfn);
2065 pcipriv->ndis_adapter.pcibridge_funcnum =
2066 PCI_FUNC(bridge_pdev->devfn);
c7cfe38e
C		 2067 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2068 pci_pcie_cap(bridge_pdev);
0c817338
LF		 2069 pcipriv->ndis_adapter.num4bytes =
2070 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2071
2072 rtl_pci_get_linkcontrol_field(hw);
2073
2074 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2075 PCI_BRIDGE_VENDOR_AMD) {
2076 pcipriv->ndis_adapter.amd_l1_patch =
2077 rtl_pci_get_amd_l1_patch(hw);
2078 }
2079 }
2080
2081 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2082 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2083 pcipriv->ndis_adapter.busnumber,
2084 pcipriv->ndis_adapter.devnumber,
2085 pcipriv->ndis_adapter.funcnumber,
2086 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 2087
2088 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2089 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2090 pcipriv->ndis_adapter.pcibridge_busnum,
2091 pcipriv->ndis_adapter.pcibridge_devnum,
2092 pcipriv->ndis_adapter.pcibridge_funcnum,
2093 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2094 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2095 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2096 pcipriv->ndis_adapter.amd_l1_patch);
0c817338
LF		 2097
2098 rtl_pci_parse_configuration(pdev, hw);
26634c4b 2099 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
0c817338
LF		 2100
2101 return true;
2102}
2103
94010fa0
AL		 2104static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2105{
2106 struct rtl_priv *rtlpriv = rtl_priv(hw);
2107 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2108 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2109 int ret;
2110
2111 ret = pci_enable_msi(rtlpci->pdev);
2112 if (ret < 0)
2113 return ret;
2114
2115 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2116 IRQF_SHARED, KBUILD_MODNAME, hw);
2117 if (ret < 0) {
2118 pci_disable_msi(rtlpci->pdev);
2119 return ret;
2120 }
2121
2122 rtlpci->using_msi = true;
2123
2124 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
2125 "MSI Interrupt Mode!\n");
2126 return 0;
2127}
2128
2129static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2130{
2131 struct rtl_priv *rtlpriv = rtl_priv(hw);
2132 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2133 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2134 int ret;
2135
2136 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2137 IRQF_SHARED, KBUILD_MODNAME, hw);
2138 if (ret < 0)
2139 return ret;
2140
2141 rtlpci->using_msi = false;
2142 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
2143 "Pin-based Interrupt Mode!\n");
2144 return 0;
2145}
2146
2147static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2148{
2149 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2150 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2151 int ret;
2152
2153 if (rtlpci->msi_support) {
2154 ret = rtl_pci_intr_mode_msi(hw);
2155 if (ret < 0)
2156 ret = rtl_pci_intr_mode_legacy(hw);
2157 } else {
2158 ret = rtl_pci_intr_mode_legacy(hw);
2159 }
2160 return ret;
2161}
2162
9e2ff36b 2163int rtl_pci_probe(struct pci_dev *pdev,
0c817338
LF		 2164 const struct pci_device_id *id)
2165{
2166 struct ieee80211_hw *hw = NULL;
2167
2168 struct rtl_priv *rtlpriv = NULL;
2169 struct rtl_pci_priv *pcipriv = NULL;
2170 struct rtl_pci *rtlpci;
2171 unsigned long pmem_start, pmem_len, pmem_flags;
2172 int err;
2173
2174 err = pci_enable_device(pdev);
2175 if (err) {
531940f9 2176 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
9d833ed7 2177 pci_name(pdev));
0c817338
LF		 2178 return err;
2179 }
2180
2181 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2182 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
531940f9
LF		 2183 WARN_ONCE(true,
2184 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
3d86b930
TG		 2185 err = -ENOMEM;
2186 goto fail1;
0c817338
LF		 2187 }
2188 }
2189
2190 pci_set_master(pdev);
2191
2192 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2193 sizeof(struct rtl_priv), &rtl_ops);
2194 if (!hw) {
531940f9 2195 WARN_ONCE(true,
9d833ed7 2196 "%s : ieee80211 alloc failed\n", pci_name(pdev));
0c817338
LF		 2197 err = -ENOMEM;
2198 goto fail1;
2199 }
2200
2201 SET_IEEE80211_DEV(hw, &pdev->dev);
2202 pci_set_drvdata(pdev, hw);
2203
2204 rtlpriv = hw->priv;
26634c4b 2205 rtlpriv->hw = hw;
0c817338
LF		 2206 pcipriv = (void *)rtlpriv->priv;
2207 pcipriv->dev.pdev = pdev;
b0302aba 2208 init_completion(&rtlpriv->firmware_loading_complete);
38506ece
LF		 2209 /*proximity init here*/
2210 rtlpriv->proximity.proxim_on = false;
2211
2212 pcipriv = (void *)rtlpriv->priv;
2213 pcipriv->dev.pdev = pdev;
0c817338 2214
c7cfe38e
C		 2215 /* init cfg & intf_ops */
2216 rtlpriv->rtlhal.interface = INTF_PCI;
2217 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2218 rtlpriv->intf_ops = &rtl_pci_ops;
6f334c2b 2219 rtlpriv->glb_var = &rtl_global_var;
c7cfe38e 2220
0c817338
LF		 2221 /* MEM map */
2222 err = pci_request_regions(pdev, KBUILD_MODNAME);
2223 if (err) {
531940f9 2224 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
3d86b930 2225 goto fail1;
0c817338
LF		 2226 }
2227
c7cfe38e
C		 2228 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2229 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2230 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 2231
2232 /*shared mem start */
2233 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 2234 (unsigned long)pci_iomap(pdev,
2235 rtlpriv->cfg->bar_id, pmem_len);
0c817338 2236 if (rtlpriv->io.pci_mem_start == 0) {
531940f9 2237 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
3d86b930 2238 err = -ENOMEM;
0c817338
LF		 2239 goto fail2;
2240 }
2241
2242 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2243 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2244 pmem_start, pmem_len, pmem_flags,
2245 rtlpriv->io.pci_mem_start);
0c817338
LF		 2246
2247 /* Disable Clk Request */
2248 pci_write_config_byte(pdev, 0x81, 0);
2249 /* leave D3 mode */
2250 pci_write_config_byte(pdev, 0x44, 0);
2251 pci_write_config_byte(pdev, 0x04, 0x06);
2252 pci_write_config_byte(pdev, 0x04, 0x07);
2253
0c817338 2254 /* find adapter */
3d86b930
TG		 2255 if (!_rtl_pci_find_adapter(pdev, hw)) {
2256 err = -ENODEV;
fa7ccfb1 2257 goto fail3;
3d86b930 2258 }
0c817338
LF		 2259
2260 /* Init IO handler */
2261 _rtl_pci_io_handler_init(&pdev->dev, hw);
2262
2263 /*like read eeprom and so on */
2264 rtlpriv->cfg->ops->read_eeprom_info(hw);
2265
7d63a5f9 2266 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
b03d968b 2267 pr_err("Can't init_sw_vars\n");
7d63a5f9
LF		 2268 err = -ENODEV;
2269 goto fail3;
2270 }
2271 rtlpriv->cfg->ops->init_sw_leds(hw);
2272
2273 /*aspm */
2274 rtl_pci_init_aspm(hw);
2275
0c817338
LF		 2276 /* Init mac80211 sw */
2277 err = rtl_init_core(hw);
2278 if (err) {
b03d968b 2279 pr_err("Can't allocate sw for mac80211\n");
0c817338
LF		 2280 goto fail3;
2281 }
2282
2283 /* Init PCI sw */
12325280 2284 err = rtl_pci_init(hw, pdev);
0c817338 2285 if (err) {
b03d968b 2286 pr_err("Failed to init PCI\n");
0c817338
LF		 2287 goto fail3;
2288 }
2289
38506ece
LF		 2290 err = ieee80211_register_hw(hw);
2291 if (err) {
b03d968b 2292 pr_err("Can't register mac80211 hw.\n");
574e02ab
LF		 2293 err = -ENODEV;
2294 goto fail3;
2295 }
38506ece 2296 rtlpriv->mac80211.mac80211_registered = 1;
574e02ab 2297
38506ece
LF		 2298 /*init rfkill */
2299 rtl_init_rfkill(hw); /* Init PCI sw */
2300
0c817338 2301 rtlpci = rtl_pcidev(pcipriv);
94010fa0 2302 err = rtl_pci_intr_mode_decide(hw);
0c817338
LF		 2303 if (err) {
2304 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2305 "%s: failed to register IRQ handler\n",
2306 wiphy_name(hw->wiphy));
0c817338 2307 goto fail3;
0c817338 2308 }
b0302aba 2309 rtlpci->irq_alloc = 1;
0c817338 2310
38506ece 2311 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
0c817338
LF		 2312 return 0;
2313
2314fail3:
38506ece 2315 pci_set_drvdata(pdev, NULL);
0c817338 2316 rtl_deinit_core(hw);
0c817338
LF		 2317
2318 if (rtlpriv->io.pci_mem_start != 0)
62e63975 2319 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 2320
2321fail2:
2322 pci_release_regions(pdev);
b0302aba 2323 complete(&rtlpriv->firmware_loading_complete);
0c817338
LF		 2324
2325fail1:
3d86b930
TG		 2326 if (hw)
2327 ieee80211_free_hw(hw);
0c817338
LF		 2328 pci_disable_device(pdev);
2329
3d86b930 2330 return err;
0c817338
LF		 2331
2332}
2333EXPORT_SYMBOL(rtl_pci_probe);
2334
2335void rtl_pci_disconnect(struct pci_dev *pdev)
2336{
2337 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2338 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2339 struct rtl_priv *rtlpriv = rtl_priv(hw);
2340 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2341 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2342
b0302aba
LF		 2343 /* just in case driver is removed before firmware callback */
2344 wait_for_completion(&rtlpriv->firmware_loading_complete);
0c817338
LF		 2345 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2346
0c817338
LF		 2347 /*ieee80211_unregister_hw will call ops_stop */
2348 if (rtlmac->mac80211_registered == 1) {
2349 ieee80211_unregister_hw(hw);
2350 rtlmac->mac80211_registered = 0;
2351 } else {
2352 rtl_deinit_deferred_work(hw);
2353 rtlpriv->intf_ops->adapter_stop(hw);
2354 }
44eb65cf 2355 rtlpriv->cfg->ops->disable_interrupt(hw);
0c817338
LF		 2356
2357 /*deinit rfkill */
2358 rtl_deinit_rfkill(hw);
2359
2360 rtl_pci_deinit(hw);
2361 rtl_deinit_core(hw);
0c817338
LF		 2362 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2363
2364 if (rtlpci->irq_alloc) {
2365 free_irq(rtlpci->pdev->irq, hw);
2366 rtlpci->irq_alloc = 0;
2367 }
2368
94010fa0
AL		 2369 if (rtlpci->using_msi)
2370 pci_disable_msi(rtlpci->pdev);
2371
26634c4b 2372 list_del(&rtlpriv->list);
0c817338 2373 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 2374 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 2375 pci_release_regions(pdev);
2376 }
2377
2378 pci_disable_device(pdev);
c7cfe38e
C		 2379
2380 rtl_pci_disable_aspm(hw);
2381
38506ece
LF		 2382 pci_set_drvdata(pdev, NULL);
2383
0c817338
LF		 2384 ieee80211_free_hw(hw);
2385}
2386EXPORT_SYMBOL(rtl_pci_disconnect);
2387
244a77e9 2388#ifdef CONFIG_PM_SLEEP
0c817338
LF		 2389/***************************************
2390kernel pci power state define:
2391PCI_D0 ((pci_power_t __force) 0)
2392PCI_D1 ((pci_power_t __force) 1)
2393PCI_D2 ((pci_power_t __force) 2)
2394PCI_D3hot ((pci_power_t __force) 3)
2395PCI_D3cold ((pci_power_t __force) 4)
2396PCI_UNKNOWN ((pci_power_t __force) 5)
2397
2398This function is called when system
2399goes into suspend state mac80211 will
2400call rtl_mac_stop() from the mac80211
2401suspend function first, So there is
2402no need to call hw_disable here.
2403****************************************/
603be388 2404int rtl_pci_suspend(struct device *dev)
0c817338 2405{
603be388 2406 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2407 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2408 struct rtl_priv *rtlpriv = rtl_priv(hw);
2409
2410 rtlpriv->cfg->ops->hw_suspend(hw);
2411 rtl_deinit_rfkill(hw);
2412
0c817338
LF		 2413 return 0;
2414}
2415EXPORT_SYMBOL(rtl_pci_suspend);
2416
603be388 2417int rtl_pci_resume(struct device *dev)
0c817338 2418{
603be388 2419 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2420 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2421 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338 2422
c7cfe38e
C		 2423 rtlpriv->cfg->ops->hw_resume(hw);
2424 rtl_init_rfkill(hw);
0c817338
LF		 2425 return 0;
2426}
2427EXPORT_SYMBOL(rtl_pci_resume);
244a77e9 2428#endif /* CONFIG_PM_SLEEP */
0c817338 2429
1bfcfdcc 2430const struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2431 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2432 .adapter_start = rtl_pci_start,
2433 .adapter_stop = rtl_pci_stop,
26634c4b 2434 .check_buddy_priv = rtl_pci_check_buddy_priv,
0c817338 2435 .adapter_tx = rtl_pci_tx,
c7cfe38e 2436 .flush = rtl_pci_flush,
0c817338 2437 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2438 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2439
2440 .disable_aspm = rtl_pci_disable_aspm,
2441 .enable_aspm = rtl_pci_enable_aspm,
2442};
Linux 6.x block layer and io_uring tree(s)