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95ea3627 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
a05b8c58 | 16 | along with this program; if not, see <http://www.gnu.org/licenses/>. |
95ea3627 ID |
17 | */ |
18 | ||
19 | /* | |
20 | Module: rt61pci | |
21 | Abstract: rt61pci device specific routines. | |
22 | Supported chipsets: RT2561, RT2561s, RT2661. | |
23 | */ | |
24 | ||
a7f3a06c | 25 | #include <linux/crc-itu-t.h> |
95ea3627 ID |
26 | #include <linux/delay.h> |
27 | #include <linux/etherdevice.h> | |
95ea3627 ID |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
95ea3627 ID |
31 | #include <linux/pci.h> |
32 | #include <linux/eeprom_93cx6.h> | |
33 | ||
34 | #include "rt2x00.h" | |
69a2bac8 | 35 | #include "rt2x00mmio.h" |
95ea3627 ID |
36 | #include "rt2x00pci.h" |
37 | #include "rt61pci.h" | |
38 | ||
008c4482 ID |
39 | /* |
40 | * Allow hardware encryption to be disabled. | |
41 | */ | |
eb939922 | 42 | static bool modparam_nohwcrypt = false; |
008c4482 ID |
43 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
44 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); | |
45 | ||
95ea3627 ID |
46 | /* |
47 | * Register access. | |
48 | * BBP and RF register require indirect register access, | |
49 | * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this. | |
50 | * These indirect registers work with busy bits, | |
51 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
52 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
b34e620f | 53 | * between each attempt. When the busy bit is still set at that time, |
95ea3627 ID |
54 | * the access attempt is considered to have failed, |
55 | * and we will print an error. | |
56 | */ | |
c9c3b1a5 | 57 | #define WAIT_FOR_BBP(__dev, __reg) \ |
1d6205d0 | 58 | rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) |
c9c3b1a5 | 59 | #define WAIT_FOR_RF(__dev, __reg) \ |
1d6205d0 | 60 | rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) |
c9c3b1a5 | 61 | #define WAIT_FOR_MCU(__dev, __reg) \ |
1d6205d0 GJ |
62 | rt2x00mmio_regbusy_read((__dev), H2M_MAILBOX_CSR, \ |
63 | H2M_MAILBOX_CSR_OWNER, (__reg)) | |
95ea3627 | 64 | |
0e14f6d3 | 65 | static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
66 | const unsigned int word, const u8 value) |
67 | { | |
68 | u32 reg; | |
69 | ||
8ff48a8b ID |
70 | mutex_lock(&rt2x00dev->csr_mutex); |
71 | ||
95ea3627 | 72 | /* |
c9c3b1a5 ID |
73 | * Wait until the BBP becomes available, afterwards we |
74 | * can safely write the new data into the register. | |
95ea3627 | 75 | */ |
c9c3b1a5 ID |
76 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
77 | reg = 0; | |
78 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); | |
79 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
80 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
81 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); | |
82 | ||
1d6205d0 | 83 | rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); |
c9c3b1a5 | 84 | } |
8ff48a8b | 85 | |
8ff48a8b | 86 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
87 | } |
88 | ||
0e14f6d3 | 89 | static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
90 | const unsigned int word, u8 *value) |
91 | { | |
92 | u32 reg; | |
93 | ||
8ff48a8b ID |
94 | mutex_lock(&rt2x00dev->csr_mutex); |
95 | ||
95ea3627 | 96 | /* |
c9c3b1a5 ID |
97 | * Wait until the BBP becomes available, afterwards we |
98 | * can safely write the read request into the register. | |
99 | * After the data has been written, we wait until hardware | |
100 | * returns the correct value, if at any time the register | |
101 | * doesn't become available in time, reg will be 0xffffffff | |
102 | * which means we return 0xff to the caller. | |
95ea3627 | 103 | */ |
c9c3b1a5 ID |
104 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
105 | reg = 0; | |
106 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
107 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
108 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); | |
95ea3627 | 109 | |
1d6205d0 | 110 | rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); |
95ea3627 | 111 | |
c9c3b1a5 ID |
112 | WAIT_FOR_BBP(rt2x00dev, ®); |
113 | } | |
95ea3627 ID |
114 | |
115 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); | |
8ff48a8b | 116 | |
8ff48a8b | 117 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
118 | } |
119 | ||
0e14f6d3 | 120 | static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
121 | const unsigned int word, const u32 value) |
122 | { | |
123 | u32 reg; | |
95ea3627 | 124 | |
8ff48a8b ID |
125 | mutex_lock(&rt2x00dev->csr_mutex); |
126 | ||
c9c3b1a5 ID |
127 | /* |
128 | * Wait until the RF becomes available, afterwards we | |
129 | * can safely write the new data into the register. | |
130 | */ | |
131 | if (WAIT_FOR_RF(rt2x00dev, ®)) { | |
132 | reg = 0; | |
133 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); | |
134 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); | |
135 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); | |
136 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); | |
137 | ||
1d6205d0 | 138 | rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); |
c9c3b1a5 | 139 | rt2x00_rf_write(rt2x00dev, word, value); |
95ea3627 ID |
140 | } |
141 | ||
8ff48a8b | 142 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
143 | } |
144 | ||
0e14f6d3 | 145 | static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
146 | const u8 command, const u8 token, |
147 | const u8 arg0, const u8 arg1) | |
148 | { | |
149 | u32 reg; | |
150 | ||
8ff48a8b ID |
151 | mutex_lock(&rt2x00dev->csr_mutex); |
152 | ||
c9c3b1a5 ID |
153 | /* |
154 | * Wait until the MCU becomes available, afterwards we | |
155 | * can safely write the new data into the register. | |
156 | */ | |
157 | if (WAIT_FOR_MCU(rt2x00dev, ®)) { | |
158 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); | |
159 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); | |
160 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); | |
161 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); | |
1d6205d0 | 162 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); |
c9c3b1a5 | 163 | |
1d6205d0 | 164 | rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, ®); |
c9c3b1a5 ID |
165 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); |
166 | rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); | |
1d6205d0 | 167 | rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); |
c9c3b1a5 | 168 | } |
8ff48a8b | 169 | |
8ff48a8b ID |
170 | mutex_unlock(&rt2x00dev->csr_mutex); |
171 | ||
95ea3627 ID |
172 | } |
173 | ||
174 | static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom) | |
175 | { | |
176 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
177 | u32 reg; | |
178 | ||
1d6205d0 | 179 | rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); |
95ea3627 ID |
180 | |
181 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); | |
182 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); | |
183 | eeprom->reg_data_clock = | |
184 | !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); | |
185 | eeprom->reg_chip_select = | |
186 | !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); | |
187 | } | |
188 | ||
189 | static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom) | |
190 | { | |
191 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
192 | u32 reg = 0; | |
193 | ||
194 | rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); | |
195 | rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); | |
196 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, | |
197 | !!eeprom->reg_data_clock); | |
198 | rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, | |
199 | !!eeprom->reg_chip_select); | |
200 | ||
1d6205d0 | 201 | rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); |
95ea3627 ID |
202 | } |
203 | ||
204 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
95ea3627 ID |
205 | static const struct rt2x00debug rt61pci_rt2x00debug = { |
206 | .owner = THIS_MODULE, | |
207 | .csr = { | |
1d6205d0 GJ |
208 | .read = rt2x00mmio_register_read, |
209 | .write = rt2x00mmio_register_write, | |
743b97ca ID |
210 | .flags = RT2X00DEBUGFS_OFFSET, |
211 | .word_base = CSR_REG_BASE, | |
95ea3627 ID |
212 | .word_size = sizeof(u32), |
213 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
214 | }, | |
215 | .eeprom = { | |
216 | .read = rt2x00_eeprom_read, | |
217 | .write = rt2x00_eeprom_write, | |
743b97ca | 218 | .word_base = EEPROM_BASE, |
95ea3627 ID |
219 | .word_size = sizeof(u16), |
220 | .word_count = EEPROM_SIZE / sizeof(u16), | |
221 | }, | |
222 | .bbp = { | |
223 | .read = rt61pci_bbp_read, | |
224 | .write = rt61pci_bbp_write, | |
743b97ca | 225 | .word_base = BBP_BASE, |
95ea3627 ID |
226 | .word_size = sizeof(u8), |
227 | .word_count = BBP_SIZE / sizeof(u8), | |
228 | }, | |
229 | .rf = { | |
230 | .read = rt2x00_rf_read, | |
231 | .write = rt61pci_rf_write, | |
743b97ca | 232 | .word_base = RF_BASE, |
95ea3627 ID |
233 | .word_size = sizeof(u32), |
234 | .word_count = RF_SIZE / sizeof(u32), | |
235 | }, | |
236 | }; | |
237 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
238 | ||
95ea3627 ID |
239 | static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
240 | { | |
241 | u32 reg; | |
242 | ||
1d6205d0 | 243 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); |
99bdf51a | 244 | return rt2x00_get_field32(reg, MAC_CSR13_VAL5); |
95ea3627 | 245 | } |
95ea3627 | 246 | |
771fd565 | 247 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 248 | static void rt61pci_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
249 | enum led_brightness brightness) |
250 | { | |
251 | struct rt2x00_led *led = | |
252 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
253 | unsigned int enabled = brightness != LED_OFF; | |
254 | unsigned int a_mode = | |
57fbcce3 | 255 | (enabled && led->rt2x00dev->curr_band == NL80211_BAND_5GHZ); |
a9450b70 | 256 | unsigned int bg_mode = |
57fbcce3 | 257 | (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); |
a9450b70 ID |
258 | |
259 | if (led->type == LED_TYPE_RADIO) { | |
260 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
261 | MCU_LEDCS_RADIO_STATUS, enabled); | |
262 | ||
263 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, | |
264 | (led->rt2x00dev->led_mcu_reg & 0xff), | |
265 | ((led->rt2x00dev->led_mcu_reg >> 8))); | |
266 | } else if (led->type == LED_TYPE_ASSOC) { | |
267 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
268 | MCU_LEDCS_LINK_BG_STATUS, bg_mode); | |
269 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
270 | MCU_LEDCS_LINK_A_STATUS, a_mode); | |
271 | ||
272 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, | |
273 | (led->rt2x00dev->led_mcu_reg & 0xff), | |
274 | ((led->rt2x00dev->led_mcu_reg >> 8))); | |
275 | } else if (led->type == LED_TYPE_QUALITY) { | |
276 | /* | |
277 | * The brightness is divided into 6 levels (0 - 5), | |
278 | * this means we need to convert the brightness | |
279 | * argument into the matching level within that range. | |
280 | */ | |
281 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, | |
282 | brightness / (LED_FULL / 6), 0); | |
283 | } | |
284 | } | |
a2e1d52a ID |
285 | |
286 | static int rt61pci_blink_set(struct led_classdev *led_cdev, | |
287 | unsigned long *delay_on, | |
288 | unsigned long *delay_off) | |
289 | { | |
290 | struct rt2x00_led *led = | |
291 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
292 | u32 reg; | |
293 | ||
1d6205d0 | 294 | rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, ®); |
a2e1d52a ID |
295 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); |
296 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); | |
1d6205d0 | 297 | rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); |
a2e1d52a ID |
298 | |
299 | return 0; | |
300 | } | |
475433be ID |
301 | |
302 | static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev, | |
303 | struct rt2x00_led *led, | |
304 | enum led_type type) | |
305 | { | |
306 | led->rt2x00dev = rt2x00dev; | |
307 | led->type = type; | |
308 | led->led_dev.brightness_set = rt61pci_brightness_set; | |
309 | led->led_dev.blink_set = rt61pci_blink_set; | |
310 | led->flags = LED_INITIALIZED; | |
311 | } | |
771fd565 | 312 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 313 | |
95ea3627 ID |
314 | /* |
315 | * Configuration handlers. | |
316 | */ | |
61e754f4 ID |
317 | static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, |
318 | struct rt2x00lib_crypto *crypto, | |
319 | struct ieee80211_key_conf *key) | |
320 | { | |
321 | struct hw_key_entry key_entry; | |
322 | struct rt2x00_field32 field; | |
323 | u32 mask; | |
324 | u32 reg; | |
325 | ||
326 | if (crypto->cmd == SET_KEY) { | |
327 | /* | |
328 | * rt2x00lib can't determine the correct free | |
329 | * key_idx for shared keys. We have 1 register | |
330 | * with key valid bits. The goal is simple, read | |
331 | * the register, if that is full we have no slots | |
332 | * left. | |
333 | * Note that each BSS is allowed to have up to 4 | |
334 | * shared keys, so put a mask over the allowed | |
335 | * entries. | |
336 | */ | |
337 | mask = (0xf << crypto->bssidx); | |
338 | ||
1d6205d0 | 339 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); |
61e754f4 ID |
340 | reg &= mask; |
341 | ||
342 | if (reg && reg == mask) | |
343 | return -ENOSPC; | |
344 | ||
acaf908d | 345 | key->hw_key_idx += reg ? ffz(reg) : 0; |
61e754f4 ID |
346 | |
347 | /* | |
348 | * Upload key to hardware | |
349 | */ | |
350 | memcpy(key_entry.key, crypto->key, | |
351 | sizeof(key_entry.key)); | |
352 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
353 | sizeof(key_entry.tx_mic)); | |
354 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
355 | sizeof(key_entry.rx_mic)); | |
356 | ||
357 | reg = SHARED_KEY_ENTRY(key->hw_key_idx); | |
1d6205d0 GJ |
358 | rt2x00mmio_register_multiwrite(rt2x00dev, reg, |
359 | &key_entry, sizeof(key_entry)); | |
61e754f4 ID |
360 | |
361 | /* | |
362 | * The cipher types are stored over 2 registers. | |
363 | * bssidx 0 and 1 keys are stored in SEC_CSR1 and | |
364 | * bssidx 1 and 2 keys are stored in SEC_CSR5. | |
365 | * Using the correct defines correctly will cause overhead, | |
366 | * so just calculate the correct offset. | |
367 | */ | |
368 | if (key->hw_key_idx < 8) { | |
369 | field.bit_offset = (3 * key->hw_key_idx); | |
370 | field.bit_mask = 0x7 << field.bit_offset; | |
371 | ||
1d6205d0 | 372 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, ®); |
61e754f4 | 373 | rt2x00_set_field32(®, field, crypto->cipher); |
1d6205d0 | 374 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg); |
61e754f4 ID |
375 | } else { |
376 | field.bit_offset = (3 * (key->hw_key_idx - 8)); | |
377 | field.bit_mask = 0x7 << field.bit_offset; | |
378 | ||
1d6205d0 | 379 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, ®); |
61e754f4 | 380 | rt2x00_set_field32(®, field, crypto->cipher); |
1d6205d0 | 381 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg); |
61e754f4 ID |
382 | } |
383 | ||
384 | /* | |
385 | * The driver does not support the IV/EIV generation | |
386 | * in hardware. However it doesn't support the IV/EIV | |
387 | * inside the ieee80211 frame either, but requires it | |
b34e620f | 388 | * to be provided separately for the descriptor. |
61e754f4 ID |
389 | * rt2x00lib will cut the IV/EIV data out of all frames |
390 | * given to us by mac80211, but we must tell mac80211 | |
391 | * to generate the IV/EIV data. | |
392 | */ | |
393 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
394 | } | |
395 | ||
396 | /* | |
397 | * SEC_CSR0 contains only single-bit fields to indicate | |
398 | * a particular key is valid. Because using the FIELD32() | |
b34e620f | 399 | * defines directly will cause a lot of overhead, we use |
61e754f4 ID |
400 | * a calculation to determine the correct bit directly. |
401 | */ | |
402 | mask = 1 << key->hw_key_idx; | |
403 | ||
1d6205d0 | 404 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); |
61e754f4 ID |
405 | if (crypto->cmd == SET_KEY) |
406 | reg |= mask; | |
407 | else if (crypto->cmd == DISABLE_KEY) | |
408 | reg &= ~mask; | |
1d6205d0 | 409 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg); |
61e754f4 ID |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
414 | static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |
415 | struct rt2x00lib_crypto *crypto, | |
416 | struct ieee80211_key_conf *key) | |
417 | { | |
418 | struct hw_pairwise_ta_entry addr_entry; | |
419 | struct hw_key_entry key_entry; | |
420 | u32 mask; | |
421 | u32 reg; | |
422 | ||
423 | if (crypto->cmd == SET_KEY) { | |
424 | /* | |
425 | * rt2x00lib can't determine the correct free | |
426 | * key_idx for pairwise keys. We have 2 registers | |
b34e620f TLSC |
427 | * with key valid bits. The goal is simple: read |
428 | * the first register. If that is full, move to | |
61e754f4 | 429 | * the next register. |
b34e620f TLSC |
430 | * When both registers are full, we drop the key. |
431 | * Otherwise, we use the first invalid entry. | |
61e754f4 | 432 | */ |
1d6205d0 | 433 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); |
61e754f4 ID |
434 | if (reg && reg == ~0) { |
435 | key->hw_key_idx = 32; | |
1d6205d0 | 436 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); |
61e754f4 ID |
437 | if (reg && reg == ~0) |
438 | return -ENOSPC; | |
439 | } | |
440 | ||
acaf908d | 441 | key->hw_key_idx += reg ? ffz(reg) : 0; |
61e754f4 ID |
442 | |
443 | /* | |
444 | * Upload key to hardware | |
445 | */ | |
446 | memcpy(key_entry.key, crypto->key, | |
447 | sizeof(key_entry.key)); | |
448 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
449 | sizeof(key_entry.tx_mic)); | |
450 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
451 | sizeof(key_entry.rx_mic)); | |
452 | ||
453 | memset(&addr_entry, 0, sizeof(addr_entry)); | |
454 | memcpy(&addr_entry, crypto->address, ETH_ALEN); | |
455 | addr_entry.cipher = crypto->cipher; | |
456 | ||
457 | reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
1d6205d0 GJ |
458 | rt2x00mmio_register_multiwrite(rt2x00dev, reg, |
459 | &key_entry, sizeof(key_entry)); | |
61e754f4 ID |
460 | |
461 | reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); | |
1d6205d0 GJ |
462 | rt2x00mmio_register_multiwrite(rt2x00dev, reg, |
463 | &addr_entry, sizeof(addr_entry)); | |
61e754f4 ID |
464 | |
465 | /* | |
b34e620f TLSC |
466 | * Enable pairwise lookup table for given BSS idx. |
467 | * Without this, received frames will not be decrypted | |
61e754f4 ID |
468 | * by the hardware. |
469 | */ | |
1d6205d0 | 470 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, ®); |
61e754f4 | 471 | reg |= (1 << crypto->bssidx); |
1d6205d0 | 472 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); |
61e754f4 ID |
473 | |
474 | /* | |
475 | * The driver does not support the IV/EIV generation | |
476 | * in hardware. However it doesn't support the IV/EIV | |
477 | * inside the ieee80211 frame either, but requires it | |
3ad2f3fb | 478 | * to be provided separately for the descriptor. |
61e754f4 ID |
479 | * rt2x00lib will cut the IV/EIV data out of all frames |
480 | * given to us by mac80211, but we must tell mac80211 | |
481 | * to generate the IV/EIV data. | |
482 | */ | |
483 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
484 | } | |
485 | ||
486 | /* | |
487 | * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate | |
488 | * a particular key is valid. Because using the FIELD32() | |
b34e620f | 489 | * defines directly will cause a lot of overhead, we use |
61e754f4 ID |
490 | * a calculation to determine the correct bit directly. |
491 | */ | |
492 | if (key->hw_key_idx < 32) { | |
493 | mask = 1 << key->hw_key_idx; | |
494 | ||
1d6205d0 | 495 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); |
61e754f4 ID |
496 | if (crypto->cmd == SET_KEY) |
497 | reg |= mask; | |
498 | else if (crypto->cmd == DISABLE_KEY) | |
499 | reg &= ~mask; | |
1d6205d0 | 500 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); |
61e754f4 ID |
501 | } else { |
502 | mask = 1 << (key->hw_key_idx - 32); | |
503 | ||
1d6205d0 | 504 | rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); |
61e754f4 ID |
505 | if (crypto->cmd == SET_KEY) |
506 | reg |= mask; | |
507 | else if (crypto->cmd == DISABLE_KEY) | |
508 | reg &= ~mask; | |
1d6205d0 | 509 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); |
61e754f4 ID |
510 | } |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
3a643d24 ID |
515 | static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, |
516 | const unsigned int filter_flags) | |
517 | { | |
518 | u32 reg; | |
519 | ||
520 | /* | |
521 | * Start configuration steps. | |
522 | * Note that the version error will always be dropped | |
523 | * and broadcast frames will always be accepted since | |
524 | * there is no filter for it at this time. | |
525 | */ | |
1d6205d0 | 526 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); |
3a643d24 ID |
527 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, |
528 | !(filter_flags & FIF_FCSFAIL)); | |
529 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, | |
530 | !(filter_flags & FIF_PLCPFAIL)); | |
531 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, | |
1afcfd54 | 532 | !(filter_flags & (FIF_CONTROL | FIF_PSPOLL))); |
262c741e EC |
533 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, |
534 | !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); | |
3a643d24 | 535 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, |
262c741e | 536 | !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && |
e0b005fa | 537 | !rt2x00dev->intf_ap_count); |
3a643d24 ID |
538 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); |
539 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, | |
540 | !(filter_flags & FIF_ALLMULTI)); | |
541 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); | |
542 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, | |
543 | !(filter_flags & FIF_CONTROL)); | |
1d6205d0 | 544 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); |
3a643d24 ID |
545 | } |
546 | ||
6bb40dd1 ID |
547 | static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, |
548 | struct rt2x00_intf *intf, | |
549 | struct rt2x00intf_conf *conf, | |
550 | const unsigned int flags) | |
95ea3627 | 551 | { |
6bb40dd1 | 552 | u32 reg; |
95ea3627 | 553 | |
6bb40dd1 | 554 | if (flags & CONFIG_UPDATE_TYPE) { |
6bb40dd1 ID |
555 | /* |
556 | * Enable synchronisation. | |
557 | */ | |
1d6205d0 | 558 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); |
6bb40dd1 | 559 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); |
1d6205d0 | 560 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); |
6bb40dd1 | 561 | } |
95ea3627 | 562 | |
6bb40dd1 ID |
563 | if (flags & CONFIG_UPDATE_MAC) { |
564 | reg = le32_to_cpu(conf->mac[1]); | |
565 | rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); | |
566 | conf->mac[1] = cpu_to_le32(reg); | |
95ea3627 | 567 | |
1d6205d0 GJ |
568 | rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2, |
569 | conf->mac, sizeof(conf->mac)); | |
6bb40dd1 | 570 | } |
95ea3627 | 571 | |
6bb40dd1 ID |
572 | if (flags & CONFIG_UPDATE_BSSID) { |
573 | reg = le32_to_cpu(conf->bssid[1]); | |
574 | rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); | |
575 | conf->bssid[1] = cpu_to_le32(reg); | |
95ea3627 | 576 | |
1d6205d0 GJ |
577 | rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4, |
578 | conf->bssid, | |
579 | sizeof(conf->bssid)); | |
6bb40dd1 | 580 | } |
95ea3627 ID |
581 | } |
582 | ||
3a643d24 | 583 | static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, |
02044643 HS |
584 | struct rt2x00lib_erp *erp, |
585 | u32 changed) | |
95ea3627 | 586 | { |
95ea3627 | 587 | u32 reg; |
95ea3627 | 588 | |
1d6205d0 | 589 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); |
4789666e | 590 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); |
8a566afe | 591 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); |
1d6205d0 | 592 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 593 | |
02044643 | 594 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
1d6205d0 | 595 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); |
02044643 HS |
596 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); |
597 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, | |
598 | !!erp->short_preamble); | |
1d6205d0 | 599 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); |
02044643 | 600 | } |
95ea3627 | 601 | |
02044643 | 602 | if (changed & BSS_CHANGED_BASIC_RATES) |
1d6205d0 GJ |
603 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5, |
604 | erp->basic_rates); | |
95ea3627 | 605 | |
02044643 | 606 | if (changed & BSS_CHANGED_BEACON_INT) { |
1d6205d0 | 607 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); |
02044643 HS |
608 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, |
609 | erp->beacon_int * 16); | |
1d6205d0 | 610 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); |
02044643 | 611 | } |
8a566afe | 612 | |
02044643 | 613 | if (changed & BSS_CHANGED_ERP_SLOT) { |
1d6205d0 | 614 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); |
02044643 | 615 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); |
1d6205d0 | 616 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); |
95ea3627 | 617 | |
1d6205d0 | 618 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, ®); |
02044643 HS |
619 | rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); |
620 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); | |
621 | rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); | |
1d6205d0 | 622 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); |
02044643 | 623 | } |
95ea3627 ID |
624 | } |
625 | ||
626 | static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 627 | struct antenna_setup *ant) |
95ea3627 ID |
628 | { |
629 | u8 r3; | |
630 | u8 r4; | |
631 | u8 r77; | |
632 | ||
633 | rt61pci_bbp_read(rt2x00dev, 3, &r3); | |
634 | rt61pci_bbp_read(rt2x00dev, 4, &r4); | |
635 | rt61pci_bbp_read(rt2x00dev, 77, &r77); | |
636 | ||
5122d898 | 637 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325)); |
e4cd2ff8 ID |
638 | |
639 | /* | |
640 | * Configure the RX antenna. | |
641 | */ | |
addc81bd | 642 | switch (ant->rx) { |
95ea3627 | 643 | case ANTENNA_HW_DIVERSITY: |
acaa410d | 644 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
95ea3627 | 645 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, |
57fbcce3 | 646 | (rt2x00dev->curr_band != NL80211_BAND_5GHZ)); |
95ea3627 ID |
647 | break; |
648 | case ANTENNA_A: | |
acaa410d | 649 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 650 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
57fbcce3 | 651 | if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) |
acaa410d MN |
652 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
653 | else | |
654 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
95ea3627 ID |
655 | break; |
656 | case ANTENNA_B: | |
a4fe07d9 | 657 | default: |
acaa410d | 658 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 659 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
57fbcce3 | 660 | if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) |
acaa410d MN |
661 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
662 | else | |
663 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
95ea3627 ID |
664 | break; |
665 | } | |
666 | ||
667 | rt61pci_bbp_write(rt2x00dev, 77, r77); | |
668 | rt61pci_bbp_write(rt2x00dev, 3, r3); | |
669 | rt61pci_bbp_write(rt2x00dev, 4, r4); | |
670 | } | |
671 | ||
672 | static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 673 | struct antenna_setup *ant) |
95ea3627 ID |
674 | { |
675 | u8 r3; | |
676 | u8 r4; | |
677 | u8 r77; | |
678 | ||
679 | rt61pci_bbp_read(rt2x00dev, 3, &r3); | |
680 | rt61pci_bbp_read(rt2x00dev, 4, &r4); | |
681 | rt61pci_bbp_read(rt2x00dev, 77, &r77); | |
682 | ||
5122d898 | 683 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); |
95ea3627 | 684 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, |
f3218bee | 685 | !rt2x00_has_cap_frame_type(rt2x00dev)); |
95ea3627 | 686 | |
e4cd2ff8 ID |
687 | /* |
688 | * Configure the RX antenna. | |
689 | */ | |
addc81bd | 690 | switch (ant->rx) { |
95ea3627 | 691 | case ANTENNA_HW_DIVERSITY: |
acaa410d | 692 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
95ea3627 ID |
693 | break; |
694 | case ANTENNA_A: | |
acaa410d MN |
695 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
696 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
95ea3627 ID |
697 | break; |
698 | case ANTENNA_B: | |
a4fe07d9 | 699 | default: |
acaa410d MN |
700 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
701 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
95ea3627 ID |
702 | break; |
703 | } | |
704 | ||
705 | rt61pci_bbp_write(rt2x00dev, 77, r77); | |
706 | rt61pci_bbp_write(rt2x00dev, 3, r3); | |
707 | rt61pci_bbp_write(rt2x00dev, 4, r4); | |
708 | } | |
709 | ||
710 | static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, | |
711 | const int p1, const int p2) | |
712 | { | |
713 | u32 reg; | |
714 | ||
1d6205d0 | 715 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); |
95ea3627 | 716 | |
99bdf51a GW |
717 | rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); |
718 | rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); | |
acaa410d | 719 | |
99bdf51a GW |
720 | rt2x00_set_field32(®, MAC_CSR13_DIR3, 0); |
721 | rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2); | |
acaa410d | 722 | |
1d6205d0 | 723 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); |
95ea3627 ID |
724 | } |
725 | ||
726 | static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 727 | struct antenna_setup *ant) |
95ea3627 | 728 | { |
95ea3627 ID |
729 | u8 r3; |
730 | u8 r4; | |
731 | u8 r77; | |
732 | ||
733 | rt61pci_bbp_read(rt2x00dev, 3, &r3); | |
734 | rt61pci_bbp_read(rt2x00dev, 4, &r4); | |
735 | rt61pci_bbp_read(rt2x00dev, 77, &r77); | |
e4cd2ff8 | 736 | |
e4cd2ff8 ID |
737 | /* |
738 | * Configure the RX antenna. | |
739 | */ | |
740 | switch (ant->rx) { | |
741 | case ANTENNA_A: | |
acaa410d MN |
742 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
743 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
744 | rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); | |
e4cd2ff8 | 745 | break; |
e4cd2ff8 ID |
746 | case ANTENNA_HW_DIVERSITY: |
747 | /* | |
a4fe07d9 ID |
748 | * FIXME: Antenna selection for the rf 2529 is very confusing |
749 | * in the legacy driver. Just default to antenna B until the | |
750 | * legacy code can be properly translated into rt2x00 code. | |
e4cd2ff8 ID |
751 | */ |
752 | case ANTENNA_B: | |
a4fe07d9 | 753 | default: |
acaa410d MN |
754 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
755 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
756 | rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); | |
e4cd2ff8 ID |
757 | break; |
758 | } | |
759 | ||
e4cd2ff8 | 760 | rt61pci_bbp_write(rt2x00dev, 77, r77); |
95ea3627 ID |
761 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
762 | rt61pci_bbp_write(rt2x00dev, 4, r4); | |
763 | } | |
764 | ||
765 | struct antenna_sel { | |
766 | u8 word; | |
767 | /* | |
768 | * value[0] -> non-LNA | |
769 | * value[1] -> LNA | |
770 | */ | |
771 | u8 value[2]; | |
772 | }; | |
773 | ||
774 | static const struct antenna_sel antenna_sel_a[] = { | |
775 | { 96, { 0x58, 0x78 } }, | |
776 | { 104, { 0x38, 0x48 } }, | |
777 | { 75, { 0xfe, 0x80 } }, | |
778 | { 86, { 0xfe, 0x80 } }, | |
779 | { 88, { 0xfe, 0x80 } }, | |
780 | { 35, { 0x60, 0x60 } }, | |
781 | { 97, { 0x58, 0x58 } }, | |
782 | { 98, { 0x58, 0x58 } }, | |
783 | }; | |
784 | ||
785 | static const struct antenna_sel antenna_sel_bg[] = { | |
786 | { 96, { 0x48, 0x68 } }, | |
787 | { 104, { 0x2c, 0x3c } }, | |
788 | { 75, { 0xfe, 0x80 } }, | |
789 | { 86, { 0xfe, 0x80 } }, | |
790 | { 88, { 0xfe, 0x80 } }, | |
791 | { 35, { 0x50, 0x50 } }, | |
792 | { 97, { 0x48, 0x48 } }, | |
793 | { 98, { 0x48, 0x48 } }, | |
794 | }; | |
795 | ||
e4ea1c40 ID |
796 | static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev, |
797 | struct antenna_setup *ant) | |
95ea3627 ID |
798 | { |
799 | const struct antenna_sel *sel; | |
800 | unsigned int lna; | |
801 | unsigned int i; | |
802 | u32 reg; | |
803 | ||
a4fe07d9 ID |
804 | /* |
805 | * We should never come here because rt2x00lib is supposed | |
806 | * to catch this and send us the correct antenna explicitely. | |
807 | */ | |
808 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
809 | ant->tx == ANTENNA_SW_DIVERSITY); | |
810 | ||
57fbcce3 | 811 | if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { |
95ea3627 | 812 | sel = antenna_sel_a; |
f3218bee | 813 | lna = rt2x00_has_cap_external_lna_a(rt2x00dev); |
95ea3627 ID |
814 | } else { |
815 | sel = antenna_sel_bg; | |
f3218bee | 816 | lna = rt2x00_has_cap_external_lna_bg(rt2x00dev); |
95ea3627 ID |
817 | } |
818 | ||
acaa410d MN |
819 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) |
820 | rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); | |
821 | ||
1d6205d0 | 822 | rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, ®); |
acaa410d | 823 | |
ddc827f9 | 824 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, |
57fbcce3 | 825 | rt2x00dev->curr_band == NL80211_BAND_2GHZ); |
ddc827f9 | 826 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, |
57fbcce3 | 827 | rt2x00dev->curr_band == NL80211_BAND_5GHZ); |
ddc827f9 | 828 | |
1d6205d0 | 829 | rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); |
95ea3627 | 830 | |
5122d898 | 831 | if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) |
addc81bd | 832 | rt61pci_config_antenna_5x(rt2x00dev, ant); |
5122d898 | 833 | else if (rt2x00_rf(rt2x00dev, RF2527)) |
addc81bd | 834 | rt61pci_config_antenna_2x(rt2x00dev, ant); |
5122d898 | 835 | else if (rt2x00_rf(rt2x00dev, RF2529)) { |
f3218bee | 836 | if (rt2x00_has_cap_double_antenna(rt2x00dev)) |
addc81bd | 837 | rt61pci_config_antenna_2x(rt2x00dev, ant); |
95ea3627 | 838 | else |
addc81bd | 839 | rt61pci_config_antenna_2529(rt2x00dev, ant); |
95ea3627 ID |
840 | } |
841 | } | |
842 | ||
e4ea1c40 ID |
843 | static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, |
844 | struct rt2x00lib_conf *libconf) | |
845 | { | |
846 | u16 eeprom; | |
847 | short lna_gain = 0; | |
848 | ||
57fbcce3 | 849 | if (libconf->conf->chandef.chan->band == NL80211_BAND_2GHZ) { |
f3218bee | 850 | if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) |
e4ea1c40 ID |
851 | lna_gain += 14; |
852 | ||
853 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); | |
854 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); | |
855 | } else { | |
f3218bee | 856 | if (rt2x00_has_cap_external_lna_a(rt2x00dev)) |
e4ea1c40 ID |
857 | lna_gain += 14; |
858 | ||
859 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); | |
860 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); | |
861 | } | |
862 | ||
863 | rt2x00dev->lna_gain = lna_gain; | |
864 | } | |
865 | ||
866 | static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, | |
867 | struct rf_channel *rf, const int txpower) | |
868 | { | |
869 | u8 r3; | |
870 | u8 r94; | |
871 | u8 smart; | |
872 | ||
873 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
874 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
875 | ||
5122d898 | 876 | smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); |
e4ea1c40 ID |
877 | |
878 | rt61pci_bbp_read(rt2x00dev, 3, &r3); | |
879 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); | |
880 | rt61pci_bbp_write(rt2x00dev, 3, r3); | |
881 | ||
882 | r94 = 6; | |
883 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) | |
884 | r94 += txpower - MAX_TXPOWER; | |
885 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) | |
886 | r94 += txpower; | |
887 | rt61pci_bbp_write(rt2x00dev, 94, r94); | |
888 | ||
889 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); | |
890 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); | |
891 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
892 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); | |
893 | ||
894 | udelay(200); | |
895 | ||
896 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); | |
897 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); | |
898 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
899 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); | |
900 | ||
901 | udelay(200); | |
902 | ||
903 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); | |
904 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); | |
905 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
906 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); | |
907 | ||
908 | msleep(1); | |
909 | } | |
910 | ||
911 | static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, | |
912 | const int txpower) | |
913 | { | |
914 | struct rf_channel rf; | |
915 | ||
916 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); | |
917 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); | |
918 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); | |
919 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); | |
920 | ||
921 | rt61pci_config_channel(rt2x00dev, &rf, txpower); | |
922 | } | |
923 | ||
924 | static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, | |
5c58ee51 | 925 | struct rt2x00lib_conf *libconf) |
95ea3627 ID |
926 | { |
927 | u32 reg; | |
928 | ||
1d6205d0 | 929 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); |
e1b4d7b7 ID |
930 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); |
931 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); | |
932 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); | |
e4ea1c40 ID |
933 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, |
934 | libconf->conf->long_frame_max_tx_count); | |
935 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, | |
936 | libconf->conf->short_frame_max_tx_count); | |
1d6205d0 | 937 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); |
e4ea1c40 | 938 | } |
95ea3627 | 939 | |
7d7f19cc ID |
940 | static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, |
941 | struct rt2x00lib_conf *libconf) | |
942 | { | |
943 | enum dev_state state = | |
944 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
945 | STATE_SLEEP : STATE_AWAKE; | |
946 | u32 reg; | |
947 | ||
948 | if (state == STATE_SLEEP) { | |
1d6205d0 | 949 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); |
7d7f19cc | 950 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, |
6b347bff | 951 | rt2x00dev->beacon_int - 10); |
7d7f19cc ID |
952 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, |
953 | libconf->conf->listen_interval - 1); | |
954 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); | |
955 | ||
956 | /* We must first disable autowake before it can be enabled */ | |
957 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); | |
1d6205d0 | 958 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); |
7d7f19cc ID |
959 | |
960 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); | |
1d6205d0 | 961 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); |
7d7f19cc | 962 | |
1d6205d0 GJ |
963 | rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, |
964 | 0x00000005); | |
965 | rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); | |
966 | rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); | |
7d7f19cc ID |
967 | |
968 | rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); | |
969 | } else { | |
1d6205d0 | 970 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); |
7d7f19cc ID |
971 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); |
972 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); | |
973 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); | |
974 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); | |
1d6205d0 | 975 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); |
7d7f19cc | 976 | |
1d6205d0 GJ |
977 | rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, |
978 | 0x00000007); | |
979 | rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); | |
980 | rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); | |
7d7f19cc ID |
981 | |
982 | rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); | |
983 | } | |
984 | } | |
985 | ||
95ea3627 | 986 | static void rt61pci_config(struct rt2x00_dev *rt2x00dev, |
6bb40dd1 ID |
987 | struct rt2x00lib_conf *libconf, |
988 | const unsigned int flags) | |
95ea3627 | 989 | { |
ba2ab471 ID |
990 | /* Always recalculate LNA gain before changing configuration */ |
991 | rt61pci_config_lna_gain(rt2x00dev, libconf); | |
992 | ||
e4ea1c40 | 993 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
5c58ee51 ID |
994 | rt61pci_config_channel(rt2x00dev, &libconf->rf, |
995 | libconf->conf->power_level); | |
e4ea1c40 ID |
996 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
997 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) | |
5c58ee51 | 998 | rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); |
e4ea1c40 ID |
999 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
1000 | rt61pci_config_retry_limit(rt2x00dev, libconf); | |
7d7f19cc ID |
1001 | if (flags & IEEE80211_CONF_CHANGE_PS) |
1002 | rt61pci_config_ps(rt2x00dev, libconf); | |
95ea3627 ID |
1003 | } |
1004 | ||
95ea3627 ID |
1005 | /* |
1006 | * Link tuning | |
1007 | */ | |
ebcf26da ID |
1008 | static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, |
1009 | struct link_qual *qual) | |
95ea3627 ID |
1010 | { |
1011 | u32 reg; | |
1012 | ||
1013 | /* | |
1014 | * Update FCS error count from register. | |
1015 | */ | |
1d6205d0 | 1016 | rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); |
ebcf26da | 1017 | qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); |
95ea3627 ID |
1018 | |
1019 | /* | |
1020 | * Update False CCA count from register. | |
1021 | */ | |
1d6205d0 | 1022 | rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); |
ebcf26da | 1023 | qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); |
95ea3627 ID |
1024 | } |
1025 | ||
5352ff65 ID |
1026 | static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev, |
1027 | struct link_qual *qual, u8 vgc_level) | |
eb20b4e8 | 1028 | { |
5352ff65 | 1029 | if (qual->vgc_level != vgc_level) { |
eb20b4e8 | 1030 | rt61pci_bbp_write(rt2x00dev, 17, vgc_level); |
5352ff65 ID |
1031 | qual->vgc_level = vgc_level; |
1032 | qual->vgc_level_reg = vgc_level; | |
eb20b4e8 ID |
1033 | } |
1034 | } | |
1035 | ||
5352ff65 ID |
1036 | static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev, |
1037 | struct link_qual *qual) | |
95ea3627 | 1038 | { |
5352ff65 | 1039 | rt61pci_set_vgc(rt2x00dev, qual, 0x20); |
95ea3627 ID |
1040 | } |
1041 | ||
5352ff65 ID |
1042 | static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev, |
1043 | struct link_qual *qual, const u32 count) | |
95ea3627 | 1044 | { |
95ea3627 ID |
1045 | u8 up_bound; |
1046 | u8 low_bound; | |
1047 | ||
95ea3627 ID |
1048 | /* |
1049 | * Determine r17 bounds. | |
1050 | */ | |
57fbcce3 | 1051 | if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { |
95ea3627 ID |
1052 | low_bound = 0x28; |
1053 | up_bound = 0x48; | |
f3218bee | 1054 | if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { |
95ea3627 ID |
1055 | low_bound += 0x10; |
1056 | up_bound += 0x10; | |
1057 | } | |
1058 | } else { | |
1059 | low_bound = 0x20; | |
1060 | up_bound = 0x40; | |
f3218bee | 1061 | if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { |
95ea3627 ID |
1062 | low_bound += 0x10; |
1063 | up_bound += 0x10; | |
1064 | } | |
1065 | } | |
1066 | ||
6bb40dd1 ID |
1067 | /* |
1068 | * If we are not associated, we should go straight to the | |
1069 | * dynamic CCA tuning. | |
1070 | */ | |
1071 | if (!rt2x00dev->intf_associated) | |
1072 | goto dynamic_cca_tune; | |
1073 | ||
95ea3627 ID |
1074 | /* |
1075 | * Special big-R17 for very short distance | |
1076 | */ | |
5352ff65 ID |
1077 | if (qual->rssi >= -35) { |
1078 | rt61pci_set_vgc(rt2x00dev, qual, 0x60); | |
95ea3627 ID |
1079 | return; |
1080 | } | |
1081 | ||
1082 | /* | |
1083 | * Special big-R17 for short distance | |
1084 | */ | |
5352ff65 ID |
1085 | if (qual->rssi >= -58) { |
1086 | rt61pci_set_vgc(rt2x00dev, qual, up_bound); | |
95ea3627 ID |
1087 | return; |
1088 | } | |
1089 | ||
1090 | /* | |
1091 | * Special big-R17 for middle-short distance | |
1092 | */ | |
5352ff65 ID |
1093 | if (qual->rssi >= -66) { |
1094 | rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10); | |
95ea3627 ID |
1095 | return; |
1096 | } | |
1097 | ||
1098 | /* | |
1099 | * Special mid-R17 for middle distance | |
1100 | */ | |
5352ff65 ID |
1101 | if (qual->rssi >= -74) { |
1102 | rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08); | |
95ea3627 ID |
1103 | return; |
1104 | } | |
1105 | ||
1106 | /* | |
1107 | * Special case: Change up_bound based on the rssi. | |
1108 | * Lower up_bound when rssi is weaker then -74 dBm. | |
1109 | */ | |
5352ff65 | 1110 | up_bound -= 2 * (-74 - qual->rssi); |
95ea3627 ID |
1111 | if (low_bound > up_bound) |
1112 | up_bound = low_bound; | |
1113 | ||
5352ff65 ID |
1114 | if (qual->vgc_level > up_bound) { |
1115 | rt61pci_set_vgc(rt2x00dev, qual, up_bound); | |
95ea3627 ID |
1116 | return; |
1117 | } | |
1118 | ||
6bb40dd1 ID |
1119 | dynamic_cca_tune: |
1120 | ||
95ea3627 ID |
1121 | /* |
1122 | * r17 does not yet exceed upper limit, continue and base | |
1123 | * the r17 tuning on the false CCA count. | |
1124 | */ | |
5352ff65 ID |
1125 | if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) |
1126 | rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); | |
1127 | else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) | |
1128 | rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); | |
95ea3627 ID |
1129 | } |
1130 | ||
5450b7e2 ID |
1131 | /* |
1132 | * Queue handlers. | |
1133 | */ | |
1134 | static void rt61pci_start_queue(struct data_queue *queue) | |
1135 | { | |
1136 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1137 | u32 reg; | |
1138 | ||
1139 | switch (queue->qid) { | |
1140 | case QID_RX: | |
1d6205d0 | 1141 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); |
5450b7e2 | 1142 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); |
1d6205d0 | 1143 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); |
5450b7e2 ID |
1144 | break; |
1145 | case QID_BEACON: | |
1d6205d0 | 1146 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); |
5450b7e2 ID |
1147 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
1148 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); | |
1149 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); | |
1d6205d0 | 1150 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); |
5450b7e2 ID |
1151 | break; |
1152 | default: | |
1153 | break; | |
1154 | } | |
1155 | } | |
1156 | ||
1157 | static void rt61pci_kick_queue(struct data_queue *queue) | |
1158 | { | |
1159 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1160 | u32 reg; | |
1161 | ||
1162 | switch (queue->qid) { | |
f615e9a3 | 1163 | case QID_AC_VO: |
1d6205d0 | 1164 | rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
5450b7e2 | 1165 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1); |
1d6205d0 | 1166 | rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
5450b7e2 | 1167 | break; |
f615e9a3 | 1168 | case QID_AC_VI: |
1d6205d0 | 1169 | rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
5450b7e2 | 1170 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1); |
1d6205d0 | 1171 | rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
5450b7e2 | 1172 | break; |
f615e9a3 | 1173 | case QID_AC_BE: |
1d6205d0 | 1174 | rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
5450b7e2 | 1175 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1); |
1d6205d0 | 1176 | rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
5450b7e2 | 1177 | break; |
f615e9a3 | 1178 | case QID_AC_BK: |
1d6205d0 | 1179 | rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
5450b7e2 | 1180 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1); |
1d6205d0 | 1181 | rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
5450b7e2 ID |
1182 | break; |
1183 | default: | |
1184 | break; | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | static void rt61pci_stop_queue(struct data_queue *queue) | |
1189 | { | |
1190 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1191 | u32 reg; | |
1192 | ||
1193 | switch (queue->qid) { | |
f615e9a3 | 1194 | case QID_AC_VO: |
1d6205d0 | 1195 | rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
5450b7e2 | 1196 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); |
1d6205d0 | 1197 | rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
5450b7e2 | 1198 | break; |
f615e9a3 | 1199 | case QID_AC_VI: |
1d6205d0 | 1200 | rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
5450b7e2 | 1201 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); |
1d6205d0 | 1202 | rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
5450b7e2 | 1203 | break; |
f615e9a3 | 1204 | case QID_AC_BE: |
1d6205d0 | 1205 | rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
5450b7e2 | 1206 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); |
1d6205d0 | 1207 | rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
5450b7e2 | 1208 | break; |
f615e9a3 | 1209 | case QID_AC_BK: |
1d6205d0 | 1210 | rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
5450b7e2 | 1211 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); |
1d6205d0 | 1212 | rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
5450b7e2 ID |
1213 | break; |
1214 | case QID_RX: | |
1d6205d0 | 1215 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); |
5450b7e2 | 1216 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); |
1d6205d0 | 1217 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); |
5450b7e2 ID |
1218 | break; |
1219 | case QID_BEACON: | |
1d6205d0 | 1220 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); |
5450b7e2 ID |
1221 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); |
1222 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1223 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1d6205d0 | 1224 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); |
5846a550 HS |
1225 | |
1226 | /* | |
1227 | * Wait for possibly running tbtt tasklets. | |
1228 | */ | |
abc11994 | 1229 | tasklet_kill(&rt2x00dev->tbtt_tasklet); |
5450b7e2 ID |
1230 | break; |
1231 | default: | |
1232 | break; | |
1233 | } | |
1234 | } | |
1235 | ||
95ea3627 | 1236 | /* |
a7f3a06c | 1237 | * Firmware functions |
95ea3627 ID |
1238 | */ |
1239 | static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) | |
1240 | { | |
49e721ec | 1241 | u16 chip; |
95ea3627 ID |
1242 | char *fw_name; |
1243 | ||
49e721ec GW |
1244 | pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip); |
1245 | switch (chip) { | |
1246 | case RT2561_PCI_ID: | |
95ea3627 ID |
1247 | fw_name = FIRMWARE_RT2561; |
1248 | break; | |
49e721ec | 1249 | case RT2561s_PCI_ID: |
95ea3627 ID |
1250 | fw_name = FIRMWARE_RT2561s; |
1251 | break; | |
49e721ec | 1252 | case RT2661_PCI_ID: |
95ea3627 ID |
1253 | fw_name = FIRMWARE_RT2661; |
1254 | break; | |
1255 | default: | |
1256 | fw_name = NULL; | |
1257 | break; | |
1258 | } | |
1259 | ||
1260 | return fw_name; | |
1261 | } | |
1262 | ||
0cbe0064 ID |
1263 | static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev, |
1264 | const u8 *data, const size_t len) | |
a7f3a06c | 1265 | { |
0cbe0064 | 1266 | u16 fw_crc; |
a7f3a06c ID |
1267 | u16 crc; |
1268 | ||
1269 | /* | |
0cbe0064 ID |
1270 | * Only support 8kb firmware files. |
1271 | */ | |
1272 | if (len != 8192) | |
1273 | return FW_BAD_LENGTH; | |
1274 | ||
1275 | /* | |
b34e620f TLSC |
1276 | * The last 2 bytes in the firmware array are the crc checksum itself. |
1277 | * This means that we should never pass those 2 bytes to the crc | |
a7f3a06c ID |
1278 | * algorithm. |
1279 | */ | |
0cbe0064 ID |
1280 | fw_crc = (data[len - 2] << 8 | data[len - 1]); |
1281 | ||
1282 | /* | |
1283 | * Use the crc itu-t algorithm. | |
1284 | */ | |
a7f3a06c ID |
1285 | crc = crc_itu_t(0, data, len - 2); |
1286 | crc = crc_itu_t_byte(crc, 0); | |
1287 | crc = crc_itu_t_byte(crc, 0); | |
1288 | ||
0cbe0064 | 1289 | return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; |
a7f3a06c ID |
1290 | } |
1291 | ||
0cbe0064 ID |
1292 | static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, |
1293 | const u8 *data, const size_t len) | |
95ea3627 ID |
1294 | { |
1295 | int i; | |
1296 | u32 reg; | |
1297 | ||
1298 | /* | |
1299 | * Wait for stable hardware. | |
1300 | */ | |
1301 | for (i = 0; i < 100; i++) { | |
1d6205d0 | 1302 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); |
95ea3627 ID |
1303 | if (reg) |
1304 | break; | |
1305 | msleep(1); | |
1306 | } | |
1307 | ||
1308 | if (!reg) { | |
ec9c4989 | 1309 | rt2x00_err(rt2x00dev, "Unstable hardware\n"); |
95ea3627 ID |
1310 | return -EBUSY; |
1311 | } | |
1312 | ||
1313 | /* | |
1314 | * Prepare MCU and mailbox for firmware loading. | |
1315 | */ | |
1316 | reg = 0; | |
1317 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); | |
1d6205d0 GJ |
1318 | rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
1319 | rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); | |
1320 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
1321 | rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0); | |
95ea3627 ID |
1322 | |
1323 | /* | |
1324 | * Write firmware to device. | |
1325 | */ | |
1326 | reg = 0; | |
1327 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); | |
1328 | rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); | |
1d6205d0 | 1329 | rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
95ea3627 | 1330 | |
1d6205d0 GJ |
1331 | rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, |
1332 | data, len); | |
95ea3627 ID |
1333 | |
1334 | rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); | |
1d6205d0 | 1335 | rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
95ea3627 ID |
1336 | |
1337 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); | |
1d6205d0 | 1338 | rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
95ea3627 ID |
1339 | |
1340 | for (i = 0; i < 100; i++) { | |
1d6205d0 | 1341 | rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, ®); |
95ea3627 ID |
1342 | if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) |
1343 | break; | |
1344 | msleep(1); | |
1345 | } | |
1346 | ||
1347 | if (i == 100) { | |
ec9c4989 | 1348 | rt2x00_err(rt2x00dev, "MCU Control register not ready\n"); |
95ea3627 ID |
1349 | return -EBUSY; |
1350 | } | |
1351 | ||
e6d3e902 ID |
1352 | /* |
1353 | * Hardware needs another millisecond before it is ready. | |
1354 | */ | |
1355 | msleep(1); | |
1356 | ||
95ea3627 ID |
1357 | /* |
1358 | * Reset MAC and BBP registers. | |
1359 | */ | |
1360 | reg = 0; | |
1361 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); | |
1362 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
1d6205d0 | 1363 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1364 | |
1d6205d0 | 1365 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1366 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
1367 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
1d6205d0 | 1368 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1369 | |
1d6205d0 | 1370 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 | 1371 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
1d6205d0 | 1372 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 ID |
1373 | |
1374 | return 0; | |
1375 | } | |
1376 | ||
a7f3a06c ID |
1377 | /* |
1378 | * Initialization functions. | |
1379 | */ | |
798b7adb | 1380 | static bool rt61pci_get_entry_state(struct queue_entry *entry) |
95ea3627 | 1381 | { |
1d6205d0 | 1382 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
95ea3627 ID |
1383 | u32 word; |
1384 | ||
798b7adb ID |
1385 | if (entry->queue->qid == QID_RX) { |
1386 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 | 1387 | |
798b7adb ID |
1388 | return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); |
1389 | } else { | |
1390 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
1391 | ||
1392 | return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | |
1393 | rt2x00_get_field32(word, TXD_W0_VALID)); | |
1394 | } | |
95ea3627 ID |
1395 | } |
1396 | ||
798b7adb | 1397 | static void rt61pci_clear_entry(struct queue_entry *entry) |
95ea3627 | 1398 | { |
1d6205d0 | 1399 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
798b7adb | 1400 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
95ea3627 ID |
1401 | u32 word; |
1402 | ||
798b7adb ID |
1403 | if (entry->queue->qid == QID_RX) { |
1404 | rt2x00_desc_read(entry_priv->desc, 5, &word); | |
1405 | rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, | |
1406 | skbdesc->skb_dma); | |
1407 | rt2x00_desc_write(entry_priv->desc, 5, word); | |
1408 | ||
1409 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
1410 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); | |
1411 | rt2x00_desc_write(entry_priv->desc, 0, word); | |
1412 | } else { | |
1413 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
1414 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); | |
1415 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); | |
1416 | rt2x00_desc_write(entry_priv->desc, 0, word); | |
1417 | } | |
95ea3627 ID |
1418 | } |
1419 | ||
181d6902 | 1420 | static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) |
95ea3627 | 1421 | { |
1d6205d0 | 1422 | struct queue_entry_priv_mmio *entry_priv; |
95ea3627 ID |
1423 | u32 reg; |
1424 | ||
95ea3627 ID |
1425 | /* |
1426 | * Initialize registers. | |
1427 | */ | |
1d6205d0 | 1428 | rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, ®); |
95ea3627 | 1429 | rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, |
181d6902 | 1430 | rt2x00dev->tx[0].limit); |
95ea3627 | 1431 | rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, |
181d6902 | 1432 | rt2x00dev->tx[1].limit); |
95ea3627 | 1433 | rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, |
181d6902 | 1434 | rt2x00dev->tx[2].limit); |
95ea3627 | 1435 | rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, |
181d6902 | 1436 | rt2x00dev->tx[3].limit); |
1d6205d0 | 1437 | rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); |
95ea3627 | 1438 | |
1d6205d0 | 1439 | rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, ®); |
95ea3627 | 1440 | rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, |
181d6902 | 1441 | rt2x00dev->tx[0].desc_size / 4); |
1d6205d0 | 1442 | rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); |
95ea3627 | 1443 | |
b8be63ff | 1444 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
1d6205d0 | 1445 | rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, ®); |
30b3a23c | 1446 | rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, |
b8be63ff | 1447 | entry_priv->desc_dma); |
1d6205d0 | 1448 | rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); |
95ea3627 | 1449 | |
b8be63ff | 1450 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
1d6205d0 | 1451 | rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, ®); |
30b3a23c | 1452 | rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, |
b8be63ff | 1453 | entry_priv->desc_dma); |
1d6205d0 | 1454 | rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); |
95ea3627 | 1455 | |
b8be63ff | 1456 | entry_priv = rt2x00dev->tx[2].entries[0].priv_data; |
1d6205d0 | 1457 | rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, ®); |
30b3a23c | 1458 | rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, |
b8be63ff | 1459 | entry_priv->desc_dma); |
1d6205d0 | 1460 | rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); |
95ea3627 | 1461 | |
b8be63ff | 1462 | entry_priv = rt2x00dev->tx[3].entries[0].priv_data; |
1d6205d0 | 1463 | rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, ®); |
30b3a23c | 1464 | rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, |
b8be63ff | 1465 | entry_priv->desc_dma); |
1d6205d0 | 1466 | rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); |
95ea3627 | 1467 | |
1d6205d0 | 1468 | rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, ®); |
181d6902 | 1469 | rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); |
95ea3627 ID |
1470 | rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, |
1471 | rt2x00dev->rx->desc_size / 4); | |
1472 | rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); | |
1d6205d0 | 1473 | rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); |
95ea3627 | 1474 | |
b8be63ff | 1475 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
1d6205d0 | 1476 | rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, ®); |
30b3a23c | 1477 | rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, |
b8be63ff | 1478 | entry_priv->desc_dma); |
1d6205d0 | 1479 | rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); |
95ea3627 | 1480 | |
1d6205d0 | 1481 | rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); |
95ea3627 ID |
1482 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); |
1483 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); | |
1484 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); | |
1485 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); | |
1d6205d0 | 1486 | rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); |
95ea3627 | 1487 | |
1d6205d0 | 1488 | rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); |
95ea3627 ID |
1489 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); |
1490 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); | |
1491 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); | |
1492 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); | |
1d6205d0 | 1493 | rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); |
95ea3627 | 1494 | |
1d6205d0 | 1495 | rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); |
95ea3627 | 1496 | rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); |
1d6205d0 | 1497 | rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); |
95ea3627 ID |
1498 | |
1499 | return 0; | |
1500 | } | |
1501 | ||
1502 | static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) | |
1503 | { | |
1504 | u32 reg; | |
1505 | ||
1d6205d0 | 1506 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); |
95ea3627 ID |
1507 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); |
1508 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1509 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); | |
1d6205d0 | 1510 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 1511 | |
1d6205d0 | 1512 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, ®); |
95ea3627 ID |
1513 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ |
1514 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); | |
1515 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ | |
1516 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); | |
1517 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ | |
1518 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); | |
1519 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ | |
1520 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); | |
1d6205d0 | 1521 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); |
95ea3627 ID |
1522 | |
1523 | /* | |
1524 | * CCK TXD BBP registers | |
1525 | */ | |
1d6205d0 | 1526 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, ®); |
95ea3627 ID |
1527 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); |
1528 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); | |
1529 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); | |
1530 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); | |
1531 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); | |
1532 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); | |
1533 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); | |
1534 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); | |
1d6205d0 | 1535 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); |
95ea3627 ID |
1536 | |
1537 | /* | |
1538 | * OFDM TXD BBP registers | |
1539 | */ | |
1d6205d0 | 1540 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, ®); |
95ea3627 ID |
1541 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); |
1542 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); | |
1543 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); | |
1544 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); | |
1545 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); | |
1546 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); | |
1d6205d0 | 1547 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); |
95ea3627 | 1548 | |
1d6205d0 | 1549 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, ®); |
95ea3627 ID |
1550 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); |
1551 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); | |
1552 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); | |
1553 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); | |
1d6205d0 | 1554 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); |
95ea3627 | 1555 | |
1d6205d0 | 1556 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, ®); |
95ea3627 ID |
1557 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); |
1558 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); | |
1559 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); | |
1560 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); | |
1d6205d0 | 1561 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); |
95ea3627 | 1562 | |
1d6205d0 | 1563 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); |
1f909162 ID |
1564 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); |
1565 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1566 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); | |
1567 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1568 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1569 | rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); | |
1d6205d0 | 1570 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); |
1f909162 | 1571 | |
1d6205d0 | 1572 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); |
95ea3627 | 1573 | |
1d6205d0 | 1574 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); |
95ea3627 | 1575 | |
1d6205d0 | 1576 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); |
95ea3627 | 1577 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); |
1d6205d0 | 1578 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); |
95ea3627 | 1579 | |
1d6205d0 | 1580 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); |
95ea3627 ID |
1581 | |
1582 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
1583 | return -EBUSY; | |
1584 | ||
1d6205d0 | 1585 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); |
95ea3627 ID |
1586 | |
1587 | /* | |
1588 | * Invalidate all Shared Keys (SEC_CSR0), | |
1589 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) | |
1590 | */ | |
1d6205d0 GJ |
1591 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000); |
1592 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000); | |
1593 | rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000); | |
95ea3627 | 1594 | |
1d6205d0 GJ |
1595 | rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); |
1596 | rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); | |
1597 | rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606); | |
1598 | rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); | |
95ea3627 | 1599 | |
1d6205d0 | 1600 | rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); |
95ea3627 | 1601 | |
1d6205d0 | 1602 | rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); |
95ea3627 | 1603 | |
1d6205d0 | 1604 | rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); |
95ea3627 | 1605 | |
6bb40dd1 ID |
1606 | /* |
1607 | * Clear all beacons | |
1608 | * For the Beacon base registers we only need to clear | |
1609 | * the first byte since that byte contains the VALID and OWNER | |
1610 | * bits which (when set to 0) will invalidate the entire beacon. | |
1611 | */ | |
1d6205d0 GJ |
1612 | rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
1613 | rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0); | |
1614 | rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0); | |
1615 | rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0); | |
6bb40dd1 | 1616 | |
95ea3627 ID |
1617 | /* |
1618 | * We must clear the error counters. | |
1619 | * These registers are cleared on read, | |
1620 | * so we may pass a useless variable to store the value. | |
1621 | */ | |
1d6205d0 GJ |
1622 | rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); |
1623 | rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); | |
1624 | rt2x00mmio_register_read(rt2x00dev, STA_CSR2, ®); | |
95ea3627 ID |
1625 | |
1626 | /* | |
1627 | * Reset MAC and BBP registers. | |
1628 | */ | |
1d6205d0 | 1629 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1630 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
1631 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
1d6205d0 | 1632 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1633 | |
1d6205d0 | 1634 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1635 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
1636 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
1d6205d0 | 1637 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1638 | |
1d6205d0 | 1639 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 | 1640 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
1d6205d0 | 1641 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 ID |
1642 | |
1643 | return 0; | |
1644 | } | |
1645 | ||
2b08da3f | 1646 | static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1647 | { |
1648 | unsigned int i; | |
95ea3627 ID |
1649 | u8 value; |
1650 | ||
1651 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1652 | rt61pci_bbp_read(rt2x00dev, 0, &value); | |
1653 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 1654 | return 0; |
95ea3627 ID |
1655 | udelay(REGISTER_BUSY_DELAY); |
1656 | } | |
1657 | ||
ec9c4989 | 1658 | rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); |
95ea3627 | 1659 | return -EACCES; |
2b08da3f ID |
1660 | } |
1661 | ||
1662 | static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1663 | { | |
1664 | unsigned int i; | |
1665 | u16 eeprom; | |
1666 | u8 reg_id; | |
1667 | u8 value; | |
1668 | ||
1669 | if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev))) | |
1670 | return -EACCES; | |
95ea3627 | 1671 | |
95ea3627 ID |
1672 | rt61pci_bbp_write(rt2x00dev, 3, 0x00); |
1673 | rt61pci_bbp_write(rt2x00dev, 15, 0x30); | |
1674 | rt61pci_bbp_write(rt2x00dev, 21, 0xc8); | |
1675 | rt61pci_bbp_write(rt2x00dev, 22, 0x38); | |
1676 | rt61pci_bbp_write(rt2x00dev, 23, 0x06); | |
1677 | rt61pci_bbp_write(rt2x00dev, 24, 0xfe); | |
1678 | rt61pci_bbp_write(rt2x00dev, 25, 0x0a); | |
1679 | rt61pci_bbp_write(rt2x00dev, 26, 0x0d); | |
1680 | rt61pci_bbp_write(rt2x00dev, 34, 0x12); | |
1681 | rt61pci_bbp_write(rt2x00dev, 37, 0x07); | |
1682 | rt61pci_bbp_write(rt2x00dev, 39, 0xf8); | |
1683 | rt61pci_bbp_write(rt2x00dev, 41, 0x60); | |
1684 | rt61pci_bbp_write(rt2x00dev, 53, 0x10); | |
1685 | rt61pci_bbp_write(rt2x00dev, 54, 0x18); | |
1686 | rt61pci_bbp_write(rt2x00dev, 60, 0x10); | |
1687 | rt61pci_bbp_write(rt2x00dev, 61, 0x04); | |
1688 | rt61pci_bbp_write(rt2x00dev, 62, 0x04); | |
1689 | rt61pci_bbp_write(rt2x00dev, 75, 0xfe); | |
1690 | rt61pci_bbp_write(rt2x00dev, 86, 0xfe); | |
1691 | rt61pci_bbp_write(rt2x00dev, 88, 0xfe); | |
1692 | rt61pci_bbp_write(rt2x00dev, 90, 0x0f); | |
1693 | rt61pci_bbp_write(rt2x00dev, 99, 0x00); | |
1694 | rt61pci_bbp_write(rt2x00dev, 102, 0x16); | |
1695 | rt61pci_bbp_write(rt2x00dev, 107, 0x04); | |
1696 | ||
95ea3627 ID |
1697 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
1698 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1699 | ||
1700 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1701 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1702 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
1703 | rt61pci_bbp_write(rt2x00dev, reg_id, value); |
1704 | } | |
1705 | } | |
95ea3627 ID |
1706 | |
1707 | return 0; | |
1708 | } | |
1709 | ||
1710 | /* | |
1711 | * Device state switch handlers. | |
1712 | */ | |
95ea3627 ID |
1713 | static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
1714 | enum dev_state state) | |
1715 | { | |
b550911a | 1716 | int mask = (state == STATE_RADIO_IRQ_OFF); |
95ea3627 | 1717 | u32 reg; |
5846a550 | 1718 | unsigned long flags; |
95ea3627 ID |
1719 | |
1720 | /* | |
1721 | * When interrupts are being enabled, the interrupt registers | |
1722 | * should clear the register to assure a clean state. | |
1723 | */ | |
1724 | if (state == STATE_RADIO_IRQ_ON) { | |
1d6205d0 GJ |
1725 | rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); |
1726 | rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); | |
95ea3627 | 1727 | |
1d6205d0 GJ |
1728 | rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); |
1729 | rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); | |
95ea3627 ID |
1730 | } |
1731 | ||
1732 | /* | |
1733 | * Only toggle the interrupts bits we are going to use. | |
1734 | * Non-checked interrupt bits are disabled by default. | |
1735 | */ | |
5846a550 HS |
1736 | spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); |
1737 | ||
1d6205d0 | 1738 | rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); |
95ea3627 ID |
1739 | rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); |
1740 | rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); | |
6646505d | 1741 | rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); |
95ea3627 ID |
1742 | rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); |
1743 | rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); | |
1d6205d0 | 1744 | rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); |
95ea3627 | 1745 | |
1d6205d0 | 1746 | rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); |
95ea3627 ID |
1747 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); |
1748 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); | |
1749 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); | |
1750 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); | |
1751 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); | |
1752 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); | |
1753 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); | |
1754 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); | |
6646505d | 1755 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask); |
1d6205d0 | 1756 | rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); |
5846a550 HS |
1757 | |
1758 | spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); | |
1759 | ||
1760 | if (state == STATE_RADIO_IRQ_OFF) { | |
1761 | /* | |
1762 | * Ensure that all tasklets are finished. | |
1763 | */ | |
abc11994 HS |
1764 | tasklet_kill(&rt2x00dev->txstatus_tasklet); |
1765 | tasklet_kill(&rt2x00dev->rxdone_tasklet); | |
1766 | tasklet_kill(&rt2x00dev->autowake_tasklet); | |
1767 | tasklet_kill(&rt2x00dev->tbtt_tasklet); | |
5846a550 | 1768 | } |
95ea3627 ID |
1769 | } |
1770 | ||
1771 | static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) | |
1772 | { | |
1773 | u32 reg; | |
1774 | ||
1775 | /* | |
1776 | * Initialize all registers. | |
1777 | */ | |
2b08da3f ID |
1778 | if (unlikely(rt61pci_init_queues(rt2x00dev) || |
1779 | rt61pci_init_registers(rt2x00dev) || | |
1780 | rt61pci_init_bbp(rt2x00dev))) | |
95ea3627 | 1781 | return -EIO; |
95ea3627 ID |
1782 | |
1783 | /* | |
1784 | * Enable RX. | |
1785 | */ | |
1d6205d0 | 1786 | rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); |
95ea3627 | 1787 | rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); |
1d6205d0 | 1788 | rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); |
95ea3627 | 1789 | |
95ea3627 ID |
1790 | return 0; |
1791 | } | |
1792 | ||
1793 | static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1794 | { | |
95ea3627 | 1795 | /* |
a2c9b652 | 1796 | * Disable power |
95ea3627 | 1797 | */ |
1d6205d0 | 1798 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
95ea3627 ID |
1799 | } |
1800 | ||
1801 | static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) | |
1802 | { | |
9655a6ec | 1803 | u32 reg, reg2; |
95ea3627 ID |
1804 | unsigned int i; |
1805 | char put_to_sleep; | |
95ea3627 ID |
1806 | |
1807 | put_to_sleep = (state != STATE_AWAKE); | |
1808 | ||
1d6205d0 | 1809 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®); |
95ea3627 ID |
1810 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); |
1811 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); | |
1d6205d0 | 1812 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1813 | |
1814 | /* | |
1815 | * Device is not guaranteed to be in the requested state yet. | |
1816 | * We must wait until the register indicates that the | |
1817 | * device has entered the correct state. | |
1818 | */ | |
1819 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1d6205d0 | 1820 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®2); |
9655a6ec | 1821 | state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); |
2b08da3f | 1822 | if (state == !put_to_sleep) |
95ea3627 | 1823 | return 0; |
1d6205d0 | 1824 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1825 | msleep(10); |
1826 | } | |
1827 | ||
95ea3627 ID |
1828 | return -EBUSY; |
1829 | } | |
1830 | ||
1831 | static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1832 | enum dev_state state) | |
1833 | { | |
1834 | int retval = 0; | |
1835 | ||
1836 | switch (state) { | |
1837 | case STATE_RADIO_ON: | |
1838 | retval = rt61pci_enable_radio(rt2x00dev); | |
1839 | break; | |
1840 | case STATE_RADIO_OFF: | |
1841 | rt61pci_disable_radio(rt2x00dev); | |
1842 | break; | |
2b08da3f ID |
1843 | case STATE_RADIO_IRQ_ON: |
1844 | case STATE_RADIO_IRQ_OFF: | |
1845 | rt61pci_toggle_irq(rt2x00dev, state); | |
95ea3627 ID |
1846 | break; |
1847 | case STATE_DEEP_SLEEP: | |
1848 | case STATE_SLEEP: | |
1849 | case STATE_STANDBY: | |
1850 | case STATE_AWAKE: | |
1851 | retval = rt61pci_set_state(rt2x00dev, state); | |
1852 | break; | |
1853 | default: | |
1854 | retval = -ENOTSUPP; | |
1855 | break; | |
1856 | } | |
1857 | ||
2b08da3f | 1858 | if (unlikely(retval)) |
ec9c4989 JP |
1859 | rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", |
1860 | state, retval); | |
2b08da3f | 1861 | |
95ea3627 ID |
1862 | return retval; |
1863 | } | |
1864 | ||
1865 | /* | |
1866 | * TX descriptor initialization | |
1867 | */ | |
93331458 | 1868 | static void rt61pci_write_tx_desc(struct queue_entry *entry, |
61e754f4 | 1869 | struct txentry_desc *txdesc) |
95ea3627 | 1870 | { |
93331458 | 1871 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
1d6205d0 | 1872 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
85b7a8b3 | 1873 | __le32 *txd = entry_priv->desc; |
95ea3627 ID |
1874 | u32 word; |
1875 | ||
1876 | /* | |
1877 | * Start writing the descriptor words. | |
1878 | */ | |
1879 | rt2x00_desc_read(txd, 1, &word); | |
2b23cdaa HS |
1880 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); |
1881 | rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); | |
1882 | rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); | |
1883 | rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); | |
61e754f4 | 1884 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); |
5adf6d63 ID |
1885 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, |
1886 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
4de36fe5 | 1887 | rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); |
95ea3627 ID |
1888 | rt2x00_desc_write(txd, 1, word); |
1889 | ||
1890 | rt2x00_desc_read(txd, 2, &word); | |
26a1d07f HS |
1891 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); |
1892 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); | |
1893 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, | |
1894 | txdesc->u.plcp.length_low); | |
1895 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, | |
1896 | txdesc->u.plcp.length_high); | |
95ea3627 ID |
1897 | rt2x00_desc_write(txd, 2, word); |
1898 | ||
61e754f4 | 1899 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { |
1ce9cdac ID |
1900 | _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); |
1901 | _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); | |
61e754f4 ID |
1902 | } |
1903 | ||
95ea3627 | 1904 | rt2x00_desc_read(txd, 5, &word); |
93331458 | 1905 | rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); |
4de36fe5 GW |
1906 | rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, |
1907 | skbdesc->entry->entry_idx); | |
95ea3627 | 1908 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, |
93331458 | 1909 | TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); |
95ea3627 ID |
1910 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
1911 | rt2x00_desc_write(txd, 5, word); | |
1912 | ||
2b23cdaa | 1913 | if (entry->queue->qid != QID_BEACON) { |
6b97cb04 GW |
1914 | rt2x00_desc_read(txd, 6, &word); |
1915 | rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, | |
1916 | skbdesc->skb_dma); | |
1917 | rt2x00_desc_write(txd, 6, word); | |
4de36fe5 | 1918 | |
d7bafff3 | 1919 | rt2x00_desc_read(txd, 11, &word); |
df624ca5 GW |
1920 | rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, |
1921 | txdesc->length); | |
d7bafff3 AB |
1922 | rt2x00_desc_write(txd, 11, word); |
1923 | } | |
95ea3627 | 1924 | |
e01f1ec3 GW |
1925 | /* |
1926 | * Writing TXD word 0 must the last to prevent a race condition with | |
1927 | * the device, whereby the device may take hold of the TXD before we | |
1928 | * finished updating it. | |
1929 | */ | |
95ea3627 ID |
1930 | rt2x00_desc_read(txd, 0, &word); |
1931 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); | |
1932 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1933 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
181d6902 | 1934 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
95ea3627 | 1935 | rt2x00_set_field32(&word, TXD_W0_ACK, |
181d6902 | 1936 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
95ea3627 | 1937 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
181d6902 | 1938 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
95ea3627 | 1939 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
076f9582 | 1940 | (txdesc->rate_mode == RATE_MODE_OFDM)); |
2517794b | 1941 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); |
95ea3627 | 1942 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
61486e0f | 1943 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
61e754f4 ID |
1944 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, |
1945 | test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); | |
1946 | rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, | |
1947 | test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); | |
1948 | rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); | |
df624ca5 | 1949 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); |
95ea3627 | 1950 | rt2x00_set_field32(&word, TXD_W0_BURST, |
181d6902 | 1951 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); |
61e754f4 | 1952 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); |
95ea3627 | 1953 | rt2x00_desc_write(txd, 0, word); |
85b7a8b3 GW |
1954 | |
1955 | /* | |
1956 | * Register descriptor details in skb frame descriptor. | |
1957 | */ | |
1958 | skbdesc->desc = txd; | |
2b23cdaa HS |
1959 | skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE : |
1960 | TXD_DESC_SIZE; | |
95ea3627 ID |
1961 | } |
1962 | ||
1963 | /* | |
1964 | * TX data initialization | |
1965 | */ | |
f224f4ef GW |
1966 | static void rt61pci_write_beacon(struct queue_entry *entry, |
1967 | struct txentry_desc *txdesc) | |
bd88a781 ID |
1968 | { |
1969 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
1d6205d0 | 1970 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
bd88a781 | 1971 | unsigned int beacon_base; |
739fd940 | 1972 | unsigned int padding_len; |
d76dfc61 | 1973 | u32 orig_reg, reg; |
bd88a781 ID |
1974 | |
1975 | /* | |
1976 | * Disable beaconing while we are reloading the beacon data, | |
1977 | * otherwise we might be sending out invalid data. | |
1978 | */ | |
1d6205d0 | 1979 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); |
d76dfc61 | 1980 | orig_reg = reg; |
bd88a781 | 1981 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
1d6205d0 | 1982 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); |
bd88a781 | 1983 | |
5c3b685c GW |
1984 | /* |
1985 | * Write the TX descriptor for the beacon. | |
1986 | */ | |
93331458 | 1987 | rt61pci_write_tx_desc(entry, txdesc); |
5c3b685c GW |
1988 | |
1989 | /* | |
1990 | * Dump beacon to userspace through debugfs. | |
1991 | */ | |
1992 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
1993 | ||
bd88a781 | 1994 | /* |
739fd940 | 1995 | * Write entire beacon with descriptor and padding to register. |
bd88a781 | 1996 | */ |
739fd940 | 1997 | padding_len = roundup(entry->skb->len, 4) - entry->skb->len; |
d76dfc61 | 1998 | if (padding_len && skb_pad(entry->skb, padding_len)) { |
ec9c4989 | 1999 | rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); |
d76dfc61 SF |
2000 | /* skb freed by skb_pad() on failure */ |
2001 | entry->skb = NULL; | |
1d6205d0 | 2002 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); |
d76dfc61 SF |
2003 | return; |
2004 | } | |
2005 | ||
bd88a781 | 2006 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
1d6205d0 GJ |
2007 | rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base, |
2008 | entry_priv->desc, TXINFO_SIZE); | |
2009 | rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, | |
2010 | entry->skb->data, | |
2011 | entry->skb->len + padding_len); | |
bd88a781 | 2012 | |
d61cb266 GW |
2013 | /* |
2014 | * Enable beaconing again. | |
2015 | * | |
2016 | * For Wi-Fi faily generated beacons between participating | |
2017 | * stations. Set TBTT phase adaptive adjustment step to 8us. | |
2018 | */ | |
1d6205d0 | 2019 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); |
d61cb266 | 2020 | |
d61cb266 | 2021 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); |
1d6205d0 | 2022 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); |
d61cb266 | 2023 | |
bd88a781 ID |
2024 | /* |
2025 | * Clean up beacon skb. | |
2026 | */ | |
2027 | dev_kfree_skb_any(entry->skb); | |
2028 | entry->skb = NULL; | |
2029 | } | |
2030 | ||
69cf36a4 HS |
2031 | static void rt61pci_clear_beacon(struct queue_entry *entry) |
2032 | { | |
2033 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
bc0df75a | 2034 | u32 orig_reg, reg; |
69cf36a4 HS |
2035 | |
2036 | /* | |
2037 | * Disable beaconing while we are reloading the beacon data, | |
2038 | * otherwise we might be sending out invalid data. | |
2039 | */ | |
bc0df75a SG |
2040 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &orig_reg); |
2041 | reg = orig_reg; | |
69cf36a4 | 2042 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
1d6205d0 | 2043 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); |
69cf36a4 HS |
2044 | |
2045 | /* | |
2046 | * Clear beacon. | |
2047 | */ | |
1d6205d0 GJ |
2048 | rt2x00mmio_register_write(rt2x00dev, |
2049 | HW_BEACON_OFFSET(entry->entry_idx), 0); | |
69cf36a4 HS |
2050 | |
2051 | /* | |
bc0df75a | 2052 | * Restore global beaconing state. |
69cf36a4 | 2053 | */ |
bc0df75a | 2054 | rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); |
69cf36a4 HS |
2055 | } |
2056 | ||
95ea3627 ID |
2057 | /* |
2058 | * RX control handlers | |
2059 | */ | |
2060 | static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) | |
2061 | { | |
ba2ab471 | 2062 | u8 offset = rt2x00dev->lna_gain; |
95ea3627 ID |
2063 | u8 lna; |
2064 | ||
2065 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); | |
2066 | switch (lna) { | |
2067 | case 3: | |
ba2ab471 | 2068 | offset += 90; |
95ea3627 ID |
2069 | break; |
2070 | case 2: | |
ba2ab471 | 2071 | offset += 74; |
95ea3627 ID |
2072 | break; |
2073 | case 1: | |
ba2ab471 | 2074 | offset += 64; |
95ea3627 ID |
2075 | break; |
2076 | default: | |
2077 | return 0; | |
2078 | } | |
2079 | ||
57fbcce3 | 2080 | if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { |
95ea3627 ID |
2081 | if (lna == 3 || lna == 2) |
2082 | offset += 10; | |
95ea3627 ID |
2083 | } |
2084 | ||
2085 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; | |
2086 | } | |
2087 | ||
181d6902 | 2088 | static void rt61pci_fill_rxdone(struct queue_entry *entry, |
55887511 | 2089 | struct rxdone_entry_desc *rxdesc) |
95ea3627 | 2090 | { |
61e754f4 | 2091 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
1d6205d0 | 2092 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
95ea3627 ID |
2093 | u32 word0; |
2094 | u32 word1; | |
2095 | ||
b8be63ff ID |
2096 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
2097 | rt2x00_desc_read(entry_priv->desc, 1, &word1); | |
95ea3627 | 2098 | |
4150c572 | 2099 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 2100 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
95ea3627 | 2101 | |
78b8f3b0 GW |
2102 | rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); |
2103 | rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); | |
61e754f4 ID |
2104 | |
2105 | if (rxdesc->cipher != CIPHER_NONE) { | |
1ce9cdac ID |
2106 | _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]); |
2107 | _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]); | |
74415edb ID |
2108 | rxdesc->dev_flags |= RXDONE_CRYPTO_IV; |
2109 | ||
61e754f4 | 2110 | _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv); |
74415edb | 2111 | rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; |
61e754f4 ID |
2112 | |
2113 | /* | |
2114 | * Hardware has stripped IV/EIV data from 802.11 frame during | |
b34e620f | 2115 | * decryption. It has provided the data separately but rt2x00lib |
61e754f4 ID |
2116 | * should decide if it should be reinserted. |
2117 | */ | |
2118 | rxdesc->flags |= RX_FLAG_IV_STRIPPED; | |
2119 | ||
2120 | /* | |
a0aff623 GW |
2121 | * The hardware has already checked the Michael Mic and has |
2122 | * stripped it from the frame. Signal this to mac80211. | |
61e754f4 ID |
2123 | */ |
2124 | rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; | |
2125 | ||
2126 | if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) | |
2127 | rxdesc->flags |= RX_FLAG_DECRYPTED; | |
2128 | else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) | |
2129 | rxdesc->flags |= RX_FLAG_MMIC_ERROR; | |
2130 | } | |
2131 | ||
95ea3627 ID |
2132 | /* |
2133 | * Obtain the status about this packet. | |
89993890 ID |
2134 | * When frame was received with an OFDM bitrate, |
2135 | * the signal is the PLCP value. If it was received with | |
2136 | * a CCK bitrate the signal is the rate in 100kbit/s. | |
95ea3627 | 2137 | */ |
181d6902 | 2138 | rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
61e754f4 | 2139 | rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); |
181d6902 | 2140 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 2141 | |
19d30e02 ID |
2142 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
2143 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | |
6c6aa3c0 ID |
2144 | else |
2145 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; | |
19d30e02 ID |
2146 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
2147 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
95ea3627 ID |
2148 | } |
2149 | ||
2150 | /* | |
2151 | * Interrupt functions. | |
2152 | */ | |
2153 | static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) | |
2154 | { | |
181d6902 ID |
2155 | struct data_queue *queue; |
2156 | struct queue_entry *entry; | |
2157 | struct queue_entry *entry_done; | |
1d6205d0 | 2158 | struct queue_entry_priv_mmio *entry_priv; |
181d6902 | 2159 | struct txdone_entry_desc txdesc; |
95ea3627 ID |
2160 | u32 word; |
2161 | u32 reg; | |
95ea3627 ID |
2162 | int type; |
2163 | int index; | |
e6474c3c | 2164 | int i; |
95ea3627 ID |
2165 | |
2166 | /* | |
e6474c3c ID |
2167 | * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO |
2168 | * at most X times and also stop processing once the TX_STA_FIFO_VALID | |
2169 | * flag is not set anymore. | |
2170 | * | |
2171 | * The legacy drivers use X=TX_RING_SIZE but state in a comment | |
2172 | * that the TX_STA_FIFO stack has a size of 16. We stick to our | |
2173 | * tx ring size for now. | |
95ea3627 | 2174 | */ |
98cd6c71 | 2175 | for (i = 0; i < rt2x00dev->tx->limit; i++) { |
1d6205d0 | 2176 | rt2x00mmio_register_read(rt2x00dev, STA_CSR4, ®); |
95ea3627 ID |
2177 | if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) |
2178 | break; | |
2179 | ||
95ea3627 ID |
2180 | /* |
2181 | * Skip this entry when it contains an invalid | |
181d6902 | 2182 | * queue identication number. |
95ea3627 ID |
2183 | */ |
2184 | type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); | |
11f818e0 | 2185 | queue = rt2x00queue_get_tx_queue(rt2x00dev, type); |
181d6902 | 2186 | if (unlikely(!queue)) |
95ea3627 ID |
2187 | continue; |
2188 | ||
2189 | /* | |
2190 | * Skip this entry when it contains an invalid | |
2191 | * index number. | |
2192 | */ | |
2193 | index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); | |
181d6902 | 2194 | if (unlikely(index >= queue->limit)) |
95ea3627 ID |
2195 | continue; |
2196 | ||
181d6902 | 2197 | entry = &queue->entries[index]; |
b8be63ff ID |
2198 | entry_priv = entry->priv_data; |
2199 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 ID |
2200 | |
2201 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | |
2202 | !rt2x00_get_field32(word, TXD_W0_VALID)) | |
2203 | return; | |
2204 | ||
181d6902 | 2205 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
62bc060b | 2206 | while (entry != entry_done) { |
181d6902 ID |
2207 | /* Catch up. |
2208 | * Just report any entries we missed as failed. | |
2209 | */ | |
ec9c4989 JP |
2210 | rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n", |
2211 | entry_done->entry_idx); | |
181d6902 | 2212 | |
65b7fc97 | 2213 | rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN); |
181d6902 | 2214 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
62bc060b MN |
2215 | } |
2216 | ||
95ea3627 ID |
2217 | /* |
2218 | * Obtain the status about this packet. | |
2219 | */ | |
fb55f4d1 ID |
2220 | txdesc.flags = 0; |
2221 | switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { | |
2222 | case 0: /* Success, maybe with retry */ | |
2223 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | |
2224 | break; | |
2225 | case 6: /* Failure, excessive retries */ | |
2226 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); | |
2227 | /* Don't break, this is a failed frame! */ | |
2228 | default: /* Failure */ | |
2229 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | |
2230 | } | |
181d6902 | 2231 | txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); |
95ea3627 | 2232 | |
e1b4d7b7 ID |
2233 | /* |
2234 | * the frame was retried at least once | |
2235 | * -> hw used fallback rates | |
2236 | */ | |
2237 | if (txdesc.retry) | |
2238 | __set_bit(TXDONE_FALLBACK, &txdesc.flags); | |
2239 | ||
e513a0b6 | 2240 | rt2x00lib_txdone(entry, &txdesc); |
95ea3627 ID |
2241 | } |
2242 | } | |
2243 | ||
9e189446 GW |
2244 | static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev) |
2245 | { | |
deee0214 | 2246 | struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf }; |
9e189446 GW |
2247 | |
2248 | rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); | |
2249 | } | |
2250 | ||
7a5a681a HS |
2251 | static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, |
2252 | struct rt2x00_field32 irq_field) | |
95ea3627 | 2253 | { |
5846a550 | 2254 | u32 reg; |
95ea3627 ID |
2255 | |
2256 | /* | |
5846a550 HS |
2257 | * Enable a single interrupt. The interrupt mask register |
2258 | * access needs locking. | |
95ea3627 | 2259 | */ |
0aa13b2e | 2260 | spin_lock_irq(&rt2x00dev->irqmask_lock); |
95ea3627 | 2261 | |
1d6205d0 | 2262 | rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); |
5846a550 | 2263 | rt2x00_set_field32(®, irq_field, 0); |
1d6205d0 | 2264 | rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); |
95ea3627 | 2265 | |
0aa13b2e | 2266 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
5846a550 | 2267 | } |
95ea3627 | 2268 | |
5846a550 HS |
2269 | static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev, |
2270 | struct rt2x00_field32 irq_field) | |
2271 | { | |
5846a550 | 2272 | u32 reg; |
95ea3627 | 2273 | |
9e189446 | 2274 | /* |
5846a550 HS |
2275 | * Enable a single MCU interrupt. The interrupt mask register |
2276 | * access needs locking. | |
9e189446 | 2277 | */ |
0aa13b2e | 2278 | spin_lock_irq(&rt2x00dev->irqmask_lock); |
9e189446 | 2279 | |
1d6205d0 | 2280 | rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); |
5846a550 | 2281 | rt2x00_set_field32(®, irq_field, 0); |
1d6205d0 | 2282 | rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); |
fa43750f | 2283 | |
0aa13b2e | 2284 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
95ea3627 ID |
2285 | } |
2286 | ||
5846a550 HS |
2287 | static void rt61pci_txstatus_tasklet(unsigned long data) |
2288 | { | |
2289 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
2290 | rt61pci_txdone(rt2x00dev); | |
abc11994 HS |
2291 | if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
2292 | rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE); | |
5846a550 HS |
2293 | } |
2294 | ||
2295 | static void rt61pci_tbtt_tasklet(unsigned long data) | |
2296 | { | |
2297 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
2298 | rt2x00lib_beacondone(rt2x00dev); | |
abc11994 HS |
2299 | if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
2300 | rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE); | |
5846a550 HS |
2301 | } |
2302 | ||
2303 | static void rt61pci_rxdone_tasklet(unsigned long data) | |
2304 | { | |
2305 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
1d6205d0 | 2306 | if (rt2x00mmio_rxdone(rt2x00dev)) |
abc11994 HS |
2307 | tasklet_schedule(&rt2x00dev->rxdone_tasklet); |
2308 | else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) | |
16638937 | 2309 | rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE); |
5846a550 HS |
2310 | } |
2311 | ||
2312 | static void rt61pci_autowake_tasklet(unsigned long data) | |
2313 | { | |
2314 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | |
2315 | rt61pci_wakeup(rt2x00dev); | |
1d6205d0 GJ |
2316 | rt2x00mmio_register_write(rt2x00dev, |
2317 | M2H_CMD_DONE_CSR, 0xffffffff); | |
abc11994 HS |
2318 | if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
2319 | rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP); | |
5846a550 | 2320 | } |
78e256c9 HS |
2321 | |
2322 | static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) | |
2323 | { | |
2324 | struct rt2x00_dev *rt2x00dev = dev_instance; | |
5846a550 HS |
2325 | u32 reg_mcu, mask_mcu; |
2326 | u32 reg, mask; | |
78e256c9 HS |
2327 | |
2328 | /* | |
2329 | * Get the interrupt sources & saved to local variable. | |
2330 | * Write register value back to clear pending interrupts. | |
2331 | */ | |
1d6205d0 GJ |
2332 | rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); |
2333 | rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); | |
78e256c9 | 2334 | |
1d6205d0 GJ |
2335 | rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); |
2336 | rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); | |
78e256c9 HS |
2337 | |
2338 | if (!reg && !reg_mcu) | |
2339 | return IRQ_NONE; | |
2340 | ||
2341 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) | |
2342 | return IRQ_HANDLED; | |
2343 | ||
5846a550 HS |
2344 | /* |
2345 | * Schedule tasklets for interrupt handling. | |
2346 | */ | |
2347 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) | |
2348 | tasklet_schedule(&rt2x00dev->rxdone_tasklet); | |
2349 | ||
2350 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) | |
2351 | tasklet_schedule(&rt2x00dev->txstatus_tasklet); | |
2352 | ||
2353 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE)) | |
2354 | tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); | |
2355 | ||
2356 | if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP)) | |
2357 | tasklet_schedule(&rt2x00dev->autowake_tasklet); | |
2358 | ||
2359 | /* | |
2360 | * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits | |
2361 | * for interrupts and interrupt masks we can just use the value of | |
2362 | * INT_SOURCE_CSR to create the interrupt mask. | |
2363 | */ | |
2364 | mask = reg; | |
2365 | mask_mcu = reg_mcu; | |
2366 | ||
2367 | /* | |
2368 | * Disable all interrupts for which a tasklet was scheduled right now, | |
2369 | * the tasklet will reenable the appropriate interrupts. | |
2370 | */ | |
0aa13b2e | 2371 | spin_lock(&rt2x00dev->irqmask_lock); |
5846a550 | 2372 | |
1d6205d0 | 2373 | rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); |
5846a550 | 2374 | reg |= mask; |
1d6205d0 | 2375 | rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); |
78e256c9 | 2376 | |
1d6205d0 | 2377 | rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); |
5846a550 | 2378 | reg |= mask_mcu; |
1d6205d0 | 2379 | rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); |
5846a550 | 2380 | |
0aa13b2e | 2381 | spin_unlock(&rt2x00dev->irqmask_lock); |
5846a550 HS |
2382 | |
2383 | return IRQ_HANDLED; | |
78e256c9 HS |
2384 | } |
2385 | ||
95ea3627 ID |
2386 | /* |
2387 | * Device probe functions. | |
2388 | */ | |
2389 | static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
2390 | { | |
2391 | struct eeprom_93cx6 eeprom; | |
2392 | u32 reg; | |
2393 | u16 word; | |
2394 | u8 *mac; | |
2395 | s8 value; | |
2396 | ||
1d6205d0 | 2397 | rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); |
95ea3627 ID |
2398 | |
2399 | eeprom.data = rt2x00dev; | |
2400 | eeprom.register_read = rt61pci_eepromregister_read; | |
2401 | eeprom.register_write = rt61pci_eepromregister_write; | |
2402 | eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? | |
2403 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; | |
2404 | eeprom.reg_data_in = 0; | |
2405 | eeprom.reg_data_out = 0; | |
2406 | eeprom.reg_data_clock = 0; | |
2407 | eeprom.reg_chip_select = 0; | |
2408 | ||
2409 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, | |
2410 | EEPROM_SIZE / sizeof(u16)); | |
2411 | ||
2412 | /* | |
2413 | * Start validation of the data that has been read. | |
2414 | */ | |
2415 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
2416 | if (!is_valid_ether_addr(mac)) { | |
f4f7f414 | 2417 | eth_random_addr(mac); |
ec9c4989 | 2418 | rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); |
95ea3627 ID |
2419 | } |
2420 | ||
2421 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
2422 | if (word == 0xffff) { | |
2423 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
362f3b6b ID |
2424 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
2425 | ANTENNA_B); | |
2426 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, | |
2427 | ANTENNA_B); | |
95ea3627 ID |
2428 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); |
2429 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); | |
2430 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
2431 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225); | |
2432 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
ec9c4989 | 2433 | rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); |
95ea3627 ID |
2434 | } |
2435 | ||
2436 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
2437 | if (word == 0xffff) { | |
2438 | rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0); | |
2439 | rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0); | |
91581b62 ID |
2440 | rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0); |
2441 | rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0); | |
95ea3627 ID |
2442 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); |
2443 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); | |
2444 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); | |
2445 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
ec9c4989 | 2446 | rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); |
95ea3627 ID |
2447 | } |
2448 | ||
2449 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); | |
2450 | if (word == 0xffff) { | |
2451 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, | |
2452 | LED_MODE_DEFAULT); | |
2453 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); | |
ec9c4989 | 2454 | rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word); |
95ea3627 ID |
2455 | } |
2456 | ||
2457 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
2458 | if (word == 0xffff) { | |
2459 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
2460 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); | |
2461 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
ec9c4989 | 2462 | rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); |
95ea3627 ID |
2463 | } |
2464 | ||
2465 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); | |
2466 | if (word == 0xffff) { | |
2467 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
2468 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
2469 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
ec9c4989 | 2470 | rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); |
95ea3627 ID |
2471 | } else { |
2472 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); | |
2473 | if (value < -10 || value > 10) | |
2474 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
2475 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); | |
2476 | if (value < -10 || value > 10) | |
2477 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
2478 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
2479 | } | |
2480 | ||
2481 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); | |
2482 | if (word == 0xffff) { | |
2483 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
2484 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
2485 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
ec9c4989 | 2486 | rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); |
95ea3627 ID |
2487 | } else { |
2488 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); | |
2489 | if (value < -10 || value > 10) | |
2490 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
2491 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); | |
2492 | if (value < -10 || value > 10) | |
2493 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
2494 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
2495 | } | |
2496 | ||
2497 | return 0; | |
2498 | } | |
2499 | ||
2500 | static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
2501 | { | |
2502 | u32 reg; | |
2503 | u16 value; | |
2504 | u16 eeprom; | |
95ea3627 ID |
2505 | |
2506 | /* | |
2507 | * Read EEPROM word for configuration. | |
2508 | */ | |
2509 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
2510 | ||
2511 | /* | |
2512 | * Identify RF chipset. | |
95ea3627 | 2513 | */ |
95ea3627 | 2514 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); |
1d6205d0 | 2515 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); |
49e721ec GW |
2516 | rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), |
2517 | value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); | |
95ea3627 | 2518 | |
5122d898 GW |
2519 | if (!rt2x00_rf(rt2x00dev, RF5225) && |
2520 | !rt2x00_rf(rt2x00dev, RF5325) && | |
2521 | !rt2x00_rf(rt2x00dev, RF2527) && | |
2522 | !rt2x00_rf(rt2x00dev, RF2529)) { | |
ec9c4989 | 2523 | rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); |
95ea3627 ID |
2524 | return -ENODEV; |
2525 | } | |
2526 | ||
e4cd2ff8 | 2527 | /* |
49513481 | 2528 | * Determine number of antennas. |
e4cd2ff8 ID |
2529 | */ |
2530 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2) | |
7dab73b3 | 2531 | __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags); |
e4cd2ff8 | 2532 | |
95ea3627 ID |
2533 | /* |
2534 | * Identify default antenna configuration. | |
2535 | */ | |
addc81bd | 2536 | rt2x00dev->default_ant.tx = |
95ea3627 | 2537 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 2538 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
2539 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
2540 | ||
2541 | /* | |
2542 | * Read the Frame type. | |
2543 | */ | |
2544 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) | |
7dab73b3 | 2545 | __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); |
95ea3627 | 2546 | |
95ea3627 | 2547 | /* |
b34e620f | 2548 | * Detect if this device has a hardware controlled radio. |
95ea3627 ID |
2549 | */ |
2550 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) | |
7dab73b3 | 2551 | __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); |
95ea3627 ID |
2552 | |
2553 | /* | |
2554 | * Read frequency offset and RF programming sequence. | |
2555 | */ | |
2556 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
2557 | if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) | |
7dab73b3 | 2558 | __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags); |
95ea3627 ID |
2559 | |
2560 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
2561 | ||
2562 | /* | |
2563 | * Read external LNA informations. | |
2564 | */ | |
2565 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
2566 | ||
2567 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) | |
7dab73b3 | 2568 | __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); |
95ea3627 | 2569 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) |
7dab73b3 | 2570 | __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); |
95ea3627 | 2571 | |
e4cd2ff8 | 2572 | /* |
b34e620f | 2573 | * When working with a RF2529 chip without double antenna, |
e4cd2ff8 ID |
2574 | * the antenna settings should be gathered from the NIC |
2575 | * eeprom word. | |
2576 | */ | |
5122d898 | 2577 | if (rt2x00_rf(rt2x00dev, RF2529) && |
f3218bee | 2578 | !rt2x00_has_cap_double_antenna(rt2x00dev)) { |
91581b62 ID |
2579 | rt2x00dev->default_ant.rx = |
2580 | ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED); | |
2581 | rt2x00dev->default_ant.tx = | |
2582 | ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED); | |
e4cd2ff8 ID |
2583 | |
2584 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) | |
2585 | rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; | |
2586 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) | |
2587 | rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; | |
2588 | } | |
2589 | ||
95ea3627 ID |
2590 | /* |
2591 | * Store led settings, for correct led behaviour. | |
2592 | * If the eeprom value is invalid, | |
2593 | * switch to default led mode. | |
2594 | */ | |
771fd565 | 2595 | #ifdef CONFIG_RT2X00_LIB_LEDS |
95ea3627 | 2596 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); |
a9450b70 ID |
2597 | value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); |
2598 | ||
475433be ID |
2599 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
2600 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
2601 | if (value == LED_MODE_SIGNAL_STRENGTH) | |
2602 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, | |
2603 | LED_TYPE_QUALITY); | |
95ea3627 | 2604 | |
a9450b70 ID |
2605 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); |
2606 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, | |
95ea3627 ID |
2607 | rt2x00_get_field16(eeprom, |
2608 | EEPROM_LED_POLARITY_GPIO_0)); | |
a9450b70 | 2609 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, |
95ea3627 ID |
2610 | rt2x00_get_field16(eeprom, |
2611 | EEPROM_LED_POLARITY_GPIO_1)); | |
a9450b70 | 2612 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, |
95ea3627 ID |
2613 | rt2x00_get_field16(eeprom, |
2614 | EEPROM_LED_POLARITY_GPIO_2)); | |
a9450b70 | 2615 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, |
95ea3627 ID |
2616 | rt2x00_get_field16(eeprom, |
2617 | EEPROM_LED_POLARITY_GPIO_3)); | |
a9450b70 | 2618 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, |
95ea3627 ID |
2619 | rt2x00_get_field16(eeprom, |
2620 | EEPROM_LED_POLARITY_GPIO_4)); | |
a9450b70 | 2621 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, |
95ea3627 | 2622 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); |
a9450b70 | 2623 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, |
95ea3627 ID |
2624 | rt2x00_get_field16(eeprom, |
2625 | EEPROM_LED_POLARITY_RDY_G)); | |
a9450b70 | 2626 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, |
95ea3627 ID |
2627 | rt2x00_get_field16(eeprom, |
2628 | EEPROM_LED_POLARITY_RDY_A)); | |
771fd565 | 2629 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
2630 | |
2631 | return 0; | |
2632 | } | |
2633 | ||
2634 | /* | |
2635 | * RF value list for RF5225 & RF5325 | |
2636 | * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled | |
2637 | */ | |
2638 | static const struct rf_channel rf_vals_noseq[] = { | |
2639 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
2640 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
2641 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
2642 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
2643 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
2644 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
2645 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
2646 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
2647 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
2648 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
2649 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
2650 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
2651 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
2652 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
2653 | ||
2654 | /* 802.11 UNI / HyperLan 2 */ | |
2655 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, | |
2656 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, | |
2657 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, | |
2658 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, | |
2659 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, | |
2660 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, | |
2661 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, | |
2662 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, | |
2663 | ||
2664 | /* 802.11 HyperLan 2 */ | |
2665 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, | |
2666 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, | |
2667 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, | |
2668 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, | |
2669 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, | |
2670 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, | |
2671 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, | |
2672 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, | |
2673 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, | |
2674 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, | |
2675 | ||
2676 | /* 802.11 UNII */ | |
2677 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, | |
2678 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, | |
2679 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, | |
2680 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, | |
2681 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, | |
2682 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, | |
2683 | ||
2684 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2685 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, | |
2686 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, | |
2687 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, | |
2688 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, | |
2689 | }; | |
2690 | ||
2691 | /* | |
2692 | * RF value list for RF5225 & RF5325 | |
2693 | * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled | |
2694 | */ | |
2695 | static const struct rf_channel rf_vals_seq[] = { | |
2696 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
2697 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
2698 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
2699 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
2700 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
2701 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
2702 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
2703 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
2704 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
2705 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
2706 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
2707 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
2708 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
2709 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
2710 | ||
2711 | /* 802.11 UNI / HyperLan 2 */ | |
2712 | { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 }, | |
2713 | { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 }, | |
2714 | { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b }, | |
2715 | { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b }, | |
2716 | { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 }, | |
2717 | { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 }, | |
2718 | { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 }, | |
2719 | { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b }, | |
2720 | ||
2721 | /* 802.11 HyperLan 2 */ | |
2722 | { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 }, | |
2723 | { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 }, | |
2724 | { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 }, | |
2725 | { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 }, | |
2726 | { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 }, | |
2727 | { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 }, | |
2728 | { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b }, | |
2729 | { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b }, | |
2730 | { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 }, | |
2731 | { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 }, | |
2732 | ||
2733 | /* 802.11 UNII */ | |
2734 | { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 }, | |
2735 | { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b }, | |
2736 | { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b }, | |
2737 | { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 }, | |
2738 | { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 }, | |
2739 | { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 }, | |
2740 | ||
2741 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2742 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b }, | |
2743 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 }, | |
2744 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b }, | |
2745 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 }, | |
2746 | }; | |
2747 | ||
8c5e7a5f | 2748 | static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
2749 | { |
2750 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
2751 | struct channel_info *info; |
2752 | char *tx_power; | |
95ea3627 ID |
2753 | unsigned int i; |
2754 | ||
93b6bd26 GW |
2755 | /* |
2756 | * Disable powersaving as default. | |
2757 | */ | |
2758 | rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
2759 | ||
95ea3627 ID |
2760 | /* |
2761 | * Initialize all hw fields. | |
2762 | */ | |
30686bf7 JB |
2763 | ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); |
2764 | ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); | |
2765 | ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); | |
2766 | ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); | |
95ea3627 | 2767 | |
14a3bf89 | 2768 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
2769 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
2770 | rt2x00_eeprom_addr(rt2x00dev, | |
2771 | EEPROM_MAC_ADDR_0)); | |
2772 | ||
95ea3627 | 2773 | /* |
e1b4d7b7 ID |
2774 | * As rt61 has a global fallback table we cannot specify |
2775 | * more then one tx rate per frame but since the hw will | |
2776 | * try several rates (based on the fallback table) we should | |
ba3b9e5e | 2777 | * initialize max_report_rates to the maximum number of rates |
e1b4d7b7 ID |
2778 | * we are going to try. Otherwise mac80211 will truncate our |
2779 | * reported tx rates and the rc algortihm will end up with | |
2780 | * incorrect data. | |
2781 | */ | |
ba3b9e5e HS |
2782 | rt2x00dev->hw->max_rates = 1; |
2783 | rt2x00dev->hw->max_report_rates = 7; | |
e1b4d7b7 ID |
2784 | rt2x00dev->hw->max_rate_tries = 1; |
2785 | ||
2786 | /* | |
95ea3627 ID |
2787 | * Initialize hw_mode information. |
2788 | */ | |
31562e80 ID |
2789 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
2790 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
95ea3627 | 2791 | |
f3218bee | 2792 | if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) { |
95ea3627 ID |
2793 | spec->num_channels = 14; |
2794 | spec->channels = rf_vals_noseq; | |
2795 | } else { | |
2796 | spec->num_channels = 14; | |
2797 | spec->channels = rf_vals_seq; | |
2798 | } | |
2799 | ||
5122d898 | 2800 | if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) { |
31562e80 | 2801 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 | 2802 | spec->num_channels = ARRAY_SIZE(rf_vals_seq); |
8c5e7a5f ID |
2803 | } |
2804 | ||
2805 | /* | |
2806 | * Create channel information array | |
2807 | */ | |
baeb2ffa | 2808 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
8c5e7a5f ID |
2809 | if (!info) |
2810 | return -ENOMEM; | |
2811 | ||
2812 | spec->channels_info = info; | |
95ea3627 | 2813 | |
8c5e7a5f | 2814 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); |
8d1331b3 ID |
2815 | for (i = 0; i < 14; i++) { |
2816 | info[i].max_power = MAX_TXPOWER; | |
2817 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
2818 | } | |
95ea3627 | 2819 | |
8c5e7a5f ID |
2820 | if (spec->num_channels > 14) { |
2821 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); | |
8d1331b3 ID |
2822 | for (i = 14; i < spec->num_channels; i++) { |
2823 | info[i].max_power = MAX_TXPOWER; | |
0a6f3a8e GJ |
2824 | info[i].default_power1 = |
2825 | TXPOWER_FROM_DEV(tx_power[i - 14]); | |
8d1331b3 | 2826 | } |
95ea3627 | 2827 | } |
8c5e7a5f ID |
2828 | |
2829 | return 0; | |
95ea3627 ID |
2830 | } |
2831 | ||
2832 | static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |
2833 | { | |
2834 | int retval; | |
a396e100 | 2835 | u32 reg; |
95ea3627 | 2836 | |
117839bd PR |
2837 | /* |
2838 | * Disable power saving. | |
2839 | */ | |
1d6205d0 | 2840 | rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); |
117839bd | 2841 | |
95ea3627 ID |
2842 | /* |
2843 | * Allocate eeprom data. | |
2844 | */ | |
2845 | retval = rt61pci_validate_eeprom(rt2x00dev); | |
2846 | if (retval) | |
2847 | return retval; | |
2848 | ||
2849 | retval = rt61pci_init_eeprom(rt2x00dev); | |
2850 | if (retval) | |
2851 | return retval; | |
2852 | ||
a396e100 GW |
2853 | /* |
2854 | * Enable rfkill polling by setting GPIO direction of the | |
2855 | * rfkill switch GPIO pin correctly. | |
2856 | */ | |
1d6205d0 | 2857 | rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); |
99bdf51a | 2858 | rt2x00_set_field32(®, MAC_CSR13_DIR5, 1); |
1d6205d0 | 2859 | rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); |
a396e100 | 2860 | |
95ea3627 ID |
2861 | /* |
2862 | * Initialize hw specifications. | |
2863 | */ | |
8c5e7a5f ID |
2864 | retval = rt61pci_probe_hw_mode(rt2x00dev); |
2865 | if (retval) | |
2866 | return retval; | |
95ea3627 | 2867 | |
1afcfd54 IP |
2868 | /* |
2869 | * This device has multiple filters for control frames, | |
2870 | * but has no a separate filter for PS Poll frames. | |
2871 | */ | |
7dab73b3 | 2872 | __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); |
1afcfd54 | 2873 | |
95ea3627 | 2874 | /* |
c4da0048 | 2875 | * This device requires firmware and DMA mapped skbs. |
95ea3627 | 2876 | */ |
7dab73b3 ID |
2877 | __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); |
2878 | __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); | |
008c4482 | 2879 | if (!modparam_nohwcrypt) |
7dab73b3 ID |
2880 | __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); |
2881 | __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); | |
95ea3627 ID |
2882 | |
2883 | /* | |
2884 | * Set the rssi offset. | |
2885 | */ | |
2886 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
2887 | ||
2888 | return 0; | |
2889 | } | |
2890 | ||
2891 | /* | |
2892 | * IEEE80211 stack callback functions. | |
2893 | */ | |
8a3a3c85 EP |
2894 | static int rt61pci_conf_tx(struct ieee80211_hw *hw, |
2895 | struct ieee80211_vif *vif, u16 queue_idx, | |
2af0a570 ID |
2896 | const struct ieee80211_tx_queue_params *params) |
2897 | { | |
2898 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2899 | struct data_queue *queue; | |
2900 | struct rt2x00_field32 field; | |
2901 | int retval; | |
2902 | u32 reg; | |
5e790023 | 2903 | u32 offset; |
2af0a570 ID |
2904 | |
2905 | /* | |
2906 | * First pass the configuration through rt2x00lib, that will | |
2907 | * update the queue settings and validate the input. After that | |
2908 | * we are free to update the registers based on the value | |
2909 | * in the queue parameter. | |
2910 | */ | |
8a3a3c85 | 2911 | retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); |
2af0a570 ID |
2912 | if (retval) |
2913 | return retval; | |
2914 | ||
5e790023 ID |
2915 | /* |
2916 | * We only need to perform additional register initialization | |
b34e620f | 2917 | * for WMM queues. |
5e790023 ID |
2918 | */ |
2919 | if (queue_idx >= 4) | |
2920 | return 0; | |
2921 | ||
11f818e0 | 2922 | queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
2af0a570 ID |
2923 | |
2924 | /* Update WMM TXOP register */ | |
5e790023 ID |
2925 | offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); |
2926 | field.bit_offset = (queue_idx & 1) * 16; | |
2927 | field.bit_mask = 0xffff << field.bit_offset; | |
2928 | ||
1d6205d0 | 2929 | rt2x00mmio_register_read(rt2x00dev, offset, ®); |
5e790023 | 2930 | rt2x00_set_field32(®, field, queue->txop); |
1d6205d0 | 2931 | rt2x00mmio_register_write(rt2x00dev, offset, reg); |
2af0a570 ID |
2932 | |
2933 | /* Update WMM registers */ | |
2934 | field.bit_offset = queue_idx * 4; | |
2935 | field.bit_mask = 0xf << field.bit_offset; | |
2936 | ||
1d6205d0 | 2937 | rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, ®); |
2af0a570 | 2938 | rt2x00_set_field32(®, field, queue->aifs); |
1d6205d0 | 2939 | rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); |
2af0a570 | 2940 | |
1d6205d0 | 2941 | rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, ®); |
2af0a570 | 2942 | rt2x00_set_field32(®, field, queue->cw_min); |
1d6205d0 | 2943 | rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); |
2af0a570 | 2944 | |
1d6205d0 | 2945 | rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, ®); |
2af0a570 | 2946 | rt2x00_set_field32(®, field, queue->cw_max); |
1d6205d0 | 2947 | rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); |
2af0a570 ID |
2948 | |
2949 | return 0; | |
2950 | } | |
2951 | ||
37a41b4a | 2952 | static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
95ea3627 ID |
2953 | { |
2954 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2955 | u64 tsf; | |
2956 | u32 reg; | |
2957 | ||
1d6205d0 | 2958 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, ®); |
95ea3627 | 2959 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; |
1d6205d0 | 2960 | rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, ®); |
95ea3627 ID |
2961 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); |
2962 | ||
2963 | return tsf; | |
2964 | } | |
2965 | ||
95ea3627 ID |
2966 | static const struct ieee80211_ops rt61pci_mac80211_ops = { |
2967 | .tx = rt2x00mac_tx, | |
4150c572 JB |
2968 | .start = rt2x00mac_start, |
2969 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
2970 | .add_interface = rt2x00mac_add_interface, |
2971 | .remove_interface = rt2x00mac_remove_interface, | |
2972 | .config = rt2x00mac_config, | |
3a643d24 | 2973 | .configure_filter = rt2x00mac_configure_filter, |
61e754f4 | 2974 | .set_key = rt2x00mac_set_key, |
d8147f9d ID |
2975 | .sw_scan_start = rt2x00mac_sw_scan_start, |
2976 | .sw_scan_complete = rt2x00mac_sw_scan_complete, | |
95ea3627 | 2977 | .get_stats = rt2x00mac_get_stats, |
471b3efd | 2978 | .bss_info_changed = rt2x00mac_bss_info_changed, |
2af0a570 | 2979 | .conf_tx = rt61pci_conf_tx, |
95ea3627 | 2980 | .get_tsf = rt61pci_get_tsf, |
e47a5cdd | 2981 | .rfkill_poll = rt2x00mac_rfkill_poll, |
f44df18c | 2982 | .flush = rt2x00mac_flush, |
0ed7b3c0 ID |
2983 | .set_antenna = rt2x00mac_set_antenna, |
2984 | .get_antenna = rt2x00mac_get_antenna, | |
e7dee444 | 2985 | .get_ringparam = rt2x00mac_get_ringparam, |
5f0dd296 | 2986 | .tx_frames_pending = rt2x00mac_tx_frames_pending, |
95ea3627 ID |
2987 | }; |
2988 | ||
2989 | static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { | |
2990 | .irq_handler = rt61pci_interrupt, | |
5846a550 HS |
2991 | .txstatus_tasklet = rt61pci_txstatus_tasklet, |
2992 | .tbtt_tasklet = rt61pci_tbtt_tasklet, | |
2993 | .rxdone_tasklet = rt61pci_rxdone_tasklet, | |
2994 | .autowake_tasklet = rt61pci_autowake_tasklet, | |
95ea3627 ID |
2995 | .probe_hw = rt61pci_probe_hw, |
2996 | .get_firmware_name = rt61pci_get_firmware_name, | |
0cbe0064 | 2997 | .check_firmware = rt61pci_check_firmware, |
95ea3627 | 2998 | .load_firmware = rt61pci_load_firmware, |
1d6205d0 GJ |
2999 | .initialize = rt2x00mmio_initialize, |
3000 | .uninitialize = rt2x00mmio_uninitialize, | |
798b7adb ID |
3001 | .get_entry_state = rt61pci_get_entry_state, |
3002 | .clear_entry = rt61pci_clear_entry, | |
95ea3627 | 3003 | .set_device_state = rt61pci_set_device_state, |
95ea3627 | 3004 | .rfkill_poll = rt61pci_rfkill_poll, |
95ea3627 ID |
3005 | .link_stats = rt61pci_link_stats, |
3006 | .reset_tuner = rt61pci_reset_tuner, | |
3007 | .link_tuner = rt61pci_link_tuner, | |
dbba306f ID |
3008 | .start_queue = rt61pci_start_queue, |
3009 | .kick_queue = rt61pci_kick_queue, | |
3010 | .stop_queue = rt61pci_stop_queue, | |
1d6205d0 | 3011 | .flush_queue = rt2x00mmio_flush_queue, |
95ea3627 | 3012 | .write_tx_desc = rt61pci_write_tx_desc, |
bd88a781 | 3013 | .write_beacon = rt61pci_write_beacon, |
69cf36a4 | 3014 | .clear_beacon = rt61pci_clear_beacon, |
95ea3627 | 3015 | .fill_rxdone = rt61pci_fill_rxdone, |
61e754f4 ID |
3016 | .config_shared_key = rt61pci_config_shared_key, |
3017 | .config_pairwise_key = rt61pci_config_pairwise_key, | |
3a643d24 | 3018 | .config_filter = rt61pci_config_filter, |
6bb40dd1 | 3019 | .config_intf = rt61pci_config_intf, |
72810379 | 3020 | .config_erp = rt61pci_config_erp, |
e4ea1c40 | 3021 | .config_ant = rt61pci_config_ant, |
95ea3627 ID |
3022 | .config = rt61pci_config, |
3023 | }; | |
3024 | ||
7106d97b GJ |
3025 | static void rt61pci_queue_init(struct data_queue *queue) |
3026 | { | |
3027 | switch (queue->qid) { | |
3028 | case QID_RX: | |
3029 | queue->limit = 32; | |
3030 | queue->data_size = DATA_FRAME_SIZE; | |
3031 | queue->desc_size = RXD_DESC_SIZE; | |
3032 | queue->priv_size = sizeof(struct queue_entry_priv_mmio); | |
3033 | break; | |
181d6902 | 3034 | |
7106d97b GJ |
3035 | case QID_AC_VO: |
3036 | case QID_AC_VI: | |
3037 | case QID_AC_BE: | |
3038 | case QID_AC_BK: | |
3039 | queue->limit = 32; | |
3040 | queue->data_size = DATA_FRAME_SIZE; | |
3041 | queue->desc_size = TXD_DESC_SIZE; | |
3042 | queue->priv_size = sizeof(struct queue_entry_priv_mmio); | |
3043 | break; | |
181d6902 | 3044 | |
7106d97b GJ |
3045 | case QID_BEACON: |
3046 | queue->limit = 4; | |
3047 | queue->data_size = 0; /* No DMA required for beacons */ | |
3048 | queue->desc_size = TXINFO_SIZE; | |
3049 | queue->priv_size = sizeof(struct queue_entry_priv_mmio); | |
3050 | break; | |
3051 | ||
3052 | case QID_ATIM: | |
3053 | /* fallthrough */ | |
3054 | default: | |
3055 | BUG(); | |
3056 | break; | |
3057 | } | |
3058 | } | |
181d6902 | 3059 | |
95ea3627 | 3060 | static const struct rt2x00_ops rt61pci_ops = { |
04d0362e | 3061 | .name = KBUILD_MODNAME, |
04d0362e GW |
3062 | .max_ap_intf = 4, |
3063 | .eeprom_size = EEPROM_SIZE, | |
3064 | .rf_size = RF_SIZE, | |
3065 | .tx_queues = NUM_TX_QUEUES, | |
7106d97b | 3066 | .queue_init = rt61pci_queue_init, |
04d0362e GW |
3067 | .lib = &rt61pci_rt2x00_ops, |
3068 | .hw = &rt61pci_mac80211_ops, | |
95ea3627 | 3069 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
04d0362e | 3070 | .debugfs = &rt61pci_rt2x00debug, |
95ea3627 ID |
3071 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
3072 | }; | |
3073 | ||
3074 | /* | |
3075 | * RT61pci module information. | |
3076 | */ | |
9baa3c34 | 3077 | static const struct pci_device_id rt61pci_device_table[] = { |
95ea3627 | 3078 | /* RT2561s */ |
e01ae27f | 3079 | { PCI_DEVICE(0x1814, 0x0301) }, |
95ea3627 | 3080 | /* RT2561 v2 */ |
e01ae27f | 3081 | { PCI_DEVICE(0x1814, 0x0302) }, |
95ea3627 | 3082 | /* RT2661 */ |
e01ae27f | 3083 | { PCI_DEVICE(0x1814, 0x0401) }, |
95ea3627 ID |
3084 | { 0, } |
3085 | }; | |
3086 | ||
3087 | MODULE_AUTHOR(DRV_PROJECT); | |
3088 | MODULE_VERSION(DRV_VERSION); | |
3089 | MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver."); | |
3090 | MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 " | |
3091 | "PCI & PCMCIA chipset based cards"); | |
3092 | MODULE_DEVICE_TABLE(pci, rt61pci_device_table); | |
3093 | MODULE_FIRMWARE(FIRMWARE_RT2561); | |
3094 | MODULE_FIRMWARE(FIRMWARE_RT2561s); | |
3095 | MODULE_FIRMWARE(FIRMWARE_RT2661); | |
3096 | MODULE_LICENSE("GPL"); | |
3097 | ||
e01ae27f GW |
3098 | static int rt61pci_probe(struct pci_dev *pci_dev, |
3099 | const struct pci_device_id *id) | |
3100 | { | |
3101 | return rt2x00pci_probe(pci_dev, &rt61pci_ops); | |
3102 | } | |
3103 | ||
95ea3627 | 3104 | static struct pci_driver rt61pci_driver = { |
2360157c | 3105 | .name = KBUILD_MODNAME, |
95ea3627 | 3106 | .id_table = rt61pci_device_table, |
e01ae27f | 3107 | .probe = rt61pci_probe, |
69202359 | 3108 | .remove = rt2x00pci_remove, |
95ea3627 ID |
3109 | .suspend = rt2x00pci_suspend, |
3110 | .resume = rt2x00pci_resume, | |
3111 | }; | |
3112 | ||
5b0a3b7e | 3113 | module_pci_driver(rt61pci_driver); |