projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mac80211: separate encoding/bandwidth from flags
[linux-2.6-block.git] / drivers / net / wireless / ralink / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
a05b8c58 27 along with this program; if not, see <http://www.gnu.org/licenses/>.
89297425
BZ		 28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
f31c9a8c 35#include <linux/crc-ccitt.h>
89297425
BZ		 36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
41977e86
RY		 62#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
64 (__reg))
89297425
BZ		 65#define WAIT_FOR_RF(__dev, __reg) \
66 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
67#define WAIT_FOR_MCU(__dev, __reg) \
68 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
69 H2M_MAILBOX_CSR_OWNER, (__reg))
70
baff8006
HS		 71static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
72{
73 /* check for rt2872 on SoC */
74 if (!rt2x00_is_soc(rt2x00dev) ||
75 !rt2x00_rt(rt2x00dev, RT2872))
76 return false;
77
78 /* we know for sure that these rf chipsets are used on rt305x boards */
79 if (rt2x00_rf(rt2x00dev, RF3020) ||
80 rt2x00_rf(rt2x00dev, RF3021) ||
81 rt2x00_rf(rt2x00dev, RF3022))
82 return true;
83
ec9c4989 84 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 85 return false;
86}
87
fcf51541
BZ		 88static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
89 const unsigned int word, const u8 value)
89297425
BZ		 90{
91 u32 reg;
92
93 mutex_lock(&rt2x00dev->csr_mutex);
94
95 /*
96 * Wait until the BBP becomes available, afterwards we
97 * can safely write the new data into the register.
98 */
99 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
100 reg = 0;
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 105 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 106
107 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
108 }
109
110 mutex_unlock(&rt2x00dev->csr_mutex);
111}
89297425 112
fcf51541
BZ		 113static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
114 const unsigned int word, u8 *value)
89297425
BZ		 115{
116 u32 reg;
117
118 mutex_lock(&rt2x00dev->csr_mutex);
119
120 /*
121 * Wait until the BBP becomes available, afterwards we
122 * can safely write the read request into the register.
123 * After the data has been written, we wait until hardware
124 * returns the correct value, if at any time the register
125 * doesn't become available in time, reg will be 0xffffffff
126 * which means we return 0xff to the caller.
127 */
128 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
129 reg = 0;
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 133 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 134
135 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
136
137 WAIT_FOR_BBP(rt2x00dev, &reg);
138 }
139
140 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
141
142 mutex_unlock(&rt2x00dev->csr_mutex);
143}
89297425 144
fcf51541
BZ		 145static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
146 const unsigned int word, const u8 value)
89297425
BZ		 147{
148 u32 reg;
149
150 mutex_lock(&rt2x00dev->csr_mutex);
151
152 /*
153 * Wait until the RFCSR becomes available, afterwards we
154 * can safely write the new data into the register.
155 */
41977e86
RY		 156 switch (rt2x00dev->chip.rt) {
157 case RT6352:
158 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
159 reg = 0;
160 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
161 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
162 word);
163 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
164 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
165
166 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
167 }
168 break;
89297425 169
41977e86
RY		 170 default:
171 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
172 reg = 0;
173 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
174 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
175 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
176 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
177
178 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
179 }
180 break;
89297425
BZ		 181 }
182
183 mutex_unlock(&rt2x00dev->csr_mutex);
184}
89297425 185
41977e86
RY		 186static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
187 const unsigned int reg, const u8 value)
188{
189 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
190}
191
192static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
193 const unsigned int reg, const u8 value)
194{
195 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
196 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
197}
198
199static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
200 const unsigned int reg, const u8 value)
201{
202 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
203 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
204}
205
fcf51541
BZ		 206static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
207 const unsigned int word, u8 *value)
89297425
BZ		 208{
209 u32 reg;
210
211 mutex_lock(&rt2x00dev->csr_mutex);
212
213 /*
214 * Wait until the RFCSR becomes available, afterwards we
215 * can safely write the read request into the register.
216 * After the data has been written, we wait until hardware
217 * returns the correct value, if at any time the register
218 * doesn't become available in time, reg will be 0xffffffff
219 * which means we return 0xff to the caller.
220 */
41977e86
RY		 221 switch (rt2x00dev->chip.rt) {
222 case RT6352:
223 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
224 reg = 0;
225 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
226 word);
227 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
228 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
89297425 229
41977e86 230 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
89297425 231
41977e86
RY		 232 WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
233 }
89297425 234
41977e86
RY		 235 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
236 break;
237
238 default:
239 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
240 reg = 0;
241 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
242 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
243 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
244
245 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
246
247 WAIT_FOR_RFCSR(rt2x00dev, &reg);
248 }
249
250 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
251 break;
252 }
89297425
BZ		 253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
89297425 256
41977e86
RY		 257static void rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
258 const unsigned int reg, u8 *value)
259{
260 rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)), value);
261}
262
fcf51541
BZ		 263static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
264 const unsigned int word, const u32 value)
89297425
BZ		 265{
266 u32 reg;
267
268 mutex_lock(&rt2x00dev->csr_mutex);
269
270 /*
271 * Wait until the RF becomes available, afterwards we
272 * can safely write the new data into the register.
273 */
274 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
275 reg = 0;
276 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
277 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
278 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
279 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
280
281 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
282 rt2x00_rf_write(rt2x00dev, word, value);
283 }
284
285 mutex_unlock(&rt2x00dev->csr_mutex);
286}
89297425 287
379448fe
GJ		 288static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
289 [EEPROM_CHIP_ID] = 0x0000,
290 [EEPROM_VERSION] = 0x0001,
291 [EEPROM_MAC_ADDR_0] = 0x0002,
292 [EEPROM_MAC_ADDR_1] = 0x0003,
293 [EEPROM_MAC_ADDR_2] = 0x0004,
294 [EEPROM_NIC_CONF0] = 0x001a,
295 [EEPROM_NIC_CONF1] = 0x001b,
296 [EEPROM_FREQ] = 0x001d,
297 [EEPROM_LED_AG_CONF] = 0x001e,
298 [EEPROM_LED_ACT_CONF] = 0x001f,
299 [EEPROM_LED_POLARITY] = 0x0020,
300 [EEPROM_NIC_CONF2] = 0x0021,
301 [EEPROM_LNA] = 0x0022,
302 [EEPROM_RSSI_BG] = 0x0023,
303 [EEPROM_RSSI_BG2] = 0x0024,
304 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
305 [EEPROM_RSSI_A] = 0x0025,
306 [EEPROM_RSSI_A2] = 0x0026,
307 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
308 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
309 [EEPROM_TXPOWER_DELTA] = 0x0028,
310 [EEPROM_TXPOWER_BG1] = 0x0029,
311 [EEPROM_TXPOWER_BG2] = 0x0030,
312 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
313 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
314 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
315 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
316 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
317 [EEPROM_TXPOWER_A1] = 0x003c,
318 [EEPROM_TXPOWER_A2] = 0x0053,
41977e86 319 [EEPROM_TXPOWER_INIT] = 0x0068,
379448fe
GJ		 320 [EEPROM_TSSI_BOUND_A1] = 0x006a,
321 [EEPROM_TSSI_BOUND_A2] = 0x006b,
322 [EEPROM_TSSI_BOUND_A3] = 0x006c,
323 [EEPROM_TSSI_BOUND_A4] = 0x006d,
324 [EEPROM_TSSI_BOUND_A5] = 0x006e,
325 [EEPROM_TXPOWER_BYRATE] = 0x006f,
326 [EEPROM_BBP_START] = 0x0078,
327};
328
fa31d157
GJ		 329static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
330 [EEPROM_CHIP_ID] = 0x0000,
331 [EEPROM_VERSION] = 0x0001,
332 [EEPROM_MAC_ADDR_0] = 0x0002,
333 [EEPROM_MAC_ADDR_1] = 0x0003,
334 [EEPROM_MAC_ADDR_2] = 0x0004,
335 [EEPROM_NIC_CONF0] = 0x001a,
336 [EEPROM_NIC_CONF1] = 0x001b,
337 [EEPROM_NIC_CONF2] = 0x001c,
338 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
339 [EEPROM_FREQ] = 0x0022,
340 [EEPROM_LED_AG_CONF] = 0x0023,
341 [EEPROM_LED_ACT_CONF] = 0x0024,
342 [EEPROM_LED_POLARITY] = 0x0025,
343 [EEPROM_LNA] = 0x0026,
344 [EEPROM_EXT_LNA2] = 0x0027,
345 [EEPROM_RSSI_BG] = 0x0028,
fa31d157 346 [EEPROM_RSSI_BG2] = 0x0029,
fa31d157
GJ		 347 [EEPROM_RSSI_A] = 0x002a,
348 [EEPROM_RSSI_A2] = 0x002b,
fa31d157
GJ		 349 [EEPROM_TXPOWER_BG1] = 0x0030,
350 [EEPROM_TXPOWER_BG2] = 0x0037,
351 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
352 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
353 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
354 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
355 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
356 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
357 [EEPROM_TXPOWER_A1] = 0x004b,
358 [EEPROM_TXPOWER_A2] = 0x0065,
359 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
360 [EEPROM_TSSI_BOUND_A1] = 0x009a,
361 [EEPROM_TSSI_BOUND_A2] = 0x009b,
362 [EEPROM_TSSI_BOUND_A3] = 0x009c,
363 [EEPROM_TSSI_BOUND_A4] = 0x009d,
364 [EEPROM_TSSI_BOUND_A5] = 0x009e,
365 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
366};
367
379448fe
GJ		 368static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
369 const enum rt2800_eeprom_word word)
370{
371 const unsigned int *map;
372 unsigned int index;
373
374 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
375 "%s: invalid EEPROM word %d\n",
376 wiphy_name(rt2x00dev->hw->wiphy), word))
377 return 0;
378
fa31d157
GJ		 379 if (rt2x00_rt(rt2x00dev, RT3593))
380 map = rt2800_eeprom_map_ext;
381 else
382 map = rt2800_eeprom_map;
383
379448fe
GJ		 384 index = map[word];
385
386 /* Index 0 is valid only for EEPROM_CHIP_ID.
387 * Otherwise it means that the offset of the
388 * given word is not initialized in the map,
389 * or that the field is not usable on the
390 * actual chipset.
391 */
392 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
393 "%s: invalid access of EEPROM word %d\n",
394 wiphy_name(rt2x00dev->hw->wiphy), word);
395
396 return index;
397}
398
3e38d3da
GJ		 399static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
400 const enum rt2800_eeprom_word word)
401{
379448fe
GJ		 402 unsigned int index;
403
404 index = rt2800_eeprom_word_index(rt2x00dev, word);
405 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 406}
407
408static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
409 const enum rt2800_eeprom_word word, u16 *data)
410{
379448fe
GJ		 411 unsigned int index;
412
413 index = rt2800_eeprom_word_index(rt2x00dev, word);
414 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 415}
416
417static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
418 const enum rt2800_eeprom_word word, u16 data)
419{
379448fe
GJ		 420 unsigned int index;
421
422 index = rt2800_eeprom_word_index(rt2x00dev, word);
423 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 424}
425
022138ca
GJ		 426static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
427 const enum rt2800_eeprom_word array,
428 unsigned int offset,
429 u16 *data)
430{
379448fe
GJ		 431 unsigned int index;
432
433 index = rt2800_eeprom_word_index(rt2x00dev, array);
434 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 435}
436
16ebd608
WH		 437static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
438{
439 u32 reg;
440 int i, count;
441
442 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
16ebd608
WH		 443 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
444 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
445 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
446 rt2x00_set_field32(&reg, WLAN_EN, 1);
447 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
448
449 udelay(REGISTER_BUSY_DELAY);
450
451 count = 0;
452 do {
453 /*
454 * Check PLL_LD & XTAL_RDY.
455 */
456 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
457 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
458 if (rt2x00_get_field32(reg, PLL_LD) &&
459 rt2x00_get_field32(reg, XTAL_RDY))
460 break;
461 udelay(REGISTER_BUSY_DELAY);
462 }
463
464 if (i >= REGISTER_BUSY_COUNT) {
465
466 if (count >= 10)
467 return -EIO;
468
469 rt2800_register_write(rt2x00dev, 0x58, 0x018);
470 udelay(REGISTER_BUSY_DELAY);
471 rt2800_register_write(rt2x00dev, 0x58, 0x418);
472 udelay(REGISTER_BUSY_DELAY);
473 rt2800_register_write(rt2x00dev, 0x58, 0x618);
474 udelay(REGISTER_BUSY_DELAY);
475 count++;
476 } else {
477 count = 0;
478 }
479
480 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
481 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
482 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
483 rt2x00_set_field32(&reg, WLAN_RESET, 1);
484 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
485 udelay(10);
486 rt2x00_set_field32(&reg, WLAN_RESET, 0);
487 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
488 udelay(10);
489 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
490 } while (count != 0);
491
492 return 0;
493}
494
89297425
BZ		 495void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
496 const u8 command, const u8 token,
497 const u8 arg0, const u8 arg1)
498{
499 u32 reg;
500
ee303e54 501 /*
cea90e55 502 * SOC devices don't support MCU requests.
ee303e54 503 */
cea90e55 504 if (rt2x00_is_soc(rt2x00dev))
ee303e54 505 return;
89297425
BZ		 506
507 mutex_lock(&rt2x00dev->csr_mutex);
508
509 /*
510 * Wait until the MCU becomes available, afterwards we
511 * can safely write the new data into the register.
512 */
513 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
514 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
515 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
516 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
517 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
518 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
519
520 reg = 0;
521 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
522 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
523 }
524
525 mutex_unlock(&rt2x00dev->csr_mutex);
526}
527EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 528
5ffddc49
ID		 529int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
530{
531 unsigned int i = 0;
532 u32 reg;
533
534 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
535 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
536 if (reg && reg != ~0)
537 return 0;
538 msleep(1);
539 }
540
ec9c4989 541 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 542 return -EBUSY;
543}
544EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
545
67a4c1e2
GW		 546int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
547{
548 unsigned int i;
549 u32 reg;
550
08e53100
HS		 551 /*
552 * Some devices are really slow to respond here. Wait a whole second
553 * before timing out.
554 */
67a4c1e2
GW		 555 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
556 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
557 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
558 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
559 return 0;
560
08e53100 561 msleep(10);
67a4c1e2
GW		 562 }
563
ec9c4989 564 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 565 return -EACCES;
566}
567EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
568
f7b395e9
JK		 569void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
570{
571 u32 reg;
572
573 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
574 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
575 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
576 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
577 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
578 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
579 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
580}
581EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
582
ae1b1c5d
GJ		 583void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
584 unsigned short *txwi_size,
585 unsigned short *rxwi_size)
586{
587 switch (rt2x00dev->chip.rt) {
588 case RT3593:
589 *txwi_size = TXWI_DESC_SIZE_4WORDS;
590 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
591 break;
592
593 case RT5592:
41977e86 594 case RT6352:
ae1b1c5d
GJ		 595 *txwi_size = TXWI_DESC_SIZE_5WORDS;
596 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
597 break;
598
599 default:
600 *txwi_size = TXWI_DESC_SIZE_4WORDS;
601 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
602 break;
603 }
604}
605EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
606
f31c9a8c
ID		 607static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
608{
609 u16 fw_crc;
610 u16 crc;
611
612 /*
613 * The last 2 bytes in the firmware array are the crc checksum itself,
614 * this means that we should never pass those 2 bytes to the crc
615 * algorithm.
616 */
617 fw_crc = (data[len - 2] << 8 | data[len - 1]);
618
619 /*
620 * Use the crc ccitt algorithm.
621 * This will return the same value as the legacy driver which
622 * used bit ordering reversion on the both the firmware bytes
623 * before input input as well as on the final output.
624 * Obviously using crc ccitt directly is much more efficient.
625 */
626 crc = crc_ccitt(~0, data, len - 2);
627
628 /*
629 * There is a small difference between the crc-itu-t + bitrev and
630 * the crc-ccitt crc calculation. In the latter method the 2 bytes
631 * will be swapped, use swab16 to convert the crc to the correct
632 * value.
633 */
634 crc = swab16(crc);
635
636 return fw_crc == crc;
637}
638
639int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
640 const u8 *data, const size_t len)
641{
642 size_t offset = 0;
643 size_t fw_len;
644 bool multiple;
645
646 /*
647 * PCI(e) & SOC devices require firmware with a length
648 * of 8kb. USB devices require firmware files with a length
649 * of 4kb. Certain USB chipsets however require different firmware,
650 * which Ralink only provides attached to the original firmware
651 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 652 * which is a multiple of 4kb. The firmware for rt3290 chip also
653 * have a length which is a multiple of 4kb.
f31c9a8c 654 */
a89534ed 655 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 656 fw_len = 4096;
a89534ed 657 else
f31c9a8c 658 fw_len = 8192;
f31c9a8c 659
a89534ed 660 multiple = true;
f31c9a8c
ID		 661 /*
662 * Validate the firmware length
663 */
664 if (len != fw_len && (!multiple || (len % fw_len) != 0))
665 return FW_BAD_LENGTH;
666
667 /*
668 * Check if the chipset requires one of the upper parts
669 * of the firmware.
670 */
671 if (rt2x00_is_usb(rt2x00dev) &&
672 !rt2x00_rt(rt2x00dev, RT2860) &&
673 !rt2x00_rt(rt2x00dev, RT2872) &&
674 !rt2x00_rt(rt2x00dev, RT3070) &&
675 ((len / fw_len) == 1))
676 return FW_BAD_VERSION;
677
678 /*
679 * 8kb firmware files must be checked as if it were
680 * 2 separate firmware files.
681 */
682 while (offset < len) {
683 if (!rt2800_check_firmware_crc(data + offset, fw_len))
684 return FW_BAD_CRC;
685
686 offset += fw_len;
687 }
688
689 return FW_OK;
690}
691EXPORT_SYMBOL_GPL(rt2800_check_firmware);
692
693int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
694 const u8 *data, const size_t len)
695{
696 unsigned int i;
697 u32 reg;
16ebd608
WH		 698 int retval;
699
700 if (rt2x00_rt(rt2x00dev, RT3290)) {
701 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
702 if (retval)
703 return -EBUSY;
704 }
f31c9a8c
ID		 705
706 /*
b9eca242
ID		 707 * If driver doesn't wake up firmware here,
708 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 709 */
b9eca242 710 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 711
f31c9a8c
ID		 712 /*
713 * Wait for stable hardware.
714 */
5ffddc49 715 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 716 return -EBUSY;
f31c9a8c 717
adde5882 718 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 719 if (rt2x00_rt(rt2x00dev, RT3290) ||
720 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 721 rt2x00_rt(rt2x00dev, RT5390) ||
722 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 723 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
724 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
725 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
726 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
727 }
f31c9a8c 728 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 729 }
f31c9a8c 730
b7e1d225
JK		 731 rt2800_disable_wpdma(rt2x00dev);
732
f31c9a8c
ID		 733 /*
734 * Write firmware to the device.
735 */
736 rt2800_drv_write_firmware(rt2x00dev, data, len);
737
738 /*
739 * Wait for device to stabilize.
740 */
741 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
742 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
743 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
744 break;
745 msleep(1);
746 }
747
748 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 749 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 750 return -EBUSY;
751 }
752
4ed1dd2a
SG		 753 /*
754 * Disable DMA, will be reenabled later when enabling
755 * the radio.
756 */
f7b395e9 757 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 758
f31c9a8c
ID		 759 /*
760 * Initialize firmware.
761 */
762 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
763 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 764 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 765 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 766 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
767 }
f31c9a8c
ID		 768 msleep(1);
769
770 return 0;
771}
772EXPORT_SYMBOL_GPL(rt2800_load_firmware);
773
0c5879bc
ID		 774void rt2800_write_tx_data(struct queue_entry *entry,
775 struct txentry_desc *txdesc)
59679b91 776{
0c5879bc 777 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 778 u32 word;
557985ae 779 int i;
59679b91
GW		 780
781 /*
782 * Initialize TX Info descriptor
783 */
784 rt2x00_desc_read(txwi, 0, &word);
785 rt2x00_set_field32(&word, TXWI_W0_FRAG,
786 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 787 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
788 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 789 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
790 rt2x00_set_field32(&word, TXWI_W0_TS,
791 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
792 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
793 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 794 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
795 txdesc->u.ht.mpdu_density);
796 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
797 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 798 rt2x00_set_field32(&word, TXWI_W0_BW,
799 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
800 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
801 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 802 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 803 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
804 rt2x00_desc_write(txwi, 0, word);
805
806 rt2x00_desc_read(txwi, 1, &word);
807 rt2x00_set_field32(&word, TXWI_W1_ACK,
808 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
809 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
810 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 811 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 812 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
813 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 814 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 815 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
816 txdesc->length);
2b23cdaa 817 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 818 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 819 rt2x00_desc_write(txwi, 1, word);
820
821 /*
557985ae
SG		 822 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
823 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 824 * When TXD_W3_WIV is set to 1 it will use the IV data
825 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
826 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 827 *
828 * Nulify all remaining words as well, we don't know how to program them.
59679b91 829 */
557985ae
SG		 830 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
831 _rt2x00_desc_write(txwi, i, 0);
59679b91 832}
0c5879bc 833EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 834
ff6133be 835static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 836{
7fc41755
LT		 837 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
838 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
839 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 840 u16 eeprom;
841 u8 offset0;
842 u8 offset1;
843 u8 offset2;
844
57fbcce3 845 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 846 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 847 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
848 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 849 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 850 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
851 } else {
3e38d3da 852 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 853 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
854 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 855 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 856 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
857 }
858
859 /*
860 * Convert the value from the descriptor into the RSSI value
861 * If the value in the descriptor is 0, it is considered invalid
862 * and the default (extremely low) rssi value is assumed
863 */
864 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
865 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
866 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
867
868 /*
869 * mac80211 only accepts a single RSSI value. Calculating the
870 * average doesn't deliver a fair answer either since -60:-60 would
871 * be considered equally good as -50:-70 while the second is the one
872 * which gives less energy...
873 */
874 rssi0 = max(rssi0, rssi1);
7fc41755 875 return (int)max(rssi0, rssi2);
74861922
ID		 876}
877
878void rt2800_process_rxwi(struct queue_entry *entry,
879 struct rxdone_entry_desc *rxdesc)
880{
881 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 882 u32 word;
883
884 rt2x00_desc_read(rxwi, 0, &word);
885
886 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
887 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
888
889 rt2x00_desc_read(rxwi, 1, &word);
890
891 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
7fdd69c5 892 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2de64dd2
GW		 893
894 if (rt2x00_get_field32(word, RXWI_W1_BW))
da6a4352 895 rxdesc->bw = RATE_INFO_BW_40;
2de64dd2
GW		 896
897 /*
898 * Detect RX rate, always use MCS as signal type.
899 */
900 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
901 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
902 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
903
904 /*
905 * Mask of 0x8 bit to remove the short preamble flag.
906 */
907 if (rxdesc->rate_mode == RATE_MODE_CCK)
908 rxdesc->signal &= ~0x8;
909
910 rt2x00_desc_read(rxwi, 2, &word);
911
74861922
ID		 912 /*
913 * Convert descriptor AGC value to RSSI value.
914 */
915 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 916 /*
917 * Remove RXWI descriptor from start of the buffer.
918 */
919 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 920}
921EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
922
9d7a7a4d
SG		 923static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
924 u32 status, enum nl80211_band band)
925{
926 u8 flags = 0;
927 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
928
929 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
930 case RATE_MODE_HT_GREENFIELD:
931 flags |= IEEE80211_TX_RC_GREEN_FIELD;
932 /* fall through */
933 case RATE_MODE_HT_MIX:
934 flags |= IEEE80211_TX_RC_MCS;
935 break;
936 case RATE_MODE_OFDM:
937 if (band == NL80211_BAND_2GHZ)
938 idx += 4;
939 break;
940 case RATE_MODE_CCK:
941 if (idx >= 8)
942 idx -= 8;
943 break;
944 }
945
946 if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
947 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
948
949 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
950 flags |= IEEE80211_TX_RC_SHORT_GI;
951
952 skbdesc->tx_rate_idx = idx;
953 skbdesc->tx_rate_flags = flags;
954}
955
293dff78
SG		 956void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
957 bool match)
14433331
HS		 958{
959 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a13d985f 960 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
b34793ee 961 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 962 struct txdone_entry_desc txdesc;
963 u32 word;
964 u16 mcs, real_mcs;
293dff78 965 int aggr, ampdu, wcid, ack_req;
14433331
HS		 966
967 /*
968 * Obtain the status about this packet.
969 */
970 txdesc.flags = 0;
14433331 971 rt2x00_desc_read(txwi, 0, &word);
b34793ee 972
14433331 973 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 974 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
975
14433331 976 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee 977 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
a13d985f 978 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
293dff78 979 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
b34793ee
HS		 980
981 /*
982 * If a frame was meant to be sent as a single non-aggregated MPDU
983 * but ended up in an aggregate the used tx rate doesn't correlate
984 * with the one specified in the TXWI as the whole aggregate is sent
985 * with the same rate.
986 *
987 * For example: two frames are sent to rt2x00, the first one sets
988 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
989 * and requests MCS15. If the hw aggregates both frames into one
990 * AMDPU the tx status for both frames will contain MCS7 although
991 * the frame was sent successfully.
992 *
993 * Hence, replace the requested rate with the real tx rate to not
994 * confuse the rate control algortihm by providing clearly wrong
995 * data.
293dff78
SG		 996 *
997 * FIXME: if we do not find matching entry, we tell that frame was
998 * posted without any retries. We need to find a way to fix that
999 * and provide retry count.
1000 */
1001 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
9d7a7a4d 1002 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
b34793ee
HS		 1003 mcs = real_mcs;
1004 }
14433331 1005
f16d2db7
HS		 1006 if (aggr == 1 || ampdu == 1)
1007 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1008
293dff78
SG		 1009 if (!ack_req)
1010 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1011
14433331
HS		 1012 /*
1013 * Ralink has a retry mechanism using a global fallback
1014 * table. We setup this fallback table to try the immediate
1015 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1016 * always contains the MCS used for the last transmission, be
1017 * it successful or not.
1018 */
1019 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1020 /*
1021 * Transmission succeeded. The number of retries is
1022 * mcs - real_mcs
1023 */
1024 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1025 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1026 } else {
1027 /*
1028 * Transmission failed. The number of retries is
1029 * always 7 in this case (for a total number of 8
1030 * frames sent).
1031 */
1032 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1033 txdesc.retry = rt2x00dev->long_retry;
1034 }
1035
1036 /*
1037 * the frame was retried at least once
1038 * -> hw used fallback rates
1039 */
1040 if (txdesc.retry)
1041 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1042
293dff78
SG		 1043 if (!match) {
1044 /* RCU assures non-null sta will not be freed by mac80211. */
1045 rcu_read_lock();
1046 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1047 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1048 else
1049 skbdesc->sta = NULL;
1050 rt2x00lib_txdone_nomatch(entry, &txdesc);
1051 rcu_read_unlock();
1052 } else {
1053 rt2x00lib_txdone(entry, &txdesc);
1054 }
14433331
HS		 1055}
1056EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1057
21c6af6b
GJ		 1058static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1059 unsigned int index)
1060{
1061 return HW_BEACON_BASE(index);
1062}
1063
634b8059
GJ		 1064static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1065 unsigned int index)
1066{
1067 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1068}
1069
ba08910e
SG		 1070static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1071{
1072 struct data_queue *queue = rt2x00dev->bcn;
1073 struct queue_entry *entry;
1074 int i, bcn_num = 0;
1075 u64 off, reg = 0;
1076 u32 bssid_dw1;
1077
1078 /*
1079 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1080 */
1081 for (i = 0; i < queue->limit; i++) {
1082 entry = &queue->entries[i];
1083 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1084 continue;
1085 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1086 reg |= off << (8 * bcn_num);
1087 bcn_num++;
1088 }
1089
ba08910e
SG		 1090 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1091 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1092
1093 /*
1094 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1095 */
1096 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
1097 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1098 bcn_num > 0 ? bcn_num - 1 : 0);
1099 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1100}
1101
f0194b2d
GW		 1102void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1103{
1104 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1105 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1106 unsigned int beacon_base;
739fd940 1107 unsigned int padding_len;
d76dfc61 1108 u32 orig_reg, reg;
f0bda571 1109 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 1110
1111 /*
1112 * Disable beaconing while we are reloading the beacon data,
1113 * otherwise we might be sending out invalid data.
1114 */
1115 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 1116 orig_reg = reg;
f0194b2d
GW		 1117 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1118 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1119
1120 /*
1121 * Add space for the TXWI in front of the skb.
1122 */
f0bda571 1123 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 1124
1125 /*
1126 * Register descriptor details in skb frame descriptor.
1127 */
1128 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1129 skbdesc->desc = entry->skb->data;
f0bda571 1130 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 1131
1132 /*
1133 * Add the TXWI for the beacon to the skb.
1134 */
0c5879bc 1135 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 1136
1137 /*
1138 * Dump beacon to userspace through debugfs.
1139 */
2ceb8137 1140 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
f0194b2d
GW		 1141
1142 /*
739fd940 1143 * Write entire beacon with TXWI and padding to register.
f0194b2d 1144 */
739fd940 1145 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 1146 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1147 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1148 /* skb freed by skb_pad() on failure */
1149 entry->skb = NULL;
1150 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1151 return;
1152 }
1153
21c6af6b
GJ		 1154 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1155
739fd940
WK		 1156 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1157 entry->skb->len + padding_len);
ba08910e
SG		 1158 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1159
1160 /*
1161 * Change global beacons settings.
1162 */
1163 rt2800_update_beacons_setup(rt2x00dev);
f0194b2d
GW		 1164
1165 /*
bc0df75a 1166 * Restore beaconing state.
f0194b2d 1167 */
bc0df75a 1168 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
f0194b2d
GW		 1169
1170 /*
1171 * Clean up beacon skb.
1172 */
1173 dev_kfree_skb_any(entry->skb);
1174 entry->skb = NULL;
1175}
50e888ea 1176EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1177
69cf36a4 1178static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1179 unsigned int index)
fdb87251
HS		 1180{
1181 int i;
0879f875 1182 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1183 unsigned int beacon_base;
1184
21c6af6b 1185 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1186
1187 /*
1188 * For the Beacon base registers we only need to clear
1189 * the whole TXWI which (when set to 0) will invalidate
1190 * the entire beacon.
1191 */
f0bda571 1192 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1193 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1194}
1195
69cf36a4
HS		 1196void rt2800_clear_beacon(struct queue_entry *entry)
1197{
1198 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bc0df75a 1199 u32 orig_reg, reg;
69cf36a4
HS		 1200
1201 /*
1202 * Disable beaconing while we are reloading the beacon data,
1203 * otherwise we might be sending out invalid data.
1204 */
bc0df75a
SG		 1205 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1206 reg = orig_reg;
69cf36a4
HS		 1207 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1208 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1209
1210 /*
1211 * Clear beacon.
1212 */
77f7c0f3 1213 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
ba08910e 1214 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
69cf36a4 1215
ba08910e
SG		 1216 /*
1217 * Change global beacons settings.
1218 */
1219 rt2800_update_beacons_setup(rt2x00dev);
69cf36a4 1220 /*
bc0df75a 1221 * Restore beaconing state.
69cf36a4 1222 */
bc0df75a 1223 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
69cf36a4
HS		 1224}
1225EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1226
f4450616
BZ		 1227#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1228const struct rt2x00debug rt2800_rt2x00debug = {
1229 .owner = THIS_MODULE,
1230 .csr = {
1231 .read = rt2800_register_read,
1232 .write = rt2800_register_write,
1233 .flags = RT2X00DEBUGFS_OFFSET,
1234 .word_base = CSR_REG_BASE,
1235 .word_size = sizeof(u32),
1236 .word_count = CSR_REG_SIZE / sizeof(u32),
1237 },
1238 .eeprom = {
3e38d3da
GJ		 1239 /* NOTE: The local EEPROM access functions can't
1240 * be used here, use the generic versions instead.
1241 */
f4450616
BZ		 1242 .read = rt2x00_eeprom_read,
1243 .write = rt2x00_eeprom_write,
1244 .word_base = EEPROM_BASE,
1245 .word_size = sizeof(u16),
1246 .word_count = EEPROM_SIZE / sizeof(u16),
1247 },
1248 .bbp = {
1249 .read = rt2800_bbp_read,
1250 .write = rt2800_bbp_write,
1251 .word_base = BBP_BASE,
1252 .word_size = sizeof(u8),
1253 .word_count = BBP_SIZE / sizeof(u8),
1254 },
1255 .rf = {
1256 .read = rt2x00_rf_read,
1257 .write = rt2800_rf_write,
1258 .word_base = RF_BASE,
1259 .word_size = sizeof(u32),
1260 .word_count = RF_SIZE / sizeof(u32),
1261 },
f2bd7f16
AA		 1262 .rfcsr = {
1263 .read = rt2800_rfcsr_read,
1264 .write = rt2800_rfcsr_write,
1265 .word_base = RFCSR_BASE,
1266 .word_size = sizeof(u8),
1267 .word_count = RFCSR_SIZE / sizeof(u8),
1268 },
f4450616
BZ		 1269};
1270EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1271#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1272
1273int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1274{
1275 u32 reg;
1276
a89534ed
WH		 1277 if (rt2x00_rt(rt2x00dev, RT3290)) {
1278 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1279 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1280 } else {
99bdf51a
GW		 1281 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1282 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1283 }
f4450616
BZ		 1284}
1285EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1286
1287#ifdef CONFIG_RT2X00_LIB_LEDS
1288static void rt2800_brightness_set(struct led_classdev *led_cdev,
1289 enum led_brightness brightness)
1290{
1291 struct rt2x00_led *led =
1292 container_of(led_cdev, struct rt2x00_led, led_dev);
1293 unsigned int enabled = brightness != LED_OFF;
1294 unsigned int bg_mode =
57fbcce3 1295 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
f4450616
BZ		 1296 unsigned int polarity =
1297 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1298 EEPROM_FREQ_LED_POLARITY);
1299 unsigned int ledmode =
1300 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1301 EEPROM_FREQ_LED_MODE);
44704e5d 1302 u32 reg;
f4450616 1303
44704e5d
LE		 1304 /* Check for SoC (SOC devices don't support MCU requests) */
1305 if (rt2x00_is_soc(led->rt2x00dev)) {
1306 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1307
1308 /* Set LED Polarity */
1309 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1310
1311 /* Set LED Mode */
1312 if (led->type == LED_TYPE_RADIO) {
1313 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1314 enabled ? 3 : 0);
1315 } else if (led->type == LED_TYPE_ASSOC) {
1316 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1317 enabled ? 3 : 0);
1318 } else if (led->type == LED_TYPE_QUALITY) {
1319 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1320 enabled ? 3 : 0);
1321 }
1322
1323 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1324
1325 } else {
1326 if (led->type == LED_TYPE_RADIO) {
1327 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1328 enabled ? 0x20 : 0);
1329 } else if (led->type == LED_TYPE_ASSOC) {
1330 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1331 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1332 } else if (led->type == LED_TYPE_QUALITY) {
1333 /*
1334 * The brightness is divided into 6 levels (0 - 5),
1335 * The specs tell us the following levels:
1336 * 0, 1 ,3, 7, 15, 31
1337 * to determine the level in a simple way we can simply
1338 * work with bitshifting:
1339 * (1 << level) - 1
1340 */
1341 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1342 (1 << brightness / (LED_FULL / 6)) - 1,
1343 polarity);
1344 }
f4450616
BZ		 1345 }
1346}
1347
b3579d6a 1348static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1349 struct rt2x00_led *led, enum led_type type)
1350{
1351 led->rt2x00dev = rt2x00dev;
1352 led->type = type;
1353 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1354 led->flags = LED_INITIALIZED;
1355}
f4450616
BZ		 1356#endif /* CONFIG_RT2X00_LIB_LEDS */
1357
1358/*
1359 * Configuration handlers.
1360 */
a2b1328a
HS		 1361static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1362 const u8 *address,
1363 int wcid)
f4450616
BZ		 1364{
1365 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1366 u32 offset;
1367
1368 offset = MAC_WCID_ENTRY(wcid);
1369
1370 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1371 if (address)
1372 memcpy(wcid_entry.mac, address, ETH_ALEN);
1373
1374 rt2800_register_multiwrite(rt2x00dev, offset,
1375 &wcid_entry, sizeof(wcid_entry));
1376}
1377
1378static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1379{
1380 u32 offset;
1381 offset = MAC_WCID_ATTR_ENTRY(wcid);
1382 rt2800_register_write(rt2x00dev, offset, 0);
1383}
1384
1385static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1386 int wcid, u32 bssidx)
1387{
1388 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1389 u32 reg;
1390
1391 /*
1392 * The BSS Idx numbers is split in a main value of 3 bits,
1393 * and a extended field for adding one additional bit to the value.
1394 */
1395 rt2800_register_read(rt2x00dev, offset, &reg);
1396 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1397 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1398 (bssidx & 0x8) >> 3);
1399 rt2800_register_write(rt2x00dev, offset, reg);
1400}
1401
1402static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1403 struct rt2x00lib_crypto *crypto,
1404 struct ieee80211_key_conf *key)
1405{
f4450616
BZ		 1406 struct mac_iveiv_entry iveiv_entry;
1407 u32 offset;
1408 u32 reg;
1409
1410 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1411
e4a0ab34
ID		 1412 if (crypto->cmd == SET_KEY) {
1413 rt2800_register_read(rt2x00dev, offset, &reg);
1414 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1415 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1416 /*
1417 * Both the cipher as the BSS Idx numbers are split in a main
1418 * value of 3 bits, and a extended field for adding one additional
1419 * bit to the value.
1420 */
1421 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1422 (crypto->cipher & 0x7));
1423 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1424 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1425 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1426 rt2800_register_write(rt2x00dev, offset, reg);
1427 } else {
a2b1328a
HS		 1428 /* Delete the cipher without touching the bssidx */
1429 rt2800_register_read(rt2x00dev, offset, &reg);
1430 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1431 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1432 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1433 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1434 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1435 }
f4450616
BZ		 1436
1437 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1438
1439 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1440 if ((crypto->cipher == CIPHER_TKIP) ||
1441 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1442 (crypto->cipher == CIPHER_AES))
1443 iveiv_entry.iv[3] |= 0x20;
1444 iveiv_entry.iv[3] |= key->keyidx << 6;
1445 rt2800_register_multiwrite(rt2x00dev, offset,
1446 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1447}
1448
1449int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1450 struct rt2x00lib_crypto *crypto,
1451 struct ieee80211_key_conf *key)
1452{
1453 struct hw_key_entry key_entry;
1454 struct rt2x00_field32 field;
1455 u32 offset;
1456 u32 reg;
1457
1458 if (crypto->cmd == SET_KEY) {
1459 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1460
1461 memcpy(key_entry.key, crypto->key,
1462 sizeof(key_entry.key));
1463 memcpy(key_entry.tx_mic, crypto->tx_mic,
1464 sizeof(key_entry.tx_mic));
1465 memcpy(key_entry.rx_mic, crypto->rx_mic,
1466 sizeof(key_entry.rx_mic));
1467
1468 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1469 rt2800_register_multiwrite(rt2x00dev, offset,
1470 &key_entry, sizeof(key_entry));
1471 }
1472
1473 /*
1474 * The cipher types are stored over multiple registers
1475 * starting with SHARED_KEY_MODE_BASE each word will have
1476 * 32 bits and contains the cipher types for 2 bssidx each.
1477 * Using the correct defines correctly will cause overhead,
1478 * so just calculate the correct offset.
1479 */
1480 field.bit_offset = 4 * (key->hw_key_idx % 8);
1481 field.bit_mask = 0x7 << field.bit_offset;
1482
1483 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1484
1485 rt2800_register_read(rt2x00dev, offset, &reg);
1486 rt2x00_set_field32(&reg, field,
1487 (crypto->cmd == SET_KEY) * crypto->cipher);
1488 rt2800_register_write(rt2x00dev, offset, reg);
1489
1490 /*
1491 * Update WCID information
1492 */
a2b1328a
HS		 1493 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1494 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1495 crypto->bssidx);
1496 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1497
1498 return 0;
1499}
1500EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1501
1502int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1503 struct rt2x00lib_crypto *crypto,
1504 struct ieee80211_key_conf *key)
1505{
1506 struct hw_key_entry key_entry;
1507 u32 offset;
1508
1509 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1510 /*
1511 * Allow key configuration only for STAs that are
1512 * known by the hw.
1513 */
ed8e0ed5 1514 if (crypto->wcid > WCID_END)
f4450616 1515 return -ENOSPC;
a2b1328a 1516 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1517
1518 memcpy(key_entry.key, crypto->key,
1519 sizeof(key_entry.key));
1520 memcpy(key_entry.tx_mic, crypto->tx_mic,
1521 sizeof(key_entry.tx_mic));
1522 memcpy(key_entry.rx_mic, crypto->rx_mic,
1523 sizeof(key_entry.rx_mic));
1524
1525 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1526 rt2800_register_multiwrite(rt2x00dev, offset,
1527 &key_entry, sizeof(key_entry));
1528 }
1529
1530 /*
1531 * Update WCID information
1532 */
a2b1328a 1533 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1534
1535 return 0;
1536}
1537EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1538
8f03a7c6
SG		 1539static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1540{
1541 u8 i, max_psdu;
1542 u32 reg;
1543 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1544
1545 for (i = 0; i < 3; i++)
1546 if (drv_data->ampdu_factor_cnt[i] > 0)
1547 break;
1548
1549 max_psdu = min(drv_data->max_psdu, i);
1550
1551 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1552 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1553 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1554}
1555
a2b1328a
HS		 1556int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1557 struct ieee80211_sta *sta)
1558{
1559 int wcid;
1560 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
ed8e0ed5 1561 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
a2b1328a 1562
8f03a7c6
SG		 1563 /*
1564 * Limit global maximum TX AMPDU length to smallest value of all
1565 * connected stations. In AP mode this can be suboptimal, but we
1566 * do not have a choice if some connected STA is not capable to
1567 * receive the same amount of data like the others.
1568 */
1569 if (sta->ht_cap.ht_supported) {
1570 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1571 rt2800_set_max_psdu_len(rt2x00dev);
1572 }
1573
a2b1328a 1574 /*
ed8e0ed5
SG		 1575 * Search for the first free WCID entry and return the corresponding
1576 * index.
a2b1328a 1577 */
ed8e0ed5 1578 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
a2b1328a
HS		 1579
1580 /*
1581 * Store selected wcid even if it is invalid so that we can
1582 * later decide if the STA is uploaded into the hw.
1583 */
1584 sta_priv->wcid = wcid;
1585
1586 /*
1587 * No space left in the device, however, we can still communicate
1588 * with the STA -> No error.
1589 */
ed8e0ed5 1590 if (wcid > WCID_END)
a2b1328a
HS		 1591 return 0;
1592
ed8e0ed5 1593 __set_bit(wcid - WCID_START, drv_data->sta_ids);
a13d985f 1594 drv_data->wcid_to_sta[wcid - WCID_START] = sta;
ed8e0ed5 1595
a2b1328a
HS		 1596 /*
1597 * Clean up WCID attributes and write STA address to the device.
1598 */
1599 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1600 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1601 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1602 rt2x00lib_get_bssidx(rt2x00dev, vif));
1603 return 0;
1604}
1605EXPORT_SYMBOL_GPL(rt2800_sta_add);
1606
8f03a7c6 1607int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, struct ieee80211_sta *sta)
a2b1328a 1608{
ed8e0ed5 1609 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8f03a7c6
SG		 1610 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1611 int wcid = sta_priv->wcid;
1612
1613 if (sta->ht_cap.ht_supported) {
1614 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1615 rt2800_set_max_psdu_len(rt2x00dev);
1616 }
ed8e0ed5
SG		 1617
1618 if (wcid > WCID_END)
1619 return 0;
a2b1328a
HS		 1620 /*
1621 * Remove WCID entry, no need to clean the attributes as they will
1622 * get renewed when the WCID is reused.
1623 */
1624 rt2800_config_wcid(rt2x00dev, NULL, wcid);
a13d985f 1625 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
ed8e0ed5 1626 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
a2b1328a
HS		 1627
1628 return 0;
1629}
1630EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1631
f4450616
BZ		 1632void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1633 const unsigned int filter_flags)
1634{
1635 u32 reg;
1636
1637 /*
1638 * Start configuration steps.
1639 * Note that the version error will always be dropped
1640 * and broadcast frames will always be accepted since
1641 * there is no filter for it at this time.
1642 */
1643 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1644 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1645 !(filter_flags & FIF_FCSFAIL));
1646 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1647 !(filter_flags & FIF_PLCPFAIL));
262c741e
EC		 1648 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1649 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
f4450616
BZ		 1650 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1651 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1652 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1653 !(filter_flags & FIF_ALLMULTI));
1654 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1655 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1656 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1657 !(filter_flags & FIF_CONTROL));
1658 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1659 !(filter_flags & FIF_CONTROL));
1660 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1661 !(filter_flags & FIF_CONTROL));
1662 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1663 !(filter_flags & FIF_CONTROL));
1664 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1665 !(filter_flags & FIF_CONTROL));
1666 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1667 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1668 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1669 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1670 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1671 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1672 !(filter_flags & FIF_CONTROL));
1673 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1674}
1675EXPORT_SYMBOL_GPL(rt2800_config_filter);
1676
1677void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1678 struct rt2x00intf_conf *conf, const unsigned int flags)
1679{
f4450616 1680 u32 reg;
fa8b4b22 1681 bool update_bssid = false;
f4450616
BZ		 1682
1683 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1684 /*
1685 * Enable synchronisation.
1686 */
1687 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1688 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1689 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1690
1691 if (conf->sync == TSF_SYNC_AP_NONE) {
1692 /*
1693 * Tune beacon queue transmit parameters for AP mode
1694 */
1695 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1696 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1697 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1698 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1699 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1700 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1701 } else {
1702 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1703 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1704 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1705 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1706 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1707 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1708 }
f4450616
BZ		 1709 }
1710
1711 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1712 if (flags & CONFIG_UPDATE_TYPE &&
1713 conf->sync == TSF_SYNC_AP_NONE) {
1714 /*
1715 * The BSSID register has to be set to our own mac
1716 * address in AP mode.
1717 */
1718 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1719 update_bssid = true;
1720 }
1721
c600c826
ID		 1722 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1723 reg = le32_to_cpu(conf->mac[1]);
1724 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1725 conf->mac[1] = cpu_to_le32(reg);
1726 }
f4450616
BZ		 1727
1728 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1729 conf->mac, sizeof(conf->mac));
1730 }
1731
fa8b4b22 1732 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1733 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1734 reg = le32_to_cpu(conf->bssid[1]);
1735 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
88ff2f45 1736 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
c600c826
ID		 1737 conf->bssid[1] = cpu_to_le32(reg);
1738 }
f4450616
BZ		 1739
1740 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1741 conf->bssid, sizeof(conf->bssid));
1742 }
1743}
1744EXPORT_SYMBOL_GPL(rt2800_config_intf);
1745
87c1915d
HS		 1746static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1747 struct rt2x00lib_erp *erp)
1748{
1749 bool any_sta_nongf = !!(erp->ht_opmode &
1750 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1751 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1752 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1753 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1754 u32 reg;
1755
1756 /* default protection rate for HT20: OFDM 24M */
1757 mm20_rate = gf20_rate = 0x4004;
1758
1759 /* default protection rate for HT40: duplicate OFDM 24M */
1760 mm40_rate = gf40_rate = 0x4084;
1761
1762 switch (protection) {
1763 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1764 /*
1765 * All STAs in this BSS are HT20/40 but there might be
1766 * STAs not supporting greenfield mode.
1767 * => Disable protection for HT transmissions.
1768 */
1769 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1770
1771 break;
1772 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1773 /*
1774 * All STAs in this BSS are HT20 or HT20/40 but there
1775 * might be STAs not supporting greenfield mode.
1776 * => Protect all HT40 transmissions.
1777 */
1778 mm20_mode = gf20_mode = 0;
6c40063d 1779 mm40_mode = gf40_mode = 1;
87c1915d
HS		 1780
1781 break;
1782 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1783 /*
1784 * Nonmember protection:
1785 * According to 802.11n we _should_ protect all
1786 * HT transmissions (but we don't have to).
1787 *
1788 * But if cts_protection is enabled we _shall_ protect
1789 * all HT transmissions using a CCK rate.
1790 *
1791 * And if any station is non GF we _shall_ protect
1792 * GF transmissions.
1793 *
1794 * We decide to protect everything
1795 * -> fall through to mixed mode.
1796 */
1797 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1798 /*
1799 * Legacy STAs are present
1800 * => Protect all HT transmissions.
1801 */
6c40063d 1802 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
87c1915d
HS		 1803
1804 /*
1805 * If erp protection is needed we have to protect HT
1806 * transmissions with CCK 11M long preamble.
1807 */
1808 if (erp->cts_protection) {
1809 /* don't duplicate RTS/CTS in CCK mode */
1810 mm20_rate = mm40_rate = 0x0003;
1811 gf20_rate = gf40_rate = 0x0003;
1812 }
1813 break;
6403eab1 1814 }
87c1915d
HS		 1815
1816 /* check for STAs not supporting greenfield mode */
1817 if (any_sta_nongf)
6c40063d 1818 gf20_mode = gf40_mode = 1;
87c1915d
HS		 1819
1820 /* Update HT protection config */
1821 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1822 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1823 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1824 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1825
1826 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1827 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1828 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1829 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1830
1831 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1832 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1833 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1834 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1835
1836 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1837 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1838 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1839 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1840}
1841
02044643
HS		 1842void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1843 u32 changed)
f4450616
BZ		 1844{
1845 u32 reg;
1846
02044643
HS		 1847 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1848 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
02044643
HS		 1849 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1850 !!erp->short_preamble);
1851 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1852 }
f4450616 1853
02044643
HS		 1854 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1855 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1856 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1857 erp->cts_protection ? 2 : 0);
1858 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1859 }
f4450616 1860
02044643
HS		 1861 if (changed & BSS_CHANGED_BASIC_RATES) {
1862 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
770e4b73 1863 0xff0 | erp->basic_rates);
02044643
HS		 1864 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1865 }
f4450616 1866
02044643
HS		 1867 if (changed & BSS_CHANGED_ERP_SLOT) {
1868 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1869 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1870 erp->slot_time);
1871 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1872
02044643
HS		 1873 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1874 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1875 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1876 }
f4450616 1877
02044643
HS		 1878 if (changed & BSS_CHANGED_BEACON_INT) {
1879 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1880 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1881 erp->beacon_int * 16);
1882 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1883 }
87c1915d
HS		 1884
1885 if (changed & BSS_CHANGED_HT)
1886 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1887}
1888EXPORT_SYMBOL_GPL(rt2800_config_erp);
1889
872834df
GW		 1890static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1891{
1892 u32 reg;
1893 u16 eeprom;
1894 u8 led_ctrl, led_g_mode, led_r_mode;
1895
1896 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
57fbcce3 1897 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
872834df
GW		 1898 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1899 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1900 } else {
1901 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1902 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1903 }
1904 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1905
1906 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1907 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1908 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1909 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1910 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1911 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1912 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1913 if (led_ctrl == 0 || led_ctrl > 0x40) {
1914 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1915 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1916 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1917 } else {
1918 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1919 (led_g_mode << 2) | led_r_mode, 1);
1920 }
1921 }
1922}
1923
d96aa640
RJH		 1924static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1925 enum antenna ant)
1926{
1927 u32 reg;
1928 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1929 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1930
1931 if (rt2x00_is_pci(rt2x00dev)) {
1932 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1933 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1934 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1935 } else if (rt2x00_is_usb(rt2x00dev))
1936 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1937 eesk_pin, 0);
1938
99bdf51a
GW		 1939 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1940 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1941 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1942 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1943}
1944
f4450616
BZ		 1945void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1946{
1947 u8 r1;
1948 u8 r3;
d96aa640 1949 u16 eeprom;
f4450616
BZ		 1950
1951 rt2800_bbp_read(rt2x00dev, 1, &r1);
1952 rt2800_bbp_read(rt2x00dev, 3, &r3);
1953
872834df 1954 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1955 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1956 rt2800_config_3572bt_ant(rt2x00dev);
1957
f4450616
BZ		 1958 /*
1959 * Configure the TX antenna.
1960 */
d96aa640 1961 switch (ant->tx_chain_num) {
f4450616
BZ		 1962 case 1:
1963 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1964 break;
1965 case 2:
872834df 1966 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1967 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1968 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1969 else
1970 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1971 break;
1972 case 3:
4788ac1e 1973 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1974 break;
1975 }
1976
1977 /*
1978 * Configure the RX antenna.
1979 */
d96aa640 1980 switch (ant->rx_chain_num) {
f4450616 1981 case 1:
d96aa640
RJH		 1982 if (rt2x00_rt(rt2x00dev, RT3070) ||
1983 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1984 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1985 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1986 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1987 EEPROM_NIC_CONF1, &eeprom);
1988 if (rt2x00_get_field16(eeprom,
1989 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1990 rt2800_set_ant_diversity(rt2x00dev,
1991 rt2x00dev->default_ant.rx);
1992 }
f4450616
BZ		 1993 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1994 break;
1995 case 2:
872834df 1996 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1997 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 1998 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1999 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
57fbcce3 2000 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
872834df
GW		 2001 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2002 } else {
2003 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2004 }
f4450616
BZ		 2005 break;
2006 case 3:
2007 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2008 break;
2009 }
2010
2011 rt2800_bbp_write(rt2x00dev, 3, r3);
2012 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 2013
2014 if (rt2x00_rt(rt2x00dev, RT3593)) {
2015 if (ant->rx_chain_num == 1)
2016 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2017 else
2018 rt2800_bbp_write(rt2x00dev, 86, 0x46);
2019 }
f4450616
BZ		 2020}
2021EXPORT_SYMBOL_GPL(rt2800_config_ant);
2022
2023static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2024 struct rt2x00lib_conf *libconf)
2025{
2026 u16 eeprom;
2027 short lna_gain;
2028
2029 if (libconf->rf.channel <= 14) {
3e38d3da 2030 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 2031 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2032 } else if (libconf->rf.channel <= 64) {
3e38d3da 2033 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 2034 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2035 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 2036 if (rt2x00_rt(rt2x00dev, RT3593)) {
2037 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
2038 lna_gain = rt2x00_get_field16(eeprom,
2039 EEPROM_EXT_LNA2_A1);
2040 } else {
2041 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
2042 lna_gain = rt2x00_get_field16(eeprom,
2043 EEPROM_RSSI_BG2_LNA_A1);
2044 }
f4450616 2045 } else {
f36bb0ca
GJ		 2046 if (rt2x00_rt(rt2x00dev, RT3593)) {
2047 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
2048 lna_gain = rt2x00_get_field16(eeprom,
2049 EEPROM_EXT_LNA2_A2);
2050 } else {
2051 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
2052 lna_gain = rt2x00_get_field16(eeprom,
2053 EEPROM_RSSI_A2_LNA_A2);
2054 }
f4450616
BZ		 2055 }
2056
2057 rt2x00dev->lna_gain = lna_gain;
2058}
2059
5c4412e0
DG		 2060static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2061{
2062 return clk_get_rate(rt2x00dev->clk) == 20000000;
2063}
2064
3f1b8739
GJ		 2065#define FREQ_OFFSET_BOUND 0x5f
2066
88452541 2067static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
3f1b8739
GJ		 2068{
2069 u8 freq_offset, prev_freq_offset;
2070 u8 rfcsr, prev_rfcsr;
2071
2072 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2073 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2074
2075 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2076 prev_rfcsr = rfcsr;
2077
2078 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2079 if (rfcsr == prev_rfcsr)
2080 return;
2081
2082 if (rt2x00_is_usb(rt2x00dev)) {
2083 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2084 freq_offset, prev_rfcsr);
2085 return;
2086 }
2087
2088 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2089 while (prev_freq_offset != freq_offset) {
2090 if (prev_freq_offset < freq_offset)
2091 prev_freq_offset++;
2092 else
2093 prev_freq_offset--;
2094
2095 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2096 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2097
2098 usleep_range(1000, 1500);
2099 }
2100}
2101
06855ef4
GW		 2102static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2103 struct ieee80211_conf *conf,
2104 struct rf_channel *rf,
2105 struct channel_info *info)
f4450616
BZ		 2106{
2107 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2108
d96aa640 2109 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 2110 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2111
d96aa640 2112 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 2113 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2114 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 2115 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 2116 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2117
2118 if (rf->channel > 14) {
2119 /*
2120 * When TX power is below 0, we should increase it by 7 to
25985edc 2121 * make it a positive value (Minimum value is -7).
f4450616
BZ		 2122 * However this means that values between 0 and 7 have
2123 * double meaning, and we should set a 7DBm boost flag.
2124 */
2125 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 2126 (info->default_power1 >= 0));
f4450616 2127
8d1331b3
ID		 2128 if (info->default_power1 < 0)
2129 info->default_power1 += 7;
f4450616 2130
8d1331b3 2131 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 2132
2133 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 2134 (info->default_power2 >= 0));
f4450616 2135
8d1331b3
ID		 2136 if (info->default_power2 < 0)
2137 info->default_power2 += 7;
f4450616 2138
8d1331b3 2139 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 2140 } else {
8d1331b3
ID		 2141 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2142 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 2143 }
2144
2145 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2146
2147 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2148 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2149 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2150 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2151
2152 udelay(200);
2153
2154 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2155 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2156 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2157 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2158
2159 udelay(200);
2160
2161 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2162 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2163 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2164 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2165}
2166
06855ef4
GW		 2167static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2168 struct ieee80211_conf *conf,
2169 struct rf_channel *rf,
2170 struct channel_info *info)
f4450616 2171{
3a1c0128 2172 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 2173 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 2174
2175 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 2176
2177 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2178 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2179 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 2180
2181 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 2182 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2183 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2184
2185 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 2186 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2187 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2188
5a673964 2189 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 2190 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2191 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 2192
2193 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2194 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2195 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2196 rt2x00dev->default_ant.rx_chain_num <= 1);
2197 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2198 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2199 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2200 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2201 rt2x00dev->default_ant.tx_chain_num <= 1);
2202 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2203 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2204 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2205
f4450616
BZ		 2206 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2207 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2208 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2209
f1f12f98
SG		 2210 if (rt2x00_rt(rt2x00dev, RT3390)) {
2211 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2212 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2213 } else {
3a1c0128
GW		 2214 if (conf_is_ht40(conf)) {
2215 calib_tx = drv_data->calibration_bw40;
2216 calib_rx = drv_data->calibration_bw40;
2217 } else {
2218 calib_tx = drv_data->calibration_bw20;
2219 calib_rx = drv_data->calibration_bw20;
2220 }
f1f12f98
SG		 2221 }
2222
2223 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2224 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2225 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2226
2227 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2228 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2229 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2230
71976907 2231 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 2232 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2233 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 2234
2235 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2236 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2237 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
31369c32
SG		 2238
2239 usleep_range(1000, 1500);
2240
3e0c7643
SG		 2241 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2242 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2243}
2244
872834df
GW		 2245static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2246 struct ieee80211_conf *conf,
2247 struct rf_channel *rf,
2248 struct channel_info *info)
2249{
3a1c0128 2250 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2251 u8 rfcsr;
2252 u32 reg;
2253
2254 if (rf->channel <= 14) {
5d137dff
GW		 2255 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2256 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2257 } else {
2258 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2259 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2260 }
2261
2262 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2263 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2264
2265 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2266 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2267 if (rf->channel <= 14)
2268 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2269 else
2270 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2271 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2272
2273 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2274 if (rf->channel <= 14)
2275 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2276 else
2277 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2278 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2279
2280 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2281 if (rf->channel <= 14) {
2282 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2283 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2284 info->default_power1);
872834df
GW		 2285 } else {
2286 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2287 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2288 (info->default_power1 & 0x3) |
2289 ((info->default_power1 & 0xC) << 1));
2290 }
2291 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2292
2293 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2294 if (rf->channel <= 14) {
2295 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2296 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2297 info->default_power2);
872834df
GW		 2298 } else {
2299 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2300 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2301 (info->default_power2 & 0x3) |
2302 ((info->default_power2 & 0xC) << 1));
2303 }
2304 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2305
2306 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2307 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2308 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2309 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2310 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2311 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2312 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
c429dfef 2313 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2314 if (rf->channel <= 14) {
2315 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2316 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2317 }
2318 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2319 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2320 } else {
2321 switch (rt2x00dev->default_ant.tx_chain_num) {
2322 case 1:
2323 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2324 case 2:
2325 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2326 break;
2327 }
2328
2329 switch (rt2x00dev->default_ant.rx_chain_num) {
2330 case 1:
2331 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2332 case 2:
2333 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2334 break;
2335 }
2336 }
2337 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2338
2339 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2340 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2341 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2342
3a1c0128
GW		 2343 if (conf_is_ht40(conf)) {
2344 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2345 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2346 } else {
2347 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2348 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2349 }
872834df
GW		 2350
2351 if (rf->channel <= 14) {
2352 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2353 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2354 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2355 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2356 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2357 rfcsr = 0x4c;
2358 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2359 drv_data->txmixer_gain_24g);
2360 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2361 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2362 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2363 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2364 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2365 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2366 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2367 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2368 } else {
58b8ae14
GW		 2369 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2370 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2371 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2372 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2373 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2374 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2375 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2376 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2377 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2378 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2379 rfcsr = 0x7a;
2380 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2381 drv_data->txmixer_gain_5g);
2382 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2383 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2384 if (rf->channel <= 64) {
2385 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2386 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2387 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2388 } else if (rf->channel <= 128) {
2389 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2390 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2391 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2392 } else {
2393 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2394 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2395 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2396 }
2397 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2398 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2399 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2400 }
2401
99bdf51a
GW		 2402 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2403 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2404 if (rf->channel <= 14)
99bdf51a 2405 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2406 else
99bdf51a
GW		 2407 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2408 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2409
2410 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2411 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2412 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2413}
60687ba7 2414
f42b0465
GJ		 2415static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2416 struct ieee80211_conf *conf,
2417 struct rf_channel *rf,
2418 struct channel_info *info)
2419{
2420 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2421 u8 txrx_agc_fc;
2422 u8 txrx_h20m;
2423 u8 rfcsr;
2424 u8 bbp;
2425 const bool txbf_enabled = false; /* TODO */
2426
2427 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2428 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2429 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2430 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2431 rt2800_bbp_write(rt2x00dev, 109, bbp);
2432
2433 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2434 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2435 rt2800_bbp_write(rt2x00dev, 110, bbp);
2436
2437 if (rf->channel <= 14) {
2438 /* Restore BBP 25 & 26 for 2.4 GHz */
2439 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2440 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2441 } else {
2442 /* Hard code BBP 25 & 26 for 5GHz */
2443
2444 /* Enable IQ Phase correction */
2445 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2446 /* Setup IQ Phase correction value */
2447 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2448 }
2449
2450 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2451 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2452
2453 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2454 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2455 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2456
2457 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2458 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2459 if (rf->channel <= 14)
2460 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2461 else
2462 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2463 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2464
2465 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2466 if (rf->channel <= 14) {
2467 rfcsr = 0;
2468 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2469 info->default_power1 & 0x1f);
2470 } else {
2471 if (rt2x00_is_usb(rt2x00dev))
2472 rfcsr = 0x40;
2473
2474 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2475 ((info->default_power1 & 0x18) << 1) |
2476 (info->default_power1 & 7));
2477 }
2478 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2479
2480 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2481 if (rf->channel <= 14) {
2482 rfcsr = 0;
2483 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2484 info->default_power2 & 0x1f);
2485 } else {
2486 if (rt2x00_is_usb(rt2x00dev))
2487 rfcsr = 0x40;
2488
2489 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2490 ((info->default_power2 & 0x18) << 1) |
2491 (info->default_power2 & 7));
2492 }
2493 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2494
2495 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2496 if (rf->channel <= 14) {
2497 rfcsr = 0;
2498 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2499 info->default_power3 & 0x1f);
2500 } else {
2501 if (rt2x00_is_usb(rt2x00dev))
2502 rfcsr = 0x40;
2503
2504 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2505 ((info->default_power3 & 0x18) << 1) |
2506 (info->default_power3 & 7));
2507 }
2508 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2509
2510 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2511 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2512 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2513 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2514 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2515 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2516 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2517 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2518 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2519
2520 switch (rt2x00dev->default_ant.tx_chain_num) {
2521 case 3:
2522 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2523 /* fallthrough */
2524 case 2:
2525 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2526 /* fallthrough */
2527 case 1:
2528 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2529 break;
2530 }
2531
2532 switch (rt2x00dev->default_ant.rx_chain_num) {
2533 case 3:
2534 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2535 /* fallthrough */
2536 case 2:
2537 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2538 /* fallthrough */
2539 case 1:
2540 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2541 break;
2542 }
2543 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2544
88452541 2545 rt2800_freq_cal_mode1(rt2x00dev);
f42b0465
GJ		 2546
2547 if (conf_is_ht40(conf)) {
2548 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2549 RFCSR24_TX_AGC_FC);
2550 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2551 RFCSR24_TX_H20M);
2552 } else {
2553 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2554 RFCSR24_TX_AGC_FC);
2555 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2556 RFCSR24_TX_H20M);
2557 }
2558
2559 /* NOTE: the reference driver does not writes the new value
2560 * back to RFCSR 32
2561 */
2562 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2563 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2564
2565 if (rf->channel <= 14)
2566 rfcsr = 0xa0;
2567 else
2568 rfcsr = 0x80;
2569 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2570
2571 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2572 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2573 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2574 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2575
2576 /* Band selection */
2577 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2578 if (rf->channel <= 14)
2579 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2580 else
2581 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2582 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2583
2584 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2585 if (rf->channel <= 14)
2586 rfcsr = 0x3c;
2587 else
2588 rfcsr = 0x20;
2589 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2590
2591 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2592 if (rf->channel <= 14)
2593 rfcsr = 0x1a;
2594 else
2595 rfcsr = 0x12;
2596 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2597
2598 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2599 if (rf->channel >= 1 && rf->channel <= 14)
2600 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2601 else if (rf->channel >= 36 && rf->channel <= 64)
2602 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2603 else if (rf->channel >= 100 && rf->channel <= 128)
2604 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2605 else
2606 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2607 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2608
2609 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2610 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2611 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2612
2613 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2614
2615 if (rf->channel <= 14) {
2616 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2617 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2618 } else {
2619 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2620 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2621 }
2622
2623 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2624 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2625 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2626
2627 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2628 if (rf->channel <= 14) {
2629 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2630 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2631 } else {
2632 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2633 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2634 }
2635 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2636
2637 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2638 if (rf->channel <= 14)
2639 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2640 else
2641 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2642
2643 if (txbf_enabled)
2644 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2645
2646 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2647
2648 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2649 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2650 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2651
2652 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2653 if (rf->channel <= 14)
2654 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2655 else
2656 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2657 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2658
2659 if (rf->channel <= 14) {
2660 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2661 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2662 } else {
2663 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2664 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2665 }
2666
2667 /* Initiate VCO calibration */
2668 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2669 if (rf->channel <= 14) {
2670 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2671 } else {
2672 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2673 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2674 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2675 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2676 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2677 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2678 }
2679 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2680
2681 if (rf->channel >= 1 && rf->channel <= 14) {
2682 rfcsr = 0x23;
2683 if (txbf_enabled)
2684 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2685 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2686
2687 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2688 } else if (rf->channel >= 36 && rf->channel <= 64) {
2689 rfcsr = 0x36;
2690 if (txbf_enabled)
2691 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2692 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2693
2694 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2695 } else if (rf->channel >= 100 && rf->channel <= 128) {
2696 rfcsr = 0x32;
2697 if (txbf_enabled)
2698 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2699 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2700
2701 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2702 } else {
2703 rfcsr = 0x30;
2704 if (txbf_enabled)
2705 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2706 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2707
2708 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2709 }
2710}
2711
7573cb5b 2712#define POWER_BOUND 0x27
8f821098 2713#define POWER_BOUND_5G 0x2b
0c9e5fb9 2714
a89534ed
WH		 2715static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2716 struct ieee80211_conf *conf,
2717 struct rf_channel *rf,
2718 struct channel_info *info)
2719{
2720 u8 rfcsr;
2721
2722 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2723 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2724 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2725 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2726 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2727
2728 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2729 if (info->default_power1 > POWER_BOUND)
2730 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2731 else
2732 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2733 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2734
88452541 2735 rt2800_freq_cal_mode1(rt2x00dev);
a89534ed
WH		 2736
2737 if (rf->channel <= 14) {
2738 if (rf->channel == 6)
2739 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2740 else
2741 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2742
2743 if (rf->channel >= 1 && rf->channel <= 6)
2744 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2745 else if (rf->channel >= 7 && rf->channel <= 11)
2746 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2747 else if (rf->channel >= 12 && rf->channel <= 14)
2748 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2749 }
2750}
2751
03839951
DG		 2752static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2753 struct ieee80211_conf *conf,
2754 struct rf_channel *rf,
2755 struct channel_info *info)
2756{
2757 u8 rfcsr;
2758
2759 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2760 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2761
2762 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2763 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2764 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2765
2766 if (info->default_power1 > POWER_BOUND)
2767 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2768 else
2769 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2770
2771 if (info->default_power2 > POWER_BOUND)
2772 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2773 else
2774 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2775
88452541 2776 rt2800_freq_cal_mode1(rt2x00dev);
03839951
DG		 2777
2778 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2779 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2780 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2781
2782 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2783 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2784 else
2785 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2786
2787 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2788 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2789 else
2790 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2791
2792 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2793 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2794
2795 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2796
2797 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2798}
2799
60687ba7 2800static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2801 struct ieee80211_conf *conf,
2802 struct rf_channel *rf,
2803 struct channel_info *info)
2804{
2805 u8 rfcsr;
adde5882
GJ		 2806
2807 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2808 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2809 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2810 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2811 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2812
2813 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2814 if (info->default_power1 > POWER_BOUND)
2815 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2816 else
2817 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2818 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2819
cff3d1f0
ZL		 2820 if (rt2x00_rt(rt2x00dev, RT5392)) {
2821 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
6264995f 2822 if (info->default_power2 > POWER_BOUND)
7573cb5b 2823 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2824 else
2825 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2826 info->default_power2);
2827 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2828 }
2829
adde5882 2830 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2831 if (rt2x00_rt(rt2x00dev, RT5392)) {
2832 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2833 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2834 }
adde5882
GJ		 2835 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2836 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2837 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2838 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2839 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2840
88452541 2841 rt2800_freq_cal_mode1(rt2x00dev);
adde5882 2842
adde5882
GJ		 2843 if (rf->channel <= 14) {
2844 int idx = rf->channel-1;
2845
c429dfef 2846 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
adde5882
GJ		 2847 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2848 /* r55/r59 value array of channel 1~14 */
2849 static const char r55_bt_rev[] = {0x83, 0x83,
2850 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2851 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2852 static const char r59_bt_rev[] = {0x0e, 0x0e,
2853 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2854 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2855
2856 rt2800_rfcsr_write(rt2x00dev, 55,
2857 r55_bt_rev[idx]);
2858 rt2800_rfcsr_write(rt2x00dev, 59,
2859 r59_bt_rev[idx]);
2860 } else {
2861 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2862 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2863 0x88, 0x88, 0x86, 0x85, 0x84};
2864
2865 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2866 }
2867 } else {
2868 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2869 static const char r55_nonbt_rev[] = {0x23, 0x23,
2870 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2871 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2872 static const char r59_nonbt_rev[] = {0x07, 0x07,
2873 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2874 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2875
2876 rt2800_rfcsr_write(rt2x00dev, 55,
2877 r55_nonbt_rev[idx]);
2878 rt2800_rfcsr_write(rt2x00dev, 59,
2879 r59_nonbt_rev[idx]);
2ed71884 2880 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
41977e86
RY		 2881 rt2x00_rt(rt2x00dev, RT5392) ||
2882 rt2x00_rt(rt2x00dev, RT6352)) {
adde5882
GJ		 2883 static const char r59_non_bt[] = {0x8f, 0x8f,
2884 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2885 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2886
98e71f44
SV		 2887 rt2800_rfcsr_write(rt2x00dev, 59,
2888 r59_non_bt[idx]);
2889 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
2890 static const char r59_non_bt[] = {0x0b, 0x0b,
2891 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
2892 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
2893
adde5882
GJ		 2894 rt2800_rfcsr_write(rt2x00dev, 59,
2895 r59_non_bt[idx]);
2896 }
2897 }
2898 }
60687ba7
RST		 2899}
2900
8f821098
SG		 2901static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2902 struct ieee80211_conf *conf,
2903 struct rf_channel *rf,
2904 struct channel_info *info)
2905{
2906 u8 rfcsr, ep_reg;
d5ae7a6b 2907 u32 reg;
8f821098
SG		 2908 int power_bound;
2909
2910 /* TODO */
2911 const bool is_11b = false;
2912 const bool is_type_ep = false;
2913
d5ae7a6b
SG		 2914 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2915 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2916 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2917 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2918
2919 /* Order of values on rf_channel entry: N, K, mod, R */
2920 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2921
2922 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2923 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2924 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2925 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2926 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2927
2928 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2929 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2930 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2931 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2932
2933 if (rf->channel <= 14) {
2934 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2935 /* FIXME: RF11 owerwrite ? */
2936 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2937 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2938 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2939 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2940 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2941 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2942 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2943 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2944 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2945 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2946 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2947 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2948 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2949 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2950 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2951 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2952 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2953 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2954 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2955 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2956 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2957 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2958 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2959 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2960 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2961 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2962 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2963 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2964
2965 /* TODO RF27 <- tssi */
2966
2967 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2968 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2969 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2970
2971 if (is_11b) {
2972 /* CCK */
2973 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2974 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2975 if (is_type_ep)
2976 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2977 else
2978 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2979 } else {
2980 /* OFDM */
2981 if (is_type_ep)
2982 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2983 else
2984 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2985 }
2986
2987 power_bound = POWER_BOUND;
2988 ep_reg = 0x2;
2989 } else {
2990 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2991 /* FIMXE: RF11 overwrite */
2992 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2993 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2994 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2995 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2996 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2997 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2998 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2999 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3000 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3001 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3002 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3003 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3004 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3005 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3006
3007 /* TODO RF27 <- tssi */
3008
3009 if (rf->channel >= 36 && rf->channel <= 64) {
3010
3011 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3012 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3013 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3014 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3015 if (rf->channel <= 50)
3016 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3017 else if (rf->channel >= 52)
3018 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3019 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3020 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3021 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3022 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3023 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3024 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3025 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3026 if (rf->channel <= 50) {
3027 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3028 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3029 } else if (rf->channel >= 52) {
3030 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3031 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3032 }
3033
3034 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3035 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3036 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3037
3038 } else if (rf->channel >= 100 && rf->channel <= 165) {
3039
3040 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3041 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3042 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3043 if (rf->channel <= 153) {
3044 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3045 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3046 } else if (rf->channel >= 155) {
3047 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3048 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3049 }
3050 if (rf->channel <= 138) {
3051 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3052 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3053 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3054 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3055 } else if (rf->channel >= 140) {
3056 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3057 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3058 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3059 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3060 }
3061 if (rf->channel <= 124)
3062 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3063 else if (rf->channel >= 126)
3064 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3065 if (rf->channel <= 138)
3066 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3067 else if (rf->channel >= 140)
3068 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3069 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3070 if (rf->channel <= 138)
3071 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3072 else if (rf->channel >= 140)
3073 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3074 if (rf->channel <= 128)
3075 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3076 else if (rf->channel >= 130)
3077 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3078 if (rf->channel <= 116)
3079 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3080 else if (rf->channel >= 118)
3081 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3082 if (rf->channel <= 138)
3083 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3084 else if (rf->channel >= 140)
3085 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3086 if (rf->channel <= 116)
3087 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3088 else if (rf->channel >= 118)
3089 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3090 }
3091
3092 power_bound = POWER_BOUND_5G;
3093 ep_reg = 0x3;
3094 }
3095
3096 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
3097 if (info->default_power1 > power_bound)
3098 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3099 else
3100 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3101 if (is_type_ep)
3102 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3103 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3104
3105 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 3106 if (info->default_power2 > power_bound)
8f821098
SG		 3107 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3108 else
3109 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3110 if (is_type_ep)
3111 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3112 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3113
3114 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3115 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3116 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3117
3118 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3119 rt2x00dev->default_ant.tx_chain_num >= 1);
3120 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3121 rt2x00dev->default_ant.tx_chain_num == 2);
3122 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3123
3124 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3125 rt2x00dev->default_ant.rx_chain_num >= 1);
3126 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3127 rt2x00dev->default_ant.rx_chain_num == 2);
3128 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3129
3130 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3131 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3132
3133 if (conf_is_ht40(conf))
3134 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3135 else
3136 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3137
3138 if (!is_11b) {
3139 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3140 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3141 }
3142
3143 /* TODO proper frequency adjustment */
88452541 3144 rt2800_freq_cal_mode1(rt2x00dev);
8f821098
SG		 3145
3146 /* TODO merge with others */
3147 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3148 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3149 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 3150
3151 /* BBP settings */
3152 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3153 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3154 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3155
3156 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3157 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3158 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3159 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3160
3161 /* GLRT band configuration */
3162 rt2800_bbp_write(rt2x00dev, 195, 128);
3163 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3164 rt2800_bbp_write(rt2x00dev, 195, 129);
3165 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3166 rt2800_bbp_write(rt2x00dev, 195, 130);
3167 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3168 rt2800_bbp_write(rt2x00dev, 195, 131);
3169 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3170 rt2800_bbp_write(rt2x00dev, 195, 133);
3171 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3172 rt2800_bbp_write(rt2x00dev, 195, 124);
3173 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 3174}
3175
41977e86
RY		 3176static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3177 struct ieee80211_conf *conf,
3178 struct rf_channel *rf,
3179 struct channel_info *info)
3180{
3181 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3182 u8 rx_agc_fc, tx_agc_fc;
3183 u8 rfcsr;
3184
3185 /* Frequeny plan setting */
3186 /* Rdiv setting (set 0x03 if Xtal==20)
3187 * R13[1:0]
3188 */
3189 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
3190 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3191 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3192 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3193
3194 /* N setting
3195 * R20[7:0] in rf->rf1
3196 * R21[0] always 0
3197 */
3198 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3199 rfcsr = (rf->rf1 & 0x00ff);
3200 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3201
3202 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3203 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3204 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3205
3206 /* K setting (always 0)
3207 * R16[3:0] (RF PLL freq selection)
3208 */
3209 rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
3210 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3211 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3212
3213 /* D setting (always 0)
3214 * R22[2:0] (D=15, R22[2:0]=<111>)
3215 */
3216 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3217 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3218 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3219
3220 /* Ksd setting
3221 * Ksd: R17<7:0> in rf->rf2
3222 * R18<7:0> in rf->rf3
3223 * R19<1:0> in rf->rf4
3224 */
3225 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3226 rfcsr = rf->rf2;
3227 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3228
3229 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
3230 rfcsr = rf->rf3;
3231 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3232
3233 rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr);
3234 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3235 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3236
3237 /* Default: XO=20MHz , SDM mode */
3238 rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
3239 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3240 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3241
3242 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3243 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3244 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3245
3246 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3247 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3248 rt2x00dev->default_ant.tx_chain_num != 1);
3249 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3250
3251 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3252 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3253 rt2x00dev->default_ant.tx_chain_num != 1);
3254 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3255 rt2x00dev->default_ant.rx_chain_num != 1);
3256 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3257
3258 rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr);
3259 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3260 rt2x00dev->default_ant.tx_chain_num != 1);
3261 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3262
3263 /* RF for DC Cal BW */
3264 if (conf_is_ht40(conf)) {
3265 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3266 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3267 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3268 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3269 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3270 } else {
3271 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3272 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3273 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3274 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3275 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3276 }
3277
3278 if (conf_is_ht40(conf)) {
3279 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3280 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3281 } else {
3282 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3283 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3284 }
3285
3286 rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr);
3287 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3288 conf_is_ht40(conf) && (rf->channel == 11));
3289 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3290
3291 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3292 if (conf_is_ht40(conf)) {
3293 rx_agc_fc = drv_data->rx_calibration_bw40;
3294 tx_agc_fc = drv_data->tx_calibration_bw40;
3295 } else {
3296 rx_agc_fc = drv_data->rx_calibration_bw20;
3297 tx_agc_fc = drv_data->tx_calibration_bw20;
3298 }
3299 rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr);
3300 rfcsr &= (~0x3F);
3301 rfcsr |= rx_agc_fc;
3302 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3303 rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr);
3304 rfcsr &= (~0x3F);
3305 rfcsr |= rx_agc_fc;
3306 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3307 rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr);
3308 rfcsr &= (~0x3F);
3309 rfcsr |= rx_agc_fc;
3310 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3311 rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr);
3312 rfcsr &= (~0x3F);
3313 rfcsr |= rx_agc_fc;
3314 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3315
3316 rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr);
3317 rfcsr &= (~0x3F);
3318 rfcsr |= tx_agc_fc;
3319 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3320 rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr);
3321 rfcsr &= (~0x3F);
3322 rfcsr |= tx_agc_fc;
3323 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3324 rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr);
3325 rfcsr &= (~0x3F);
3326 rfcsr |= tx_agc_fc;
3327 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3328 rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr);
3329 rfcsr &= (~0x3F);
3330 rfcsr |= tx_agc_fc;
3331 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3332 }
3333}
3334
3335static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3336 struct ieee80211_channel *chan,
3337 int power_level) {
3338 u16 eeprom, target_power, max_power;
3339 u32 mac_sys_ctrl, mac_status;
3340 u32 reg;
3341 u8 bbp;
3342 int i;
3343
3344 /* hardware unit is 0.5dBm, limited to 23.5dBm */
3345 power_level *= 2;
3346 if (power_level > 0x2f)
3347 power_level = 0x2f;
3348
3349 max_power = chan->max_power * 2;
3350 if (max_power > 0x2f)
3351 max_power = 0x2f;
3352
3353 rt2800_register_read(rt2x00dev, TX_ALC_CFG_0, &reg);
3354 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3355 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3356 rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3357 rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3358
3359 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3360 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3361 /* init base power by eeprom target power */
3362 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_INIT,
3363 &target_power);
3364 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3365 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3366 }
3367 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3368
3369 rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
3370 rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3371 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3372
3373 /* Save MAC SYS CTRL registers */
3374 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
3375 /* Disable Tx/Rx */
3376 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3377 /* Check MAC Tx/Rx idle */
3378 for (i = 0; i < 10000; i++) {
3379 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG,
3380 &mac_status);
3381 if (mac_status & 0x3)
3382 usleep_range(50, 200);
3383 else
3384 break;
3385 }
3386
3387 if (i == 10000)
3388 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3389
3390 if (chan->center_freq > 2457) {
3391 rt2800_bbp_read(rt2x00dev, 30, &bbp);
3392 bbp = 0x40;
3393 rt2800_bbp_write(rt2x00dev, 30, bbp);
3394 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3395 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3396 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3397 else
3398 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3399 } else {
3400 rt2800_bbp_read(rt2x00dev, 30, &bbp);
3401 bbp = 0x1f;
3402 rt2800_bbp_write(rt2x00dev, 30, bbp);
3403 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3404 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3405 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3406 else
3407 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3408 }
3409 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
2031bada
DG		 3410
3411 rt2800_vco_calibration(rt2x00dev);
41977e86
RY		 3412}
3413
5bc2dd06
SG		 3414static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3415 const unsigned int word,
3416 const u8 value)
3417{
3418 u8 chain, reg;
3419
3420 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3421 rt2800_bbp_read(rt2x00dev, 27, &reg);
3422 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3423 rt2800_bbp_write(rt2x00dev, 27, reg);
3424
3425 rt2800_bbp_write(rt2x00dev, word, value);
3426 }
3427}
3428
8756130b
SG		 3429static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3430{
3431 u8 cal;
3432
415e3f2f 3433 /* TX0 IQ Gain */
8756130b 3434 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3435 if (channel <= 14)
3436 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3437 else if (channel >= 36 && channel <= 64)
3438 cal = rt2x00_eeprom_byte(rt2x00dev,
3439 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3440 else if (channel >= 100 && channel <= 138)
3441 cal = rt2x00_eeprom_byte(rt2x00dev,
3442 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3443 else if (channel >= 140 && channel <= 165)
3444 cal = rt2x00_eeprom_byte(rt2x00dev,
3445 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3446 else
3447 cal = 0;
8756130b
SG		 3448 rt2800_bbp_write(rt2x00dev, 159, cal);
3449
415e3f2f 3450 /* TX0 IQ Phase */
8756130b 3451 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3452 if (channel <= 14)
3453 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3454 else if (channel >= 36 && channel <= 64)
3455 cal = rt2x00_eeprom_byte(rt2x00dev,
3456 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3457 else if (channel >= 100 && channel <= 138)
3458 cal = rt2x00_eeprom_byte(rt2x00dev,
3459 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3460 else if (channel >= 140 && channel <= 165)
3461 cal = rt2x00_eeprom_byte(rt2x00dev,
3462 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3463 else
3464 cal = 0;
8756130b
SG		 3465 rt2800_bbp_write(rt2x00dev, 159, cal);
3466
415e3f2f 3467 /* TX1 IQ Gain */
8756130b 3468 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3469 if (channel <= 14)
3470 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3471 else if (channel >= 36 && channel <= 64)
3472 cal = rt2x00_eeprom_byte(rt2x00dev,
3473 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3474 else if (channel >= 100 && channel <= 138)
3475 cal = rt2x00_eeprom_byte(rt2x00dev,
3476 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3477 else if (channel >= 140 && channel <= 165)
3478 cal = rt2x00_eeprom_byte(rt2x00dev,
3479 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3480 else
3481 cal = 0;
8756130b
SG		 3482 rt2800_bbp_write(rt2x00dev, 159, cal);
3483
415e3f2f 3484 /* TX1 IQ Phase */
8756130b 3485 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3486 if (channel <= 14)
3487 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3488 else if (channel >= 36 && channel <= 64)
3489 cal = rt2x00_eeprom_byte(rt2x00dev,
3490 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3491 else if (channel >= 100 && channel <= 138)
3492 cal = rt2x00_eeprom_byte(rt2x00dev,
3493 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3494 else if (channel >= 140 && channel <= 165)
3495 cal = rt2x00_eeprom_byte(rt2x00dev,
3496 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3497 else
3498 cal = 0;
8756130b
SG		 3499 rt2800_bbp_write(rt2x00dev, 159, cal);
3500
415e3f2f
SG		 3501 /* FIXME: possible RX0, RX1 callibration ? */
3502
8756130b
SG		 3503 /* RF IQ compensation control */
3504 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3505 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3506 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3507
3508 /* RF IQ imbalance compensation control */
3509 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3510 cal = rt2x00_eeprom_byte(rt2x00dev,
3511 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3512 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3513}
3514
97aa03f1
GJ		 3515static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3516 unsigned int channel,
3517 char txpower)
3518{
fc739cfe
GJ		 3519 if (rt2x00_rt(rt2x00dev, RT3593))
3520 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3521
97aa03f1
GJ		 3522 if (channel <= 14)
3523 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3524
3525 if (rt2x00_rt(rt2x00dev, RT3593))
3526 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3527 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3528 else
3529 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3530}
3531
f4450616
BZ		 3532static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3533 struct ieee80211_conf *conf,
3534 struct rf_channel *rf,
3535 struct channel_info *info)
3536{
3537 u32 reg;
41977e86 3538 u32 tx_pin;
a89534ed 3539 u8 bbp, rfcsr;
f4450616 3540
97aa03f1
GJ		 3541 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3542 info->default_power1);
3543 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3544 info->default_power2);
c0a14369
GJ		 3545 if (rt2x00dev->default_ant.tx_chain_num > 2)
3546 info->default_power3 =
3547 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3548 info->default_power3);
46323e11 3549
5aa57015
GW		 3550 switch (rt2x00dev->chip.rf) {
3551 case RF2020:
3552 case RF3020:
3553 case RF3021:
3554 case RF3022:
3555 case RF3320:
06855ef4 3556 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3557 break;
3558 case RF3052:
872834df 3559 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3560 break;
f42b0465
GJ		 3561 case RF3053:
3562 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3563 break;
a89534ed
WH		 3564 case RF3290:
3565 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3566 break;
03839951
DG		 3567 case RF3322:
3568 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3569 break;
3b9b74ba 3570 case RF3070:
98e71f44 3571 case RF5350:
ccf91bd6 3572 case RF5360:
ac0372ab 3573 case RF5362:
5aa57015 3574 case RF5370:
2ed71884 3575 case RF5372:
5aa57015 3576 case RF5390:
cff3d1f0 3577 case RF5392:
adde5882 3578 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3579 break;
8f821098
SG		 3580 case RF5592:
3581 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3582 break;
41977e86
RY		 3583 case RF7620:
3584 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
3585 break;
5aa57015 3586 default:
06855ef4 3587 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3588 }
f4450616 3589
3b9b74ba
SG		 3590 if (rt2x00_rf(rt2x00dev, RF3070) ||
3591 rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3592 rt2x00_rf(rt2x00dev, RF3322) ||
98e71f44 3593 rt2x00_rf(rt2x00dev, RF5350) ||
a89534ed 3594 rt2x00_rf(rt2x00dev, RF5360) ||
ac0372ab 3595 rt2x00_rf(rt2x00dev, RF5362) ||
a89534ed
WH		 3596 rt2x00_rf(rt2x00dev, RF5370) ||
3597 rt2x00_rf(rt2x00dev, RF5372) ||
3598 rt2x00_rf(rt2x00dev, RF5390) ||
3599 rt2x00_rf(rt2x00dev, RF5392)) {
3600 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
e974f3ac
SV		 3601 if (rt2x00_rf(rt2x00dev, RF3322)) {
3602 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
3603 conf_is_ht40(conf));
3604 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
3605 conf_is_ht40(conf));
3606 } else {
3607 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
3608 conf_is_ht40(conf));
3609 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
3610 conf_is_ht40(conf));
3611 }
a89534ed
WH		 3612 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3613
3614 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3615 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3616 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3617 }
3618
f4450616
BZ		 3619 /*
3620 * Change BBP settings
3621 */
dab38e7d 3622
03839951 3623 if (rt2x00_rt(rt2x00dev, RT3352)) {
dab38e7d
DG		 3624 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3625 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3626 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3627
03839951 3628 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3629 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3630 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3631 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
dab38e7d
DG		 3632 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3633 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
f42b0465
GJ		 3634 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3635 if (rf->channel > 14) {
3636 /* Disable CCK Packet detection on 5GHz */
3637 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3638 } else {
3639 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3640 }
3641
3642 if (conf_is_ht40(conf))
3643 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3644 else
3645 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3646
3647 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3648 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3649 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3650 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3651 } else {
3652 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3653 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3654 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3655 rt2800_bbp_write(rt2x00dev, 86, 0);
3656 }
f4450616
BZ		 3657
3658 if (rf->channel <= 14) {
2ed71884 3659 if (!rt2x00_rt(rt2x00dev, RT5390) &&
41977e86
RY		 3660 !rt2x00_rt(rt2x00dev, RT5392) &&
3661 !rt2x00_rt(rt2x00dev, RT6352)) {
c429dfef 3662 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
adde5882
GJ		 3663 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3664 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3665 } else {
f42b0465
GJ		 3666 if (rt2x00_rt(rt2x00dev, RT3593))
3667 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3668 else
3669 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3670 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3671 }
f42b0465
GJ		 3672 if (rt2x00_rt(rt2x00dev, RT3593))
3673 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3674 }
f42b0465 3675
f4450616 3676 } else {
872834df
GW		 3677 if (rt2x00_rt(rt2x00dev, RT3572))
3678 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3679 else if (rt2x00_rt(rt2x00dev, RT3593))
3680 rt2800_bbp_write(rt2x00dev, 82, 0x82);
41977e86 3681 else if (!rt2x00_rt(rt2x00dev, RT6352))
872834df 3682 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3683
f42b0465
GJ		 3684 if (rt2x00_rt(rt2x00dev, RT3593))
3685 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3686
c429dfef 3687 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
f4450616
BZ		 3688 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3689 else
3690 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3691 }
3692
3693 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3694 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3695 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3696 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3697 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3698
872834df
GW		 3699 if (rt2x00_rt(rt2x00dev, RT3572))
3700 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3701
41977e86 3702 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
f4450616 3703
bb16d488
GJ		 3704 switch (rt2x00dev->default_ant.tx_chain_num) {
3705 case 3:
3706 /* Turn on tertiary PAs */
3707 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3708 rf->channel > 14);
3709 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3710 rf->channel <= 14);
3711 /* fall-through */
3712 case 2:
3713 /* Turn on secondary PAs */
65f31b5e
GW		 3714 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3715 rf->channel > 14);
3716 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3717 rf->channel <= 14);
bb16d488
GJ		 3718 /* fall-through */
3719 case 1:
3720 /* Turn on primary PAs */
3721 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3722 rf->channel > 14);
c429dfef 3723 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
bb16d488
GJ		 3724 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3725 else
3726 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3727 rf->channel <= 14);
3728 break;
f4450616
BZ		 3729 }
3730
bb16d488
GJ		 3731 switch (rt2x00dev->default_ant.rx_chain_num) {
3732 case 3:
3733 /* Turn on tertiary LNAs */
3734 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3735 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3736 /* fall-through */
3737 case 2:
3738 /* Turn on secondary LNAs */
f4450616
BZ		 3739 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3740 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3741 /* fall-through */
3742 case 1:
3743 /* Turn on primary LNAs */
3744 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3745 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3746 break;
f4450616
BZ		 3747 }
3748
f4450616
BZ		 3749 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3750 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
41977e86 3751 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
f4450616
BZ		 3752
3753 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3754
733aec6a 3755 if (rt2x00_rt(rt2x00dev, RT3572)) {
872834df
GW		 3756 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3757
733aec6a
GJ		 3758 /* AGC init */
3759 if (rf->channel <= 14)
3760 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3761 else
3762 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3763
3764 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3765 }
3766
f42b0465 3767 if (rt2x00_rt(rt2x00dev, RT3593)) {
60751001 3768 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
f42b0465 3769
60751001
GJ		 3770 /* Band selection */
3771 if (rt2x00_is_usb(rt2x00dev) ||
3772 rt2x00_is_pcie(rt2x00dev)) {
3773 /* GPIO #8 controls all paths */
f42b0465
GJ		 3774 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3775 if (rf->channel <= 14)
3776 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3777 else
3778 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
60751001 3779 }
f42b0465 3780
60751001
GJ		 3781 /* LNA PE control. */
3782 if (rt2x00_is_usb(rt2x00dev)) {
3783 /* GPIO #4 controls PE0 and PE1,
3784 * GPIO #7 controls PE2
3785 */
f42b0465
GJ		 3786 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3787 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3788
f42b0465
GJ		 3789 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3790 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
60751001
GJ		 3791 } else if (rt2x00_is_pcie(rt2x00dev)) {
3792 /* GPIO #4 controls PE0, PE1 and PE2 */
3793 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3794 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
f42b0465
GJ		 3795 }
3796
60751001
GJ		 3797 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3798
f42b0465
GJ		 3799 /* AGC init */
3800 if (rf->channel <= 14)
3801 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3802 else
3803 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3804
3805 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3806
3807 usleep_range(1000, 1500);
3808 }
3809
41977e86 3810 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
225a644a
DG		 3811 reg = 0x10;
3812 if (!conf_is_ht40(conf)) {
3813 if (rt2x00_rt(rt2x00dev, RT6352) &&
3814 rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3815 reg |= 0x5;
3816 } else {
3817 reg |= 0xa;
3818 }
3819 }
6803141b 3820 rt2800_bbp_write(rt2x00dev, 195, 141);
225a644a 3821 rt2800_bbp_write(rt2x00dev, 196, reg);
6803141b 3822
8ba0ebf3 3823 /* AGC init */
225a644a
DG		 3824 if (rt2x00_rt(rt2x00dev, RT6352))
3825 reg = 0x04;
3826 else
3827 reg = rf->channel <= 14 ? 0x1c : 0x24;
3828
3829 reg += 2 * rt2x00dev->lna_gain;
8ba0ebf3
SG		 3830 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3831
8756130b 3832 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3833 }
3834
f4450616
BZ		 3835 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3836 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3837 rt2800_bbp_write(rt2x00dev, 4, bbp);
3838
3839 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3840 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3841 rt2800_bbp_write(rt2x00dev, 3, bbp);
3842
8d0c9b65 3843 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3844 if (conf_is_ht40(conf)) {
3845 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3846 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3847 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3848 } else {
3849 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3850 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3851 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3852 }
3853 }
3854
31369c32 3855 usleep_range(1000, 1500);
977206d7
HS		 3856
3857 /*
3858 * Clear channel statistic counters
3859 */
3860 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3861 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3862 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3863
3864 /*
3865 * Clear update flag
3866 */
98e71f44
SV		 3867 if (rt2x00_rt(rt2x00dev, RT3352) ||
3868 rt2x00_rt(rt2x00dev, RT5350)) {
03839951
DG		 3869 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3870 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3871 rt2800_bbp_write(rt2x00dev, 49, bbp);
3872 }
f4450616
BZ		 3873}
3874
9e33a355
HS		 3875static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3876{
3877 u8 tssi_bounds[9];
3878 u8 current_tssi;
3879 u16 eeprom;
3880 u8 step;
3881 int i;
3882
6e956da2
SG		 3883 /*
3884 * First check if temperature compensation is supported.
3885 */
3886 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3887 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3888 return 0;
3889
9e33a355
HS		 3890 /*
3891 * Read TSSI boundaries for temperature compensation from
3892 * the EEPROM.
3893 *
3894 * Array idx 0 1 2 3 4 5 6 7 8
3895 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3896 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3897 */
57fbcce3 3898 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 3899 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3900 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3901 EEPROM_TSSI_BOUND_BG1_MINUS4);
3902 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3903 EEPROM_TSSI_BOUND_BG1_MINUS3);
3904
3e38d3da 3905 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3906 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3907 EEPROM_TSSI_BOUND_BG2_MINUS2);
3908 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3909 EEPROM_TSSI_BOUND_BG2_MINUS1);
3910
3e38d3da 3911 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3912 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3913 EEPROM_TSSI_BOUND_BG3_REF);
3914 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3915 EEPROM_TSSI_BOUND_BG3_PLUS1);
3916
3e38d3da 3917 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3918 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3919 EEPROM_TSSI_BOUND_BG4_PLUS2);
3920 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3921 EEPROM_TSSI_BOUND_BG4_PLUS3);
3922
3e38d3da 3923 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3924 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3925 EEPROM_TSSI_BOUND_BG5_PLUS4);
3926
3927 step = rt2x00_get_field16(eeprom,
3928 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3929 } else {
3e38d3da 3930 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3931 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3932 EEPROM_TSSI_BOUND_A1_MINUS4);
3933 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3934 EEPROM_TSSI_BOUND_A1_MINUS3);
3935
3e38d3da 3936 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3937 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3938 EEPROM_TSSI_BOUND_A2_MINUS2);
3939 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3940 EEPROM_TSSI_BOUND_A2_MINUS1);
3941
3e38d3da 3942 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3943 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3944 EEPROM_TSSI_BOUND_A3_REF);
3945 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3946 EEPROM_TSSI_BOUND_A3_PLUS1);
3947
3e38d3da 3948 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3949 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3950 EEPROM_TSSI_BOUND_A4_PLUS2);
3951 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3952 EEPROM_TSSI_BOUND_A4_PLUS3);
3953
3e38d3da 3954 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3955 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3956 EEPROM_TSSI_BOUND_A5_PLUS4);
3957
3958 step = rt2x00_get_field16(eeprom,
3959 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3960 }
3961
3962 /*
3963 * Check if temperature compensation is supported.
3964 */
bf7e1abe 3965 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3966 return 0;
3967
3968 /*
3969 * Read current TSSI (BBP 49).
3970 */
3971 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3972
3973 /*
3974 * Compare TSSI value (BBP49) with the compensation boundaries
3975 * from the EEPROM and increase or decrease tx power.
3976 */
3977 for (i = 0; i <= 3; i++) {
3978 if (current_tssi > tssi_bounds[i])
3979 break;
3980 }
3981
3982 if (i == 4) {
3983 for (i = 8; i >= 5; i--) {
3984 if (current_tssi < tssi_bounds[i])
3985 break;
3986 }
3987 }
3988
3989 return (i - 4) * step;
3990}
3991
e90c54b2 3992static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
57fbcce3 3993 enum nl80211_band band)
e90c54b2
RJH		 3994{
3995 u16 eeprom;
3996 u8 comp_en;
3997 u8 comp_type;
75faae8b 3998 int comp_value = 0;
e90c54b2 3999
3e38d3da 4000 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 4001
75faae8b
HS		 4002 /*
4003 * HT40 compensation not required.
4004 */
4005 if (eeprom == 0xffff ||
4006 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 4007 return 0;
4008
57fbcce3 4009 if (band == NL80211_BAND_2GHZ) {
e90c54b2
RJH		 4010 comp_en = rt2x00_get_field16(eeprom,
4011 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4012 if (comp_en) {
4013 comp_type = rt2x00_get_field16(eeprom,
4014 EEPROM_TXPOWER_DELTA_TYPE_2G);
4015 comp_value = rt2x00_get_field16(eeprom,
4016 EEPROM_TXPOWER_DELTA_VALUE_2G);
4017 if (!comp_type)
4018 comp_value = -comp_value;
4019 }
4020 } else {
4021 comp_en = rt2x00_get_field16(eeprom,
4022 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4023 if (comp_en) {
4024 comp_type = rt2x00_get_field16(eeprom,
4025 EEPROM_TXPOWER_DELTA_TYPE_5G);
4026 comp_value = rt2x00_get_field16(eeprom,
4027 EEPROM_TXPOWER_DELTA_VALUE_5G);
4028 if (!comp_type)
4029 comp_value = -comp_value;
4030 }
4031 }
4032
4033 return comp_value;
4034}
4035
1e4cf249
SG		 4036static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4037 int power_level, int max_power)
4038{
4039 int delta;
4040
c429dfef 4041 if (rt2x00_has_cap_power_limit(rt2x00dev))
1e4cf249
SG		 4042 return 0;
4043
4044 /*
4045 * XXX: We don't know the maximum transmit power of our hardware since
4046 * the EEPROM doesn't expose it. We only know that we are calibrated
4047 * to 100% tx power.
4048 *
4049 * Hence, we assume the regulatory limit that cfg80211 calulated for
4050 * the current channel is our maximum and if we are requested to lower
4051 * the value we just reduce our tx power accordingly.
4052 */
4053 delta = power_level - max_power;
4054 return min(delta, 0);
4055}
4056
fa71a160 4057static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
57fbcce3 4058 enum nl80211_band band, int power_level,
fa71a160 4059 u8 txpower, int delta)
e90c54b2 4060{
e90c54b2
RJH		 4061 u16 eeprom;
4062 u8 criterion;
4063 u8 eirp_txpower;
4064 u8 eirp_txpower_criterion;
4065 u8 reg_limit;
e90c54b2 4066
34542ff5
GJ		 4067 if (rt2x00_rt(rt2x00dev, RT3593))
4068 return min_t(u8, txpower, 0xc);
4069
c429dfef 4070 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
e90c54b2
RJH		 4071 /*
4072 * Check if eirp txpower exceed txpower_limit.
4073 * We use OFDM 6M as criterion and its eirp txpower
4074 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4075 * .11b data rate need add additional 4dbm
4076 * when calculating eirp txpower.
4077 */
022138ca
GJ		 4078 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4079 1, &eeprom);
d9bceaeb
SG		 4080 criterion = rt2x00_get_field16(eeprom,
4081 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 4082
3e38d3da 4083 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 4084 &eeprom);
e90c54b2 4085
57fbcce3 4086 if (band == NL80211_BAND_2GHZ)
e90c54b2
RJH		 4087 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4088 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4089 else
4090 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4091 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4092
4093 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 4094 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 4095
4096 reg_limit = (eirp_txpower > power_level) ?
4097 (eirp_txpower - power_level) : 0;
4098 } else
4099 reg_limit = 0;
4100
19f3fa24
SG		 4101 txpower = max(0, txpower + delta - reg_limit);
4102 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 4103}
4104
34542ff5
GJ		 4105
4106enum {
4107 TX_PWR_CFG_0_IDX,
4108 TX_PWR_CFG_1_IDX,
4109 TX_PWR_CFG_2_IDX,
4110 TX_PWR_CFG_3_IDX,
4111 TX_PWR_CFG_4_IDX,
4112 TX_PWR_CFG_5_IDX,
4113 TX_PWR_CFG_6_IDX,
4114 TX_PWR_CFG_7_IDX,
4115 TX_PWR_CFG_8_IDX,
4116 TX_PWR_CFG_9_IDX,
4117 TX_PWR_CFG_0_EXT_IDX,
4118 TX_PWR_CFG_1_EXT_IDX,
4119 TX_PWR_CFG_2_EXT_IDX,
4120 TX_PWR_CFG_3_EXT_IDX,
4121 TX_PWR_CFG_4_EXT_IDX,
4122 TX_PWR_CFG_IDX_COUNT,
4123};
4124
4125static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4126 struct ieee80211_channel *chan,
4127 int power_level)
4128{
4129 u8 txpower;
4130 u16 eeprom;
4131 u32 regs[TX_PWR_CFG_IDX_COUNT];
4132 unsigned int offset;
57fbcce3 4133 enum nl80211_band band = chan->band;
34542ff5
GJ		 4134 int delta;
4135 int i;
4136
4137 memset(regs, '\0', sizeof(regs));
4138
4139 /* TODO: adapt TX power reduction from the rt28xx code */
4140
4141 /* calculate temperature compensation delta */
4142 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4143
57fbcce3 4144 if (band == NL80211_BAND_5GHZ)
34542ff5
GJ		 4145 offset = 16;
4146 else
4147 offset = 0;
4148
4149 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4150 offset += 8;
4151
4152 /* read the next four txpower values */
4153 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4154 offset, &eeprom);
4155
4156 /* CCK 1MBS,2MBS */
4157 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4158 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4159 txpower, delta);
4160 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4161 TX_PWR_CFG_0_CCK1_CH0, txpower);
4162 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4163 TX_PWR_CFG_0_CCK1_CH1, txpower);
4164 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4165 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4166
4167 /* CCK 5.5MBS,11MBS */
4168 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4169 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4170 txpower, delta);
4171 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4172 TX_PWR_CFG_0_CCK5_CH0, txpower);
4173 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4174 TX_PWR_CFG_0_CCK5_CH1, txpower);
4175 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4176 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4177
4178 /* OFDM 6MBS,9MBS */
4179 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4180 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4181 txpower, delta);
4182 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4183 TX_PWR_CFG_0_OFDM6_CH0, txpower);
4184 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4185 TX_PWR_CFG_0_OFDM6_CH1, txpower);
4186 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4187 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4188
4189 /* OFDM 12MBS,18MBS */
4190 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4191 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4192 txpower, delta);
4193 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4194 TX_PWR_CFG_0_OFDM12_CH0, txpower);
4195 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4196 TX_PWR_CFG_0_OFDM12_CH1, txpower);
4197 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4198 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4199
4200 /* read the next four txpower values */
4201 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4202 offset + 1, &eeprom);
4203
4204 /* OFDM 24MBS,36MBS */
4205 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4206 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4207 txpower, delta);
4208 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4209 TX_PWR_CFG_1_OFDM24_CH0, txpower);
4210 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4211 TX_PWR_CFG_1_OFDM24_CH1, txpower);
4212 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4213 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4214
4215 /* OFDM 48MBS */
4216 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4217 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4218 txpower, delta);
4219 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4220 TX_PWR_CFG_1_OFDM48_CH0, txpower);
4221 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4222 TX_PWR_CFG_1_OFDM48_CH1, txpower);
4223 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4224 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4225
4226 /* OFDM 54MBS */
4227 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4228 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4229 txpower, delta);
4230 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4231 TX_PWR_CFG_7_OFDM54_CH0, txpower);
4232 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4233 TX_PWR_CFG_7_OFDM54_CH1, txpower);
4234 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4235 TX_PWR_CFG_7_OFDM54_CH2, txpower);
4236
4237 /* read the next four txpower values */
4238 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4239 offset + 2, &eeprom);
4240
4241 /* MCS 0,1 */
4242 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4243 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4244 txpower, delta);
4245 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4246 TX_PWR_CFG_1_MCS0_CH0, txpower);
4247 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4248 TX_PWR_CFG_1_MCS0_CH1, txpower);
4249 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4250 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4251
4252 /* MCS 2,3 */
4253 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4254 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4255 txpower, delta);
4256 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4257 TX_PWR_CFG_1_MCS2_CH0, txpower);
4258 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4259 TX_PWR_CFG_1_MCS2_CH1, txpower);
4260 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4261 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4262
4263 /* MCS 4,5 */
4264 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4265 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4266 txpower, delta);
4267 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4268 TX_PWR_CFG_2_MCS4_CH0, txpower);
4269 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4270 TX_PWR_CFG_2_MCS4_CH1, txpower);
4271 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4272 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4273
4274 /* MCS 6 */
4275 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4276 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4277 txpower, delta);
4278 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4279 TX_PWR_CFG_2_MCS6_CH0, txpower);
4280 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4281 TX_PWR_CFG_2_MCS6_CH1, txpower);
4282 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4283 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4284
4285 /* read the next four txpower values */
4286 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4287 offset + 3, &eeprom);
4288
4289 /* MCS 7 */
4290 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4291 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4292 txpower, delta);
4293 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4294 TX_PWR_CFG_7_MCS7_CH0, txpower);
4295 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4296 TX_PWR_CFG_7_MCS7_CH1, txpower);
4297 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4298 TX_PWR_CFG_7_MCS7_CH2, txpower);
4299
4300 /* MCS 8,9 */
4301 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4302 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4303 txpower, delta);
4304 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4305 TX_PWR_CFG_2_MCS8_CH0, txpower);
4306 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4307 TX_PWR_CFG_2_MCS8_CH1, txpower);
4308 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4309 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4310
4311 /* MCS 10,11 */
4312 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4313 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4314 txpower, delta);
4315 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4316 TX_PWR_CFG_2_MCS10_CH0, txpower);
4317 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4318 TX_PWR_CFG_2_MCS10_CH1, txpower);
4319 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4320 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4321
4322 /* MCS 12,13 */
4323 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4324 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4325 txpower, delta);
4326 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4327 TX_PWR_CFG_3_MCS12_CH0, txpower);
4328 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4329 TX_PWR_CFG_3_MCS12_CH1, txpower);
4330 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4331 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4332
4333 /* read the next four txpower values */
4334 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4335 offset + 4, &eeprom);
4336
4337 /* MCS 14 */
4338 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4339 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4340 txpower, delta);
4341 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4342 TX_PWR_CFG_3_MCS14_CH0, txpower);
4343 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4344 TX_PWR_CFG_3_MCS14_CH1, txpower);
4345 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4346 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4347
4348 /* MCS 15 */
4349 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4350 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4351 txpower, delta);
4352 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4353 TX_PWR_CFG_8_MCS15_CH0, txpower);
4354 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4355 TX_PWR_CFG_8_MCS15_CH1, txpower);
4356 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4357 TX_PWR_CFG_8_MCS15_CH2, txpower);
4358
4359 /* MCS 16,17 */
4360 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4361 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4362 txpower, delta);
4363 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4364 TX_PWR_CFG_5_MCS16_CH0, txpower);
4365 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4366 TX_PWR_CFG_5_MCS16_CH1, txpower);
4367 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4368 TX_PWR_CFG_5_MCS16_CH2, txpower);
4369
4370 /* MCS 18,19 */
4371 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4372 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4373 txpower, delta);
4374 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4375 TX_PWR_CFG_5_MCS18_CH0, txpower);
4376 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4377 TX_PWR_CFG_5_MCS18_CH1, txpower);
4378 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4379 TX_PWR_CFG_5_MCS18_CH2, txpower);
4380
4381 /* read the next four txpower values */
4382 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4383 offset + 5, &eeprom);
4384
4385 /* MCS 20,21 */
4386 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4387 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4388 txpower, delta);
4389 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4390 TX_PWR_CFG_6_MCS20_CH0, txpower);
4391 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4392 TX_PWR_CFG_6_MCS20_CH1, txpower);
4393 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4394 TX_PWR_CFG_6_MCS20_CH2, txpower);
4395
4396 /* MCS 22 */
4397 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4398 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4399 txpower, delta);
4400 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4401 TX_PWR_CFG_6_MCS22_CH0, txpower);
4402 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4403 TX_PWR_CFG_6_MCS22_CH1, txpower);
4404 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4405 TX_PWR_CFG_6_MCS22_CH2, txpower);
4406
4407 /* MCS 23 */
4408 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4409 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4410 txpower, delta);
4411 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4412 TX_PWR_CFG_8_MCS23_CH0, txpower);
4413 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4414 TX_PWR_CFG_8_MCS23_CH1, txpower);
4415 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4416 TX_PWR_CFG_8_MCS23_CH2, txpower);
4417
4418 /* read the next four txpower values */
4419 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4420 offset + 6, &eeprom);
4421
4422 /* STBC, MCS 0,1 */
4423 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4424 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4425 txpower, delta);
4426 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4427 TX_PWR_CFG_3_STBC0_CH0, txpower);
4428 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4429 TX_PWR_CFG_3_STBC0_CH1, txpower);
4430 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4431 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4432
4433 /* STBC, MCS 2,3 */
4434 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4435 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4436 txpower, delta);
4437 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4438 TX_PWR_CFG_3_STBC2_CH0, txpower);
4439 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4440 TX_PWR_CFG_3_STBC2_CH1, txpower);
4441 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4442 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4443
4444 /* STBC, MCS 4,5 */
4445 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4446 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4447 txpower, delta);
4448 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4449 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4450 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4451 txpower);
4452
4453 /* STBC, MCS 6 */
4454 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4455 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4456 txpower, delta);
4457 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4458 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4459 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4460 txpower);
4461
4462 /* read the next four txpower values */
4463 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4464 offset + 7, &eeprom);
4465
4466 /* STBC, MCS 7 */
4467 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4468 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4469 txpower, delta);
4470 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4471 TX_PWR_CFG_9_STBC7_CH0, txpower);
4472 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4473 TX_PWR_CFG_9_STBC7_CH1, txpower);
4474 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4475 TX_PWR_CFG_9_STBC7_CH2, txpower);
4476
4477 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4478 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4479 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4480 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4481 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4482 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4483 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4484 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4485 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4486 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4487
4488 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4489 regs[TX_PWR_CFG_0_EXT_IDX]);
4490 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4491 regs[TX_PWR_CFG_1_EXT_IDX]);
4492 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4493 regs[TX_PWR_CFG_2_EXT_IDX]);
4494 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4495 regs[TX_PWR_CFG_3_EXT_IDX]);
4496 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4497 regs[TX_PWR_CFG_4_EXT_IDX]);
4498
4499 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4500 rt2x00_dbg(rt2x00dev,
4501 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
57fbcce3 4502 (band == NL80211_BAND_5GHZ) ? '5' : '2',
34542ff5
GJ		 4503 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4504 '4' : '2',
4505 (i > TX_PWR_CFG_9_IDX) ?
4506 (i - TX_PWR_CFG_9_IDX - 1) : i,
4507 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4508 (unsigned long) regs[i]);
4509}
4510
41977e86
RY		 4511static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
4512 struct ieee80211_channel *chan,
4513 int power_level)
4514{
4515 u32 reg, pwreg;
4516 u16 eeprom;
4517 u32 data, gdata;
4518 u8 t, i;
4519 enum nl80211_band band = chan->band;
4520 int delta;
4521
4522 /* Warn user if bw_comp is set in EEPROM */
4523 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4524
4525 if (delta)
4526 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
4527 delta);
4528
4529 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
4530 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
4531 * driver does as well, though it looks kinda wrong.
4532 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
4533 * the hardware has a problem handling 0x20, and as the code initially
4534 * used a fixed offset between HT20 and HT40 rates they had to work-
4535 * around that issue and most likely just forgot about it later on.
4536 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
4537 * however, the corresponding EEPROM value is not respected by the
4538 * vendor driver, so maybe this is rather being taken care of the
4539 * TXALC and the driver doesn't need to handle it...?
4540 * Though this is all very awkward, just do as they did, as that's what
4541 * board vendors expected when they populated the EEPROM...
4542 */
4543 for (i = 0; i < 5; i++) {
4544 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4545 i * 2, &eeprom);
4546
4547 data = eeprom;
4548
4549 t = eeprom & 0x3f;
4550 if (t == 32)
4551 t++;
4552
4553 gdata = t;
4554
4555 t = (eeprom & 0x3f00) >> 8;
4556 if (t == 32)
4557 t++;
4558
4559 gdata |= (t << 8);
4560
4561 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4562 (i * 2) + 1, &eeprom);
4563
4564 t = eeprom & 0x3f;
4565 if (t == 32)
4566 t++;
4567
4568 gdata |= (t << 16);
4569
4570 t = (eeprom & 0x3f00) >> 8;
4571 if (t == 32)
4572 t++;
4573
4574 gdata |= (t << 24);
4575 data |= (eeprom << 16);
4576
4577 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
4578 /* HT20 */
4579 if (data != 0xffffffff)
4580 rt2800_register_write(rt2x00dev,
4581 TX_PWR_CFG_0 + (i * 4),
4582 data);
4583 } else {
4584 /* HT40 */
4585 if (gdata != 0xffffffff)
4586 rt2800_register_write(rt2x00dev,
4587 TX_PWR_CFG_0 + (i * 4),
4588 gdata);
4589 }
4590 }
4591
4592 /* Aparently Ralink ran out of space in the BYRATE calibration section
4593 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
4594 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
4595 * power-offsets more space would be needed. Ralink decided to keep the
4596 * EEPROM layout untouched and rather have some shared values covering
4597 * multiple bitrates.
4598 * Populate the registers not covered by the EEPROM in the same way the
4599 * vendor driver does.
4600 */
4601
4602 /* For OFDM 54MBS use value from OFDM 48MBS */
4603 pwreg = 0;
4604 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
4605 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
4606 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
4607
4608 /* For MCS 7 use value from MCS 6 */
4609 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
4610 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
4611 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
4612 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
4613
4614 /* For MCS 15 use value from MCS 14 */
4615 pwreg = 0;
4616 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
4617 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
4618 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
4619 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
4620
4621 /* For STBC MCS 7 use value from STBC MCS 6 */
4622 pwreg = 0;
4623 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
4624 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
4625 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
4626 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
4627
4628 rt2800_config_alc(rt2x00dev, chan, power_level);
4629
4630 /* TODO: temperature compensation code! */
4631}
4632
7a66205a
SG		 4633/*
4634 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4635 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4636 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4637 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4638 * Reference per rate transmit power values are located in the EEPROM at
4639 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4640 * current conditions (i.e. band, bandwidth, temperature, user settings).
4641 */
34542ff5
GJ		 4642static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4643 struct ieee80211_channel *chan,
4644 int power_level)
f4450616 4645{
cee2c731 4646 u8 txpower, r1;
5e846004 4647 u16 eeprom;
cee2c731
SG		 4648 u32 reg, offset;
4649 int i, is_rate_b, delta, power_ctrl;
57fbcce3 4650 enum nl80211_band band = chan->band;
2af242e1
HS		 4651
4652 /*
7a66205a
SG		 4653 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4654 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4655 */
4656 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4657
9e33a355 4658 /*
7a66205a
SG		 4659 * Calculate temperature compensation. Depends on measurement of current
4660 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4661 * to temperature or maybe other factors) is smaller or bigger than
4662 * expected. We adjust it, based on TSSI reference and boundaries values
4663 * provided in EEPROM.
9e33a355 4664 */
87dd2d76
SG		 4665 switch (rt2x00dev->chip.rt) {
4666 case RT2860:
4667 case RT2872:
4668 case RT2883:
4669 case RT3070:
4670 case RT3071:
4671 case RT3090:
4672 case RT3572:
4673 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4674 break;
4675 default:
4676 /* TODO: temperature compensation code for other chips. */
4677 break;
4678 }
f4450616 4679
1e4cf249 4680 /*
7a66205a
SG		 4681 * Decrease power according to user settings, on devices with unknown
4682 * maximum tx power. For other devices we take user power_level into
4683 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4684 */
4685 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4686 chan->max_power);
4687
5e846004 4688 /*
cee2c731
SG		 4689 * BBP_R1 controls TX power for all rates, it allow to set the following
4690 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4691 *
4692 * TODO: we do not use +6 dBm option to do not increase power beyond
4693 * regulatory limit, however this could be utilized for devices with
4694 * CAPABILITY_POWER_LIMIT.
8c8d2017 4695 */
87dd2d76
SG		 4696 if (delta <= -12) {
4697 power_ctrl = 2;
4698 delta += 12;
4699 } else if (delta <= -6) {
4700 power_ctrl = 1;
4701 delta += 6;
4702 } else {
4703 power_ctrl = 0;
cee2c731 4704 }
87dd2d76
SG		 4705 rt2800_bbp_read(rt2x00dev, 1, &r1);
4706 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4707 rt2800_bbp_write(rt2x00dev, 1, r1);
8c8d2017 4708
5e846004
HS		 4709 offset = TX_PWR_CFG_0;
4710
4711 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4712 /* just to be safe */
4713 if (offset > TX_PWR_CFG_4)
4714 break;
4715
4716 rt2800_register_read(rt2x00dev, offset, &reg);
4717
4718 /* read the next four txpower values */
022138ca
GJ		 4719 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4720 i, &eeprom);
5e846004 4721
e90c54b2
RJH		 4722 is_rate_b = i ? 0 : 1;
4723 /*
4724 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4725 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4726 * TX_PWR_CFG_4: unknown
4727 */
5e846004
HS		 4728 txpower = rt2x00_get_field16(eeprom,
4729 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4730 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4731 power_level, txpower, delta);
e90c54b2 4732 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4733
e90c54b2
RJH		 4734 /*
4735 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4736 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4737 * TX_PWR_CFG_4: unknown
4738 */
5e846004
HS		 4739 txpower = rt2x00_get_field16(eeprom,
4740 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4741 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4742 power_level, txpower, delta);
e90c54b2 4743 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4744
e90c54b2
RJH		 4745 /*
4746 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4747 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4748 * TX_PWR_CFG_4: unknown
4749 */
5e846004
HS		 4750 txpower = rt2x00_get_field16(eeprom,
4751 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4752 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4753 power_level, txpower, delta);
e90c54b2 4754 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4755
e90c54b2
RJH		 4756 /*
4757 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4758 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4759 * TX_PWR_CFG_4: unknown
4760 */
5e846004
HS		 4761 txpower = rt2x00_get_field16(eeprom,
4762 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4763 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4764 power_level, txpower, delta);
e90c54b2 4765 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4766
4767 /* read the next four txpower values */
022138ca
GJ		 4768 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4769 i + 1, &eeprom);
5e846004 4770
e90c54b2
RJH		 4771 is_rate_b = 0;
4772 /*
4773 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4774 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4775 * TX_PWR_CFG_4: unknown
4776 */
5e846004
HS		 4777 txpower = rt2x00_get_field16(eeprom,
4778 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4779 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4780 power_level, txpower, delta);
e90c54b2 4781 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4782
e90c54b2
RJH		 4783 /*
4784 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4785 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4786 * TX_PWR_CFG_4: unknown
4787 */
5e846004
HS		 4788 txpower = rt2x00_get_field16(eeprom,
4789 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4790 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4791 power_level, txpower, delta);
e90c54b2 4792 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4793
e90c54b2
RJH		 4794 /*
4795 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4796 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4797 * TX_PWR_CFG_4: unknown
4798 */
5e846004
HS		 4799 txpower = rt2x00_get_field16(eeprom,
4800 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4801 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4802 power_level, txpower, delta);
e90c54b2 4803 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4804
e90c54b2
RJH		 4805 /*
4806 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4807 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4808 * TX_PWR_CFG_4: unknown
4809 */
5e846004
HS		 4810 txpower = rt2x00_get_field16(eeprom,
4811 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4812 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4813 power_level, txpower, delta);
e90c54b2 4814 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4815
4816 rt2800_register_write(rt2x00dev, offset, reg);
4817
4818 /* next TX_PWR_CFG register */
4819 offset += 4;
4820 }
f4450616
BZ		 4821}
4822
34542ff5
GJ		 4823static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4824 struct ieee80211_channel *chan,
4825 int power_level)
4826{
4827 if (rt2x00_rt(rt2x00dev, RT3593))
4828 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
41977e86
RY		 4829 else if (rt2x00_rt(rt2x00dev, RT6352))
4830 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
34542ff5
GJ		 4831 else
4832 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4833}
4834
9e33a355
HS		 4835void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4836{
675a0b04 4837 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4838 rt2x00dev->tx_power);
4839}
4840EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4841
2e9c43dd
JL		 4842void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4843{
4844 u32 tx_pin;
4845 u8 rfcsr;
41977e86 4846 unsigned long min_sleep = 0;
2e9c43dd
JL		 4847
4848 /*
4849 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4850 * designed to be controlled in oscillation frequency by a voltage
4851 * input. Maybe the temperature will affect the frequency of
4852 * oscillation to be shifted. The VCO calibration will be called
4853 * periodically to adjust the frequency to be precision.
4854 */
4855
4856 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4857 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4858 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4859
4860 switch (rt2x00dev->chip.rf) {
4861 case RF2020:
4862 case RF3020:
4863 case RF3021:
4864 case RF3022:
4865 case RF3320:
4866 case RF3052:
4867 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4868 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4869 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4870 break;
1095df07 4871 case RF3053:
3b9b74ba 4872 case RF3070:
a89534ed 4873 case RF3290:
98e71f44 4874 case RF5350:
ccf91bd6 4875 case RF5360:
ac0372ab 4876 case RF5362:
2e9c43dd
JL		 4877 case RF5370:
4878 case RF5372:
4879 case RF5390:
cff3d1f0 4880 case RF5392:
24d42ef3 4881 case RF5592:
2e9c43dd 4882 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 4883 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd 4884 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
41977e86
RY		 4885 min_sleep = 1000;
4886 break;
4887 case RF7620:
4888 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
4889 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
4890 rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
4891 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
4892 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
4893 min_sleep = 2000;
2e9c43dd
JL		 4894 break;
4895 default:
bc007705
SG		 4896 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
4897 rt2x00dev->chip.rf);
2e9c43dd
JL		 4898 return;
4899 }
4900
41977e86
RY		 4901 if (min_sleep > 0)
4902 usleep_range(min_sleep, min_sleep * 2);
2e9c43dd
JL		 4903
4904 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4905 if (rt2x00dev->rf_channel <= 14) {
4906 switch (rt2x00dev->default_ant.tx_chain_num) {
4907 case 3:
4908 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4909 /* fall through */
4910 case 2:
4911 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4912 /* fall through */
4913 case 1:
4914 default:
4915 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4916 break;
4917 }
4918 } else {
4919 switch (rt2x00dev->default_ant.tx_chain_num) {
4920 case 3:
4921 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4922 /* fall through */
4923 case 2:
4924 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4925 /* fall through */
4926 case 1:
4927 default:
4928 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4929 break;
4930 }
4931 }
4932 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4933
41977e86 4934 if (rt2x00_rt(rt2x00dev, RT6352)) {
4bd96b5d 4935 if (rt2x00dev->default_ant.rx_chain_num == 1) {
41977e86
RY		 4936 rt2800_bbp_write(rt2x00dev, 91, 0x07);
4937 rt2800_bbp_write(rt2x00dev, 95, 0x1A);
4938 rt2800_bbp_write(rt2x00dev, 195, 128);
4939 rt2800_bbp_write(rt2x00dev, 196, 0xA0);
4940 rt2800_bbp_write(rt2x00dev, 195, 170);
4941 rt2800_bbp_write(rt2x00dev, 196, 0x12);
4942 rt2800_bbp_write(rt2x00dev, 195, 171);
4943 rt2800_bbp_write(rt2x00dev, 196, 0x10);
4944 } else {
4945 rt2800_bbp_write(rt2x00dev, 91, 0x06);
4946 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
4947 rt2800_bbp_write(rt2x00dev, 195, 128);
4948 rt2800_bbp_write(rt2x00dev, 196, 0xE0);
4949 rt2800_bbp_write(rt2x00dev, 195, 170);
4950 rt2800_bbp_write(rt2x00dev, 196, 0x30);
4951 rt2800_bbp_write(rt2x00dev, 195, 171);
4952 rt2800_bbp_write(rt2x00dev, 196, 0x30);
4953 }
4954
4955 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4bd96b5d
TP		 4956 rt2800_bbp_write(rt2x00dev, 75, 0x68);
4957 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
41977e86
RY		 4958 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
4959 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
4960 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
4961 }
4962
4963 /* On 11A, We should delay and wait RF/BBP to be stable
4964 * and the appropriate time should be 1000 micro seconds
4965 * 2005/06/05 - On 11G, we also need this delay time.
4966 * Otherwise it's difficult to pass the WHQL.
4967 */
4968 usleep_range(1000, 1500);
4969 }
2e9c43dd
JL		 4970}
4971EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4972
f4450616
BZ		 4973static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4974 struct rt2x00lib_conf *libconf)
4975{
4976 u32 reg;
4977
4978 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4979 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4980 libconf->conf->short_frame_max_tx_count);
4981 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4982 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4983 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4984}
4985
4986static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4987 struct rt2x00lib_conf *libconf)
4988{
4989 enum dev_state state =
4990 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4991 STATE_SLEEP : STATE_AWAKE;
4992 u32 reg;
4993
4994 if (state == STATE_SLEEP) {
4995 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4996
4997 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4998 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4999 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5000 libconf->conf->listen_interval - 1);
5001 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5002 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5003
5004 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5005 } else {
f4450616
BZ		 5006 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
5007 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5008 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5009 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5010 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 5011
5012 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 5013 }
5014}
5015
5016void rt2800_config(struct rt2x00_dev *rt2x00dev,
5017 struct rt2x00lib_conf *libconf,
5018 const unsigned int flags)
5019{
5020 /* Always recalculate LNA gain before changing configuration */
5021 rt2800_config_lna_gain(rt2x00dev, libconf);
5022
e90c54b2 5023 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 5024 rt2800_config_channel(rt2x00dev, libconf->conf,
5025 &libconf->rf, &libconf->channel);
675a0b04 5026 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 5027 libconf->conf->power_level);
e90c54b2 5028 }
f4450616 5029 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 5030 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 5031 libconf->conf->power_level);
f4450616
BZ		 5032 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5033 rt2800_config_retry_limit(rt2x00dev, libconf);
5034 if (flags & IEEE80211_CONF_CHANGE_PS)
5035 rt2800_config_ps(rt2x00dev, libconf);
5036}
5037EXPORT_SYMBOL_GPL(rt2800_config);
5038
5039/*
5040 * Link tuning
5041 */
5042void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5043{
5044 u32 reg;
5045
5046 /*
5047 * Update FCS error count from register.
5048 */
5049 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
5050 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5051}
5052EXPORT_SYMBOL_GPL(rt2800_link_stats);
5053
5054static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5055{
8c6728b0
GW		 5056 u8 vgc;
5057
57fbcce3 5058 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
d5385bfc 5059 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 5060 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 5061 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 5062 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 5063 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 5064 rt2x00_rt(rt2x00dev, RT3572) ||
0ffd2a9a 5065 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 5066 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e 5067 rt2x00_rt(rt2x00dev, RT5392) ||
41977e86
RY		 5068 rt2x00_rt(rt2x00dev, RT5592) ||
5069 rt2x00_rt(rt2x00dev, RT6352))
8c6728b0
GW		 5070 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5071 else
5072 vgc = 0x2e + rt2x00dev->lna_gain;
5073 } else { /* 5GHZ band */
733aec6a 5074 if (rt2x00_rt(rt2x00dev, RT3593))
0ffd2a9a 5075 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 5076 else if (rt2x00_rt(rt2x00dev, RT5592))
5077 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 5078 else {
5079 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5080 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5081 else
5082 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5083 }
f4450616
BZ		 5084 }
5085
8c6728b0 5086 return vgc;
f4450616
BZ		 5087}
5088
5089static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5090 struct link_qual *qual, u8 vgc_level)
5091{
5092 if (qual->vgc_level != vgc_level) {
271f1a4d
GJ		 5093 if (rt2x00_rt(rt2x00dev, RT3572) ||
5094 rt2x00_rt(rt2x00dev, RT3593)) {
5095 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5096 vgc_level);
5097 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
3d81535e
SG		 5098 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5099 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
271f1a4d 5100 } else {
3d81535e 5101 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
271f1a4d
GJ		 5102 }
5103
f4450616
BZ		 5104 qual->vgc_level = vgc_level;
5105 qual->vgc_level_reg = vgc_level;
5106 }
5107}
5108
5109void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5110{
5111 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5112}
5113EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5114
5115void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5116 const u32 count)
5117{
3d81535e
SG		 5118 u8 vgc;
5119
8d0c9b65 5120 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 5121 return;
e25aa82a
GJ		 5122
5123 /* When RSSI is better than a certain threshold, increase VGC
5124 * with a chip specific value in order to improve the balance
5125 * between sensibility and noise isolation.
f4450616 5126 */
3d81535e
SG		 5127
5128 vgc = rt2800_get_default_vgc(rt2x00dev);
5129
e25aa82a
GJ		 5130 switch (rt2x00dev->chip.rt) {
5131 case RT3572:
5132 case RT3593:
5133 if (qual->rssi > -65) {
57fbcce3 5134 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
e25aa82a
GJ		 5135 vgc += 0x20;
5136 else
5137 vgc += 0x10;
5138 }
5139 break;
5140
5141 case RT5592:
0beb1bbf
GJ		 5142 if (qual->rssi > -65)
5143 vgc += 0x20;
e25aa82a
GJ		 5144 break;
5145
5146 default:
0beb1bbf
GJ		 5147 if (qual->rssi > -80)
5148 vgc += 0x10;
e25aa82a 5149 break;
0beb1bbf 5150 }
3d81535e
SG		 5151
5152 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 5153}
5154EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 5155
5156/*
5157 * Initialization functions.
5158 */
b9a07ae9 5159static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541 5160{
8f03a7c6 5161 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
fcf51541 5162 u32 reg;
d5385bfc 5163 u16 eeprom;
fcf51541 5164 unsigned int i;
e3a896b9 5165 int ret;
fcf51541 5166
f7b395e9 5167 rt2800_disable_wpdma(rt2x00dev);
a9dce149 5168
e3a896b9
GW		 5169 ret = rt2800_drv_init_registers(rt2x00dev);
5170 if (ret)
5171 return ret;
fcf51541 5172
fcf51541
BZ		 5173 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5174 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5175
5176 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5177
5178 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 5179 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 5180 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5181 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5182 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5183 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5184 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5185 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5186
a9dce149
GW		 5187 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5188
5189 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
5190 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5191 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5192 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5193
a89534ed
WH		 5194 if (rt2x00_rt(rt2x00dev, RT3290)) {
5195 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
5196 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5197 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5198 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5199 }
5200
5201 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
5202 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5203 rt2x00_set_field32(&reg, LDO0_EN, 1);
5204 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5205 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5206 }
5207
5208 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
5209 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5210 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5211 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5212 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5213
5214 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
5215 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5216 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5217
5218 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
5219 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5220 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5221 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5222 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5223 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5224
5225 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
5226 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5227 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5228 }
5229
64522957 5230 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 5231 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 5232 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 5233 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 5234
5235 if (rt2x00_rt(rt2x00dev, RT3290))
5236 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5237 0x00000404);
5238 else
5239 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5240 0x00000400);
5241
fcf51541 5242 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 5243 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 5244 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5245 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 5246 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5247 &eeprom);
38c8a566 5248 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 5249 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5250 0x0000002c);
5251 else
5252 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5253 0x0000000f);
5254 } else {
5255 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5256 }
d5385bfc 5257 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 5258 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 5259
5260 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5261 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5262 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5263 } else {
5264 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5265 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5266 }
c295a81d
HS		 5267 } else if (rt2800_is_305x_soc(rt2x00dev)) {
5268 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5269 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 5270 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 5271 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5272 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5273 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5274 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 5275 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5276 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5277 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 5278 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5279 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5280 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5281 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5282 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5283 &eeprom);
5284 if (rt2x00_get_field16(eeprom,
5285 EEPROM_NIC_CONF1_DAC_TEST))
5286 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5287 0x0000001f);
5288 else
5289 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5290 0x0000000f);
5291 } else {
5292 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5293 0x00000000);
5294 }
2ed71884 5295 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
41977e86
RY		 5296 rt2x00_rt(rt2x00dev, RT5392) ||
5297 rt2x00_rt(rt2x00dev, RT6352)) {
adde5882
GJ		 5298 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5299 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5300 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
231aeca1
SG		 5301 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5302 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5303 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5304 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
98e71f44
SV		 5305 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5306 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
41977e86
RY		 5307 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5308 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5309 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5310 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5311 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5312 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5313 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
5314 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5315 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5316 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5317 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5318 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5319 0x3630363A);
5320 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5321 0x3630363A);
5322 rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
5323 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5324 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
fcf51541
BZ		 5325 } else {
5326 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5327 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5328 }
5329
5330 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
5331 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5332 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5333 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5334 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5335 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5336 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5337 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5338 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5339 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5340
5341 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
5342 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 5343 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 5344 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5345 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5346
5347 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
5348 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
66ecec02
SG		 5349 if (rt2x00_is_usb(rt2x00dev)) {
5350 drv_data->max_psdu = 3;
5351 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5352 rt2x00_rt(rt2x00dev, RT2883) ||
5353 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
8f03a7c6 5354 drv_data->max_psdu = 2;
8f03a7c6
SG		 5355 } else {
5356 drv_data->max_psdu = 1;
8f03a7c6 5357 }
66ecec02 5358 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
a51b8969
SG		 5359 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5360 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
fcf51541
BZ		 5361 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5362
a9dce149
GW		 5363 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
5364 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5365 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5366 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5367 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5368 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5369 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5370 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5371 rt2800_register_write(rt2x00dev, LED_CFG, reg);
5372
fcf51541
BZ		 5373 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5374
a9dce149 5375 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
01d97ef4
SG		 5376 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5377 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
a9dce149
GW		 5378 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5379 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5380 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5381 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5382 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5383
fcf51541
BZ		 5384 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
5385 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 5386 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
be82de9d 5387 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
fcf51541 5388 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
be82de9d 5389 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
fcf51541
BZ		 5390 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5391 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5392 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5393
5394 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 5395 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 5396 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 5397 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 5398 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5399 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5400 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 5401 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 5402 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 5403 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5404 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 5405 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5406
5407 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 5408 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 5409 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 5410 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 5411 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5412 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5413 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 5414 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 5415 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 5416 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5417 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 5418 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5419
5420 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5421 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
8d79b007 5422 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 5423 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 5424 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 5425 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5426 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5427 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5428 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5429 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 5430 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 5431 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5432
5433 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5434 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
8d79b007 5435 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 5436 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 5437 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 5438 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5439 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5440 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5441 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5442 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 5443 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 5444 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5445
5446 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5447 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
8d79b007 5448 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 5449 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 5450 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 5451 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5452 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5453 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5454 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5455 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 5456 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 5457 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5458
5459 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5460 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
8d79b007 5461 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 5462 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 5463 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 5464 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5465 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5466 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5467 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5468 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 5469 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 5470 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5471
cea90e55 5472 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 5473 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5474
5475 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5476 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5477 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5478 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5479 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5480 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5481 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5482 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5483 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5484 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5485 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5486 }
5487
961621ab
HS		 5488 /*
5489 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
5490 * although it is reserved.
5491 */
5492 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
5493 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
5494 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
5495 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
5496 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
5497 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
5498 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
5499 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
5500 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
5501 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
5502 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
5503 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
5504
7641328d
SG		 5505 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
5506 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 5507
5508 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
e4019e7f 5509 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
fcf51541
BZ		 5510 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
5511 IEEE80211_MAX_RTS_THRESHOLD);
e4019e7f 5512 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
fcf51541
BZ		 5513 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5514
5515 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 5516
a21c2ab4
HS		 5517 /*
5518 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
5519 * time should be set to 16. However, the original Ralink driver uses
5520 * 16 for both and indeed using a value of 10 for CCK SIFS results in
5521 * connection problems with 11g + CTS protection. Hence, use the same
5522 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
5523 */
a9dce149 5524 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 5525 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
5526 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 5527 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
5528 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
5529 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
5530 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
5531
fcf51541
BZ		 5532 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
5533
5534 /*
5535 * ASIC will keep garbage value after boot, clear encryption keys.
5536 */
5537 for (i = 0; i < 4; i++)
5538 rt2800_register_write(rt2x00dev,
5539 SHARED_KEY_MODE_ENTRY(i), 0);
5540
5541 for (i = 0; i < 256; i++) {
d7d259d3
HS		 5542 rt2800_config_wcid(rt2x00dev, NULL, i);
5543 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 5544 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
5545 }
5546
5547 /*
5548 * Clear all beacons
fcf51541 5549 */
77f7c0f3
GJ		 5550 for (i = 0; i < 8; i++)
5551 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 5552
cea90e55 5553 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 5554 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
5555 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
5556 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 5557 } else if (rt2x00_is_pcie(rt2x00dev)) {
5558 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
5559 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
5560 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 5561 }
5562
5563 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
5564 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
5565 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
5566 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
5567 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
5568 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
5569 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
5570 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
5571 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
5572 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
5573
5574 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
5575 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
5576 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
5577 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
5578 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
5579 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
5580 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
5581 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
5582 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
5583 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
5584
5585 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
5586 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
5587 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
5588 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
5589 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
5590 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
5591 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
5592 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
5593 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
5594 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
5595
5596 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
5597 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
5598 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
5599 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
5600 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
5601 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
5602
47ee3eb1
HS		 5603 /*
5604 * Do not force the BA window size, we use the TXWI to set it
5605 */
5606 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
5607 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
5608 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
5609 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
5610
fcf51541
BZ		 5611 /*
5612 * We must clear the error counters.
5613 * These registers are cleared on read,
5614 * so we may pass a useless variable to store the value.
5615 */
5616 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
5617 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
5618 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
5619 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
5620 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
5621 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
5622
9f926fb5
HS		 5623 /*
5624 * Setup leadtime for pre tbtt interrupt to 6ms
5625 */
5626 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
5627 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
5628 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
5629
977206d7
HS		 5630 /*
5631 * Set up channel statistics timer
5632 */
5633 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
5634 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
5635 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5636 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5637 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5638 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5639 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5640
fcf51541
BZ		 5641 return 0;
5642}
fcf51541
BZ		 5643
5644static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5645{
5646 unsigned int i;
5647 u32 reg;
5648
5649 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5650 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5651 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5652 return 0;
5653
5654 udelay(REGISTER_BUSY_DELAY);
5655 }
5656
ec9c4989 5657 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 5658 return -EACCES;
5659}
5660
5661static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5662{
5663 unsigned int i;
5664 u8 value;
5665
5666 /*
5667 * BBP was enabled after firmware was loaded,
5668 * but we need to reactivate it now.
5669 */
5670 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5671 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5672 msleep(1);
5673
5674 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5675 rt2800_bbp_read(rt2x00dev, 0, &value);
5676 if ((value != 0xff) && (value != 0x00))
5677 return 0;
5678 udelay(REGISTER_BUSY_DELAY);
5679 }
5680
ec9c4989 5681 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 5682 return -EACCES;
5683}
5684
a7bbbe5c
SG		 5685static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5686{
5687 u8 value;
5688
5689 rt2800_bbp_read(rt2x00dev, 4, &value);
5690 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5691 rt2800_bbp_write(rt2x00dev, 4, value);
5692}
5693
c2675487
SG		 5694static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5695{
5696 rt2800_bbp_write(rt2x00dev, 142, 1);
5697 rt2800_bbp_write(rt2x00dev, 143, 57);
5698}
5699
a7bbbe5c
SG		 5700static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5701{
5702 const u8 glrt_table[] = {
5703 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5704 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5705 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5706 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5707 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5708 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5709 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5710 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5711 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5712 };
5713 int i;
5714
5715 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5716 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5717 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5718 }
5719};
5720
624708b8 5721static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5722{
5723 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5724 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5725 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5726 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5727 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5728 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5729 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5730 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5731 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5732 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5733 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5734 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5735 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5736 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5737 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5738 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5739}
5740
5df1ff3a
SG		 5741static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5742{
5743 u16 eeprom;
5744 u8 value;
5745
5746 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5747 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5748 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5749 value |= 0x20;
5750 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5751 value &= ~0x02;
5752 rt2800_bbp_write(rt2x00dev, 138, value);
5753}
5754
dae62957
SG		 5755static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5756{
b2f8e0bd 5757 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5758
5759 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5760 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5761
5762 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5763 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5764
5765 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5766
5767 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5768 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5769
5770 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5771
5772 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5773
5774 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5775
5776 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5777
5778 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5779
5780 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5781
5782 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5783
5784 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5785
5786 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5787}
5788
39ab3e8b
SG		 5789static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5790{
e379de12
SG		 5791 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5792 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5793
5794 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5795 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5796 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5797 } else {
5798 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5799 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5800 }
8d97be38
SG		 5801
5802 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5803
5804 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5805
5806 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5807
5808 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5809
5810 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5811 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5812 else
5813 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5814
5815 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5816
5817 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5818
5819 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5820
5821 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5822
5823 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5824
5825 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5826}
5827
5828static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5829{
e379de12
SG		 5830 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5831 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5832
5833 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5834 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5835
5836 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5837
5838 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5839 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5840 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5841
5842 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5843
5844 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5845
5846 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5847
5848 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5849
5850 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5851
5852 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5853
5854 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5855 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5856 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5857 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5858 else
5859 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5860
5861 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5862
5863 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5864
5865 if (rt2x00_rt(rt2x00dev, RT3071) ||
5866 rt2x00_rt(rt2x00dev, RT3090))
5867 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5868}
5869
5870static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5871{
6addb24e
SG		 5872 u8 value;
5873
c3223573 5874 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5875
5876 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5877
5878 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5879 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5880
5881 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5882
5883 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5884 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5885 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5886 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5887
5888 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5889
5890 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5891
5892 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5893 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5894 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5895 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5896
5897 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5898
5899 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5900
5901 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5902
5903 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5904
5905 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5906
5907 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5908
5909 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5910
5911 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5912
5913 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5914
5915 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5916
5917 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5918
5919 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5920 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5921 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5922 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5923 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5924 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5925 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5926 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5927 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5928 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5929
5930 rt2800_bbp_read(rt2x00dev, 47, &value);
5931 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5932 rt2800_bbp_write(rt2x00dev, 47, value);
5933
5934 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5935 rt2800_bbp_read(rt2x00dev, 3, &value);
5936 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5937 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5938 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5939}
5940
5941static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5942{
29f3a58b
SG		 5943 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5944 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5945
5946 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5947
5948 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5949
5950 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5951 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5952
5953 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5954
5955 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5956 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5957 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5958 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5959
5960 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5961
5962 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5963
5964 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5965 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5966 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5967
5968 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414 5969
98e71f44
SV		 5970 if (rt2x00_rt(rt2x00dev, RT5350)) {
5971 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5972 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5973 } else {
5974 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5975 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5976 }
aef9f38b
SG		 5977
5978 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5979
5980 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5981
5982 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5983
5984 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5985
5986 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5987
5988 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118 5989
98e71f44
SV		 5990 if (rt2x00_rt(rt2x00dev, RT5350)) {
5991 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5992 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5993 } else {
5994 rt2800_bbp_write(rt2x00dev, 105, 0x34);
5995 rt2800_bbp_write(rt2x00dev, 106, 0x05);
5996 }
46b90d32
SG		 5997
5998 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 5999
6000 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 6001
6002 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6003 /* Set ITxBF timeout to 0x9c40=1000msec */
6004 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6005 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6006 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6007 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6008 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6009 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6010 /* Reprogram the inband interface to put right values in RXWI */
6011 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6012 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6013 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6014 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6015 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6016 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6017 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6018 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6019
6020 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
98e71f44
SV		 6021
6022 if (rt2x00_rt(rt2x00dev, RT5350)) {
6023 /* Antenna Software OFDM */
6024 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6025 /* Antenna Software CCK */
6026 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6027 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6028 /* Clear previously selected antenna */
6029 rt2800_bbp_write(rt2x00dev, 154, 0);
6030 }
39ab3e8b
SG		 6031}
6032
6033static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6034{
e379de12
SG		 6035 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6036 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 6037
6038 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6039 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 6040
6041 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 6042
6043 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6044 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6045 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 6046
6047 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 6048
6049 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 6050
6051 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 6052
6053 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 6054
6055 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 6056
6057 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 6058
6059 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6060 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6061 else
6062 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 6063
6064 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 6065
6066 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 6067
6068 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 6069}
6070
6071static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6072{
b2f8e0bd 6073 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 6074
6075 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6076 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 6077
6078 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6079 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 6080
6081 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 6082
6083 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6084 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6085 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 6086
6087 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 6088
6089 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 6090
6091 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 6092
6093 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 6094
6095 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 6096
6097 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 6098
6099 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 6100
6101 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 6102
6103 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 6104
6105 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 6106}
6107
b189a181
GJ		 6108static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6109{
6110 rt2800_init_bbp_early(rt2x00dev);
6111
6112 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6113 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6114 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6115 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6116
6117 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6118
6119 /* Enable DC filter */
6120 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6121 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6122}
6123
39ab3e8b
SG		 6124static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6125{
32ef8f49
SG		 6126 int ant, div_mode;
6127 u16 eeprom;
6128 u8 value;
6129
c3223573 6130 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 6131
6132 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 6133
6134 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6135 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 6136
6137 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142 6138
58422191 6139 rt2800_bbp_write(rt2x00dev, 69, 0x12);
72ffe142
SG		 6140 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6141 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6142 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6143
6144 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38 6145
58422191
SG		 6146 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6147
43f535e2
SG		 6148 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6149 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6150 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 6151
6152 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 6153
6154 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 6155
6156 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 6157
6158 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 6159
6160 if (rt2x00_rt(rt2x00dev, RT5392))
6161 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 6162
6163 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 6164
6165 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 6166
6167 if (rt2x00_rt(rt2x00dev, RT5392)) {
6168 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6169 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6170 }
672d1188
SG		 6171
6172 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 6173
6174 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 6175
6176 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 6177
6178 if (rt2x00_rt(rt2x00dev, RT5390))
6179 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6180 else if (rt2x00_rt(rt2x00dev, RT5392))
6181 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6182 else
6183 WARN_ON(1);
f2b6777c
SG		 6184
6185 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 6186
6187 if (rt2x00_rt(rt2x00dev, RT5392)) {
6188 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6189 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6190 }
5df1ff3a
SG		 6191
6192 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 6193
3e38d3da 6194 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 6195 div_mode = rt2x00_get_field16(eeprom,
6196 EEPROM_NIC_CONF1_ANT_DIVERSITY);
6197 ant = (div_mode == 3) ? 1 : 0;
6198
6199 /* check if this is a Bluetooth combo card */
c429dfef 6200 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
32ef8f49
SG		 6201 u32 reg;
6202
6203 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6204 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6205 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6206 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6207 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6208 if (ant == 0)
6209 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6210 else if (ant == 1)
6211 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6212 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6213 }
6214
6215 /* This chip has hardware antenna diversity*/
6216 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
6217 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6218 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6219 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6220 }
6221
6222 rt2800_bbp_read(rt2x00dev, 152, &value);
6223 if (ant == 0)
6224 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6225 else
6226 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6227 rt2800_bbp_write(rt2x00dev, 152, value);
6228
6229 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 6230}
6231
a7bbbe5c
SG		 6232static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6233{
6234 int ant, div_mode;
6235 u16 eeprom;
6236 u8 value;
6237
624708b8 6238 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 6239
a7bbbe5c
SG		 6240 rt2800_bbp_read(rt2x00dev, 105, &value);
6241 rt2x00_set_field8(&value, BBP105_MLD,
6242 rt2x00dev->default_ant.rx_chain_num == 2);
6243 rt2800_bbp_write(rt2x00dev, 105, value);
6244
6245 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6246
6247 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6248 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6249 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6250 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6251 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6252 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6253 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6254 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6255 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6256 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6257 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6258 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6259 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6260 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6261 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6262 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6263 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6264 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6265 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6266 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6267 /* FIXME BBP105 owerwrite */
6268 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6269 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6270 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6271 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6272 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6273 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6274
6275 /* Initialize GLRT (Generalized Likehood Radio Test) */
6276 rt2800_init_bbp_5592_glrt(rt2x00dev);
6277
6278 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6279
3e38d3da 6280 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 6281 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6282 ant = (div_mode == 3) ? 1 : 0;
6283 rt2800_bbp_read(rt2x00dev, 152, &value);
6284 if (ant == 0) {
6285 /* Main antenna */
6286 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6287 } else {
6288 /* Auxiliary antenna */
6289 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6290 }
6291 rt2800_bbp_write(rt2x00dev, 152, value);
6292
6293 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6294 rt2800_bbp_read(rt2x00dev, 254, &value);
6295 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6296 rt2800_bbp_write(rt2x00dev, 254, value);
6297 }
6298
c2675487
SG		 6299 rt2800_init_freq_calibration(rt2x00dev);
6300
a7bbbe5c 6301 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 6302 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6303 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 6304}
6305
41977e86
RY		 6306static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6307 const u8 reg, const u8 value)
6308{
6309 rt2800_bbp_write(rt2x00dev, 195, reg);
6310 rt2800_bbp_write(rt2x00dev, 196, value);
6311}
6312
6313static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6314 const u8 reg, const u8 value)
6315{
6316 rt2800_bbp_write(rt2x00dev, 158, reg);
6317 rt2800_bbp_write(rt2x00dev, 159, value);
6318}
6319
6320static void rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev,
6321 const u8 reg, u8 *value)
6322{
6323 rt2800_bbp_write(rt2x00dev, 158, reg);
6324 rt2800_bbp_read(rt2x00dev, 159, value);
6325}
6326
6327static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6328{
6329 u8 bbp;
6330
6331 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6332 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6333 rt2x00_set_field8(&bbp, BBP105_MLD,
6334 rt2x00dev->default_ant.rx_chain_num == 2);
6335 rt2800_bbp_write(rt2x00dev, 105, bbp);
6336
6337 /* Avoid data loss and CRC errors */
6338 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6339
6340 /* Fix I/Q swap issue */
6341 rt2800_bbp_read(rt2x00dev, 1, &bbp);
6342 bbp |= 0x04;
6343 rt2800_bbp_write(rt2x00dev, 1, bbp);
6344
6345 /* BBP for G band */
6346 rt2800_bbp_write(rt2x00dev, 3, 0x08);
6347 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6348 rt2800_bbp_write(rt2x00dev, 6, 0x08);
6349 rt2800_bbp_write(rt2x00dev, 14, 0x09);
6350 rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6351 rt2800_bbp_write(rt2x00dev, 16, 0x01);
6352 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6353 rt2800_bbp_write(rt2x00dev, 21, 0x00);
6354 rt2800_bbp_write(rt2x00dev, 22, 0x00);
6355 rt2800_bbp_write(rt2x00dev, 27, 0x00);
6356 rt2800_bbp_write(rt2x00dev, 28, 0x00);
6357 rt2800_bbp_write(rt2x00dev, 30, 0x00);
6358 rt2800_bbp_write(rt2x00dev, 31, 0x48);
6359 rt2800_bbp_write(rt2x00dev, 47, 0x40);
6360 rt2800_bbp_write(rt2x00dev, 62, 0x00);
6361 rt2800_bbp_write(rt2x00dev, 63, 0x00);
6362 rt2800_bbp_write(rt2x00dev, 64, 0x00);
6363 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6364 rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6365 rt2800_bbp_write(rt2x00dev, 67, 0x20);
6366 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6367 rt2800_bbp_write(rt2x00dev, 69, 0x10);
6368 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6369 rt2800_bbp_write(rt2x00dev, 73, 0x18);
6370 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6371 rt2800_bbp_write(rt2x00dev, 75, 0x60);
6372 rt2800_bbp_write(rt2x00dev, 76, 0x44);
6373 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6374 rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6375 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6376 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6377 rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6378 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6379 rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6380 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6381 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6382 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6383 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6384 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6385 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6386 rt2800_bbp_write(rt2x00dev, 96, 0x00);
6387 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6388 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6389 /* FIXME BBP105 owerwrite */
6390 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6391 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6392 rt2800_bbp_write(rt2x00dev, 109, 0x00);
6393 rt2800_bbp_write(rt2x00dev, 134, 0x10);
6394 rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6395 rt2800_bbp_write(rt2x00dev, 137, 0x04);
6396 rt2800_bbp_write(rt2x00dev, 142, 0x30);
6397 rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6398 rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6399 rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6400 rt2800_bbp_write(rt2x00dev, 162, 0x77);
6401 rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6402 rt2800_bbp_write(rt2x00dev, 164, 0x00);
6403 rt2800_bbp_write(rt2x00dev, 165, 0x00);
6404 rt2800_bbp_write(rt2x00dev, 186, 0x00);
6405 rt2800_bbp_write(rt2x00dev, 187, 0x00);
6406 rt2800_bbp_write(rt2x00dev, 188, 0x00);
6407 rt2800_bbp_write(rt2x00dev, 186, 0x00);
6408 rt2800_bbp_write(rt2x00dev, 187, 0x01);
6409 rt2800_bbp_write(rt2x00dev, 188, 0x00);
6410 rt2800_bbp_write(rt2x00dev, 189, 0x00);
6411
6412 rt2800_bbp_write(rt2x00dev, 91, 0x06);
6413 rt2800_bbp_write(rt2x00dev, 92, 0x04);
6414 rt2800_bbp_write(rt2x00dev, 93, 0x54);
6415 rt2800_bbp_write(rt2x00dev, 99, 0x50);
6416 rt2800_bbp_write(rt2x00dev, 148, 0x84);
6417 rt2800_bbp_write(rt2x00dev, 167, 0x80);
6418 rt2800_bbp_write(rt2x00dev, 178, 0xFF);
6419 rt2800_bbp_write(rt2x00dev, 106, 0x13);
6420
6421 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
6422 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
6423 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
6424 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
6425 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
6426 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
6427 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
6428 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
6429 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
6430 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
6431 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
6432 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
6433 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
6434 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
6435 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
6436 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
6437 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
6438 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
6439 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
6440 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
6441 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
6442 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
6443 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
6444 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
6445 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
6446 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
6447 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
6448 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
6449 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
6450 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
6451 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
6452 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
6453 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
6454 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
6455 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
6456 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
6457 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
6458 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
6459 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
6460 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
6461 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
6462 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
6463 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
6464 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
6465 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
6466 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
6467 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
6468 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
6469 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
6470 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
6471 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
6472 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
6473 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
6474 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
6475 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
6476 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
6477 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
6478 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
6479 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
6480 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
6481 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
6482 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
6483 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
6484 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
6485 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
6486 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
6487 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
6488 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
6489 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
6490 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
6491 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
6492 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
6493 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
6494 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
6495 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
6496 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
6497 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
6498 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
6499 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
6500 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
6501 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
6502 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
6503 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
6504 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
6505
6506 /* BBP for G band DCOC function */
6507 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
6508 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
6509 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
6510 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
6511 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
6512 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
6513 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
6514 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
6515 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
6516 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
6517 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
6518 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
6519 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
6520 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
6521 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
6522 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
6523 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
6524 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
6525 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
6526 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
6527
6528 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6529}
6530
a1ef5039 6531static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 6532{
6533 unsigned int i;
6534 u16 eeprom;
6535 u8 reg_id;
6536 u8 value;
6537
dae62957
SG		 6538 if (rt2800_is_305x_soc(rt2x00dev))
6539 rt2800_init_bbp_305x_soc(rt2x00dev);
6540
39ab3e8b
SG		 6541 switch (rt2x00dev->chip.rt) {
6542 case RT2860:
6543 case RT2872:
6544 case RT2883:
6545 rt2800_init_bbp_28xx(rt2x00dev);
6546 break;
6547 case RT3070:
6548 case RT3071:
6549 case RT3090:
6550 rt2800_init_bbp_30xx(rt2x00dev);
6551 break;
6552 case RT3290:
6553 rt2800_init_bbp_3290(rt2x00dev);
6554 break;
6555 case RT3352:
98e71f44 6556 case RT5350:
39ab3e8b
SG		 6557 rt2800_init_bbp_3352(rt2x00dev);
6558 break;
6559 case RT3390:
6560 rt2800_init_bbp_3390(rt2x00dev);
6561 break;
6562 case RT3572:
6563 rt2800_init_bbp_3572(rt2x00dev);
6564 break;
b189a181
GJ		 6565 case RT3593:
6566 rt2800_init_bbp_3593(rt2x00dev);
6567 return;
39ab3e8b
SG		 6568 case RT5390:
6569 case RT5392:
6570 rt2800_init_bbp_53xx(rt2x00dev);
6571 break;
6572 case RT5592:
a7bbbe5c 6573 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 6574 return;
41977e86
RY		 6575 case RT6352:
6576 rt2800_init_bbp_6352(rt2x00dev);
6577 break;
a7bbbe5c
SG		 6578 }
6579
fcf51541 6580 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 6581 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
6582 &eeprom);
fcf51541
BZ		 6583
6584 if (eeprom != 0xffff && eeprom != 0x0000) {
6585 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
6586 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
6587 rt2800_bbp_write(rt2x00dev, reg_id, value);
6588 }
6589 }
fcf51541 6590}
fcf51541 6591
d9517f2f
SG		 6592static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
6593{
6594 u32 reg;
6595
6596 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
6597 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
6598 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
6599}
6600
c5b3c350
SG		 6601static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
6602 u8 filter_target)
fcf51541
BZ		 6603{
6604 unsigned int i;
6605 u8 bbp;
6606 u8 rfcsr;
6607 u8 passband;
6608 u8 stopband;
6609 u8 overtuned = 0;
c5b3c350 6610 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 6611
6612 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6613
6614 rt2800_bbp_read(rt2x00dev, 4, &bbp);
6615 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
6616 rt2800_bbp_write(rt2x00dev, 4, bbp);
6617
80d184e6
RJH		 6618 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
6619 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
6620 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
6621
fcf51541
BZ		 6622 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
6623 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
6624 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6625
6626 /*
6627 * Set power & frequency of passband test tone
6628 */
6629 rt2800_bbp_write(rt2x00dev, 24, 0);
6630
6631 for (i = 0; i < 100; i++) {
6632 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6633 msleep(1);
6634
6635 rt2800_bbp_read(rt2x00dev, 55, &passband);
6636 if (passband)
6637 break;
6638 }
6639
6640 /*
6641 * Set power & frequency of stopband test tone
6642 */
6643 rt2800_bbp_write(rt2x00dev, 24, 0x06);
6644
6645 for (i = 0; i < 100; i++) {
6646 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6647 msleep(1);
6648
6649 rt2800_bbp_read(rt2x00dev, 55, &stopband);
6650
6651 if ((passband - stopband) <= filter_target) {
6652 rfcsr24++;
6653 overtuned += ((passband - stopband) == filter_target);
6654 } else
6655 break;
6656
6657 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6658 }
6659
6660 rfcsr24 -= !!overtuned;
6661
6662 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6663 return rfcsr24;
6664}
6665
ce94ede9
SG		 6666static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
6667 const unsigned int rf_reg)
6668{
6669 u8 rfcsr;
6670
6671 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
6672 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
6673 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6674 msleep(1);
6675 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
6676 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6677}
6678
c5b3c350
SG		 6679static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
6680{
6681 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6682 u8 filter_tgt_bw20;
6683 u8 filter_tgt_bw40;
6684 u8 rfcsr, bbp;
6685
6686 /*
6687 * TODO: sync filter_tgt values with vendor driver
6688 */
6689 if (rt2x00_rt(rt2x00dev, RT3070)) {
6690 filter_tgt_bw20 = 0x16;
6691 filter_tgt_bw40 = 0x19;
6692 } else {
6693 filter_tgt_bw20 = 0x13;
6694 filter_tgt_bw40 = 0x15;
6695 }
6696
6697 drv_data->calibration_bw20 =
6698 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
6699 drv_data->calibration_bw40 =
6700 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
6701
6702 /*
6703 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
6704 */
6705 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6706 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6707
6708 /*
6709 * Set back to initial state
6710 */
6711 rt2800_bbp_write(rt2x00dev, 24, 0);
6712
6713 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
6714 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
6715 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6716
6717 /*
6718 * Set BBP back to BW20
6719 */
6720 rt2800_bbp_read(rt2x00dev, 4, &bbp);
6721 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
6722 rt2800_bbp_write(rt2x00dev, 4, bbp);
6723}
6724
da8064c2
SG		 6725static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
6726{
6727 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6728 u8 min_gain, rfcsr, bbp;
6729 u16 eeprom;
6730
6731 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
6732
6733 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
6734 if (rt2x00_rt(rt2x00dev, RT3070) ||
6735 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6736 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
6737 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
c429dfef 6738 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
da8064c2
SG		 6739 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
6740 }
6741
6742 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
6743 if (drv_data->txmixer_gain_24g >= min_gain) {
6744 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
6745 drv_data->txmixer_gain_24g);
6746 }
6747
6748 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
6749
6750 if (rt2x00_rt(rt2x00dev, RT3090)) {
6751 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
6752 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 6753 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 6754 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6755 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
6756 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6757 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
6758 rt2800_bbp_write(rt2x00dev, 138, bbp);
6759 }
6760
6761 if (rt2x00_rt(rt2x00dev, RT3070)) {
6762 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
6763 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
6764 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
6765 else
6766 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
6767 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
6768 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
6769 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
6770 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
6771 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6772 rt2x00_rt(rt2x00dev, RT3090) ||
6773 rt2x00_rt(rt2x00dev, RT3390)) {
6774 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
6775 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6776 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
6777 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
6778 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
6779 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
6780 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6781
6782 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
6783 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
6784 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
6785
6786 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
6787 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
6788 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
6789
6790 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
6791 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
6792 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
6793 }
6794}
6795
ab7078ac
GJ		 6796static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
6797{
6798 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6799 u8 rfcsr;
6800 u8 tx_gain;
6801
6802 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
6803 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
6804 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
6805
6806 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
6807 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
6808 RFCSR17_TXMIXER_GAIN);
6809 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
6810 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
6811
6812 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
6813 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
6814 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
6815
6816 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
6817 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
6818 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
6819
6820 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
6821 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6822 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
6823 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6824
6825 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
6826 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
6827 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
6828
6829 /* TODO: enable stream mode */
6830}
6831
f7df8fe5
SG		 6832static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
6833{
6834 u8 reg;
6835 u16 eeprom;
6836
6837 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
6838 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 6839 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 6840 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6841 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
6842 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6843 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
6844 rt2800_bbp_write(rt2x00dev, 138, reg);
6845
6846 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
6847 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
6848 rt2800_rfcsr_write(rt2x00dev, 38, reg);
6849
6850 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
6851 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
6852 rt2800_rfcsr_write(rt2x00dev, 39, reg);
6853
6854 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6855
6856 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
6857 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
6858 rt2800_rfcsr_write(rt2x00dev, 30, reg);
6859}
6860
d5374ef1
SG		 6861static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
6862{
ce94ede9
SG		 6863 rt2800_rf_init_calibration(rt2x00dev, 30);
6864
d5374ef1
SG		 6865 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
6866 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
6867 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
6868 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
6869 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6870 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6871 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6872 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
6873 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
6874 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6875 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
6876 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6877 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
6878 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
6879 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6880 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6881 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6882 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6883 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6884 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6885 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6886 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6887 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6888 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6889 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6890 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6891 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6892 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6893 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6894 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6895 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6896 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6897}
6898
6899static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6900{
c9a221b2
SG		 6901 u8 rfcsr;
6902 u16 eeprom;
6903 u32 reg;
6904
ce94ede9
SG		 6905 /* XXX vendor driver do this only for 3070 */
6906 rt2800_rf_init_calibration(rt2x00dev, 30);
6907
d5374ef1
SG		 6908 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6909 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6910 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6911 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6912 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6913 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6914 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6915 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6916 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6917 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6918 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6919 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6920 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6921 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6922 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6923 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6924 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
772eb433 6925 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
d5374ef1 6926 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 6927
6928 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6929 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6930 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6931 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6932 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6933 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6934 rt2x00_rt(rt2x00dev, RT3090)) {
6935 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6936
6937 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6938 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6939 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6940
6941 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6942 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6943 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6944 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6945 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6946 &eeprom);
c9a221b2
SG		 6947 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6948 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6949 else
6950 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6951 }
6952 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6953
6954 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6955 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6956 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6957 }
c5b3c350
SG		 6958
6959 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6960
6961 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6962 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6963 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6964 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6965
6966 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6967 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6968}
6969
6970static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6971{
f9cdcbb1
SG		 6972 u8 rfcsr;
6973
ce94ede9
SG		 6974 rt2800_rf_init_calibration(rt2x00dev, 2);
6975
d5374ef1
SG		 6976 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6977 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6978 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6979 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6980 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6981 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6982 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6983 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6984 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6985 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6986 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6987 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6988 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6989 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6990 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6991 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6992 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6993 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6994 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6995 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6996 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6997 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6998 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6999 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7000 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7001 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7002 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7003 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7004 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7005 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7006 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7007 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7008 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7009 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7010 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7011 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7012 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7013 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7014 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7015 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7016 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7017 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7018 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7019 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7020 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7021 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 7022
7023 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
7024 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7025 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 7026
7027 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 7028 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 7029}
7030
7031static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7032{
1f242a3d 7033 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
dab38e7d 7034 &rt2x00dev->cap_flags);
1f242a3d 7035 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
dab38e7d
DG		 7036 &rt2x00dev->cap_flags);
7037 u8 rfcsr;
7038
ce94ede9
SG		 7039 rt2800_rf_init_calibration(rt2x00dev, 30);
7040
d5374ef1
SG		 7041 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7042 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7043 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7044 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7045 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7046 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7047 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7048 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7049 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7050 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7051 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7052 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7053 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7054 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7055 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7056 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7057 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7058 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7059 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7060 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7061 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7062 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7063 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7064 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7065 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7066 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7067 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7068 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7069 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7070 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7071 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7072 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7073 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
dab38e7d 7074 rfcsr = 0x01;
1f242a3d 7075 if (tx0_ext_pa)
dab38e7d 7076 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
1f242a3d 7077 if (tx1_ext_pa)
dab38e7d
DG		 7078 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7079 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
d5374ef1
SG		 7080 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7081 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7082 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7083 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7084 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7085 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
dab38e7d 7086 rfcsr = 0x52;
1f242a3d 7087 if (!tx0_ext_pa) {
dab38e7d
DG		 7088 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7089 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7090 }
7091 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7092 rfcsr = 0x52;
1f242a3d 7093 if (!tx1_ext_pa) {
dab38e7d
DG		 7094 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7095 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7096 }
7097 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
d5374ef1
SG		 7098 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7099 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7100 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7101 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7102 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7103 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7104 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
dab38e7d 7105 rfcsr = 0x2d;
1f242a3d 7106 if (tx0_ext_pa)
dab38e7d 7107 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
1f242a3d 7108 if (tx1_ext_pa)
dab38e7d
DG		 7109 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7110 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
1f242a3d
DG		 7111 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7112 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7113 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7114 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7115 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7116 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7117 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7118 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
d5374ef1
SG		 7119 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7120 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7121 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7122 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7123 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 7124
7125 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 7126 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 7127 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 7128}
7129
7130static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7131{
2971e66f
SG		 7132 u32 reg;
7133
ce94ede9
SG		 7134 rt2800_rf_init_calibration(rt2x00dev, 30);
7135
d5374ef1
SG		 7136 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7137 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7138 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7139 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7140 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7141 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7142 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7143 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7144 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7145 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7146 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7147 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7148 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7149 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7150 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7151 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7152 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7153 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7154 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7155 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7156 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7157 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7158 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7159 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7160 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7161 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7162 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7163 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7164 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7165 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7166 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7167 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 7168
7169 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
7170 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7171 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 7172
7173 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 7174
7175 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7176 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 7177
7178 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 7179 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 7180}
7181
7182static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7183{
87d91db9
SG		 7184 u8 rfcsr;
7185 u32 reg;
7186
ce94ede9
SG		 7187 rt2800_rf_init_calibration(rt2x00dev, 30);
7188
d5374ef1
SG		 7189 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7190 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7191 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7192 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7193 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7194 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7195 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7196 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7197 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7198 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7199 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7200 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7201 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7202 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7203 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7204 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7205 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7206 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7207 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7208 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7209 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7210 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7211 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7212 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7213 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7214 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7215 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7216 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7217 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7218 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7219 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 7220
7221 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
7222 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7223 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7224
7225 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
7226 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7227 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7228 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7229 msleep(1);
7230 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
7231 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7232 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7233 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 7234
7235 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 7236 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 7237 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 7238}
7239
d63f7e8c
GJ		 7240static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7241{
7242 u8 bbp;
7243 bool txbf_enabled = false; /* FIXME */
7244
7245 rt2800_bbp_read(rt2x00dev, 105, &bbp);
7246 if (rt2x00dev->default_ant.rx_chain_num == 1)
7247 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7248 else
7249 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7250 rt2800_bbp_write(rt2x00dev, 105, bbp);
7251
7252 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7253
7254 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7255 rt2800_bbp_write(rt2x00dev, 82, 0x82);
7256 rt2800_bbp_write(rt2x00dev, 106, 0x05);
7257 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7258 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7259 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7260 rt2800_bbp_write(rt2x00dev, 47, 0x48);
7261 rt2800_bbp_write(rt2x00dev, 120, 0x50);
7262
7263 if (txbf_enabled)
7264 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7265 else
7266 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7267
7268 /* SNR mapping */
7269 rt2800_bbp_write(rt2x00dev, 142, 6);
7270 rt2800_bbp_write(rt2x00dev, 143, 160);
7271 rt2800_bbp_write(rt2x00dev, 142, 7);
7272 rt2800_bbp_write(rt2x00dev, 143, 161);
7273 rt2800_bbp_write(rt2x00dev, 142, 8);
7274 rt2800_bbp_write(rt2x00dev, 143, 162);
7275
7276 /* ADC/DAC control */
7277 rt2800_bbp_write(rt2x00dev, 31, 0x08);
7278
7279 /* RX AGC energy lower bound in log2 */
7280 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7281
7282 /* FIXME: BBP 105 owerwrite? */
7283 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 7284
d63f7e8c
GJ		 7285}
7286
ab7078ac
GJ		 7287static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7288{
7289 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7290 u32 reg;
7291 u8 rfcsr;
7292
7293 /* Disable GPIO #4 and #7 function for LAN PE control */
7294 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
7295 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7296 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7297 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7298
7299 /* Initialize default register values */
7300 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7301 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7302 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7303 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7304 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7305 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7306 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7307 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7308 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7309 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7310 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7311 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7312 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7313 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7314 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7315 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7316 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7317 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7318 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7319 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7320 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7321 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7322 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7323 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7324 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7325 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7326 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7327 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7328 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7329 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7330 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7331 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7332
7333 /* Initiate calibration */
7334 /* TODO: use rt2800_rf_init_calibration ? */
7335 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
7336 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7337 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7338
88452541 7339 rt2800_freq_cal_mode1(rt2x00dev);
ab7078ac
GJ		 7340
7341 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
7342 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7343 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7344
7345 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
7346 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7347 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7348 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7349 usleep_range(1000, 1500);
7350 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
7351 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7352 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7353
7354 /* Set initial values for RX filter calibration */
7355 drv_data->calibration_bw20 = 0x1f;
7356 drv_data->calibration_bw40 = 0x2f;
7357
7358 /* Save BBP 25 & 26 values for later use in channel switching */
7359 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
7360 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
7361
7362 rt2800_led_open_drain_enable(rt2x00dev);
7363 rt2800_normal_mode_setup_3593(rt2x00dev);
7364
d63f7e8c 7365 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 7366
7367 /* TODO: enable stream mode support */
7368}
7369
98e71f44
SV		 7370static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7371{
7372 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7373 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7374 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7375 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7376 rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7377 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7378 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7379 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7380 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7381 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7382 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7383 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7384 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7385 if (rt2800_clk_is_20mhz(rt2x00dev))
7386 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7387 else
7388 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7389 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7390 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7391 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7392 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7393 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7394 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7395 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7396 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7397 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7398 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7399 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7400 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7401 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7402 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7403 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
7404 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7405 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7406 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7407 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7408 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7409 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7410 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7411 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7412 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7413 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7414 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7415 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7416 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7417 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7418 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
7419 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
7420 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7421 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7422 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7423 rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
7424 rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
7425 rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
7426 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7427 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7428 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7429 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7430 rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
7431 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7432 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7433 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
7434 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7435 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7436 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7437 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7438}
7439
d5374ef1
SG		 7440static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
7441{
ce94ede9
SG		 7442 rt2800_rf_init_calibration(rt2x00dev, 2);
7443
d5374ef1
SG		 7444 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7445 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7446 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7447 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7448 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7449 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7450 else
7451 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7452 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7453 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7454 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
c8520bcb 7455 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
d5374ef1
SG		 7456 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7457 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7458 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7459 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7460 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7461 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7462
7463 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7464 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7465 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7466 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7467 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
c8520bcb
KL		 7468 if (rt2x00_is_usb(rt2x00dev) &&
7469 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
d5374ef1
SG		 7470 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7471 else
7472 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
7473 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7474 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7475 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7476 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7477
7122e660 7478 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
d5374ef1
SG		 7479 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7480 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7481 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7482 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7483 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7484 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7485 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7486 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7487 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7488
c8520bcb 7489 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
d5374ef1
SG		 7490 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7491 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
7492 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
7493 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7494 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7495 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7496 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7497 else
7498 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
7499 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7500 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7501 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7502
7503 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7504 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7505 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7506 else
7507 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
7508 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7509 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
c8520bcb
KL		 7510 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7511 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
7512 else
7513 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
d5374ef1
SG		 7514 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7515 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7122e660 7516 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
d5374ef1
SG		 7517
7518 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
c8520bcb
KL		 7519 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
7520 if (rt2x00_is_usb(rt2x00dev))
7521 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7522 else
7523 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
7524 } else {
7525 if (rt2x00_is_usb(rt2x00dev))
7526 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
7527 else
7528 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
7529 }
d5374ef1
SG		 7530 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7531 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 7532
7533 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 7534
7535 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 7536}
7537
7538static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
7539{
ce94ede9
SG		 7540 rt2800_rf_init_calibration(rt2x00dev, 2);
7541
d5374ef1 7542 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
d5374ef1
SG		 7543 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7544 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7545 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7546 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7547 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7548 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7549 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7550 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7551 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7552 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7553 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7554 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7555 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
7556 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7557 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
7558 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7559 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
7560 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
7561 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7562 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7563 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7564 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7565 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7566 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7567 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7568 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
7569 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7570 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7571 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7572 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7573 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7574 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
7575 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7576 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
7577 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7578 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7579 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7580 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7581 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7582 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7583 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
7584 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7585 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7586 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
7587 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
7588 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
7589 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
7590 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7591 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7592 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
7593 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7594 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7595 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
7596 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7597 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
7598 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
7599 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 7600
7601 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 7602
7603 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 7604}
7605
0c9e5fb9
SG		 7606static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
7607{
ce94ede9
SG		 7608 rt2800_rf_init_calibration(rt2x00dev, 30);
7609
0c9e5fb9
SG		 7610 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
7611 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
0c9e5fb9
SG		 7612 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7613 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
7614 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7615 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7616 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7617 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7618 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7619 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
7620 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
7621 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
7622 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7623 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7624 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7625 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7626 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7627 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7628 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
7629 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
7630 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7631
7632 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7633 msleep(1);
7634
88452541 7635 rt2800_freq_cal_mode1(rt2x00dev);
c630ccf1 7636
c630ccf1
SG		 7637 /* Enable DC filter */
7638 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7639 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7640
f7df8fe5 7641 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 7642
7643 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
7644 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 7645
7646 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 7647}
7648
41977e86
RY		 7649static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
7650 bool set_bw, bool is_ht40)
7651{
7652 u8 bbp_val;
7653
7654 rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
7655 bbp_val |= 0x1;
7656 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7657 usleep_range(100, 200);
7658
7659 if (set_bw) {
7660 rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
7661 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
7662 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7663 usleep_range(100, 200);
7664 }
7665
7666 rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
7667 bbp_val &= (~0x1);
7668 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7669 usleep_range(100, 200);
7670}
7671
7672static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
7673{
7674 u8 rf_val;
7675
7676 if (btxcal)
7677 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
7678 else
7679 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
7680
7681 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
7682
7683 rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &rf_val);
7684 rf_val |= 0x80;
7685 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
7686
7687 if (btxcal) {
7688 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
7689 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
7690 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7691 rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val);
7692 rf_val &= (~0x3F);
7693 rf_val |= 0x3F;
7694 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7695 rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val);
7696 rf_val &= (~0x3F);
7697 rf_val |= 0x3F;
7698 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7699 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
7700 } else {
7701 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
7702 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
7703 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7704 rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val);
7705 rf_val &= (~0x3F);
7706 rf_val |= 0x34;
7707 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7708 rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val);
7709 rf_val &= (~0x3F);
7710 rf_val |= 0x34;
7711 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7712 }
7713
7714 return 0;
7715}
7716
7717static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
7718{
7719 unsigned int cnt;
7720 u8 bbp_val;
7721 char cal_val;
7722
7723 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
7724
7725 cnt = 0;
7726 do {
7727 usleep_range(500, 2000);
7728 rt2800_bbp_read(rt2x00dev, 159, &bbp_val);
7729 if (bbp_val == 0x02 || cnt == 20)
7730 break;
7731
7732 cnt++;
7733 } while (cnt < 20);
7734
7735 rt2800_bbp_dcoc_read(rt2x00dev, 0x39, &bbp_val);
7736 cal_val = bbp_val & 0x7F;
7737 if (cal_val >= 0x40)
7738 cal_val -= 128;
7739
7740 return cal_val;
7741}
7742
7743static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
7744 bool btxcal)
7745{
7746 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7747 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
7748 u8 filter_target;
7749 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
7750 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
7751 int loop = 0, is_ht40, cnt;
7752 u8 bbp_val, rf_val;
7753 char cal_r32_init, cal_r32_val, cal_diff;
7754 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
7755 u8 saverfb5r06, saverfb5r07;
7756 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
7757 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
7758 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
7759 u8 saverfb5r58, saverfb5r59;
7760 u8 savebbp159r0, savebbp159r2, savebbpr23;
7761 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
7762
7763 /* Save MAC registers */
7764 rt2800_register_read(rt2x00dev, RF_CONTROL0, &MAC_RF_CONTROL0);
7765 rt2800_register_read(rt2x00dev, RF_BYPASS0, &MAC_RF_BYPASS0);
7766
7767 /* save BBP registers */
7768 rt2800_bbp_read(rt2x00dev, 23, &savebbpr23);
7769
7770 rt2800_bbp_dcoc_read(rt2x00dev, 0, &savebbp159r0);
7771 rt2800_bbp_dcoc_read(rt2x00dev, 2, &savebbp159r2);
7772
7773 /* Save RF registers */
7774 rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &saverfb5r00);
7775 rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &saverfb5r01);
7776 rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &saverfb5r03);
7777 rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &saverfb5r04);
7778 rt2800_rfcsr_read_bank(rt2x00dev, 5, 5, &saverfb5r05);
7779 rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &saverfb5r06);
7780 rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &saverfb5r07);
7781 rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &saverfb5r08);
7782 rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &saverfb5r17);
7783 rt2800_rfcsr_read_bank(rt2x00dev, 5, 18, &saverfb5r18);
7784 rt2800_rfcsr_read_bank(rt2x00dev, 5, 19, &saverfb5r19);
7785 rt2800_rfcsr_read_bank(rt2x00dev, 5, 20, &saverfb5r20);
7786
7787 rt2800_rfcsr_read_bank(rt2x00dev, 5, 37, &saverfb5r37);
7788 rt2800_rfcsr_read_bank(rt2x00dev, 5, 38, &saverfb5r38);
7789 rt2800_rfcsr_read_bank(rt2x00dev, 5, 39, &saverfb5r39);
7790 rt2800_rfcsr_read_bank(rt2x00dev, 5, 40, &saverfb5r40);
7791 rt2800_rfcsr_read_bank(rt2x00dev, 5, 41, &saverfb5r41);
7792 rt2800_rfcsr_read_bank(rt2x00dev, 5, 42, &saverfb5r42);
7793 rt2800_rfcsr_read_bank(rt2x00dev, 5, 43, &saverfb5r43);
7794 rt2800_rfcsr_read_bank(rt2x00dev, 5, 44, &saverfb5r44);
7795 rt2800_rfcsr_read_bank(rt2x00dev, 5, 45, &saverfb5r45);
7796 rt2800_rfcsr_read_bank(rt2x00dev, 5, 46, &saverfb5r46);
7797
7798 rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &saverfb5r58);
7799 rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &saverfb5r59);
7800
7801 rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val);
7802 rf_val |= 0x3;
7803 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7804
7805 rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val);
7806 rf_val |= 0x1;
7807 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
7808
7809 cnt = 0;
7810 do {
7811 usleep_range(500, 2000);
7812 rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val);
7813 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
7814 break;
7815 cnt++;
7816 } while (cnt < 40);
7817
7818 rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val);
7819 rf_val &= (~0x3);
7820 rf_val |= 0x1;
7821 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7822
7823 /* I-3 */
7824 rt2800_bbp_read(rt2x00dev, 23, &bbp_val);
7825 bbp_val &= (~0x1F);
7826 bbp_val |= 0x10;
7827 rt2800_bbp_write(rt2x00dev, 23, bbp_val);
7828
7829 do {
7830 /* I-4,5,6,7,8,9 */
7831 if (loop == 0) {
7832 is_ht40 = false;
7833
7834 if (btxcal)
7835 filter_target = tx_filter_target_20m;
7836 else
7837 filter_target = rx_filter_target_20m;
7838 } else {
7839 is_ht40 = true;
7840
7841 if (btxcal)
7842 filter_target = tx_filter_target_40m;
7843 else
7844 filter_target = rx_filter_target_40m;
7845 }
7846
7847 rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &rf_val);
7848 rf_val &= (~0x04);
7849 if (loop == 1)
7850 rf_val |= 0x4;
7851
7852 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
7853
7854 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
7855
7856 rt2800_rf_lp_config(rt2x00dev, btxcal);
7857 if (btxcal) {
7858 tx_agc_fc = 0;
7859 rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val);
7860 rf_val &= (~0x7F);
7861 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
7862 rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val);
7863 rf_val &= (~0x7F);
7864 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7865 } else {
7866 rx_agc_fc = 0;
7867 rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val);
7868 rf_val &= (~0x7F);
7869 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
7870 rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val);
7871 rf_val &= (~0x7F);
7872 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7873 }
7874
7875 usleep_range(1000, 2000);
7876
7877 rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
7878 bbp_val &= (~0x6);
7879 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7880
7881 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7882
7883 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7884
7885 rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
7886 bbp_val |= 0x6;
7887 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7888do_cal:
7889 if (btxcal) {
7890 rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val);
7891 rf_val &= (~0x7F);
7892 rf_val |= tx_agc_fc;
7893 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
7894 rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val);
7895 rf_val &= (~0x7F);
7896 rf_val |= tx_agc_fc;
7897 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7898 } else {
7899 rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val);
7900 rf_val &= (~0x7F);
7901 rf_val |= rx_agc_fc;
7902 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
7903 rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val);
7904 rf_val &= (~0x7F);
7905 rf_val |= rx_agc_fc;
7906 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7907 }
7908
7909 usleep_range(500, 1000);
7910
7911 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7912
7913 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7914
7915 cal_diff = cal_r32_init - cal_r32_val;
7916
7917 if (btxcal)
7918 cmm_agc_fc = tx_agc_fc;
7919 else
7920 cmm_agc_fc = rx_agc_fc;
7921
7922 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
7923 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
7924 if (btxcal)
7925 tx_agc_fc = 0;
7926 else
7927 rx_agc_fc = 0;
7928 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
7929 if (btxcal)
7930 tx_agc_fc++;
7931 else
7932 rx_agc_fc++;
7933 goto do_cal;
7934 }
7935
7936 if (btxcal) {
7937 if (loop == 0)
7938 drv_data->tx_calibration_bw20 = tx_agc_fc;
7939 else
7940 drv_data->tx_calibration_bw40 = tx_agc_fc;
7941 } else {
7942 if (loop == 0)
7943 drv_data->rx_calibration_bw20 = rx_agc_fc;
7944 else
7945 drv_data->rx_calibration_bw40 = rx_agc_fc;
7946 }
7947
7948 loop++;
7949 } while (loop <= 1);
7950
7951 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
7952 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
7953 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
7954 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
7955 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
7956 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
7957 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
7958 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
7959 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
7960 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
7961 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
7962 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
7963
7964 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
7965 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
7966 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
7967 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
7968 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
7969 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
7970 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
7971 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
7972 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
7973 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
7974
7975 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
7976 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
7977
7978 rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
7979
7980 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
7981 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
7982
7983 rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
7984 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
7985 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
7986 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7987
7988 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
7989 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
7990}
7991
7992static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
7993{
7994 /* Initialize RF central register to default value */
7995 rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
7996 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7997 rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
7998 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
7999 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8000 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8001 rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8002 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8003 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8004 rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8005 rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8006 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8007 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8008 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8009 rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8010 rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8011 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8012 rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8013 rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8014 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8015 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8016 rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8017 rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8018 rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8019 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8020 rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8021 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8022 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8023 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8024 rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8025 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8026 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8027 rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8028 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8029 rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8030 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8031 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8032 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8033 rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8034 rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8035 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8036 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8037 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8038 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8039
8040 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8041 if (rt2800_clk_is_20mhz(rt2x00dev))
8042 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8043 else
8044 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8045 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8046 rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8047 rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8048 rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8049 rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8050 rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8051 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8052 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8053 rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8054 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8055 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8056 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8057 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8058 rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8059 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8060 rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8061
8062 rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8063 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8064 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8065
8066 /* Initialize RF channel register to default value */
8067 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8068 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8069 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8070 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8071 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8072 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8073 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8074 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8075 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8076 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8077 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8078 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8079 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8080 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8081 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8082 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8083 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8084 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8085 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8086 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8087 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8088 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8089 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8090 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8091 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8092 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8093 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8094 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8095 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8096 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8097 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8098 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8099 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8100 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8101 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8102 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8103 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8104 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8105 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8106 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8107 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8108 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8109 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8110 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8111 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8112 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8113 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8114 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8115 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8116 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8117 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8118 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8119 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8120 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8121 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8122 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8123 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8124 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8125 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8126 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8127
8128 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8129
8130 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8131 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8132 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8133 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8134 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8135 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8136 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8137 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8138 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8139 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8140 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8141 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8142 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8143 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8144 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8145 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8146 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8147 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
a0597834
TP		 8148 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8149 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
41977e86 8150 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
a0597834
TP		 8151 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8152 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
41977e86
RY		 8153 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8154 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8155 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8156 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8157 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8158 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8159 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8160
8161 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8162 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8163 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8164 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8165 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8166 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8167 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8168 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8169 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8170
8171 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8172 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8173 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8174 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8175 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8176 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8177
8178 /* Initialize RF channel register for DRQFN */
8179 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8180 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8181 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8182 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8183 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8184 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8185 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8186 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8187
8188 /* Initialize RF DC calibration register to default value */
8189 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8190 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8191 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8192 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8193 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8194 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8195 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8196 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8197 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8198 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8199 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8200 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8201 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8202 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8203 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8204 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8205 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8206 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8207 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8208 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8209 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8210 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8211 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8212 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8213 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8214 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8215 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8216 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8217 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8218 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8219 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8220 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8221 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8222 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8223 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8224 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8225 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8226 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8227 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8228 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8229 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8230 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8231 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8232 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8233 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8234 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8235 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8236 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8237 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8238 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8239 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8240 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8241 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8242 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8243 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8244 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8245 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8246 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8247 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8248
8249 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8250 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8251 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8252
8253 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8254 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8255
8256 rt2800_bw_filter_calibration(rt2x00dev, true);
8257 rt2800_bw_filter_calibration(rt2x00dev, false);
8258}
8259
074f2529 8260static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 8261{
d5374ef1
SG		 8262 if (rt2800_is_305x_soc(rt2x00dev)) {
8263 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 8264 return;
d5374ef1
SG		 8265 }
8266
8267 switch (rt2x00dev->chip.rt) {
8268 case RT3070:
8269 case RT3071:
8270 case RT3090:
8271 rt2800_init_rfcsr_30xx(rt2x00dev);
8272 break;
8273 case RT3290:
8274 rt2800_init_rfcsr_3290(rt2x00dev);
8275 break;
8276 case RT3352:
8277 rt2800_init_rfcsr_3352(rt2x00dev);
8278 break;
8279 case RT3390:
8280 rt2800_init_rfcsr_3390(rt2x00dev);
8281 break;
8282 case RT3572:
8283 rt2800_init_rfcsr_3572(rt2x00dev);
8284 break;
ab7078ac
GJ		 8285 case RT3593:
8286 rt2800_init_rfcsr_3593(rt2x00dev);
8287 break;
98e71f44
SV		 8288 case RT5350:
8289 rt2800_init_rfcsr_5350(rt2x00dev);
8290 break;
d5374ef1
SG		 8291 case RT5390:
8292 rt2800_init_rfcsr_5390(rt2x00dev);
8293 break;
8294 case RT5392:
8295 rt2800_init_rfcsr_5392(rt2x00dev);
8296 break;
0c9e5fb9
SG		 8297 case RT5592:
8298 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 8299 break;
41977e86
RY		 8300 case RT6352:
8301 rt2800_init_rfcsr_6352(rt2x00dev);
8302 break;
8cdd15e0 8303 }
fcf51541 8304}
b9a07ae9
ID		 8305
8306int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
8307{
8308 u32 reg;
8309 u16 word;
8310
8311 /*
61edc7fa 8312 * Initialize MAC registers.
b9a07ae9
ID		 8313 */
8314 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 8315 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 8316 return -EIO;
8317
61edc7fa
SG		 8318 /*
8319 * Wait BBP/RF to wake up.
8320 */
f4e1a4d3
SG		 8321 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
8322 return -EIO;
8323
b9a07ae9 8324 /*
61edc7fa 8325 * Send signal during boot time to initialize firmware.
b9a07ae9 8326 */
c630ccf1
SG		 8327 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
8328 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
f4e1a4d3 8329 if (rt2x00_is_usb(rt2x00dev))
c630ccf1 8330 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f4e1a4d3 8331 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
c630ccf1
SG		 8332 msleep(1);
8333
61edc7fa
SG		 8334 /*
8335 * Make sure BBP is up and running.
8336 */
f4e1a4d3 8337 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 8338 return -EIO;
b9a07ae9 8339
61edc7fa
SG		 8340 /*
8341 * Initialize BBP/RF registers.
8342 */
a1ef5039 8343 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 8344 rt2800_init_rfcsr(rt2x00dev);
8345
b9a07ae9
ID		 8346 if (rt2x00_is_usb(rt2x00dev) &&
8347 (rt2x00_rt(rt2x00dev, RT3070) ||
8348 rt2x00_rt(rt2x00dev, RT3071) ||
8349 rt2x00_rt(rt2x00dev, RT3572))) {
8350 udelay(200);
8351 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
8352 udelay(10);
8353 }
8354
8355 /*
8356 * Enable RX.
8357 */
8358 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
8359 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8360 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8361 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8362
8363 udelay(50);
8364
8365 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
8366 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
8367 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
b9a07ae9
ID		 8368 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
8369 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
8370
8371 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
8372 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8373 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
8374 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8375
8376 /*
8377 * Initialize LED control
8378 */
3e38d3da 8379 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 8380 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 8381 word & 0xff, (word >> 8) & 0xff);
8382
3e38d3da 8383 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 8384 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 8385 word & 0xff, (word >> 8) & 0xff);
8386
3e38d3da 8387 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 8388 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 8389 word & 0xff, (word >> 8) & 0xff);
8390
8391 return 0;
8392}
8393EXPORT_SYMBOL_GPL(rt2800_enable_radio);
8394
8395void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
8396{
8397 u32 reg;
8398
f7b395e9 8399 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 8400
8401 /* Wait for DMA, ignore error */
8402 rt2800_wait_wpdma_ready(rt2x00dev);
8403
8404 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
8405 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
8406 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8407 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 8408}
8409EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 8410
30e84034
BZ		 8411int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
8412{
8413 u32 reg;
a89534ed 8414 u16 efuse_ctrl_reg;
30e84034 8415
a89534ed
WH		 8416 if (rt2x00_rt(rt2x00dev, RT3290))
8417 efuse_ctrl_reg = EFUSE_CTRL_3290;
8418 else
8419 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 8420
a89534ed 8421 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 8422 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
8423}
8424EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
8425
8426static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
8427{
8428 u32 reg;
a89534ed
WH		 8429 u16 efuse_ctrl_reg;
8430 u16 efuse_data0_reg;
8431 u16 efuse_data1_reg;
8432 u16 efuse_data2_reg;
8433 u16 efuse_data3_reg;
8434
8435 if (rt2x00_rt(rt2x00dev, RT3290)) {
8436 efuse_ctrl_reg = EFUSE_CTRL_3290;
8437 efuse_data0_reg = EFUSE_DATA0_3290;
8438 efuse_data1_reg = EFUSE_DATA1_3290;
8439 efuse_data2_reg = EFUSE_DATA2_3290;
8440 efuse_data3_reg = EFUSE_DATA3_3290;
8441 } else {
8442 efuse_ctrl_reg = EFUSE_CTRL;
8443 efuse_data0_reg = EFUSE_DATA0;
8444 efuse_data1_reg = EFUSE_DATA1;
8445 efuse_data2_reg = EFUSE_DATA2;
8446 efuse_data3_reg = EFUSE_DATA3;
8447 }
31a4cf1f
GW		 8448 mutex_lock(&rt2x00dev->csr_mutex);
8449
a89534ed 8450 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 8451 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
8452 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
8453 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 8454 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 8455
8456 /* Wait until the EEPROM has been loaded */
a89534ed 8457 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 8458 /* Apparently the data is read from end to start */
a89534ed 8459 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 8460 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 8461 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 8462 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 8463 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 8464 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 8465 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 8466 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 8467 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 8468
8469 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 8470}
8471
a02308e9 8472int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 8473{
8474 unsigned int i;
8475
8476 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
8477 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 8478
8479 return 0;
30e84034
BZ		 8480}
8481EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
8482
a3f1625d
GJ		 8483static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
8484{
8485 u16 word;
8486
6316c786
GJ		 8487 if (rt2x00_rt(rt2x00dev, RT3593))
8488 return 0;
8489
a3f1625d
GJ		 8490 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
8491 if ((word & 0x00ff) != 0x00ff)
8492 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
8493
8494 return 0;
8495}
8496
8497static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
8498{
8499 u16 word;
8500
6316c786
GJ		 8501 if (rt2x00_rt(rt2x00dev, RT3593))
8502 return 0;
8503
a3f1625d
GJ		 8504 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
8505 if ((word & 0x00ff) != 0x00ff)
8506 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
8507
8508 return 0;
8509}
8510
ad417a53 8511static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 8512{
77c06c2c 8513 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 8514 u16 word;
8515 u8 *mac;
8516 u8 default_lna_gain;
a02308e9 8517 int retval;
38bd7b8a 8518
ad417a53
GW		 8519 /*
8520 * Read the EEPROM.
8521 */
a02308e9
GJ		 8522 retval = rt2800_read_eeprom(rt2x00dev);
8523 if (retval)
8524 return retval;
ad417a53 8525
38bd7b8a
BZ		 8526 /*
8527 * Start validation of the data that has been read.
8528 */
3e38d3da 8529 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9766cb70 8530 rt2x00lib_set_mac_address(rt2x00dev, mac);
38bd7b8a 8531
3e38d3da 8532 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 8533 if (word == 0xffff) {
38c8a566
RJH		 8534 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8535 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
8536 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 8537 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 8538 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 8539 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 8540 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 8541 /*
8542 * There is a max of 2 RX streams for RT28x0 series
8543 */
38c8a566
RJH		 8544 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
8545 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 8546 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 8547 }
8548
3e38d3da 8549 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 8550 if (word == 0xffff) {
38c8a566
RJH		 8551 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
8552 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
8553 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
8554 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
8555 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
8556 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
8557 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
8558 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
8559 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
8560 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
8561 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
8562 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
8563 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
8564 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
8565 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 8566 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 8567 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 8568 }
8569
3e38d3da 8570 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 8571 if ((word & 0x00ff) == 0x00ff) {
8572 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 8573 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 8574 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 8575 }
8576 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 8577 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
8578 LED_MODE_TXRX_ACTIVITY);
8579 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 8580 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8581 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
8582 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
8583 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 8584 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 8585 }
8586
8587 /*
8588 * During the LNA validation we are going to use
8589 * lna0 as correct value. Note that EEPROM_LNA
8590 * is never validated.
8591 */
3e38d3da 8592 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 8593 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
8594
3e38d3da 8595 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 8596 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
8597 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
8598 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
8599 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 8600 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 8601
a3f1625d 8602 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 8603
3e38d3da 8604 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 8605 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
8606 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 8607 if (!rt2x00_rt(rt2x00dev, RT3593)) {
8608 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
8609 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
8610 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
8611 default_lna_gain);
8612 }
3e38d3da 8613 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 8614
a3f1625d 8615 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 8616
3e38d3da 8617 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 8618 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
8619 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
8620 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
8621 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 8622 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 8623
3e38d3da 8624 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 8625 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
8626 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 8627 if (!rt2x00_rt(rt2x00dev, RT3593)) {
8628 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
8629 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
8630 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
8631 default_lna_gain);
8632 }
3e38d3da 8633 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 8634
f36bb0ca
GJ		 8635 if (rt2x00_rt(rt2x00dev, RT3593)) {
8636 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
8637 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
8638 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
8639 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8640 default_lna_gain);
8641 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
8642 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
8643 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8644 default_lna_gain);
8645 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
8646 }
8647
38bd7b8a
BZ		 8648 return 0;
8649}
38bd7b8a 8650
ad417a53 8651static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 8652{
38bd7b8a
BZ		 8653 u16 value;
8654 u16 eeprom;
86868b26 8655 u16 rf;
38bd7b8a 8656
86868b26
GJ		 8657 /*
8658 * Read EEPROM word for configuration.
8659 */
3e38d3da 8660 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 8661
8662 /*
8663 * Identify RF chipset by EEPROM value
8664 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
8665 * RT53xx: defined in "EEPROM_CHIP_ID" field
8666 */
8667 if (rt2x00_rt(rt2x00dev, RT3290) ||
8668 rt2x00_rt(rt2x00dev, RT5390) ||
41977e86
RY		 8669 rt2x00_rt(rt2x00dev, RT5392) ||
8670 rt2x00_rt(rt2x00dev, RT6352))
3e38d3da 8671 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
b8c2db58
FF		 8672 else if (rt2x00_rt(rt2x00dev, RT3352))
8673 rf = RF3322;
98e71f44
SV		 8674 else if (rt2x00_rt(rt2x00dev, RT5350))
8675 rf = RF5350;
86868b26
GJ		 8676 else
8677 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
8678
8679 switch (rf) {
d331eb51
LF		 8680 case RF2820:
8681 case RF2850:
8682 case RF2720:
8683 case RF2750:
8684 case RF3020:
8685 case RF2020:
8686 case RF3021:
8687 case RF3022:
8688 case RF3052:
0f5af26a 8689 case RF3053:
3b9b74ba 8690 case RF3070:
a89534ed 8691 case RF3290:
d331eb51 8692 case RF3320:
03839951 8693 case RF3322:
98e71f44 8694 case RF5350:
ccf91bd6 8695 case RF5360:
ac0372ab 8696 case RF5362:
d331eb51 8697 case RF5370:
2ed71884 8698 case RF5372:
d331eb51 8699 case RF5390:
cff3d1f0 8700 case RF5392:
b8863f8b 8701 case RF5592:
41977e86 8702 case RF7620:
d331eb51
LF		 8703 break;
8704 default:
ec9c4989
JP		 8705 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
8706 rf);
38bd7b8a
BZ		 8707 return -ENODEV;
8708 }
8709
86868b26
GJ		 8710 rt2x00_set_rf(rt2x00dev, rf);
8711
38bd7b8a
BZ		 8712 /*
8713 * Identify default antenna configuration.
8714 */
d96aa640 8715 rt2x00dev->default_ant.tx_chain_num =
38c8a566 8716 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 8717 rt2x00dev->default_ant.rx_chain_num =
38c8a566 8718 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 8719
3e38d3da 8720 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 8721
8722 if (rt2x00_rt(rt2x00dev, RT3070) ||
8723 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 8724 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 8725 rt2x00_rt(rt2x00dev, RT3390)) {
8726 value = rt2x00_get_field16(eeprom,
8727 EEPROM_NIC_CONF1_ANT_DIVERSITY);
8728 switch (value) {
8729 case 0:
8730 case 1:
8731 case 2:
8732 rt2x00dev->default_ant.tx = ANTENNA_A;
8733 rt2x00dev->default_ant.rx = ANTENNA_A;
8734 break;
8735 case 3:
8736 rt2x00dev->default_ant.tx = ANTENNA_A;
8737 rt2x00dev->default_ant.rx = ANTENNA_B;
8738 break;
8739 }
8740 } else {
8741 rt2x00dev->default_ant.tx = ANTENNA_A;
8742 rt2x00dev->default_ant.rx = ANTENNA_A;
8743 }
8744
0586a11b
AA		 8745 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
8746 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
8747 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
8748 }
8749
38bd7b8a 8750 /*
9328fdac 8751 * Determine external LNA informations.
38bd7b8a 8752 */
38c8a566 8753 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 8754 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 8755 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 8756 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 8757
8758 /*
8759 * Detect if this device has an hardware controlled radio.
8760 */
38c8a566 8761 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 8762 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 8763
fdbc7b0a
GW		 8764 /*
8765 * Detect if this device has Bluetooth co-existence.
8766 */
dab38e7d
DG		 8767 if (!rt2x00_rt(rt2x00dev, RT3352) &&
8768 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
fdbc7b0a
GW		 8769 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
8770
9328fdac
GW		 8771 /*
8772 * Read frequency offset and RF programming sequence.
8773 */
3e38d3da 8774 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 8775 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
8776
38bd7b8a
BZ		 8777 /*
8778 * Store led settings, for correct led behaviour.
8779 */
8780#ifdef CONFIG_RT2X00_LIB_LEDS
8781 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
8782 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
8783 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
8784
9328fdac 8785 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 8786#endif /* CONFIG_RT2X00_LIB_LEDS */
8787
e90c54b2
RJH		 8788 /*
8789 * Check if support EIRP tx power limit feature.
8790 */
3e38d3da 8791 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 8792
8793 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
8794 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 8795 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 8796
dab38e7d
DG		 8797 /*
8798 * Detect if device uses internal or external PA
8799 */
8800 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
8801
8802 if (rt2x00_rt(rt2x00dev, RT3352)) {
1f242a3d 8803 if (rt2x00_get_field16(eeprom,
dab38e7d 8804 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
1f242a3d 8805 __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
dab38e7d 8806 &rt2x00dev->cap_flags);
1f242a3d 8807 if (rt2x00_get_field16(eeprom,
dab38e7d 8808 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
1f242a3d 8809 __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
dab38e7d
DG		 8810 &rt2x00dev->cap_flags);
8811 }
8812
38bd7b8a
BZ		 8813 return 0;
8814}
38bd7b8a 8815
4da2933f 8816/*
55f9321a 8817 * RF value list for rt28xx
4da2933f
BZ		 8818 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
8819 */
8820static const struct rf_channel rf_vals[] = {
8821 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
8822 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
8823 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
8824 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
8825 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
8826 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
8827 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
8828 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
8829 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
8830 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
8831 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
8832 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
8833 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
8834 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
8835
8836 /* 802.11 UNI / HyperLan 2 */
8837 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
8838 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
8839 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
8840 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
8841 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
8842 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
8843 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
8844 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
8845 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
8846 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
8847 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
8848 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
8849
8850 /* 802.11 HyperLan 2 */
8851 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
8852 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
8853 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
8854 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
8855 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
8856 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
8857 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
8858 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
8859 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
8860 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
8861 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
8862 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
8863 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
8864 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
8865 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
8866 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
8867
8868 /* 802.11 UNII */
8869 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
8870 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
8871 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
8872 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
8873 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
8874 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
8875 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
8876 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
8877 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
8878 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
8879 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
8880
8881 /* 802.11 Japan */
8882 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
8883 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
8884 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
8885 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
8886 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
8887 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
8888 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
8889};
8890
8891/*
55f9321a 8892 * RF value list for rt3xxx
b6b561c3 8893 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
4da2933f 8894 */
55f9321a 8895static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 8896 {1, 241, 2, 2 },
8897 {2, 241, 2, 7 },
8898 {3, 242, 2, 2 },
8899 {4, 242, 2, 7 },
8900 {5, 243, 2, 2 },
8901 {6, 243, 2, 7 },
8902 {7, 244, 2, 2 },
8903 {8, 244, 2, 7 },
8904 {9, 245, 2, 2 },
8905 {10, 245, 2, 7 },
8906 {11, 246, 2, 2 },
8907 {12, 246, 2, 7 },
8908 {13, 247, 2, 2 },
8909 {14, 248, 2, 4 },
55f9321a
ID		 8910
8911 /* 802.11 UNI / HyperLan 2 */
8912 {36, 0x56, 0, 4},
8913 {38, 0x56, 0, 6},
8914 {40, 0x56, 0, 8},
8915 {44, 0x57, 0, 0},
8916 {46, 0x57, 0, 2},
8917 {48, 0x57, 0, 4},
8918 {52, 0x57, 0, 8},
8919 {54, 0x57, 0, 10},
8920 {56, 0x58, 0, 0},
8921 {60, 0x58, 0, 4},
8922 {62, 0x58, 0, 6},
8923 {64, 0x58, 0, 8},
8924
8925 /* 802.11 HyperLan 2 */
8926 {100, 0x5b, 0, 8},
8927 {102, 0x5b, 0, 10},
8928 {104, 0x5c, 0, 0},
8929 {108, 0x5c, 0, 4},
8930 {110, 0x5c, 0, 6},
8931 {112, 0x5c, 0, 8},
8932 {116, 0x5d, 0, 0},
8933 {118, 0x5d, 0, 2},
8934 {120, 0x5d, 0, 4},
8935 {124, 0x5d, 0, 8},
8936 {126, 0x5d, 0, 10},
8937 {128, 0x5e, 0, 0},
8938 {132, 0x5e, 0, 4},
8939 {134, 0x5e, 0, 6},
8940 {136, 0x5e, 0, 8},
8941 {140, 0x5f, 0, 0},
8942
8943 /* 802.11 UNII */
8944 {149, 0x5f, 0, 9},
8945 {151, 0x5f, 0, 11},
8946 {153, 0x60, 0, 1},
8947 {157, 0x60, 0, 5},
8948 {159, 0x60, 0, 7},
8949 {161, 0x60, 0, 9},
8950 {165, 0x61, 0, 1},
8951 {167, 0x61, 0, 3},
8952 {169, 0x61, 0, 5},
8953 {171, 0x61, 0, 7},
8954 {173, 0x61, 0, 9},
4da2933f
BZ		 8955};
8956
5c4412e0
DG		 8957/*
8958 * RF value list for rt3xxx with Xtal20MHz
8959 * Supports: 2.4 GHz (all) (RF3322)
8960 */
8961static const struct rf_channel rf_vals_3x_xtal20[] = {
8962 {1, 0xE2, 2, 0x14},
8963 {2, 0xE3, 2, 0x14},
8964 {3, 0xE4, 2, 0x14},
8965 {4, 0xE5, 2, 0x14},
8966 {5, 0xE6, 2, 0x14},
8967 {6, 0xE7, 2, 0x14},
8968 {7, 0xE8, 2, 0x14},
8969 {8, 0xE9, 2, 0x14},
8970 {9, 0xEA, 2, 0x14},
8971 {10, 0xEB, 2, 0x14},
8972 {11, 0xEC, 2, 0x14},
8973 {12, 0xED, 2, 0x14},
8974 {13, 0xEE, 2, 0x14},
8975 {14, 0xF0, 2, 0x18},
8976};
8977
7848b231
SG		 8978static const struct rf_channel rf_vals_5592_xtal20[] = {
8979 /* Channel, N, K, mod, R */
8980 {1, 482, 4, 10, 3},
8981 {2, 483, 4, 10, 3},
8982 {3, 484, 4, 10, 3},
8983 {4, 485, 4, 10, 3},
8984 {5, 486, 4, 10, 3},
8985 {6, 487, 4, 10, 3},
8986 {7, 488, 4, 10, 3},
8987 {8, 489, 4, 10, 3},
8988 {9, 490, 4, 10, 3},
8989 {10, 491, 4, 10, 3},
8990 {11, 492, 4, 10, 3},
8991 {12, 493, 4, 10, 3},
8992 {13, 494, 4, 10, 3},
8993 {14, 496, 8, 10, 3},
8994 {36, 172, 8, 12, 1},
8995 {38, 173, 0, 12, 1},
8996 {40, 173, 4, 12, 1},
8997 {42, 173, 8, 12, 1},
8998 {44, 174, 0, 12, 1},
8999 {46, 174, 4, 12, 1},
9000 {48, 174, 8, 12, 1},
9001 {50, 175, 0, 12, 1},
9002 {52, 175, 4, 12, 1},
9003 {54, 175, 8, 12, 1},
9004 {56, 176, 0, 12, 1},
9005 {58, 176, 4, 12, 1},
9006 {60, 176, 8, 12, 1},
9007 {62, 177, 0, 12, 1},
9008 {64, 177, 4, 12, 1},
9009 {100, 183, 4, 12, 1},
9010 {102, 183, 8, 12, 1},
9011 {104, 184, 0, 12, 1},
9012 {106, 184, 4, 12, 1},
9013 {108, 184, 8, 12, 1},
9014 {110, 185, 0, 12, 1},
9015 {112, 185, 4, 12, 1},
9016 {114, 185, 8, 12, 1},
9017 {116, 186, 0, 12, 1},
9018 {118, 186, 4, 12, 1},
9019 {120, 186, 8, 12, 1},
9020 {122, 187, 0, 12, 1},
9021 {124, 187, 4, 12, 1},
9022 {126, 187, 8, 12, 1},
9023 {128, 188, 0, 12, 1},
9024 {130, 188, 4, 12, 1},
9025 {132, 188, 8, 12, 1},
9026 {134, 189, 0, 12, 1},
9027 {136, 189, 4, 12, 1},
9028 {138, 189, 8, 12, 1},
9029 {140, 190, 0, 12, 1},
9030 {149, 191, 6, 12, 1},
9031 {151, 191, 10, 12, 1},
9032 {153, 192, 2, 12, 1},
9033 {155, 192, 6, 12, 1},
9034 {157, 192, 10, 12, 1},
9035 {159, 193, 2, 12, 1},
9036 {161, 193, 6, 12, 1},
9037 {165, 194, 2, 12, 1},
9038 {184, 164, 0, 12, 1},
9039 {188, 164, 4, 12, 1},
9040 {192, 165, 8, 12, 1},
9041 {196, 166, 0, 12, 1},
9042};
9043
9044static const struct rf_channel rf_vals_5592_xtal40[] = {
9045 /* Channel, N, K, mod, R */
9046 {1, 241, 2, 10, 3},
9047 {2, 241, 7, 10, 3},
9048 {3, 242, 2, 10, 3},
9049 {4, 242, 7, 10, 3},
9050 {5, 243, 2, 10, 3},
9051 {6, 243, 7, 10, 3},
9052 {7, 244, 2, 10, 3},
9053 {8, 244, 7, 10, 3},
9054 {9, 245, 2, 10, 3},
9055 {10, 245, 7, 10, 3},
9056 {11, 246, 2, 10, 3},
9057 {12, 246, 7, 10, 3},
9058 {13, 247, 2, 10, 3},
9059 {14, 248, 4, 10, 3},
9060 {36, 86, 4, 12, 1},
9061 {38, 86, 6, 12, 1},
9062 {40, 86, 8, 12, 1},
9063 {42, 86, 10, 12, 1},
9064 {44, 87, 0, 12, 1},
9065 {46, 87, 2, 12, 1},
9066 {48, 87, 4, 12, 1},
9067 {50, 87, 6, 12, 1},
9068 {52, 87, 8, 12, 1},
9069 {54, 87, 10, 12, 1},
9070 {56, 88, 0, 12, 1},
9071 {58, 88, 2, 12, 1},
9072 {60, 88, 4, 12, 1},
9073 {62, 88, 6, 12, 1},
9074 {64, 88, 8, 12, 1},
9075 {100, 91, 8, 12, 1},
9076 {102, 91, 10, 12, 1},
9077 {104, 92, 0, 12, 1},
9078 {106, 92, 2, 12, 1},
9079 {108, 92, 4, 12, 1},
9080 {110, 92, 6, 12, 1},
9081 {112, 92, 8, 12, 1},
9082 {114, 92, 10, 12, 1},
9083 {116, 93, 0, 12, 1},
9084 {118, 93, 2, 12, 1},
9085 {120, 93, 4, 12, 1},
9086 {122, 93, 6, 12, 1},
9087 {124, 93, 8, 12, 1},
9088 {126, 93, 10, 12, 1},
9089 {128, 94, 0, 12, 1},
9090 {130, 94, 2, 12, 1},
9091 {132, 94, 4, 12, 1},
9092 {134, 94, 6, 12, 1},
9093 {136, 94, 8, 12, 1},
9094 {138, 94, 10, 12, 1},
9095 {140, 95, 0, 12, 1},
9096 {149, 95, 9, 12, 1},
9097 {151, 95, 11, 12, 1},
9098 {153, 96, 1, 12, 1},
9099 {155, 96, 3, 12, 1},
9100 {157, 96, 5, 12, 1},
9101 {159, 96, 7, 12, 1},
9102 {161, 96, 9, 12, 1},
9103 {165, 97, 1, 12, 1},
9104 {184, 82, 0, 12, 1},
9105 {188, 82, 4, 12, 1},
9106 {192, 82, 8, 12, 1},
9107 {196, 83, 0, 12, 1},
9108};
9109
41977e86
RY		 9110static const struct rf_channel rf_vals_7620[] = {
9111 {1, 0x50, 0x99, 0x99, 1},
9112 {2, 0x50, 0x44, 0x44, 2},
9113 {3, 0x50, 0xEE, 0xEE, 2},
9114 {4, 0x50, 0x99, 0x99, 3},
9115 {5, 0x51, 0x44, 0x44, 0},
9116 {6, 0x51, 0xEE, 0xEE, 0},
9117 {7, 0x51, 0x99, 0x99, 1},
9118 {8, 0x51, 0x44, 0x44, 2},
9119 {9, 0x51, 0xEE, 0xEE, 2},
9120 {10, 0x51, 0x99, 0x99, 3},
9121 {11, 0x52, 0x44, 0x44, 0},
9122 {12, 0x52, 0xEE, 0xEE, 0},
9123 {13, 0x52, 0x99, 0x99, 1},
9124 {14, 0x52, 0x33, 0x33, 3},
9125};
9126
ad417a53 9127static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 9128{
4da2933f
BZ		 9129 struct hw_mode_spec *spec = &rt2x00dev->spec;
9130 struct channel_info *info;
8d1331b3
ID		 9131 char *default_power1;
9132 char *default_power2;
c0a14369 9133 char *default_power3;
cea5b03d 9134 unsigned int i, tx_chains, rx_chains;
7848b231 9135 u32 reg;
4da2933f 9136
93b6bd26 9137 /*
58e33a21 9138 * Disable powersaving as default.
93b6bd26 9139 */
58e33a21 9140 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
93b6bd26 9141
01d97ef4
SG		 9142 /*
9143 * Change default retry settings to values corresponding more closely
9144 * to rate[0].count setting of minstrel rate control algorithm.
9145 */
9146 rt2x00dev->hw->wiphy->retry_short = 2;
9147 rt2x00dev->hw->wiphy->retry_long = 2;
9148
4da2933f
BZ		 9149 /*
9150 * Initialize all hw fields.
9151 */
30686bf7
JB		 9152 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9153 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9154 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9155 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9156 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9d4f09b8 9157
5a5b6ed6
HS		 9158 /*
9159 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9160 * unless we are capable of sending the buffered frames out after the
9161 * DTIM transmission using rt2x00lib_beacondone. This will send out
9162 * multicast and broadcast traffic immediately instead of buffering it
9163 * infinitly and thus dropping it after some time.
9164 */
9165 if (!rt2x00_is_usb(rt2x00dev))
30686bf7 9166 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
4da2933f 9167
2557654d
CYY		 9168 /* Set MFP if HW crypto is disabled. */
9169 if (rt2800_hwcrypt_disabled(rt2x00dev))
9170 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9171
4da2933f
BZ		 9172 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9173 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 9174 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 9175 EEPROM_MAC_ADDR_0));
9176
3f2bee24
HS		 9177 /*
9178 * As rt2800 has a global fallback table we cannot specify
9179 * more then one tx rate per frame but since the hw will
9180 * try several rates (based on the fallback table) we should
ba3b9e5e 9181 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 9182 * we are going to try. Otherwise mac80211 will truncate our
9183 * reported tx rates and the rc algortihm will end up with
9184 * incorrect data.
9185 */
ba3b9e5e
HS		 9186 rt2x00dev->hw->max_rates = 1;
9187 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 9188 rt2x00dev->hw->max_rate_tries = 1;
9189
4da2933f
BZ		 9190 /*
9191 * Initialize hw_mode information.
9192 */
4da2933f
BZ		 9193 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
9194
4a32c36d
GJ		 9195 switch (rt2x00dev->chip.rf) {
9196 case RF2720:
9197 case RF2820:
4da2933f
BZ		 9198 spec->num_channels = 14;
9199 spec->channels = rf_vals;
4a32c36d
GJ		 9200 break;
9201
9202 case RF2750:
9203 case RF2850:
4da2933f
BZ		 9204 spec->num_channels = ARRAY_SIZE(rf_vals);
9205 spec->channels = rf_vals;
4a32c36d
GJ		 9206 break;
9207
9208 case RF2020:
9209 case RF3020:
9210 case RF3021:
9211 case RF3022:
9212 case RF3070:
9213 case RF3290:
9214 case RF3320:
9215 case RF3322:
98e71f44 9216 case RF5350:
4a32c36d 9217 case RF5360:
ac0372ab 9218 case RF5362:
4a32c36d
GJ		 9219 case RF5370:
9220 case RF5372:
9221 case RF5390:
9222 case RF5392:
55f9321a 9223 spec->num_channels = 14;
5c4412e0
DG		 9224 if (rt2800_clk_is_20mhz(rt2x00dev))
9225 spec->channels = rf_vals_3x_xtal20;
9226 else
9227 spec->channels = rf_vals_3x;
4a32c36d
GJ		 9228 break;
9229
41977e86
RY		 9230 case RF7620:
9231 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
9232 spec->channels = rf_vals_7620;
9233 break;
9234
4a32c36d
GJ		 9235 case RF3052:
9236 case RF3053:
55f9321a
ID		 9237 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
9238 spec->channels = rf_vals_3x;
4a32c36d 9239 break;
7848b231 9240
4a32c36d 9241 case RF5592:
7848b231
SG		 9242 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
9243 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
9244 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
9245 spec->channels = rf_vals_5592_xtal40;
9246 } else {
9247 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
9248 spec->channels = rf_vals_5592_xtal20;
9249 }
4a32c36d 9250 break;
4da2933f
BZ		 9251 }
9252
53216d6a
SG		 9253 if (WARN_ON_ONCE(!spec->channels))
9254 return -ENODEV;
9255
53c5a099
GJ		 9256 spec->supported_bands = SUPPORT_BAND_2GHZ;
9257 if (spec->num_channels > 14)
9258 spec->supported_bands |= SUPPORT_BAND_5GHZ;
9259
4da2933f
BZ		 9260 /*
9261 * Initialize HT information.
9262 */
5122d898 9263 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 9264 spec->ht.ht_supported = true;
9265 else
9266 spec->ht.ht_supported = false;
9267
4da2933f 9268 spec->ht.cap =
06443e46 9269 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 9270 IEEE80211_HT_CAP_GRN_FLD |
9271 IEEE80211_HT_CAP_SGI_20 |
aa674631 9272 IEEE80211_HT_CAP_SGI_40;
22cabaa6 9273
cea5b03d
SG		 9274 tx_chains = rt2x00dev->default_ant.tx_chain_num;
9275 rx_chains = rt2x00dev->default_ant.rx_chain_num;
9276
9277 if (tx_chains >= 2)
22cabaa6
HS		 9278 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
9279
cea5b03d 9280 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
aa674631 9281
a08b9819 9282 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
4da2933f 9283 spec->ht.ampdu_density = 4;
cea5b03d
SG		 9284 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
9285 if (tx_chains != rx_chains) {
9286 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
9287 spec->ht.mcs.tx_params |=
9288 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
9289 }
4da2933f 9290
cea5b03d 9291 switch (rx_chains) {
4da2933f
BZ		 9292 case 3:
9293 spec->ht.mcs.rx_mask[2] = 0xff;
9294 case 2:
9295 spec->ht.mcs.rx_mask[1] = 0xff;
9296 case 1:
9297 spec->ht.mcs.rx_mask[0] = 0xff;
9298 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
9299 break;
9300 }
9301
9302 /*
9303 * Create channel information array
9304 */
baeb2ffa 9305 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 9306 if (!info)
9307 return -ENOMEM;
9308
9309 spec->channels_info = info;
9310
3e38d3da
GJ		 9311 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
9312 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 9313
c0a14369
GJ		 9314 if (rt2x00dev->default_ant.tx_chain_num > 2)
9315 default_power3 = rt2800_eeprom_addr(rt2x00dev,
9316 EEPROM_EXT_TXPOWER_BG3);
9317 else
9318 default_power3 = NULL;
9319
4da2933f 9320 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 9321 info[i].default_power1 = default_power1[i];
9322 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 9323 if (default_power3)
9324 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 9325 }
9326
9327 if (spec->num_channels > 14) {
3e38d3da
GJ		 9328 default_power1 = rt2800_eeprom_addr(rt2x00dev,
9329 EEPROM_TXPOWER_A1);
9330 default_power2 = rt2800_eeprom_addr(rt2x00dev,
9331 EEPROM_TXPOWER_A2);
4da2933f 9332
c0a14369
GJ		 9333 if (rt2x00dev->default_ant.tx_chain_num > 2)
9334 default_power3 =
9335 rt2800_eeprom_addr(rt2x00dev,
9336 EEPROM_EXT_TXPOWER_A3);
9337 else
9338 default_power3 = NULL;
9339
4da2933f 9340 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 9341 info[i].default_power1 = default_power1[i - 14];
9342 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 9343 if (default_power3)
9344 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 9345 }
9346 }
9347
2e9c43dd
JL		 9348 switch (rt2x00dev->chip.rf) {
9349 case RF2020:
9350 case RF3020:
9351 case RF3021:
9352 case RF3022:
9353 case RF3320:
9354 case RF3052:
1095df07 9355 case RF3053:
3b9b74ba 9356 case RF3070:
a89534ed 9357 case RF3290:
98e71f44 9358 case RF5350:
ccf91bd6 9359 case RF5360:
ac0372ab 9360 case RF5362:
2e9c43dd
JL		 9361 case RF5370:
9362 case RF5372:
9363 case RF5390:
cff3d1f0 9364 case RF5392:
24d42ef3 9365 case RF5592:
41977e86 9366 case RF7620:
2e9c43dd
JL		 9367 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
9368 break;
9369 }
9370
4da2933f
BZ		 9371 return 0;
9372}
ad417a53 9373
cbafb601
GJ		 9374static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
9375{
9376 u32 reg;
9377 u32 rt;
9378 u32 rev;
9379
9380 if (rt2x00_rt(rt2x00dev, RT3290))
9381 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
9382 else
9383 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
9384
9385 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
9386 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
9387
9388 switch (rt) {
9389 case RT2860:
9390 case RT2872:
9391 case RT2883:
9392 case RT3070:
9393 case RT3071:
9394 case RT3090:
9395 case RT3290:
9396 case RT3352:
9397 case RT3390:
9398 case RT3572:
2dc2bd2f 9399 case RT3593:
98e71f44 9400 case RT5350:
cbafb601
GJ		 9401 case RT5390:
9402 case RT5392:
9403 case RT5592:
9404 break;
9405 default:
ec9c4989
JP		 9406 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
9407 rt, rev);
cbafb601
GJ		 9408 return -ENODEV;
9409 }
9410
41977e86
RY		 9411 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
9412 rt = RT6352;
9413
cbafb601
GJ		 9414 rt2x00_set_rt(rt2x00dev, rt, rev);
9415
9416 return 0;
9417}
9418
ad417a53
GW		 9419int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
9420{
9421 int retval;
9422 u32 reg;
9423
cbafb601
GJ		 9424 retval = rt2800_probe_rt(rt2x00dev);
9425 if (retval)
9426 return retval;
9427
ad417a53
GW		 9428 /*
9429 * Allocate eeprom data.
9430 */
9431 retval = rt2800_validate_eeprom(rt2x00dev);
9432 if (retval)
9433 return retval;
9434
9435 retval = rt2800_init_eeprom(rt2x00dev);
9436 if (retval)
9437 return retval;
9438
9439 /*
9440 * Enable rfkill polling by setting GPIO direction of the
9441 * rfkill switch GPIO pin correctly.
9442 */
9443 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
9444 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
9445 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
9446
9447 /*
9448 * Initialize hw specifications.
9449 */
9450 retval = rt2800_probe_hw_mode(rt2x00dev);
9451 if (retval)
9452 return retval;
9453
9454 /*
9455 * Set device capabilities.
9456 */
9457 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
9458 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
9459 if (!rt2x00_is_usb(rt2x00dev))
9460 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9461
9462 /*
9463 * Set device requirements.
9464 */
9465 if (!rt2x00_is_soc(rt2x00dev))
9466 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
9467 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
9468 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
9469 if (!rt2800_hwcrypt_disabled(rt2x00dev))
9470 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
9471 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
9472 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
9473 if (rt2x00_is_usb(rt2x00dev))
9474 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
9475 else {
9476 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
9477 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
9478 }
9479
9480 /*
9481 * Set the rssi offset.
9482 */
9483 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
9484
9485 return 0;
9486}
9487EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 9488
2ce33995
BZ		 9489/*
9490 * IEEE80211 stack callback functions.
9491 */
9352c19f
JB		 9492void rt2800_get_key_seq(struct ieee80211_hw *hw,
9493 struct ieee80211_key_conf *key,
9494 struct ieee80211_key_seq *seq)
2ce33995
BZ		 9495{
9496 struct rt2x00_dev *rt2x00dev = hw->priv;
9497 struct mac_iveiv_entry iveiv_entry;
9498 u32 offset;
9499
9352c19f
JB		 9500 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
9501 return;
9502
9503 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
2ce33995
BZ		 9504 rt2800_register_multiread(rt2x00dev, offset,
9505 &iveiv_entry, sizeof(iveiv_entry));
9506
9352c19f
JB		 9507 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
9508 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
2ce33995 9509}
9352c19f 9510EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
2ce33995 9511
e783619e 9512int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 9513{
9514 struct rt2x00_dev *rt2x00dev = hw->priv;
9515 u32 reg;
9516 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
9517
9518 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
9519 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
9520 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
9521
9522 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
9523 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
9524 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
9525
9526 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
9527 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
9528 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
9529
9530 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
9531 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
9532 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
9533
9534 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
9535 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
9536 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
9537
9538 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
9539 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
9540 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
9541
9542 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
9543 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
9544 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
9545
9546 return 0;
9547}
e783619e 9548EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 9549
8a3a3c85
EP		 9550int rt2800_conf_tx(struct ieee80211_hw *hw,
9551 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 9552 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 9553{
9554 struct rt2x00_dev *rt2x00dev = hw->priv;
9555 struct data_queue *queue;
9556 struct rt2x00_field32 field;
9557 int retval;
9558 u32 reg;
9559 u32 offset;
9560
9561 /*
9562 * First pass the configuration through rt2x00lib, that will
9563 * update the queue settings and validate the input. After that
9564 * we are free to update the registers based on the value
9565 * in the queue parameter.
9566 */
8a3a3c85 9567 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 9568 if (retval)
9569 return retval;
9570
9571 /*
9572 * We only need to perform additional register initialization
9573 * for WMM queues/
9574 */
9575 if (queue_idx >= 4)
9576 return 0;
9577
11f818e0 9578 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 9579
9580 /* Update WMM TXOP register */
9581 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
9582 field.bit_offset = (queue_idx & 1) * 16;
9583 field.bit_mask = 0xffff << field.bit_offset;
9584
9585 rt2800_register_read(rt2x00dev, offset, &reg);
9586 rt2x00_set_field32(&reg, field, queue->txop);
9587 rt2800_register_write(rt2x00dev, offset, reg);
9588
9589 /* Update WMM registers */
9590 field.bit_offset = queue_idx * 4;
9591 field.bit_mask = 0xf << field.bit_offset;
9592
9593 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
9594 rt2x00_set_field32(&reg, field, queue->aifs);
9595 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
9596
9597 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
9598 rt2x00_set_field32(&reg, field, queue->cw_min);
9599 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
9600
9601 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
9602 rt2x00_set_field32(&reg, field, queue->cw_max);
9603 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
9604
9605 /* Update EDCA registers */
9606 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
9607
9608 rt2800_register_read(rt2x00dev, offset, &reg);
9609 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
9610 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
9611 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
9612 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
9613 rt2800_register_write(rt2x00dev, offset, reg);
9614
9615 return 0;
9616}
e783619e 9617EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 9618
37a41b4a 9619u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 9620{
9621 struct rt2x00_dev *rt2x00dev = hw->priv;
9622 u64 tsf;
9623 u32 reg;
9624
9625 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
9626 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
9627 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
9628 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
9629
9630 return tsf;
9631}
e783619e 9632EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 9633
e783619e 9634int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 9635 struct ieee80211_ampdu_params *params)
1df90809 9636{
50ea05ef
SS		 9637 struct ieee80211_sta *sta = params->sta;
9638 enum ieee80211_ampdu_mlme_action action = params->action;
9639 u16 tid = params->tid;
af35323d 9640 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 9641 int ret = 0;
9642
af35323d
HS		 9643 /*
9644 * Don't allow aggregation for stations the hardware isn't aware
9645 * of because tx status reports for frames to an unknown station
ed8e0ed5
SG		 9646 * always contain wcid=WCID_END+1 and thus we can't distinguish
9647 * between multiple stations which leads to unwanted situations
9648 * when the hw reorders frames due to aggregation.
af35323d 9649 */
ed8e0ed5 9650 if (sta_priv->wcid > WCID_END)
af35323d
HS		 9651 return 1;
9652
1df90809
HS		 9653 switch (action) {
9654 case IEEE80211_AMPDU_RX_START:
9655 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 9656 /*
9657 * The hw itself takes care of setting up BlockAck mechanisms.
9658 * So, we only have to allow mac80211 to nagotiate a BlockAck
9659 * agreement. Once that is done, the hw will BlockAck incoming
9660 * AMPDUs without further setup.
9661 */
1df90809
HS		 9662 break;
9663 case IEEE80211_AMPDU_TX_START:
9664 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9665 break;
18b559d5
JB		 9666 case IEEE80211_AMPDU_TX_STOP_CONT:
9667 case IEEE80211_AMPDU_TX_STOP_FLUSH:
9668 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 9669 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9670 break;
9671 case IEEE80211_AMPDU_TX_OPERATIONAL:
9672 break;
9673 default:
ec9c4989
JP		 9674 rt2x00_warn((struct rt2x00_dev *)hw->priv,
9675 "Unknown AMPDU action\n");
1df90809
HS		 9676 }
9677
9678 return ret;
9679}
e783619e 9680EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 9681
977206d7
HS		 9682int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
9683 struct survey_info *survey)
9684{
9685 struct rt2x00_dev *rt2x00dev = hw->priv;
9686 struct ieee80211_conf *conf = &hw->conf;
9687 u32 idle, busy, busy_ext;
9688
9689 if (idx != 0)
9690 return -ENOENT;
9691
675a0b04 9692 survey->channel = conf->chandef.chan;
977206d7
HS		 9693
9694 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
9695 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
9696 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
9697
9698 if (idle || busy) {
4ed20beb
JB		 9699 survey->filled = SURVEY_INFO_TIME |
9700 SURVEY_INFO_TIME_BUSY |
9701 SURVEY_INFO_TIME_EXT_BUSY;
977206d7 9702
4ed20beb
JB		 9703 survey->time = (idle + busy) / 1000;
9704 survey->time_busy = busy / 1000;
9705 survey->time_ext_busy = busy_ext / 1000;
977206d7
HS		 9706 }
9707
9931df26
HS		 9708 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
9709 survey->filled |= SURVEY_INFO_IN_USE;
9710
977206d7
HS		 9711 return 0;
9712
9713}
9714EXPORT_SYMBOL_GPL(rt2800_get_survey);
9715
a5ea2f02
ID		 9716MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
9717MODULE_VERSION(DRV_VERSION);
9718MODULE_DESCRIPTION("Ralink RT2800 library");
9719MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)