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cfg80211: remove enum ieee80211_band
[linux-block.git] / drivers / net / wireless / ralink / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
a05b8c58 27 along with this program; if not, see <http://www.gnu.org/licenses/>.
89297425
BZ		 28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
f31c9a8c 35#include <linux/crc-ccitt.h>
89297425
BZ		 36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
baff8006
HS		 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
ec9c4989 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 82 return false;
83}
84
fcf51541
BZ		 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
89297425
BZ		 87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 103
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 }
106
107 mutex_unlock(&rt2x00dev->csr_mutex);
108}
89297425 109
fcf51541
BZ		 110static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, u8 *value)
89297425
BZ		 112{
113 u32 reg;
114
115 mutex_lock(&rt2x00dev->csr_mutex);
116
117 /*
118 * Wait until the BBP becomes available, afterwards we
119 * can safely write the read request into the register.
120 * After the data has been written, we wait until hardware
121 * returns the correct value, if at any time the register
122 * doesn't become available in time, reg will be 0xffffffff
123 * which means we return 0xff to the caller.
124 */
125 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 131
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
133
134 WAIT_FOR_BBP(rt2x00dev, &reg);
135 }
136
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
138
139 mutex_unlock(&rt2x00dev->csr_mutex);
140}
89297425 141
fcf51541
BZ		 142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
143 const unsigned int word, const u8 value)
89297425
BZ		 144{
145 u32 reg;
146
147 mutex_lock(&rt2x00dev->csr_mutex);
148
149 /*
150 * Wait until the RFCSR becomes available, afterwards we
151 * can safely write the new data into the register.
152 */
153 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
154 reg = 0;
155 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
156 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
159
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
161 }
162
163 mutex_unlock(&rt2x00dev->csr_mutex);
164}
89297425 165
fcf51541
BZ		 166static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
167 const unsigned int word, u8 *value)
89297425
BZ		 168{
169 u32 reg;
170
171 mutex_lock(&rt2x00dev->csr_mutex);
172
173 /*
174 * Wait until the RFCSR becomes available, afterwards we
175 * can safely write the read request into the register.
176 * After the data has been written, we wait until hardware
177 * returns the correct value, if at any time the register
178 * doesn't become available in time, reg will be 0xffffffff
179 * which means we return 0xff to the caller.
180 */
181 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
182 reg = 0;
183 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
184 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
186
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
188
189 WAIT_FOR_RFCSR(rt2x00dev, &reg);
190 }
191
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
193
194 mutex_unlock(&rt2x00dev->csr_mutex);
195}
89297425 196
fcf51541
BZ		 197static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
89297425
BZ		 199{
200 u32 reg;
201
202 mutex_lock(&rt2x00dev->csr_mutex);
203
204 /*
205 * Wait until the RF becomes available, afterwards we
206 * can safely write the new data into the register.
207 */
208 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
209 reg = 0;
210 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
214
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
216 rt2x00_rf_write(rt2x00dev, word, value);
217 }
218
219 mutex_unlock(&rt2x00dev->csr_mutex);
220}
89297425 221
379448fe
GJ		 222static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
223 [EEPROM_CHIP_ID] = 0x0000,
224 [EEPROM_VERSION] = 0x0001,
225 [EEPROM_MAC_ADDR_0] = 0x0002,
226 [EEPROM_MAC_ADDR_1] = 0x0003,
227 [EEPROM_MAC_ADDR_2] = 0x0004,
228 [EEPROM_NIC_CONF0] = 0x001a,
229 [EEPROM_NIC_CONF1] = 0x001b,
230 [EEPROM_FREQ] = 0x001d,
231 [EEPROM_LED_AG_CONF] = 0x001e,
232 [EEPROM_LED_ACT_CONF] = 0x001f,
233 [EEPROM_LED_POLARITY] = 0x0020,
234 [EEPROM_NIC_CONF2] = 0x0021,
235 [EEPROM_LNA] = 0x0022,
236 [EEPROM_RSSI_BG] = 0x0023,
237 [EEPROM_RSSI_BG2] = 0x0024,
238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
239 [EEPROM_RSSI_A] = 0x0025,
240 [EEPROM_RSSI_A2] = 0x0026,
241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
243 [EEPROM_TXPOWER_DELTA] = 0x0028,
244 [EEPROM_TXPOWER_BG1] = 0x0029,
245 [EEPROM_TXPOWER_BG2] = 0x0030,
246 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
247 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
248 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
249 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
250 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
251 [EEPROM_TXPOWER_A1] = 0x003c,
252 [EEPROM_TXPOWER_A2] = 0x0053,
253 [EEPROM_TSSI_BOUND_A1] = 0x006a,
254 [EEPROM_TSSI_BOUND_A2] = 0x006b,
255 [EEPROM_TSSI_BOUND_A3] = 0x006c,
256 [EEPROM_TSSI_BOUND_A4] = 0x006d,
257 [EEPROM_TSSI_BOUND_A5] = 0x006e,
258 [EEPROM_TXPOWER_BYRATE] = 0x006f,
259 [EEPROM_BBP_START] = 0x0078,
260};
261
fa31d157
GJ		 262static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
263 [EEPROM_CHIP_ID] = 0x0000,
264 [EEPROM_VERSION] = 0x0001,
265 [EEPROM_MAC_ADDR_0] = 0x0002,
266 [EEPROM_MAC_ADDR_1] = 0x0003,
267 [EEPROM_MAC_ADDR_2] = 0x0004,
268 [EEPROM_NIC_CONF0] = 0x001a,
269 [EEPROM_NIC_CONF1] = 0x001b,
270 [EEPROM_NIC_CONF2] = 0x001c,
271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
272 [EEPROM_FREQ] = 0x0022,
273 [EEPROM_LED_AG_CONF] = 0x0023,
274 [EEPROM_LED_ACT_CONF] = 0x0024,
275 [EEPROM_LED_POLARITY] = 0x0025,
276 [EEPROM_LNA] = 0x0026,
277 [EEPROM_EXT_LNA2] = 0x0027,
278 [EEPROM_RSSI_BG] = 0x0028,
fa31d157 279 [EEPROM_RSSI_BG2] = 0x0029,
fa31d157
GJ		 280 [EEPROM_RSSI_A] = 0x002a,
281 [EEPROM_RSSI_A2] = 0x002b,
fa31d157
GJ		 282 [EEPROM_TXPOWER_BG1] = 0x0030,
283 [EEPROM_TXPOWER_BG2] = 0x0037,
284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
285 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
286 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
287 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
288 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
289 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
290 [EEPROM_TXPOWER_A1] = 0x004b,
291 [EEPROM_TXPOWER_A2] = 0x0065,
292 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
293 [EEPROM_TSSI_BOUND_A1] = 0x009a,
294 [EEPROM_TSSI_BOUND_A2] = 0x009b,
295 [EEPROM_TSSI_BOUND_A3] = 0x009c,
296 [EEPROM_TSSI_BOUND_A4] = 0x009d,
297 [EEPROM_TSSI_BOUND_A5] = 0x009e,
298 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
299};
300
379448fe
GJ		 301static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
302 const enum rt2800_eeprom_word word)
303{
304 const unsigned int *map;
305 unsigned int index;
306
307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
308 "%s: invalid EEPROM word %d\n",
309 wiphy_name(rt2x00dev->hw->wiphy), word))
310 return 0;
311
fa31d157
GJ		 312 if (rt2x00_rt(rt2x00dev, RT3593))
313 map = rt2800_eeprom_map_ext;
314 else
315 map = rt2800_eeprom_map;
316
379448fe
GJ		 317 index = map[word];
318
319 /* Index 0 is valid only for EEPROM_CHIP_ID.
320 * Otherwise it means that the offset of the
321 * given word is not initialized in the map,
322 * or that the field is not usable on the
323 * actual chipset.
324 */
325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
326 "%s: invalid access of EEPROM word %d\n",
327 wiphy_name(rt2x00dev->hw->wiphy), word);
328
329 return index;
330}
331
3e38d3da
GJ		 332static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
333 const enum rt2800_eeprom_word word)
334{
379448fe
GJ		 335 unsigned int index;
336
337 index = rt2800_eeprom_word_index(rt2x00dev, word);
338 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 339}
340
341static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
342 const enum rt2800_eeprom_word word, u16 *data)
343{
379448fe
GJ		 344 unsigned int index;
345
346 index = rt2800_eeprom_word_index(rt2x00dev, word);
347 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 348}
349
350static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
351 const enum rt2800_eeprom_word word, u16 data)
352{
379448fe
GJ		 353 unsigned int index;
354
355 index = rt2800_eeprom_word_index(rt2x00dev, word);
356 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 357}
358
022138ca
GJ		 359static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
360 const enum rt2800_eeprom_word array,
361 unsigned int offset,
362 u16 *data)
363{
379448fe
GJ		 364 unsigned int index;
365
366 index = rt2800_eeprom_word_index(rt2x00dev, array);
367 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 368}
369
16ebd608
WH		 370static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
371{
372 u32 reg;
373 int i, count;
374
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
376 if (rt2x00_get_field32(reg, WLAN_EN))
377 return 0;
378
379 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
380 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
381 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
382 rt2x00_set_field32(&reg, WLAN_EN, 1);
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
384
385 udelay(REGISTER_BUSY_DELAY);
386
387 count = 0;
388 do {
389 /*
390 * Check PLL_LD & XTAL_RDY.
391 */
392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
393 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
394 if (rt2x00_get_field32(reg, PLL_LD) &&
395 rt2x00_get_field32(reg, XTAL_RDY))
396 break;
397 udelay(REGISTER_BUSY_DELAY);
398 }
399
400 if (i >= REGISTER_BUSY_COUNT) {
401
402 if (count >= 10)
403 return -EIO;
404
405 rt2800_register_write(rt2x00dev, 0x58, 0x018);
406 udelay(REGISTER_BUSY_DELAY);
407 rt2800_register_write(rt2x00dev, 0x58, 0x418);
408 udelay(REGISTER_BUSY_DELAY);
409 rt2800_register_write(rt2x00dev, 0x58, 0x618);
410 udelay(REGISTER_BUSY_DELAY);
411 count++;
412 } else {
413 count = 0;
414 }
415
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
417 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
418 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
419 rt2x00_set_field32(&reg, WLAN_RESET, 1);
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
421 udelay(10);
422 rt2x00_set_field32(&reg, WLAN_RESET, 0);
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
424 udelay(10);
425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
426 } while (count != 0);
427
428 return 0;
429}
430
89297425
BZ		 431void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
432 const u8 command, const u8 token,
433 const u8 arg0, const u8 arg1)
434{
435 u32 reg;
436
ee303e54 437 /*
cea90e55 438 * SOC devices don't support MCU requests.
ee303e54 439 */
cea90e55 440 if (rt2x00_is_soc(rt2x00dev))
ee303e54 441 return;
89297425
BZ		 442
443 mutex_lock(&rt2x00dev->csr_mutex);
444
445 /*
446 * Wait until the MCU becomes available, afterwards we
447 * can safely write the new data into the register.
448 */
449 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
450 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
451 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
452 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
453 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
455
456 reg = 0;
457 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
459 }
460
461 mutex_unlock(&rt2x00dev->csr_mutex);
462}
463EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 464
5ffddc49
ID		 465int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
466{
467 unsigned int i = 0;
468 u32 reg;
469
470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
471 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
472 if (reg && reg != ~0)
473 return 0;
474 msleep(1);
475 }
476
ec9c4989 477 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 478 return -EBUSY;
479}
480EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
481
67a4c1e2
GW		 482int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
483{
484 unsigned int i;
485 u32 reg;
486
08e53100
HS		 487 /*
488 * Some devices are really slow to respond here. Wait a whole second
489 * before timing out.
490 */
67a4c1e2
GW		 491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
495 return 0;
496
08e53100 497 msleep(10);
67a4c1e2
GW		 498 }
499
ec9c4989 500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 501 return -EACCES;
502}
503EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
504
f7b395e9
JK		 505void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
506{
507 u32 reg;
508
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
510 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
511 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
516}
517EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
518
ae1b1c5d
GJ		 519void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
520 unsigned short *txwi_size,
521 unsigned short *rxwi_size)
522{
523 switch (rt2x00dev->chip.rt) {
524 case RT3593:
525 *txwi_size = TXWI_DESC_SIZE_4WORDS;
526 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
527 break;
528
529 case RT5592:
530 *txwi_size = TXWI_DESC_SIZE_5WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
532 break;
533
534 default:
535 *txwi_size = TXWI_DESC_SIZE_4WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
537 break;
538 }
539}
540EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
541
f31c9a8c
ID		 542static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
543{
544 u16 fw_crc;
545 u16 crc;
546
547 /*
548 * The last 2 bytes in the firmware array are the crc checksum itself,
549 * this means that we should never pass those 2 bytes to the crc
550 * algorithm.
551 */
552 fw_crc = (data[len - 2] << 8 | data[len - 1]);
553
554 /*
555 * Use the crc ccitt algorithm.
556 * This will return the same value as the legacy driver which
557 * used bit ordering reversion on the both the firmware bytes
558 * before input input as well as on the final output.
559 * Obviously using crc ccitt directly is much more efficient.
560 */
561 crc = crc_ccitt(~0, data, len - 2);
562
563 /*
564 * There is a small difference between the crc-itu-t + bitrev and
565 * the crc-ccitt crc calculation. In the latter method the 2 bytes
566 * will be swapped, use swab16 to convert the crc to the correct
567 * value.
568 */
569 crc = swab16(crc);
570
571 return fw_crc == crc;
572}
573
574int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
575 const u8 *data, const size_t len)
576{
577 size_t offset = 0;
578 size_t fw_len;
579 bool multiple;
580
581 /*
582 * PCI(e) & SOC devices require firmware with a length
583 * of 8kb. USB devices require firmware files with a length
584 * of 4kb. Certain USB chipsets however require different firmware,
585 * which Ralink only provides attached to the original firmware
586 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 587 * which is a multiple of 4kb. The firmware for rt3290 chip also
588 * have a length which is a multiple of 4kb.
f31c9a8c 589 */
a89534ed 590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 591 fw_len = 4096;
a89534ed 592 else
f31c9a8c 593 fw_len = 8192;
f31c9a8c 594
a89534ed 595 multiple = true;
f31c9a8c
ID		 596 /*
597 * Validate the firmware length
598 */
599 if (len != fw_len && (!multiple || (len % fw_len) != 0))
600 return FW_BAD_LENGTH;
601
602 /*
603 * Check if the chipset requires one of the upper parts
604 * of the firmware.
605 */
606 if (rt2x00_is_usb(rt2x00dev) &&
607 !rt2x00_rt(rt2x00dev, RT2860) &&
608 !rt2x00_rt(rt2x00dev, RT2872) &&
609 !rt2x00_rt(rt2x00dev, RT3070) &&
610 ((len / fw_len) == 1))
611 return FW_BAD_VERSION;
612
613 /*
614 * 8kb firmware files must be checked as if it were
615 * 2 separate firmware files.
616 */
617 while (offset < len) {
618 if (!rt2800_check_firmware_crc(data + offset, fw_len))
619 return FW_BAD_CRC;
620
621 offset += fw_len;
622 }
623
624 return FW_OK;
625}
626EXPORT_SYMBOL_GPL(rt2800_check_firmware);
627
628int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
629 const u8 *data, const size_t len)
630{
631 unsigned int i;
632 u32 reg;
16ebd608
WH		 633 int retval;
634
635 if (rt2x00_rt(rt2x00dev, RT3290)) {
636 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
637 if (retval)
638 return -EBUSY;
639 }
f31c9a8c
ID		 640
641 /*
b9eca242
ID		 642 * If driver doesn't wake up firmware here,
643 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 644 */
b9eca242 645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 646
f31c9a8c
ID		 647 /*
648 * Wait for stable hardware.
649 */
5ffddc49 650 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 651 return -EBUSY;
f31c9a8c 652
adde5882 653 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 654 if (rt2x00_rt(rt2x00dev, RT3290) ||
655 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 656 rt2x00_rt(rt2x00dev, RT5390) ||
657 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 658 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
659 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
660 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
662 }
f31c9a8c 663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 664 }
f31c9a8c 665
b7e1d225
JK		 666 rt2800_disable_wpdma(rt2x00dev);
667
f31c9a8c
ID		 668 /*
669 * Write firmware to the device.
670 */
671 rt2800_drv_write_firmware(rt2x00dev, data, len);
672
673 /*
674 * Wait for device to stabilize.
675 */
676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
679 break;
680 msleep(1);
681 }
682
683 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 684 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 685 return -EBUSY;
686 }
687
4ed1dd2a
SG		 688 /*
689 * Disable DMA, will be reenabled later when enabling
690 * the radio.
691 */
f7b395e9 692 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 693
f31c9a8c
ID		 694 /*
695 * Initialize firmware.
696 */
697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 699 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
702 }
f31c9a8c
ID		 703 msleep(1);
704
705 return 0;
706}
707EXPORT_SYMBOL_GPL(rt2800_load_firmware);
708
0c5879bc
ID		 709void rt2800_write_tx_data(struct queue_entry *entry,
710 struct txentry_desc *txdesc)
59679b91 711{
0c5879bc 712 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 713 u32 word;
557985ae 714 int i;
59679b91
GW		 715
716 /*
717 * Initialize TX Info descriptor
718 */
719 rt2x00_desc_read(txwi, 0, &word);
720 rt2x00_set_field32(&word, TXWI_W0_FRAG,
721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
725 rt2x00_set_field32(&word, TXWI_W0_TS,
726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
730 txdesc->u.ht.mpdu_density);
731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 733 rt2x00_set_field32(&word, TXWI_W0_BW,
734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
739 rt2x00_desc_write(txwi, 0, word);
740
741 rt2x00_desc_read(txwi, 1, &word);
742 rt2x00_set_field32(&word, TXWI_W1_ACK,
743 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
744 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 749 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
751 txdesc->length);
2b23cdaa 752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 754 rt2x00_desc_write(txwi, 1, word);
755
756 /*
557985ae
SG		 757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 759 * When TXD_W3_WIV is set to 1 it will use the IV data
760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
761 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 762 *
763 * Nulify all remaining words as well, we don't know how to program them.
59679b91 764 */
557985ae
SG		 765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
766 _rt2x00_desc_write(txwi, i, 0);
59679b91 767}
0c5879bc 768EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 769
ff6133be 770static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 771{
7fc41755
LT		 772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 775 u16 eeprom;
776 u8 offset0;
777 u8 offset1;
778 u8 offset2;
779
57fbcce3 780 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
786 } else {
3e38d3da 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
792 }
793
794 /*
795 * Convert the value from the descriptor into the RSSI value
796 * If the value in the descriptor is 0, it is considered invalid
797 * and the default (extremely low) rssi value is assumed
798 */
799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
802
803 /*
804 * mac80211 only accepts a single RSSI value. Calculating the
805 * average doesn't deliver a fair answer either since -60:-60 would
806 * be considered equally good as -50:-70 while the second is the one
807 * which gives less energy...
808 */
809 rssi0 = max(rssi0, rssi1);
7fc41755 810 return (int)max(rssi0, rssi2);
74861922
ID		 811}
812
813void rt2800_process_rxwi(struct queue_entry *entry,
814 struct rxdone_entry_desc *rxdesc)
815{
816 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 817 u32 word;
818
819 rt2x00_desc_read(rxwi, 0, &word);
820
821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
823
824 rt2x00_desc_read(rxwi, 1, &word);
825
826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
827 rxdesc->flags |= RX_FLAG_SHORT_GI;
828
829 if (rt2x00_get_field32(word, RXWI_W1_BW))
830 rxdesc->flags |= RX_FLAG_40MHZ;
831
832 /*
833 * Detect RX rate, always use MCS as signal type.
834 */
835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
838
839 /*
840 * Mask of 0x8 bit to remove the short preamble flag.
841 */
842 if (rxdesc->rate_mode == RATE_MODE_CCK)
843 rxdesc->signal &= ~0x8;
844
845 rt2x00_desc_read(rxwi, 2, &word);
846
74861922
ID		 847 /*
848 * Convert descriptor AGC value to RSSI value.
849 */
850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 851 /*
852 * Remove RXWI descriptor from start of the buffer.
853 */
854 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 855}
856EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
857
31937c42 858void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 859{
860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 862 struct txdone_entry_desc txdesc;
863 u32 word;
864 u16 mcs, real_mcs;
b34793ee 865 int aggr, ampdu;
14433331
HS		 866
867 /*
868 * Obtain the status about this packet.
869 */
870 txdesc.flags = 0;
14433331 871 rt2x00_desc_read(txwi, 0, &word);
b34793ee 872
14433331 873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
875
14433331 876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
878
879 /*
880 * If a frame was meant to be sent as a single non-aggregated MPDU
881 * but ended up in an aggregate the used tx rate doesn't correlate
882 * with the one specified in the TXWI as the whole aggregate is sent
883 * with the same rate.
884 *
885 * For example: two frames are sent to rt2x00, the first one sets
886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
887 * and requests MCS15. If the hw aggregates both frames into one
888 * AMDPU the tx status for both frames will contain MCS7 although
889 * the frame was sent successfully.
890 *
891 * Hence, replace the requested rate with the real tx rate to not
892 * confuse the rate control algortihm by providing clearly wrong
893 * data.
894 */
5356d963 895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 896 skbdesc->tx_rate_idx = real_mcs;
897 mcs = real_mcs;
898 }
14433331 899
f16d2db7
HS		 900 if (aggr == 1 || ampdu == 1)
901 __set_bit(TXDONE_AMPDU, &txdesc.flags);
902
14433331
HS		 903 /*
904 * Ralink has a retry mechanism using a global fallback
905 * table. We setup this fallback table to try the immediate
906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
907 * always contains the MCS used for the last transmission, be
908 * it successful or not.
909 */
910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
911 /*
912 * Transmission succeeded. The number of retries is
913 * mcs - real_mcs
914 */
915 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
917 } else {
918 /*
919 * Transmission failed. The number of retries is
920 * always 7 in this case (for a total number of 8
921 * frames sent).
922 */
923 __set_bit(TXDONE_FAILURE, &txdesc.flags);
924 txdesc.retry = rt2x00dev->long_retry;
925 }
926
927 /*
928 * the frame was retried at least once
929 * -> hw used fallback rates
930 */
931 if (txdesc.retry)
932 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
933
934 rt2x00lib_txdone(entry, &txdesc);
935}
936EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
937
21c6af6b
GJ		 938static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
939 unsigned int index)
940{
941 return HW_BEACON_BASE(index);
942}
943
634b8059
GJ		 944static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
945 unsigned int index)
946{
947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
948}
949
ba08910e
SG		 950static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
951{
952 struct data_queue *queue = rt2x00dev->bcn;
953 struct queue_entry *entry;
954 int i, bcn_num = 0;
955 u64 off, reg = 0;
956 u32 bssid_dw1;
957
958 /*
959 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
960 */
961 for (i = 0; i < queue->limit; i++) {
962 entry = &queue->entries[i];
963 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
964 continue;
965 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
966 reg |= off << (8 * bcn_num);
967 bcn_num++;
968 }
969
970 WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing);
971
972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
974
975 /*
976 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
977 */
978 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
979 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
980 bcn_num > 0 ? bcn_num - 1 : 0);
981 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
982}
983
f0194b2d
GW		 984void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
985{
986 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
987 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
988 unsigned int beacon_base;
739fd940 989 unsigned int padding_len;
d76dfc61 990 u32 orig_reg, reg;
f0bda571 991 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 992
993 /*
994 * Disable beaconing while we are reloading the beacon data,
995 * otherwise we might be sending out invalid data.
996 */
997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 998 orig_reg = reg;
f0194b2d
GW		 999 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1001
1002 /*
1003 * Add space for the TXWI in front of the skb.
1004 */
f0bda571 1005 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 1006
1007 /*
1008 * Register descriptor details in skb frame descriptor.
1009 */
1010 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1011 skbdesc->desc = entry->skb->data;
f0bda571 1012 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 1013
1014 /*
1015 * Add the TXWI for the beacon to the skb.
1016 */
0c5879bc 1017 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 1018
1019 /*
1020 * Dump beacon to userspace through debugfs.
1021 */
1022 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1023
1024 /*
739fd940 1025 * Write entire beacon with TXWI and padding to register.
f0194b2d 1026 */
739fd940 1027 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 1028 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1029 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1030 /* skb freed by skb_pad() on failure */
1031 entry->skb = NULL;
1032 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1033 return;
1034 }
1035
21c6af6b
GJ		 1036 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1037
739fd940
WK		 1038 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1039 entry->skb->len + padding_len);
ba08910e
SG		 1040 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1041
1042 /*
1043 * Change global beacons settings.
1044 */
1045 rt2800_update_beacons_setup(rt2x00dev);
f0194b2d
GW		 1046
1047 /*
bc0df75a 1048 * Restore beaconing state.
f0194b2d 1049 */
bc0df75a 1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
f0194b2d
GW		 1051
1052 /*
1053 * Clean up beacon skb.
1054 */
1055 dev_kfree_skb_any(entry->skb);
1056 entry->skb = NULL;
1057}
50e888ea 1058EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1059
69cf36a4 1060static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1061 unsigned int index)
fdb87251
HS		 1062{
1063 int i;
0879f875 1064 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1065 unsigned int beacon_base;
1066
21c6af6b 1067 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1068
1069 /*
1070 * For the Beacon base registers we only need to clear
1071 * the whole TXWI which (when set to 0) will invalidate
1072 * the entire beacon.
1073 */
f0bda571 1074 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1075 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1076}
1077
69cf36a4
HS		 1078void rt2800_clear_beacon(struct queue_entry *entry)
1079{
1080 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bc0df75a 1081 u32 orig_reg, reg;
69cf36a4
HS		 1082
1083 /*
1084 * Disable beaconing while we are reloading the beacon data,
1085 * otherwise we might be sending out invalid data.
1086 */
bc0df75a
SG		 1087 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1088 reg = orig_reg;
69cf36a4
HS		 1089 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1091
1092 /*
1093 * Clear beacon.
1094 */
77f7c0f3 1095 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
ba08910e 1096 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
69cf36a4 1097
ba08910e
SG		 1098 /*
1099 * Change global beacons settings.
1100 */
1101 rt2800_update_beacons_setup(rt2x00dev);
69cf36a4 1102 /*
bc0df75a 1103 * Restore beaconing state.
69cf36a4 1104 */
bc0df75a 1105 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
69cf36a4
HS		 1106}
1107EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1108
f4450616
BZ		 1109#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1110const struct rt2x00debug rt2800_rt2x00debug = {
1111 .owner = THIS_MODULE,
1112 .csr = {
1113 .read = rt2800_register_read,
1114 .write = rt2800_register_write,
1115 .flags = RT2X00DEBUGFS_OFFSET,
1116 .word_base = CSR_REG_BASE,
1117 .word_size = sizeof(u32),
1118 .word_count = CSR_REG_SIZE / sizeof(u32),
1119 },
1120 .eeprom = {
3e38d3da
GJ		 1121 /* NOTE: The local EEPROM access functions can't
1122 * be used here, use the generic versions instead.
1123 */
f4450616
BZ		 1124 .read = rt2x00_eeprom_read,
1125 .write = rt2x00_eeprom_write,
1126 .word_base = EEPROM_BASE,
1127 .word_size = sizeof(u16),
1128 .word_count = EEPROM_SIZE / sizeof(u16),
1129 },
1130 .bbp = {
1131 .read = rt2800_bbp_read,
1132 .write = rt2800_bbp_write,
1133 .word_base = BBP_BASE,
1134 .word_size = sizeof(u8),
1135 .word_count = BBP_SIZE / sizeof(u8),
1136 },
1137 .rf = {
1138 .read = rt2x00_rf_read,
1139 .write = rt2800_rf_write,
1140 .word_base = RF_BASE,
1141 .word_size = sizeof(u32),
1142 .word_count = RF_SIZE / sizeof(u32),
1143 },
f2bd7f16
AA		 1144 .rfcsr = {
1145 .read = rt2800_rfcsr_read,
1146 .write = rt2800_rfcsr_write,
1147 .word_base = RFCSR_BASE,
1148 .word_size = sizeof(u8),
1149 .word_count = RFCSR_SIZE / sizeof(u8),
1150 },
f4450616
BZ		 1151};
1152EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1153#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1154
1155int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1156{
1157 u32 reg;
1158
a89534ed
WH		 1159 if (rt2x00_rt(rt2x00dev, RT3290)) {
1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1162 } else {
99bdf51a
GW		 1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1165 }
f4450616
BZ		 1166}
1167EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1168
1169#ifdef CONFIG_RT2X00_LIB_LEDS
1170static void rt2800_brightness_set(struct led_classdev *led_cdev,
1171 enum led_brightness brightness)
1172{
1173 struct rt2x00_led *led =
1174 container_of(led_cdev, struct rt2x00_led, led_dev);
1175 unsigned int enabled = brightness != LED_OFF;
1176 unsigned int bg_mode =
57fbcce3 1177 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
f4450616
BZ		 1178 unsigned int polarity =
1179 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1180 EEPROM_FREQ_LED_POLARITY);
1181 unsigned int ledmode =
1182 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1183 EEPROM_FREQ_LED_MODE);
44704e5d 1184 u32 reg;
f4450616 1185
44704e5d
LE		 1186 /* Check for SoC (SOC devices don't support MCU requests) */
1187 if (rt2x00_is_soc(led->rt2x00dev)) {
1188 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1189
1190 /* Set LED Polarity */
1191 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1192
1193 /* Set LED Mode */
1194 if (led->type == LED_TYPE_RADIO) {
1195 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1196 enabled ? 3 : 0);
1197 } else if (led->type == LED_TYPE_ASSOC) {
1198 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1199 enabled ? 3 : 0);
1200 } else if (led->type == LED_TYPE_QUALITY) {
1201 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1202 enabled ? 3 : 0);
1203 }
1204
1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1206
1207 } else {
1208 if (led->type == LED_TYPE_RADIO) {
1209 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1210 enabled ? 0x20 : 0);
1211 } else if (led->type == LED_TYPE_ASSOC) {
1212 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1213 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1214 } else if (led->type == LED_TYPE_QUALITY) {
1215 /*
1216 * The brightness is divided into 6 levels (0 - 5),
1217 * The specs tell us the following levels:
1218 * 0, 1 ,3, 7, 15, 31
1219 * to determine the level in a simple way we can simply
1220 * work with bitshifting:
1221 * (1 << level) - 1
1222 */
1223 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1224 (1 << brightness / (LED_FULL / 6)) - 1,
1225 polarity);
1226 }
f4450616
BZ		 1227 }
1228}
1229
b3579d6a 1230static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1231 struct rt2x00_led *led, enum led_type type)
1232{
1233 led->rt2x00dev = rt2x00dev;
1234 led->type = type;
1235 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1236 led->flags = LED_INITIALIZED;
1237}
f4450616
BZ		 1238#endif /* CONFIG_RT2X00_LIB_LEDS */
1239
1240/*
1241 * Configuration handlers.
1242 */
a2b1328a
HS		 1243static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1244 const u8 *address,
1245 int wcid)
f4450616
BZ		 1246{
1247 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1248 u32 offset;
1249
1250 offset = MAC_WCID_ENTRY(wcid);
1251
1252 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1253 if (address)
1254 memcpy(wcid_entry.mac, address, ETH_ALEN);
1255
1256 rt2800_register_multiwrite(rt2x00dev, offset,
1257 &wcid_entry, sizeof(wcid_entry));
1258}
1259
1260static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1261{
1262 u32 offset;
1263 offset = MAC_WCID_ATTR_ENTRY(wcid);
1264 rt2800_register_write(rt2x00dev, offset, 0);
1265}
1266
1267static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1268 int wcid, u32 bssidx)
1269{
1270 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1271 u32 reg;
1272
1273 /*
1274 * The BSS Idx numbers is split in a main value of 3 bits,
1275 * and a extended field for adding one additional bit to the value.
1276 */
1277 rt2800_register_read(rt2x00dev, offset, &reg);
1278 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1279 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1280 (bssidx & 0x8) >> 3);
1281 rt2800_register_write(rt2x00dev, offset, reg);
1282}
1283
1284static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1285 struct rt2x00lib_crypto *crypto,
1286 struct ieee80211_key_conf *key)
1287{
f4450616
BZ		 1288 struct mac_iveiv_entry iveiv_entry;
1289 u32 offset;
1290 u32 reg;
1291
1292 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1293
e4a0ab34
ID		 1294 if (crypto->cmd == SET_KEY) {
1295 rt2800_register_read(rt2x00dev, offset, &reg);
1296 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1297 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1298 /*
1299 * Both the cipher as the BSS Idx numbers are split in a main
1300 * value of 3 bits, and a extended field for adding one additional
1301 * bit to the value.
1302 */
1303 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1304 (crypto->cipher & 0x7));
1305 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1306 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1307 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1308 rt2800_register_write(rt2x00dev, offset, reg);
1309 } else {
a2b1328a
HS		 1310 /* Delete the cipher without touching the bssidx */
1311 rt2800_register_read(rt2x00dev, offset, &reg);
1312 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1313 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1314 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1315 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1316 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1317 }
f4450616
BZ		 1318
1319 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1320
1321 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1322 if ((crypto->cipher == CIPHER_TKIP) ||
1323 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1324 (crypto->cipher == CIPHER_AES))
1325 iveiv_entry.iv[3] |= 0x20;
1326 iveiv_entry.iv[3] |= key->keyidx << 6;
1327 rt2800_register_multiwrite(rt2x00dev, offset,
1328 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1329}
1330
1331int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1332 struct rt2x00lib_crypto *crypto,
1333 struct ieee80211_key_conf *key)
1334{
1335 struct hw_key_entry key_entry;
1336 struct rt2x00_field32 field;
1337 u32 offset;
1338 u32 reg;
1339
1340 if (crypto->cmd == SET_KEY) {
1341 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1342
1343 memcpy(key_entry.key, crypto->key,
1344 sizeof(key_entry.key));
1345 memcpy(key_entry.tx_mic, crypto->tx_mic,
1346 sizeof(key_entry.tx_mic));
1347 memcpy(key_entry.rx_mic, crypto->rx_mic,
1348 sizeof(key_entry.rx_mic));
1349
1350 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1351 rt2800_register_multiwrite(rt2x00dev, offset,
1352 &key_entry, sizeof(key_entry));
1353 }
1354
1355 /*
1356 * The cipher types are stored over multiple registers
1357 * starting with SHARED_KEY_MODE_BASE each word will have
1358 * 32 bits and contains the cipher types for 2 bssidx each.
1359 * Using the correct defines correctly will cause overhead,
1360 * so just calculate the correct offset.
1361 */
1362 field.bit_offset = 4 * (key->hw_key_idx % 8);
1363 field.bit_mask = 0x7 << field.bit_offset;
1364
1365 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1366
1367 rt2800_register_read(rt2x00dev, offset, &reg);
1368 rt2x00_set_field32(&reg, field,
1369 (crypto->cmd == SET_KEY) * crypto->cipher);
1370 rt2800_register_write(rt2x00dev, offset, reg);
1371
1372 /*
1373 * Update WCID information
1374 */
a2b1328a
HS		 1375 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1376 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1377 crypto->bssidx);
1378 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1379
1380 return 0;
1381}
1382EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1383
1384int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1385 struct rt2x00lib_crypto *crypto,
1386 struct ieee80211_key_conf *key)
1387{
1388 struct hw_key_entry key_entry;
1389 u32 offset;
1390
1391 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1392 /*
1393 * Allow key configuration only for STAs that are
1394 * known by the hw.
1395 */
ed8e0ed5 1396 if (crypto->wcid > WCID_END)
f4450616 1397 return -ENOSPC;
a2b1328a 1398 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1399
1400 memcpy(key_entry.key, crypto->key,
1401 sizeof(key_entry.key));
1402 memcpy(key_entry.tx_mic, crypto->tx_mic,
1403 sizeof(key_entry.tx_mic));
1404 memcpy(key_entry.rx_mic, crypto->rx_mic,
1405 sizeof(key_entry.rx_mic));
1406
1407 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1408 rt2800_register_multiwrite(rt2x00dev, offset,
1409 &key_entry, sizeof(key_entry));
1410 }
1411
1412 /*
1413 * Update WCID information
1414 */
a2b1328a 1415 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1416
1417 return 0;
1418}
1419EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1420
a2b1328a
HS		 1421int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1422 struct ieee80211_sta *sta)
1423{
1424 int wcid;
1425 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
ed8e0ed5 1426 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
a2b1328a
HS		 1427
1428 /*
ed8e0ed5
SG		 1429 * Search for the first free WCID entry and return the corresponding
1430 * index.
a2b1328a 1431 */
ed8e0ed5 1432 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
a2b1328a
HS		 1433
1434 /*
1435 * Store selected wcid even if it is invalid so that we can
1436 * later decide if the STA is uploaded into the hw.
1437 */
1438 sta_priv->wcid = wcid;
1439
1440 /*
1441 * No space left in the device, however, we can still communicate
1442 * with the STA -> No error.
1443 */
ed8e0ed5 1444 if (wcid > WCID_END)
a2b1328a
HS		 1445 return 0;
1446
ed8e0ed5
SG		 1447 __set_bit(wcid - WCID_START, drv_data->sta_ids);
1448
a2b1328a
HS		 1449 /*
1450 * Clean up WCID attributes and write STA address to the device.
1451 */
1452 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1453 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1454 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1455 rt2x00lib_get_bssidx(rt2x00dev, vif));
1456 return 0;
1457}
1458EXPORT_SYMBOL_GPL(rt2800_sta_add);
1459
1460int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1461{
ed8e0ed5
SG		 1462 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1463
1464 if (wcid > WCID_END)
1465 return 0;
a2b1328a
HS		 1466 /*
1467 * Remove WCID entry, no need to clean the attributes as they will
1468 * get renewed when the WCID is reused.
1469 */
1470 rt2800_config_wcid(rt2x00dev, NULL, wcid);
ed8e0ed5 1471 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
a2b1328a
HS		 1472
1473 return 0;
1474}
1475EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1476
f4450616
BZ		 1477void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1478 const unsigned int filter_flags)
1479{
1480 u32 reg;
1481
1482 /*
1483 * Start configuration steps.
1484 * Note that the version error will always be dropped
1485 * and broadcast frames will always be accepted since
1486 * there is no filter for it at this time.
1487 */
1488 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1489 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1490 !(filter_flags & FIF_FCSFAIL));
1491 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1492 !(filter_flags & FIF_PLCPFAIL));
262c741e
EC		 1493 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1494 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
f4450616
BZ		 1495 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1496 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1497 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1498 !(filter_flags & FIF_ALLMULTI));
1499 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1500 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1501 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1502 !(filter_flags & FIF_CONTROL));
1503 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1504 !(filter_flags & FIF_CONTROL));
1505 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1506 !(filter_flags & FIF_CONTROL));
1507 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1508 !(filter_flags & FIF_CONTROL));
1509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1510 !(filter_flags & FIF_CONTROL));
1511 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1512 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1513 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1515 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1517 !(filter_flags & FIF_CONTROL));
1518 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1519}
1520EXPORT_SYMBOL_GPL(rt2800_config_filter);
1521
1522void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1523 struct rt2x00intf_conf *conf, const unsigned int flags)
1524{
f4450616 1525 u32 reg;
fa8b4b22 1526 bool update_bssid = false;
f4450616
BZ		 1527
1528 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1529 /*
1530 * Enable synchronisation.
1531 */
1532 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1533 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1534 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1535
1536 if (conf->sync == TSF_SYNC_AP_NONE) {
1537 /*
1538 * Tune beacon queue transmit parameters for AP mode
1539 */
1540 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1541 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1542 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1543 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1544 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1545 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1546 } else {
1547 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1548 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1549 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1550 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1551 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1552 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1553 }
f4450616
BZ		 1554 }
1555
1556 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1557 if (flags & CONFIG_UPDATE_TYPE &&
1558 conf->sync == TSF_SYNC_AP_NONE) {
1559 /*
1560 * The BSSID register has to be set to our own mac
1561 * address in AP mode.
1562 */
1563 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1564 update_bssid = true;
1565 }
1566
c600c826
ID		 1567 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1568 reg = le32_to_cpu(conf->mac[1]);
1569 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1570 conf->mac[1] = cpu_to_le32(reg);
1571 }
f4450616
BZ		 1572
1573 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1574 conf->mac, sizeof(conf->mac));
1575 }
1576
fa8b4b22 1577 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1578 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1579 reg = le32_to_cpu(conf->bssid[1]);
1580 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
88ff2f45 1581 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
c600c826
ID		 1582 conf->bssid[1] = cpu_to_le32(reg);
1583 }
f4450616
BZ		 1584
1585 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1586 conf->bssid, sizeof(conf->bssid));
1587 }
1588}
1589EXPORT_SYMBOL_GPL(rt2800_config_intf);
1590
87c1915d
HS		 1591static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1592 struct rt2x00lib_erp *erp)
1593{
1594 bool any_sta_nongf = !!(erp->ht_opmode &
1595 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1596 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1597 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1598 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1599 u32 reg;
1600
1601 /* default protection rate for HT20: OFDM 24M */
1602 mm20_rate = gf20_rate = 0x4004;
1603
1604 /* default protection rate for HT40: duplicate OFDM 24M */
1605 mm40_rate = gf40_rate = 0x4084;
1606
1607 switch (protection) {
1608 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1609 /*
1610 * All STAs in this BSS are HT20/40 but there might be
1611 * STAs not supporting greenfield mode.
1612 * => Disable protection for HT transmissions.
1613 */
1614 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1615
1616 break;
1617 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1618 /*
1619 * All STAs in this BSS are HT20 or HT20/40 but there
1620 * might be STAs not supporting greenfield mode.
1621 * => Protect all HT40 transmissions.
1622 */
1623 mm20_mode = gf20_mode = 0;
1624 mm40_mode = gf40_mode = 2;
1625
1626 break;
1627 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1628 /*
1629 * Nonmember protection:
1630 * According to 802.11n we _should_ protect all
1631 * HT transmissions (but we don't have to).
1632 *
1633 * But if cts_protection is enabled we _shall_ protect
1634 * all HT transmissions using a CCK rate.
1635 *
1636 * And if any station is non GF we _shall_ protect
1637 * GF transmissions.
1638 *
1639 * We decide to protect everything
1640 * -> fall through to mixed mode.
1641 */
1642 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1643 /*
1644 * Legacy STAs are present
1645 * => Protect all HT transmissions.
1646 */
1647 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1648
1649 /*
1650 * If erp protection is needed we have to protect HT
1651 * transmissions with CCK 11M long preamble.
1652 */
1653 if (erp->cts_protection) {
1654 /* don't duplicate RTS/CTS in CCK mode */
1655 mm20_rate = mm40_rate = 0x0003;
1656 gf20_rate = gf40_rate = 0x0003;
1657 }
1658 break;
6403eab1 1659 }
87c1915d
HS		 1660
1661 /* check for STAs not supporting greenfield mode */
1662 if (any_sta_nongf)
1663 gf20_mode = gf40_mode = 2;
1664
1665 /* Update HT protection config */
1666 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1667 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1668 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1669 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1670
1671 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1672 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1673 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1674 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1675
1676 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1677 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1678 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1679 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1680
1681 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1682 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1683 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1684 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1685}
1686
02044643
HS		 1687void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1688 u32 changed)
f4450616
BZ		 1689{
1690 u32 reg;
1691
02044643
HS		 1692 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1693 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1694 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1695 !!erp->short_preamble);
1696 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1697 !!erp->short_preamble);
1698 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1699 }
f4450616 1700
02044643
HS		 1701 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1702 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1703 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1704 erp->cts_protection ? 2 : 0);
1705 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1706 }
f4450616 1707
02044643
HS		 1708 if (changed & BSS_CHANGED_BASIC_RATES) {
1709 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1710 erp->basic_rates);
1711 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1712 }
f4450616 1713
02044643
HS		 1714 if (changed & BSS_CHANGED_ERP_SLOT) {
1715 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1716 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1717 erp->slot_time);
1718 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1719
02044643
HS		 1720 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1721 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1722 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1723 }
f4450616 1724
02044643
HS		 1725 if (changed & BSS_CHANGED_BEACON_INT) {
1726 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1727 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1728 erp->beacon_int * 16);
1729 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1730 }
87c1915d
HS		 1731
1732 if (changed & BSS_CHANGED_HT)
1733 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1734}
1735EXPORT_SYMBOL_GPL(rt2800_config_erp);
1736
872834df
GW		 1737static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1738{
1739 u32 reg;
1740 u16 eeprom;
1741 u8 led_ctrl, led_g_mode, led_r_mode;
1742
1743 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
57fbcce3 1744 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
872834df
GW		 1745 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1746 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1747 } else {
1748 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1749 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1750 }
1751 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1752
1753 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1754 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1755 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1756 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1757 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1758 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1759 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1760 if (led_ctrl == 0 || led_ctrl > 0x40) {
1761 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1762 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1763 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1764 } else {
1765 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1766 (led_g_mode << 2) | led_r_mode, 1);
1767 }
1768 }
1769}
1770
d96aa640
RJH		 1771static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1772 enum antenna ant)
1773{
1774 u32 reg;
1775 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1776 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1777
1778 if (rt2x00_is_pci(rt2x00dev)) {
1779 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1780 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1781 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1782 } else if (rt2x00_is_usb(rt2x00dev))
1783 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1784 eesk_pin, 0);
1785
99bdf51a
GW		 1786 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1787 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1788 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1789 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1790}
1791
f4450616
BZ		 1792void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1793{
1794 u8 r1;
1795 u8 r3;
d96aa640 1796 u16 eeprom;
f4450616
BZ		 1797
1798 rt2800_bbp_read(rt2x00dev, 1, &r1);
1799 rt2800_bbp_read(rt2x00dev, 3, &r3);
1800
872834df 1801 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1802 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1803 rt2800_config_3572bt_ant(rt2x00dev);
1804
f4450616
BZ		 1805 /*
1806 * Configure the TX antenna.
1807 */
d96aa640 1808 switch (ant->tx_chain_num) {
f4450616
BZ		 1809 case 1:
1810 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1811 break;
1812 case 2:
872834df 1813 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1814 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1815 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1816 else
1817 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1818 break;
1819 case 3:
4788ac1e 1820 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1821 break;
1822 }
1823
1824 /*
1825 * Configure the RX antenna.
1826 */
d96aa640 1827 switch (ant->rx_chain_num) {
f4450616 1828 case 1:
d96aa640
RJH		 1829 if (rt2x00_rt(rt2x00dev, RT3070) ||
1830 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1831 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1832 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1833 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1834 EEPROM_NIC_CONF1, &eeprom);
1835 if (rt2x00_get_field16(eeprom,
1836 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1837 rt2800_set_ant_diversity(rt2x00dev,
1838 rt2x00dev->default_ant.rx);
1839 }
f4450616
BZ		 1840 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1841 break;
1842 case 2:
872834df 1843 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1844 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 1845 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1846 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
57fbcce3 1847 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
872834df
GW		 1848 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1849 } else {
1850 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1851 }
f4450616
BZ		 1852 break;
1853 case 3:
1854 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1855 break;
1856 }
1857
1858 rt2800_bbp_write(rt2x00dev, 3, r3);
1859 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 1860
1861 if (rt2x00_rt(rt2x00dev, RT3593)) {
1862 if (ant->rx_chain_num == 1)
1863 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1864 else
1865 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1866 }
f4450616
BZ		 1867}
1868EXPORT_SYMBOL_GPL(rt2800_config_ant);
1869
1870static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1871 struct rt2x00lib_conf *libconf)
1872{
1873 u16 eeprom;
1874 short lna_gain;
1875
1876 if (libconf->rf.channel <= 14) {
3e38d3da 1877 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1878 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1879 } else if (libconf->rf.channel <= 64) {
3e38d3da 1880 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1881 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1882 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 1883 if (rt2x00_rt(rt2x00dev, RT3593)) {
1884 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1885 lna_gain = rt2x00_get_field16(eeprom,
1886 EEPROM_EXT_LNA2_A1);
1887 } else {
1888 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1889 lna_gain = rt2x00_get_field16(eeprom,
1890 EEPROM_RSSI_BG2_LNA_A1);
1891 }
f4450616 1892 } else {
f36bb0ca
GJ		 1893 if (rt2x00_rt(rt2x00dev, RT3593)) {
1894 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1895 lna_gain = rt2x00_get_field16(eeprom,
1896 EEPROM_EXT_LNA2_A2);
1897 } else {
1898 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1899 lna_gain = rt2x00_get_field16(eeprom,
1900 EEPROM_RSSI_A2_LNA_A2);
1901 }
f4450616
BZ		 1902 }
1903
1904 rt2x00dev->lna_gain = lna_gain;
1905}
1906
3f1b8739
GJ		 1907#define FREQ_OFFSET_BOUND 0x5f
1908
1909static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1910{
1911 u8 freq_offset, prev_freq_offset;
1912 u8 rfcsr, prev_rfcsr;
1913
1914 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1915 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1916
1917 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1918 prev_rfcsr = rfcsr;
1919
1920 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1921 if (rfcsr == prev_rfcsr)
1922 return;
1923
1924 if (rt2x00_is_usb(rt2x00dev)) {
1925 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1926 freq_offset, prev_rfcsr);
1927 return;
1928 }
1929
1930 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1931 while (prev_freq_offset != freq_offset) {
1932 if (prev_freq_offset < freq_offset)
1933 prev_freq_offset++;
1934 else
1935 prev_freq_offset--;
1936
1937 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1938 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1939
1940 usleep_range(1000, 1500);
1941 }
1942}
1943
06855ef4
GW		 1944static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1945 struct ieee80211_conf *conf,
1946 struct rf_channel *rf,
1947 struct channel_info *info)
f4450616
BZ		 1948{
1949 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1950
d96aa640 1951 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1952 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1953
d96aa640 1954 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1955 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1956 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1957 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1958 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1959
1960 if (rf->channel > 14) {
1961 /*
1962 * When TX power is below 0, we should increase it by 7 to
25985edc 1963 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1964 * However this means that values between 0 and 7 have
1965 * double meaning, and we should set a 7DBm boost flag.
1966 */
1967 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1968 (info->default_power1 >= 0));
f4450616 1969
8d1331b3
ID		 1970 if (info->default_power1 < 0)
1971 info->default_power1 += 7;
f4450616 1972
8d1331b3 1973 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1974
1975 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1976 (info->default_power2 >= 0));
f4450616 1977
8d1331b3
ID		 1978 if (info->default_power2 < 0)
1979 info->default_power2 += 7;
f4450616 1980
8d1331b3 1981 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1982 } else {
8d1331b3
ID		 1983 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1984 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1985 }
1986
1987 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1988
1989 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1990 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1991 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1992 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1993
1994 udelay(200);
1995
1996 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1997 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1998 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1999 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2000
2001 udelay(200);
2002
2003 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2004 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2005 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2006 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2007}
2008
06855ef4
GW		 2009static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2010 struct ieee80211_conf *conf,
2011 struct rf_channel *rf,
2012 struct channel_info *info)
f4450616 2013{
3a1c0128 2014 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 2015 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 2016
2017 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 2018
2019 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2020 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2021 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 2022
2023 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 2024 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2025 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2026
2027 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 2028 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2029 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2030
5a673964 2031 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 2032 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2033 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 2034
2035 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2036 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2037 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2038 rt2x00dev->default_ant.rx_chain_num <= 1);
2039 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2040 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2041 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2042 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2043 rt2x00dev->default_ant.tx_chain_num <= 1);
2044 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2045 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2046 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2047
f4450616
BZ		 2048 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2049 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2050 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2051
f1f12f98
SG		 2052 if (rt2x00_rt(rt2x00dev, RT3390)) {
2053 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2054 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2055 } else {
3a1c0128
GW		 2056 if (conf_is_ht40(conf)) {
2057 calib_tx = drv_data->calibration_bw40;
2058 calib_rx = drv_data->calibration_bw40;
2059 } else {
2060 calib_tx = drv_data->calibration_bw20;
2061 calib_rx = drv_data->calibration_bw20;
2062 }
f1f12f98
SG		 2063 }
2064
2065 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2066 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2067 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2068
2069 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2070 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2071 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2072
71976907 2073 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 2074 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2075 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 2076
2077 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2078 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2079 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2080 msleep(1);
2081 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2082 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2083}
2084
872834df
GW		 2085static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2086 struct ieee80211_conf *conf,
2087 struct rf_channel *rf,
2088 struct channel_info *info)
2089{
3a1c0128 2090 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2091 u8 rfcsr;
2092 u32 reg;
2093
2094 if (rf->channel <= 14) {
5d137dff
GW		 2095 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2096 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2097 } else {
2098 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2099 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2100 }
2101
2102 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2103 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2104
2105 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2106 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2107 if (rf->channel <= 14)
2108 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2109 else
2110 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2111 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2112
2113 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2114 if (rf->channel <= 14)
2115 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2116 else
2117 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2118 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2119
2120 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2121 if (rf->channel <= 14) {
2122 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2123 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2124 info->default_power1);
872834df
GW		 2125 } else {
2126 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2127 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2128 (info->default_power1 & 0x3) |
2129 ((info->default_power1 & 0xC) << 1));
2130 }
2131 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2132
2133 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2134 if (rf->channel <= 14) {
2135 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2136 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2137 info->default_power2);
872834df
GW		 2138 } else {
2139 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2140 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2141 (info->default_power2 & 0x3) |
2142 ((info->default_power2 & 0xC) << 1));
2143 }
2144 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2145
2146 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2147 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2148 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2149 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2150 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2151 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2152 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
c429dfef 2153 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2154 if (rf->channel <= 14) {
2155 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2156 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2157 }
2158 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2159 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2160 } else {
2161 switch (rt2x00dev->default_ant.tx_chain_num) {
2162 case 1:
2163 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2164 case 2:
2165 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2166 break;
2167 }
2168
2169 switch (rt2x00dev->default_ant.rx_chain_num) {
2170 case 1:
2171 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2172 case 2:
2173 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2174 break;
2175 }
2176 }
2177 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2178
2179 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2180 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2181 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2182
3a1c0128
GW		 2183 if (conf_is_ht40(conf)) {
2184 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2185 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2186 } else {
2187 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2188 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2189 }
872834df
GW		 2190
2191 if (rf->channel <= 14) {
2192 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2193 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2194 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2195 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2196 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2197 rfcsr = 0x4c;
2198 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2199 drv_data->txmixer_gain_24g);
2200 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2201 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2202 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2203 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2204 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2205 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2206 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2207 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2208 } else {
58b8ae14
GW		 2209 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2210 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2211 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2212 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2213 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2214 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2215 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2216 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2217 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2218 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2219 rfcsr = 0x7a;
2220 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2221 drv_data->txmixer_gain_5g);
2222 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2223 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2224 if (rf->channel <= 64) {
2225 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2226 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2227 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2228 } else if (rf->channel <= 128) {
2229 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2230 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2231 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2232 } else {
2233 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2234 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2235 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2236 }
2237 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2238 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2239 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2240 }
2241
99bdf51a
GW		 2242 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2243 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2244 if (rf->channel <= 14)
99bdf51a 2245 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2246 else
99bdf51a
GW		 2247 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2248 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2249
2250 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2251 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2252 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2253}
60687ba7 2254
f42b0465
GJ		 2255static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2256 struct ieee80211_conf *conf,
2257 struct rf_channel *rf,
2258 struct channel_info *info)
2259{
2260 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2261 u8 txrx_agc_fc;
2262 u8 txrx_h20m;
2263 u8 rfcsr;
2264 u8 bbp;
2265 const bool txbf_enabled = false; /* TODO */
2266
2267 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2268 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2269 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2270 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2271 rt2800_bbp_write(rt2x00dev, 109, bbp);
2272
2273 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2274 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2275 rt2800_bbp_write(rt2x00dev, 110, bbp);
2276
2277 if (rf->channel <= 14) {
2278 /* Restore BBP 25 & 26 for 2.4 GHz */
2279 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2280 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2281 } else {
2282 /* Hard code BBP 25 & 26 for 5GHz */
2283
2284 /* Enable IQ Phase correction */
2285 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2286 /* Setup IQ Phase correction value */
2287 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2288 }
2289
2290 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2291 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2292
2293 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2294 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2295 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2296
2297 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2298 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2299 if (rf->channel <= 14)
2300 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2301 else
2302 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2303 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2304
2305 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2306 if (rf->channel <= 14) {
2307 rfcsr = 0;
2308 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2309 info->default_power1 & 0x1f);
2310 } else {
2311 if (rt2x00_is_usb(rt2x00dev))
2312 rfcsr = 0x40;
2313
2314 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2315 ((info->default_power1 & 0x18) << 1) |
2316 (info->default_power1 & 7));
2317 }
2318 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2319
2320 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2321 if (rf->channel <= 14) {
2322 rfcsr = 0;
2323 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2324 info->default_power2 & 0x1f);
2325 } else {
2326 if (rt2x00_is_usb(rt2x00dev))
2327 rfcsr = 0x40;
2328
2329 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2330 ((info->default_power2 & 0x18) << 1) |
2331 (info->default_power2 & 7));
2332 }
2333 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2334
2335 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2336 if (rf->channel <= 14) {
2337 rfcsr = 0;
2338 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2339 info->default_power3 & 0x1f);
2340 } else {
2341 if (rt2x00_is_usb(rt2x00dev))
2342 rfcsr = 0x40;
2343
2344 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2345 ((info->default_power3 & 0x18) << 1) |
2346 (info->default_power3 & 7));
2347 }
2348 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2349
2350 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2351 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2352 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2353 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2354 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2355 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2356 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2357 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2358 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2359
2360 switch (rt2x00dev->default_ant.tx_chain_num) {
2361 case 3:
2362 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2363 /* fallthrough */
2364 case 2:
2365 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2366 /* fallthrough */
2367 case 1:
2368 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2369 break;
2370 }
2371
2372 switch (rt2x00dev->default_ant.rx_chain_num) {
2373 case 3:
2374 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2375 /* fallthrough */
2376 case 2:
2377 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2378 /* fallthrough */
2379 case 1:
2380 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2381 break;
2382 }
2383 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2384
e979a8ab 2385 rt2800_adjust_freq_offset(rt2x00dev);
f42b0465
GJ		 2386
2387 if (conf_is_ht40(conf)) {
2388 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2389 RFCSR24_TX_AGC_FC);
2390 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2391 RFCSR24_TX_H20M);
2392 } else {
2393 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2394 RFCSR24_TX_AGC_FC);
2395 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2396 RFCSR24_TX_H20M);
2397 }
2398
2399 /* NOTE: the reference driver does not writes the new value
2400 * back to RFCSR 32
2401 */
2402 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2403 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2404
2405 if (rf->channel <= 14)
2406 rfcsr = 0xa0;
2407 else
2408 rfcsr = 0x80;
2409 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2410
2411 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2412 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2413 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2414 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2415
2416 /* Band selection */
2417 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2418 if (rf->channel <= 14)
2419 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2420 else
2421 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2422 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2423
2424 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2425 if (rf->channel <= 14)
2426 rfcsr = 0x3c;
2427 else
2428 rfcsr = 0x20;
2429 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2430
2431 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2432 if (rf->channel <= 14)
2433 rfcsr = 0x1a;
2434 else
2435 rfcsr = 0x12;
2436 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2437
2438 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2439 if (rf->channel >= 1 && rf->channel <= 14)
2440 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2441 else if (rf->channel >= 36 && rf->channel <= 64)
2442 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2443 else if (rf->channel >= 100 && rf->channel <= 128)
2444 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2445 else
2446 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2447 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2448
2449 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2450 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2451 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2452
2453 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2454
2455 if (rf->channel <= 14) {
2456 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2457 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2458 } else {
2459 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2460 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2461 }
2462
2463 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2464 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2465 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2466
2467 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2468 if (rf->channel <= 14) {
2469 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2470 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2471 } else {
2472 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2473 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2474 }
2475 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2476
2477 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2478 if (rf->channel <= 14)
2479 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2480 else
2481 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2482
2483 if (txbf_enabled)
2484 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2485
2486 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2487
2488 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2489 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2490 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2491
2492 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2493 if (rf->channel <= 14)
2494 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2495 else
2496 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2497 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2498
2499 if (rf->channel <= 14) {
2500 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2501 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2502 } else {
2503 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2504 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2505 }
2506
2507 /* Initiate VCO calibration */
2508 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2509 if (rf->channel <= 14) {
2510 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2511 } else {
2512 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2513 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2514 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2515 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2516 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2517 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2518 }
2519 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2520
2521 if (rf->channel >= 1 && rf->channel <= 14) {
2522 rfcsr = 0x23;
2523 if (txbf_enabled)
2524 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2525 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2526
2527 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2528 } else if (rf->channel >= 36 && rf->channel <= 64) {
2529 rfcsr = 0x36;
2530 if (txbf_enabled)
2531 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2532 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2533
2534 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2535 } else if (rf->channel >= 100 && rf->channel <= 128) {
2536 rfcsr = 0x32;
2537 if (txbf_enabled)
2538 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2539 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2540
2541 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2542 } else {
2543 rfcsr = 0x30;
2544 if (txbf_enabled)
2545 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2546 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2547
2548 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2549 }
2550}
2551
7573cb5b 2552#define POWER_BOUND 0x27
8f821098 2553#define POWER_BOUND_5G 0x2b
0c9e5fb9 2554
a89534ed
WH		 2555static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2556 struct ieee80211_conf *conf,
2557 struct rf_channel *rf,
2558 struct channel_info *info)
2559{
2560 u8 rfcsr;
2561
2562 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2563 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2564 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2565 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2566 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2567
2568 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2569 if (info->default_power1 > POWER_BOUND)
2570 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2571 else
2572 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2573 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2574
0c9e5fb9 2575 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2576
2577 if (rf->channel <= 14) {
2578 if (rf->channel == 6)
2579 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2580 else
2581 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2582
2583 if (rf->channel >= 1 && rf->channel <= 6)
2584 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2585 else if (rf->channel >= 7 && rf->channel <= 11)
2586 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2587 else if (rf->channel >= 12 && rf->channel <= 14)
2588 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2589 }
2590}
2591
03839951
DG		 2592static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2593 struct ieee80211_conf *conf,
2594 struct rf_channel *rf,
2595 struct channel_info *info)
2596{
2597 u8 rfcsr;
2598
2599 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2600 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2601
2602 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2603 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2604 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2605
2606 if (info->default_power1 > POWER_BOUND)
2607 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2608 else
2609 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2610
2611 if (info->default_power2 > POWER_BOUND)
2612 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2613 else
2614 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2615
0c9e5fb9 2616 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2617
2618 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2619 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2620 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2621
2622 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2623 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2624 else
2625 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2626
2627 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2628 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2629 else
2630 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2631
2632 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2633 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2634
2635 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2636
2637 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2638}
2639
60687ba7 2640static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2641 struct ieee80211_conf *conf,
2642 struct rf_channel *rf,
2643 struct channel_info *info)
2644{
2645 u8 rfcsr;
adde5882
GJ		 2646
2647 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2648 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2649 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2650 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2651 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2652
2653 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2654 if (info->default_power1 > POWER_BOUND)
2655 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2656 else
2657 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2658 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2659
cff3d1f0
ZL		 2660 if (rt2x00_rt(rt2x00dev, RT5392)) {
2661 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
6264995f 2662 if (info->default_power2 > POWER_BOUND)
7573cb5b 2663 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2664 else
2665 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2666 info->default_power2);
2667 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2668 }
2669
adde5882 2670 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2671 if (rt2x00_rt(rt2x00dev, RT5392)) {
2672 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2673 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2674 }
adde5882
GJ		 2675 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2676 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2677 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2678 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2679 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2680
0c9e5fb9 2681 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2682
adde5882
GJ		 2683 if (rf->channel <= 14) {
2684 int idx = rf->channel-1;
2685
c429dfef 2686 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
adde5882
GJ		 2687 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2688 /* r55/r59 value array of channel 1~14 */
2689 static const char r55_bt_rev[] = {0x83, 0x83,
2690 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2691 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2692 static const char r59_bt_rev[] = {0x0e, 0x0e,
2693 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2694 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2695
2696 rt2800_rfcsr_write(rt2x00dev, 55,
2697 r55_bt_rev[idx]);
2698 rt2800_rfcsr_write(rt2x00dev, 59,
2699 r59_bt_rev[idx]);
2700 } else {
2701 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2702 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2703 0x88, 0x88, 0x86, 0x85, 0x84};
2704
2705 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2706 }
2707 } else {
2708 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2709 static const char r55_nonbt_rev[] = {0x23, 0x23,
2710 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2711 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2712 static const char r59_nonbt_rev[] = {0x07, 0x07,
2713 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2714 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2715
2716 rt2800_rfcsr_write(rt2x00dev, 55,
2717 r55_nonbt_rev[idx]);
2718 rt2800_rfcsr_write(rt2x00dev, 59,
2719 r59_nonbt_rev[idx]);
2ed71884 2720 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2721 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2722 static const char r59_non_bt[] = {0x8f, 0x8f,
2723 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2724 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2725
2726 rt2800_rfcsr_write(rt2x00dev, 59,
2727 r59_non_bt[idx]);
2728 }
2729 }
2730 }
60687ba7
RST		 2731}
2732
8f821098
SG		 2733static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2734 struct ieee80211_conf *conf,
2735 struct rf_channel *rf,
2736 struct channel_info *info)
2737{
2738 u8 rfcsr, ep_reg;
d5ae7a6b 2739 u32 reg;
8f821098
SG		 2740 int power_bound;
2741
2742 /* TODO */
2743 const bool is_11b = false;
2744 const bool is_type_ep = false;
2745
d5ae7a6b
SG		 2746 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2747 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2748 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2749 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2750
2751 /* Order of values on rf_channel entry: N, K, mod, R */
2752 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2753
2754 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2755 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2756 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2757 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2758 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2759
2760 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2761 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2762 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2763 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2764
2765 if (rf->channel <= 14) {
2766 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2767 /* FIXME: RF11 owerwrite ? */
2768 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2769 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2770 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2771 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2772 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2773 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2774 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2775 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2776 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2777 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2778 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2779 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2780 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2781 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2782 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2783 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2784 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2785 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2786 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2787 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2788 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2789 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2790 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2791 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2792 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2793 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2794 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2795 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2796
2797 /* TODO RF27 <- tssi */
2798
2799 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2800 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2801 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2802
2803 if (is_11b) {
2804 /* CCK */
2805 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2806 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2807 if (is_type_ep)
2808 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2809 else
2810 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2811 } else {
2812 /* OFDM */
2813 if (is_type_ep)
2814 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2815 else
2816 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2817 }
2818
2819 power_bound = POWER_BOUND;
2820 ep_reg = 0x2;
2821 } else {
2822 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2823 /* FIMXE: RF11 overwrite */
2824 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2825 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2826 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2827 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2828 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2829 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2830 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2831 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2832 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2833 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2834 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2835 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2836 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2837 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2838
2839 /* TODO RF27 <- tssi */
2840
2841 if (rf->channel >= 36 && rf->channel <= 64) {
2842
2843 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2844 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2845 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2846 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2847 if (rf->channel <= 50)
2848 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2849 else if (rf->channel >= 52)
2850 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2851 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2852 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2853 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2854 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2855 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2856 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2857 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2858 if (rf->channel <= 50) {
2859 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2860 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2861 } else if (rf->channel >= 52) {
2862 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2863 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2864 }
2865
2866 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2867 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2868 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2869
2870 } else if (rf->channel >= 100 && rf->channel <= 165) {
2871
2872 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2873 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2874 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2875 if (rf->channel <= 153) {
2876 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2877 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2878 } else if (rf->channel >= 155) {
2879 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2880 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2881 }
2882 if (rf->channel <= 138) {
2883 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2884 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2885 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2886 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2887 } else if (rf->channel >= 140) {
2888 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2889 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2890 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2891 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2892 }
2893 if (rf->channel <= 124)
2894 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2895 else if (rf->channel >= 126)
2896 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2897 if (rf->channel <= 138)
2898 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2899 else if (rf->channel >= 140)
2900 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2901 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2902 if (rf->channel <= 138)
2903 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2904 else if (rf->channel >= 140)
2905 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2906 if (rf->channel <= 128)
2907 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2908 else if (rf->channel >= 130)
2909 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2910 if (rf->channel <= 116)
2911 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2912 else if (rf->channel >= 118)
2913 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2914 if (rf->channel <= 138)
2915 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2916 else if (rf->channel >= 140)
2917 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2918 if (rf->channel <= 116)
2919 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2920 else if (rf->channel >= 118)
2921 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2922 }
2923
2924 power_bound = POWER_BOUND_5G;
2925 ep_reg = 0x3;
2926 }
2927
2928 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2929 if (info->default_power1 > power_bound)
2930 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2931 else
2932 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2933 if (is_type_ep)
2934 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2935 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2936
2937 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2938 if (info->default_power2 > power_bound)
8f821098
SG		 2939 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2940 else
2941 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2942 if (is_type_ep)
2943 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2944 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2945
2946 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2947 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2948 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2949
2950 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2951 rt2x00dev->default_ant.tx_chain_num >= 1);
2952 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2953 rt2x00dev->default_ant.tx_chain_num == 2);
2954 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2955
2956 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2957 rt2x00dev->default_ant.rx_chain_num >= 1);
2958 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2959 rt2x00dev->default_ant.rx_chain_num == 2);
2960 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2961
2962 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2963 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2964
2965 if (conf_is_ht40(conf))
2966 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2967 else
2968 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2969
2970 if (!is_11b) {
2971 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2972 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2973 }
2974
2975 /* TODO proper frequency adjustment */
0c9e5fb9 2976 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2977
2978 /* TODO merge with others */
2979 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2980 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2981 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 2982
2983 /* BBP settings */
2984 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2985 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2986 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2987
2988 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2989 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2990 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2991 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2992
2993 /* GLRT band configuration */
2994 rt2800_bbp_write(rt2x00dev, 195, 128);
2995 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2996 rt2800_bbp_write(rt2x00dev, 195, 129);
2997 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2998 rt2800_bbp_write(rt2x00dev, 195, 130);
2999 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3000 rt2800_bbp_write(rt2x00dev, 195, 131);
3001 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3002 rt2800_bbp_write(rt2x00dev, 195, 133);
3003 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3004 rt2800_bbp_write(rt2x00dev, 195, 124);
3005 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 3006}
3007
5bc2dd06
SG		 3008static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3009 const unsigned int word,
3010 const u8 value)
3011{
3012 u8 chain, reg;
3013
3014 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3015 rt2800_bbp_read(rt2x00dev, 27, &reg);
3016 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3017 rt2800_bbp_write(rt2x00dev, 27, reg);
3018
3019 rt2800_bbp_write(rt2x00dev, word, value);
3020 }
3021}
3022
8756130b
SG		 3023static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3024{
3025 u8 cal;
3026
415e3f2f 3027 /* TX0 IQ Gain */
8756130b 3028 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3029 if (channel <= 14)
3030 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3031 else if (channel >= 36 && channel <= 64)
3032 cal = rt2x00_eeprom_byte(rt2x00dev,
3033 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3034 else if (channel >= 100 && channel <= 138)
3035 cal = rt2x00_eeprom_byte(rt2x00dev,
3036 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3037 else if (channel >= 140 && channel <= 165)
3038 cal = rt2x00_eeprom_byte(rt2x00dev,
3039 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3040 else
3041 cal = 0;
8756130b
SG		 3042 rt2800_bbp_write(rt2x00dev, 159, cal);
3043
415e3f2f 3044 /* TX0 IQ Phase */
8756130b 3045 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3046 if (channel <= 14)
3047 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3048 else if (channel >= 36 && channel <= 64)
3049 cal = rt2x00_eeprom_byte(rt2x00dev,
3050 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3051 else if (channel >= 100 && channel <= 138)
3052 cal = rt2x00_eeprom_byte(rt2x00dev,
3053 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3054 else if (channel >= 140 && channel <= 165)
3055 cal = rt2x00_eeprom_byte(rt2x00dev,
3056 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3057 else
3058 cal = 0;
8756130b
SG		 3059 rt2800_bbp_write(rt2x00dev, 159, cal);
3060
415e3f2f 3061 /* TX1 IQ Gain */
8756130b 3062 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3063 if (channel <= 14)
3064 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3065 else if (channel >= 36 && channel <= 64)
3066 cal = rt2x00_eeprom_byte(rt2x00dev,
3067 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3068 else if (channel >= 100 && channel <= 138)
3069 cal = rt2x00_eeprom_byte(rt2x00dev,
3070 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3071 else if (channel >= 140 && channel <= 165)
3072 cal = rt2x00_eeprom_byte(rt2x00dev,
3073 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3074 else
3075 cal = 0;
8756130b
SG		 3076 rt2800_bbp_write(rt2x00dev, 159, cal);
3077
415e3f2f 3078 /* TX1 IQ Phase */
8756130b 3079 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3080 if (channel <= 14)
3081 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3082 else if (channel >= 36 && channel <= 64)
3083 cal = rt2x00_eeprom_byte(rt2x00dev,
3084 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3085 else if (channel >= 100 && channel <= 138)
3086 cal = rt2x00_eeprom_byte(rt2x00dev,
3087 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3088 else if (channel >= 140 && channel <= 165)
3089 cal = rt2x00_eeprom_byte(rt2x00dev,
3090 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3091 else
3092 cal = 0;
8756130b
SG		 3093 rt2800_bbp_write(rt2x00dev, 159, cal);
3094
415e3f2f
SG		 3095 /* FIXME: possible RX0, RX1 callibration ? */
3096
8756130b
SG		 3097 /* RF IQ compensation control */
3098 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3099 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3100 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3101
3102 /* RF IQ imbalance compensation control */
3103 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3104 cal = rt2x00_eeprom_byte(rt2x00dev,
3105 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3106 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3107}
3108
97aa03f1
GJ		 3109static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3110 unsigned int channel,
3111 char txpower)
3112{
fc739cfe
GJ		 3113 if (rt2x00_rt(rt2x00dev, RT3593))
3114 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3115
97aa03f1
GJ		 3116 if (channel <= 14)
3117 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3118
3119 if (rt2x00_rt(rt2x00dev, RT3593))
3120 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3121 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3122 else
3123 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3124}
3125
f4450616
BZ		 3126static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3127 struct ieee80211_conf *conf,
3128 struct rf_channel *rf,
3129 struct channel_info *info)
3130{
3131 u32 reg;
3132 unsigned int tx_pin;
a89534ed 3133 u8 bbp, rfcsr;
f4450616 3134
97aa03f1
GJ		 3135 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3136 info->default_power1);
3137 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3138 info->default_power2);
c0a14369
GJ		 3139 if (rt2x00dev->default_ant.tx_chain_num > 2)
3140 info->default_power3 =
3141 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3142 info->default_power3);
46323e11 3143
5aa57015
GW		 3144 switch (rt2x00dev->chip.rf) {
3145 case RF2020:
3146 case RF3020:
3147 case RF3021:
3148 case RF3022:
3149 case RF3320:
06855ef4 3150 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3151 break;
3152 case RF3052:
872834df 3153 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3154 break;
f42b0465
GJ		 3155 case RF3053:
3156 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3157 break;
a89534ed
WH		 3158 case RF3290:
3159 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3160 break;
03839951
DG		 3161 case RF3322:
3162 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3163 break;
3b9b74ba 3164 case RF3070:
ccf91bd6 3165 case RF5360:
ac0372ab 3166 case RF5362:
5aa57015 3167 case RF5370:
2ed71884 3168 case RF5372:
5aa57015 3169 case RF5390:
cff3d1f0 3170 case RF5392:
adde5882 3171 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3172 break;
8f821098
SG		 3173 case RF5592:
3174 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3175 break;
5aa57015 3176 default:
06855ef4 3177 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3178 }
f4450616 3179
3b9b74ba
SG		 3180 if (rt2x00_rf(rt2x00dev, RF3070) ||
3181 rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3182 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed 3183 rt2x00_rf(rt2x00dev, RF5360) ||
ac0372ab 3184 rt2x00_rf(rt2x00dev, RF5362) ||
a89534ed
WH		 3185 rt2x00_rf(rt2x00dev, RF5370) ||
3186 rt2x00_rf(rt2x00dev, RF5372) ||
3187 rt2x00_rf(rt2x00dev, RF5390) ||
3188 rt2x00_rf(rt2x00dev, RF5392)) {
3189 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3190 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3191 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3192 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3193
3194 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3195 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3196 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3197 }
3198
f4450616
BZ		 3199 /*
3200 * Change BBP settings
3201 */
03839951
DG		 3202 if (rt2x00_rt(rt2x00dev, RT3352)) {
3203 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3204 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3205 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3206 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
f42b0465
GJ		 3207 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3208 if (rf->channel > 14) {
3209 /* Disable CCK Packet detection on 5GHz */
3210 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3211 } else {
3212 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3213 }
3214
3215 if (conf_is_ht40(conf))
3216 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3217 else
3218 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3219
3220 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3221 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3222 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3223 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3224 } else {
3225 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3226 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3227 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3228 rt2800_bbp_write(rt2x00dev, 86, 0);
3229 }
f4450616
BZ		 3230
3231 if (rf->channel <= 14) {
2ed71884 3232 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 3233 !rt2x00_rt(rt2x00dev, RT5392)) {
c429dfef 3234 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
adde5882
GJ		 3235 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3236 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3237 } else {
f42b0465
GJ		 3238 if (rt2x00_rt(rt2x00dev, RT3593))
3239 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3240 else
3241 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3242 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3243 }
f42b0465
GJ		 3244 if (rt2x00_rt(rt2x00dev, RT3593))
3245 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3246 }
f42b0465 3247
f4450616 3248 } else {
872834df
GW		 3249 if (rt2x00_rt(rt2x00dev, RT3572))
3250 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3251 else if (rt2x00_rt(rt2x00dev, RT3593))
3252 rt2800_bbp_write(rt2x00dev, 82, 0x82);
872834df
GW		 3253 else
3254 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3255
f42b0465
GJ		 3256 if (rt2x00_rt(rt2x00dev, RT3593))
3257 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3258
c429dfef 3259 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
f4450616
BZ		 3260 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3261 else
3262 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3263 }
3264
3265 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3266 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3267 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3268 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3269 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3270
872834df
GW		 3271 if (rt2x00_rt(rt2x00dev, RT3572))
3272 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3273
f4450616
BZ		 3274 tx_pin = 0;
3275
bb16d488
GJ		 3276 switch (rt2x00dev->default_ant.tx_chain_num) {
3277 case 3:
3278 /* Turn on tertiary PAs */
3279 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3280 rf->channel > 14);
3281 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3282 rf->channel <= 14);
3283 /* fall-through */
3284 case 2:
3285 /* Turn on secondary PAs */
65f31b5e
GW		 3286 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3287 rf->channel > 14);
3288 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3289 rf->channel <= 14);
bb16d488
GJ		 3290 /* fall-through */
3291 case 1:
3292 /* Turn on primary PAs */
3293 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3294 rf->channel > 14);
c429dfef 3295 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
bb16d488
GJ		 3296 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3297 else
3298 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3299 rf->channel <= 14);
3300 break;
f4450616
BZ		 3301 }
3302
bb16d488
GJ		 3303 switch (rt2x00dev->default_ant.rx_chain_num) {
3304 case 3:
3305 /* Turn on tertiary LNAs */
3306 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3307 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3308 /* fall-through */
3309 case 2:
3310 /* Turn on secondary LNAs */
f4450616
BZ		 3311 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3312 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3313 /* fall-through */
3314 case 1:
3315 /* Turn on primary LNAs */
3316 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3317 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3318 break;
f4450616
BZ		 3319 }
3320
f4450616
BZ		 3321 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3322 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 3323
3324 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3325
733aec6a 3326 if (rt2x00_rt(rt2x00dev, RT3572)) {
872834df
GW		 3327 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3328
733aec6a
GJ		 3329 /* AGC init */
3330 if (rf->channel <= 14)
3331 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3332 else
3333 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3334
3335 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3336 }
3337
f42b0465 3338 if (rt2x00_rt(rt2x00dev, RT3593)) {
60751001 3339 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
f42b0465 3340
60751001
GJ		 3341 /* Band selection */
3342 if (rt2x00_is_usb(rt2x00dev) ||
3343 rt2x00_is_pcie(rt2x00dev)) {
3344 /* GPIO #8 controls all paths */
f42b0465
GJ		 3345 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3346 if (rf->channel <= 14)
3347 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3348 else
3349 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
60751001 3350 }
f42b0465 3351
60751001
GJ		 3352 /* LNA PE control. */
3353 if (rt2x00_is_usb(rt2x00dev)) {
3354 /* GPIO #4 controls PE0 and PE1,
3355 * GPIO #7 controls PE2
3356 */
f42b0465
GJ		 3357 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3358 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3359
f42b0465
GJ		 3360 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3361 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
60751001
GJ		 3362 } else if (rt2x00_is_pcie(rt2x00dev)) {
3363 /* GPIO #4 controls PE0, PE1 and PE2 */
3364 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3365 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
f42b0465
GJ		 3366 }
3367
60751001
GJ		 3368 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3369
f42b0465
GJ		 3370 /* AGC init */
3371 if (rf->channel <= 14)
3372 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3373 else
3374 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3375
3376 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3377
3378 usleep_range(1000, 1500);
3379 }
3380
6803141b
SG		 3381 if (rt2x00_rt(rt2x00dev, RT5592)) {
3382 rt2800_bbp_write(rt2x00dev, 195, 141);
3383 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3384
8ba0ebf3
SG		 3385 /* AGC init */
3386 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3387 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3388
8756130b 3389 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3390 }
3391
f4450616
BZ		 3392 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3393 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3394 rt2800_bbp_write(rt2x00dev, 4, bbp);
3395
3396 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3397 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3398 rt2800_bbp_write(rt2x00dev, 3, bbp);
3399
8d0c9b65 3400 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3401 if (conf_is_ht40(conf)) {
3402 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3403 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3404 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3405 } else {
3406 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3407 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3408 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3409 }
3410 }
3411
3412 msleep(1);
977206d7
HS		 3413
3414 /*
3415 * Clear channel statistic counters
3416 */
3417 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3418 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3419 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3420
3421 /*
3422 * Clear update flag
3423 */
3424 if (rt2x00_rt(rt2x00dev, RT3352)) {
3425 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3426 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3427 rt2800_bbp_write(rt2x00dev, 49, bbp);
3428 }
f4450616
BZ		 3429}
3430
9e33a355
HS		 3431static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3432{
3433 u8 tssi_bounds[9];
3434 u8 current_tssi;
3435 u16 eeprom;
3436 u8 step;
3437 int i;
3438
6e956da2
SG		 3439 /*
3440 * First check if temperature compensation is supported.
3441 */
3442 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3443 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3444 return 0;
3445
9e33a355
HS		 3446 /*
3447 * Read TSSI boundaries for temperature compensation from
3448 * the EEPROM.
3449 *
3450 * Array idx 0 1 2 3 4 5 6 7 8
3451 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3452 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3453 */
57fbcce3 3454 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 3455 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3456 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3457 EEPROM_TSSI_BOUND_BG1_MINUS4);
3458 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3459 EEPROM_TSSI_BOUND_BG1_MINUS3);
3460
3e38d3da 3461 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3462 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3463 EEPROM_TSSI_BOUND_BG2_MINUS2);
3464 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3465 EEPROM_TSSI_BOUND_BG2_MINUS1);
3466
3e38d3da 3467 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3468 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3469 EEPROM_TSSI_BOUND_BG3_REF);
3470 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3471 EEPROM_TSSI_BOUND_BG3_PLUS1);
3472
3e38d3da 3473 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3474 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3475 EEPROM_TSSI_BOUND_BG4_PLUS2);
3476 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3477 EEPROM_TSSI_BOUND_BG4_PLUS3);
3478
3e38d3da 3479 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3480 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3481 EEPROM_TSSI_BOUND_BG5_PLUS4);
3482
3483 step = rt2x00_get_field16(eeprom,
3484 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3485 } else {
3e38d3da 3486 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3487 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3488 EEPROM_TSSI_BOUND_A1_MINUS4);
3489 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3490 EEPROM_TSSI_BOUND_A1_MINUS3);
3491
3e38d3da 3492 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3493 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3494 EEPROM_TSSI_BOUND_A2_MINUS2);
3495 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3496 EEPROM_TSSI_BOUND_A2_MINUS1);
3497
3e38d3da 3498 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3499 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3500 EEPROM_TSSI_BOUND_A3_REF);
3501 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3502 EEPROM_TSSI_BOUND_A3_PLUS1);
3503
3e38d3da 3504 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3505 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3506 EEPROM_TSSI_BOUND_A4_PLUS2);
3507 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3508 EEPROM_TSSI_BOUND_A4_PLUS3);
3509
3e38d3da 3510 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3511 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3512 EEPROM_TSSI_BOUND_A5_PLUS4);
3513
3514 step = rt2x00_get_field16(eeprom,
3515 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3516 }
3517
3518 /*
3519 * Check if temperature compensation is supported.
3520 */
bf7e1abe 3521 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3522 return 0;
3523
3524 /*
3525 * Read current TSSI (BBP 49).
3526 */
3527 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3528
3529 /*
3530 * Compare TSSI value (BBP49) with the compensation boundaries
3531 * from the EEPROM and increase or decrease tx power.
3532 */
3533 for (i = 0; i <= 3; i++) {
3534 if (current_tssi > tssi_bounds[i])
3535 break;
3536 }
3537
3538 if (i == 4) {
3539 for (i = 8; i >= 5; i--) {
3540 if (current_tssi < tssi_bounds[i])
3541 break;
3542 }
3543 }
3544
3545 return (i - 4) * step;
3546}
3547
e90c54b2 3548static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
57fbcce3 3549 enum nl80211_band band)
e90c54b2
RJH		 3550{
3551 u16 eeprom;
3552 u8 comp_en;
3553 u8 comp_type;
75faae8b 3554 int comp_value = 0;
e90c54b2 3555
3e38d3da 3556 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3557
75faae8b
HS		 3558 /*
3559 * HT40 compensation not required.
3560 */
3561 if (eeprom == 0xffff ||
3562 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3563 return 0;
3564
57fbcce3 3565 if (band == NL80211_BAND_2GHZ) {
e90c54b2
RJH		 3566 comp_en = rt2x00_get_field16(eeprom,
3567 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3568 if (comp_en) {
3569 comp_type = rt2x00_get_field16(eeprom,
3570 EEPROM_TXPOWER_DELTA_TYPE_2G);
3571 comp_value = rt2x00_get_field16(eeprom,
3572 EEPROM_TXPOWER_DELTA_VALUE_2G);
3573 if (!comp_type)
3574 comp_value = -comp_value;
3575 }
3576 } else {
3577 comp_en = rt2x00_get_field16(eeprom,
3578 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3579 if (comp_en) {
3580 comp_type = rt2x00_get_field16(eeprom,
3581 EEPROM_TXPOWER_DELTA_TYPE_5G);
3582 comp_value = rt2x00_get_field16(eeprom,
3583 EEPROM_TXPOWER_DELTA_VALUE_5G);
3584 if (!comp_type)
3585 comp_value = -comp_value;
3586 }
3587 }
3588
3589 return comp_value;
3590}
3591
1e4cf249
SG		 3592static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3593 int power_level, int max_power)
3594{
3595 int delta;
3596
c429dfef 3597 if (rt2x00_has_cap_power_limit(rt2x00dev))
1e4cf249
SG		 3598 return 0;
3599
3600 /*
3601 * XXX: We don't know the maximum transmit power of our hardware since
3602 * the EEPROM doesn't expose it. We only know that we are calibrated
3603 * to 100% tx power.
3604 *
3605 * Hence, we assume the regulatory limit that cfg80211 calulated for
3606 * the current channel is our maximum and if we are requested to lower
3607 * the value we just reduce our tx power accordingly.
3608 */
3609 delta = power_level - max_power;
3610 return min(delta, 0);
3611}
3612
fa71a160 3613static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
57fbcce3 3614 enum nl80211_band band, int power_level,
fa71a160 3615 u8 txpower, int delta)
e90c54b2 3616{
e90c54b2
RJH		 3617 u16 eeprom;
3618 u8 criterion;
3619 u8 eirp_txpower;
3620 u8 eirp_txpower_criterion;
3621 u8 reg_limit;
e90c54b2 3622
34542ff5
GJ		 3623 if (rt2x00_rt(rt2x00dev, RT3593))
3624 return min_t(u8, txpower, 0xc);
3625
c429dfef 3626 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
e90c54b2
RJH		 3627 /*
3628 * Check if eirp txpower exceed txpower_limit.
3629 * We use OFDM 6M as criterion and its eirp txpower
3630 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3631 * .11b data rate need add additional 4dbm
3632 * when calculating eirp txpower.
3633 */
022138ca
GJ		 3634 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3635 1, &eeprom);
d9bceaeb
SG		 3636 criterion = rt2x00_get_field16(eeprom,
3637 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3638
3e38d3da 3639 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3640 &eeprom);
e90c54b2 3641
57fbcce3 3642 if (band == NL80211_BAND_2GHZ)
e90c54b2
RJH		 3643 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3644 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3645 else
3646 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3647 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3648
3649 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3650 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3651
3652 reg_limit = (eirp_txpower > power_level) ?
3653 (eirp_txpower - power_level) : 0;
3654 } else
3655 reg_limit = 0;
3656
19f3fa24
SG		 3657 txpower = max(0, txpower + delta - reg_limit);
3658 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3659}
3660
34542ff5
GJ		 3661
3662enum {
3663 TX_PWR_CFG_0_IDX,
3664 TX_PWR_CFG_1_IDX,
3665 TX_PWR_CFG_2_IDX,
3666 TX_PWR_CFG_3_IDX,
3667 TX_PWR_CFG_4_IDX,
3668 TX_PWR_CFG_5_IDX,
3669 TX_PWR_CFG_6_IDX,
3670 TX_PWR_CFG_7_IDX,
3671 TX_PWR_CFG_8_IDX,
3672 TX_PWR_CFG_9_IDX,
3673 TX_PWR_CFG_0_EXT_IDX,
3674 TX_PWR_CFG_1_EXT_IDX,
3675 TX_PWR_CFG_2_EXT_IDX,
3676 TX_PWR_CFG_3_EXT_IDX,
3677 TX_PWR_CFG_4_EXT_IDX,
3678 TX_PWR_CFG_IDX_COUNT,
3679};
3680
3681static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3682 struct ieee80211_channel *chan,
3683 int power_level)
3684{
3685 u8 txpower;
3686 u16 eeprom;
3687 u32 regs[TX_PWR_CFG_IDX_COUNT];
3688 unsigned int offset;
57fbcce3 3689 enum nl80211_band band = chan->band;
34542ff5
GJ		 3690 int delta;
3691 int i;
3692
3693 memset(regs, '\0', sizeof(regs));
3694
3695 /* TODO: adapt TX power reduction from the rt28xx code */
3696
3697 /* calculate temperature compensation delta */
3698 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3699
57fbcce3 3700 if (band == NL80211_BAND_5GHZ)
34542ff5
GJ		 3701 offset = 16;
3702 else
3703 offset = 0;
3704
3705 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3706 offset += 8;
3707
3708 /* read the next four txpower values */
3709 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3710 offset, &eeprom);
3711
3712 /* CCK 1MBS,2MBS */
3713 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3714 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3715 txpower, delta);
3716 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3717 TX_PWR_CFG_0_CCK1_CH0, txpower);
3718 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3719 TX_PWR_CFG_0_CCK1_CH1, txpower);
3720 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3721 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3722
3723 /* CCK 5.5MBS,11MBS */
3724 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3725 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3726 txpower, delta);
3727 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3728 TX_PWR_CFG_0_CCK5_CH0, txpower);
3729 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3730 TX_PWR_CFG_0_CCK5_CH1, txpower);
3731 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3732 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3733
3734 /* OFDM 6MBS,9MBS */
3735 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3736 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3737 txpower, delta);
3738 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3739 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3740 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3741 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3742 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3743 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3744
3745 /* OFDM 12MBS,18MBS */
3746 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3747 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3748 txpower, delta);
3749 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3750 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3751 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3752 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3753 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3754 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3755
3756 /* read the next four txpower values */
3757 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3758 offset + 1, &eeprom);
3759
3760 /* OFDM 24MBS,36MBS */
3761 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3762 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3763 txpower, delta);
3764 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3765 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3766 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3767 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3768 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3769 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3770
3771 /* OFDM 48MBS */
3772 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3773 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3774 txpower, delta);
3775 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3776 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3777 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3778 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3779 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3780 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3781
3782 /* OFDM 54MBS */
3783 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3784 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3785 txpower, delta);
3786 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3787 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3788 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3789 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3790 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3791 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3792
3793 /* read the next four txpower values */
3794 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3795 offset + 2, &eeprom);
3796
3797 /* MCS 0,1 */
3798 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3799 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3800 txpower, delta);
3801 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3802 TX_PWR_CFG_1_MCS0_CH0, txpower);
3803 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3804 TX_PWR_CFG_1_MCS0_CH1, txpower);
3805 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3806 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3807
3808 /* MCS 2,3 */
3809 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3810 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3811 txpower, delta);
3812 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3813 TX_PWR_CFG_1_MCS2_CH0, txpower);
3814 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3815 TX_PWR_CFG_1_MCS2_CH1, txpower);
3816 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3817 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3818
3819 /* MCS 4,5 */
3820 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3821 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3822 txpower, delta);
3823 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3824 TX_PWR_CFG_2_MCS4_CH0, txpower);
3825 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3826 TX_PWR_CFG_2_MCS4_CH1, txpower);
3827 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3828 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3829
3830 /* MCS 6 */
3831 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3832 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3833 txpower, delta);
3834 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3835 TX_PWR_CFG_2_MCS6_CH0, txpower);
3836 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3837 TX_PWR_CFG_2_MCS6_CH1, txpower);
3838 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3839 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3840
3841 /* read the next four txpower values */
3842 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3843 offset + 3, &eeprom);
3844
3845 /* MCS 7 */
3846 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3847 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3848 txpower, delta);
3849 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3850 TX_PWR_CFG_7_MCS7_CH0, txpower);
3851 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3852 TX_PWR_CFG_7_MCS7_CH1, txpower);
3853 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3854 TX_PWR_CFG_7_MCS7_CH2, txpower);
3855
3856 /* MCS 8,9 */
3857 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3858 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3859 txpower, delta);
3860 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3861 TX_PWR_CFG_2_MCS8_CH0, txpower);
3862 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3863 TX_PWR_CFG_2_MCS8_CH1, txpower);
3864 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3865 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3866
3867 /* MCS 10,11 */
3868 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3869 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3870 txpower, delta);
3871 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3872 TX_PWR_CFG_2_MCS10_CH0, txpower);
3873 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3874 TX_PWR_CFG_2_MCS10_CH1, txpower);
3875 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3876 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3877
3878 /* MCS 12,13 */
3879 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3880 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3881 txpower, delta);
3882 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3883 TX_PWR_CFG_3_MCS12_CH0, txpower);
3884 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3885 TX_PWR_CFG_3_MCS12_CH1, txpower);
3886 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3887 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3888
3889 /* read the next four txpower values */
3890 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3891 offset + 4, &eeprom);
3892
3893 /* MCS 14 */
3894 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3895 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3896 txpower, delta);
3897 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3898 TX_PWR_CFG_3_MCS14_CH0, txpower);
3899 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3900 TX_PWR_CFG_3_MCS14_CH1, txpower);
3901 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3902 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3903
3904 /* MCS 15 */
3905 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3906 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3907 txpower, delta);
3908 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3909 TX_PWR_CFG_8_MCS15_CH0, txpower);
3910 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3911 TX_PWR_CFG_8_MCS15_CH1, txpower);
3912 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3913 TX_PWR_CFG_8_MCS15_CH2, txpower);
3914
3915 /* MCS 16,17 */
3916 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3917 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3918 txpower, delta);
3919 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3920 TX_PWR_CFG_5_MCS16_CH0, txpower);
3921 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3922 TX_PWR_CFG_5_MCS16_CH1, txpower);
3923 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3924 TX_PWR_CFG_5_MCS16_CH2, txpower);
3925
3926 /* MCS 18,19 */
3927 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3928 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3929 txpower, delta);
3930 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3931 TX_PWR_CFG_5_MCS18_CH0, txpower);
3932 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3933 TX_PWR_CFG_5_MCS18_CH1, txpower);
3934 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3935 TX_PWR_CFG_5_MCS18_CH2, txpower);
3936
3937 /* read the next four txpower values */
3938 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3939 offset + 5, &eeprom);
3940
3941 /* MCS 20,21 */
3942 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3943 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3944 txpower, delta);
3945 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3946 TX_PWR_CFG_6_MCS20_CH0, txpower);
3947 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3948 TX_PWR_CFG_6_MCS20_CH1, txpower);
3949 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3950 TX_PWR_CFG_6_MCS20_CH2, txpower);
3951
3952 /* MCS 22 */
3953 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3954 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3955 txpower, delta);
3956 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3957 TX_PWR_CFG_6_MCS22_CH0, txpower);
3958 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3959 TX_PWR_CFG_6_MCS22_CH1, txpower);
3960 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3961 TX_PWR_CFG_6_MCS22_CH2, txpower);
3962
3963 /* MCS 23 */
3964 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3965 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3966 txpower, delta);
3967 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3968 TX_PWR_CFG_8_MCS23_CH0, txpower);
3969 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3970 TX_PWR_CFG_8_MCS23_CH1, txpower);
3971 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3972 TX_PWR_CFG_8_MCS23_CH2, txpower);
3973
3974 /* read the next four txpower values */
3975 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3976 offset + 6, &eeprom);
3977
3978 /* STBC, MCS 0,1 */
3979 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3980 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3981 txpower, delta);
3982 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3983 TX_PWR_CFG_3_STBC0_CH0, txpower);
3984 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3985 TX_PWR_CFG_3_STBC0_CH1, txpower);
3986 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3987 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3988
3989 /* STBC, MCS 2,3 */
3990 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3991 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3992 txpower, delta);
3993 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3994 TX_PWR_CFG_3_STBC2_CH0, txpower);
3995 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3996 TX_PWR_CFG_3_STBC2_CH1, txpower);
3997 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3998 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3999
4000 /* STBC, MCS 4,5 */
4001 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4002 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4003 txpower, delta);
4004 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4005 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4006 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4007 txpower);
4008
4009 /* STBC, MCS 6 */
4010 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4011 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4012 txpower, delta);
4013 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4014 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4015 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4016 txpower);
4017
4018 /* read the next four txpower values */
4019 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4020 offset + 7, &eeprom);
4021
4022 /* STBC, MCS 7 */
4023 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4024 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4025 txpower, delta);
4026 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4027 TX_PWR_CFG_9_STBC7_CH0, txpower);
4028 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4029 TX_PWR_CFG_9_STBC7_CH1, txpower);
4030 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4031 TX_PWR_CFG_9_STBC7_CH2, txpower);
4032
4033 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4034 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4035 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4036 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4037 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4038 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4039 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4040 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4041 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4042 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4043
4044 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4045 regs[TX_PWR_CFG_0_EXT_IDX]);
4046 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4047 regs[TX_PWR_CFG_1_EXT_IDX]);
4048 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4049 regs[TX_PWR_CFG_2_EXT_IDX]);
4050 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4051 regs[TX_PWR_CFG_3_EXT_IDX]);
4052 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4053 regs[TX_PWR_CFG_4_EXT_IDX]);
4054
4055 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4056 rt2x00_dbg(rt2x00dev,
4057 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
57fbcce3 4058 (band == NL80211_BAND_5GHZ) ? '5' : '2',
34542ff5
GJ		 4059 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4060 '4' : '2',
4061 (i > TX_PWR_CFG_9_IDX) ?
4062 (i - TX_PWR_CFG_9_IDX - 1) : i,
4063 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4064 (unsigned long) regs[i]);
4065}
4066
7a66205a
SG		 4067/*
4068 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4069 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4070 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4071 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4072 * Reference per rate transmit power values are located in the EEPROM at
4073 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4074 * current conditions (i.e. band, bandwidth, temperature, user settings).
4075 */
34542ff5
GJ		 4076static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4077 struct ieee80211_channel *chan,
4078 int power_level)
f4450616 4079{
cee2c731 4080 u8 txpower, r1;
5e846004 4081 u16 eeprom;
cee2c731
SG		 4082 u32 reg, offset;
4083 int i, is_rate_b, delta, power_ctrl;
57fbcce3 4084 enum nl80211_band band = chan->band;
2af242e1
HS		 4085
4086 /*
7a66205a
SG		 4087 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4088 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4089 */
4090 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4091
9e33a355 4092 /*
7a66205a
SG		 4093 * Calculate temperature compensation. Depends on measurement of current
4094 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4095 * to temperature or maybe other factors) is smaller or bigger than
4096 * expected. We adjust it, based on TSSI reference and boundaries values
4097 * provided in EEPROM.
9e33a355 4098 */
87dd2d76
SG		 4099 switch (rt2x00dev->chip.rt) {
4100 case RT2860:
4101 case RT2872:
4102 case RT2883:
4103 case RT3070:
4104 case RT3071:
4105 case RT3090:
4106 case RT3572:
4107 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4108 break;
4109 default:
4110 /* TODO: temperature compensation code for other chips. */
4111 break;
4112 }
f4450616 4113
1e4cf249 4114 /*
7a66205a
SG		 4115 * Decrease power according to user settings, on devices with unknown
4116 * maximum tx power. For other devices we take user power_level into
4117 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4118 */
4119 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4120 chan->max_power);
4121
5e846004 4122 /*
cee2c731
SG		 4123 * BBP_R1 controls TX power for all rates, it allow to set the following
4124 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4125 *
4126 * TODO: we do not use +6 dBm option to do not increase power beyond
4127 * regulatory limit, however this could be utilized for devices with
4128 * CAPABILITY_POWER_LIMIT.
8c8d2017 4129 */
87dd2d76
SG		 4130 if (delta <= -12) {
4131 power_ctrl = 2;
4132 delta += 12;
4133 } else if (delta <= -6) {
4134 power_ctrl = 1;
4135 delta += 6;
4136 } else {
4137 power_ctrl = 0;
cee2c731 4138 }
87dd2d76
SG		 4139 rt2800_bbp_read(rt2x00dev, 1, &r1);
4140 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4141 rt2800_bbp_write(rt2x00dev, 1, r1);
8c8d2017 4142
5e846004
HS		 4143 offset = TX_PWR_CFG_0;
4144
4145 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4146 /* just to be safe */
4147 if (offset > TX_PWR_CFG_4)
4148 break;
4149
4150 rt2800_register_read(rt2x00dev, offset, &reg);
4151
4152 /* read the next four txpower values */
022138ca
GJ		 4153 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4154 i, &eeprom);
5e846004 4155
e90c54b2
RJH		 4156 is_rate_b = i ? 0 : 1;
4157 /*
4158 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4159 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4160 * TX_PWR_CFG_4: unknown
4161 */
5e846004
HS		 4162 txpower = rt2x00_get_field16(eeprom,
4163 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4164 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4165 power_level, txpower, delta);
e90c54b2 4166 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4167
e90c54b2
RJH		 4168 /*
4169 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4170 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4171 * TX_PWR_CFG_4: unknown
4172 */
5e846004
HS		 4173 txpower = rt2x00_get_field16(eeprom,
4174 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4175 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4176 power_level, txpower, delta);
e90c54b2 4177 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4178
e90c54b2
RJH		 4179 /*
4180 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4181 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4182 * TX_PWR_CFG_4: unknown
4183 */
5e846004
HS		 4184 txpower = rt2x00_get_field16(eeprom,
4185 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4186 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4187 power_level, txpower, delta);
e90c54b2 4188 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4189
e90c54b2
RJH		 4190 /*
4191 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4192 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4193 * TX_PWR_CFG_4: unknown
4194 */
5e846004
HS		 4195 txpower = rt2x00_get_field16(eeprom,
4196 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4197 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4198 power_level, txpower, delta);
e90c54b2 4199 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4200
4201 /* read the next four txpower values */
022138ca
GJ		 4202 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4203 i + 1, &eeprom);
5e846004 4204
e90c54b2
RJH		 4205 is_rate_b = 0;
4206 /*
4207 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4208 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4209 * TX_PWR_CFG_4: unknown
4210 */
5e846004
HS		 4211 txpower = rt2x00_get_field16(eeprom,
4212 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4213 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4214 power_level, txpower, delta);
e90c54b2 4215 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4216
e90c54b2
RJH		 4217 /*
4218 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4219 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4220 * TX_PWR_CFG_4: unknown
4221 */
5e846004
HS		 4222 txpower = rt2x00_get_field16(eeprom,
4223 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4224 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4225 power_level, txpower, delta);
e90c54b2 4226 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4227
e90c54b2
RJH		 4228 /*
4229 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4230 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4231 * TX_PWR_CFG_4: unknown
4232 */
5e846004
HS		 4233 txpower = rt2x00_get_field16(eeprom,
4234 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4235 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4236 power_level, txpower, delta);
e90c54b2 4237 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4238
e90c54b2
RJH		 4239 /*
4240 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4241 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4242 * TX_PWR_CFG_4: unknown
4243 */
5e846004
HS		 4244 txpower = rt2x00_get_field16(eeprom,
4245 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4246 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4247 power_level, txpower, delta);
e90c54b2 4248 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4249
4250 rt2800_register_write(rt2x00dev, offset, reg);
4251
4252 /* next TX_PWR_CFG register */
4253 offset += 4;
4254 }
f4450616
BZ		 4255}
4256
34542ff5
GJ		 4257static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4258 struct ieee80211_channel *chan,
4259 int power_level)
4260{
4261 if (rt2x00_rt(rt2x00dev, RT3593))
4262 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4263 else
4264 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4265}
4266
9e33a355
HS		 4267void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4268{
675a0b04 4269 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4270 rt2x00dev->tx_power);
4271}
4272EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4273
2e9c43dd
JL		 4274void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4275{
4276 u32 tx_pin;
4277 u8 rfcsr;
4278
4279 /*
4280 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4281 * designed to be controlled in oscillation frequency by a voltage
4282 * input. Maybe the temperature will affect the frequency of
4283 * oscillation to be shifted. The VCO calibration will be called
4284 * periodically to adjust the frequency to be precision.
4285 */
4286
4287 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4288 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4289 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4290
4291 switch (rt2x00dev->chip.rf) {
4292 case RF2020:
4293 case RF3020:
4294 case RF3021:
4295 case RF3022:
4296 case RF3320:
4297 case RF3052:
4298 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4299 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4300 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4301 break;
1095df07 4302 case RF3053:
3b9b74ba 4303 case RF3070:
a89534ed 4304 case RF3290:
ccf91bd6 4305 case RF5360:
ac0372ab 4306 case RF5362:
2e9c43dd
JL		 4307 case RF5370:
4308 case RF5372:
4309 case RF5390:
cff3d1f0 4310 case RF5392:
2e9c43dd 4311 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 4312 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 4313 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4314 break;
4315 default:
4316 return;
4317 }
4318
4319 mdelay(1);
4320
4321 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4322 if (rt2x00dev->rf_channel <= 14) {
4323 switch (rt2x00dev->default_ant.tx_chain_num) {
4324 case 3:
4325 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4326 /* fall through */
4327 case 2:
4328 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4329 /* fall through */
4330 case 1:
4331 default:
4332 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4333 break;
4334 }
4335 } else {
4336 switch (rt2x00dev->default_ant.tx_chain_num) {
4337 case 3:
4338 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4339 /* fall through */
4340 case 2:
4341 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4342 /* fall through */
4343 case 1:
4344 default:
4345 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4346 break;
4347 }
4348 }
4349 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4350
4351}
4352EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4353
f4450616
BZ		 4354static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4355 struct rt2x00lib_conf *libconf)
4356{
4357 u32 reg;
4358
4359 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4360 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4361 libconf->conf->short_frame_max_tx_count);
4362 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4363 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4364 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4365}
4366
4367static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4368 struct rt2x00lib_conf *libconf)
4369{
4370 enum dev_state state =
4371 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4372 STATE_SLEEP : STATE_AWAKE;
4373 u32 reg;
4374
4375 if (state == STATE_SLEEP) {
4376 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4377
4378 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4379 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4380 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4381 libconf->conf->listen_interval - 1);
4382 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4383 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4384
4385 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4386 } else {
f4450616
BZ		 4387 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4388 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4389 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4390 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4391 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 4392
4393 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 4394 }
4395}
4396
4397void rt2800_config(struct rt2x00_dev *rt2x00dev,
4398 struct rt2x00lib_conf *libconf,
4399 const unsigned int flags)
4400{
4401 /* Always recalculate LNA gain before changing configuration */
4402 rt2800_config_lna_gain(rt2x00dev, libconf);
4403
e90c54b2 4404 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 4405 rt2800_config_channel(rt2x00dev, libconf->conf,
4406 &libconf->rf, &libconf->channel);
675a0b04 4407 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4408 libconf->conf->power_level);
e90c54b2 4409 }
f4450616 4410 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 4411 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4412 libconf->conf->power_level);
f4450616
BZ		 4413 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4414 rt2800_config_retry_limit(rt2x00dev, libconf);
4415 if (flags & IEEE80211_CONF_CHANGE_PS)
4416 rt2800_config_ps(rt2x00dev, libconf);
4417}
4418EXPORT_SYMBOL_GPL(rt2800_config);
4419
4420/*
4421 * Link tuning
4422 */
4423void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4424{
4425 u32 reg;
4426
4427 /*
4428 * Update FCS error count from register.
4429 */
4430 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4431 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4432}
4433EXPORT_SYMBOL_GPL(rt2800_link_stats);
4434
4435static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4436{
8c6728b0
GW		 4437 u8 vgc;
4438
57fbcce3 4439 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
d5385bfc 4440 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 4441 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4442 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4443 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 4444 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 4445 rt2x00_rt(rt2x00dev, RT3572) ||
0ffd2a9a 4446 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 4447 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 4448 rt2x00_rt(rt2x00dev, RT5392) ||
4449 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 4450 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4451 else
4452 vgc = 0x2e + rt2x00dev->lna_gain;
4453 } else { /* 5GHZ band */
733aec6a 4454 if (rt2x00_rt(rt2x00dev, RT3593))
0ffd2a9a 4455 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 4456 else if (rt2x00_rt(rt2x00dev, RT5592))
4457 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 4458 else {
4459 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4460 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4461 else
4462 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4463 }
f4450616
BZ		 4464 }
4465
8c6728b0 4466 return vgc;
f4450616
BZ		 4467}
4468
4469static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4470 struct link_qual *qual, u8 vgc_level)
4471{
4472 if (qual->vgc_level != vgc_level) {
271f1a4d
GJ		 4473 if (rt2x00_rt(rt2x00dev, RT3572) ||
4474 rt2x00_rt(rt2x00dev, RT3593)) {
4475 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4476 vgc_level);
4477 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
3d81535e
SG		 4478 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4479 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
271f1a4d 4480 } else {
3d81535e 4481 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
271f1a4d
GJ		 4482 }
4483
f4450616
BZ		 4484 qual->vgc_level = vgc_level;
4485 qual->vgc_level_reg = vgc_level;
4486 }
4487}
4488
4489void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4490{
4491 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4492}
4493EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4494
4495void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4496 const u32 count)
4497{
3d81535e
SG		 4498 u8 vgc;
4499
8d0c9b65 4500 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 4501 return;
e25aa82a
GJ		 4502
4503 /* When RSSI is better than a certain threshold, increase VGC
4504 * with a chip specific value in order to improve the balance
4505 * between sensibility and noise isolation.
f4450616 4506 */
3d81535e
SG		 4507
4508 vgc = rt2800_get_default_vgc(rt2x00dev);
4509
e25aa82a
GJ		 4510 switch (rt2x00dev->chip.rt) {
4511 case RT3572:
4512 case RT3593:
4513 if (qual->rssi > -65) {
57fbcce3 4514 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
e25aa82a
GJ		 4515 vgc += 0x20;
4516 else
4517 vgc += 0x10;
4518 }
4519 break;
4520
4521 case RT5592:
0beb1bbf
GJ		 4522 if (qual->rssi > -65)
4523 vgc += 0x20;
e25aa82a
GJ		 4524 break;
4525
4526 default:
0beb1bbf
GJ		 4527 if (qual->rssi > -80)
4528 vgc += 0x10;
e25aa82a 4529 break;
0beb1bbf 4530 }
3d81535e
SG		 4531
4532 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 4533}
4534EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 4535
4536/*
4537 * Initialization functions.
4538 */
b9a07ae9 4539static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4540{
4541 u32 reg;
d5385bfc 4542 u16 eeprom;
fcf51541 4543 unsigned int i;
e3a896b9 4544 int ret;
fcf51541 4545
f7b395e9 4546 rt2800_disable_wpdma(rt2x00dev);
a9dce149 4547
e3a896b9
GW		 4548 ret = rt2800_drv_init_registers(rt2x00dev);
4549 if (ret)
4550 return ret;
fcf51541 4551
fcf51541
BZ		 4552 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4553 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4554
4555 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4556
4557 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 4558 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 4559 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4560 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4561 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4562 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4563 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4564 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4565
a9dce149
GW		 4566 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4567
4568 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4569 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4570 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4571 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4572
a89534ed
WH		 4573 if (rt2x00_rt(rt2x00dev, RT3290)) {
4574 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4575 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4576 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4577 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4578 }
4579
4580 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4581 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4582 rt2x00_set_field32(&reg, LDO0_EN, 1);
4583 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4584 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4585 }
4586
4587 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4588 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4589 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4590 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4591 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4592
4593 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4594 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4595 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4596
4597 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4598 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4599 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4600 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4601 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4602 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4603
4604 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4605 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4606 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4607 }
4608
64522957 4609 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4610 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4611 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 4612 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 4613
4614 if (rt2x00_rt(rt2x00dev, RT3290))
4615 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4616 0x00000404);
4617 else
4618 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4619 0x00000400);
4620
fcf51541 4621 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 4622 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4623 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4624 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 4625 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4626 &eeprom);
38c8a566 4627 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4628 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4629 0x0000002c);
4630 else
4631 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4632 0x0000000f);
4633 } else {
4634 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4635 }
d5385bfc 4636 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 4637 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 4638
4639 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4640 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4641 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4642 } else {
4643 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4644 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4645 }
c295a81d
HS		 4646 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4647 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4648 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 4649 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 4650 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4651 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4652 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4653 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 4654 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4655 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4656 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 4657 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4658 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4659 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4660 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4661 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4662 &eeprom);
4663 if (rt2x00_get_field16(eeprom,
4664 EEPROM_NIC_CONF1_DAC_TEST))
4665 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4666 0x0000001f);
4667 else
4668 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4669 0x0000000f);
4670 } else {
4671 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4672 0x00000000);
4673 }
2ed71884 4674 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 4675 rt2x00_rt(rt2x00dev, RT5392) ||
4676 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 4677 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4678 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4679 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 4680 } else {
4681 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4682 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4683 }
4684
4685 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4686 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4687 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4688 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4689 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4690 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4691 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4692 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4693 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4694 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4695
4696 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4697 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 4698 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 4699 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4700 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4701
4702 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4703 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 4704 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 4705 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 4706 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 4707 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4708 else
4709 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4710 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4711 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4712 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4713
a9dce149
GW		 4714 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4715 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4716 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4717 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4718 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4719 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4720 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4721 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4722 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4723
fcf51541
BZ		 4724 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4725
a9dce149
GW		 4726 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4727 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4728 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4729 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4730 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4731 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4732 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4733 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4734
fcf51541
BZ		 4735 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4736 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 4737 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 4738 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4739 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 4740 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 4741 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4742 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4743 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4744
4745 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 4746 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4747 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4748 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4749 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4750 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4751 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4752 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4753 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4754 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4755 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4756 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4757
4758 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 4759 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4760 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4761 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4762 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4763 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4764 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4765 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4766 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4767 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4768 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4769 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4770
4771 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4772 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4773 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4774 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4775 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4776 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4777 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4778 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4779 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4780 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4781 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4782 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4783
4784 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4785 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 4786 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4787 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4788 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4789 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4790 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4791 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4792 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4793 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4794 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4795 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4796
4797 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4798 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4799 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4800 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4801 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4802 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4803 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4804 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4805 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4806 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4807 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4808 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4809
4810 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4811 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4812 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4813 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4814 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4815 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4816 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4817 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4818 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4819 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4820 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4821 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4822
cea90e55 4823 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 4824 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4825
4826 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4827 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4828 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4829 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4830 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4831 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4832 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4833 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4834 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4835 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4836 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4837 }
4838
961621ab
HS		 4839 /*
4840 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4841 * although it is reserved.
4842 */
4843 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4844 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4845 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4846 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4847 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4848 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4849 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4850 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4851 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4852 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4853 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4854 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4855
7641328d
SG		 4856 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4857 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 4858
4859 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4860 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4861 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4862 IEEE80211_MAX_RTS_THRESHOLD);
4863 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4864 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4865
4866 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 4867
a21c2ab4
HS		 4868 /*
4869 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4870 * time should be set to 16. However, the original Ralink driver uses
4871 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4872 * connection problems with 11g + CTS protection. Hence, use the same
4873 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4874 */
a9dce149 4875 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 4876 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4877 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 4878 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4879 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4880 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4881 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4882
fcf51541
BZ		 4883 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4884
4885 /*
4886 * ASIC will keep garbage value after boot, clear encryption keys.
4887 */
4888 for (i = 0; i < 4; i++)
4889 rt2800_register_write(rt2x00dev,
4890 SHARED_KEY_MODE_ENTRY(i), 0);
4891
4892 for (i = 0; i < 256; i++) {
d7d259d3
HS		 4893 rt2800_config_wcid(rt2x00dev, NULL, i);
4894 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 4895 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4896 }
4897
4898 /*
4899 * Clear all beacons
fcf51541 4900 */
77f7c0f3
GJ		 4901 for (i = 0; i < 8; i++)
4902 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 4903
cea90e55 4904 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 4905 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4906 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4907 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 4908 } else if (rt2x00_is_pcie(rt2x00dev)) {
4909 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4910 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4911 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 4912 }
4913
4914 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4915 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4916 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4917 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4918 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4919 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4920 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4921 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4922 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4923 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4924
4925 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4926 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4927 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4928 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4929 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4930 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4931 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4932 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4933 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4934 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4935
4936 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4937 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4938 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4939 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4940 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4941 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4942 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4943 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4944 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4945 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4946
4947 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4948 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4949 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4950 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4951 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4952 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4953
47ee3eb1
HS		 4954 /*
4955 * Do not force the BA window size, we use the TXWI to set it
4956 */
4957 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4958 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4959 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4960 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4961
fcf51541
BZ		 4962 /*
4963 * We must clear the error counters.
4964 * These registers are cleared on read,
4965 * so we may pass a useless variable to store the value.
4966 */
4967 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4968 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4969 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4970 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4971 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4972 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4973
9f926fb5
HS		 4974 /*
4975 * Setup leadtime for pre tbtt interrupt to 6ms
4976 */
4977 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4978 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4979 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4980
977206d7
HS		 4981 /*
4982 * Set up channel statistics timer
4983 */
4984 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4985 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4986 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4987 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4988 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4989 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4990 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4991
fcf51541
BZ		 4992 return 0;
4993}
fcf51541
BZ		 4994
4995static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4996{
4997 unsigned int i;
4998 u32 reg;
4999
5000 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5001 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5002 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5003 return 0;
5004
5005 udelay(REGISTER_BUSY_DELAY);
5006 }
5007
ec9c4989 5008 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 5009 return -EACCES;
5010}
5011
5012static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5013{
5014 unsigned int i;
5015 u8 value;
5016
5017 /*
5018 * BBP was enabled after firmware was loaded,
5019 * but we need to reactivate it now.
5020 */
5021 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5022 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5023 msleep(1);
5024
5025 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5026 rt2800_bbp_read(rt2x00dev, 0, &value);
5027 if ((value != 0xff) && (value != 0x00))
5028 return 0;
5029 udelay(REGISTER_BUSY_DELAY);
5030 }
5031
ec9c4989 5032 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 5033 return -EACCES;
5034}
5035
a7bbbe5c
SG		 5036static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5037{
5038 u8 value;
5039
5040 rt2800_bbp_read(rt2x00dev, 4, &value);
5041 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5042 rt2800_bbp_write(rt2x00dev, 4, value);
5043}
5044
c2675487
SG		 5045static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5046{
5047 rt2800_bbp_write(rt2x00dev, 142, 1);
5048 rt2800_bbp_write(rt2x00dev, 143, 57);
5049}
5050
a7bbbe5c
SG		 5051static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5052{
5053 const u8 glrt_table[] = {
5054 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5055 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5056 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5057 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5058 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5059 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5060 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5061 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5062 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5063 };
5064 int i;
5065
5066 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5067 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5068 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5069 }
5070};
5071
624708b8 5072static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5073{
5074 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5075 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5076 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5077 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5078 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5079 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5080 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5081 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5082 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5083 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5084 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5085 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5086 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5087 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5088 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5089 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5090}
5091
5df1ff3a
SG		 5092static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5093{
5094 u16 eeprom;
5095 u8 value;
5096
5097 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5098 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5099 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5100 value |= 0x20;
5101 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5102 value &= ~0x02;
5103 rt2800_bbp_write(rt2x00dev, 138, value);
5104}
5105
dae62957
SG		 5106static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5107{
b2f8e0bd 5108 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5109
5110 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5111 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5112
5113 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5114 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5115
5116 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5117
5118 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5119 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5120
5121 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5122
5123 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5124
5125 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5126
5127 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5128
5129 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5130
5131 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5132
5133 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5134
5135 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5136
5137 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5138}
5139
39ab3e8b
SG		 5140static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5141{
e379de12
SG		 5142 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5143 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5144
5145 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5146 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5147 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5148 } else {
5149 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5150 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5151 }
8d97be38
SG		 5152
5153 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5154
5155 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5156
5157 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5158
5159 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5160
5161 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5162 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5163 else
5164 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5165
5166 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5167
5168 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5169
5170 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5171
5172 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5173
5174 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5175
5176 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5177}
5178
5179static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5180{
e379de12
SG		 5181 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5182 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5183
5184 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5185 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5186
5187 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5188
5189 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5190 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5191 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5192
5193 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5194
5195 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5196
5197 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5198
5199 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5200
5201 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5202
5203 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5204
5205 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5206 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5207 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5208 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5209 else
5210 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5211
5212 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5213
5214 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5215
5216 if (rt2x00_rt(rt2x00dev, RT3071) ||
5217 rt2x00_rt(rt2x00dev, RT3090))
5218 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5219}
5220
5221static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5222{
6addb24e
SG		 5223 u8 value;
5224
c3223573 5225 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5226
5227 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5228
5229 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5230 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5231
5232 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5233
5234 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5235 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5236 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5237 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5238
5239 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5240
5241 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5242
5243 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5244 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5245 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5246 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5247
5248 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5249
5250 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5251
5252 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5253
5254 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5255
5256 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5257
5258 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5259
5260 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5261
5262 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5263
5264 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5265
5266 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5267
5268 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5269
5270 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5271 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5272 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5273 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5274 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5275 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5276 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5277 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5278 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5279 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5280
5281 rt2800_bbp_read(rt2x00dev, 47, &value);
5282 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5283 rt2800_bbp_write(rt2x00dev, 47, value);
5284
5285 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5286 rt2800_bbp_read(rt2x00dev, 3, &value);
5287 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5288 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5289 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5290}
5291
5292static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5293{
29f3a58b
SG		 5294 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5295 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5296
5297 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5298
5299 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5300
5301 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5302 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5303
5304 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5305
5306 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5307 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5308 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5309 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5310
5311 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5312
5313 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5314
5315 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5316 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5317 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5318
5319 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5320
5321 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5322
5323 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5324
5325 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5326
5327 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5328
5329 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5330
5331 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5332
5333 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5334
5335 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5336
5337 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 5338
5339 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 5340
5341 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 5342
5343 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 5344
5345 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5346 /* Set ITxBF timeout to 0x9c40=1000msec */
5347 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5348 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5349 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5350 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5351 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5352 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5353 /* Reprogram the inband interface to put right values in RXWI */
5354 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5355 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5356 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5357 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5358 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5359 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5360 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5361 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5362
5363 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 5364}
5365
5366static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5367{
e379de12
SG		 5368 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5369 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5370
5371 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5372 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5373
5374 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5375
5376 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5377 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5378 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5379
5380 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5381
5382 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5383
5384 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5385
5386 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5387
5388 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5389
5390 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5391
5392 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5393 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5394 else
5395 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5396
5397 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5398
5399 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5400
5401 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5402}
5403
5404static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5405{
b2f8e0bd 5406 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5407
5408 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5409 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5410
5411 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5412 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5413
5414 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5415
5416 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5417 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5418 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5419
5420 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5421
5422 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5423
5424 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5425
5426 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5427
5428 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5429
5430 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5431
5432 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5433
5434 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5435
5436 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5437
5438 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5439}
5440
b189a181
GJ		 5441static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5442{
5443 rt2800_init_bbp_early(rt2x00dev);
5444
5445 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5446 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5447 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5448 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5449
5450 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5451
5452 /* Enable DC filter */
5453 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5454 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5455}
5456
39ab3e8b
SG		 5457static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5458{
32ef8f49
SG		 5459 int ant, div_mode;
5460 u16 eeprom;
5461 u8 value;
5462
c3223573 5463 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5464
5465 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5466
5467 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5468 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5469
5470 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142 5471
58422191 5472 rt2800_bbp_write(rt2x00dev, 69, 0x12);
72ffe142
SG		 5473 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5474 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5475 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5476
5477 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38 5478
58422191
SG		 5479 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5480
43f535e2
SG		 5481 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5482 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5483 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5484
5485 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5486
5487 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5488
5489 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5490
5491 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5492
5493 if (rt2x00_rt(rt2x00dev, RT5392))
5494 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5495
5496 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5497
5498 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 5499
5500 if (rt2x00_rt(rt2x00dev, RT5392)) {
5501 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5502 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5503 }
672d1188
SG		 5504
5505 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5506
5507 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5508
5509 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 5510
5511 if (rt2x00_rt(rt2x00dev, RT5390))
5512 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5513 else if (rt2x00_rt(rt2x00dev, RT5392))
5514 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5515 else
5516 WARN_ON(1);
f2b6777c
SG		 5517
5518 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 5519
5520 if (rt2x00_rt(rt2x00dev, RT5392)) {
5521 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5522 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5523 }
5df1ff3a
SG		 5524
5525 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 5526
3e38d3da 5527 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 5528 div_mode = rt2x00_get_field16(eeprom,
5529 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5530 ant = (div_mode == 3) ? 1 : 0;
5531
5532 /* check if this is a Bluetooth combo card */
c429dfef 5533 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
32ef8f49
SG		 5534 u32 reg;
5535
5536 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5537 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5538 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5539 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5540 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5541 if (ant == 0)
5542 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5543 else if (ant == 1)
5544 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5545 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5546 }
5547
5548 /* This chip has hardware antenna diversity*/
5549 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5550 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5551 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5552 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5553 }
5554
5555 rt2800_bbp_read(rt2x00dev, 152, &value);
5556 if (ant == 0)
5557 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5558 else
5559 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5560 rt2800_bbp_write(rt2x00dev, 152, value);
5561
5562 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 5563}
5564
a7bbbe5c
SG		 5565static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5566{
5567 int ant, div_mode;
5568 u16 eeprom;
5569 u8 value;
5570
624708b8 5571 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 5572
a7bbbe5c
SG		 5573 rt2800_bbp_read(rt2x00dev, 105, &value);
5574 rt2x00_set_field8(&value, BBP105_MLD,
5575 rt2x00dev->default_ant.rx_chain_num == 2);
5576 rt2800_bbp_write(rt2x00dev, 105, value);
5577
5578 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5579
5580 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5581 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5582 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5583 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5584 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5585 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5586 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5587 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5588 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5589 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5590 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5591 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5592 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5593 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5594 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5595 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5596 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5597 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5598 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5599 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5600 /* FIXME BBP105 owerwrite */
5601 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5602 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5603 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5604 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5605 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5606 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5607
5608 /* Initialize GLRT (Generalized Likehood Radio Test) */
5609 rt2800_init_bbp_5592_glrt(rt2x00dev);
5610
5611 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5612
3e38d3da 5613 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 5614 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5615 ant = (div_mode == 3) ? 1 : 0;
5616 rt2800_bbp_read(rt2x00dev, 152, &value);
5617 if (ant == 0) {
5618 /* Main antenna */
5619 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5620 } else {
5621 /* Auxiliary antenna */
5622 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5623 }
5624 rt2800_bbp_write(rt2x00dev, 152, value);
5625
5626 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5627 rt2800_bbp_read(rt2x00dev, 254, &value);
5628 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5629 rt2800_bbp_write(rt2x00dev, 254, value);
5630 }
5631
c2675487
SG		 5632 rt2800_init_freq_calibration(rt2x00dev);
5633
a7bbbe5c 5634 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 5635 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5636 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 5637}
5638
a1ef5039 5639static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 5640{
5641 unsigned int i;
5642 u16 eeprom;
5643 u8 reg_id;
5644 u8 value;
5645
dae62957
SG		 5646 if (rt2800_is_305x_soc(rt2x00dev))
5647 rt2800_init_bbp_305x_soc(rt2x00dev);
5648
39ab3e8b
SG		 5649 switch (rt2x00dev->chip.rt) {
5650 case RT2860:
5651 case RT2872:
5652 case RT2883:
5653 rt2800_init_bbp_28xx(rt2x00dev);
5654 break;
5655 case RT3070:
5656 case RT3071:
5657 case RT3090:
5658 rt2800_init_bbp_30xx(rt2x00dev);
5659 break;
5660 case RT3290:
5661 rt2800_init_bbp_3290(rt2x00dev);
5662 break;
5663 case RT3352:
5664 rt2800_init_bbp_3352(rt2x00dev);
5665 break;
5666 case RT3390:
5667 rt2800_init_bbp_3390(rt2x00dev);
5668 break;
5669 case RT3572:
5670 rt2800_init_bbp_3572(rt2x00dev);
5671 break;
b189a181
GJ		 5672 case RT3593:
5673 rt2800_init_bbp_3593(rt2x00dev);
5674 return;
39ab3e8b
SG		 5675 case RT5390:
5676 case RT5392:
5677 rt2800_init_bbp_53xx(rt2x00dev);
5678 break;
5679 case RT5592:
a7bbbe5c 5680 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 5681 return;
a7bbbe5c
SG		 5682 }
5683
fcf51541 5684 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 5685 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5686 &eeprom);
fcf51541
BZ		 5687
5688 if (eeprom != 0xffff && eeprom != 0x0000) {
5689 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5690 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5691 rt2800_bbp_write(rt2x00dev, reg_id, value);
5692 }
5693 }
fcf51541 5694}
fcf51541 5695
d9517f2f
SG		 5696static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5697{
5698 u32 reg;
5699
5700 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5701 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5702 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5703}
5704
c5b3c350
SG		 5705static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5706 u8 filter_target)
fcf51541
BZ		 5707{
5708 unsigned int i;
5709 u8 bbp;
5710 u8 rfcsr;
5711 u8 passband;
5712 u8 stopband;
5713 u8 overtuned = 0;
c5b3c350 5714 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 5715
5716 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5717
5718 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5719 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5720 rt2800_bbp_write(rt2x00dev, 4, bbp);
5721
80d184e6
RJH		 5722 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5723 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5724 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5725
fcf51541
BZ		 5726 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5727 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5728 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5729
5730 /*
5731 * Set power & frequency of passband test tone
5732 */
5733 rt2800_bbp_write(rt2x00dev, 24, 0);
5734
5735 for (i = 0; i < 100; i++) {
5736 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5737 msleep(1);
5738
5739 rt2800_bbp_read(rt2x00dev, 55, &passband);
5740 if (passband)
5741 break;
5742 }
5743
5744 /*
5745 * Set power & frequency of stopband test tone
5746 */
5747 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5748
5749 for (i = 0; i < 100; i++) {
5750 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5751 msleep(1);
5752
5753 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5754
5755 if ((passband - stopband) <= filter_target) {
5756 rfcsr24++;
5757 overtuned += ((passband - stopband) == filter_target);
5758 } else
5759 break;
5760
5761 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5762 }
5763
5764 rfcsr24 -= !!overtuned;
5765
5766 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5767 return rfcsr24;
5768}
5769
ce94ede9
SG		 5770static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5771 const unsigned int rf_reg)
5772{
5773 u8 rfcsr;
5774
5775 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5776 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5777 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5778 msleep(1);
5779 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5780 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5781}
5782
c5b3c350
SG		 5783static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5784{
5785 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5786 u8 filter_tgt_bw20;
5787 u8 filter_tgt_bw40;
5788 u8 rfcsr, bbp;
5789
5790 /*
5791 * TODO: sync filter_tgt values with vendor driver
5792 */
5793 if (rt2x00_rt(rt2x00dev, RT3070)) {
5794 filter_tgt_bw20 = 0x16;
5795 filter_tgt_bw40 = 0x19;
5796 } else {
5797 filter_tgt_bw20 = 0x13;
5798 filter_tgt_bw40 = 0x15;
5799 }
5800
5801 drv_data->calibration_bw20 =
5802 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5803 drv_data->calibration_bw40 =
5804 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5805
5806 /*
5807 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5808 */
5809 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5810 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5811
5812 /*
5813 * Set back to initial state
5814 */
5815 rt2800_bbp_write(rt2x00dev, 24, 0);
5816
5817 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5818 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5819 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5820
5821 /*
5822 * Set BBP back to BW20
5823 */
5824 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5825 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5826 rt2800_bbp_write(rt2x00dev, 4, bbp);
5827}
5828
da8064c2
SG		 5829static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5830{
5831 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5832 u8 min_gain, rfcsr, bbp;
5833 u16 eeprom;
5834
5835 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5836
5837 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5838 if (rt2x00_rt(rt2x00dev, RT3070) ||
5839 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5840 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5841 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
c429dfef 5842 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
da8064c2
SG		 5843 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5844 }
5845
5846 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5847 if (drv_data->txmixer_gain_24g >= min_gain) {
5848 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5849 drv_data->txmixer_gain_24g);
5850 }
5851
5852 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5853
5854 if (rt2x00_rt(rt2x00dev, RT3090)) {
5855 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5856 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 5857 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 5858 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5859 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5860 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5861 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5862 rt2800_bbp_write(rt2x00dev, 138, bbp);
5863 }
5864
5865 if (rt2x00_rt(rt2x00dev, RT3070)) {
5866 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5867 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5868 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5869 else
5870 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5871 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5872 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5873 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5874 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5875 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5876 rt2x00_rt(rt2x00dev, RT3090) ||
5877 rt2x00_rt(rt2x00dev, RT3390)) {
5878 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5879 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5880 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5881 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5882 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5883 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5884 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5885
5886 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5887 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5888 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5889
5890 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5891 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5892 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5893
5894 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5895 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5896 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5897 }
5898}
5899
ab7078ac
GJ		 5900static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5901{
5902 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5903 u8 rfcsr;
5904 u8 tx_gain;
5905
5906 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5907 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5908 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5909
5910 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5911 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5912 RFCSR17_TXMIXER_GAIN);
5913 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5914 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5915
5916 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5917 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5918 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5919
5920 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5921 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5922 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5923
5924 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5925 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5926 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5927 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5928
5929 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5930 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5931 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5932
5933 /* TODO: enable stream mode */
5934}
5935
f7df8fe5
SG		 5936static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5937{
5938 u8 reg;
5939 u16 eeprom;
5940
5941 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5942 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 5943 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 5944 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5945 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5946 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5947 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5948 rt2800_bbp_write(rt2x00dev, 138, reg);
5949
5950 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5951 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5952 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5953
5954 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5955 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5956 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5957
5958 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5959
5960 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5961 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5962 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5963}
5964
d5374ef1
SG		 5965static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5966{
ce94ede9
SG		 5967 rt2800_rf_init_calibration(rt2x00dev, 30);
5968
d5374ef1
SG		 5969 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5970 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5971 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5972 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5973 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5974 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5975 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5976 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5977 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5978 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5979 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5980 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5981 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5982 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5983 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5984 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5985 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5986 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5987 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5988 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5989 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5990 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5991 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5992 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5993 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5994 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5995 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5996 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5997 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5998 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5999 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6000 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6001}
6002
6003static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6004{
c9a221b2
SG		 6005 u8 rfcsr;
6006 u16 eeprom;
6007 u32 reg;
6008
ce94ede9
SG		 6009 /* XXX vendor driver do this only for 3070 */
6010 rt2800_rf_init_calibration(rt2x00dev, 30);
6011
d5374ef1
SG		 6012 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6013 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6014 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6015 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6016 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6017 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6018 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6019 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6020 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6021 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6022 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6023 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6024 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6025 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6026 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6027 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6028 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
772eb433 6029 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
d5374ef1 6030 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 6031
6032 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6033 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6034 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6035 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6036 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6037 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6038 rt2x00_rt(rt2x00dev, RT3090)) {
6039 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6040
6041 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6042 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6043 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6044
6045 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6046 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6047 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6048 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6049 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6050 &eeprom);
c9a221b2
SG		 6051 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6052 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6053 else
6054 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6055 }
6056 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6057
6058 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6059 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6060 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6061 }
c5b3c350
SG		 6062
6063 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6064
6065 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6066 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6067 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6068 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6069
6070 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6071 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6072}
6073
6074static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6075{
f9cdcbb1
SG		 6076 u8 rfcsr;
6077
ce94ede9
SG		 6078 rt2800_rf_init_calibration(rt2x00dev, 2);
6079
d5374ef1
SG		 6080 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6081 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6082 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6083 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6084 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6085 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6086 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6087 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6088 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6089 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6090 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6091 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6092 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6093 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6094 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6095 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6096 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6097 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6098 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6099 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6100 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6101 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6102 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6103 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6104 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6105 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6106 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6107 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6108 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6109 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6110 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6111 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6112 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6113 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6114 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6115 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6116 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6117 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6118 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6119 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6120 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6121 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6122 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6123 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6124 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6125 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 6126
6127 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6128 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6129 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 6130
6131 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6132 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6133}
6134
6135static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6136{
ce94ede9
SG		 6137 rt2800_rf_init_calibration(rt2x00dev, 30);
6138
d5374ef1
SG		 6139 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6140 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6141 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6142 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6143 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6144 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6145 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6146 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6147 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6148 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6149 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6150 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6151 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6152 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6153 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6154 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6155 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6156 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6157 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6158 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6159 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6160 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6161 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6162 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6163 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6164 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6165 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6166 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6167 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6168 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6169 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6170 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6171 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6172 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6173 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6174 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6175 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6176 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6177 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6178 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6179 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6180 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6181 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6182 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6183 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6184 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6185 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6186 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6187 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6188 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6189 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6190 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6191 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6192 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6193 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6194 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6195 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6196 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6197 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6198 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6199 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6200 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6201 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 6202
6203 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6204 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6205 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6206}
6207
6208static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6209{
2971e66f
SG		 6210 u32 reg;
6211
ce94ede9
SG		 6212 rt2800_rf_init_calibration(rt2x00dev, 30);
6213
d5374ef1
SG		 6214 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6215 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6216 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6217 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6218 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6219 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6220 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6221 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6222 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6223 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6224 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6225 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6226 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6227 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6228 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6229 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6230 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6231 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6232 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6233 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6234 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6235 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6236 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6237 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6238 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6239 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6240 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6241 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6242 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6243 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6244 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6245 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 6246
6247 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6248 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6249 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 6250
6251 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6252
6253 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6254 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6255
6256 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6257 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6258}
6259
6260static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6261{
87d91db9
SG		 6262 u8 rfcsr;
6263 u32 reg;
6264
ce94ede9
SG		 6265 rt2800_rf_init_calibration(rt2x00dev, 30);
6266
d5374ef1
SG		 6267 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6268 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6269 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6270 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6271 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6272 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6273 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6274 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6275 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6276 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6277 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6278 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6279 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6280 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6281 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6282 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6283 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6284 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6285 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6286 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6287 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6288 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6289 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6290 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6291 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6292 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6293 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6294 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6295 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6296 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6297 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 6298
6299 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6300 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6301 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6302
6303 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6304 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6305 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6306 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6307 msleep(1);
6308 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6309 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6310 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6311 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 6312
6313 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6314 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6315 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6316}
6317
d63f7e8c
GJ		 6318static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6319{
6320 u8 bbp;
6321 bool txbf_enabled = false; /* FIXME */
6322
6323 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6324 if (rt2x00dev->default_ant.rx_chain_num == 1)
6325 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6326 else
6327 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6328 rt2800_bbp_write(rt2x00dev, 105, bbp);
6329
6330 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6331
6332 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6333 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6334 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6335 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6336 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6337 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6338 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6339 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6340
6341 if (txbf_enabled)
6342 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6343 else
6344 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6345
6346 /* SNR mapping */
6347 rt2800_bbp_write(rt2x00dev, 142, 6);
6348 rt2800_bbp_write(rt2x00dev, 143, 160);
6349 rt2800_bbp_write(rt2x00dev, 142, 7);
6350 rt2800_bbp_write(rt2x00dev, 143, 161);
6351 rt2800_bbp_write(rt2x00dev, 142, 8);
6352 rt2800_bbp_write(rt2x00dev, 143, 162);
6353
6354 /* ADC/DAC control */
6355 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6356
6357 /* RX AGC energy lower bound in log2 */
6358 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6359
6360 /* FIXME: BBP 105 owerwrite? */
6361 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 6362
d63f7e8c
GJ		 6363}
6364
ab7078ac
GJ		 6365static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6366{
6367 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6368 u32 reg;
6369 u8 rfcsr;
6370
6371 /* Disable GPIO #4 and #7 function for LAN PE control */
6372 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6373 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6374 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6375 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6376
6377 /* Initialize default register values */
6378 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6379 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6380 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6381 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6382 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6383 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6384 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6385 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6386 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6387 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6388 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6389 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6390 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6391 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6392 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6393 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6394 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6395 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6396 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6397 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6398 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6399 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6400 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6401 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6402 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6403 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6404 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6405 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6406 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6407 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6408 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6409 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6410
6411 /* Initiate calibration */
6412 /* TODO: use rt2800_rf_init_calibration ? */
6413 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6414 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6415 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6416
6417 rt2800_adjust_freq_offset(rt2x00dev);
6418
6419 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6420 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6421 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6422
6423 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6424 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6425 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6426 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6427 usleep_range(1000, 1500);
6428 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6429 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6430 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6431
6432 /* Set initial values for RX filter calibration */
6433 drv_data->calibration_bw20 = 0x1f;
6434 drv_data->calibration_bw40 = 0x2f;
6435
6436 /* Save BBP 25 & 26 values for later use in channel switching */
6437 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6438 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6439
6440 rt2800_led_open_drain_enable(rt2x00dev);
6441 rt2800_normal_mode_setup_3593(rt2x00dev);
6442
d63f7e8c 6443 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 6444
6445 /* TODO: enable stream mode support */
6446}
6447
d5374ef1
SG		 6448static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6449{
ce94ede9
SG		 6450 rt2800_rf_init_calibration(rt2x00dev, 2);
6451
d5374ef1
SG		 6452 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6453 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6454 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6455 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6456 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6457 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6458 else
6459 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6460 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6461 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6462 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
c8520bcb 6463 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
d5374ef1
SG		 6464 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6465 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6466 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6467 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6468 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6469 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6470
6471 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6472 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6473 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6474 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6475 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
c8520bcb
KL		 6476 if (rt2x00_is_usb(rt2x00dev) &&
6477 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
d5374ef1
SG		 6478 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6479 else
6480 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6481 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6482 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6483 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6484 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6485
7122e660 6486 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
d5374ef1
SG		 6487 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6488 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6489 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6490 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6491 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6492 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6493 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6494 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6495 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6496
c8520bcb 6497 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
d5374ef1
SG		 6498 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6499 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6500 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6501 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6502 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6503 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6504 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6505 else
6506 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6507 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6508 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6509 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6510
6511 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6512 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6513 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6514 else
6515 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6516 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6517 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
c8520bcb
KL		 6518 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6519 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6520 else
6521 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
d5374ef1
SG		 6522 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6523 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7122e660 6524 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
d5374ef1
SG		 6525
6526 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
c8520bcb
KL		 6527 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6528 if (rt2x00_is_usb(rt2x00dev))
6529 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6530 else
6531 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6532 } else {
6533 if (rt2x00_is_usb(rt2x00dev))
6534 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6535 else
6536 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6537 }
d5374ef1
SG		 6538 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6539 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 6540
6541 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6542
6543 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6544}
6545
6546static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6547{
ce94ede9
SG		 6548 rt2800_rf_init_calibration(rt2x00dev, 2);
6549
d5374ef1 6550 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
d5374ef1
SG		 6551 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6552 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6553 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6554 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6555 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6556 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6557 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6558 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6559 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6560 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6561 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6562 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6563 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6564 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6565 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6566 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6567 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6568 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6569 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6570 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6571 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6572 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6573 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6574 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6575 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6576 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6577 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6578 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6579 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6580 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6581 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6582 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6583 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6584 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6585 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6586 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6587 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6588 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6589 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6590 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6591 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6592 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6593 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6594 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6595 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6596 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6597 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6598 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6599 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6600 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6601 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6602 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6603 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6604 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6605 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6606 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6607 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 6608
6609 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6610
6611 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6612}
6613
0c9e5fb9
SG		 6614static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6615{
ce94ede9
SG		 6616 rt2800_rf_init_calibration(rt2x00dev, 30);
6617
0c9e5fb9
SG		 6618 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6619 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
0c9e5fb9
SG		 6620 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6621 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6622 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6623 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6624 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6625 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6626 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6627 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6628 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6629 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6630 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6631 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6632 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6633 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6634 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6635 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6636 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6637 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6638 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6639
6640 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6641 msleep(1);
6642
6643 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 6644
c630ccf1
SG		 6645 /* Enable DC filter */
6646 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6647 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6648
f7df8fe5 6649 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 6650
6651 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6652 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6653
6654 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 6655}
6656
074f2529 6657static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 6658{
d5374ef1
SG		 6659 if (rt2800_is_305x_soc(rt2x00dev)) {
6660 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 6661 return;
d5374ef1
SG		 6662 }
6663
6664 switch (rt2x00dev->chip.rt) {
6665 case RT3070:
6666 case RT3071:
6667 case RT3090:
6668 rt2800_init_rfcsr_30xx(rt2x00dev);
6669 break;
6670 case RT3290:
6671 rt2800_init_rfcsr_3290(rt2x00dev);
6672 break;
6673 case RT3352:
6674 rt2800_init_rfcsr_3352(rt2x00dev);
6675 break;
6676 case RT3390:
6677 rt2800_init_rfcsr_3390(rt2x00dev);
6678 break;
6679 case RT3572:
6680 rt2800_init_rfcsr_3572(rt2x00dev);
6681 break;
ab7078ac
GJ		 6682 case RT3593:
6683 rt2800_init_rfcsr_3593(rt2x00dev);
6684 break;
d5374ef1
SG		 6685 case RT5390:
6686 rt2800_init_rfcsr_5390(rt2x00dev);
6687 break;
6688 case RT5392:
6689 rt2800_init_rfcsr_5392(rt2x00dev);
6690 break;
0c9e5fb9
SG		 6691 case RT5592:
6692 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 6693 break;
8cdd15e0 6694 }
fcf51541 6695}
b9a07ae9
ID		 6696
6697int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6698{
6699 u32 reg;
6700 u16 word;
6701
6702 /*
61edc7fa 6703 * Initialize MAC registers.
b9a07ae9
ID		 6704 */
6705 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 6706 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 6707 return -EIO;
6708
61edc7fa
SG		 6709 /*
6710 * Wait BBP/RF to wake up.
6711 */
f4e1a4d3
SG		 6712 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6713 return -EIO;
6714
b9a07ae9 6715 /*
61edc7fa 6716 * Send signal during boot time to initialize firmware.
b9a07ae9 6717 */
c630ccf1
SG		 6718 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6719 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
f4e1a4d3 6720 if (rt2x00_is_usb(rt2x00dev))
c630ccf1 6721 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f4e1a4d3 6722 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
c630ccf1
SG		 6723 msleep(1);
6724
61edc7fa
SG		 6725 /*
6726 * Make sure BBP is up and running.
6727 */
f4e1a4d3 6728 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 6729 return -EIO;
b9a07ae9 6730
61edc7fa
SG		 6731 /*
6732 * Initialize BBP/RF registers.
6733 */
a1ef5039 6734 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 6735 rt2800_init_rfcsr(rt2x00dev);
6736
b9a07ae9
ID		 6737 if (rt2x00_is_usb(rt2x00dev) &&
6738 (rt2x00_rt(rt2x00dev, RT3070) ||
6739 rt2x00_rt(rt2x00dev, RT3071) ||
6740 rt2x00_rt(rt2x00dev, RT3572))) {
6741 udelay(200);
6742 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6743 udelay(10);
6744 }
6745
6746 /*
6747 * Enable RX.
6748 */
6749 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6750 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6751 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6752 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6753
6754 udelay(50);
6755
6756 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6757 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6758 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6759 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6760 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6761 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6762
6763 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6764 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6765 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6766 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6767
6768 /*
6769 * Initialize LED control
6770 */
3e38d3da 6771 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 6772 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 6773 word & 0xff, (word >> 8) & 0xff);
6774
3e38d3da 6775 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 6776 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 6777 word & 0xff, (word >> 8) & 0xff);
6778
3e38d3da 6779 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 6780 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 6781 word & 0xff, (word >> 8) & 0xff);
6782
6783 return 0;
6784}
6785EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6786
6787void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6788{
6789 u32 reg;
6790
f7b395e9 6791 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 6792
6793 /* Wait for DMA, ignore error */
6794 rt2800_wait_wpdma_ready(rt2x00dev);
6795
6796 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6797 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6798 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6799 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 6800}
6801EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 6802
30e84034
BZ		 6803int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6804{
6805 u32 reg;
a89534ed 6806 u16 efuse_ctrl_reg;
30e84034 6807
a89534ed
WH		 6808 if (rt2x00_rt(rt2x00dev, RT3290))
6809 efuse_ctrl_reg = EFUSE_CTRL_3290;
6810 else
6811 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 6812
a89534ed 6813 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6814 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6815}
6816EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6817
6818static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6819{
6820 u32 reg;
a89534ed
WH		 6821 u16 efuse_ctrl_reg;
6822 u16 efuse_data0_reg;
6823 u16 efuse_data1_reg;
6824 u16 efuse_data2_reg;
6825 u16 efuse_data3_reg;
6826
6827 if (rt2x00_rt(rt2x00dev, RT3290)) {
6828 efuse_ctrl_reg = EFUSE_CTRL_3290;
6829 efuse_data0_reg = EFUSE_DATA0_3290;
6830 efuse_data1_reg = EFUSE_DATA1_3290;
6831 efuse_data2_reg = EFUSE_DATA2_3290;
6832 efuse_data3_reg = EFUSE_DATA3_3290;
6833 } else {
6834 efuse_ctrl_reg = EFUSE_CTRL;
6835 efuse_data0_reg = EFUSE_DATA0;
6836 efuse_data1_reg = EFUSE_DATA1;
6837 efuse_data2_reg = EFUSE_DATA2;
6838 efuse_data3_reg = EFUSE_DATA3;
6839 }
31a4cf1f
GW		 6840 mutex_lock(&rt2x00dev->csr_mutex);
6841
a89534ed 6842 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6843 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6844 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6845 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 6846 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 6847
6848 /* Wait until the EEPROM has been loaded */
a89534ed 6849 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 6850 /* Apparently the data is read from end to start */
a89534ed 6851 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 6852 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 6853 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 6854 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 6855 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 6856 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 6857 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 6858 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 6859 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 6860
6861 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 6862}
6863
a02308e9 6864int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 6865{
6866 unsigned int i;
6867
6868 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6869 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 6870
6871 return 0;
30e84034
BZ		 6872}
6873EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6874
a3f1625d
GJ		 6875static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6876{
6877 u16 word;
6878
6316c786
GJ		 6879 if (rt2x00_rt(rt2x00dev, RT3593))
6880 return 0;
6881
a3f1625d
GJ		 6882 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6883 if ((word & 0x00ff) != 0x00ff)
6884 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6885
6886 return 0;
6887}
6888
6889static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6890{
6891 u16 word;
6892
6316c786
GJ		 6893 if (rt2x00_rt(rt2x00dev, RT3593))
6894 return 0;
6895
a3f1625d
GJ		 6896 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6897 if ((word & 0x00ff) != 0x00ff)
6898 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6899
6900 return 0;
6901}
6902
ad417a53 6903static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6904{
77c06c2c 6905 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 6906 u16 word;
6907 u8 *mac;
6908 u8 default_lna_gain;
a02308e9 6909 int retval;
38bd7b8a 6910
ad417a53
GW		 6911 /*
6912 * Read the EEPROM.
6913 */
a02308e9
GJ		 6914 retval = rt2800_read_eeprom(rt2x00dev);
6915 if (retval)
6916 return retval;
ad417a53 6917
38bd7b8a
BZ		 6918 /*
6919 * Start validation of the data that has been read.
6920 */
3e38d3da 6921 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
38bd7b8a 6922 if (!is_valid_ether_addr(mac)) {
f4f7f414 6923 eth_random_addr(mac);
ec9c4989 6924 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 6925 }
6926
3e38d3da 6927 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 6928 if (word == 0xffff) {
38c8a566
RJH		 6929 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6930 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6931 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 6932 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 6933 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 6934 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 6935 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 6936 /*
6937 * There is a max of 2 RX streams for RT28x0 series
6938 */
38c8a566
RJH		 6939 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6940 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 6941 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 6942 }
6943
3e38d3da 6944 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 6945 if (word == 0xffff) {
38c8a566
RJH		 6946 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6947 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6948 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6949 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6950 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6951 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6952 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6953 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6954 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6955 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6956 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6957 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6958 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6959 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6960 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 6961 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 6962 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 6963 }
6964
3e38d3da 6965 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 6966 if ((word & 0x00ff) == 0x00ff) {
6967 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 6968 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 6969 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 6970 }
6971 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 6972 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6973 LED_MODE_TXRX_ACTIVITY);
6974 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 6975 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6976 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6977 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6978 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 6979 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 6980 }
6981
6982 /*
6983 * During the LNA validation we are going to use
6984 * lna0 as correct value. Note that EEPROM_LNA
6985 * is never validated.
6986 */
3e38d3da 6987 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 6988 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6989
3e38d3da 6990 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 6991 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6992 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6993 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6994 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 6995 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 6996
a3f1625d 6997 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 6998
3e38d3da 6999 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 7000 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
7001 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 7002 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7003 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
7004 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
7005 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
7006 default_lna_gain);
7007 }
3e38d3da 7008 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 7009
a3f1625d 7010 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 7011
3e38d3da 7012 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 7013 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7014 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7015 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7016 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 7017 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 7018
3e38d3da 7019 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 7020 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7021 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 7022 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7023 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7024 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7025 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7026 default_lna_gain);
7027 }
3e38d3da 7028 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 7029
f36bb0ca
GJ		 7030 if (rt2x00_rt(rt2x00dev, RT3593)) {
7031 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7032 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7033 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7034 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7035 default_lna_gain);
7036 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7037 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7038 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7039 default_lna_gain);
7040 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7041 }
7042
38bd7b8a
BZ		 7043 return 0;
7044}
38bd7b8a 7045
ad417a53 7046static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 7047{
38bd7b8a
BZ		 7048 u16 value;
7049 u16 eeprom;
86868b26 7050 u16 rf;
38bd7b8a 7051
86868b26
GJ		 7052 /*
7053 * Read EEPROM word for configuration.
7054 */
3e38d3da 7055 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 7056
7057 /*
7058 * Identify RF chipset by EEPROM value
7059 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7060 * RT53xx: defined in "EEPROM_CHIP_ID" field
7061 */
7062 if (rt2x00_rt(rt2x00dev, RT3290) ||
7063 rt2x00_rt(rt2x00dev, RT5390) ||
7064 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 7065 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 7066 else
7067 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7068
7069 switch (rf) {
d331eb51
LF		 7070 case RF2820:
7071 case RF2850:
7072 case RF2720:
7073 case RF2750:
7074 case RF3020:
7075 case RF2020:
7076 case RF3021:
7077 case RF3022:
7078 case RF3052:
0f5af26a 7079 case RF3053:
3b9b74ba 7080 case RF3070:
a89534ed 7081 case RF3290:
d331eb51 7082 case RF3320:
03839951 7083 case RF3322:
ccf91bd6 7084 case RF5360:
ac0372ab 7085 case RF5362:
d331eb51 7086 case RF5370:
2ed71884 7087 case RF5372:
d331eb51 7088 case RF5390:
cff3d1f0 7089 case RF5392:
b8863f8b 7090 case RF5592:
d331eb51
LF		 7091 break;
7092 default:
ec9c4989
JP		 7093 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7094 rf);
38bd7b8a
BZ		 7095 return -ENODEV;
7096 }
7097
86868b26
GJ		 7098 rt2x00_set_rf(rt2x00dev, rf);
7099
38bd7b8a
BZ		 7100 /*
7101 * Identify default antenna configuration.
7102 */
d96aa640 7103 rt2x00dev->default_ant.tx_chain_num =
38c8a566 7104 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 7105 rt2x00dev->default_ant.rx_chain_num =
38c8a566 7106 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 7107
3e38d3da 7108 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 7109
7110 if (rt2x00_rt(rt2x00dev, RT3070) ||
7111 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 7112 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 7113 rt2x00_rt(rt2x00dev, RT3390)) {
7114 value = rt2x00_get_field16(eeprom,
7115 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7116 switch (value) {
7117 case 0:
7118 case 1:
7119 case 2:
7120 rt2x00dev->default_ant.tx = ANTENNA_A;
7121 rt2x00dev->default_ant.rx = ANTENNA_A;
7122 break;
7123 case 3:
7124 rt2x00dev->default_ant.tx = ANTENNA_A;
7125 rt2x00dev->default_ant.rx = ANTENNA_B;
7126 break;
7127 }
7128 } else {
7129 rt2x00dev->default_ant.tx = ANTENNA_A;
7130 rt2x00dev->default_ant.rx = ANTENNA_A;
7131 }
7132
0586a11b
AA		 7133 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7134 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7135 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7136 }
7137
38bd7b8a 7138 /*
9328fdac 7139 * Determine external LNA informations.
38bd7b8a 7140 */
38c8a566 7141 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 7142 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 7143 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 7144 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 7145
7146 /*
7147 * Detect if this device has an hardware controlled radio.
7148 */
38c8a566 7149 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 7150 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 7151
fdbc7b0a
GW		 7152 /*
7153 * Detect if this device has Bluetooth co-existence.
7154 */
7155 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7156 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7157
9328fdac
GW		 7158 /*
7159 * Read frequency offset and RF programming sequence.
7160 */
3e38d3da 7161 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 7162 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7163
38bd7b8a
BZ		 7164 /*
7165 * Store led settings, for correct led behaviour.
7166 */
7167#ifdef CONFIG_RT2X00_LIB_LEDS
7168 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7169 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7170 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7171
9328fdac 7172 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 7173#endif /* CONFIG_RT2X00_LIB_LEDS */
7174
e90c54b2
RJH		 7175 /*
7176 * Check if support EIRP tx power limit feature.
7177 */
3e38d3da 7178 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 7179
7180 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7181 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 7182 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 7183
38bd7b8a
BZ		 7184 return 0;
7185}
38bd7b8a 7186
4da2933f 7187/*
55f9321a 7188 * RF value list for rt28xx
4da2933f
BZ		 7189 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7190 */
7191static const struct rf_channel rf_vals[] = {
7192 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7193 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7194 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7195 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7196 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7197 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7198 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7199 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7200 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7201 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7202 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7203 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7204 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7205 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7206
7207 /* 802.11 UNI / HyperLan 2 */
7208 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7209 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7210 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7211 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7212 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7213 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7214 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7215 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7216 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7217 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7218 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7219 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7220
7221 /* 802.11 HyperLan 2 */
7222 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7223 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7224 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7225 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7226 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7227 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7228 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7229 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7230 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7231 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7232 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7233 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7234 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7235 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7236 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7237 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7238
7239 /* 802.11 UNII */
7240 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7241 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7242 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7243 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7244 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7245 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7246 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7247 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7248 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7249 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7250 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7251
7252 /* 802.11 Japan */
7253 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7254 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7255 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7256 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7257 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7258 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7259 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7260};
7261
7262/*
55f9321a 7263 * RF value list for rt3xxx
b6b561c3 7264 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
4da2933f 7265 */
55f9321a 7266static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 7267 {1, 241, 2, 2 },
7268 {2, 241, 2, 7 },
7269 {3, 242, 2, 2 },
7270 {4, 242, 2, 7 },
7271 {5, 243, 2, 2 },
7272 {6, 243, 2, 7 },
7273 {7, 244, 2, 2 },
7274 {8, 244, 2, 7 },
7275 {9, 245, 2, 2 },
7276 {10, 245, 2, 7 },
7277 {11, 246, 2, 2 },
7278 {12, 246, 2, 7 },
7279 {13, 247, 2, 2 },
7280 {14, 248, 2, 4 },
55f9321a
ID		 7281
7282 /* 802.11 UNI / HyperLan 2 */
7283 {36, 0x56, 0, 4},
7284 {38, 0x56, 0, 6},
7285 {40, 0x56, 0, 8},
7286 {44, 0x57, 0, 0},
7287 {46, 0x57, 0, 2},
7288 {48, 0x57, 0, 4},
7289 {52, 0x57, 0, 8},
7290 {54, 0x57, 0, 10},
7291 {56, 0x58, 0, 0},
7292 {60, 0x58, 0, 4},
7293 {62, 0x58, 0, 6},
7294 {64, 0x58, 0, 8},
7295
7296 /* 802.11 HyperLan 2 */
7297 {100, 0x5b, 0, 8},
7298 {102, 0x5b, 0, 10},
7299 {104, 0x5c, 0, 0},
7300 {108, 0x5c, 0, 4},
7301 {110, 0x5c, 0, 6},
7302 {112, 0x5c, 0, 8},
7303 {116, 0x5d, 0, 0},
7304 {118, 0x5d, 0, 2},
7305 {120, 0x5d, 0, 4},
7306 {124, 0x5d, 0, 8},
7307 {126, 0x5d, 0, 10},
7308 {128, 0x5e, 0, 0},
7309 {132, 0x5e, 0, 4},
7310 {134, 0x5e, 0, 6},
7311 {136, 0x5e, 0, 8},
7312 {140, 0x5f, 0, 0},
7313
7314 /* 802.11 UNII */
7315 {149, 0x5f, 0, 9},
7316 {151, 0x5f, 0, 11},
7317 {153, 0x60, 0, 1},
7318 {157, 0x60, 0, 5},
7319 {159, 0x60, 0, 7},
7320 {161, 0x60, 0, 9},
7321 {165, 0x61, 0, 1},
7322 {167, 0x61, 0, 3},
7323 {169, 0x61, 0, 5},
7324 {171, 0x61, 0, 7},
7325 {173, 0x61, 0, 9},
4da2933f
BZ		 7326};
7327
7848b231
SG		 7328static const struct rf_channel rf_vals_5592_xtal20[] = {
7329 /* Channel, N, K, mod, R */
7330 {1, 482, 4, 10, 3},
7331 {2, 483, 4, 10, 3},
7332 {3, 484, 4, 10, 3},
7333 {4, 485, 4, 10, 3},
7334 {5, 486, 4, 10, 3},
7335 {6, 487, 4, 10, 3},
7336 {7, 488, 4, 10, 3},
7337 {8, 489, 4, 10, 3},
7338 {9, 490, 4, 10, 3},
7339 {10, 491, 4, 10, 3},
7340 {11, 492, 4, 10, 3},
7341 {12, 493, 4, 10, 3},
7342 {13, 494, 4, 10, 3},
7343 {14, 496, 8, 10, 3},
7344 {36, 172, 8, 12, 1},
7345 {38, 173, 0, 12, 1},
7346 {40, 173, 4, 12, 1},
7347 {42, 173, 8, 12, 1},
7348 {44, 174, 0, 12, 1},
7349 {46, 174, 4, 12, 1},
7350 {48, 174, 8, 12, 1},
7351 {50, 175, 0, 12, 1},
7352 {52, 175, 4, 12, 1},
7353 {54, 175, 8, 12, 1},
7354 {56, 176, 0, 12, 1},
7355 {58, 176, 4, 12, 1},
7356 {60, 176, 8, 12, 1},
7357 {62, 177, 0, 12, 1},
7358 {64, 177, 4, 12, 1},
7359 {100, 183, 4, 12, 1},
7360 {102, 183, 8, 12, 1},
7361 {104, 184, 0, 12, 1},
7362 {106, 184, 4, 12, 1},
7363 {108, 184, 8, 12, 1},
7364 {110, 185, 0, 12, 1},
7365 {112, 185, 4, 12, 1},
7366 {114, 185, 8, 12, 1},
7367 {116, 186, 0, 12, 1},
7368 {118, 186, 4, 12, 1},
7369 {120, 186, 8, 12, 1},
7370 {122, 187, 0, 12, 1},
7371 {124, 187, 4, 12, 1},
7372 {126, 187, 8, 12, 1},
7373 {128, 188, 0, 12, 1},
7374 {130, 188, 4, 12, 1},
7375 {132, 188, 8, 12, 1},
7376 {134, 189, 0, 12, 1},
7377 {136, 189, 4, 12, 1},
7378 {138, 189, 8, 12, 1},
7379 {140, 190, 0, 12, 1},
7380 {149, 191, 6, 12, 1},
7381 {151, 191, 10, 12, 1},
7382 {153, 192, 2, 12, 1},
7383 {155, 192, 6, 12, 1},
7384 {157, 192, 10, 12, 1},
7385 {159, 193, 2, 12, 1},
7386 {161, 193, 6, 12, 1},
7387 {165, 194, 2, 12, 1},
7388 {184, 164, 0, 12, 1},
7389 {188, 164, 4, 12, 1},
7390 {192, 165, 8, 12, 1},
7391 {196, 166, 0, 12, 1},
7392};
7393
7394static const struct rf_channel rf_vals_5592_xtal40[] = {
7395 /* Channel, N, K, mod, R */
7396 {1, 241, 2, 10, 3},
7397 {2, 241, 7, 10, 3},
7398 {3, 242, 2, 10, 3},
7399 {4, 242, 7, 10, 3},
7400 {5, 243, 2, 10, 3},
7401 {6, 243, 7, 10, 3},
7402 {7, 244, 2, 10, 3},
7403 {8, 244, 7, 10, 3},
7404 {9, 245, 2, 10, 3},
7405 {10, 245, 7, 10, 3},
7406 {11, 246, 2, 10, 3},
7407 {12, 246, 7, 10, 3},
7408 {13, 247, 2, 10, 3},
7409 {14, 248, 4, 10, 3},
7410 {36, 86, 4, 12, 1},
7411 {38, 86, 6, 12, 1},
7412 {40, 86, 8, 12, 1},
7413 {42, 86, 10, 12, 1},
7414 {44, 87, 0, 12, 1},
7415 {46, 87, 2, 12, 1},
7416 {48, 87, 4, 12, 1},
7417 {50, 87, 6, 12, 1},
7418 {52, 87, 8, 12, 1},
7419 {54, 87, 10, 12, 1},
7420 {56, 88, 0, 12, 1},
7421 {58, 88, 2, 12, 1},
7422 {60, 88, 4, 12, 1},
7423 {62, 88, 6, 12, 1},
7424 {64, 88, 8, 12, 1},
7425 {100, 91, 8, 12, 1},
7426 {102, 91, 10, 12, 1},
7427 {104, 92, 0, 12, 1},
7428 {106, 92, 2, 12, 1},
7429 {108, 92, 4, 12, 1},
7430 {110, 92, 6, 12, 1},
7431 {112, 92, 8, 12, 1},
7432 {114, 92, 10, 12, 1},
7433 {116, 93, 0, 12, 1},
7434 {118, 93, 2, 12, 1},
7435 {120, 93, 4, 12, 1},
7436 {122, 93, 6, 12, 1},
7437 {124, 93, 8, 12, 1},
7438 {126, 93, 10, 12, 1},
7439 {128, 94, 0, 12, 1},
7440 {130, 94, 2, 12, 1},
7441 {132, 94, 4, 12, 1},
7442 {134, 94, 6, 12, 1},
7443 {136, 94, 8, 12, 1},
7444 {138, 94, 10, 12, 1},
7445 {140, 95, 0, 12, 1},
7446 {149, 95, 9, 12, 1},
7447 {151, 95, 11, 12, 1},
7448 {153, 96, 1, 12, 1},
7449 {155, 96, 3, 12, 1},
7450 {157, 96, 5, 12, 1},
7451 {159, 96, 7, 12, 1},
7452 {161, 96, 9, 12, 1},
7453 {165, 97, 1, 12, 1},
7454 {184, 82, 0, 12, 1},
7455 {188, 82, 4, 12, 1},
7456 {192, 82, 8, 12, 1},
7457 {196, 83, 0, 12, 1},
7458};
7459
ad417a53 7460static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 7461{
4da2933f
BZ		 7462 struct hw_mode_spec *spec = &rt2x00dev->spec;
7463 struct channel_info *info;
8d1331b3
ID		 7464 char *default_power1;
7465 char *default_power2;
c0a14369 7466 char *default_power3;
4da2933f 7467 unsigned int i;
7848b231 7468 u32 reg;
4da2933f 7469
93b6bd26 7470 /*
58e33a21 7471 * Disable powersaving as default.
93b6bd26 7472 */
58e33a21 7473 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
93b6bd26 7474
4da2933f
BZ		 7475 /*
7476 * Initialize all hw fields.
7477 */
30686bf7
JB		 7478 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_HT_CCK_RATES);
7479 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
7480 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
7481 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
7482 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
7483 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9d4f09b8 7484
5a5b6ed6
HS		 7485 /*
7486 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7487 * unless we are capable of sending the buffered frames out after the
7488 * DTIM transmission using rt2x00lib_beacondone. This will send out
7489 * multicast and broadcast traffic immediately instead of buffering it
7490 * infinitly and thus dropping it after some time.
7491 */
7492 if (!rt2x00_is_usb(rt2x00dev))
30686bf7 7493 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
4da2933f 7494
4da2933f
BZ		 7495 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7496 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 7497 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 7498 EEPROM_MAC_ADDR_0));
7499
3f2bee24
HS		 7500 /*
7501 * As rt2800 has a global fallback table we cannot specify
7502 * more then one tx rate per frame but since the hw will
7503 * try several rates (based on the fallback table) we should
ba3b9e5e 7504 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 7505 * we are going to try. Otherwise mac80211 will truncate our
7506 * reported tx rates and the rc algortihm will end up with
7507 * incorrect data.
7508 */
ba3b9e5e
HS		 7509 rt2x00dev->hw->max_rates = 1;
7510 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 7511 rt2x00dev->hw->max_rate_tries = 1;
7512
4da2933f
BZ		 7513 /*
7514 * Initialize hw_mode information.
7515 */
4da2933f
BZ		 7516 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7517
4a32c36d
GJ		 7518 switch (rt2x00dev->chip.rf) {
7519 case RF2720:
7520 case RF2820:
4da2933f
BZ		 7521 spec->num_channels = 14;
7522 spec->channels = rf_vals;
4a32c36d
GJ		 7523 break;
7524
7525 case RF2750:
7526 case RF2850:
4da2933f
BZ		 7527 spec->num_channels = ARRAY_SIZE(rf_vals);
7528 spec->channels = rf_vals;
4a32c36d
GJ		 7529 break;
7530
7531 case RF2020:
7532 case RF3020:
7533 case RF3021:
7534 case RF3022:
7535 case RF3070:
7536 case RF3290:
7537 case RF3320:
7538 case RF3322:
7539 case RF5360:
ac0372ab 7540 case RF5362:
4a32c36d
GJ		 7541 case RF5370:
7542 case RF5372:
7543 case RF5390:
7544 case RF5392:
55f9321a
ID		 7545 spec->num_channels = 14;
7546 spec->channels = rf_vals_3x;
4a32c36d
GJ		 7547 break;
7548
7549 case RF3052:
7550 case RF3053:
55f9321a
ID		 7551 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7552 spec->channels = rf_vals_3x;
4a32c36d 7553 break;
7848b231 7554
4a32c36d 7555 case RF5592:
7848b231
SG		 7556 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7557 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7558 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7559 spec->channels = rf_vals_5592_xtal40;
7560 } else {
7561 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7562 spec->channels = rf_vals_5592_xtal20;
7563 }
4a32c36d 7564 break;
4da2933f
BZ		 7565 }
7566
53216d6a
SG		 7567 if (WARN_ON_ONCE(!spec->channels))
7568 return -ENODEV;
7569
53c5a099
GJ		 7570 spec->supported_bands = SUPPORT_BAND_2GHZ;
7571 if (spec->num_channels > 14)
7572 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7573
4da2933f
BZ		 7574 /*
7575 * Initialize HT information.
7576 */
5122d898 7577 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 7578 spec->ht.ht_supported = true;
7579 else
7580 spec->ht.ht_supported = false;
7581
4da2933f 7582 spec->ht.cap =
06443e46 7583 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 7584 IEEE80211_HT_CAP_GRN_FLD |
7585 IEEE80211_HT_CAP_SGI_20 |
aa674631 7586 IEEE80211_HT_CAP_SGI_40;
22cabaa6 7587
aa10350d 7588 if (rt2x00dev->default_ant.tx_chain_num >= 2)
22cabaa6
HS		 7589 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7590
aa10350d
GJ		 7591 spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num <<
7592 IEEE80211_HT_CAP_RX_STBC_SHIFT;
aa674631 7593
4da2933f
BZ		 7594 spec->ht.ampdu_factor = 3;
7595 spec->ht.ampdu_density = 4;
7596 spec->ht.mcs.tx_params =
7597 IEEE80211_HT_MCS_TX_DEFINED |
7598 IEEE80211_HT_MCS_TX_RX_DIFF |
aa10350d
GJ		 7599 ((rt2x00dev->default_ant.tx_chain_num - 1) <<
7600 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4da2933f 7601
aa10350d 7602 switch (rt2x00dev->default_ant.rx_chain_num) {
4da2933f
BZ		 7603 case 3:
7604 spec->ht.mcs.rx_mask[2] = 0xff;
7605 case 2:
7606 spec->ht.mcs.rx_mask[1] = 0xff;
7607 case 1:
7608 spec->ht.mcs.rx_mask[0] = 0xff;
7609 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7610 break;
7611 }
7612
7613 /*
7614 * Create channel information array
7615 */
baeb2ffa 7616 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 7617 if (!info)
7618 return -ENOMEM;
7619
7620 spec->channels_info = info;
7621
3e38d3da
GJ		 7622 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7623 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 7624
c0a14369
GJ		 7625 if (rt2x00dev->default_ant.tx_chain_num > 2)
7626 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7627 EEPROM_EXT_TXPOWER_BG3);
7628 else
7629 default_power3 = NULL;
7630
4da2933f 7631 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 7632 info[i].default_power1 = default_power1[i];
7633 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 7634 if (default_power3)
7635 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 7636 }
7637
7638 if (spec->num_channels > 14) {
3e38d3da
GJ		 7639 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7640 EEPROM_TXPOWER_A1);
7641 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7642 EEPROM_TXPOWER_A2);
4da2933f 7643
c0a14369
GJ		 7644 if (rt2x00dev->default_ant.tx_chain_num > 2)
7645 default_power3 =
7646 rt2800_eeprom_addr(rt2x00dev,
7647 EEPROM_EXT_TXPOWER_A3);
7648 else
7649 default_power3 = NULL;
7650
4da2933f 7651 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 7652 info[i].default_power1 = default_power1[i - 14];
7653 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 7654 if (default_power3)
7655 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 7656 }
7657 }
7658
2e9c43dd
JL		 7659 switch (rt2x00dev->chip.rf) {
7660 case RF2020:
7661 case RF3020:
7662 case RF3021:
7663 case RF3022:
7664 case RF3320:
7665 case RF3052:
1095df07 7666 case RF3053:
3b9b74ba 7667 case RF3070:
a89534ed 7668 case RF3290:
ccf91bd6 7669 case RF5360:
ac0372ab 7670 case RF5362:
2e9c43dd
JL		 7671 case RF5370:
7672 case RF5372:
7673 case RF5390:
cff3d1f0 7674 case RF5392:
2e9c43dd
JL		 7675 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7676 break;
7677 }
7678
4da2933f
BZ		 7679 return 0;
7680}
ad417a53 7681
cbafb601
GJ		 7682static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7683{
7684 u32 reg;
7685 u32 rt;
7686 u32 rev;
7687
7688 if (rt2x00_rt(rt2x00dev, RT3290))
7689 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7690 else
7691 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7692
7693 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7694 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7695
7696 switch (rt) {
7697 case RT2860:
7698 case RT2872:
7699 case RT2883:
7700 case RT3070:
7701 case RT3071:
7702 case RT3090:
7703 case RT3290:
7704 case RT3352:
7705 case RT3390:
7706 case RT3572:
2dc2bd2f 7707 case RT3593:
cbafb601
GJ		 7708 case RT5390:
7709 case RT5392:
7710 case RT5592:
7711 break;
7712 default:
ec9c4989
JP		 7713 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7714 rt, rev);
cbafb601
GJ		 7715 return -ENODEV;
7716 }
7717
7718 rt2x00_set_rt(rt2x00dev, rt, rev);
7719
7720 return 0;
7721}
7722
ad417a53
GW		 7723int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7724{
7725 int retval;
7726 u32 reg;
7727
cbafb601
GJ		 7728 retval = rt2800_probe_rt(rt2x00dev);
7729 if (retval)
7730 return retval;
7731
ad417a53
GW		 7732 /*
7733 * Allocate eeprom data.
7734 */
7735 retval = rt2800_validate_eeprom(rt2x00dev);
7736 if (retval)
7737 return retval;
7738
7739 retval = rt2800_init_eeprom(rt2x00dev);
7740 if (retval)
7741 return retval;
7742
7743 /*
7744 * Enable rfkill polling by setting GPIO direction of the
7745 * rfkill switch GPIO pin correctly.
7746 */
7747 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7748 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7749 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7750
7751 /*
7752 * Initialize hw specifications.
7753 */
7754 retval = rt2800_probe_hw_mode(rt2x00dev);
7755 if (retval)
7756 return retval;
7757
7758 /*
7759 * Set device capabilities.
7760 */
7761 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7762 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7763 if (!rt2x00_is_usb(rt2x00dev))
7764 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7765
7766 /*
7767 * Set device requirements.
7768 */
7769 if (!rt2x00_is_soc(rt2x00dev))
7770 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7771 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7772 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7773 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7774 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7775 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7776 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7777 if (rt2x00_is_usb(rt2x00dev))
7778 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7779 else {
7780 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7781 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7782 }
7783
7784 /*
7785 * Set the rssi offset.
7786 */
7787 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7788
7789 return 0;
7790}
7791EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 7792
2ce33995
BZ		 7793/*
7794 * IEEE80211 stack callback functions.
7795 */
9352c19f
JB		 7796void rt2800_get_key_seq(struct ieee80211_hw *hw,
7797 struct ieee80211_key_conf *key,
7798 struct ieee80211_key_seq *seq)
2ce33995
BZ		 7799{
7800 struct rt2x00_dev *rt2x00dev = hw->priv;
7801 struct mac_iveiv_entry iveiv_entry;
7802 u32 offset;
7803
9352c19f
JB		 7804 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
7805 return;
7806
7807 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
2ce33995
BZ		 7808 rt2800_register_multiread(rt2x00dev, offset,
7809 &iveiv_entry, sizeof(iveiv_entry));
7810
9352c19f
JB		 7811 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
7812 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
2ce33995 7813}
9352c19f 7814EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
2ce33995 7815
e783619e 7816int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 7817{
7818 struct rt2x00_dev *rt2x00dev = hw->priv;
7819 u32 reg;
7820 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7821
7822 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7823 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7824 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7825
7826 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7827 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7828 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7829
7830 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7831 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7832 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7833
7834 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7835 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7836 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7837
7838 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7839 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7840 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7841
7842 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7843 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7844 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7845
7846 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7847 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7848 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7849
7850 return 0;
7851}
e783619e 7852EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 7853
8a3a3c85
EP		 7854int rt2800_conf_tx(struct ieee80211_hw *hw,
7855 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 7856 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 7857{
7858 struct rt2x00_dev *rt2x00dev = hw->priv;
7859 struct data_queue *queue;
7860 struct rt2x00_field32 field;
7861 int retval;
7862 u32 reg;
7863 u32 offset;
7864
7865 /*
7866 * First pass the configuration through rt2x00lib, that will
7867 * update the queue settings and validate the input. After that
7868 * we are free to update the registers based on the value
7869 * in the queue parameter.
7870 */
8a3a3c85 7871 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 7872 if (retval)
7873 return retval;
7874
7875 /*
7876 * We only need to perform additional register initialization
7877 * for WMM queues/
7878 */
7879 if (queue_idx >= 4)
7880 return 0;
7881
11f818e0 7882 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 7883
7884 /* Update WMM TXOP register */
7885 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7886 field.bit_offset = (queue_idx & 1) * 16;
7887 field.bit_mask = 0xffff << field.bit_offset;
7888
7889 rt2800_register_read(rt2x00dev, offset, &reg);
7890 rt2x00_set_field32(&reg, field, queue->txop);
7891 rt2800_register_write(rt2x00dev, offset, reg);
7892
7893 /* Update WMM registers */
7894 field.bit_offset = queue_idx * 4;
7895 field.bit_mask = 0xf << field.bit_offset;
7896
7897 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7898 rt2x00_set_field32(&reg, field, queue->aifs);
7899 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7900
7901 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7902 rt2x00_set_field32(&reg, field, queue->cw_min);
7903 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7904
7905 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7906 rt2x00_set_field32(&reg, field, queue->cw_max);
7907 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7908
7909 /* Update EDCA registers */
7910 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7911
7912 rt2800_register_read(rt2x00dev, offset, &reg);
7913 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7914 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7915 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7916 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7917 rt2800_register_write(rt2x00dev, offset, reg);
7918
7919 return 0;
7920}
e783619e 7921EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 7922
37a41b4a 7923u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 7924{
7925 struct rt2x00_dev *rt2x00dev = hw->priv;
7926 u64 tsf;
7927 u32 reg;
7928
7929 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7930 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7931 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7932 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7933
7934 return tsf;
7935}
e783619e 7936EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 7937
e783619e 7938int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 7939 struct ieee80211_ampdu_params *params)
1df90809 7940{
50ea05ef
SS		 7941 struct ieee80211_sta *sta = params->sta;
7942 enum ieee80211_ampdu_mlme_action action = params->action;
7943 u16 tid = params->tid;
af35323d 7944 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 7945 int ret = 0;
7946
af35323d
HS		 7947 /*
7948 * Don't allow aggregation for stations the hardware isn't aware
7949 * of because tx status reports for frames to an unknown station
ed8e0ed5
SG		 7950 * always contain wcid=WCID_END+1 and thus we can't distinguish
7951 * between multiple stations which leads to unwanted situations
7952 * when the hw reorders frames due to aggregation.
af35323d 7953 */
ed8e0ed5 7954 if (sta_priv->wcid > WCID_END)
af35323d
HS		 7955 return 1;
7956
1df90809
HS		 7957 switch (action) {
7958 case IEEE80211_AMPDU_RX_START:
7959 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 7960 /*
7961 * The hw itself takes care of setting up BlockAck mechanisms.
7962 * So, we only have to allow mac80211 to nagotiate a BlockAck
7963 * agreement. Once that is done, the hw will BlockAck incoming
7964 * AMPDUs without further setup.
7965 */
1df90809
HS		 7966 break;
7967 case IEEE80211_AMPDU_TX_START:
7968 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7969 break;
18b559d5
JB		 7970 case IEEE80211_AMPDU_TX_STOP_CONT:
7971 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7972 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 7973 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7974 break;
7975 case IEEE80211_AMPDU_TX_OPERATIONAL:
7976 break;
7977 default:
ec9c4989
JP		 7978 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7979 "Unknown AMPDU action\n");
1df90809
HS		 7980 }
7981
7982 return ret;
7983}
e783619e 7984EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 7985
977206d7
HS		 7986int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7987 struct survey_info *survey)
7988{
7989 struct rt2x00_dev *rt2x00dev = hw->priv;
7990 struct ieee80211_conf *conf = &hw->conf;
7991 u32 idle, busy, busy_ext;
7992
7993 if (idx != 0)
7994 return -ENOENT;
7995
675a0b04 7996 survey->channel = conf->chandef.chan;
977206d7
HS		 7997
7998 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7999 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8000 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8001
8002 if (idle || busy) {
4ed20beb
JB		 8003 survey->filled = SURVEY_INFO_TIME |
8004 SURVEY_INFO_TIME_BUSY |
8005 SURVEY_INFO_TIME_EXT_BUSY;
977206d7 8006
4ed20beb
JB		 8007 survey->time = (idle + busy) / 1000;
8008 survey->time_busy = busy / 1000;
8009 survey->time_ext_busy = busy_ext / 1000;
977206d7
HS		 8010 }
8011
9931df26
HS		 8012 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8013 survey->filled |= SURVEY_INFO_IN_USE;
8014
977206d7
HS		 8015 return 0;
8016
8017}
8018EXPORT_SYMBOL_GPL(rt2800_get_survey);
8019
a5ea2f02
ID		 8020MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8021MODULE_VERSION(DRV_VERSION);
8022MODULE_DESCRIPTION("Ralink RT2800 library");
8023MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)