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wifi: mac80211: change QoS settings API to take link into account
[linux-block.git] / drivers / net / wireless / ralink / rt2x00 / rt2400pci.c
CommitLineData
1ccea77e 1// SPDX-License-Identifier: GPL-2.0-or-later
95ea3627 2/*
9c9a0d14 3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 4 <http://rt2x00.serialmonkey.com>
5
95ea3627
ID		 6 */
7
8/*
9 Module: rt2400pci
10 Abstract: rt2400pci device specific routines.
11 Supported chipsets: RT2460.
12 */
13
95ea3627
ID		 14#include <linux/delay.h>
15#include <linux/etherdevice.h>
95ea3627
ID		 16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/eeprom_93cx6.h>
5a0e3ad6 20#include <linux/slab.h>
95ea3627
ID		 21
22#include "rt2x00.h"
69a2bac8 23#include "rt2x00mmio.h"
95ea3627
ID		 24#include "rt2x00pci.h"
25#include "rt2400pci.h"
26
27/*
28 * Register access.
29 * All access to the CSR registers will go through the methods
172c5911 30 * rt2x00mmio_register_read and rt2x00mmio_register_write.
95ea3627
ID		 31 * BBP and RF register require indirect register access,
32 * and use the CSR registers BBPCSR and RFCSR to achieve this.
33 * These indirect registers work with busy bits,
34 * and we will try maximal REGISTER_BUSY_COUNT times to access
35 * the register while taking a REGISTER_BUSY_DELAY us delay
f5a9987d 36 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 37 * the access attempt is considered to have failed,
38 * and we will print an error.
39 */
c9c3b1a5 40#define WAIT_FOR_BBP(__dev, __reg) \
172c5911 41 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
c9c3b1a5 42#define WAIT_FOR_RF(__dev, __reg) \
172c5911 43 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 44
0e14f6d3 45static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 46 const unsigned int word, const u8 value)
47{
48 u32 reg;
49
8ff48a8b
ID		 50 mutex_lock(&rt2x00dev->csr_mutex);
51
95ea3627 52 /*
c9c3b1a5
ID		 53 * Wait until the BBP becomes available, afterwards we
54 * can safely write the new data into the register.
95ea3627 55 */
c9c3b1a5
ID		 56 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
57 reg = 0;
58 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
59 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
60 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
61 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
62
172c5911 63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
c9c3b1a5 64 }
8ff48a8b 65
8ff48a8b 66 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 67}
68
5fbbe378
AB		 69static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
70 const unsigned int word)
95ea3627
ID		 71{
72 u32 reg;
5fbbe378 73 u8 value;
95ea3627 74
8ff48a8b
ID		 75 mutex_lock(&rt2x00dev->csr_mutex);
76
95ea3627 77 /*
c9c3b1a5
ID		 78 * Wait until the BBP becomes available, afterwards we
79 * can safely write the read request into the register.
80 * After the data has been written, we wait until hardware
81 * returns the correct value, if at any time the register
82 * doesn't become available in time, reg will be 0xffffffff
83 * which means we return 0xff to the caller.
95ea3627 84 */
c9c3b1a5
ID		 85 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
86 reg = 0;
87 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
88 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
89 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 90
172c5911 91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 92
c9c3b1a5
ID		 93 WAIT_FOR_BBP(rt2x00dev, &reg);
94 }
95ea3627 95
5fbbe378 96 value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 97
98 mutex_unlock(&rt2x00dev->csr_mutex);
5fbbe378
AB		 99
100 return value;
95ea3627
ID		 101}
102
0e14f6d3 103static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 104 const unsigned int word, const u32 value)
105{
106 u32 reg;
95ea3627 107
8ff48a8b
ID		 108 mutex_lock(&rt2x00dev->csr_mutex);
109
c9c3b1a5
ID		 110 /*
111 * Wait until the RF becomes available, afterwards we
112 * can safely write the new data into the register.
113 */
114 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
115 reg = 0;
116 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
117 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
118 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
119 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
120
172c5911 121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
c9c3b1a5 122 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 123 }
124
8ff48a8b 125 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 126}
127
128static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
129{
130 struct rt2x00_dev *rt2x00dev = eeprom->data;
131 u32 reg;
132
3954b4e3 133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
95ea3627
ID		 134
135 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
136 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
137 eeprom->reg_data_clock =
138 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
139 eeprom->reg_chip_select =
140 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
141}
142
143static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
144{
145 struct rt2x00_dev *rt2x00dev = eeprom->data;
146 u32 reg = 0;
147
148 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
149 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
150 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
151 !!eeprom->reg_data_clock);
152 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
153 !!eeprom->reg_chip_select);
154
172c5911 155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
95ea3627
ID		 156}
157
158#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 159static const struct rt2x00debug rt2400pci_rt2x00debug = {
160 .owner = THIS_MODULE,
161 .csr = {
3954b4e3 162 .read = rt2x00mmio_register_read,
172c5911 163 .write = rt2x00mmio_register_write,
743b97ca
ID		 164 .flags = RT2X00DEBUGFS_OFFSET,
165 .word_base = CSR_REG_BASE,
95ea3627
ID		 166 .word_size = sizeof(u32),
167 .word_count = CSR_REG_SIZE / sizeof(u32),
168 },
169 .eeprom = {
38651683 170 .read = rt2x00_eeprom_read,
95ea3627 171 .write = rt2x00_eeprom_write,
743b97ca 172 .word_base = EEPROM_BASE,
95ea3627
ID		 173 .word_size = sizeof(u16),
174 .word_count = EEPROM_SIZE / sizeof(u16),
175 },
176 .bbp = {
5fbbe378 177 .read = rt2400pci_bbp_read,
95ea3627 178 .write = rt2400pci_bbp_write,
743b97ca 179 .word_base = BBP_BASE,
95ea3627
ID		 180 .word_size = sizeof(u8),
181 .word_count = BBP_SIZE / sizeof(u8),
182 },
183 .rf = {
aea8baa1 184 .read = rt2x00_rf_read,
95ea3627 185 .write = rt2400pci_rf_write,
743b97ca 186 .word_base = RF_BASE,
95ea3627
ID		 187 .word_size = sizeof(u32),
188 .word_count = RF_SIZE / sizeof(u32),
189 },
190};
191#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
192
95ea3627
ID		 193static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
194{
195 u32 reg;
196
3954b4e3 197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
99bdf51a 198 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
95ea3627 199}
95ea3627 200
771fd565 201#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 202static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 203 enum led_brightness brightness)
204{
205 struct rt2x00_led *led =
206 container_of(led_cdev, struct rt2x00_led, led_dev);
207 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 208 u32 reg;
209
3954b4e3 210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
a9450b70 211
a2e1d52a 212 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 213 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 214 else if (led->type == LED_TYPE_ACTIVITY)
215 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70 216
172c5911 217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
a9450b70 218}
a2e1d52a
ID		 219
220static int rt2400pci_blink_set(struct led_classdev *led_cdev,
221 unsigned long *delay_on,
222 unsigned long *delay_off)
223{
224 struct rt2x00_led *led =
225 container_of(led_cdev, struct rt2x00_led, led_dev);
226 u32 reg;
227
3954b4e3 228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
a2e1d52a
ID		 229 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
230 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
172c5911 231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
a2e1d52a
ID		 232
233 return 0;
234}
475433be
ID		 235
236static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
237 struct rt2x00_led *led,
238 enum led_type type)
239{
240 led->rt2x00dev = rt2x00dev;
241 led->type = type;
242 led->led_dev.brightness_set = rt2400pci_brightness_set;
243 led->led_dev.blink_set = rt2400pci_blink_set;
244 led->flags = LED_INITIALIZED;
245}
771fd565 246#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 247
95ea3627
ID		 248/*
249 * Configuration handlers.
250 */
3a643d24
ID		 251static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
252 const unsigned int filter_flags)
253{
254 u32 reg;
255
256 /*
257 * Start configuration steps.
258 * Note that the version error will always be dropped
259 * since there is no filter for it at this time.
260 */
3954b4e3 261 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
3a643d24
ID		 262 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
263 !(filter_flags & FIF_FCSFAIL));
264 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
265 !(filter_flags & FIF_PLCPFAIL));
266 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
267 !(filter_flags & FIF_CONTROL));
262c741e
EC		 268 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
269 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
3a643d24 270 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
262c741e 271 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
e0b005fa 272 !rt2x00dev->intf_ap_count);
3a643d24 273 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
172c5911 274 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
3a643d24
ID		 275}
276
6bb40dd1
ID		 277static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
278 struct rt2x00_intf *intf,
279 struct rt2x00intf_conf *conf,
280 const unsigned int flags)
95ea3627 281{
6bb40dd1
ID		 282 unsigned int bcn_preload;
283 u32 reg;
95ea3627 284
6bb40dd1 285 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 286 /*
287 * Enable beacon config
288 */
bad13639 289 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
3954b4e3 290 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
6bb40dd1 291 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
172c5911 292 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 293
6bb40dd1
ID		 294 /*
295 * Enable synchronisation.
296 */
3954b4e3 297 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
6bb40dd1 298 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
172c5911 299 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
6bb40dd1 300 }
95ea3627 301
6bb40dd1 302 if (flags & CONFIG_UPDATE_MAC)
172c5911
GJ		 303 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
304 conf->mac, sizeof(conf->mac));
95ea3627 305
6bb40dd1 306 if (flags & CONFIG_UPDATE_BSSID)
172c5911
GJ		 307 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
308 conf->bssid,
309 sizeof(conf->bssid));
95ea3627
ID		 310}
311
3a643d24 312static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 313 struct rt2x00lib_erp *erp,
314 u32 changed)
95ea3627 315{
5c58ee51 316 int preamble_mask;
95ea3627 317 u32 reg;
95ea3627 318
5c58ee51
ID		 319 /*
320 * When short preamble is enabled, we should set bit 0x08
321 */
02044643
HS		 322 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
323 preamble_mask = erp->short_preamble << 3;
324
3954b4e3 325 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
02044643
HS		 326 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
327 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
328 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
329 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
172c5911 330 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
02044643 331
3954b4e3 332 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
02044643
HS		 333 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
334 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
335 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
336 GET_DURATION(ACK_SIZE, 10));
172c5911 337 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
02044643 338
3954b4e3 339 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
02044643
HS		 340 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
341 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
342 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
343 GET_DURATION(ACK_SIZE, 20));
172c5911 344 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
02044643 345
3954b4e3 346 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
02044643
HS		 347 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
348 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
349 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
350 GET_DURATION(ACK_SIZE, 55));
172c5911 351 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
02044643 352
3954b4e3 353 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
02044643
HS		 354 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
355 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
357 GET_DURATION(ACK_SIZE, 110));
172c5911 358 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
02044643
HS		 359 }
360
361 if (changed & BSS_CHANGED_BASIC_RATES)
172c5911 362 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
02044643
HS		 363
364 if (changed & BSS_CHANGED_ERP_SLOT) {
3954b4e3 365 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
02044643 366 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
172c5911 367 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
02044643 368
3954b4e3 369 reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
02044643
HS		 370 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
371 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
172c5911 372 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
02044643 373
3954b4e3 374 reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
02044643
HS		 375 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
376 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
172c5911 377 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
02044643
HS		 378 }
379
380 if (changed & BSS_CHANGED_BEACON_INT) {
3954b4e3 381 reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
02044643
HS		 382 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
383 erp->beacon_int * 16);
384 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
385 erp->beacon_int * 16);
172c5911 386 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
02044643 387 }
95ea3627
ID		 388}
389
e4ea1c40
ID		 390static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
391 struct antenna_setup *ant)
95ea3627 392{
e4ea1c40
ID		 393 u8 r1;
394 u8 r4;
395
396 /*
397 * We should never come here because rt2x00lib is supposed
398 * to catch this and send us the correct antenna explicitely.
399 */
400 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
401 ant->tx == ANTENNA_SW_DIVERSITY);
402
5fbbe378
AB		 403 r4 = rt2400pci_bbp_read(rt2x00dev, 4);
404 r1 = rt2400pci_bbp_read(rt2x00dev, 1);
e4ea1c40
ID		 405
406 /*
407 * Configure the TX antenna.
408 */
409 switch (ant->tx) {
410 case ANTENNA_HW_DIVERSITY:
411 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
412 break;
413 case ANTENNA_A:
414 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
415 break;
416 case ANTENNA_B:
417 default:
418 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
419 break;
420 }
421
422 /*
423 * Configure the RX antenna.
424 */
425 switch (ant->rx) {
426 case ANTENNA_HW_DIVERSITY:
427 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
428 break;
429 case ANTENNA_A:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
431 break;
432 case ANTENNA_B:
433 default:
434 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
435 break;
436 }
437
438 rt2400pci_bbp_write(rt2x00dev, 4, r4);
439 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 440}
441
442static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 443 struct rf_channel *rf)
95ea3627 444{
95ea3627
ID		 445 /*
446 * Switch on tuning bits.
447 */
5c58ee51
ID		 448 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
449 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 450
5c58ee51
ID		 451 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
452 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
453 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 454
455 /*
456 * RF2420 chipset don't need any additional actions.
457 */
5122d898 458 if (rt2x00_rf(rt2x00dev, RF2420))
95ea3627
ID		 459 return;
460
461 /*
462 * For the RT2421 chipsets we need to write an invalid
463 * reference clock rate to activate auto_tune.
464 * After that we set the value back to the correct channel.
465 */
5c58ee51 466 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 467 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 468 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 469
470 msleep(1);
471
5c58ee51
ID		 472 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
473 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
474 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 475
476 msleep(1);
477
478 /*
479 * Switch off tuning bits.
480 */
5c58ee51
ID		 481 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
482 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 483
5c58ee51
ID		 484 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
485 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 486
487 /*
488 * Clear false CRC during channel switch.
489 */
3954b4e3 490 rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
95ea3627
ID		 491}
492
493static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
494{
495 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
496}
497
e4ea1c40
ID		 498static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
499 struct rt2x00lib_conf *libconf)
95ea3627 500{
e4ea1c40 501 u32 reg;
95ea3627 502
3954b4e3 503 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
e4ea1c40
ID		 504 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
505 libconf->conf->long_frame_max_tx_count);
506 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
507 libconf->conf->short_frame_max_tx_count);
172c5911 508 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 509}
510
7d7f19cc
ID		 511static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
512 struct rt2x00lib_conf *libconf)
513{
514 enum dev_state state =
515 (libconf->conf->flags & IEEE80211_CONF_PS) ?
516 STATE_SLEEP : STATE_AWAKE;
517 u32 reg;
518
519 if (state == STATE_SLEEP) {
3954b4e3 520 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
7d7f19cc 521 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 522 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 523 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
524 libconf->conf->listen_interval - 1);
525
526 /* We must first disable autowake before it can be enabled */
527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
172c5911 528 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 529
530 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
172c5911 531 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
5731858d 532 } else {
3954b4e3 533 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
5731858d 534 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
172c5911 535 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 536 }
537
538 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
539}
540
95ea3627 541static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 542 struct rt2x00lib_conf *libconf,
543 const unsigned int flags)
95ea3627 544{
e4ea1c40 545 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 546 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 547 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 548 rt2400pci_config_txpower(rt2x00dev,
549 libconf->conf->power_level);
e4ea1c40
ID		 550 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
551 rt2400pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 552 if (flags & IEEE80211_CONF_CHANGE_PS)
553 rt2400pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 554}
555
556static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 557 const int cw_min, const int cw_max)
95ea3627
ID		 558{
559 u32 reg;
560
3954b4e3 561 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
181d6902
ID		 562 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
563 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
172c5911 564 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 565}
566
95ea3627
ID		 567/*
568 * Link tuning
569 */
ebcf26da
ID		 570static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
571 struct link_qual *qual)
95ea3627
ID		 572{
573 u32 reg;
574 u8 bbp;
575
576 /*
577 * Update FCS error count from register.
578 */
3954b4e3 579 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
ebcf26da 580 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 581
582 /*
583 * Update False CCA count from register.
584 */
5fbbe378 585 bbp = rt2400pci_bbp_read(rt2x00dev, 39);
ebcf26da 586 qual->false_cca = bbp;
95ea3627
ID		 587}
588
5352ff65
ID		 589static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
590 struct link_qual *qual, u8 vgc_level)
eb20b4e8 591{
223dcc26
ID		 592 if (qual->vgc_level_reg != vgc_level) {
593 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
594 qual->vgc_level = vgc_level;
595 qual->vgc_level_reg = vgc_level;
596 }
eb20b4e8
ID		 597}
598
5352ff65
ID		 599static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
600 struct link_qual *qual)
95ea3627 601{
5352ff65 602 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
95ea3627
ID		 603}
604
5352ff65
ID		 605static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
606 struct link_qual *qual, const u32 count)
95ea3627 607{
95ea3627
ID		 608 /*
609 * The link tuner should not run longer then 60 seconds,
610 * and should run once every 2 seconds.
611 */
5352ff65 612 if (count > 60 || !(count & 1))
95ea3627
ID		 613 return;
614
615 /*
616 * Base r13 link tuning on the false cca count.
617 */
5352ff65
ID		 618 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
619 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
620 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
621 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 622}
623
5450b7e2
ID		 624/*
625 * Queue handlers.
626 */
627static void rt2400pci_start_queue(struct data_queue *queue)
628{
629 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
630 u32 reg;
631
632 switch (queue->qid) {
633 case QID_RX:
3954b4e3 634 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
5450b7e2 635 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
172c5911 636 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
5450b7e2
ID		 637 break;
638 case QID_BEACON:
3954b4e3 639 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
5450b7e2
ID		 640 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
641 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
642 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
172c5911 643 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
5450b7e2
ID		 644 break;
645 default:
646 break;
647 }
648}
649
650static void rt2400pci_kick_queue(struct data_queue *queue)
651{
652 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
653 u32 reg;
654
655 switch (queue->qid) {
f615e9a3 656 case QID_AC_VO:
3954b4e3 657 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
5450b7e2 658 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
172c5911 659 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2 660 break;
f615e9a3 661 case QID_AC_VI:
3954b4e3 662 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
5450b7e2 663 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
172c5911 664 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 665 break;
666 case QID_ATIM:
3954b4e3 667 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
5450b7e2 668 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
172c5911 669 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 670 break;
671 default:
672 break;
673 }
674}
675
676static void rt2400pci_stop_queue(struct data_queue *queue)
677{
678 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
679 u32 reg;
680
681 switch (queue->qid) {
f615e9a3
ID		 682 case QID_AC_VO:
683 case QID_AC_VI:
5450b7e2 684 case QID_ATIM:
3954b4e3 685 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
5450b7e2 686 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
172c5911 687 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 688 break;
689 case QID_RX:
3954b4e3 690 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
5450b7e2 691 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
172c5911 692 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
5450b7e2
ID		 693 break;
694 case QID_BEACON:
3954b4e3 695 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
5450b7e2
ID		 696 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
697 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
698 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
172c5911 699 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
bcf3cfd0
HS		 700
701 /*
702 * Wait for possibly running tbtt tasklets.
703 */
abc11994 704 tasklet_kill(&rt2x00dev->tbtt_tasklet);
5450b7e2
ID		 705 break;
706 default:
707 break;
708 }
709}
710
95ea3627
ID		 711/*
712 * Initialization functions.
713 */
798b7adb 714static bool rt2400pci_get_entry_state(struct queue_entry *entry)
95ea3627 715{
172c5911 716 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
95ea3627
ID		 717 u32 word;
718
798b7adb 719 if (entry->queue->qid == QID_RX) {
b9b23872 720 word = rt2x00_desc_read(entry_priv->desc, 0);
95ea3627 721
798b7adb
ID		 722 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
723 } else {
b9b23872 724 word = rt2x00_desc_read(entry_priv->desc, 0);
95ea3627 725
798b7adb
ID		 726 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
727 rt2x00_get_field32(word, TXD_W0_VALID));
728 }
95ea3627
ID		 729}
730
798b7adb 731static void rt2400pci_clear_entry(struct queue_entry *entry)
95ea3627 732{
172c5911 733 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
798b7adb 734 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 735 u32 word;
736
798b7adb 737 if (entry->queue->qid == QID_RX) {
b9b23872 738 word = rt2x00_desc_read(entry_priv->desc, 2);
798b7adb
ID		 739 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
740 rt2x00_desc_write(entry_priv->desc, 2, word);
741
b9b23872 742 word = rt2x00_desc_read(entry_priv->desc, 1);
798b7adb
ID		 743 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
744 rt2x00_desc_write(entry_priv->desc, 1, word);
745
b9b23872 746 word = rt2x00_desc_read(entry_priv->desc, 0);
798b7adb
ID		 747 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
748 rt2x00_desc_write(entry_priv->desc, 0, word);
749 } else {
b9b23872 750 word = rt2x00_desc_read(entry_priv->desc, 0);
798b7adb
ID		 751 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
752 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
753 rt2x00_desc_write(entry_priv->desc, 0, word);
754 }
95ea3627
ID		 755}
756
181d6902 757static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 758{
172c5911 759 struct queue_entry_priv_mmio *entry_priv;
95ea3627
ID		 760 u32 reg;
761
95ea3627
ID		 762 /*
763 * Initialize registers.
764 */
3954b4e3 765 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
181d6902
ID		 766 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
767 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
e74df4a7 768 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
181d6902 769 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
172c5911 770 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
95ea3627 771
b8be63ff 772 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
3954b4e3 773 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
30b3a23c 774 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 775 entry_priv->desc_dma);
172c5911 776 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
95ea3627 777
b8be63ff 778 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
3954b4e3 779 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
30b3a23c 780 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 781 entry_priv->desc_dma);
172c5911 782 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
95ea3627 783
e74df4a7 784 entry_priv = rt2x00dev->atim->entries[0].priv_data;
3954b4e3 785 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
30b3a23c 786 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 787 entry_priv->desc_dma);
172c5911 788 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
95ea3627 789
e74df4a7 790 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
3954b4e3 791 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
30b3a23c 792 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 793 entry_priv->desc_dma);
172c5911 794 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
95ea3627 795
3954b4e3 796 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
95ea3627 797 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 798 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
172c5911 799 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
95ea3627 800
b8be63ff 801 entry_priv = rt2x00dev->rx->entries[0].priv_data;
3954b4e3 802 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
b8be63ff
ID		 803 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
804 entry_priv->desc_dma);
172c5911 805 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
95ea3627
ID		 806
807 return 0;
808}
809
810static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
811{
812 u32 reg;
813
172c5911
GJ		 814 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
815 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
816 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
817 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
95ea3627 818
3954b4e3 819 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
95ea3627
ID		 820 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
821 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
822 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
172c5911 823 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
95ea3627 824
3954b4e3 825 reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
95ea3627
ID		 826 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
827 (rt2x00dev->rx->data_size / 128));
172c5911 828 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
95ea3627 829
3954b4e3 830 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1f909162
ID		 831 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
832 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
833 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
834 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
835 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
836 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
837 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
838 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
172c5911 839 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1f909162 840
172c5911 841 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
95ea3627 842
3954b4e3 843 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);
95ea3627
ID		 844 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
845 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
846 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
847 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
172c5911 848 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
95ea3627 849
3954b4e3 850 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
95ea3627
ID		 851 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
852 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
853 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
854 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
855 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
856 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
172c5911 857 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
95ea3627 858
172c5911 859 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
95ea3627
ID		 860
861 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
862 return -EBUSY;
863
172c5911
GJ		 864 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
865 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
95ea3627 866
3954b4e3 867 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
95ea3627 868 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
172c5911 869 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
95ea3627 870
3954b4e3 871 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
95ea3627
ID		 872 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
873 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
874 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
875 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
172c5911 876 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
95ea3627 877
3954b4e3 878 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
95ea3627
ID		 879 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
880 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
881 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
172c5911 882 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
95ea3627 883
3954b4e3 884 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
95ea3627
ID		 885 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
886 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
172c5911 887 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
95ea3627
ID		 888
889 /*
890 * We must clear the FCS and FIFO error count.
891 * These registers are cleared on read,
892 * so we may pass a useless variable to store the value.
893 */
3954b4e3
AB		 894 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
895 reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
95ea3627
ID		 896
897 return 0;
898}
899
2b08da3f 900static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 901{
902 unsigned int i;
95ea3627
ID		 903 u8 value;
904
905 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5fbbe378 906 value = rt2400pci_bbp_read(rt2x00dev, 0);
95ea3627 907 if ((value != 0xff) && (value != 0x00))
2b08da3f 908 return 0;
95ea3627
ID		 909 udelay(REGISTER_BUSY_DELAY);
910 }
911
ec9c4989 912 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
95ea3627 913 return -EACCES;
2b08da3f
ID		 914}
915
916static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
917{
918 unsigned int i;
919 u16 eeprom;
920 u8 reg_id;
921 u8 value;
922
923 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
924 return -EACCES;
95ea3627 925
95ea3627
ID		 926 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
927 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
928 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
929 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
930 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
931 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
932 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
933 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
934 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
935 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
936 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
937 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
938 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
939 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
940
95ea3627 941 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
38651683 942 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
95ea3627
ID		 943
944 if (eeprom != 0xffff && eeprom != 0x0000) {
945 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
946 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 947 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
948 }
949 }
95ea3627
ID		 950
951 return 0;
952}
953
954/*
955 * Device state switch handlers.
956 */
95ea3627
ID		 957static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
958 enum dev_state state)
959{
b550911a 960 int mask = (state == STATE_RADIO_IRQ_OFF);
95ea3627 961 u32 reg;
bcf3cfd0 962 unsigned long flags;
95ea3627
ID		 963
964 /*
965 * When interrupts are being enabled, the interrupt registers
966 * should clear the register to assure a clean state.
967 */
968 if (state == STATE_RADIO_IRQ_ON) {
3954b4e3 969 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
172c5911 970 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
95ea3627
ID		 971 }
972
973 /*
974 * Only toggle the interrupts bits we are going to use.
975 * Non-checked interrupt bits are disabled by default.
976 */
bcf3cfd0
HS		 977 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
978
3954b4e3 979 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
95ea3627
ID		 980 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
981 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
982 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
983 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
984 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
172c5911 985 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0
HS		 986
987 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
988
989 if (state == STATE_RADIO_IRQ_OFF) {
990 /*
991 * Ensure that all tasklets are finished before
992 * disabling the interrupts.
993 */
abc11994
HS		 994 tasklet_kill(&rt2x00dev->txstatus_tasklet);
995 tasklet_kill(&rt2x00dev->rxdone_tasklet);
996 tasklet_kill(&rt2x00dev->tbtt_tasklet);
bcf3cfd0 997 }
95ea3627
ID		 998}
999
1000static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1001{
1002 /*
1003 * Initialize all registers.
1004 */
2b08da3f
ID		 1005 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1006 rt2400pci_init_registers(rt2x00dev) ||
1007 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 1008 return -EIO;
95ea3627 1009
95ea3627
ID		 1010 return 0;
1011}
1012
1013static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1014{
95ea3627 1015 /*
a2c9b652 1016 * Disable power
95ea3627 1017 */
172c5911 1018 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1019}
1020
1021static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1022 enum dev_state state)
1023{
9655a6ec 1024 u32 reg, reg2;
95ea3627
ID		 1025 unsigned int i;
1026 char put_to_sleep;
1027 char bbp_state;
1028 char rf_state;
1029
1030 put_to_sleep = (state != STATE_AWAKE);
1031
3954b4e3 1032 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
95ea3627
ID		 1033 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1034 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1035 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1036 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
172c5911 1037 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1038
1039 /*
1040 * Device is not guaranteed to be in the requested state yet.
1041 * We must wait until the register indicates that the
1042 * device has entered the correct state.
1043 */
1044 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3954b4e3 1045 reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
9655a6ec
GW		 1046 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1047 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 1048 if (bbp_state == state && rf_state == state)
1049 return 0;
172c5911 1050 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1051 msleep(10);
1052 }
1053
95ea3627
ID		 1054 return -EBUSY;
1055}
1056
1057static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1058 enum dev_state state)
1059{
1060 int retval = 0;
1061
1062 switch (state) {
1063 case STATE_RADIO_ON:
1064 retval = rt2400pci_enable_radio(rt2x00dev);
1065 break;
1066 case STATE_RADIO_OFF:
1067 rt2400pci_disable_radio(rt2x00dev);
1068 break;
2b08da3f
ID		 1069 case STATE_RADIO_IRQ_ON:
1070 case STATE_RADIO_IRQ_OFF:
1071 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1072 break;
1073 case STATE_DEEP_SLEEP:
1074 case STATE_SLEEP:
1075 case STATE_STANDBY:
1076 case STATE_AWAKE:
1077 retval = rt2400pci_set_state(rt2x00dev, state);
1078 break;
1079 default:
1080 retval = -ENOTSUPP;
1081 break;
1082 }
1083
2b08da3f 1084 if (unlikely(retval))
ec9c4989
JP		 1085 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1086 state, retval);
2b08da3f 1087
95ea3627
ID		 1088 return retval;
1089}
1090
1091/*
1092 * TX descriptor initialization
1093 */
93331458 1094static void rt2400pci_write_tx_desc(struct queue_entry *entry,
61486e0f 1095 struct txentry_desc *txdesc)
95ea3627 1096{
93331458 1097 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
172c5911 1098 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
85b7a8b3 1099 __le32 *txd = entry_priv->desc;
95ea3627 1100 u32 word;
95ea3627
ID		 1101
1102 /*
1103 * Start writing the descriptor words.
1104 */
b9b23872 1105 word = rt2x00_desc_read(txd, 1);
c4da0048 1106 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1107 rt2x00_desc_write(txd, 1, word);
4de36fe5 1108
b9b23872 1109 word = rt2x00_desc_read(txd, 2);
df624ca5
GW		 1110 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1111 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1112 rt2x00_desc_write(txd, 2, word);
1113
b9b23872 1114 word = rt2x00_desc_read(txd, 3);
26a1d07f 1115 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
49da2605
ID		 1116 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1117 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
26a1d07f 1118 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
49da2605
ID		 1119 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1120 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1121 rt2x00_desc_write(txd, 3, word);
1122
b9b23872 1123 word = rt2x00_desc_read(txd, 4);
26a1d07f
HS		 1124 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1125 txdesc->u.plcp.length_low);
49da2605
ID		 1126 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1127 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
26a1d07f
HS		 1128 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1129 txdesc->u.plcp.length_high);
49da2605
ID		 1130 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1131 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1132 rt2x00_desc_write(txd, 4, word);
1133
e01f1ec3
GW		 1134 /*
1135 * Writing TXD word 0 must the last to prevent a race condition with
1136 * the device, whereby the device may take hold of the TXD before we
1137 * finished updating it.
1138 */
b9b23872 1139 word = rt2x00_desc_read(txd, 0);
95ea3627
ID		 1140 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1141 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1142 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1143 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1144 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1145 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1146 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1147 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1148 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902 1149 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
2517794b 1150 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
95ea3627 1151 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1152 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1153 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1154
1155 /*
1156 * Register descriptor details in skb frame descriptor.
1157 */
1158 skbdesc->desc = txd;
1159 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1160}
1161
1162/*
1163 * TX data initialization
1164 */
f224f4ef
GW		 1165static void rt2400pci_write_beacon(struct queue_entry *entry,
1166 struct txentry_desc *txdesc)
bd88a781
ID		 1167{
1168 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1169 u32 reg;
1170
1171 /*
1172 * Disable beaconing while we are reloading the beacon data,
1173 * otherwise we might be sending out invalid data.
1174 */
3954b4e3 1175 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
bd88a781 1176 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
172c5911 1177 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
bd88a781 1178
4ea545d4 1179 if (rt2x00queue_map_txskb(entry)) {
ec9c4989 1180 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
4ea545d4
SG		 1181 goto out;
1182 }
1183 /*
1184 * Enable beaconing again.
1185 */
1186 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
5c3b685c
GW		 1187 /*
1188 * Write the TX descriptor for the beacon.
1189 */
93331458 1190 rt2400pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1191
1192 /*
1193 * Dump beacon to userspace through debugfs.
1194 */
2ceb8137 1195 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
4ea545d4 1196out:
d61cb266
GW		 1197 /*
1198 * Enable beaconing again.
1199 */
d61cb266 1200 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
172c5911 1201 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1202}
1203
95ea3627
ID		 1204/*
1205 * RX control handlers
1206 */
181d6902
ID		 1207static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1208 struct rxdone_entry_desc *rxdesc)
95ea3627 1209{
ae73e58e 1210 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
172c5911 1211 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
95ea3627
ID		 1212 u32 word0;
1213 u32 word2;
89993890 1214 u32 word3;
ae73e58e
ID		 1215 u32 word4;
1216 u64 tsf;
1217 u32 rx_low;
1218 u32 rx_high;
95ea3627 1219
b9b23872
AB		 1220 word0 = rt2x00_desc_read(entry_priv->desc, 0);
1221 word2 = rt2x00_desc_read(entry_priv->desc, 2);
1222 word3 = rt2x00_desc_read(entry_priv->desc, 3);
1223 word4 = rt2x00_desc_read(entry_priv->desc, 4);
95ea3627 1224
4150c572 1225 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1226 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1227 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1228 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1229
ae73e58e
ID		 1230 /*
1231 * We only get the lower 32bits from the timestamp,
1232 * to get the full 64bits we must complement it with
1233 * the timestamp from get_tsf().
1234 * Note that when a wraparound of the lower 32bits
1235 * has occurred between the frame arrival and the get_tsf()
1236 * call, we must decrease the higher 32bits with 1 to get
1237 * to correct value.
1238 */
37a41b4a 1239 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
ae73e58e
ID		 1240 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1241 rx_high = upper_32_bits(tsf);
1242
1243 if ((u32)tsf <= rx_low)
1244 rx_high--;
1245
95ea3627
ID		 1246 /*
1247 * Obtain the status about this packet.
8ed09854
ID		 1248 * The signal is the PLCP value, and needs to be stripped
1249 * of the preamble bit (0x08).
95ea3627 1250 */
ae73e58e 1251 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1252 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
2bf127a5 1253 rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) -
181d6902 1254 entry->queue->rt2x00dev->rssi_offset;
181d6902 1255 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1256
dec13b6b 1257 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1258 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1259 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1260}
1261
1262/*
1263 * Interrupt functions.
1264 */
181d6902 1265static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1266 const enum data_queue_qid queue_idx)
95ea3627 1267{
61c6e489 1268 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
172c5911 1269 struct queue_entry_priv_mmio *entry_priv;
181d6902
ID		 1270 struct queue_entry *entry;
1271 struct txdone_entry_desc txdesc;
95ea3627 1272 u32 word;
95ea3627 1273
181d6902
ID		 1274 while (!rt2x00queue_empty(queue)) {
1275 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff 1276 entry_priv = entry->priv_data;
b9b23872 1277 word = rt2x00_desc_read(entry_priv->desc, 0);
95ea3627
ID		 1278
1279 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1280 !rt2x00_get_field32(word, TXD_W0_VALID))
1281 break;
1282
1283 /*
1284 * Obtain the status about this packet.
1285 */
fb55f4d1
ID		 1286 txdesc.flags = 0;
1287 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1288 case 0: /* Success */
1289 case 1: /* Success with retry */
1290 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1291 break;
1292 case 2: /* Failure, excessive retries */
1293 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
74aad394 1294 fallthrough; /* this is a failed frame! */
fb55f4d1
ID		 1295 default: /* Failure */
1296 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1297 }
181d6902 1298 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1299
e513a0b6 1300 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1301 }
95ea3627
ID		 1302}
1303
7a5a681a
HS		 1304static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1305 struct rt2x00_field32 irq_field)
95ea3627 1306{
bcf3cfd0 1307 u32 reg;
95ea3627
ID		 1308
1309 /*
bcf3cfd0
HS		 1310 * Enable a single interrupt. The interrupt mask register
1311 * access needs locking.
95ea3627 1312 */
0aa13b2e 1313 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1314
3954b4e3 1315 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
bcf3cfd0 1316 rt2x00_set_field32(&reg, irq_field, 0);
172c5911 1317 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
95ea3627 1318
0aa13b2e 1319 spin_unlock_irq(&rt2x00dev->irqmask_lock);
bcf3cfd0 1320}
95ea3627 1321
a0d6ea9b 1322static void rt2400pci_txstatus_tasklet(struct tasklet_struct *t)
bcf3cfd0 1323{
a0d6ea9b
AP		 1324 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1325 txstatus_tasklet);
bcf3cfd0 1326 u32 reg;
95ea3627
ID		 1327
1328 /*
bcf3cfd0 1329 * Handle all tx queues.
95ea3627 1330 */
bcf3cfd0
HS		 1331 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1332 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1333 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
95ea3627
ID		 1334
1335 /*
bcf3cfd0 1336 * Enable all TXDONE interrupts again.
95ea3627 1337 */
abc11994
HS		 1338 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1339 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1340
3954b4e3 1341 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
abc11994
HS		 1342 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1343 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1344 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
172c5911 1345 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0 1346
abc11994
HS		 1347 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1348 }
bcf3cfd0
HS		 1349}
1350
a0d6ea9b 1351static void rt2400pci_tbtt_tasklet(struct tasklet_struct *t)
bcf3cfd0 1352{
a0d6ea9b 1353 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
bcf3cfd0 1354 rt2x00lib_beacondone(rt2x00dev);
abc11994
HS		 1355 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1356 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
bcf3cfd0
HS		 1357}
1358
a0d6ea9b 1359static void rt2400pci_rxdone_tasklet(struct tasklet_struct *t)
bcf3cfd0 1360{
a0d6ea9b
AP		 1361 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1362 rxdone_tasklet);
172c5911 1363 if (rt2x00mmio_rxdone(rt2x00dev))
16638937 1364 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 1365 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 1366 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
95ea3627
ID		 1367}
1368
78e256c9
HS		 1369static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1370{
1371 struct rt2x00_dev *rt2x00dev = dev_instance;
bcf3cfd0 1372 u32 reg, mask;
78e256c9
HS		 1373
1374 /*
1375 * Get the interrupt sources & saved to local variable.
1376 * Write register value back to clear pending interrupts.
1377 */
3954b4e3 1378 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
172c5911 1379 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
78e256c9
HS		 1380
1381 if (!reg)
1382 return IRQ_NONE;
1383
1384 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1385 return IRQ_HANDLED;
1386
bcf3cfd0
HS		 1387 mask = reg;
1388
1389 /*
1390 * Schedule tasklets for interrupt handling.
1391 */
1392 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1393 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1394
1395 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1396 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1397
1398 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1399 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1400 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1401 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1402 /*
1403 * Mask out all txdone interrupts.
1404 */
1405 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1406 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1407 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1408 }
78e256c9 1409
bcf3cfd0
HS		 1410 /*
1411 * Disable all interrupts for which a tasklet was scheduled right now,
1412 * the tasklet will reenable the appropriate interrupts.
1413 */
0aa13b2e 1414 spin_lock(&rt2x00dev->irqmask_lock);
78e256c9 1415
3954b4e3 1416 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
bcf3cfd0 1417 reg |= mask;
172c5911 1418 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0 1419
0aa13b2e 1420 spin_unlock(&rt2x00dev->irqmask_lock);
bcf3cfd0
HS		 1421
1422
1423
1424 return IRQ_HANDLED;
78e256c9
HS		 1425}
1426
95ea3627
ID		 1427/*
1428 * Device probe functions.
1429 */
1430static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1431{
1432 struct eeprom_93cx6 eeprom;
1433 u32 reg;
1434 u16 word;
1435 u8 *mac;
1436
3954b4e3 1437 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
95ea3627
ID		 1438
1439 eeprom.data = rt2x00dev;
1440 eeprom.register_read = rt2400pci_eepromregister_read;
1441 eeprom.register_write = rt2400pci_eepromregister_write;
1442 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1443 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1444 eeprom.reg_data_in = 0;
1445 eeprom.reg_data_out = 0;
1446 eeprom.reg_data_clock = 0;
1447 eeprom.reg_chip_select = 0;
1448
1449 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1450 EEPROM_SIZE / sizeof(u16));
1451
1452 /*
1453 * Start validation of the data that has been read.
1454 */
1455 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9766cb70 1456 rt2x00lib_set_mac_address(rt2x00dev, mac);
95ea3627 1457
38651683 1458 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
95ea3627 1459 if (word == 0xffff) {
ec9c4989 1460 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
95ea3627
ID		 1461 return -EINVAL;
1462 }
1463
1464 return 0;
1465}
1466
1467static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1468{
1469 u32 reg;
1470 u16 value;
1471 u16 eeprom;
1472
1473 /*
1474 * Read EEPROM word for configuration.
1475 */
38651683 1476 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
95ea3627
ID		 1477
1478 /*
1479 * Identify RF chipset.
1480 */
1481 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
3954b4e3 1482 reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
49e721ec
GW		 1483 rt2x00_set_chip(rt2x00dev, RT2460, value,
1484 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1485
5122d898 1486 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
ec9c4989 1487 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
95ea3627
ID		 1488 return -ENODEV;
1489 }
1490
1491 /*
1492 * Identify default antenna configuration.
1493 */
addc81bd 1494 rt2x00dev->default_ant.tx =
95ea3627 1495 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1496 rt2x00dev->default_ant.rx =
95ea3627
ID		 1497 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1498
addc81bd
ID		 1499 /*
1500 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1501 * I am not 100% sure about this, but the legacy drivers do not
1502 * indicate antenna swapping in software is required when
1503 * diversity is enabled.
1504 */
1505 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1506 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1507 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1508 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1509
95ea3627
ID		 1510 /*
1511 * Store led mode, for correct led behaviour.
1512 */
771fd565 1513#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1514 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1515
475433be 1516 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1517 if (value == LED_MODE_TXRX_ACTIVITY ||
1518 value == LED_MODE_DEFAULT ||
1519 value == LED_MODE_ASUS)
475433be
ID		 1520 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1521 LED_TYPE_ACTIVITY);
771fd565 1522#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1523
1524 /*
1525 * Detect if this device has an hardware controlled radio.
1526 */
1527 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
7dab73b3 1528 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
95ea3627
ID		 1529
1530 /*
1531 * Check if the BBP tuning should be enabled.
1532 */
27df2a9c 1533 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
7dab73b3 1534 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
95ea3627
ID		 1535
1536 return 0;
1537}
1538
1539/*
1540 * RF value list for RF2420 & RF2421
1541 * Supports: 2.4 GHz
1542 */
8c5e7a5f 1543static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1544 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1545 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1546 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1547 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1548 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1549 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1550 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1551 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1552 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1553 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1554 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1555 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1556 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1557 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1558};
1559
8c5e7a5f 1560static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1561{
1562 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1563 struct channel_info *info;
1564 char *tx_power;
95ea3627
ID		 1565 unsigned int i;
1566
1567 /*
1568 * Initialize all hw fields.
1569 */
30686bf7
JB		 1570 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1571 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1572 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1573 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
95ea3627 1574
14a3bf89 1575 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1576 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1577 rt2x00_eeprom_addr(rt2x00dev,
1578 EEPROM_MAC_ADDR_0));
1579
95ea3627
ID		 1580 /*
1581 * Initialize hw_mode information.
1582 */
31562e80
ID		 1583 spec->supported_bands = SUPPORT_BAND_2GHZ;
1584 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1585
8c5e7a5f
ID		 1586 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1587 spec->channels = rf_vals_b;
1588
1589 /*
1590 * Create channel information array
1591 */
baeb2ffa 1592 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1593 if (!info)
1594 return -ENOMEM;
1595
1596 spec->channels_info = info;
1597
1598 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1599 for (i = 0; i < 14; i++) {
1600 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1601 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1602 }
8c5e7a5f
ID		 1603
1604 return 0;
95ea3627
ID		 1605}
1606
1607static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1608{
1609 int retval;
a396e100 1610 u32 reg;
95ea3627
ID		 1611
1612 /*
1613 * Allocate eeprom data.
1614 */
1615 retval = rt2400pci_validate_eeprom(rt2x00dev);
1616 if (retval)
1617 return retval;
1618
1619 retval = rt2400pci_init_eeprom(rt2x00dev);
1620 if (retval)
1621 return retval;
1622
a396e100
GW		 1623 /*
1624 * Enable rfkill polling by setting GPIO direction of the
1625 * rfkill switch GPIO pin correctly.
1626 */
3954b4e3 1627 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
99bdf51a 1628 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
172c5911 1629 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
a396e100 1630
95ea3627
ID		 1631 /*
1632 * Initialize hw specifications.
1633 */
8c5e7a5f
ID		 1634 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1635 if (retval)
1636 return retval;
95ea3627
ID		 1637
1638 /*
c4da0048 1639 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1640 */
7dab73b3
ID		 1641 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1642 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1643 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
95ea3627
ID		 1644
1645 /*
1646 * Set the rssi offset.
1647 */
1648 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1649
1650 return 0;
1651}
1652
1653/*
1654 * IEEE80211 stack callback functions.
1655 */
8a3a3c85 1656static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
b3e2130b
JB		 1657 struct ieee80211_vif *vif,
1658 unsigned int link_id, u16 queue,
95ea3627
ID		 1659 const struct ieee80211_tx_queue_params *params)
1660{
1661 struct rt2x00_dev *rt2x00dev = hw->priv;
1662
1663 /*
1664 * We don't support variating cw_min and cw_max variables
1665 * per queue. So by default we only configure the TX queue,
1666 * and ignore all other configurations.
1667 */
e100bb64 1668 if (queue != 0)
95ea3627
ID		 1669 return -EINVAL;
1670
b3e2130b 1671 if (rt2x00mac_conf_tx(hw, vif, link_id, queue, params))
95ea3627
ID		 1672 return -EINVAL;
1673
1674 /*
1675 * Write configuration to register.
1676 */
181d6902
ID		 1677 rt2400pci_config_cw(rt2x00dev,
1678 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1679
1680 return 0;
1681}
1682
37a41b4a
EP		 1683static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1684 struct ieee80211_vif *vif)
95ea3627
ID		 1685{
1686 struct rt2x00_dev *rt2x00dev = hw->priv;
1687 u64 tsf;
1688 u32 reg;
1689
3954b4e3 1690 reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
95ea3627 1691 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
3954b4e3 1692 reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
95ea3627
ID		 1693 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1694
1695 return tsf;
1696}
1697
95ea3627
ID		 1698static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1699{
1700 struct rt2x00_dev *rt2x00dev = hw->priv;
1701 u32 reg;
1702
3954b4e3 1703 reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
95ea3627
ID		 1704 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1705}
1706
1707static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1708 .tx = rt2x00mac_tx,
4150c572
JB		 1709 .start = rt2x00mac_start,
1710 .stop = rt2x00mac_stop,
95ea3627
ID		 1711 .add_interface = rt2x00mac_add_interface,
1712 .remove_interface = rt2x00mac_remove_interface,
1713 .config = rt2x00mac_config,
3a643d24 1714 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 1715 .sw_scan_start = rt2x00mac_sw_scan_start,
1716 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 1717 .get_stats = rt2x00mac_get_stats,
471b3efd 1718 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1719 .conf_tx = rt2400pci_conf_tx,
95ea3627 1720 .get_tsf = rt2400pci_get_tsf,
95ea3627 1721 .tx_last_beacon = rt2400pci_tx_last_beacon,
e47a5cdd 1722 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 1723 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 1724 .set_antenna = rt2x00mac_set_antenna,
1725 .get_antenna = rt2x00mac_get_antenna,
e7dee444 1726 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1727 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 1728};
1729
1730static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1731 .irq_handler = rt2400pci_interrupt,
bcf3cfd0
HS		 1732 .txstatus_tasklet = rt2400pci_txstatus_tasklet,
1733 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1734 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
95ea3627 1735 .probe_hw = rt2400pci_probe_hw,
172c5911
GJ		 1736 .initialize = rt2x00mmio_initialize,
1737 .uninitialize = rt2x00mmio_uninitialize,
798b7adb
ID		 1738 .get_entry_state = rt2400pci_get_entry_state,
1739 .clear_entry = rt2400pci_clear_entry,
95ea3627 1740 .set_device_state = rt2400pci_set_device_state,
95ea3627 1741 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1742 .link_stats = rt2400pci_link_stats,
1743 .reset_tuner = rt2400pci_reset_tuner,
1744 .link_tuner = rt2400pci_link_tuner,
dbba306f
ID		 1745 .start_queue = rt2400pci_start_queue,
1746 .kick_queue = rt2400pci_kick_queue,
1747 .stop_queue = rt2400pci_stop_queue,
172c5911 1748 .flush_queue = rt2x00mmio_flush_queue,
95ea3627 1749 .write_tx_desc = rt2400pci_write_tx_desc,
bd88a781 1750 .write_beacon = rt2400pci_write_beacon,
95ea3627 1751 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1752 .config_filter = rt2400pci_config_filter,
6bb40dd1 1753 .config_intf = rt2400pci_config_intf,
72810379 1754 .config_erp = rt2400pci_config_erp,
e4ea1c40 1755 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1756 .config = rt2400pci_config,
1757};
1758
3d8979ba
GJ		 1759static void rt2400pci_queue_init(struct data_queue *queue)
1760{
1761 switch (queue->qid) {
1762 case QID_RX:
1763 queue->limit = 24;
1764 queue->data_size = DATA_FRAME_SIZE;
1765 queue->desc_size = RXD_DESC_SIZE;
1766 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1767 break;
181d6902 1768
3d8979ba
GJ		 1769 case QID_AC_VO:
1770 case QID_AC_VI:
1771 case QID_AC_BE:
1772 case QID_AC_BK:
1773 queue->limit = 24;
1774 queue->data_size = DATA_FRAME_SIZE;
1775 queue->desc_size = TXD_DESC_SIZE;
1776 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1777 break;
181d6902 1778
3d8979ba
GJ		 1779 case QID_BEACON:
1780 queue->limit = 1;
1781 queue->data_size = MGMT_FRAME_SIZE;
1782 queue->desc_size = TXD_DESC_SIZE;
1783 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1784 break;
181d6902 1785
3d8979ba
GJ		 1786 case QID_ATIM:
1787 queue->limit = 8;
1788 queue->data_size = DATA_FRAME_SIZE;
1789 queue->desc_size = TXD_DESC_SIZE;
1790 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1791 break;
1792
1793 default:
1794 BUG();
1795 break;
1796 }
1797}
181d6902 1798
95ea3627 1799static const struct rt2x00_ops rt2400pci_ops = {
04d0362e 1800 .name = KBUILD_MODNAME,
04d0362e
GW		 1801 .max_ap_intf = 1,
1802 .eeprom_size = EEPROM_SIZE,
1803 .rf_size = RF_SIZE,
1804 .tx_queues = NUM_TX_QUEUES,
3d8979ba 1805 .queue_init = rt2400pci_queue_init,
04d0362e
GW		 1806 .lib = &rt2400pci_rt2x00_ops,
1807 .hw = &rt2400pci_mac80211_ops,
95ea3627 1808#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1809 .debugfs = &rt2400pci_rt2x00debug,
95ea3627
ID		 1810#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1811};
1812
1813/*
1814 * RT2400pci module information.
1815 */
9baa3c34 1816static const struct pci_device_id rt2400pci_device_table[] = {
e01ae27f 1817 { PCI_DEVICE(0x1814, 0x0101) },
95ea3627
ID		 1818 { 0, }
1819};
1820
e01ae27f 1821
95ea3627
ID		 1822MODULE_AUTHOR(DRV_PROJECT);
1823MODULE_VERSION(DRV_VERSION);
1824MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
95ea3627
ID		 1825MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1826MODULE_LICENSE("GPL");
1827
e01ae27f
GW		 1828static int rt2400pci_probe(struct pci_dev *pci_dev,
1829 const struct pci_device_id *id)
1830{
1831 return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1832}
1833
95ea3627 1834static struct pci_driver rt2400pci_driver = {
2360157c 1835 .name = KBUILD_MODNAME,
95ea3627 1836 .id_table = rt2400pci_device_table,
e01ae27f 1837 .probe = rt2400pci_probe,
69202359 1838 .remove = rt2x00pci_remove,
560a218d 1839 .driver.pm = &rt2x00pci_pm_ops,
95ea3627
ID		 1840};
1841
5b0a3b7e 1842module_pci_driver(rt2400pci_driver);
Linux 6.x block layer and io_uring tree(s)