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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Copyright (C) 2002 Intersil Americas Inc. | |
4 | * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org> | |
5 | * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/version.h> | |
23 | #include <linux/module.h> | |
24 | ||
25 | #include <linux/netdevice.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/if_arp.h> | |
30 | ||
31 | #include <asm/io.h> | |
32 | ||
33 | #include "prismcompat.h" | |
34 | #include "isl_38xx.h" | |
35 | #include "isl_ioctl.h" | |
36 | #include "islpci_dev.h" | |
37 | #include "islpci_mgt.h" | |
38 | #include "islpci_eth.h" | |
39 | #include "oid_mgt.h" | |
40 | ||
41 | #define ISL3877_IMAGE_FILE "isl3877" | |
42 | #define ISL3886_IMAGE_FILE "isl3886" | |
43 | #define ISL3890_IMAGE_FILE "isl3890" | |
44 | ||
45 | static int prism54_bring_down(islpci_private *); | |
46 | static int islpci_alloc_memory(islpci_private *); | |
47 | static struct net_device_stats *islpci_statistics(struct net_device *); | |
48 | ||
49 | /* Temporary dummy MAC address to use until firmware is loaded. | |
50 | * The idea there is that some tools (such as nameif) may query | |
51 | * the MAC address before the netdev is 'open'. By using a valid | |
52 | * OUI prefix, they can process the netdev properly. | |
53 | * Of course, this is not the final/real MAC address. It doesn't | |
54 | * matter, as you are suppose to be able to change it anytime via | |
55 | * ndev->set_mac_address. Jean II */ | |
56 | static const unsigned char dummy_mac[6] = { 0x00, 0x30, 0xB4, 0x00, 0x00, 0x00 }; | |
57 | ||
58 | static int | |
59 | isl_upload_firmware(islpci_private *priv) | |
60 | { | |
61 | u32 reg, rc; | |
62 | void __iomem *device_base = priv->device_base; | |
63 | ||
64 | /* clear the RAMBoot and the Reset bit */ | |
65 | reg = readl(device_base + ISL38XX_CTRL_STAT_REG); | |
66 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
67 | reg &= ~ISL38XX_CTRL_STAT_RAMBOOT; | |
68 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
69 | wmb(); | |
70 | udelay(ISL38XX_WRITEIO_DELAY); | |
71 | ||
72 | /* set the Reset bit without reading the register ! */ | |
73 | reg |= ISL38XX_CTRL_STAT_RESET; | |
74 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
75 | wmb(); | |
76 | udelay(ISL38XX_WRITEIO_DELAY); | |
77 | ||
78 | /* clear the Reset bit */ | |
79 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
80 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
81 | wmb(); | |
82 | ||
83 | /* wait a while for the device to reboot */ | |
84 | mdelay(50); | |
85 | ||
86 | { | |
87 | const struct firmware *fw_entry = NULL; | |
88 | long fw_len; | |
89 | const u32 *fw_ptr; | |
90 | ||
91 | rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV); | |
92 | if (rc) { | |
93 | printk(KERN_ERR | |
94 | "%s: request_firmware() failed for '%s'\n", | |
95 | "prism54", priv->firmware); | |
96 | return rc; | |
97 | } | |
98 | /* prepare the Direct Memory Base register */ | |
99 | reg = ISL38XX_DEV_FIRMWARE_ADDRES; | |
100 | ||
101 | fw_ptr = (u32 *) fw_entry->data; | |
102 | fw_len = fw_entry->size; | |
103 | ||
104 | if (fw_len % 4) { | |
105 | printk(KERN_ERR | |
106 | "%s: firmware '%s' size is not multiple of 32bit, aborting!\n", | |
107 | "prism54", priv->firmware); | |
108 | release_firmware(fw_entry); | |
109 | return -EILSEQ; /* Illegal byte sequence */; | |
110 | } | |
111 | ||
112 | while (fw_len > 0) { | |
113 | long _fw_len = | |
114 | (fw_len > | |
115 | ISL38XX_MEMORY_WINDOW_SIZE) ? | |
116 | ISL38XX_MEMORY_WINDOW_SIZE : fw_len; | |
117 | u32 __iomem *dev_fw_ptr = device_base + ISL38XX_DIRECT_MEM_WIN; | |
118 | ||
119 | /* set the cards base address for writting the data */ | |
120 | isl38xx_w32_flush(device_base, reg, | |
121 | ISL38XX_DIR_MEM_BASE_REG); | |
122 | wmb(); /* be paranoid */ | |
123 | ||
124 | /* increment the write address for next iteration */ | |
125 | reg += _fw_len; | |
126 | fw_len -= _fw_len; | |
127 | ||
128 | /* write the data to the Direct Memory Window 32bit-wise */ | |
129 | /* memcpy_toio() doesn't guarantee 32bit writes :-| */ | |
130 | while (_fw_len > 0) { | |
131 | /* use non-swapping writel() */ | |
132 | __raw_writel(*fw_ptr, dev_fw_ptr); | |
133 | fw_ptr++, dev_fw_ptr++; | |
134 | _fw_len -= 4; | |
135 | } | |
136 | ||
137 | /* flush PCI posting */ | |
138 | (void) readl(device_base + ISL38XX_PCI_POSTING_FLUSH); | |
139 | wmb(); /* be paranoid again */ | |
140 | ||
141 | BUG_ON(_fw_len != 0); | |
142 | } | |
143 | ||
144 | BUG_ON(fw_len != 0); | |
145 | ||
146 | /* Firmware version is at offset 40 (also for "newmac") */ | |
147 | printk(KERN_DEBUG "%s: firmware version: %.8s\n", | |
148 | priv->ndev->name, fw_entry->data + 40); | |
149 | ||
150 | release_firmware(fw_entry); | |
151 | } | |
152 | ||
153 | /* now reset the device | |
154 | * clear the Reset & ClkRun bit, set the RAMBoot bit */ | |
155 | reg = readl(device_base + ISL38XX_CTRL_STAT_REG); | |
156 | reg &= ~ISL38XX_CTRL_STAT_CLKRUN; | |
157 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
158 | reg |= ISL38XX_CTRL_STAT_RAMBOOT; | |
159 | isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG); | |
160 | wmb(); | |
161 | udelay(ISL38XX_WRITEIO_DELAY); | |
162 | ||
163 | /* set the reset bit latches the host override and RAMBoot bits | |
164 | * into the device for operation when the reset bit is reset */ | |
165 | reg |= ISL38XX_CTRL_STAT_RESET; | |
166 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
167 | /* don't do flush PCI posting here! */ | |
168 | wmb(); | |
169 | udelay(ISL38XX_WRITEIO_DELAY); | |
170 | ||
171 | /* clear the reset bit should start the whole circus */ | |
172 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
173 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
174 | /* don't do flush PCI posting here! */ | |
175 | wmb(); | |
176 | udelay(ISL38XX_WRITEIO_DELAY); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | /****************************************************************************** | |
182 | Device Interrupt Handler | |
183 | ******************************************************************************/ | |
184 | ||
185 | irqreturn_t | |
186 | islpci_interrupt(int irq, void *config, struct pt_regs *regs) | |
187 | { | |
188 | u32 reg; | |
189 | islpci_private *priv = config; | |
190 | struct net_device *ndev = priv->ndev; | |
191 | void __iomem *device = priv->device_base; | |
192 | int powerstate = ISL38XX_PSM_POWERSAVE_STATE; | |
193 | ||
194 | /* lock the interrupt handler */ | |
195 | spin_lock(&priv->slock); | |
196 | ||
197 | /* received an interrupt request on a shared IRQ line | |
198 | * first check whether the device is in sleep mode */ | |
199 | reg = readl(device + ISL38XX_CTRL_STAT_REG); | |
200 | if (reg & ISL38XX_CTRL_STAT_SLEEPMODE) | |
201 | /* device is in sleep mode, IRQ was generated by someone else */ | |
202 | { | |
203 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
204 | DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n"); | |
205 | #endif | |
206 | spin_unlock(&priv->slock); | |
207 | return IRQ_NONE; | |
208 | } | |
209 | ||
210 | ||
211 | /* check whether there is any source of interrupt on the device */ | |
212 | reg = readl(device + ISL38XX_INT_IDENT_REG); | |
213 | ||
214 | /* also check the contents of the Interrupt Enable Register, because this | |
215 | * will filter out interrupt sources from other devices on the same irq ! */ | |
216 | reg &= readl(device + ISL38XX_INT_EN_REG); | |
217 | reg &= ISL38XX_INT_SOURCES; | |
218 | ||
219 | if (reg != 0) { | |
220 | if (islpci_get_state(priv) != PRV_STATE_SLEEP) | |
221 | powerstate = ISL38XX_PSM_ACTIVE_STATE; | |
222 | ||
223 | /* reset the request bits in the Identification register */ | |
224 | isl38xx_w32_flush(device, reg, ISL38XX_INT_ACK_REG); | |
225 | ||
226 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
227 | DEBUG(SHOW_FUNCTION_CALLS, | |
228 | "IRQ: Identification register 0x%p 0x%x \n", device, reg); | |
229 | #endif | |
230 | ||
231 | /* check for each bit in the register separately */ | |
232 | if (reg & ISL38XX_INT_IDENT_UPDATE) { | |
233 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
234 | /* Queue has been updated */ | |
235 | DEBUG(SHOW_TRACING, "IRQ: Update flag \n"); | |
236 | ||
237 | DEBUG(SHOW_QUEUE_INDEXES, | |
238 | "CB drv Qs: [%i][%i][%i][%i][%i][%i]\n", | |
239 | le32_to_cpu(priv->control_block-> | |
240 | driver_curr_frag[0]), | |
241 | le32_to_cpu(priv->control_block-> | |
242 | driver_curr_frag[1]), | |
243 | le32_to_cpu(priv->control_block-> | |
244 | driver_curr_frag[2]), | |
245 | le32_to_cpu(priv->control_block-> | |
246 | driver_curr_frag[3]), | |
247 | le32_to_cpu(priv->control_block-> | |
248 | driver_curr_frag[4]), | |
249 | le32_to_cpu(priv->control_block-> | |
250 | driver_curr_frag[5]) | |
251 | ); | |
252 | ||
253 | DEBUG(SHOW_QUEUE_INDEXES, | |
254 | "CB dev Qs: [%i][%i][%i][%i][%i][%i]\n", | |
255 | le32_to_cpu(priv->control_block-> | |
256 | device_curr_frag[0]), | |
257 | le32_to_cpu(priv->control_block-> | |
258 | device_curr_frag[1]), | |
259 | le32_to_cpu(priv->control_block-> | |
260 | device_curr_frag[2]), | |
261 | le32_to_cpu(priv->control_block-> | |
262 | device_curr_frag[3]), | |
263 | le32_to_cpu(priv->control_block-> | |
264 | device_curr_frag[4]), | |
265 | le32_to_cpu(priv->control_block-> | |
266 | device_curr_frag[5]) | |
267 | ); | |
268 | #endif | |
269 | ||
270 | /* cleanup the data low transmit queue */ | |
271 | islpci_eth_cleanup_transmit(priv, priv->control_block); | |
272 | ||
273 | /* device is in active state, update the | |
274 | * powerstate flag if necessary */ | |
275 | powerstate = ISL38XX_PSM_ACTIVE_STATE; | |
276 | ||
277 | /* check all three queues in priority order | |
278 | * call the PIMFOR receive function until the | |
279 | * queue is empty */ | |
280 | if (isl38xx_in_queue(priv->control_block, | |
281 | ISL38XX_CB_RX_MGMTQ) != 0) { | |
282 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
283 | DEBUG(SHOW_TRACING, | |
284 | "Received frame in Management Queue\n"); | |
285 | #endif | |
286 | islpci_mgt_receive(ndev); | |
287 | ||
288 | islpci_mgt_cleanup_transmit(ndev); | |
289 | ||
290 | /* Refill slots in receive queue */ | |
291 | islpci_mgmt_rx_fill(ndev); | |
292 | ||
293 | /* no need to trigger the device, next | |
294 | islpci_mgt_transaction does it */ | |
295 | } | |
296 | ||
297 | while (isl38xx_in_queue(priv->control_block, | |
298 | ISL38XX_CB_RX_DATA_LQ) != 0) { | |
299 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
300 | DEBUG(SHOW_TRACING, | |
301 | "Received frame in Data Low Queue \n"); | |
302 | #endif | |
303 | islpci_eth_receive(priv); | |
304 | } | |
305 | ||
306 | /* check whether the data transmit queues were full */ | |
307 | if (priv->data_low_tx_full) { | |
308 | /* check whether the transmit is not full anymore */ | |
309 | if (ISL38XX_CB_TX_QSIZE - | |
310 | isl38xx_in_queue(priv->control_block, | |
311 | ISL38XX_CB_TX_DATA_LQ) >= | |
312 | ISL38XX_MIN_QTHRESHOLD) { | |
313 | /* nope, the driver is ready for more network frames */ | |
314 | netif_wake_queue(priv->ndev); | |
315 | ||
316 | /* reset the full flag */ | |
317 | priv->data_low_tx_full = 0; | |
318 | } | |
319 | } | |
320 | } | |
321 | ||
322 | if (reg & ISL38XX_INT_IDENT_INIT) { | |
323 | /* Device has been initialized */ | |
324 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
325 | DEBUG(SHOW_TRACING, | |
326 | "IRQ: Init flag, device initialized \n"); | |
327 | #endif | |
328 | wake_up(&priv->reset_done); | |
329 | } | |
330 | ||
331 | if (reg & ISL38XX_INT_IDENT_SLEEP) { | |
332 | /* Device intends to move to powersave state */ | |
333 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
334 | DEBUG(SHOW_TRACING, "IRQ: Sleep flag \n"); | |
335 | #endif | |
336 | isl38xx_handle_sleep_request(priv->control_block, | |
337 | &powerstate, | |
338 | priv->device_base); | |
339 | } | |
340 | ||
341 | if (reg & ISL38XX_INT_IDENT_WAKEUP) { | |
342 | /* Device has been woken up to active state */ | |
343 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
344 | DEBUG(SHOW_TRACING, "IRQ: Wakeup flag \n"); | |
345 | #endif | |
346 | ||
347 | isl38xx_handle_wakeup(priv->control_block, | |
348 | &powerstate, priv->device_base); | |
349 | } | |
350 | } else { | |
351 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
352 | DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n"); | |
353 | #endif | |
354 | spin_unlock(&priv->slock); | |
355 | return IRQ_NONE; | |
356 | } | |
357 | ||
358 | /* sleep -> ready */ | |
359 | if (islpci_get_state(priv) == PRV_STATE_SLEEP | |
360 | && powerstate == ISL38XX_PSM_ACTIVE_STATE) | |
361 | islpci_set_state(priv, PRV_STATE_READY); | |
362 | ||
363 | /* !sleep -> sleep */ | |
364 | if (islpci_get_state(priv) != PRV_STATE_SLEEP | |
365 | && powerstate == ISL38XX_PSM_POWERSAVE_STATE) | |
366 | islpci_set_state(priv, PRV_STATE_SLEEP); | |
367 | ||
368 | /* unlock the interrupt handler */ | |
369 | spin_unlock(&priv->slock); | |
370 | ||
371 | return IRQ_HANDLED; | |
372 | } | |
373 | ||
374 | /****************************************************************************** | |
375 | Network Interface Control & Statistical functions | |
376 | ******************************************************************************/ | |
377 | static int | |
378 | islpci_open(struct net_device *ndev) | |
379 | { | |
380 | u32 rc; | |
381 | islpci_private *priv = netdev_priv(ndev); | |
382 | ||
383 | /* reset data structures, upload firmware and reset device */ | |
384 | rc = islpci_reset(priv,1); | |
385 | if (rc) { | |
386 | prism54_bring_down(priv); | |
387 | return rc; /* Returns informative message */ | |
388 | } | |
389 | ||
390 | netif_start_queue(ndev); | |
391 | /* netif_mark_up( ndev ); */ | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | static int | |
397 | islpci_close(struct net_device *ndev) | |
398 | { | |
399 | islpci_private *priv = netdev_priv(ndev); | |
400 | ||
401 | printk(KERN_DEBUG "%s: islpci_close ()\n", ndev->name); | |
402 | ||
403 | netif_stop_queue(ndev); | |
404 | ||
405 | return prism54_bring_down(priv); | |
406 | } | |
407 | ||
408 | static int | |
409 | prism54_bring_down(islpci_private *priv) | |
410 | { | |
411 | void __iomem *device_base = priv->device_base; | |
412 | u32 reg; | |
413 | /* we are going to shutdown the device */ | |
414 | islpci_set_state(priv, PRV_STATE_PREBOOT); | |
415 | ||
416 | /* disable all device interrupts in case they weren't */ | |
417 | isl38xx_disable_interrupts(priv->device_base); | |
418 | ||
419 | /* For safety reasons, we may want to ensure that no DMA transfer is | |
420 | * currently in progress by emptying the TX and RX queues. */ | |
421 | ||
422 | /* wait until interrupts have finished executing on other CPUs */ | |
423 | synchronize_irq(priv->pdev->irq); | |
424 | ||
425 | reg = readl(device_base + ISL38XX_CTRL_STAT_REG); | |
426 | reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT); | |
427 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
428 | wmb(); | |
429 | udelay(ISL38XX_WRITEIO_DELAY); | |
430 | ||
431 | reg |= ISL38XX_CTRL_STAT_RESET; | |
432 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
433 | wmb(); | |
434 | udelay(ISL38XX_WRITEIO_DELAY); | |
435 | ||
436 | /* clear the Reset bit */ | |
437 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
438 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
439 | wmb(); | |
440 | ||
441 | /* wait a while for the device to reset */ | |
442 | set_current_state(TASK_UNINTERRUPTIBLE); | |
443 | schedule_timeout(50*HZ/1000); | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
448 | static int | |
449 | islpci_upload_fw(islpci_private *priv) | |
450 | { | |
451 | islpci_state_t old_state; | |
452 | u32 rc; | |
453 | ||
454 | old_state = islpci_set_state(priv, PRV_STATE_BOOT); | |
455 | ||
456 | printk(KERN_DEBUG "%s: uploading firmware...\n", priv->ndev->name); | |
457 | ||
458 | rc = isl_upload_firmware(priv); | |
459 | if (rc) { | |
460 | /* error uploading the firmware */ | |
461 | printk(KERN_ERR "%s: could not upload firmware ('%s')\n", | |
462 | priv->ndev->name, priv->firmware); | |
463 | ||
464 | islpci_set_state(priv, old_state); | |
465 | return rc; | |
466 | } | |
467 | ||
468 | printk(KERN_DEBUG "%s: firmware upload complete\n", | |
469 | priv->ndev->name); | |
470 | ||
471 | islpci_set_state(priv, PRV_STATE_POSTBOOT); | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | static int | |
477 | islpci_reset_if(islpci_private *priv) | |
478 | { | |
479 | long remaining; | |
480 | int result = -ETIME; | |
481 | int count; | |
482 | ||
483 | DEFINE_WAIT(wait); | |
484 | prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE); | |
485 | ||
486 | /* now the last step is to reset the interface */ | |
487 | isl38xx_interface_reset(priv->device_base, priv->device_host_address); | |
488 | islpci_set_state(priv, PRV_STATE_PREINIT); | |
489 | ||
490 | for(count = 0; count < 2 && result; count++) { | |
491 | /* The software reset acknowledge needs about 220 msec here. | |
492 | * Be conservative and wait for up to one second. */ | |
493 | ||
494 | set_current_state(TASK_UNINTERRUPTIBLE); | |
495 | remaining = schedule_timeout(HZ); | |
496 | ||
497 | if(remaining > 0) { | |
498 | result = 0; | |
499 | break; | |
500 | } | |
501 | ||
502 | /* If we're here it's because our IRQ hasn't yet gone through. | |
503 | * Retry a bit more... | |
504 | */ | |
505 | printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n", | |
506 | priv->ndev->name); | |
507 | } | |
508 | ||
509 | finish_wait(&priv->reset_done, &wait); | |
510 | ||
511 | if (result) { | |
512 | printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name); | |
513 | return result; | |
514 | } | |
515 | ||
516 | islpci_set_state(priv, PRV_STATE_INIT); | |
517 | ||
518 | /* Now that the device is 100% up, let's allow | |
519 | * for the other interrupts -- | |
520 | * NOTE: this is not *yet* true since we've only allowed the | |
521 | * INIT interrupt on the IRQ line. We can perhaps poll | |
522 | * the IRQ line until we know for sure the reset went through */ | |
523 | isl38xx_enable_common_interrupts(priv->device_base); | |
524 | ||
525 | down_write(&priv->mib_sem); | |
526 | result = mgt_commit(priv); | |
527 | if (result) { | |
528 | printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name); | |
529 | up_write(&priv->mib_sem); | |
530 | return result; | |
531 | } | |
532 | up_write(&priv->mib_sem); | |
533 | ||
534 | islpci_set_state(priv, PRV_STATE_READY); | |
535 | ||
536 | printk(KERN_DEBUG "%s: interface reset complete\n", priv->ndev->name); | |
537 | return 0; | |
538 | } | |
539 | ||
540 | int | |
541 | islpci_reset(islpci_private *priv, int reload_firmware) | |
542 | { | |
543 | isl38xx_control_block *cb = /* volatile not needed */ | |
544 | (isl38xx_control_block *) priv->control_block; | |
545 | unsigned counter; | |
546 | int rc; | |
547 | ||
548 | if (reload_firmware) | |
549 | islpci_set_state(priv, PRV_STATE_PREBOOT); | |
550 | else | |
551 | islpci_set_state(priv, PRV_STATE_POSTBOOT); | |
552 | ||
553 | printk(KERN_DEBUG "%s: resetting device...\n", priv->ndev->name); | |
554 | ||
555 | /* disable all device interrupts in case they weren't */ | |
556 | isl38xx_disable_interrupts(priv->device_base); | |
557 | ||
558 | /* flush all management queues */ | |
559 | priv->index_mgmt_tx = 0; | |
560 | priv->index_mgmt_rx = 0; | |
561 | ||
562 | /* clear the indexes in the frame pointer */ | |
563 | for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) { | |
564 | cb->driver_curr_frag[counter] = cpu_to_le32(0); | |
565 | cb->device_curr_frag[counter] = cpu_to_le32(0); | |
566 | } | |
567 | ||
568 | /* reset the mgmt receive queue */ | |
569 | for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) { | |
570 | isl38xx_fragment *frag = &cb->rx_data_mgmt[counter]; | |
571 | frag->size = cpu_to_le16(MGMT_FRAME_SIZE); | |
572 | frag->flags = 0; | |
573 | frag->address = cpu_to_le32(priv->mgmt_rx[counter].pci_addr); | |
574 | } | |
575 | ||
576 | for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { | |
577 | cb->rx_data_low[counter].address = | |
578 | cpu_to_le32((u32) priv->pci_map_rx_address[counter]); | |
579 | } | |
580 | ||
581 | /* since the receive queues are filled with empty fragments, now we can | |
582 | * set the corresponding indexes in the Control Block */ | |
583 | priv->control_block->driver_curr_frag[ISL38XX_CB_RX_DATA_LQ] = | |
584 | cpu_to_le32(ISL38XX_CB_RX_QSIZE); | |
585 | priv->control_block->driver_curr_frag[ISL38XX_CB_RX_MGMTQ] = | |
586 | cpu_to_le32(ISL38XX_CB_MGMT_QSIZE); | |
587 | ||
588 | /* reset the remaining real index registers and full flags */ | |
589 | priv->free_data_rx = 0; | |
590 | priv->free_data_tx = 0; | |
591 | priv->data_low_tx_full = 0; | |
592 | ||
593 | if (reload_firmware) { /* Should we load the firmware ? */ | |
594 | /* now that the data structures are cleaned up, upload | |
595 | * firmware and reset interface */ | |
596 | rc = islpci_upload_fw(priv); | |
597 | if (rc) { | |
598 | printk(KERN_ERR "%s: islpci_reset: failure\n", | |
599 | priv->ndev->name); | |
600 | return rc; | |
601 | } | |
602 | } | |
603 | ||
604 | /* finally reset interface */ | |
605 | rc = islpci_reset_if(priv); | |
606 | if (rc) | |
607 | printk(KERN_ERR "prism54: Your card/socket may be faulty, or IRQ line too busy :(\n"); | |
608 | return rc; | |
609 | } | |
610 | ||
611 | static struct net_device_stats * | |
612 | islpci_statistics(struct net_device *ndev) | |
613 | { | |
614 | islpci_private *priv = netdev_priv(ndev); | |
615 | ||
616 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
617 | DEBUG(SHOW_FUNCTION_CALLS, "islpci_statistics\n"); | |
618 | #endif | |
619 | ||
620 | return &priv->statistics; | |
621 | } | |
622 | ||
623 | /****************************************************************************** | |
624 | Network device configuration functions | |
625 | ******************************************************************************/ | |
626 | static int | |
627 | islpci_alloc_memory(islpci_private *priv) | |
628 | { | |
629 | int counter; | |
630 | ||
631 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
632 | printk(KERN_DEBUG "islpci_alloc_memory\n"); | |
633 | #endif | |
634 | ||
635 | /* remap the PCI device base address to accessable */ | |
636 | if (!(priv->device_base = | |
637 | ioremap(pci_resource_start(priv->pdev, 0), | |
638 | ISL38XX_PCI_MEM_SIZE))) { | |
639 | /* error in remapping the PCI device memory address range */ | |
640 | printk(KERN_ERR "PCI memory remapping failed \n"); | |
641 | return -1; | |
642 | } | |
643 | ||
644 | /* memory layout for consistent DMA region: | |
645 | * | |
646 | * Area 1: Control Block for the device interface | |
647 | * Area 2: Power Save Mode Buffer for temporary frame storage. Be aware that | |
648 | * the number of supported stations in the AP determines the minimal | |
649 | * size of the buffer ! | |
650 | */ | |
651 | ||
652 | /* perform the allocation */ | |
653 | priv->driver_mem_address = pci_alloc_consistent(priv->pdev, | |
654 | HOST_MEM_BLOCK, | |
655 | &priv-> | |
656 | device_host_address); | |
657 | ||
658 | if (!priv->driver_mem_address) { | |
659 | /* error allocating the block of PCI memory */ | |
660 | printk(KERN_ERR "%s: could not allocate DMA memory, aborting!", | |
661 | "prism54"); | |
662 | return -1; | |
663 | } | |
664 | ||
665 | /* assign the Control Block to the first address of the allocated area */ | |
666 | priv->control_block = | |
667 | (isl38xx_control_block *) priv->driver_mem_address; | |
668 | ||
669 | /* set the Power Save Buffer pointer directly behind the CB */ | |
670 | priv->device_psm_buffer = | |
671 | priv->device_host_address + CONTROL_BLOCK_SIZE; | |
672 | ||
673 | /* make sure all buffer pointers are initialized */ | |
674 | for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) { | |
675 | priv->control_block->driver_curr_frag[counter] = cpu_to_le32(0); | |
676 | priv->control_block->device_curr_frag[counter] = cpu_to_le32(0); | |
677 | } | |
678 | ||
679 | priv->index_mgmt_rx = 0; | |
680 | memset(priv->mgmt_rx, 0, sizeof(priv->mgmt_rx)); | |
681 | memset(priv->mgmt_tx, 0, sizeof(priv->mgmt_tx)); | |
682 | ||
683 | /* allocate rx queue for management frames */ | |
684 | if (islpci_mgmt_rx_fill(priv->ndev) < 0) | |
685 | goto out_free; | |
686 | ||
687 | /* now get the data rx skb's */ | |
688 | memset(priv->data_low_rx, 0, sizeof (priv->data_low_rx)); | |
689 | memset(priv->pci_map_rx_address, 0, sizeof (priv->pci_map_rx_address)); | |
690 | ||
691 | for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { | |
692 | struct sk_buff *skb; | |
693 | ||
694 | /* allocate an sk_buff for received data frames storage | |
695 | * each frame on receive size consists of 1 fragment | |
696 | * include any required allignment operations */ | |
697 | if (!(skb = dev_alloc_skb(MAX_FRAGMENT_SIZE_RX + 2))) { | |
698 | /* error allocating an sk_buff structure elements */ | |
699 | printk(KERN_ERR "Error allocating skb.\n"); | |
700 | skb = NULL; | |
701 | goto out_free; | |
702 | } | |
703 | skb_reserve(skb, (4 - (long) skb->data) & 0x03); | |
704 | /* add the new allocated sk_buff to the buffer array */ | |
705 | priv->data_low_rx[counter] = skb; | |
706 | ||
707 | /* map the allocated skb data area to pci */ | |
708 | priv->pci_map_rx_address[counter] = | |
709 | pci_map_single(priv->pdev, (void *) skb->data, | |
710 | MAX_FRAGMENT_SIZE_RX + 2, | |
711 | PCI_DMA_FROMDEVICE); | |
712 | if (!priv->pci_map_rx_address[counter]) { | |
713 | /* error mapping the buffer to device | |
714 | accessable memory address */ | |
715 | printk(KERN_ERR "failed to map skb DMA'able\n"); | |
716 | goto out_free; | |
717 | } | |
718 | } | |
719 | ||
720 | prism54_acl_init(&priv->acl); | |
721 | prism54_wpa_ie_init(priv); | |
722 | if (mgt_init(priv)) | |
723 | goto out_free; | |
724 | ||
725 | return 0; | |
726 | out_free: | |
727 | islpci_free_memory(priv); | |
728 | return -1; | |
729 | } | |
730 | ||
731 | int | |
732 | islpci_free_memory(islpci_private *priv) | |
733 | { | |
734 | int counter; | |
735 | ||
736 | if (priv->device_base) | |
737 | iounmap(priv->device_base); | |
738 | priv->device_base = NULL; | |
739 | ||
740 | /* free consistent DMA area... */ | |
741 | if (priv->driver_mem_address) | |
742 | pci_free_consistent(priv->pdev, HOST_MEM_BLOCK, | |
743 | priv->driver_mem_address, | |
744 | priv->device_host_address); | |
745 | ||
746 | /* clear some dangling pointers */ | |
747 | priv->driver_mem_address = NULL; | |
748 | priv->device_host_address = 0; | |
749 | priv->device_psm_buffer = 0; | |
750 | priv->control_block = NULL; | |
751 | ||
752 | /* clean up mgmt rx buffers */ | |
753 | for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) { | |
754 | struct islpci_membuf *buf = &priv->mgmt_rx[counter]; | |
755 | if (buf->pci_addr) | |
756 | pci_unmap_single(priv->pdev, buf->pci_addr, | |
757 | buf->size, PCI_DMA_FROMDEVICE); | |
758 | buf->pci_addr = 0; | |
759 | if (buf->mem) | |
760 | kfree(buf->mem); | |
761 | buf->size = 0; | |
762 | buf->mem = NULL; | |
763 | } | |
764 | ||
765 | /* clean up data rx buffers */ | |
766 | for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { | |
767 | if (priv->pci_map_rx_address[counter]) | |
768 | pci_unmap_single(priv->pdev, | |
769 | priv->pci_map_rx_address[counter], | |
770 | MAX_FRAGMENT_SIZE_RX + 2, | |
771 | PCI_DMA_FROMDEVICE); | |
772 | priv->pci_map_rx_address[counter] = 0; | |
773 | ||
774 | if (priv->data_low_rx[counter]) | |
775 | dev_kfree_skb(priv->data_low_rx[counter]); | |
776 | priv->data_low_rx[counter] = NULL; | |
777 | } | |
778 | ||
779 | /* Free the acces control list and the WPA list */ | |
780 | prism54_acl_clean(&priv->acl); | |
781 | prism54_wpa_ie_clean(priv); | |
782 | mgt_clean(priv); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
787 | #if 0 | |
788 | static void | |
789 | islpci_set_multicast_list(struct net_device *dev) | |
790 | { | |
791 | /* put device into promisc mode and let network layer handle it */ | |
792 | } | |
793 | #endif | |
794 | ||
795 | struct net_device * | |
796 | islpci_setup(struct pci_dev *pdev) | |
797 | { | |
798 | islpci_private *priv; | |
799 | struct net_device *ndev = alloc_etherdev(sizeof (islpci_private)); | |
800 | ||
801 | if (!ndev) | |
802 | return ndev; | |
803 | ||
804 | SET_MODULE_OWNER(ndev); | |
805 | pci_set_drvdata(pdev, ndev); | |
806 | #if defined(SET_NETDEV_DEV) | |
807 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
808 | #endif | |
809 | ||
810 | /* setup the structure members */ | |
811 | ndev->base_addr = pci_resource_start(pdev, 0); | |
812 | ndev->irq = pdev->irq; | |
813 | ||
814 | /* initialize the function pointers */ | |
815 | ndev->open = &islpci_open; | |
816 | ndev->stop = &islpci_close; | |
817 | ndev->get_stats = &islpci_statistics; | |
818 | ndev->get_wireless_stats = &prism54_get_wireless_stats; | |
819 | ndev->do_ioctl = &prism54_ioctl; | |
820 | ndev->wireless_handlers = | |
821 | (struct iw_handler_def *) &prism54_handler_def; | |
822 | ||
823 | ndev->hard_start_xmit = &islpci_eth_transmit; | |
824 | /* ndev->set_multicast_list = &islpci_set_multicast_list; */ | |
825 | ndev->addr_len = ETH_ALEN; | |
826 | ndev->set_mac_address = &prism54_set_mac_address; | |
827 | /* Get a non-zero dummy MAC address for nameif. Jean II */ | |
828 | memcpy(ndev->dev_addr, dummy_mac, 6); | |
829 | ||
830 | #ifdef HAVE_TX_TIMEOUT | |
831 | ndev->watchdog_timeo = ISLPCI_TX_TIMEOUT; | |
832 | ndev->tx_timeout = &islpci_eth_tx_timeout; | |
833 | #endif | |
834 | ||
835 | /* allocate a private device structure to the network device */ | |
836 | priv = netdev_priv(ndev); | |
837 | priv->ndev = ndev; | |
838 | priv->pdev = pdev; | |
839 | priv->monitor_type = ARPHRD_IEEE80211; | |
840 | priv->ndev->type = (priv->iw_mode == IW_MODE_MONITOR) ? | |
841 | priv->monitor_type : ARPHRD_ETHER; | |
842 | ||
843 | #if WIRELESS_EXT > 16 | |
844 | /* Add pointers to enable iwspy support. */ | |
845 | priv->wireless_data.spy_data = &priv->spy_data; | |
846 | ndev->wireless_data = &priv->wireless_data; | |
847 | #endif /* WIRELESS_EXT > 16 */ | |
848 | ||
849 | /* save the start and end address of the PCI memory area */ | |
850 | ndev->mem_start = (unsigned long) priv->device_base; | |
851 | ndev->mem_end = ndev->mem_start + ISL38XX_PCI_MEM_SIZE; | |
852 | ||
853 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
854 | DEBUG(SHOW_TRACING, "PCI Memory remapped to 0x%p\n", priv->device_base); | |
855 | #endif | |
856 | ||
857 | init_waitqueue_head(&priv->reset_done); | |
858 | ||
859 | /* init the queue read locks, process wait counter */ | |
860 | sema_init(&priv->mgmt_sem, 1); | |
861 | priv->mgmt_received = NULL; | |
862 | init_waitqueue_head(&priv->mgmt_wqueue); | |
863 | sema_init(&priv->stats_sem, 1); | |
864 | spin_lock_init(&priv->slock); | |
865 | ||
866 | /* init state machine with off#1 state */ | |
867 | priv->state = PRV_STATE_OFF; | |
868 | priv->state_off = 1; | |
869 | ||
870 | /* initialize workqueue's */ | |
871 | INIT_WORK(&priv->stats_work, | |
872 | (void (*)(void *)) prism54_update_stats, priv); | |
873 | priv->stats_timestamp = 0; | |
874 | ||
875 | INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake, priv); | |
876 | priv->reset_task_pending = 0; | |
877 | ||
878 | /* allocate various memory areas */ | |
879 | if (islpci_alloc_memory(priv)) | |
880 | goto do_free_netdev; | |
881 | ||
882 | /* select the firmware file depending on the device id */ | |
883 | switch (pdev->device) { | |
884 | case 0x3877: | |
885 | strcpy(priv->firmware, ISL3877_IMAGE_FILE); | |
886 | break; | |
887 | ||
888 | case 0x3886: | |
889 | strcpy(priv->firmware, ISL3886_IMAGE_FILE); | |
890 | break; | |
891 | ||
892 | default: | |
893 | strcpy(priv->firmware, ISL3890_IMAGE_FILE); | |
894 | break; | |
895 | } | |
896 | ||
897 | if (register_netdev(ndev)) { | |
898 | DEBUG(SHOW_ERROR_MESSAGES, | |
899 | "ERROR: register_netdev() failed \n"); | |
900 | goto do_islpci_free_memory; | |
901 | } | |
902 | ||
903 | return ndev; | |
904 | ||
905 | do_islpci_free_memory: | |
906 | islpci_free_memory(priv); | |
907 | do_free_netdev: | |
908 | pci_set_drvdata(pdev, NULL); | |
909 | free_netdev(ndev); | |
910 | priv = NULL; | |
911 | return NULL; | |
912 | } | |
913 | ||
914 | islpci_state_t | |
915 | islpci_set_state(islpci_private *priv, islpci_state_t new_state) | |
916 | { | |
917 | islpci_state_t old_state; | |
918 | ||
919 | /* lock */ | |
920 | old_state = priv->state; | |
921 | ||
922 | /* this means either a race condition or some serious error in | |
923 | * the driver code */ | |
924 | switch (new_state) { | |
925 | case PRV_STATE_OFF: | |
926 | priv->state_off++; | |
927 | default: | |
928 | priv->state = new_state; | |
929 | break; | |
930 | ||
931 | case PRV_STATE_PREBOOT: | |
932 | /* there are actually many off-states, enumerated by | |
933 | * state_off */ | |
934 | if (old_state == PRV_STATE_OFF) | |
935 | priv->state_off--; | |
936 | ||
937 | /* only if hw_unavailable is zero now it means we either | |
938 | * were in off#1 state, or came here from | |
939 | * somewhere else */ | |
940 | if (!priv->state_off) | |
941 | priv->state = new_state; | |
942 | break; | |
943 | }; | |
944 | #if 0 | |
945 | printk(KERN_DEBUG "%s: state transition %d -> %d (off#%d)\n", | |
946 | priv->ndev->name, old_state, new_state, priv->state_off); | |
947 | #endif | |
948 | ||
949 | /* invariants */ | |
950 | BUG_ON(priv->state_off < 0); | |
951 | BUG_ON(priv->state_off && (priv->state != PRV_STATE_OFF)); | |
952 | BUG_ON(!priv->state_off && (priv->state == PRV_STATE_OFF)); | |
953 | ||
954 | /* unlock */ | |
955 | return old_state; | |
956 | } |