Commit | Line | Data |
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cd8d3d32 CL |
1 | /* |
2 | * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de> | |
3 | * Copyright 2008 Johannes Berg <johannes@sipsolutions.net> | |
4 | * | |
5 | * This driver is a port from stlc45xx: | |
6 | * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies). | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/firmware.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/spi/spi.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/gpio.h> | |
32 | ||
33 | #include "p54spi.h" | |
34 | #include "p54spi_eeprom.h" | |
35 | #include "p54.h" | |
36 | ||
d8c92107 | 37 | #include "lmac.h" |
cd8d3d32 CL |
38 | |
39 | MODULE_FIRMWARE("3826.arm"); | |
40 | MODULE_ALIAS("stlc45xx"); | |
41 | ||
a2116993 CL |
42 | /* |
43 | * gpios should be handled in board files and provided via platform data, | |
44 | * but because it's currently impossible for p54spi to have a header file | |
45 | * in include/linux, let's use module paramaters for now | |
46 | */ | |
47 | ||
48 | static int p54spi_gpio_power = 97; | |
49 | module_param(p54spi_gpio_power, int, 0444); | |
50 | MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line"); | |
51 | ||
52 | static int p54spi_gpio_irq = 87; | |
53 | module_param(p54spi_gpio_irq, int, 0444); | |
54 | MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line"); | |
55 | ||
cd8d3d32 CL |
56 | static void p54spi_spi_read(struct p54s_priv *priv, u8 address, |
57 | void *buf, size_t len) | |
58 | { | |
59 | struct spi_transfer t[2]; | |
60 | struct spi_message m; | |
61 | __le16 addr; | |
62 | ||
63 | /* We first push the address */ | |
64 | addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15); | |
65 | ||
66 | spi_message_init(&m); | |
67 | memset(t, 0, sizeof(t)); | |
68 | ||
69 | t[0].tx_buf = &addr; | |
70 | t[0].len = sizeof(addr); | |
71 | spi_message_add_tail(&t[0], &m); | |
72 | ||
73 | t[1].rx_buf = buf; | |
74 | t[1].len = len; | |
75 | spi_message_add_tail(&t[1], &m); | |
76 | ||
77 | spi_sync(priv->spi, &m); | |
78 | } | |
79 | ||
80 | ||
81 | static void p54spi_spi_write(struct p54s_priv *priv, u8 address, | |
82 | const void *buf, size_t len) | |
83 | { | |
84 | struct spi_transfer t[3]; | |
85 | struct spi_message m; | |
86 | __le16 addr; | |
87 | ||
88 | /* We first push the address */ | |
89 | addr = cpu_to_le16(address << 8); | |
90 | ||
91 | spi_message_init(&m); | |
92 | memset(t, 0, sizeof(t)); | |
93 | ||
94 | t[0].tx_buf = &addr; | |
95 | t[0].len = sizeof(addr); | |
96 | spi_message_add_tail(&t[0], &m); | |
97 | ||
98 | t[1].tx_buf = buf; | |
69712e92 | 99 | t[1].len = len & ~1; |
cd8d3d32 CL |
100 | spi_message_add_tail(&t[1], &m); |
101 | ||
102 | if (len % 2) { | |
103 | __le16 last_word; | |
104 | last_word = cpu_to_le16(((u8 *)buf)[len - 1]); | |
105 | ||
106 | t[2].tx_buf = &last_word; | |
107 | t[2].len = sizeof(last_word); | |
108 | spi_message_add_tail(&t[2], &m); | |
109 | } | |
110 | ||
111 | spi_sync(priv->spi, &m); | |
112 | } | |
113 | ||
cd8d3d32 CL |
114 | static u32 p54spi_read32(struct p54s_priv *priv, u8 addr) |
115 | { | |
116 | __le32 val; | |
117 | ||
118 | p54spi_spi_read(priv, addr, &val, sizeof(val)); | |
119 | ||
120 | return le32_to_cpu(val); | |
121 | } | |
122 | ||
123 | static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val) | |
124 | { | |
125 | p54spi_spi_write(priv, addr, &val, sizeof(val)); | |
126 | } | |
127 | ||
128 | static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val) | |
129 | { | |
130 | p54spi_spi_write(priv, addr, &val, sizeof(val)); | |
131 | } | |
132 | ||
a7eee06b | 133 | static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits) |
cd8d3d32 CL |
134 | { |
135 | int i; | |
cd8d3d32 CL |
136 | |
137 | for (i = 0; i < 2000; i++) { | |
a7eee06b | 138 | u32 buffer = p54spi_read32(priv, reg); |
f74d0f5c | 139 | if ((buffer & bits) == bits) |
cd8d3d32 | 140 | return 1; |
cd8d3d32 CL |
141 | } |
142 | return 0; | |
143 | } | |
144 | ||
4f5cab96 MF |
145 | static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base, |
146 | const void *buf, size_t len) | |
147 | { | |
a7eee06b | 148 | if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) { |
4f5cab96 | 149 | dev_err(&priv->spi->dev, "spi_write_dma not allowed " |
87cbfd06 | 150 | "to DMA write.\n"); |
4f5cab96 MF |
151 | return -EAGAIN; |
152 | } | |
153 | ||
210dd1bb MF |
154 | p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL, |
155 | cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE)); | |
156 | ||
4f5cab96 MF |
157 | p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len)); |
158 | p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base); | |
159 | p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len); | |
160 | return 0; | |
161 | } | |
162 | ||
cd8d3d32 CL |
163 | static int p54spi_request_firmware(struct ieee80211_hw *dev) |
164 | { | |
165 | struct p54s_priv *priv = dev->priv; | |
166 | int ret; | |
167 | ||
168 | /* FIXME: should driver use it's own struct device? */ | |
169 | ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev); | |
170 | ||
171 | if (ret < 0) { | |
172 | dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret); | |
173 | return ret; | |
174 | } | |
175 | ||
176 | ret = p54_parse_firmware(dev, priv->firmware); | |
177 | if (ret) { | |
178 | release_firmware(priv->firmware); | |
179 | return ret; | |
180 | } | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static int p54spi_request_eeprom(struct ieee80211_hw *dev) | |
186 | { | |
187 | struct p54s_priv *priv = dev->priv; | |
188 | const struct firmware *eeprom; | |
189 | int ret; | |
190 | ||
191 | /* | |
192 | * allow users to customize their eeprom. | |
193 | */ | |
194 | ||
195 | ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev); | |
196 | if (ret < 0) { | |
197 | dev_info(&priv->spi->dev, "loading default eeprom...\n"); | |
198 | ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom, | |
199 | sizeof(p54spi_eeprom)); | |
200 | } else { | |
201 | dev_info(&priv->spi->dev, "loading user eeprom...\n"); | |
202 | ret = p54_parse_eeprom(dev, (void *) eeprom->data, | |
203 | (int)eeprom->size); | |
204 | release_firmware(eeprom); | |
205 | } | |
206 | return ret; | |
207 | } | |
208 | ||
209 | static int p54spi_upload_firmware(struct ieee80211_hw *dev) | |
210 | { | |
211 | struct p54s_priv *priv = dev->priv; | |
5e3af1d2 MF |
212 | unsigned long fw_len, _fw_len; |
213 | unsigned int offset = 0; | |
214 | int err = 0; | |
215 | u8 *fw; | |
216 | ||
217 | fw_len = priv->firmware->size; | |
218 | fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL); | |
219 | if (!fw) | |
220 | return -ENOMEM; | |
cd8d3d32 CL |
221 | |
222 | /* stop the device */ | |
223 | p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( | |
224 | SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET | | |
225 | SPI_CTRL_STAT_START_HALTED)); | |
226 | ||
227 | msleep(TARGET_BOOT_SLEEP); | |
228 | ||
229 | p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( | |
230 | SPI_CTRL_STAT_HOST_OVERRIDE | | |
231 | SPI_CTRL_STAT_START_HALTED)); | |
232 | ||
233 | msleep(TARGET_BOOT_SLEEP); | |
234 | ||
cd8d3d32 CL |
235 | while (fw_len > 0) { |
236 | _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE); | |
237 | ||
4f5cab96 MF |
238 | err = p54spi_spi_write_dma(priv, cpu_to_le32( |
239 | ISL38XX_DEV_FIRMWARE_ADDR + offset), | |
240 | (fw + offset), _fw_len); | |
241 | if (err < 0) | |
5e3af1d2 | 242 | goto out; |
cd8d3d32 CL |
243 | |
244 | fw_len -= _fw_len; | |
5e3af1d2 | 245 | offset += _fw_len; |
cd8d3d32 CL |
246 | } |
247 | ||
248 | BUG_ON(fw_len != 0); | |
249 | ||
250 | /* enable host interrupts */ | |
251 | p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, | |
252 | cpu_to_le32(SPI_HOST_INTS_DEFAULT)); | |
253 | ||
254 | /* boot the device */ | |
255 | p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( | |
256 | SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET | | |
257 | SPI_CTRL_STAT_RAM_BOOT)); | |
258 | ||
259 | msleep(TARGET_BOOT_SLEEP); | |
260 | ||
261 | p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( | |
262 | SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT)); | |
263 | msleep(TARGET_BOOT_SLEEP); | |
5e3af1d2 MF |
264 | |
265 | out: | |
266 | kfree(fw); | |
267 | return err; | |
cd8d3d32 CL |
268 | } |
269 | ||
270 | static void p54spi_power_off(struct p54s_priv *priv) | |
271 | { | |
a2116993 CL |
272 | disable_irq(gpio_to_irq(p54spi_gpio_irq)); |
273 | gpio_set_value(p54spi_gpio_power, 0); | |
cd8d3d32 CL |
274 | } |
275 | ||
276 | static void p54spi_power_on(struct p54s_priv *priv) | |
277 | { | |
a2116993 CL |
278 | gpio_set_value(p54spi_gpio_power, 1); |
279 | enable_irq(gpio_to_irq(p54spi_gpio_irq)); | |
cd8d3d32 CL |
280 | |
281 | /* | |
282 | * need to wait a while before device can be accessed, the lenght | |
283 | * is just a guess | |
284 | */ | |
285 | msleep(10); | |
286 | } | |
287 | ||
288 | static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val) | |
289 | { | |
290 | p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val)); | |
291 | } | |
292 | ||
465b6353 | 293 | static int p54spi_wakeup(struct p54s_priv *priv) |
cd8d3d32 | 294 | { |
cd8d3d32 CL |
295 | /* wake the chip */ |
296 | p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS, | |
297 | cpu_to_le32(SPI_TARGET_INT_WAKEUP)); | |
298 | ||
299 | /* And wait for the READY interrupt */ | |
87cbfd06 | 300 | if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS, |
a7eee06b | 301 | SPI_HOST_INT_READY)) { |
87cbfd06 | 302 | dev_err(&priv->spi->dev, "INT_READY timeout\n"); |
465b6353 | 303 | return -EBUSY; |
cd8d3d32 CL |
304 | } |
305 | ||
306 | p54spi_int_ack(priv, SPI_HOST_INT_READY); | |
465b6353 | 307 | return 0; |
cd8d3d32 CL |
308 | } |
309 | ||
310 | static inline void p54spi_sleep(struct p54s_priv *priv) | |
311 | { | |
312 | p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS, | |
313 | cpu_to_le32(SPI_TARGET_INT_SLEEP)); | |
314 | } | |
315 | ||
316 | static void p54spi_int_ready(struct p54s_priv *priv) | |
317 | { | |
318 | p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32( | |
319 | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE)); | |
320 | ||
321 | switch (priv->fw_state) { | |
322 | case FW_STATE_BOOTING: | |
323 | priv->fw_state = FW_STATE_READY; | |
324 | complete(&priv->fw_comp); | |
325 | break; | |
326 | case FW_STATE_RESETTING: | |
327 | priv->fw_state = FW_STATE_READY; | |
328 | /* TODO: reinitialize state */ | |
329 | break; | |
330 | default: | |
331 | break; | |
332 | } | |
333 | } | |
334 | ||
335 | static int p54spi_rx(struct p54s_priv *priv) | |
336 | { | |
337 | struct sk_buff *skb; | |
338 | u16 len; | |
ff561ac8 MF |
339 | u16 rx_head[2]; |
340 | #define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16)) | |
cd8d3d32 | 341 | |
465b6353 MF |
342 | if (p54spi_wakeup(priv) < 0) |
343 | return -EBUSY; | |
cd8d3d32 | 344 | |
ff561ac8 MF |
345 | /* Read data size and first data word in one SPI transaction |
346 | * This is workaround for firmware/DMA bug, | |
347 | * when first data word gets lost under high load. | |
348 | */ | |
349 | p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head)); | |
350 | len = rx_head[0]; | |
cd8d3d32 CL |
351 | |
352 | if (len == 0) { | |
ff561ac8 MF |
353 | p54spi_sleep(priv); |
354 | dev_err(&priv->spi->dev, "rx request of zero bytes\n"); | |
cd8d3d32 CL |
355 | return 0; |
356 | } | |
357 | ||
9f201a87 MF |
358 | /* Firmware may insert up to 4 padding bytes after the lmac header, |
359 | * but it does not amend the size of SPI data transfer. | |
360 | * Such packets has correct data size in header, thus referencing | |
361 | * past the end of allocated skb. Reserve extra 4 bytes for this case */ | |
362 | skb = dev_alloc_skb(len + 4); | |
cd8d3d32 | 363 | if (!skb) { |
ff561ac8 | 364 | p54spi_sleep(priv); |
cd8d3d32 | 365 | dev_err(&priv->spi->dev, "could not alloc skb"); |
ff561ac8 | 366 | return -ENOMEM; |
cd8d3d32 CL |
367 | } |
368 | ||
ff561ac8 MF |
369 | if (len <= READAHEAD_SZ) { |
370 | memcpy(skb_put(skb, len), rx_head + 1, len); | |
371 | } else { | |
372 | memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ); | |
373 | p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, | |
374 | skb_put(skb, len - READAHEAD_SZ), | |
375 | len - READAHEAD_SZ); | |
376 | } | |
cd8d3d32 | 377 | p54spi_sleep(priv); |
9f201a87 MF |
378 | /* Put additional bytes to compensate for the possible |
379 | * alignment-caused truncation */ | |
380 | skb_put(skb, 4); | |
cd8d3d32 CL |
381 | |
382 | if (p54_rx(priv->hw, skb) == 0) | |
383 | dev_kfree_skb(skb); | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
388 | ||
389 | static irqreturn_t p54spi_interrupt(int irq, void *config) | |
390 | { | |
391 | struct spi_device *spi = config; | |
392 | struct p54s_priv *priv = dev_get_drvdata(&spi->dev); | |
393 | ||
394 | queue_work(priv->hw->workqueue, &priv->work); | |
395 | ||
396 | return IRQ_HANDLED; | |
397 | } | |
398 | ||
399 | static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb) | |
400 | { | |
401 | struct p54_hdr *hdr = (struct p54_hdr *) skb->data; | |
cd8d3d32 | 402 | int ret = 0; |
cd8d3d32 | 403 | |
465b6353 MF |
404 | if (p54spi_wakeup(priv) < 0) |
405 | return -EBUSY; | |
cd8d3d32 | 406 | |
4f5cab96 MF |
407 | ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len); |
408 | if (ret < 0) | |
409 | goto out; | |
cd8d3d32 | 410 | |
87cbfd06 | 411 | if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS, |
a7eee06b | 412 | SPI_HOST_INT_WR_READY)) { |
87cbfd06 | 413 | dev_err(&priv->spi->dev, "WR_READY timeout\n"); |
6edf534a | 414 | ret = -EAGAIN; |
87cbfd06 | 415 | goto out; |
cd8d3d32 CL |
416 | } |
417 | ||
418 | p54spi_int_ack(priv, SPI_HOST_INT_WR_READY); | |
cd8d3d32 | 419 | |
cd8d3d32 CL |
420 | if (FREE_AFTER_TX(skb)) |
421 | p54_free_skb(priv->hw, skb); | |
4f5cab96 | 422 | out: |
6edf534a | 423 | p54spi_sleep(priv); |
cd8d3d32 CL |
424 | return ret; |
425 | } | |
426 | ||
427 | static int p54spi_wq_tx(struct p54s_priv *priv) | |
428 | { | |
429 | struct p54s_tx_info *entry; | |
430 | struct sk_buff *skb; | |
431 | struct ieee80211_tx_info *info; | |
432 | struct p54_tx_info *minfo; | |
433 | struct p54s_tx_info *dinfo; | |
731c6531 | 434 | unsigned long flags; |
cd8d3d32 CL |
435 | int ret = 0; |
436 | ||
731c6531 | 437 | spin_lock_irqsave(&priv->tx_lock, flags); |
cd8d3d32 CL |
438 | |
439 | while (!list_empty(&priv->tx_pending)) { | |
440 | entry = list_entry(priv->tx_pending.next, | |
441 | struct p54s_tx_info, tx_list); | |
442 | ||
443 | list_del_init(&entry->tx_list); | |
444 | ||
731c6531 | 445 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
cd8d3d32 CL |
446 | |
447 | dinfo = container_of((void *) entry, struct p54s_tx_info, | |
448 | tx_list); | |
449 | minfo = container_of((void *) dinfo, struct p54_tx_info, | |
450 | data); | |
451 | info = container_of((void *) minfo, struct ieee80211_tx_info, | |
452 | rate_driver_data); | |
453 | skb = container_of((void *) info, struct sk_buff, cb); | |
454 | ||
455 | ret = p54spi_tx_frame(priv, skb); | |
456 | ||
cd8d3d32 CL |
457 | if (ret < 0) { |
458 | p54_free_skb(priv->hw, skb); | |
731c6531 | 459 | return ret; |
cd8d3d32 | 460 | } |
cd8d3d32 | 461 | |
731c6531 CL |
462 | spin_lock_irqsave(&priv->tx_lock, flags); |
463 | } | |
464 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
cd8d3d32 CL |
465 | return ret; |
466 | } | |
467 | ||
468 | static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb) | |
469 | { | |
470 | struct p54s_priv *priv = dev->priv; | |
471 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
472 | struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data; | |
473 | struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data; | |
731c6531 | 474 | unsigned long flags; |
cd8d3d32 CL |
475 | |
476 | BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data))); | |
477 | ||
731c6531 | 478 | spin_lock_irqsave(&priv->tx_lock, flags); |
cd8d3d32 | 479 | list_add_tail(&di->tx_list, &priv->tx_pending); |
731c6531 | 480 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
cd8d3d32 CL |
481 | |
482 | queue_work(priv->hw->workqueue, &priv->work); | |
483 | } | |
484 | ||
485 | static void p54spi_work(struct work_struct *work) | |
486 | { | |
487 | struct p54s_priv *priv = container_of(work, struct p54s_priv, work); | |
488 | u32 ints; | |
489 | int ret; | |
490 | ||
491 | mutex_lock(&priv->mutex); | |
492 | ||
4de2dc74 | 493 | if (priv->fw_state == FW_STATE_OFF) |
cd8d3d32 CL |
494 | goto out; |
495 | ||
496 | ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS); | |
497 | ||
498 | if (ints & SPI_HOST_INT_READY) { | |
499 | p54spi_int_ready(priv); | |
500 | p54spi_int_ack(priv, SPI_HOST_INT_READY); | |
501 | } | |
502 | ||
503 | if (priv->fw_state != FW_STATE_READY) | |
504 | goto out; | |
505 | ||
506 | if (ints & SPI_HOST_INT_UPDATE) { | |
507 | p54spi_int_ack(priv, SPI_HOST_INT_UPDATE); | |
508 | ret = p54spi_rx(priv); | |
509 | if (ret < 0) | |
510 | goto out; | |
511 | } | |
512 | if (ints & SPI_HOST_INT_SW_UPDATE) { | |
513 | p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE); | |
514 | ret = p54spi_rx(priv); | |
515 | if (ret < 0) | |
516 | goto out; | |
517 | } | |
518 | ||
519 | ret = p54spi_wq_tx(priv); | |
cd8d3d32 CL |
520 | out: |
521 | mutex_unlock(&priv->mutex); | |
522 | } | |
523 | ||
524 | static int p54spi_op_start(struct ieee80211_hw *dev) | |
525 | { | |
526 | struct p54s_priv *priv = dev->priv; | |
527 | unsigned long timeout; | |
528 | int ret = 0; | |
529 | ||
530 | if (mutex_lock_interruptible(&priv->mutex)) { | |
531 | ret = -EINTR; | |
532 | goto out; | |
533 | } | |
534 | ||
535 | priv->fw_state = FW_STATE_BOOTING; | |
536 | ||
537 | p54spi_power_on(priv); | |
538 | ||
539 | ret = p54spi_upload_firmware(dev); | |
540 | if (ret < 0) { | |
541 | p54spi_power_off(priv); | |
542 | goto out_unlock; | |
543 | } | |
544 | ||
545 | mutex_unlock(&priv->mutex); | |
546 | ||
547 | timeout = msecs_to_jiffies(2000); | |
548 | timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp, | |
549 | timeout); | |
550 | if (!timeout) { | |
551 | dev_err(&priv->spi->dev, "firmware boot failed"); | |
552 | p54spi_power_off(priv); | |
553 | ret = -1; | |
554 | goto out; | |
555 | } | |
556 | ||
557 | if (mutex_lock_interruptible(&priv->mutex)) { | |
558 | ret = -EINTR; | |
559 | p54spi_power_off(priv); | |
560 | goto out; | |
561 | } | |
562 | ||
563 | WARN_ON(priv->fw_state != FW_STATE_READY); | |
564 | ||
565 | out_unlock: | |
566 | mutex_unlock(&priv->mutex); | |
567 | ||
568 | out: | |
569 | return ret; | |
570 | } | |
571 | ||
572 | static void p54spi_op_stop(struct ieee80211_hw *dev) | |
573 | { | |
574 | struct p54s_priv *priv = dev->priv; | |
731c6531 | 575 | unsigned long flags; |
cd8d3d32 CL |
576 | |
577 | if (mutex_lock_interruptible(&priv->mutex)) { | |
578 | /* FIXME: how to handle this error? */ | |
579 | return; | |
580 | } | |
581 | ||
582 | WARN_ON(priv->fw_state != FW_STATE_READY); | |
583 | ||
584 | cancel_work_sync(&priv->work); | |
585 | ||
586 | p54spi_power_off(priv); | |
731c6531 | 587 | spin_lock_irqsave(&priv->tx_lock, flags); |
cd8d3d32 | 588 | INIT_LIST_HEAD(&priv->tx_pending); |
731c6531 | 589 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
cd8d3d32 CL |
590 | |
591 | priv->fw_state = FW_STATE_OFF; | |
592 | mutex_unlock(&priv->mutex); | |
593 | } | |
594 | ||
595 | static int __devinit p54spi_probe(struct spi_device *spi) | |
596 | { | |
597 | struct p54s_priv *priv = NULL; | |
598 | struct ieee80211_hw *hw; | |
599 | int ret = -EINVAL; | |
600 | ||
601 | hw = p54_init_common(sizeof(*priv)); | |
602 | if (!hw) { | |
bfa99bfd | 603 | dev_err(&spi->dev, "could not alloc ieee80211_hw"); |
cd8d3d32 CL |
604 | return -ENOMEM; |
605 | } | |
606 | ||
607 | priv = hw->priv; | |
608 | priv->hw = hw; | |
609 | dev_set_drvdata(&spi->dev, priv); | |
610 | priv->spi = spi; | |
611 | ||
cd8d3d32 CL |
612 | spi->bits_per_word = 16; |
613 | spi->max_speed_hz = 24000000; | |
614 | ||
615 | ret = spi_setup(spi); | |
616 | if (ret < 0) { | |
617 | dev_err(&priv->spi->dev, "spi_setup failed"); | |
618 | goto err_free_common; | |
619 | } | |
620 | ||
a2116993 | 621 | ret = gpio_request(p54spi_gpio_power, "p54spi power"); |
cd8d3d32 CL |
622 | if (ret < 0) { |
623 | dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret); | |
624 | goto err_free_common; | |
625 | } | |
626 | ||
a2116993 | 627 | ret = gpio_request(p54spi_gpio_irq, "p54spi irq"); |
cd8d3d32 CL |
628 | if (ret < 0) { |
629 | dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret); | |
630 | goto err_free_common; | |
631 | } | |
632 | ||
a2116993 CL |
633 | gpio_direction_output(p54spi_gpio_power, 0); |
634 | gpio_direction_input(p54spi_gpio_irq); | |
cd8d3d32 | 635 | |
a2116993 | 636 | ret = request_irq(gpio_to_irq(p54spi_gpio_irq), |
cd8d3d32 CL |
637 | p54spi_interrupt, IRQF_DISABLED, "p54spi", |
638 | priv->spi); | |
639 | if (ret < 0) { | |
640 | dev_err(&priv->spi->dev, "request_irq() failed"); | |
641 | goto err_free_common; | |
642 | } | |
643 | ||
a2116993 | 644 | set_irq_type(gpio_to_irq(p54spi_gpio_irq), |
cd8d3d32 CL |
645 | IRQ_TYPE_EDGE_RISING); |
646 | ||
a2116993 | 647 | disable_irq(gpio_to_irq(p54spi_gpio_irq)); |
cd8d3d32 CL |
648 | |
649 | INIT_WORK(&priv->work, p54spi_work); | |
650 | init_completion(&priv->fw_comp); | |
651 | INIT_LIST_HEAD(&priv->tx_pending); | |
652 | mutex_init(&priv->mutex); | |
653 | SET_IEEE80211_DEV(hw, &spi->dev); | |
654 | priv->common.open = p54spi_op_start; | |
655 | priv->common.stop = p54spi_op_stop; | |
656 | priv->common.tx = p54spi_op_tx; | |
657 | ||
658 | ret = p54spi_request_firmware(hw); | |
659 | if (ret < 0) | |
660 | goto err_free_common; | |
661 | ||
662 | ret = p54spi_request_eeprom(hw); | |
663 | if (ret) | |
664 | goto err_free_common; | |
665 | ||
2ac71072 CL |
666 | ret = p54_register_common(hw, &priv->spi->dev); |
667 | if (ret) | |
cd8d3d32 | 668 | goto err_free_common; |
cd8d3d32 | 669 | |
cd8d3d32 CL |
670 | return 0; |
671 | ||
672 | err_free_common: | |
673 | p54_free_common(priv->hw); | |
674 | return ret; | |
675 | } | |
676 | ||
677 | static int __devexit p54spi_remove(struct spi_device *spi) | |
678 | { | |
679 | struct p54s_priv *priv = dev_get_drvdata(&spi->dev); | |
680 | ||
d8c92107 | 681 | p54_unregister_common(priv->hw); |
cd8d3d32 | 682 | |
a2116993 | 683 | free_irq(gpio_to_irq(p54spi_gpio_irq), spi); |
cd8d3d32 | 684 | |
a2116993 CL |
685 | gpio_free(p54spi_gpio_power); |
686 | gpio_free(p54spi_gpio_irq); | |
cd8d3d32 CL |
687 | release_firmware(priv->firmware); |
688 | ||
689 | mutex_destroy(&priv->mutex); | |
690 | ||
691 | p54_free_common(priv->hw); | |
cd8d3d32 CL |
692 | |
693 | return 0; | |
694 | } | |
695 | ||
696 | ||
697 | static struct spi_driver p54spi_driver = { | |
698 | .driver = { | |
699 | /* use cx3110x name because board-n800.c uses that for the | |
700 | * SPI port */ | |
701 | .name = "cx3110x", | |
702 | .bus = &spi_bus_type, | |
703 | .owner = THIS_MODULE, | |
704 | }, | |
705 | ||
706 | .probe = p54spi_probe, | |
707 | .remove = __devexit_p(p54spi_remove), | |
708 | }; | |
709 | ||
710 | static int __init p54spi_init(void) | |
711 | { | |
712 | int ret; | |
713 | ||
714 | ret = spi_register_driver(&p54spi_driver); | |
715 | if (ret < 0) { | |
716 | printk(KERN_ERR "failed to register SPI driver: %d", ret); | |
717 | goto out; | |
718 | } | |
719 | ||
720 | out: | |
721 | return ret; | |
722 | } | |
723 | ||
724 | static void __exit p54spi_exit(void) | |
725 | { | |
726 | spi_unregister_driver(&p54spi_driver); | |
727 | } | |
728 | ||
729 | module_init(p54spi_init); | |
730 | module_exit(p54spi_exit); | |
731 | ||
732 | MODULE_LICENSE("GPL"); | |
733 | MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>"); |