[linux-2.6-block.git] / drivers / net / wireless / p54 / p54spi.c

/*
 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
 * Copyright 2008       Johannes Berg <johannes@sipsolutions.net>
 *
 * This driver is a port from stlc45xx:
 *	Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/firmware.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <linux/etherdevice.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#include "p54spi.h"
#include "p54.h"

#include "lmac.h"

#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
#include "p54spi_eeprom.h"
#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */

MODULE_FIRMWARE("3826.arm");
MODULE_ALIAS("stlc45xx");

/*
 * gpios should be handled in board files and provided via platform data,
 * but because it's currently impossible for p54spi to have a header file
 * in include/linux, let's use module paramaters for now
 */

static int p54spi_gpio_power = 97;
module_param(p54spi_gpio_power, int, 0444);
MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");

static int p54spi_gpio_irq = 87;
module_param(p54spi_gpio_irq, int, 0444);
MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");

static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
			      void *buf, size_t len)
{
	struct spi_transfer t[2];
	struct spi_message m;
	__le16 addr;

	/* We first push the address */
	addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = &addr;
	t[0].len = sizeof(addr);
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = len;
	spi_message_add_tail(&t[1], &m);

	spi_sync(priv->spi, &m);
}


static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
			     const void *buf, size_t len)
{
	struct spi_transfer t[3];
	struct spi_message m;
	__le16 addr;

	/* We first push the address */
	addr = cpu_to_le16(address << 8);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = &addr;
	t[0].len = sizeof(addr);
	spi_message_add_tail(&t[0], &m);

	t[1].tx_buf = buf;
	t[1].len = len & ~1;
	spi_message_add_tail(&t[1], &m);

	if (len % 2) {
		__le16 last_word;
		last_word = cpu_to_le16(((u8 *)buf)[len - 1]);

		t[2].tx_buf = &last_word;
		t[2].len = sizeof(last_word);
		spi_message_add_tail(&t[2], &m);
	}

	spi_sync(priv->spi, &m);
}

static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
{
	__le32 val;

	p54spi_spi_read(priv, addr, &val, sizeof(val));

	return le32_to_cpu(val);
}

static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
{
	p54spi_spi_write(priv, addr, &val, sizeof(val));
}

static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
{
	p54spi_spi_write(priv, addr, &val, sizeof(val));
}

static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
{
	int i;

	for (i = 0; i < 2000; i++) {
		u32 buffer = p54spi_read32(priv, reg);
		if ((buffer & bits) == bits)
			return 1;
	}
	return 0;
}

static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
				const void *buf, size_t len)
{
	if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
		dev_err(&priv->spi->dev, "spi_write_dma not allowed "
			"to DMA write.\n");
		return -EAGAIN;
	}

	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
		       cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));

	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
	p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
	p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
	return 0;
}

static int p54spi_request_firmware(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	int ret;

	/* FIXME: should driver use it's own struct device? */
	ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);

	if (ret < 0) {
		dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
		return ret;
	}

	ret = p54_parse_firmware(dev, priv->firmware);
	if (ret) {
		release_firmware(priv->firmware);
		return ret;
	}

	return 0;
}

static int p54spi_request_eeprom(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	const struct firmware *eeprom;
	int ret;

	/*
	 * allow users to customize their eeprom.
	 */

	ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
	if (ret < 0) {
#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
		dev_info(&priv->spi->dev, "loading default eeprom...\n");
		ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
				       sizeof(p54spi_eeprom));
#else
		dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
	} else {
		dev_info(&priv->spi->dev, "loading user eeprom...\n");
		ret = p54_parse_eeprom(dev, (void *) eeprom->data,
				       (int)eeprom->size);
		release_firmware(eeprom);
	}
	return ret;
}

static int p54spi_upload_firmware(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long fw_len, _fw_len;
	unsigned int offset = 0;
	int err = 0;
	u8 *fw;

	fw_len = priv->firmware->size;
	fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
	if (!fw)
		return -ENOMEM;

	/* stop the device */
	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
		       SPI_CTRL_STAT_START_HALTED));

	msleep(TARGET_BOOT_SLEEP);

	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE |
		       SPI_CTRL_STAT_START_HALTED));

	msleep(TARGET_BOOT_SLEEP);

	while (fw_len > 0) {
		_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);

		err = p54spi_spi_write_dma(priv, cpu_to_le32(
					   ISL38XX_DEV_FIRMWARE_ADDR + offset),
					   (fw + offset), _fw_len);
		if (err < 0)
			goto out;

		fw_len -= _fw_len;
		offset += _fw_len;
	}

	BUG_ON(fw_len != 0);

	/* enable host interrupts */
	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
		       cpu_to_le32(SPI_HOST_INTS_DEFAULT));

	/* boot the device */
	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
		       SPI_CTRL_STAT_RAM_BOOT));

	msleep(TARGET_BOOT_SLEEP);

	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
	msleep(TARGET_BOOT_SLEEP);

out:
	kfree(fw);
	return err;
}

static void p54spi_power_off(struct p54s_priv *priv)
{
	disable_irq(gpio_to_irq(p54spi_gpio_irq));
	gpio_set_value(p54spi_gpio_power, 0);
}

static void p54spi_power_on(struct p54s_priv *priv)
{
	gpio_set_value(p54spi_gpio_power, 1);
	enable_irq(gpio_to_irq(p54spi_gpio_irq));

	/*
	 * need to wait a while before device can be accessed, the length
	 * is just a guess
	 */
	msleep(10);
}

static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
{
	p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
}

static int p54spi_wakeup(struct p54s_priv *priv)
{
	/* wake the chip */
	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
		       cpu_to_le32(SPI_TARGET_INT_WAKEUP));

	/* And wait for the READY interrupt */
	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
			     SPI_HOST_INT_READY)) {
		dev_err(&priv->spi->dev, "INT_READY timeout\n");
		return -EBUSY;
	}

	p54spi_int_ack(priv, SPI_HOST_INT_READY);
	return 0;
}

static inline void p54spi_sleep(struct p54s_priv *priv)
{
	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
		       cpu_to_le32(SPI_TARGET_INT_SLEEP));
}

static void p54spi_int_ready(struct p54s_priv *priv)
{
	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
		       SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));

	switch (priv->fw_state) {
	case FW_STATE_BOOTING:
		priv->fw_state = FW_STATE_READY;
		complete(&priv->fw_comp);
		break;
	case FW_STATE_RESETTING:
		priv->fw_state = FW_STATE_READY;
		/* TODO: reinitialize state */
		break;
	default:
		break;
	}
}

static int p54spi_rx(struct p54s_priv *priv)
{
	struct sk_buff *skb;
	u16 len;
	u16 rx_head[2];
#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))

	if (p54spi_wakeup(priv) < 0)
		return -EBUSY;

	/* Read data size and first data word in one SPI transaction
	 * This is workaround for firmware/DMA bug,
	 * when first data word gets lost under high load.
	 */
	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
	len = rx_head[0];

	if (len == 0) {
		p54spi_sleep(priv);
		dev_err(&priv->spi->dev, "rx request of zero bytes\n");
		return 0;
	}

	/* Firmware may insert up to 4 padding bytes after the lmac header,
	 * but it does not amend the size of SPI data transfer.
	 * Such packets has correct data size in header, thus referencing
	 * past the end of allocated skb. Reserve extra 4 bytes for this case */
	skb = dev_alloc_skb(len + 4);
	if (!skb) {
		p54spi_sleep(priv);
		dev_err(&priv->spi->dev, "could not alloc skb");
		return -ENOMEM;
	}

	if (len <= READAHEAD_SZ) {
		memcpy(skb_put(skb, len), rx_head + 1, len);
	} else {
		memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
		p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
				skb_put(skb, len - READAHEAD_SZ),
				len - READAHEAD_SZ);
	}
	p54spi_sleep(priv);
	/* Put additional bytes to compensate for the possible
	 * alignment-caused truncation */
	skb_put(skb, 4);

	if (p54_rx(priv->hw, skb) == 0)
		dev_kfree_skb(skb);

	return 0;
}


static irqreturn_t p54spi_interrupt(int irq, void *config)
{
	struct spi_device *spi = config;
	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);

	ieee80211_queue_work(priv->hw, &priv->work);

	return IRQ_HANDLED;
}

static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
{
	struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
	int ret = 0;

	if (p54spi_wakeup(priv) < 0)
		return -EBUSY;

	ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
	if (ret < 0)
		goto out;

	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
			     SPI_HOST_INT_WR_READY)) {
		dev_err(&priv->spi->dev, "WR_READY timeout\n");
		ret = -EAGAIN;
		goto out;
	}

	p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);

	if (FREE_AFTER_TX(skb))
		p54_free_skb(priv->hw, skb);
out:
	p54spi_sleep(priv);
	return ret;
}

static int p54spi_wq_tx(struct p54s_priv *priv)
{
	struct p54s_tx_info *entry;
	struct sk_buff *skb;
	struct ieee80211_tx_info *info;
	struct p54_tx_info *minfo;
	struct p54s_tx_info *dinfo;
	unsigned long flags;
	int ret = 0;

	spin_lock_irqsave(&priv->tx_lock, flags);

	while (!list_empty(&priv->tx_pending)) {
		entry = list_entry(priv->tx_pending.next,
				   struct p54s_tx_info, tx_list);

		list_del_init(&entry->tx_list);

		spin_unlock_irqrestore(&priv->tx_lock, flags);

		dinfo = container_of((void *) entry, struct p54s_tx_info,
				     tx_list);
		minfo = container_of((void *) dinfo, struct p54_tx_info,
				     data);
		info = container_of((void *) minfo, struct ieee80211_tx_info,
				    rate_driver_data);
		skb = container_of((void *) info, struct sk_buff, cb);

		ret = p54spi_tx_frame(priv, skb);

		if (ret < 0) {
			p54_free_skb(priv->hw, skb);
			return ret;
		}

		spin_lock_irqsave(&priv->tx_lock, flags);
	}
	spin_unlock_irqrestore(&priv->tx_lock, flags);
	return ret;
}

static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
	struct p54s_priv *priv = dev->priv;
	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
	struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
	struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
	unsigned long flags;

	BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));

	spin_lock_irqsave(&priv->tx_lock, flags);
	list_add_tail(&di->tx_list, &priv->tx_pending);
	spin_unlock_irqrestore(&priv->tx_lock, flags);

	ieee80211_queue_work(priv->hw, &priv->work);
}

static void p54spi_work(struct work_struct *work)
{
	struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
	u32 ints;
	int ret;

	mutex_lock(&priv->mutex);

	if (priv->fw_state == FW_STATE_OFF)
		goto out;

	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);

	if (ints & SPI_HOST_INT_READY) {
		p54spi_int_ready(priv);
		p54spi_int_ack(priv, SPI_HOST_INT_READY);
	}

	if (priv->fw_state != FW_STATE_READY)
		goto out;

	if (ints & SPI_HOST_INT_UPDATE) {
		p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
		ret = p54spi_rx(priv);
		if (ret < 0)
			goto out;
	}
	if (ints & SPI_HOST_INT_SW_UPDATE) {
		p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
		ret = p54spi_rx(priv);
		if (ret < 0)
			goto out;
	}

	ret = p54spi_wq_tx(priv);
out:
	mutex_unlock(&priv->mutex);
}

static int p54spi_op_start(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long timeout;
	int ret = 0;

	if (mutex_lock_interruptible(&priv->mutex)) {
		ret = -EINTR;
		goto out;
	}

	priv->fw_state = FW_STATE_BOOTING;

	p54spi_power_on(priv);

	ret = p54spi_upload_firmware(dev);
	if (ret < 0) {
		p54spi_power_off(priv);
		goto out_unlock;
	}

	mutex_unlock(&priv->mutex);

	timeout = msecs_to_jiffies(2000);
	timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
							    timeout);
	if (!timeout) {
		dev_err(&priv->spi->dev, "firmware boot failed");
		p54spi_power_off(priv);
		ret = -1;
		goto out;
	}

	if (mutex_lock_interruptible(&priv->mutex)) {
		ret = -EINTR;
		p54spi_power_off(priv);
		goto out;
	}

	WARN_ON(priv->fw_state != FW_STATE_READY);

out_unlock:
	mutex_unlock(&priv->mutex);

out:
	return ret;
}

static void p54spi_op_stop(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long flags;

	if (mutex_lock_interruptible(&priv->mutex)) {
		/* FIXME: how to handle this error? */
		return;
	}

	WARN_ON(priv->fw_state != FW_STATE_READY);

	cancel_work_sync(&priv->work);

	p54spi_power_off(priv);
	spin_lock_irqsave(&priv->tx_lock, flags);
	INIT_LIST_HEAD(&priv->tx_pending);
	spin_unlock_irqrestore(&priv->tx_lock, flags);

	priv->fw_state = FW_STATE_OFF;
	mutex_unlock(&priv->mutex);
}

static int __devinit p54spi_probe(struct spi_device *spi)
{
	struct p54s_priv *priv = NULL;
	struct ieee80211_hw *hw;
	int ret = -EINVAL;

	hw = p54_init_common(sizeof(*priv));
	if (!hw) {
		dev_err(&spi->dev, "could not alloc ieee80211_hw");
		return -ENOMEM;
	}

	priv = hw->priv;
	priv->hw = hw;
	dev_set_drvdata(&spi->dev, priv);
	priv->spi = spi;

	spi->bits_per_word = 16;
	spi->max_speed_hz = 24000000;

	ret = spi_setup(spi);
	if (ret < 0) {
		dev_err(&priv->spi->dev, "spi_setup failed");
		goto err_free_common;
	}

	ret = gpio_request(p54spi_gpio_power, "p54spi power");
	if (ret < 0) {
		dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
		goto err_free_common;
	}

	ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
	if (ret < 0) {
		dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
		goto err_free_common;
	}

	gpio_direction_output(p54spi_gpio_power, 0);
	gpio_direction_input(p54spi_gpio_irq);

	ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
			  p54spi_interrupt, IRQF_DISABLED, "p54spi",
			  priv->spi);
	if (ret < 0) {
		dev_err(&priv->spi->dev, "request_irq() failed");
		goto err_free_common;
	}

	irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);

	disable_irq(gpio_to_irq(p54spi_gpio_irq));

	INIT_WORK(&priv->work, p54spi_work);
	init_completion(&priv->fw_comp);
	INIT_LIST_HEAD(&priv->tx_pending);
	mutex_init(&priv->mutex);
	SET_IEEE80211_DEV(hw, &spi->dev);
	priv->common.open = p54spi_op_start;
	priv->common.stop = p54spi_op_stop;
	priv->common.tx = p54spi_op_tx;

	ret = p54spi_request_firmware(hw);
	if (ret < 0)
		goto err_free_common;

	ret = p54spi_request_eeprom(hw);
	if (ret)
		goto err_free_common;

	ret = p54_register_common(hw, &priv->spi->dev);
	if (ret)
		goto err_free_common;

	return 0;

err_free_common:
	p54_free_common(priv->hw);
	return ret;
}

static int __devexit p54spi_remove(struct spi_device *spi)
{
	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);

	p54_unregister_common(priv->hw);

	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);

	gpio_free(p54spi_gpio_power);
	gpio_free(p54spi_gpio_irq);
	release_firmware(priv->firmware);

	mutex_destroy(&priv->mutex);

	p54_free_common(priv->hw);

	return 0;
}


static struct spi_driver p54spi_driver = {
	.driver = {
		.name		= "p54spi",
		.bus		= &spi_bus_type,
		.owner		= THIS_MODULE,
	},

	.probe		= p54spi_probe,
	.remove		= __devexit_p(p54spi_remove),
};

static int __init p54spi_init(void)
{
	int ret;

	ret = spi_register_driver(&p54spi_driver);
	if (ret < 0) {
		printk(KERN_ERR "failed to register SPI driver: %d", ret);
		goto out;
	}

out:
	return ret;
}

static void __exit p54spi_exit(void)
{
	spi_unregister_driver(&p54spi_driver);
}

module_init(p54spi_init);
module_exit(p54spi_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
MODULE_ALIAS("spi:cx3110x");
MODULE_ALIAS("spi:p54spi");
Commit	Line	Data
cd8d3d32 CL	1	/*
	2	* Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
	3	* Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
	4	*
	5	* This driver is a port from stlc45xx:
	6	* Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/firmware.h>
	27	#include <linux/delay.h>
	28	#include <linux/irq.h>
	29	#include <linux/spi/spi.h>
	30	#include <linux/etherdevice.h>
	31	#include <linux/gpio.h>
5a0e3ad6	32	#include <linux/slab.h>
cd8d3d32 CL	33
cd8d3d32 CL	34	#include "p54spi.h"
cd8d3d32 CL	35	#include "p54.h"
cd8d3d32 CL	36
d8c92107	37	#include "lmac.h"
cd8d3d32	38
d7065c30 CL	39	#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
	40	#include "p54spi_eeprom.h"
	41	#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
	42
cd8d3d32 CL	43	MODULE_FIRMWARE("3826.arm");
	44	MODULE_ALIAS("stlc45xx");
	45
a2116993 CL	46	/*
	47	* gpios should be handled in board files and provided via platform data,
	48	* but because it's currently impossible for p54spi to have a header file
	49	* in include/linux, let's use module paramaters for now
	50	*/
	51
	52	static int p54spi_gpio_power = 97;
	53	module_param(p54spi_gpio_power, int, 0444);
	54	MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
	55
	56	static int p54spi_gpio_irq = 87;
	57	module_param(p54spi_gpio_irq, int, 0444);
	58	MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
	59
cd8d3d32 CL	60	static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
	61	void *buf, size_t len)
	62	{
	63	struct spi_transfer t[2];
	64	struct spi_message m;
	65	__le16 addr;
	66
	67	/* We first push the address */
	68	addr = cpu_to_le16(address << 8 \| SPI_ADRS_READ_BIT_15);
	69
	70	spi_message_init(&m);
	71	memset(t, 0, sizeof(t));
	72
	73	t[0].tx_buf = &addr;
	74	t[0].len = sizeof(addr);
	75	spi_message_add_tail(&t[0], &m);
	76
	77	t[1].rx_buf = buf;
	78	t[1].len = len;
	79	spi_message_add_tail(&t[1], &m);
	80
	81	spi_sync(priv->spi, &m);
	82	}
	83
	84
	85	static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
	86	const void *buf, size_t len)
	87	{
	88	struct spi_transfer t[3];
	89	struct spi_message m;
	90	__le16 addr;
	91
	92	/* We first push the address */
	93	addr = cpu_to_le16(address << 8);
	94
	95	spi_message_init(&m);
	96	memset(t, 0, sizeof(t));
	97
	98	t[0].tx_buf = &addr;
	99	t[0].len = sizeof(addr);
	100	spi_message_add_tail(&t[0], &m);
	101
	102	t[1].tx_buf = buf;
69712e92	103	t[1].len = len & ~1;
cd8d3d32 CL	104	spi_message_add_tail(&t[1], &m);
	105
	106	if (len % 2) {
	107	__le16 last_word;
	108	last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
	109
	110	t[2].tx_buf = &last_word;
	111	t[2].len = sizeof(last_word);
	112	spi_message_add_tail(&t[2], &m);
	113	}
	114
	115	spi_sync(priv->spi, &m);
	116	}
	117
cd8d3d32 CL	118	static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
	119	{
	120	__le32 val;
	121
	122	p54spi_spi_read(priv, addr, &val, sizeof(val));
	123
	124	return le32_to_cpu(val);
	125	}
	126
	127	static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
	128	{
	129	p54spi_spi_write(priv, addr, &val, sizeof(val));
	130	}
	131
	132	static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
	133	{
	134	p54spi_spi_write(priv, addr, &val, sizeof(val));
	135	}
	136
a7eee06b	137	static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
cd8d3d32 CL	138	{
cd8d3d32 CL	139	int i;
cd8d3d32 CL	140
cd8d3d32 CL	141	for (i = 0; i < 2000; i++) {
a7eee06b	142	u32 buffer = p54spi_read32(priv, reg);
f74d0f5c	143	if ((buffer & bits) == bits)
cd8d3d32	144	return 1;
cd8d3d32 CL	145	}
	146	return 0;
	147	}
	148
4f5cab96 MF	149	static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
	150	const void *buf, size_t len)
	151	{
a7eee06b	152	if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
4f5cab96	153	dev_err(&priv->spi->dev, "spi_write_dma not allowed "
87cbfd06	154	"to DMA write.\n");
4f5cab96 MF	155	return -EAGAIN;
	156	}
	157
210dd1bb MF	158	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
	159	cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
	160
4f5cab96 MF	161	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
	162	p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
	163	p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
	164	return 0;
	165	}
	166
cd8d3d32 CL	167	static int p54spi_request_firmware(struct ieee80211_hw *dev)
	168	{
	169	struct p54s_priv *priv = dev->priv;
	170	int ret;
	171
	172	/* FIXME: should driver use it's own struct device? */
	173	ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
	174
	175	if (ret < 0) {
	176	dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
	177	return ret;
	178	}
	179
	180	ret = p54_parse_firmware(dev, priv->firmware);
	181	if (ret) {
	182	release_firmware(priv->firmware);
	183	return ret;
	184	}
	185
	186	return 0;
	187	}
	188
	189	static int p54spi_request_eeprom(struct ieee80211_hw *dev)
	190	{
	191	struct p54s_priv *priv = dev->priv;
	192	const struct firmware *eeprom;
	193	int ret;
	194
	195	/*
	196	* allow users to customize their eeprom.
	197	*/
	198
	199	ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
	200	if (ret < 0) {
d7065c30	201	#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
cd8d3d32 CL	202	dev_info(&priv->spi->dev, "loading default eeprom...\n");
	203	ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
	204	sizeof(p54spi_eeprom));
f4bbf922 MB	205	#else
f4bbf922 MB	206	dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
d7065c30	207	#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
cd8d3d32 CL	208	} else {
	209	dev_info(&priv->spi->dev, "loading user eeprom...\n");
	210	ret = p54_parse_eeprom(dev, (void *) eeprom->data,
	211	(int)eeprom->size);
	212	release_firmware(eeprom);
	213	}
	214	return ret;
	215	}
	216
	217	static int p54spi_upload_firmware(struct ieee80211_hw *dev)
	218	{
	219	struct p54s_priv *priv = dev->priv;
5e3af1d2 MF	220	unsigned long fw_len, _fw_len;
	221	unsigned int offset = 0;
	222	int err = 0;
	223	u8 *fw;
	224
	225	fw_len = priv->firmware->size;
	226	fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
	227	if (!fw)
	228	return -ENOMEM;
cd8d3d32 CL	229
	230	/* stop the device */
	231	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	232	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_HOST_RESET \|
	233	SPI_CTRL_STAT_START_HALTED));
	234
	235	msleep(TARGET_BOOT_SLEEP);
	236
	237	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	238	SPI_CTRL_STAT_HOST_OVERRIDE \|
	239	SPI_CTRL_STAT_START_HALTED));
	240
	241	msleep(TARGET_BOOT_SLEEP);
	242
cd8d3d32 CL	243	while (fw_len > 0) {
	244	_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
	245
4f5cab96 MF	246	err = p54spi_spi_write_dma(priv, cpu_to_le32(
	247	ISL38XX_DEV_FIRMWARE_ADDR + offset),
	248	(fw + offset), _fw_len);
	249	if (err < 0)
5e3af1d2	250	goto out;
cd8d3d32 CL	251
cd8d3d32 CL	252	fw_len -= _fw_len;
5e3af1d2	253	offset += _fw_len;
cd8d3d32 CL	254	}
	255
	256	BUG_ON(fw_len != 0);
	257
	258	/* enable host interrupts */
	259	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
	260	cpu_to_le32(SPI_HOST_INTS_DEFAULT));
	261
	262	/* boot the device */
	263	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	264	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_HOST_RESET \|
	265	SPI_CTRL_STAT_RAM_BOOT));
	266
	267	msleep(TARGET_BOOT_SLEEP);
	268
	269	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	270	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_RAM_BOOT));
	271	msleep(TARGET_BOOT_SLEEP);
5e3af1d2 MF	272
	273	out:
	274	kfree(fw);
	275	return err;
cd8d3d32 CL	276	}
	277
	278	static void p54spi_power_off(struct p54s_priv *priv)
	279	{
a2116993 CL	280	disable_irq(gpio_to_irq(p54spi_gpio_irq));
a2116993 CL	281	gpio_set_value(p54spi_gpio_power, 0);
cd8d3d32 CL	282	}
	283
	284	static void p54spi_power_on(struct p54s_priv *priv)
	285	{
a2116993 CL	286	gpio_set_value(p54spi_gpio_power, 1);
a2116993 CL	287	enable_irq(gpio_to_irq(p54spi_gpio_irq));
cd8d3d32 CL	288
cd8d3d32 CL	289	/*
25985edc	290	* need to wait a while before device can be accessed, the length
cd8d3d32 CL	291	* is just a guess
	292	*/
	293	msleep(10);
	294	}
	295
	296	static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
	297	{
	298	p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
	299	}
	300
465b6353	301	static int p54spi_wakeup(struct p54s_priv *priv)
cd8d3d32	302	{
cd8d3d32 CL	303	/* wake the chip */
	304	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
	305	cpu_to_le32(SPI_TARGET_INT_WAKEUP));
	306
	307	/* And wait for the READY interrupt */
87cbfd06	308	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
a7eee06b	309	SPI_HOST_INT_READY)) {
87cbfd06	310	dev_err(&priv->spi->dev, "INT_READY timeout\n");
465b6353	311	return -EBUSY;
cd8d3d32 CL	312	}
	313
	314	p54spi_int_ack(priv, SPI_HOST_INT_READY);
465b6353	315	return 0;
cd8d3d32 CL	316	}
	317
	318	static inline void p54spi_sleep(struct p54s_priv *priv)
	319	{
	320	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
	321	cpu_to_le32(SPI_TARGET_INT_SLEEP));
	322	}
	323
	324	static void p54spi_int_ready(struct p54s_priv *priv)
	325	{
	326	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
	327	SPI_HOST_INT_UPDATE \| SPI_HOST_INT_SW_UPDATE));
	328
	329	switch (priv->fw_state) {
	330	case FW_STATE_BOOTING:
	331	priv->fw_state = FW_STATE_READY;
	332	complete(&priv->fw_comp);
	333	break;
	334	case FW_STATE_RESETTING:
	335	priv->fw_state = FW_STATE_READY;
	336	/* TODO: reinitialize state */
	337	break;
	338	default:
	339	break;
	340	}
	341	}
	342
	343	static int p54spi_rx(struct p54s_priv *priv)
	344	{
	345	struct sk_buff *skb;
	346	u16 len;
ff561ac8 MF	347	u16 rx_head[2];
ff561ac8 MF	348	#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
cd8d3d32	349
465b6353 MF	350	if (p54spi_wakeup(priv) < 0)
465b6353 MF	351	return -EBUSY;
cd8d3d32	352
ff561ac8 MF	353	/* Read data size and first data word in one SPI transaction
	354	* This is workaround for firmware/DMA bug,
	355	* when first data word gets lost under high load.
	356	*/
	357	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
	358	len = rx_head[0];
cd8d3d32 CL	359
cd8d3d32 CL	360	if (len == 0) {
ff561ac8 MF	361	p54spi_sleep(priv);
ff561ac8 MF	362	dev_err(&priv->spi->dev, "rx request of zero bytes\n");
cd8d3d32 CL	363	return 0;
	364	}
	365
9f201a87 MF	366	/* Firmware may insert up to 4 padding bytes after the lmac header,
	367	* but it does not amend the size of SPI data transfer.
	368	* Such packets has correct data size in header, thus referencing
	369	* past the end of allocated skb. Reserve extra 4 bytes for this case */
	370	skb = dev_alloc_skb(len + 4);
cd8d3d32	371	if (!skb) {
ff561ac8	372	p54spi_sleep(priv);
cd8d3d32	373	dev_err(&priv->spi->dev, "could not alloc skb");
ff561ac8	374	return -ENOMEM;
cd8d3d32 CL	375	}
cd8d3d32 CL	376
ff561ac8 MF	377	if (len <= READAHEAD_SZ) {
	378	memcpy(skb_put(skb, len), rx_head + 1, len);
	379	} else {
	380	memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
	381	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
	382	skb_put(skb, len - READAHEAD_SZ),
	383	len - READAHEAD_SZ);
	384	}
cd8d3d32	385	p54spi_sleep(priv);
9f201a87 MF	386	/* Put additional bytes to compensate for the possible
	387	* alignment-caused truncation */
	388	skb_put(skb, 4);
cd8d3d32 CL	389
	390	if (p54_rx(priv->hw, skb) == 0)
	391	dev_kfree_skb(skb);
	392
	393	return 0;
	394	}
	395
	396
	397	static irqreturn_t p54spi_interrupt(int irq, void *config)
	398	{
	399	struct spi_device *spi = config;
	400	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
	401
42935eca	402	ieee80211_queue_work(priv->hw, &priv->work);
cd8d3d32 CL	403
	404	return IRQ_HANDLED;
	405	}
	406
	407	static int p54spi_tx_frame(struct p54s_priv priv, struct sk_buff skb)
	408	{
	409	struct p54_hdr hdr = (struct p54_hdr ) skb->data;
cd8d3d32	410	int ret = 0;
cd8d3d32	411
465b6353 MF	412	if (p54spi_wakeup(priv) < 0)
465b6353 MF	413	return -EBUSY;
cd8d3d32	414
4f5cab96 MF	415	ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
	416	if (ret < 0)
	417	goto out;
cd8d3d32	418
87cbfd06	419	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
a7eee06b	420	SPI_HOST_INT_WR_READY)) {
87cbfd06	421	dev_err(&priv->spi->dev, "WR_READY timeout\n");
6edf534a	422	ret = -EAGAIN;
87cbfd06	423	goto out;
cd8d3d32 CL	424	}
	425
	426	p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
cd8d3d32	427
cd8d3d32 CL	428	if (FREE_AFTER_TX(skb))
cd8d3d32 CL	429	p54_free_skb(priv->hw, skb);
4f5cab96	430	out:
6edf534a	431	p54spi_sleep(priv);
cd8d3d32 CL	432	return ret;
	433	}
	434
	435	static int p54spi_wq_tx(struct p54s_priv *priv)
	436	{
	437	struct p54s_tx_info *entry;
	438	struct sk_buff *skb;
	439	struct ieee80211_tx_info *info;
	440	struct p54_tx_info *minfo;
	441	struct p54s_tx_info *dinfo;
731c6531	442	unsigned long flags;
cd8d3d32 CL	443	int ret = 0;
cd8d3d32 CL	444
731c6531	445	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32 CL	446
	447	while (!list_empty(&priv->tx_pending)) {
	448	entry = list_entry(priv->tx_pending.next,
	449	struct p54s_tx_info, tx_list);
	450
	451	list_del_init(&entry->tx_list);
	452
731c6531	453	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	454
	455	dinfo = container_of((void *) entry, struct p54s_tx_info,
	456	tx_list);
	457	minfo = container_of((void *) dinfo, struct p54_tx_info,
	458	data);
	459	info = container_of((void *) minfo, struct ieee80211_tx_info,
	460	rate_driver_data);
	461	skb = container_of((void *) info, struct sk_buff, cb);
	462
	463	ret = p54spi_tx_frame(priv, skb);
	464
cd8d3d32 CL	465	if (ret < 0) {
cd8d3d32 CL	466	p54_free_skb(priv->hw, skb);
731c6531	467	return ret;
cd8d3d32	468	}
cd8d3d32	469
731c6531 CL	470	spin_lock_irqsave(&priv->tx_lock, flags);
	471	}
	472	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	473	return ret;
	474	}
	475
	476	static void p54spi_op_tx(struct ieee80211_hw dev, struct sk_buff skb)
	477	{
	478	struct p54s_priv *priv = dev->priv;
	479	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
	480	struct p54_tx_info mi = (struct p54_tx_info ) info->rate_driver_data;
	481	struct p54s_tx_info di = (struct p54s_tx_info ) mi->data;
731c6531	482	unsigned long flags;
cd8d3d32 CL	483
	484	BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
	485
731c6531	486	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32	487	list_add_tail(&di->tx_list, &priv->tx_pending);
731c6531	488	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32	489
42935eca	490	ieee80211_queue_work(priv->hw, &priv->work);
cd8d3d32 CL	491	}
	492
	493	static void p54spi_work(struct work_struct *work)
	494	{
	495	struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
	496	u32 ints;
	497	int ret;
	498
	499	mutex_lock(&priv->mutex);
	500
4de2dc74	501	if (priv->fw_state == FW_STATE_OFF)
cd8d3d32 CL	502	goto out;
	503
	504	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
	505
	506	if (ints & SPI_HOST_INT_READY) {
	507	p54spi_int_ready(priv);
	508	p54spi_int_ack(priv, SPI_HOST_INT_READY);
	509	}
	510
	511	if (priv->fw_state != FW_STATE_READY)
	512	goto out;
	513
	514	if (ints & SPI_HOST_INT_UPDATE) {
	515	p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
	516	ret = p54spi_rx(priv);
	517	if (ret < 0)
	518	goto out;
	519	}
	520	if (ints & SPI_HOST_INT_SW_UPDATE) {
	521	p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
	522	ret = p54spi_rx(priv);
	523	if (ret < 0)
	524	goto out;
	525	}
	526
	527	ret = p54spi_wq_tx(priv);
cd8d3d32 CL	528	out:
	529	mutex_unlock(&priv->mutex);
	530	}
	531
	532	static int p54spi_op_start(struct ieee80211_hw *dev)
	533	{
	534	struct p54s_priv *priv = dev->priv;
	535	unsigned long timeout;
	536	int ret = 0;
	537
	538	if (mutex_lock_interruptible(&priv->mutex)) {
	539	ret = -EINTR;
	540	goto out;
	541	}
	542
	543	priv->fw_state = FW_STATE_BOOTING;
	544
	545	p54spi_power_on(priv);
	546
	547	ret = p54spi_upload_firmware(dev);
	548	if (ret < 0) {
	549	p54spi_power_off(priv);
	550	goto out_unlock;
	551	}
	552
	553	mutex_unlock(&priv->mutex);
	554
	555	timeout = msecs_to_jiffies(2000);
	556	timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
	557	timeout);
	558	if (!timeout) {
	559	dev_err(&priv->spi->dev, "firmware boot failed");
	560	p54spi_power_off(priv);
	561	ret = -1;
	562	goto out;
	563	}
	564
	565	if (mutex_lock_interruptible(&priv->mutex)) {
	566	ret = -EINTR;
	567	p54spi_power_off(priv);
	568	goto out;
	569	}
	570
	571	WARN_ON(priv->fw_state != FW_STATE_READY);
	572
	573	out_unlock:
	574	mutex_unlock(&priv->mutex);
	575
	576	out:
	577	return ret;
	578	}
	579
	580	static void p54spi_op_stop(struct ieee80211_hw *dev)
	581	{
	582	struct p54s_priv *priv = dev->priv;
731c6531	583	unsigned long flags;
cd8d3d32 CL	584
	585	if (mutex_lock_interruptible(&priv->mutex)) {
	586	/* FIXME: how to handle this error? */
	587	return;
	588	}
	589
	590	WARN_ON(priv->fw_state != FW_STATE_READY);
	591
	592	cancel_work_sync(&priv->work);
	593
	594	p54spi_power_off(priv);
731c6531	595	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32	596	INIT_LIST_HEAD(&priv->tx_pending);
731c6531	597	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	598
	599	priv->fw_state = FW_STATE_OFF;
	600	mutex_unlock(&priv->mutex);
	601	}
	602
	603	static int __devinit p54spi_probe(struct spi_device *spi)
	604	{
	605	struct p54s_priv *priv = NULL;
	606	struct ieee80211_hw *hw;
	607	int ret = -EINVAL;
	608
	609	hw = p54_init_common(sizeof(*priv));
	610	if (!hw) {
bfa99bfd	611	dev_err(&spi->dev, "could not alloc ieee80211_hw");
cd8d3d32 CL	612	return -ENOMEM;
	613	}
	614
	615	priv = hw->priv;
	616	priv->hw = hw;
	617	dev_set_drvdata(&spi->dev, priv);
	618	priv->spi = spi;
	619
cd8d3d32 CL	620	spi->bits_per_word = 16;
	621	spi->max_speed_hz = 24000000;
	622
	623	ret = spi_setup(spi);
	624	if (ret < 0) {
	625	dev_err(&priv->spi->dev, "spi_setup failed");
	626	goto err_free_common;
	627	}
	628
a2116993	629	ret = gpio_request(p54spi_gpio_power, "p54spi power");
cd8d3d32 CL	630	if (ret < 0) {
	631	dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
	632	goto err_free_common;
	633	}
	634
a2116993	635	ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
cd8d3d32 CL	636	if (ret < 0) {
	637	dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
	638	goto err_free_common;
	639	}
	640
a2116993 CL	641	gpio_direction_output(p54spi_gpio_power, 0);
a2116993 CL	642	gpio_direction_input(p54spi_gpio_irq);
cd8d3d32	643
a2116993	644	ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
cd8d3d32 CL	645	p54spi_interrupt, IRQF_DISABLED, "p54spi",
	646	priv->spi);
	647	if (ret < 0) {
	648	dev_err(&priv->spi->dev, "request_irq() failed");
	649	goto err_free_common;
	650	}
	651
dced35ae	652	irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);
cd8d3d32	653
a2116993	654	disable_irq(gpio_to_irq(p54spi_gpio_irq));
cd8d3d32 CL	655
	656	INIT_WORK(&priv->work, p54spi_work);
	657	init_completion(&priv->fw_comp);
	658	INIT_LIST_HEAD(&priv->tx_pending);
	659	mutex_init(&priv->mutex);
	660	SET_IEEE80211_DEV(hw, &spi->dev);
	661	priv->common.open = p54spi_op_start;
	662	priv->common.stop = p54spi_op_stop;
	663	priv->common.tx = p54spi_op_tx;
	664
	665	ret = p54spi_request_firmware(hw);
	666	if (ret < 0)
	667	goto err_free_common;
	668
	669	ret = p54spi_request_eeprom(hw);
	670	if (ret)
	671	goto err_free_common;
	672
2ac71072 CL	673	ret = p54_register_common(hw, &priv->spi->dev);
2ac71072 CL	674	if (ret)
cd8d3d32	675	goto err_free_common;
cd8d3d32	676
cd8d3d32 CL	677	return 0;
	678
	679	err_free_common:
	680	p54_free_common(priv->hw);
	681	return ret;
	682	}
	683
	684	static int __devexit p54spi_remove(struct spi_device *spi)
	685	{
	686	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
	687
d8c92107	688	p54_unregister_common(priv->hw);
cd8d3d32	689
a2116993	690	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
cd8d3d32	691
a2116993 CL	692	gpio_free(p54spi_gpio_power);
a2116993 CL	693	gpio_free(p54spi_gpio_irq);
cd8d3d32 CL	694	release_firmware(priv->firmware);
	695
	696	mutex_destroy(&priv->mutex);
	697
	698	p54_free_common(priv->hw);
cd8d3d32 CL	699
	700	return 0;
	701	}
	702
	703
	704	static struct spi_driver p54spi_driver = {
	705	.driver = {
5f1e83db	706	.name = "p54spi",
cd8d3d32 CL	707	.bus = &spi_bus_type,
	708	.owner = THIS_MODULE,
	709	},
	710
	711	.probe = p54spi_probe,
	712	.remove = __devexit_p(p54spi_remove),
	713	};
	714
	715	static int __init p54spi_init(void)
	716	{
	717	int ret;
	718
	719	ret = spi_register_driver(&p54spi_driver);
	720	if (ret < 0) {
	721	printk(KERN_ERR "failed to register SPI driver: %d", ret);
	722	goto out;
	723	}
	724
	725	out:
	726	return ret;
	727	}
	728
	729	static void __exit p54spi_exit(void)
	730	{
	731	spi_unregister_driver(&p54spi_driver);
	732	}
	733
	734	module_init(p54spi_init);
	735	module_exit(p54spi_exit);
	736
	737	MODULE_LICENSE("GPL");
	738	MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
e0626e38	739	MODULE_ALIAS("spi:cx3110x");
5f1e83db	740	MODULE_ALIAS("spi:p54spi");