Commit | Line | Data |
---|---|---|
eff1a59c MW |
1 | |
2 | /* | |
3 | * Linux device driver for PCI based Prism54 | |
4 | * | |
5 | * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> | |
7262d593 | 6 | * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de> |
eff1a59c MW |
7 | * |
8 | * Based on the islsm (softmac prism54) driver, which is: | |
9 | * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/pci.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
eff1a59c MW |
19 | #include <linux/firmware.h> |
20 | #include <linux/etherdevice.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/completion.h> | |
23 | #include <net/mac80211.h> | |
24 | ||
25 | #include "p54.h" | |
d8c92107 | 26 | #include "lmac.h" |
eff1a59c MW |
27 | #include "p54pci.h" |
28 | ||
29 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
30 | MODULE_DESCRIPTION("Prism54 PCI wireless driver"); | |
31 | MODULE_LICENSE("GPL"); | |
32 | MODULE_ALIAS("prism54pci"); | |
9a8675d7 | 33 | MODULE_FIRMWARE("isl3886pci"); |
eff1a59c | 34 | |
a3aa1884 | 35 | static DEFINE_PCI_DEVICE_TABLE(p54p_table) = { |
eff1a59c MW |
36 | /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */ |
37 | { PCI_DEVICE(0x1260, 0x3890) }, | |
38 | /* 3COM 3CRWE154G72 Wireless LAN adapter */ | |
39 | { PCI_DEVICE(0x10b7, 0x6001) }, | |
40 | /* Intersil PRISM Indigo Wireless LAN adapter */ | |
41 | { PCI_DEVICE(0x1260, 0x3877) }, | |
42 | /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */ | |
43 | { PCI_DEVICE(0x1260, 0x3886) }, | |
90f4dd0f | 44 | { }, |
eff1a59c MW |
45 | }; |
46 | ||
47 | MODULE_DEVICE_TABLE(pci, p54p_table); | |
48 | ||
49 | static int p54p_upload_firmware(struct ieee80211_hw *dev) | |
50 | { | |
51 | struct p54p_priv *priv = dev->priv; | |
eff1a59c MW |
52 | __le32 reg; |
53 | int err; | |
8160c031 | 54 | __le32 *data; |
eff1a59c MW |
55 | u32 remains, left, device_addr; |
56 | ||
8160c031 | 57 | P54P_WRITE(int_enable, cpu_to_le32(0)); |
eff1a59c MW |
58 | P54P_READ(int_enable); |
59 | udelay(10); | |
60 | ||
61 | reg = P54P_READ(ctrl_stat); | |
62 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); | |
63 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT); | |
64 | P54P_WRITE(ctrl_stat, reg); | |
65 | P54P_READ(ctrl_stat); | |
66 | udelay(10); | |
67 | ||
68 | reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET); | |
69 | P54P_WRITE(ctrl_stat, reg); | |
70 | wmb(); | |
71 | udelay(10); | |
72 | ||
73 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); | |
74 | P54P_WRITE(ctrl_stat, reg); | |
75 | wmb(); | |
76 | ||
40db0b22 CL |
77 | /* wait for the firmware to reset properly */ |
78 | mdelay(10); | |
eff1a59c | 79 | |
40db0b22 CL |
80 | err = p54_parse_firmware(dev, priv->firmware); |
81 | if (err) | |
4e416a6f | 82 | return err; |
eff1a59c | 83 | |
e365f160 CL |
84 | if (priv->common.fw_interface != FW_LM86) { |
85 | dev_err(&priv->pdev->dev, "wrong firmware, " | |
86 | "please get a LM86(PCI) firmware a try again.\n"); | |
87 | return -EINVAL; | |
88 | } | |
89 | ||
40db0b22 CL |
90 | data = (__le32 *) priv->firmware->data; |
91 | remains = priv->firmware->size; | |
eff1a59c MW |
92 | device_addr = ISL38XX_DEV_FIRMWARE_ADDR; |
93 | while (remains) { | |
94 | u32 i = 0; | |
95 | left = min((u32)0x1000, remains); | |
96 | P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr)); | |
97 | P54P_READ(int_enable); | |
98 | ||
99 | device_addr += 0x1000; | |
100 | while (i < left) { | |
101 | P54P_WRITE(direct_mem_win[i], *data++); | |
102 | i += sizeof(u32); | |
103 | } | |
104 | ||
105 | remains -= left; | |
106 | P54P_READ(int_enable); | |
107 | } | |
108 | ||
eff1a59c MW |
109 | reg = P54P_READ(ctrl_stat); |
110 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN); | |
111 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); | |
112 | reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT); | |
113 | P54P_WRITE(ctrl_stat, reg); | |
114 | P54P_READ(ctrl_stat); | |
115 | udelay(10); | |
116 | ||
117 | reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET); | |
118 | P54P_WRITE(ctrl_stat, reg); | |
119 | wmb(); | |
120 | udelay(10); | |
121 | ||
122 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); | |
123 | P54P_WRITE(ctrl_stat, reg); | |
124 | wmb(); | |
125 | udelay(10); | |
126 | ||
7cb77072 | 127 | /* wait for the firmware to boot properly */ |
eff1a59c | 128 | mdelay(100); |
eff1a59c | 129 | |
7cb77072 | 130 | return 0; |
eff1a59c MW |
131 | } |
132 | ||
7262d593 CL |
133 | static void p54p_refill_rx_ring(struct ieee80211_hw *dev, |
134 | int ring_index, struct p54p_desc *ring, u32 ring_limit, | |
135 | struct sk_buff **rx_buf) | |
eff1a59c MW |
136 | { |
137 | struct p54p_priv *priv = dev->priv; | |
eb76bf29 | 138 | struct p54p_ring_control *ring_control = priv->ring_control; |
7262d593 | 139 | u32 limit, idx, i; |
eff1a59c | 140 | |
7262d593 CL |
141 | idx = le32_to_cpu(ring_control->host_idx[ring_index]); |
142 | limit = idx; | |
143 | limit -= le32_to_cpu(ring_control->device_idx[ring_index]); | |
144 | limit = ring_limit - limit; | |
eff1a59c | 145 | |
7262d593 | 146 | i = idx % ring_limit; |
eff1a59c | 147 | while (limit-- > 1) { |
7262d593 | 148 | struct p54p_desc *desc = &ring[i]; |
eff1a59c MW |
149 | |
150 | if (!desc->host_addr) { | |
151 | struct sk_buff *skb; | |
152 | dma_addr_t mapping; | |
4e416a6f | 153 | skb = dev_alloc_skb(priv->common.rx_mtu + 32); |
eff1a59c MW |
154 | if (!skb) |
155 | break; | |
156 | ||
157 | mapping = pci_map_single(priv->pdev, | |
158 | skb_tail_pointer(skb), | |
4e416a6f | 159 | priv->common.rx_mtu + 32, |
eff1a59c | 160 | PCI_DMA_FROMDEVICE); |
288c8ce8 CL |
161 | |
162 | if (pci_dma_mapping_error(priv->pdev, mapping)) { | |
163 | dev_kfree_skb_any(skb); | |
164 | dev_err(&priv->pdev->dev, | |
165 | "RX DMA Mapping error\n"); | |
166 | break; | |
167 | } | |
168 | ||
eff1a59c MW |
169 | desc->host_addr = cpu_to_le32(mapping); |
170 | desc->device_addr = 0; // FIXME: necessary? | |
4e416a6f | 171 | desc->len = cpu_to_le16(priv->common.rx_mtu + 32); |
eff1a59c | 172 | desc->flags = 0; |
7262d593 | 173 | rx_buf[i] = skb; |
eff1a59c MW |
174 | } |
175 | ||
7262d593 | 176 | i++; |
eff1a59c | 177 | idx++; |
7262d593 | 178 | i %= ring_limit; |
eff1a59c MW |
179 | } |
180 | ||
181 | wmb(); | |
7262d593 CL |
182 | ring_control->host_idx[ring_index] = cpu_to_le32(idx); |
183 | } | |
184 | ||
185 | static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index, | |
186 | int ring_index, struct p54p_desc *ring, u32 ring_limit, | |
187 | struct sk_buff **rx_buf) | |
188 | { | |
189 | struct p54p_priv *priv = dev->priv; | |
190 | struct p54p_ring_control *ring_control = priv->ring_control; | |
191 | struct p54p_desc *desc; | |
192 | u32 idx, i; | |
193 | ||
194 | i = (*index) % ring_limit; | |
195 | (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]); | |
196 | idx %= ring_limit; | |
197 | while (i != idx) { | |
198 | u16 len; | |
199 | struct sk_buff *skb; | |
200 | desc = &ring[i]; | |
201 | len = le16_to_cpu(desc->len); | |
202 | skb = rx_buf[i]; | |
203 | ||
0c25970d CL |
204 | if (!skb) { |
205 | i++; | |
206 | i %= ring_limit; | |
7262d593 | 207 | continue; |
0c25970d | 208 | } |
f5300e04 CL |
209 | |
210 | if (unlikely(len > priv->common.rx_mtu)) { | |
211 | if (net_ratelimit()) | |
212 | dev_err(&priv->pdev->dev, "rx'd frame size " | |
213 | "exceeds length threshold.\n"); | |
214 | ||
215 | len = priv->common.rx_mtu; | |
216 | } | |
7262d593 CL |
217 | skb_put(skb, len); |
218 | ||
219 | if (p54_rx(dev, skb)) { | |
220 | pci_unmap_single(priv->pdev, | |
221 | le32_to_cpu(desc->host_addr), | |
4e416a6f CL |
222 | priv->common.rx_mtu + 32, |
223 | PCI_DMA_FROMDEVICE); | |
7262d593 CL |
224 | rx_buf[i] = NULL; |
225 | desc->host_addr = 0; | |
226 | } else { | |
227 | skb_trim(skb, 0); | |
4e416a6f | 228 | desc->len = cpu_to_le16(priv->common.rx_mtu + 32); |
7262d593 CL |
229 | } |
230 | ||
231 | i++; | |
232 | i %= ring_limit; | |
233 | } | |
234 | ||
235 | p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf); | |
236 | } | |
237 | ||
7262d593 CL |
238 | static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, |
239 | int ring_index, struct p54p_desc *ring, u32 ring_limit, | |
d713804c | 240 | struct sk_buff **tx_buf) |
7262d593 CL |
241 | { |
242 | struct p54p_priv *priv = dev->priv; | |
243 | struct p54p_ring_control *ring_control = priv->ring_control; | |
244 | struct p54p_desc *desc; | |
d713804c | 245 | struct sk_buff *skb; |
7262d593 CL |
246 | u32 idx, i; |
247 | ||
248 | i = (*index) % ring_limit; | |
249 | (*index) = idx = le32_to_cpu(ring_control->device_idx[1]); | |
250 | idx %= ring_limit; | |
251 | ||
252 | while (i != idx) { | |
253 | desc = &ring[i]; | |
d713804c CL |
254 | |
255 | skb = tx_buf[i]; | |
7262d593 CL |
256 | tx_buf[i] = NULL; |
257 | ||
258 | pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr), | |
259 | le16_to_cpu(desc->len), PCI_DMA_TODEVICE); | |
260 | ||
261 | desc->host_addr = 0; | |
262 | desc->device_addr = 0; | |
263 | desc->len = 0; | |
264 | desc->flags = 0; | |
265 | ||
b92f7d30 | 266 | if (skb && FREE_AFTER_TX(skb)) |
d713804c | 267 | p54_free_skb(dev, skb); |
d713804c | 268 | |
7262d593 CL |
269 | i++; |
270 | i %= ring_limit; | |
271 | } | |
272 | } | |
273 | ||
d713804c | 274 | static void p54p_tasklet(unsigned long dev_id) |
7262d593 CL |
275 | { |
276 | struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id; | |
277 | struct p54p_priv *priv = dev->priv; | |
278 | struct p54p_ring_control *ring_control = priv->ring_control; | |
279 | ||
d713804c CL |
280 | p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt, |
281 | ARRAY_SIZE(ring_control->tx_mgmt), | |
282 | priv->tx_buf_mgmt); | |
283 | ||
284 | p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data, | |
285 | ARRAY_SIZE(ring_control->tx_data), | |
286 | priv->tx_buf_data); | |
287 | ||
7262d593 CL |
288 | p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt, |
289 | ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt); | |
290 | ||
291 | p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data, | |
292 | ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data); | |
293 | ||
294 | wmb(); | |
295 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); | |
eff1a59c MW |
296 | } |
297 | ||
298 | static irqreturn_t p54p_interrupt(int irq, void *dev_id) | |
299 | { | |
300 | struct ieee80211_hw *dev = dev_id; | |
301 | struct p54p_priv *priv = dev->priv; | |
302 | __le32 reg; | |
303 | ||
eff1a59c | 304 | reg = P54P_READ(int_ident); |
8160c031 | 305 | if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) { |
d713804c | 306 | goto out; |
eff1a59c | 307 | } |
eff1a59c MW |
308 | P54P_WRITE(int_ack, reg); |
309 | ||
310 | reg &= P54P_READ(int_enable); | |
311 | ||
d713804c CL |
312 | if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) |
313 | tasklet_schedule(&priv->tasklet); | |
314 | else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT)) | |
eff1a59c MW |
315 | complete(&priv->boot_comp); |
316 | ||
d713804c | 317 | out: |
eff1a59c MW |
318 | return reg ? IRQ_HANDLED : IRQ_NONE; |
319 | } | |
320 | ||
0a5ec96a | 321 | static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb) |
eff1a59c | 322 | { |
b92f7d30 | 323 | unsigned long flags; |
eff1a59c | 324 | struct p54p_priv *priv = dev->priv; |
eb76bf29 | 325 | struct p54p_ring_control *ring_control = priv->ring_control; |
eff1a59c MW |
326 | struct p54p_desc *desc; |
327 | dma_addr_t mapping; | |
328 | u32 device_idx, idx, i; | |
329 | ||
330 | spin_lock_irqsave(&priv->lock, flags); | |
eb76bf29 DT |
331 | device_idx = le32_to_cpu(ring_control->device_idx[1]); |
332 | idx = le32_to_cpu(ring_control->host_idx[1]); | |
333 | i = idx % ARRAY_SIZE(ring_control->tx_data); | |
eff1a59c | 334 | |
b92f30d6 CL |
335 | mapping = pci_map_single(priv->pdev, skb->data, skb->len, |
336 | PCI_DMA_TODEVICE); | |
288c8ce8 CL |
337 | if (pci_dma_mapping_error(priv->pdev, mapping)) { |
338 | spin_unlock_irqrestore(&priv->lock, flags); | |
339 | p54_free_skb(dev, skb); | |
340 | dev_err(&priv->pdev->dev, "TX DMA mapping error\n"); | |
341 | return ; | |
342 | } | |
343 | priv->tx_buf_data[i] = skb; | |
344 | ||
eb76bf29 | 345 | desc = &ring_control->tx_data[i]; |
eff1a59c | 346 | desc->host_addr = cpu_to_le32(mapping); |
27df605e | 347 | desc->device_addr = ((struct p54_hdr *)skb->data)->req_id; |
b92f30d6 | 348 | desc->len = cpu_to_le16(skb->len); |
eff1a59c MW |
349 | desc->flags = 0; |
350 | ||
351 | wmb(); | |
eb76bf29 | 352 | ring_control->host_idx[1] = cpu_to_le32(idx + 1); |
eff1a59c MW |
353 | spin_unlock_irqrestore(&priv->lock, flags); |
354 | ||
355 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); | |
356 | P54P_READ(dev_int); | |
eff1a59c MW |
357 | } |
358 | ||
eff1a59c MW |
359 | static void p54p_stop(struct ieee80211_hw *dev) |
360 | { | |
361 | struct p54p_priv *priv = dev->priv; | |
eb76bf29 | 362 | struct p54p_ring_control *ring_control = priv->ring_control; |
eff1a59c MW |
363 | unsigned int i; |
364 | struct p54p_desc *desc; | |
365 | ||
8160c031 | 366 | P54P_WRITE(int_enable, cpu_to_le32(0)); |
eff1a59c MW |
367 | P54P_READ(int_enable); |
368 | udelay(10); | |
369 | ||
370 | free_irq(priv->pdev->irq, dev); | |
371 | ||
b92f7d30 CL |
372 | tasklet_kill(&priv->tasklet); |
373 | ||
eff1a59c MW |
374 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET)); |
375 | ||
7262d593 | 376 | for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) { |
eb76bf29 | 377 | desc = &ring_control->rx_data[i]; |
eff1a59c | 378 | if (desc->host_addr) |
7262d593 CL |
379 | pci_unmap_single(priv->pdev, |
380 | le32_to_cpu(desc->host_addr), | |
4e416a6f CL |
381 | priv->common.rx_mtu + 32, |
382 | PCI_DMA_FROMDEVICE); | |
7262d593 CL |
383 | kfree_skb(priv->rx_buf_data[i]); |
384 | priv->rx_buf_data[i] = NULL; | |
eff1a59c MW |
385 | } |
386 | ||
7262d593 CL |
387 | for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) { |
388 | desc = &ring_control->rx_mgmt[i]; | |
389 | if (desc->host_addr) | |
390 | pci_unmap_single(priv->pdev, | |
391 | le32_to_cpu(desc->host_addr), | |
4e416a6f CL |
392 | priv->common.rx_mtu + 32, |
393 | PCI_DMA_FROMDEVICE); | |
7262d593 CL |
394 | kfree_skb(priv->rx_buf_mgmt[i]); |
395 | priv->rx_buf_mgmt[i] = NULL; | |
396 | } | |
397 | ||
398 | for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) { | |
eb76bf29 | 399 | desc = &ring_control->tx_data[i]; |
eff1a59c | 400 | if (desc->host_addr) |
7262d593 CL |
401 | pci_unmap_single(priv->pdev, |
402 | le32_to_cpu(desc->host_addr), | |
403 | le16_to_cpu(desc->len), | |
404 | PCI_DMA_TODEVICE); | |
405 | ||
b92f30d6 | 406 | p54_free_skb(dev, priv->tx_buf_data[i]); |
7262d593 CL |
407 | priv->tx_buf_data[i] = NULL; |
408 | } | |
409 | ||
410 | for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) { | |
411 | desc = &ring_control->tx_mgmt[i]; | |
412 | if (desc->host_addr) | |
413 | pci_unmap_single(priv->pdev, | |
414 | le32_to_cpu(desc->host_addr), | |
415 | le16_to_cpu(desc->len), | |
416 | PCI_DMA_TODEVICE); | |
eff1a59c | 417 | |
b92f30d6 | 418 | p54_free_skb(dev, priv->tx_buf_mgmt[i]); |
7262d593 | 419 | priv->tx_buf_mgmt[i] = NULL; |
eff1a59c MW |
420 | } |
421 | ||
7262d593 | 422 | memset(ring_control, 0, sizeof(*ring_control)); |
eff1a59c MW |
423 | } |
424 | ||
35961627 CL |
425 | static int p54p_open(struct ieee80211_hw *dev) |
426 | { | |
427 | struct p54p_priv *priv = dev->priv; | |
428 | int err; | |
429 | ||
430 | init_completion(&priv->boot_comp); | |
8fbd90b0 | 431 | err = request_irq(priv->pdev->irq, p54p_interrupt, |
35961627 CL |
432 | IRQF_SHARED, "p54pci", dev); |
433 | if (err) { | |
ad5e72ee | 434 | dev_err(&priv->pdev->dev, "failed to register IRQ handler\n"); |
35961627 CL |
435 | return err; |
436 | } | |
437 | ||
438 | memset(priv->ring_control, 0, sizeof(*priv->ring_control)); | |
439 | err = p54p_upload_firmware(dev); | |
440 | if (err) { | |
441 | free_irq(priv->pdev->irq, dev); | |
442 | return err; | |
443 | } | |
444 | priv->rx_idx_data = priv->tx_idx_data = 0; | |
445 | priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0; | |
446 | ||
447 | p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data, | |
448 | ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data); | |
449 | ||
450 | p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt, | |
451 | ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt); | |
452 | ||
453 | P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma)); | |
454 | P54P_READ(ring_control_base); | |
455 | wmb(); | |
456 | udelay(10); | |
457 | ||
458 | P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT)); | |
459 | P54P_READ(int_enable); | |
460 | wmb(); | |
461 | udelay(10); | |
462 | ||
463 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET)); | |
464 | P54P_READ(dev_int); | |
465 | ||
466 | if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) { | |
467 | printk(KERN_ERR "%s: Cannot boot firmware!\n", | |
468 | wiphy_name(dev->wiphy)); | |
469 | p54p_stop(dev); | |
470 | return -ETIMEDOUT; | |
471 | } | |
472 | ||
473 | P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)); | |
474 | P54P_READ(int_enable); | |
475 | wmb(); | |
476 | udelay(10); | |
477 | ||
478 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); | |
479 | P54P_READ(dev_int); | |
480 | wmb(); | |
481 | udelay(10); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
eff1a59c MW |
486 | static int __devinit p54p_probe(struct pci_dev *pdev, |
487 | const struct pci_device_id *id) | |
488 | { | |
489 | struct p54p_priv *priv; | |
490 | struct ieee80211_hw *dev; | |
491 | unsigned long mem_addr, mem_len; | |
492 | int err; | |
eff1a59c MW |
493 | |
494 | err = pci_enable_device(pdev); | |
495 | if (err) { | |
ad5e72ee | 496 | dev_err(&pdev->dev, "Cannot enable new PCI device\n"); |
eff1a59c MW |
497 | return err; |
498 | } | |
499 | ||
500 | mem_addr = pci_resource_start(pdev, 0); | |
501 | mem_len = pci_resource_len(pdev, 0); | |
502 | if (mem_len < sizeof(struct p54p_csr)) { | |
ad5e72ee | 503 | dev_err(&pdev->dev, "Too short PCI resources\n"); |
40db0b22 | 504 | goto err_disable_dev; |
eff1a59c MW |
505 | } |
506 | ||
32ddf071 | 507 | err = pci_request_regions(pdev, "p54pci"); |
eff1a59c | 508 | if (err) { |
ad5e72ee | 509 | dev_err(&pdev->dev, "Cannot obtain PCI resources\n"); |
40db0b22 | 510 | goto err_disable_dev; |
eff1a59c MW |
511 | } |
512 | ||
e930438c YH |
513 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) || |
514 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
ad5e72ee | 515 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
eff1a59c MW |
516 | goto err_free_reg; |
517 | } | |
518 | ||
519 | pci_set_master(pdev); | |
520 | pci_try_set_mwi(pdev); | |
521 | ||
522 | pci_write_config_byte(pdev, 0x40, 0); | |
523 | pci_write_config_byte(pdev, 0x41, 0); | |
524 | ||
525 | dev = p54_init_common(sizeof(*priv)); | |
526 | if (!dev) { | |
ad5e72ee | 527 | dev_err(&pdev->dev, "ieee80211 alloc failed\n"); |
eff1a59c MW |
528 | err = -ENOMEM; |
529 | goto err_free_reg; | |
530 | } | |
531 | ||
532 | priv = dev->priv; | |
533 | priv->pdev = pdev; | |
534 | ||
535 | SET_IEEE80211_DEV(dev, &pdev->dev); | |
536 | pci_set_drvdata(pdev, dev); | |
537 | ||
538 | priv->map = ioremap(mem_addr, mem_len); | |
539 | if (!priv->map) { | |
ad5e72ee CL |
540 | dev_err(&pdev->dev, "Cannot map device memory\n"); |
541 | err = -ENOMEM; | |
eff1a59c MW |
542 | goto err_free_dev; |
543 | } | |
544 | ||
545 | priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control), | |
546 | &priv->ring_control_dma); | |
547 | if (!priv->ring_control) { | |
ad5e72ee | 548 | dev_err(&pdev->dev, "Cannot allocate rings\n"); |
eff1a59c MW |
549 | err = -ENOMEM; |
550 | goto err_iounmap; | |
551 | } | |
eff1a59c MW |
552 | priv->common.open = p54p_open; |
553 | priv->common.stop = p54p_stop; | |
554 | priv->common.tx = p54p_tx; | |
555 | ||
556 | spin_lock_init(&priv->lock); | |
d713804c | 557 | tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev); |
eff1a59c | 558 | |
40db0b22 CL |
559 | err = request_firmware(&priv->firmware, "isl3886pci", |
560 | &priv->pdev->dev); | |
561 | if (err) { | |
ad5e72ee | 562 | dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n"); |
40db0b22 CL |
563 | err = request_firmware(&priv->firmware, "isl3886", |
564 | &priv->pdev->dev); | |
565 | if (err) | |
566 | goto err_free_common; | |
567 | } | |
568 | ||
35961627 CL |
569 | err = p54p_open(dev); |
570 | if (err) | |
571 | goto err_free_common; | |
7cb77072 CL |
572 | err = p54_read_eeprom(dev); |
573 | p54p_stop(dev); | |
574 | if (err) | |
35961627 | 575 | goto err_free_common; |
7cb77072 | 576 | |
2ac71072 CL |
577 | err = p54_register_common(dev, &pdev->dev); |
578 | if (err) | |
eff1a59c | 579 | goto err_free_common; |
eff1a59c | 580 | |
eff1a59c MW |
581 | return 0; |
582 | ||
583 | err_free_common: | |
40db0b22 | 584 | release_firmware(priv->firmware); |
eff1a59c MW |
585 | pci_free_consistent(pdev, sizeof(*priv->ring_control), |
586 | priv->ring_control, priv->ring_control_dma); | |
587 | ||
588 | err_iounmap: | |
589 | iounmap(priv->map); | |
590 | ||
591 | err_free_dev: | |
592 | pci_set_drvdata(pdev, NULL); | |
d8c92107 | 593 | p54_free_common(dev); |
eff1a59c MW |
594 | |
595 | err_free_reg: | |
596 | pci_release_regions(pdev); | |
40db0b22 | 597 | err_disable_dev: |
eff1a59c MW |
598 | pci_disable_device(pdev); |
599 | return err; | |
600 | } | |
601 | ||
602 | static void __devexit p54p_remove(struct pci_dev *pdev) | |
603 | { | |
604 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
605 | struct p54p_priv *priv; | |
606 | ||
607 | if (!dev) | |
608 | return; | |
609 | ||
d8c92107 | 610 | p54_unregister_common(dev); |
eff1a59c | 611 | priv = dev->priv; |
40db0b22 | 612 | release_firmware(priv->firmware); |
eff1a59c MW |
613 | pci_free_consistent(pdev, sizeof(*priv->ring_control), |
614 | priv->ring_control, priv->ring_control_dma); | |
eff1a59c MW |
615 | iounmap(priv->map); |
616 | pci_release_regions(pdev); | |
617 | pci_disable_device(pdev); | |
d8c92107 | 618 | p54_free_common(dev); |
eff1a59c MW |
619 | } |
620 | ||
621 | #ifdef CONFIG_PM | |
622 | static int p54p_suspend(struct pci_dev *pdev, pm_message_t state) | |
623 | { | |
624 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
625 | struct p54p_priv *priv = dev->priv; | |
626 | ||
05c914fe | 627 | if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) { |
eff1a59c MW |
628 | ieee80211_stop_queues(dev); |
629 | p54p_stop(dev); | |
630 | } | |
631 | ||
632 | pci_save_state(pdev); | |
633 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
634 | return 0; | |
635 | } | |
636 | ||
637 | static int p54p_resume(struct pci_dev *pdev) | |
638 | { | |
639 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
640 | struct p54p_priv *priv = dev->priv; | |
641 | ||
642 | pci_set_power_state(pdev, PCI_D0); | |
643 | pci_restore_state(pdev); | |
644 | ||
05c914fe | 645 | if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) { |
eff1a59c | 646 | p54p_open(dev); |
36d6825b | 647 | ieee80211_wake_queues(dev); |
eff1a59c MW |
648 | } |
649 | ||
650 | return 0; | |
651 | } | |
652 | #endif /* CONFIG_PM */ | |
653 | ||
654 | static struct pci_driver p54p_driver = { | |
32ddf071 | 655 | .name = "p54pci", |
eff1a59c MW |
656 | .id_table = p54p_table, |
657 | .probe = p54p_probe, | |
658 | .remove = __devexit_p(p54p_remove), | |
659 | #ifdef CONFIG_PM | |
660 | .suspend = p54p_suspend, | |
661 | .resume = p54p_resume, | |
662 | #endif /* CONFIG_PM */ | |
663 | }; | |
664 | ||
665 | static int __init p54p_init(void) | |
666 | { | |
667 | return pci_register_driver(&p54p_driver); | |
668 | } | |
669 | ||
670 | static void __exit p54p_exit(void) | |
671 | { | |
672 | pci_unregister_driver(&p54p_driver); | |
673 | } | |
674 | ||
675 | module_init(p54p_init); | |
676 | module_exit(p54p_exit); |