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net: convert print_mac to %pM
[linux-2.6-block.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW		 1
2/*
3 * Common code for mac80211 Prism54 drivers
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/firmware.h>
18#include <linux/etherdevice.h>
19
20#include <net/mac80211.h>
21
22#include "p54.h"
23#include "p54common.h"
24
25MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
26MODULE_DESCRIPTION("Softmac Prism54 common code");
27MODULE_LICENSE("GPL");
28MODULE_ALIAS("prism54common");
29
1b997534 30static struct ieee80211_rate p54_bgrates[] = {
8318d78a
JB		 31 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
32 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
33 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
34 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
35 { .bitrate = 60, .hw_value = 4, },
36 { .bitrate = 90, .hw_value = 5, },
37 { .bitrate = 120, .hw_value = 6, },
38 { .bitrate = 180, .hw_value = 7, },
39 { .bitrate = 240, .hw_value = 8, },
40 { .bitrate = 360, .hw_value = 9, },
41 { .bitrate = 480, .hw_value = 10, },
42 { .bitrate = 540, .hw_value = 11, },
43};
44
1b997534 45static struct ieee80211_channel p54_bgchannels[] = {
8318d78a
JB		 46 { .center_freq = 2412, .hw_value = 1, },
47 { .center_freq = 2417, .hw_value = 2, },
48 { .center_freq = 2422, .hw_value = 3, },
49 { .center_freq = 2427, .hw_value = 4, },
50 { .center_freq = 2432, .hw_value = 5, },
51 { .center_freq = 2437, .hw_value = 6, },
52 { .center_freq = 2442, .hw_value = 7, },
53 { .center_freq = 2447, .hw_value = 8, },
54 { .center_freq = 2452, .hw_value = 9, },
55 { .center_freq = 2457, .hw_value = 10, },
56 { .center_freq = 2462, .hw_value = 11, },
57 { .center_freq = 2467, .hw_value = 12, },
58 { .center_freq = 2472, .hw_value = 13, },
59 { .center_freq = 2484, .hw_value = 14, },
60};
61
c2976ab0 62static struct ieee80211_supported_band band_2GHz = {
1b997534
CL		 63 .channels = p54_bgchannels,
64 .n_channels = ARRAY_SIZE(p54_bgchannels),
65 .bitrates = p54_bgrates,
66 .n_bitrates = ARRAY_SIZE(p54_bgrates),
67};
68
69static struct ieee80211_rate p54_arates[] = {
70 { .bitrate = 60, .hw_value = 4, },
71 { .bitrate = 90, .hw_value = 5, },
72 { .bitrate = 120, .hw_value = 6, },
73 { .bitrate = 180, .hw_value = 7, },
74 { .bitrate = 240, .hw_value = 8, },
75 { .bitrate = 360, .hw_value = 9, },
76 { .bitrate = 480, .hw_value = 10, },
77 { .bitrate = 540, .hw_value = 11, },
78};
79
80static struct ieee80211_channel p54_achannels[] = {
81 { .center_freq = 4920 },
82 { .center_freq = 4940 },
83 { .center_freq = 4960 },
84 { .center_freq = 4980 },
85 { .center_freq = 5040 },
86 { .center_freq = 5060 },
87 { .center_freq = 5080 },
88 { .center_freq = 5170 },
89 { .center_freq = 5180 },
90 { .center_freq = 5190 },
91 { .center_freq = 5200 },
92 { .center_freq = 5210 },
93 { .center_freq = 5220 },
94 { .center_freq = 5230 },
95 { .center_freq = 5240 },
96 { .center_freq = 5260 },
97 { .center_freq = 5280 },
98 { .center_freq = 5300 },
99 { .center_freq = 5320 },
100 { .center_freq = 5500 },
101 { .center_freq = 5520 },
102 { .center_freq = 5540 },
103 { .center_freq = 5560 },
104 { .center_freq = 5580 },
105 { .center_freq = 5600 },
106 { .center_freq = 5620 },
107 { .center_freq = 5640 },
108 { .center_freq = 5660 },
109 { .center_freq = 5680 },
110 { .center_freq = 5700 },
111 { .center_freq = 5745 },
112 { .center_freq = 5765 },
113 { .center_freq = 5785 },
114 { .center_freq = 5805 },
115 { .center_freq = 5825 },
116};
117
118static struct ieee80211_supported_band band_5GHz = {
119 .channels = p54_achannels,
120 .n_channels = ARRAY_SIZE(p54_achannels),
121 .bitrates = p54_arates,
122 .n_bitrates = ARRAY_SIZE(p54_arates),
8318d78a
JB		 123};
124
4e416a6f 125int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
eff1a59c
MW		 126{
127 struct p54_common *priv = dev->priv;
128 struct bootrec_exp_if *exp_if;
129 struct bootrec *bootrec;
130 u32 *data = (u32 *)fw->data;
131 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
132 u8 *fw_version = NULL;
133 size_t len;
134 int i;
135
136 if (priv->rx_start)
4e416a6f 137 return 0;
eff1a59c
MW		 138
139 while (data < end_data && *data)
140 data++;
141
142 while (data < end_data && !*data)
143 data++;
144
145 bootrec = (struct bootrec *) data;
146
147 while (bootrec->data <= end_data &&
148 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
149 u32 code = le32_to_cpu(bootrec->code);
150 switch (code) {
151 case BR_CODE_COMPONENT_ID:
1f1c0e33
LF		 152 priv->fw_interface = be32_to_cpup((__be32 *)
153 bootrec->data);
2b80848e 154 switch (priv->fw_interface) {
eff1a59c
MW		 155 case FW_FMAC:
156 printk(KERN_INFO "p54: FreeMAC firmware\n");
157 break;
158 case FW_LM20:
159 printk(KERN_INFO "p54: LM20 firmware\n");
160 break;
161 case FW_LM86:
162 printk(KERN_INFO "p54: LM86 firmware\n");
163 break;
164 case FW_LM87:
2b80848e 165 printk(KERN_INFO "p54: LM87 firmware\n");
eff1a59c
MW		 166 break;
167 default:
168 printk(KERN_INFO "p54: unknown firmware\n");
169 break;
170 }
171 break;
172 case BR_CODE_COMPONENT_VERSION:
173 /* 24 bytes should be enough for all firmwares */
174 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
175 fw_version = (unsigned char*)bootrec->data;
176 break;
4e416a6f
CL		 177 case BR_CODE_DESCR: {
178 struct bootrec_desc *desc =
179 (struct bootrec_desc *)bootrec->data;
180 priv->rx_start = le32_to_cpu(desc->rx_start);
eff1a59c 181 /* FIXME add sanity checking */
4e416a6f
CL		 182 priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
183 priv->headroom = desc->headroom;
184 priv->tailroom = desc->tailroom;
1f1c0e33
LF		 185 if (le32_to_cpu(bootrec->len) == 11)
186 priv->rx_mtu = le16_to_cpu(bootrec->rx_mtu);
4e416a6f
CL		 187 else
188 priv->rx_mtu = (size_t)
189 0x620 - priv->tx_hdr_len;
eff1a59c 190 break;
4e416a6f 191 }
eff1a59c
MW		 192 case BR_CODE_EXPOSED_IF:
193 exp_if = (struct bootrec_exp_if *) bootrec->data;
194 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 195 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW		 196 priv->fw_var = le16_to_cpu(exp_if[i].variant);
197 break;
198 case BR_CODE_DEPENDENT_IF:
199 break;
200 case BR_CODE_END_OF_BRA:
201 case LEGACY_BR_CODE_END_OF_BRA:
202 end_data = NULL;
203 break;
204 default:
205 break;
206 }
207 bootrec = (struct bootrec *)&bootrec->data[len];
208 }
209
210 if (fw_version)
211 printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
212 fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
213
214 if (priv->fw_var >= 0x300) {
215 /* Firmware supports QoS, use it! */
84df3ed3
C		 216 priv->tx_stats[4].limit = 3;
217 priv->tx_stats[5].limit = 4;
218 priv->tx_stats[6].limit = 3;
219 priv->tx_stats[7].limit = 1;
eff1a59c
MW		 220 dev->queues = 4;
221 }
4e416a6f
CL		 222
223 return 0;
eff1a59c
MW		 224}
225EXPORT_SYMBOL_GPL(p54_parse_firmware);
226
154e3af1
CL		 227static int p54_convert_rev0(struct ieee80211_hw *dev,
228 struct pda_pa_curve_data *curve_data)
eff1a59c
MW		 229{
230 struct p54_common *priv = dev->priv;
154e3af1
CL		 231 struct p54_pa_curve_data_sample *dst;
232 struct pda_pa_curve_data_sample_rev0 *src;
eff1a59c 233 size_t cd_len = sizeof(*curve_data) +
154e3af1 234 (curve_data->points_per_channel*sizeof(*dst) + 2) *
eff1a59c
MW		 235 curve_data->channels;
236 unsigned int i, j;
237 void *source, *target;
238
239 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
240 if (!priv->curve_data)
241 return -ENOMEM;
242
243 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
244 source = curve_data->data;
245 target = priv->curve_data->data;
246 for (i = 0; i < curve_data->channels; i++) {
247 __le16 *freq = source;
248 source += sizeof(__le16);
249 *((__le16 *)target) = *freq;
250 target += sizeof(__le16);
251 for (j = 0; j < curve_data->points_per_channel; j++) {
154e3af1
CL		 252 dst = target;
253 src = source;
eff1a59c 254
154e3af1
CL		 255 dst->rf_power = src->rf_power;
256 dst->pa_detector = src->pa_detector;
257 dst->data_64qam = src->pcv;
eff1a59c
MW		 258 /* "invent" the points for the other modulations */
259#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
154e3af1
CL		 260 dst->data_16qam = SUB(src->pcv, 12);
261 dst->data_qpsk = SUB(dst->data_16qam, 12);
262 dst->data_bpsk = SUB(dst->data_qpsk, 12);
263 dst->data_barker = SUB(dst->data_bpsk, 14);
eff1a59c 264#undef SUB
154e3af1
CL		 265 target += sizeof(*dst);
266 source += sizeof(*src);
eff1a59c
MW		 267 }
268 }
269
270 return 0;
271}
272
154e3af1
CL		 273static int p54_convert_rev1(struct ieee80211_hw *dev,
274 struct pda_pa_curve_data *curve_data)
275{
276 struct p54_common *priv = dev->priv;
277 struct p54_pa_curve_data_sample *dst;
278 struct pda_pa_curve_data_sample_rev1 *src;
279 size_t cd_len = sizeof(*curve_data) +
280 (curve_data->points_per_channel*sizeof(*dst) + 2) *
281 curve_data->channels;
282 unsigned int i, j;
283 void *source, *target;
284
285 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
286 if (!priv->curve_data)
287 return -ENOMEM;
288
289 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
290 source = curve_data->data;
291 target = priv->curve_data->data;
292 for (i = 0; i < curve_data->channels; i++) {
293 __le16 *freq = source;
294 source += sizeof(__le16);
295 *((__le16 *)target) = *freq;
296 target += sizeof(__le16);
297 for (j = 0; j < curve_data->points_per_channel; j++) {
298 memcpy(target, source, sizeof(*src));
299
300 target += sizeof(*dst);
301 source += sizeof(*src);
302 }
303 source++;
304 }
305
306 return 0;
307}
308
4cc683c9
CL		 309static const char *p54_rf_chips[] = { "NULL", "Duette3", "Duette2",
310 "Frisbee", "Xbow", "Longbow", "NULL", "NULL" };
1b997534 311static int p54_init_xbow_synth(struct ieee80211_hw *dev);
7cb77072 312
1f1c0e33 313static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
eff1a59c
MW		 314{
315 struct p54_common *priv = dev->priv;
316 struct eeprom_pda_wrap *wrap = NULL;
317 struct pda_entry *entry;
eff1a59c
MW		 318 unsigned int data_len, entry_len;
319 void *tmp;
320 int err;
c2f2d3a0 321 u8 *end = (u8 *)eeprom + len;
4cc683c9 322 u16 synth;
eff1a59c
MW		 323
324 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 325 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB		 326
327 /* verify that at least the entry length/code fits */
328 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW		 329 entry_len = le16_to_cpu(entry->len);
330 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB		 331
332 /* abort if entry exceeds whole structure */
333 if ((u8 *)entry + sizeof(*entry) + data_len > end)
334 break;
335
eff1a59c
MW		 336 switch (le16_to_cpu(entry->code)) {
337 case PDR_MAC_ADDRESS:
338 SET_IEEE80211_PERM_ADDR(dev, entry->data);
339 break;
340 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
341 if (data_len < 2) {
342 err = -EINVAL;
343 goto err;
344 }
345
346 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
347 err = -EINVAL;
348 goto err;
349 }
350
351 priv->output_limit = kmalloc(entry->data[1] *
352 sizeof(*priv->output_limit), GFP_KERNEL);
353
354 if (!priv->output_limit) {
355 err = -ENOMEM;
356 goto err;
357 }
358
359 memcpy(priv->output_limit, &entry->data[2],
360 entry->data[1]*sizeof(*priv->output_limit));
361 priv->output_limit_len = entry->data[1];
362 break;
154e3af1
CL		 363 case PDR_PRISM_PA_CAL_CURVE_DATA: {
364 struct pda_pa_curve_data *curve_data =
365 (struct pda_pa_curve_data *)entry->data;
366 if (data_len < sizeof(*curve_data)) {
eff1a59c
MW		 367 err = -EINVAL;
368 goto err;
369 }
370
154e3af1
CL		 371 switch (curve_data->cal_method_rev) {
372 case 0:
373 err = p54_convert_rev0(dev, curve_data);
374 break;
375 case 1:
376 err = p54_convert_rev1(dev, curve_data);
377 break;
378 default:
379 printk(KERN_ERR "p54: unknown curve data "
380 "revision %d\n",
381 curve_data->cal_method_rev);
382 err = -ENODEV;
383 break;
eff1a59c 384 }
154e3af1
CL		 385 if (err)
386 goto err;
eff1a59c 387
154e3af1 388 }
eff1a59c
MW		 389 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
390 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
391 if (!priv->iq_autocal) {
392 err = -ENOMEM;
393 goto err;
394 }
395
396 memcpy(priv->iq_autocal, entry->data, data_len);
397 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
398 break;
399 case PDR_INTERFACE_LIST:
400 tmp = entry->data;
401 while ((u8 *)tmp < entry->data + data_len) {
402 struct bootrec_exp_if *exp_if = tmp;
4cc683c9
CL		 403 if (le16_to_cpu(exp_if->if_id) == 0xf)
404 synth = le16_to_cpu(exp_if->variant);
eff1a59c
MW		 405 tmp += sizeof(struct bootrec_exp_if);
406 }
407 break;
408 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
409 priv->version = *(u8 *)(entry->data + 1);
410 break;
411 case PDR_END:
c2f2d3a0
JB		 412 /* make it overrun */
413 entry_len = len;
eff1a59c 414 break;
58e30739
FF		 415 default:
416 printk(KERN_INFO "p54: unknown eeprom code : 0x%x\n",
417 le16_to_cpu(entry->code));
418 break;
eff1a59c
MW		 419 }
420
421 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW		 422 }
423
424 if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) {
425 printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
426 err = -EINVAL;
427 goto err;
428 }
429
4cc683c9
CL		 430 priv->rxhw = synth & 0x07;
431 if (priv->rxhw == 4)
1b997534 432 p54_init_xbow_synth(dev);
4cc683c9 433 if (!(synth & 0x40))
1b997534 434 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
4cc683c9
CL		 435 if (!(synth & 0x80))
436 dev->wiphy->bands[IEEE80211_BAND_5GHZ] = &band_5GHz;
7cb77072
CL		 437
438 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
439 u8 perm_addr[ETH_ALEN];
440
441 printk(KERN_WARNING "%s: Invalid hwaddr! Using randomly generated MAC addr\n",
442 wiphy_name(dev->wiphy));
443 random_ether_addr(perm_addr);
444 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
445 }
446
e174961c 447 printk(KERN_INFO "%s: hwaddr %pM, MAC:isl38%02x RF:%s\n",
7cb77072 448 wiphy_name(dev->wiphy),
e174961c 449 dev->wiphy->perm_addr,
7cb77072
CL		 450 priv->version, p54_rf_chips[priv->rxhw]);
451
eff1a59c
MW		 452 return 0;
453
454 err:
455 if (priv->iq_autocal) {
456 kfree(priv->iq_autocal);
457 priv->iq_autocal = NULL;
458 }
459
460 if (priv->output_limit) {
461 kfree(priv->output_limit);
462 priv->output_limit = NULL;
463 }
464
465 if (priv->curve_data) {
466 kfree(priv->curve_data);
467 priv->curve_data = NULL;
468 }
469
470 printk(KERN_ERR "p54: eeprom parse failed!\n");
471 return err;
472}
eff1a59c 473
cc6de669
CL		 474static int p54_rssi_to_dbm(struct ieee80211_hw *dev, int rssi)
475{
476 /* TODO: get the rssi_add & rssi_mul data from the eeprom */
477 return ((rssi * 0x83) / 64 - 400) / 4;
478}
479
19c19d54 480static int p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 481{
a0db663f 482 struct p54_common *priv = dev->priv;
eff1a59c
MW		 483 struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data;
484 struct ieee80211_rx_status rx_status = {0};
485 u16 freq = le16_to_cpu(hdr->freq);
19c19d54 486 size_t header_len = sizeof(*hdr);
a0db663f 487 u32 tsf32;
eff1a59c 488
78d57eb2
CL		 489 if (!(hdr->magic & cpu_to_le16(0x0001))) {
490 if (priv->filter_flags & FIF_FCSFAIL)
491 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
492 else
493 return 0;
494 }
495
cc6de669
CL		 496 rx_status.signal = p54_rssi_to_dbm(dev, hdr->rssi);
497 rx_status.noise = priv->noise;
8318d78a 498 /* XX correct? */
18d72605 499 rx_status.qual = (100 * hdr->rssi) / 127;
cf3e74c2
CL		 500 rx_status.rate_idx = (dev->conf.channel->band == IEEE80211_BAND_2GHZ ?
501 hdr->rate : (hdr->rate - 4)) & 0xf;
eff1a59c 502 rx_status.freq = freq;
cf3e74c2 503 rx_status.band = dev->conf.channel->band;
eff1a59c 504 rx_status.antenna = hdr->antenna;
a0db663f
CL		 505
506 tsf32 = le32_to_cpu(hdr->tsf32);
507 if (tsf32 < priv->tsf_low32)
508 priv->tsf_high32++;
509 rx_status.mactime = ((u64)priv->tsf_high32) << 32 | tsf32;
510 priv->tsf_low32 = tsf32;
511
03bffc13 512 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c 513
19c19d54
CL		 514 if (hdr->magic & cpu_to_le16(0x4000))
515 header_len += hdr->align[0];
516
517 skb_pull(skb, header_len);
eff1a59c
MW		 518 skb_trim(skb, le16_to_cpu(hdr->len));
519
520 ieee80211_rx_irqsafe(dev, skb, &rx_status);
19c19d54
CL		 521
522 return -1;
eff1a59c
MW		 523}
524
525static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
526{
527 struct p54_common *priv = dev->priv;
528 int i;
529
eff1a59c 530 for (i = 0; i < dev->queues; i++)
84df3ed3 531 if (priv->tx_stats[i + 4].len < priv->tx_stats[i + 4].limit)
eff1a59c
MW		 532 ieee80211_wake_queue(dev, i);
533}
534
535static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
536{
537 struct p54_common *priv = dev->priv;
538 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
539 struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data;
540 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
4e416a6f 541 u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom;
eff1a59c
MW		 542 struct memrecord *range = NULL;
543 u32 freed = 0;
544 u32 last_addr = priv->rx_start;
031d10ee 545 unsigned long flags;
eff1a59c 546
031d10ee 547 spin_lock_irqsave(&priv->tx_queue.lock, flags);
eff1a59c 548 while (entry != (struct sk_buff *)&priv->tx_queue) {
552fe53f
JB		 549 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
550 range = (void *)info->driver_data;
eff1a59c 551 if (range->start_addr == addr) {
eff1a59c
MW		 552 struct p54_control_hdr *entry_hdr;
553 struct p54_tx_control_allocdata *entry_data;
554 int pad = 0;
555
552fe53f
JB		 556 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
557 struct ieee80211_tx_info *ni;
558 struct memrecord *mr;
559
560 ni = IEEE80211_SKB_CB(entry->next);
561 mr = (struct memrecord *)ni->driver_data;
562 freed = mr->start_addr - last_addr;
563 } else
eff1a59c
MW		 564 freed = priv->rx_end - last_addr;
565
566 last_addr = range->end_addr;
567 __skb_unlink(entry, &priv->tx_queue);
031d10ee
C		 568 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
569
e039fa4a 570 memset(&info->status, 0, sizeof(info->status));
eff1a59c
MW		 571 entry_hdr = (struct p54_control_hdr *) entry->data;
572 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
573 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
574 pad = entry_data->align[0];
575
84df3ed3 576 priv->tx_stats[entry_data->hw_queue].len--;
e039fa4a 577 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
eff1a59c 578 if (!(payload->status & 0x01))
e039fa4a 579 info->flags |= IEEE80211_TX_STAT_ACK;
eff1a59c 580 else
e039fa4a 581 info->status.excessive_retries = 1;
eff1a59c 582 }
e039fa4a 583 info->status.retry_count = payload->retries - 1;
cc6de669
CL		 584 info->status.ack_signal = p54_rssi_to_dbm(dev,
585 le16_to_cpu(payload->ack_rssi));
eff1a59c 586 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
e039fa4a 587 ieee80211_tx_status_irqsafe(dev, entry);
031d10ee 588 goto out;
eff1a59c
MW		 589 } else
590 last_addr = range->end_addr;
591 entry = entry->next;
592 }
031d10ee 593 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
eff1a59c 594
031d10ee 595out:
eff1a59c
MW		 596 if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
597 sizeof(struct p54_control_hdr))
598 p54_wake_free_queues(dev);
599}
600
7cb77072
CL		 601static void p54_rx_eeprom_readback(struct ieee80211_hw *dev,
602 struct sk_buff *skb)
603{
604 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
605 struct p54_eeprom_lm86 *eeprom = (struct p54_eeprom_lm86 *) hdr->data;
606 struct p54_common *priv = dev->priv;
607
608 if (!priv->eeprom)
609 return ;
610
1f1c0e33 611 memcpy(priv->eeprom, eeprom->data, le16_to_cpu(eeprom->len));
7cb77072
CL		 612
613 complete(&priv->eeprom_comp);
614}
615
cc6de669
CL		 616static void p54_rx_stats(struct ieee80211_hw *dev, struct sk_buff *skb)
617{
618 struct p54_common *priv = dev->priv;
619 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
620 struct p54_statistics *stats = (struct p54_statistics *) hdr->data;
621 u32 tsf32 = le32_to_cpu(stats->tsf32);
622
623 if (tsf32 < priv->tsf_low32)
624 priv->tsf_high32++;
625 priv->tsf_low32 = tsf32;
626
627 priv->stats.dot11RTSFailureCount = le32_to_cpu(stats->rts_fail);
628 priv->stats.dot11RTSSuccessCount = le32_to_cpu(stats->rts_success);
629 priv->stats.dot11FCSErrorCount = le32_to_cpu(stats->rx_bad_fcs);
630
631 priv->noise = p54_rssi_to_dbm(dev, le32_to_cpu(stats->noise));
632 complete(&priv->stats_comp);
633
634 mod_timer(&priv->stats_timer, jiffies + 5 * HZ);
635}
636
19c19d54 637static int p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c
MW		 638{
639 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
640
641 switch (le16_to_cpu(hdr->type)) {
642 case P54_CONTROL_TYPE_TXDONE:
643 p54_rx_frame_sent(dev, skb);
644 break;
645 case P54_CONTROL_TYPE_BBP:
646 break;
cc6de669
CL		 647 case P54_CONTROL_TYPE_STAT_READBACK:
648 p54_rx_stats(dev, skb);
649 break;
7cb77072
CL		 650 case P54_CONTROL_TYPE_EEPROM_READBACK:
651 p54_rx_eeprom_readback(dev, skb);
652 break;
eff1a59c
MW		 653 default:
654 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
655 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
656 break;
657 }
19c19d54
CL		 658
659 return 0;
eff1a59c
MW		 660}
661
662/* returns zero if skb can be reused */
663int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
664{
665 u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8;
19c19d54
CL		 666
667 if (type == 0x80)
668 return p54_rx_control(dev, skb);
669 else
670 return p54_rx_data(dev, skb);
eff1a59c
MW		 671}
672EXPORT_SYMBOL_GPL(p54_rx);
673
674/*
675 * So, the firmware is somewhat stupid and doesn't know what places in its
676 * memory incoming data should go to. By poking around in the firmware, we
677 * can find some unused memory to upload our packets to. However, data that we
678 * want the card to TX needs to stay intact until the card has told us that
679 * it is done with it. This function finds empty places we can upload to and
680 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
681 * allocated areas.
682 */
683static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
e039fa4a 684 struct p54_control_hdr *data, u32 len)
eff1a59c
MW		 685{
686 struct p54_common *priv = dev->priv;
687 struct sk_buff *entry = priv->tx_queue.next;
688 struct sk_buff *target_skb = NULL;
eff1a59c
MW		 689 u32 last_addr = priv->rx_start;
690 u32 largest_hole = 0;
691 u32 target_addr = priv->rx_start;
692 unsigned long flags;
693 unsigned int left;
4e416a6f 694 len = (len + priv->headroom + priv->tailroom + 3) & ~0x3;
eff1a59c
MW		 695
696 spin_lock_irqsave(&priv->tx_queue.lock, flags);
697 left = skb_queue_len(&priv->tx_queue);
698 while (left--) {
699 u32 hole_size;
e039fa4a
JB		 700 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
701 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 702 hole_size = range->start_addr - last_addr;
703 if (!target_skb && hole_size >= len) {
704 target_skb = entry->prev;
705 hole_size -= len;
706 target_addr = last_addr;
707 }
708 largest_hole = max(largest_hole, hole_size);
709 last_addr = range->end_addr;
710 entry = entry->next;
711 }
712 if (!target_skb && priv->rx_end - last_addr >= len) {
713 target_skb = priv->tx_queue.prev;
714 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
715 if (!skb_queue_empty(&priv->tx_queue)) {
e039fa4a
JB		 716 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(target_skb);
717 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 718 target_addr = range->end_addr;
719 }
720 } else
721 largest_hole = max(largest_hole, priv->rx_end - last_addr);
722
723 if (skb) {
e039fa4a
JB		 724 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
725 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 726 range->start_addr = target_addr;
727 range->end_addr = target_addr + len;
eff1a59c 728 __skb_queue_after(&priv->tx_queue, target_skb, skb);
4e416a6f
CL		 729 if (largest_hole < priv->rx_mtu + priv->headroom +
730 priv->tailroom +
eff1a59c
MW		 731 sizeof(struct p54_control_hdr))
732 ieee80211_stop_queues(dev);
733 }
734 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
735
4e416a6f 736 data->req_id = cpu_to_le32(target_addr + priv->headroom);
eff1a59c
MW		 737}
738
7cb77072
CL		 739int p54_read_eeprom(struct ieee80211_hw *dev)
740{
741 struct p54_common *priv = dev->priv;
742 struct p54_control_hdr *hdr = NULL;
743 struct p54_eeprom_lm86 *eeprom_hdr;
744 size_t eeprom_size = 0x2020, offset = 0, blocksize;
745 int ret = -ENOMEM;
746 void *eeprom = NULL;
747
748 hdr = (struct p54_control_hdr *)kzalloc(sizeof(*hdr) +
749 sizeof(*eeprom_hdr) + EEPROM_READBACK_LEN, GFP_KERNEL);
750 if (!hdr)
751 goto free;
752
753 priv->eeprom = kzalloc(EEPROM_READBACK_LEN, GFP_KERNEL);
754 if (!priv->eeprom)
755 goto free;
756
757 eeprom = kzalloc(eeprom_size, GFP_KERNEL);
758 if (!eeprom)
759 goto free;
760
761 hdr->magic1 = cpu_to_le16(0x8000);
762 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK);
763 hdr->retry1 = hdr->retry2 = 0;
764 eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data;
765
766 while (eeprom_size) {
767 blocksize = min(eeprom_size, (size_t)EEPROM_READBACK_LEN);
768 hdr->len = cpu_to_le16(blocksize + sizeof(*eeprom_hdr));
769 eeprom_hdr->offset = cpu_to_le16(offset);
770 eeprom_hdr->len = cpu_to_le16(blocksize);
1f1c0e33
LF		 771 p54_assign_address(dev, NULL, hdr, le16_to_cpu(hdr->len) +
772 sizeof(*hdr));
773 priv->tx(dev, hdr, le16_to_cpu(hdr->len) + sizeof(*hdr), 0);
7cb77072
CL		 774
775 if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) {
776 printk(KERN_ERR "%s: device does not respond!\n",
777 wiphy_name(dev->wiphy));
778 ret = -EBUSY;
779 goto free;
780 }
781
782 memcpy(eeprom + offset, priv->eeprom, blocksize);
783 offset += blocksize;
784 eeprom_size -= blocksize;
785 }
786
787 ret = p54_parse_eeprom(dev, eeprom, offset);
788free:
789 kfree(priv->eeprom);
790 priv->eeprom = NULL;
791 kfree(hdr);
792 kfree(eeprom);
793
794 return ret;
795}
796EXPORT_SYMBOL_GPL(p54_read_eeprom);
797
e039fa4a 798static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 799{
e039fa4a 800 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
57ffc589 801 struct ieee80211_tx_queue_stats *current_queue;
eff1a59c
MW		 802 struct p54_common *priv = dev->priv;
803 struct p54_control_hdr *hdr;
eda0c003 804 struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
eff1a59c 805 struct p54_tx_control_allocdata *txhdr;
eff1a59c
MW		 806 size_t padding, len;
807 u8 rate;
aaa15535 808 u8 cts_rate = 0x20;
eff1a59c 809
84df3ed3 810 current_queue = &priv->tx_stats[skb_get_queue_mapping(skb) + 4];
eff1a59c
MW		 811 if (unlikely(current_queue->len > current_queue->limit))
812 return NETDEV_TX_BUSY;
813 current_queue->len++;
814 current_queue->count++;
815 if (current_queue->len == current_queue->limit)
e2530083 816 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
eff1a59c
MW		 817
818 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
819 len = skb->len;
820
eff1a59c
MW		 821 txhdr = (struct p54_tx_control_allocdata *)
822 skb_push(skb, sizeof(*txhdr) + padding);
823 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
824
825 if (padding)
826 hdr->magic1 = cpu_to_le16(0x4010);
827 else
828 hdr->magic1 = cpu_to_le16(0x0010);
829 hdr->len = cpu_to_le16(len);
e039fa4a
JB		 830 hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1);
831 hdr->retry1 = hdr->retry2 = info->control.retry_limit;
eff1a59c 832
eff1a59c 833 /* TODO: add support for alternate retry TX rates */
e039fa4a 834 rate = ieee80211_get_tx_rate(dev, info)->hw_value;
aaa15535 835 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) {
8318d78a 836 rate |= 0x10;
aaa15535
CL		 837 cts_rate |= 0x10;
838 }
839 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
eff1a59c 840 rate |= 0x40;
aaa15535
CL		 841 cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value;
842 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
eff1a59c 843 rate |= 0x20;
aaa15535
CL		 844 cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value;
845 }
eff1a59c 846 memset(txhdr->rateset, rate, 8);
aaa15535
CL		 847 txhdr->key_type = 0;
848 txhdr->key_len = 0;
849 txhdr->hw_queue = skb_get_queue_mapping(skb) + 4;
850 txhdr->tx_antenna = (info->antenna_sel_tx == 0) ?
e039fa4a 851 2 : info->antenna_sel_tx - 1;
09adf284 852 txhdr->output_power = priv->output_power;
aaa15535
CL		 853 txhdr->cts_rate = (info->flags & IEEE80211_TX_CTL_NO_ACK) ?
854 0 : cts_rate;
eff1a59c
MW		 855 if (padding)
856 txhdr->align[0] = padding;
857
eda0c003
LF		 858 /* FIXME: The sequence that follows is needed for this driver to
859 * work with mac80211 since "mac80211: fix TX sequence numbers".
860 * As with the temporary code in rt2x00, changes will be needed
861 * to get proper sequence numbers on beacons. In addition, this
862 * patch places the sequence number in the hardware state, which
863 * limits us to a single virtual state.
864 */
865 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
866 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
867 priv->seqno += 0x10;
868 ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
869 ieee80211hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
870 }
e039fa4a
JB		 871 /* modifies skb->cb and with it info, so must be last! */
872 p54_assign_address(dev, skb, hdr, skb->len);
873
eff1a59c
MW		 874 priv->tx(dev, hdr, skb->len, 0);
875 return 0;
876}
877
878static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
e0a58eac 879 const u8 *bssid)
eff1a59c
MW		 880{
881 struct p54_common *priv = dev->priv;
882 struct p54_control_hdr *hdr;
883 struct p54_tx_control_filter *filter;
19c19d54 884 size_t data_len;
eff1a59c
MW		 885
886 hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) +
ba8007ce 887 priv->tx_hdr_len, GFP_ATOMIC);
eff1a59c
MW		 888 if (!hdr)
889 return -ENOMEM;
890
891 hdr = (void *)hdr + priv->tx_hdr_len;
892
893 filter = (struct p54_tx_control_filter *) hdr->data;
894 hdr->magic1 = cpu_to_le16(0x8001);
eff1a59c
MW		 895 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
896
e0a58eac
CL		 897 priv->filter_type = filter->filter_type = cpu_to_le16(filter_type);
898 memcpy(filter->mac_addr, priv->mac_addr, ETH_ALEN);
899 if (!bssid)
900 memset(filter->bssid, ~0, ETH_ALEN);
eff1a59c 901 else
e0a58eac
CL		 902 memcpy(filter->bssid, bssid, ETH_ALEN);
903
904 filter->rx_antenna = priv->rx_antenna;
eff1a59c 905
19c19d54
CL		 906 if (priv->fw_var < 0x500) {
907 data_len = P54_TX_CONTROL_FILTER_V1_LEN;
908 filter->v1.basic_rate_mask = cpu_to_le32(0x15F);
909 filter->v1.rx_addr = cpu_to_le32(priv->rx_end);
910 filter->v1.max_rx = cpu_to_le16(priv->rx_mtu);
911 filter->v1.rxhw = cpu_to_le16(priv->rxhw);
912 filter->v1.wakeup_timer = cpu_to_le16(500);
913 } else {
914 data_len = P54_TX_CONTROL_FILTER_V2_LEN;
915 filter->v2.rx_addr = cpu_to_le32(priv->rx_end);
916 filter->v2.max_rx = cpu_to_le16(priv->rx_mtu);
917 filter->v2.rxhw = cpu_to_le16(priv->rxhw);
918 filter->v2.timer = cpu_to_le16(1000);
919 }
920
921 hdr->len = cpu_to_le16(data_len);
922 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + data_len);
923 priv->tx(dev, hdr, sizeof(*hdr) + data_len, 1);
eff1a59c
MW		 924 return 0;
925}
926
927static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
928{
929 struct p54_common *priv = dev->priv;
930 struct p54_control_hdr *hdr;
931 struct p54_tx_control_channel *chan;
932 unsigned int i;
19c19d54 933 size_t data_len;
eff1a59c
MW		 934 void *entry;
935
154e3af1 936 hdr = kzalloc(sizeof(*hdr) + sizeof(*chan) +
eff1a59c
MW		 937 priv->tx_hdr_len, GFP_KERNEL);
938 if (!hdr)
939 return -ENOMEM;
940
941 hdr = (void *)hdr + priv->tx_hdr_len;
942
943 chan = (struct p54_tx_control_channel *) hdr->data;
944
945 hdr->magic1 = cpu_to_le16(0x8001);
19c19d54 946
eff1a59c 947 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
eff1a59c 948
154e3af1
CL		 949 chan->flags = cpu_to_le16(0x1);
950 chan->dwell = cpu_to_le16(0x0);
eff1a59c
MW		 951
952 for (i = 0; i < priv->iq_autocal_len; i++) {
953 if (priv->iq_autocal[i].freq != freq)
954 continue;
955
956 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
957 sizeof(*priv->iq_autocal));
958 break;
959 }
960 if (i == priv->iq_autocal_len)
961 goto err;
962
963 for (i = 0; i < priv->output_limit_len; i++) {
964 if (priv->output_limit[i].freq != freq)
965 continue;
966
967 chan->val_barker = 0x38;
154e3af1
CL		 968 chan->val_bpsk = chan->dup_bpsk =
969 priv->output_limit[i].val_bpsk;
970 chan->val_qpsk = chan->dup_qpsk =
971 priv->output_limit[i].val_qpsk;
972 chan->val_16qam = chan->dup_16qam =
973 priv->output_limit[i].val_16qam;
974 chan->val_64qam = chan->dup_64qam =
975 priv->output_limit[i].val_64qam;
eff1a59c
MW		 976 break;
977 }
978 if (i == priv->output_limit_len)
979 goto err;
980
eff1a59c
MW		 981 entry = priv->curve_data->data;
982 for (i = 0; i < priv->curve_data->channels; i++) {
983 if (*((__le16 *)entry) != freq) {
984 entry += sizeof(__le16);
154e3af1
CL		 985 entry += sizeof(struct p54_pa_curve_data_sample) *
986 priv->curve_data->points_per_channel;
eff1a59c
MW		 987 continue;
988 }
989
990 entry += sizeof(__le16);
154e3af1
CL		 991 chan->pa_points_per_curve =
992 min(priv->curve_data->points_per_channel, (u8) 8);
993
eff1a59c
MW		 994 memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
995 chan->pa_points_per_curve);
996 break;
997 }
998
19c19d54
CL		 999 if (priv->fw_var < 0x500) {
1000 data_len = P54_TX_CONTROL_CHANNEL_V1_LEN;
1001 chan->v1.rssical_mul = cpu_to_le16(130);
1002 chan->v1.rssical_add = cpu_to_le16(0xfe70);
1003 } else {
1004 data_len = P54_TX_CONTROL_CHANNEL_V2_LEN;
1005 chan->v2.rssical_mul = cpu_to_le16(130);
1006 chan->v2.rssical_add = cpu_to_le16(0xfe70);
1007 chan->v2.basic_rate_mask = cpu_to_le32(0x15f);
1008 }
eff1a59c 1009
19c19d54
CL		 1010 hdr->len = cpu_to_le16(data_len);
1011 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + data_len);
1012 priv->tx(dev, hdr, sizeof(*hdr) + data_len, 1);
eff1a59c
MW		 1013 return 0;
1014
1015 err:
1016 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
1017 kfree(hdr);
1018 return -EINVAL;
1019}
1020
1021static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
1022{
1023 struct p54_common *priv = dev->priv;
1024 struct p54_control_hdr *hdr;
1025 struct p54_tx_control_led *led;
1026
1027 hdr = kzalloc(sizeof(*hdr) + sizeof(*led) +
1028 priv->tx_hdr_len, GFP_KERNEL);
1029 if (!hdr)
1030 return -ENOMEM;
1031
1032 hdr = (void *)hdr + priv->tx_hdr_len;
1033 hdr->magic1 = cpu_to_le16(0x8001);
1034 hdr->len = cpu_to_le16(sizeof(*led));
1035 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
e039fa4a 1036 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led));
eff1a59c
MW		 1037
1038 led = (struct p54_tx_control_led *) hdr->data;
1039 led->mode = cpu_to_le16(mode);
1040 led->led_permanent = cpu_to_le16(link);
1041 led->led_temporary = cpu_to_le16(act);
1042 led->duration = cpu_to_le16(1000);
1043
1044 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1);
1045
1046 return 0;
1047}
1048
3330d7be 1049#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW		 1050do { \
1051 queue.aifs = cpu_to_le16(ai_fs); \
1052 queue.cwmin = cpu_to_le16(cw_min); \
1053 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 1054 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW		 1055} while(0)
1056
1057static void p54_init_vdcf(struct ieee80211_hw *dev)
1058{
1059 struct p54_common *priv = dev->priv;
1060 struct p54_control_hdr *hdr;
1061 struct p54_tx_control_vdcf *vdcf;
1062
1063 /* all USB V1 adapters need a extra headroom */
1064 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
1065 hdr->magic1 = cpu_to_le16(0x8001);
1066 hdr->len = cpu_to_le16(sizeof(*vdcf));
1067 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT);
1068 hdr->req_id = cpu_to_le32(priv->rx_start);
1069
1070 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
1071
3330d7be
JB		 1072 P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 47);
1073 P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 94);
5200e8cd 1074 P54_SET_QUEUE(vdcf->queue[2], 0x0003, 0x000f, 0x03ff, 0);
3330d7be 1075 P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0);
eff1a59c
MW		 1076}
1077
1078static void p54_set_vdcf(struct ieee80211_hw *dev)
1079{
1080 struct p54_common *priv = dev->priv;
1081 struct p54_control_hdr *hdr;
1082 struct p54_tx_control_vdcf *vdcf;
1083
1084 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
1085
e039fa4a 1086 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf));
eff1a59c
MW		 1087
1088 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
1089
1090 if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
1091 vdcf->slottime = 9;
5423b2ed
CL		 1092 vdcf->magic1 = 0x10;
1093 vdcf->magic2 = 0x00;
eff1a59c
MW		 1094 } else {
1095 vdcf->slottime = 20;
1096 vdcf->magic1 = 0x0a;
1097 vdcf->magic2 = 0x06;
1098 }
1099
1100 /* (see prism54/isl_oid.h for further details) */
1101 vdcf->frameburst = cpu_to_le16(0);
1102
1103 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0);
1104}
1105
4150c572
JB		 1106static int p54_start(struct ieee80211_hw *dev)
1107{
1108 struct p54_common *priv = dev->priv;
1109 int err;
1110
69bbc7dc
CL		 1111 if (!priv->cached_vdcf) {
1112 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf)+
1113 priv->tx_hdr_len + sizeof(struct p54_control_hdr),
1114 GFP_KERNEL);
1115
1116 if (!priv->cached_vdcf)
1117 return -ENOMEM;
1118 }
1119
cc6de669
CL		 1120 if (!priv->cached_stats) {
1121 priv->cached_stats = kzalloc(sizeof(struct p54_statistics) +
1122 priv->tx_hdr_len + sizeof(struct p54_control_hdr),
1123 GFP_KERNEL);
1124
1125 if (!priv->cached_stats) {
1126 kfree(priv->cached_vdcf);
1127 priv->cached_vdcf = NULL;
1128 return -ENOMEM;
1129 }
1130 }
1131
4150c572
JB		 1132 err = priv->open(dev);
1133 if (!err)
05c914fe 1134 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 1135
69bbc7dc
CL		 1136 p54_init_vdcf(dev);
1137
cc6de669 1138 mod_timer(&priv->stats_timer, jiffies + HZ);
4150c572
JB		 1139 return err;
1140}
1141
1142static void p54_stop(struct ieee80211_hw *dev)
1143{
1144 struct p54_common *priv = dev->priv;
1145 struct sk_buff *skb;
cc6de669
CL		 1146
1147 del_timer(&priv->stats_timer);
e039fa4a 1148 while ((skb = skb_dequeue(&priv->tx_queue)))
4150c572 1149 kfree_skb(skb);
4150c572 1150 priv->stop(dev);
a0db663f 1151 priv->tsf_high32 = priv->tsf_low32 = 0;
05c914fe 1152 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
4150c572
JB		 1153}
1154
eff1a59c
MW		 1155static int p54_add_interface(struct ieee80211_hw *dev,
1156 struct ieee80211_if_init_conf *conf)
1157{
1158 struct p54_common *priv = dev->priv;
eff1a59c 1159
05c914fe 1160 if (priv->mode != NL80211_IFTYPE_MONITOR)
4150c572 1161 return -EOPNOTSUPP;
eff1a59c
MW		 1162
1163 switch (conf->type) {
05c914fe 1164 case NL80211_IFTYPE_STATION:
eff1a59c
MW		 1165 priv->mode = conf->type;
1166 break;
1167 default:
1168 return -EOPNOTSUPP;
1169 }
1170
4150c572 1171 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
eff1a59c 1172
e0a58eac 1173 p54_set_filter(dev, 0, NULL);
eff1a59c
MW		 1174
1175 switch (conf->type) {
05c914fe 1176 case NL80211_IFTYPE_STATION:
e0a58eac 1177 p54_set_filter(dev, 1, NULL);
eff1a59c 1178 break;
4150c572
JB		 1179 default:
1180 BUG(); /* impossible */
1181 break;
eff1a59c
MW		 1182 }
1183
1184 p54_set_leds(dev, 1, 0, 0);
1185
1186 return 0;
1187}
1188
1189static void p54_remove_interface(struct ieee80211_hw *dev,
1190 struct ieee80211_if_init_conf *conf)
1191{
1192 struct p54_common *priv = dev->priv;
05c914fe 1193 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 1194 memset(priv->mac_addr, 0, ETH_ALEN);
e0a58eac 1195 p54_set_filter(dev, 0, NULL);
eff1a59c
MW		 1196}
1197
1198static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1199{
1200 int ret;
6041e2a0 1201 struct p54_common *priv = dev->priv;
eff1a59c 1202
6041e2a0 1203 mutex_lock(&priv->conf_mutex);
e0a58eac
CL		 1204 priv->rx_antenna = (conf->antenna_sel_rx == 0) ?
1205 2 : conf->antenna_sel_tx - 1;
09adf284 1206 priv->output_power = conf->power_level << 2;
8318d78a 1207 ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq));
eff1a59c 1208 p54_set_vdcf(dev);
6041e2a0 1209 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1210 return ret;
1211}
1212
32bfd35d
JB		 1213static int p54_config_interface(struct ieee80211_hw *dev,
1214 struct ieee80211_vif *vif,
eff1a59c
MW		 1215 struct ieee80211_if_conf *conf)
1216{
1217 struct p54_common *priv = dev->priv;
1218
6041e2a0 1219 mutex_lock(&priv->conf_mutex);
e0a58eac 1220 p54_set_filter(dev, 0, conf->bssid);
eff1a59c 1221 p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
4150c572 1222 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6041e2a0 1223 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1224 return 0;
1225}
1226
4150c572
JB		 1227static void p54_configure_filter(struct ieee80211_hw *dev,
1228 unsigned int changed_flags,
1229 unsigned int *total_flags,
1230 int mc_count, struct dev_mc_list *mclist)
1231{
1232 struct p54_common *priv = dev->priv;
1233
78d57eb2
CL		 1234 *total_flags &= FIF_BCN_PRBRESP_PROMISC |
1235 FIF_PROMISC_IN_BSS |
1236 FIF_FCSFAIL;
1237
1238 priv->filter_flags = *total_flags;
4150c572
JB		 1239
1240 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1241 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1f1c0e33
LF		 1242 p54_set_filter(dev, le16_to_cpu(priv->filter_type),
1243 NULL);
78d57eb2 1244 else
1f1c0e33
LF		 1245 p54_set_filter(dev, le16_to_cpu(priv->filter_type),
1246 priv->bssid);
78d57eb2
CL		 1247 }
1248
1249 if (changed_flags & FIF_PROMISC_IN_BSS) {
1250 if (*total_flags & FIF_PROMISC_IN_BSS)
1f1c0e33
LF		 1251 p54_set_filter(dev, le16_to_cpu(priv->filter_type) |
1252 0x8, NULL);
4150c572 1253 else
1f1c0e33
LF		 1254 p54_set_filter(dev, le16_to_cpu(priv->filter_type) &
1255 ~0x8, priv->bssid);
4150c572
JB		 1256 }
1257}
1258
e100bb64 1259static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW		 1260 const struct ieee80211_tx_queue_params *params)
1261{
1262 struct p54_common *priv = dev->priv;
1263 struct p54_tx_control_vdcf *vdcf;
1264
1265 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
1266 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
1267
3df5ee60 1268 if ((params) && !(queue > 4)) {
eff1a59c 1269 P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
3330d7be 1270 params->cw_min, params->cw_max, params->txop);
eff1a59c
MW		 1271 } else
1272 return -EINVAL;
1273
1274 p54_set_vdcf(dev);
1275
1276 return 0;
1277}
1278
1b997534
CL		 1279static int p54_init_xbow_synth(struct ieee80211_hw *dev)
1280{
1281 struct p54_common *priv = dev->priv;
1282 struct p54_control_hdr *hdr;
1283 struct p54_tx_control_xbow_synth *xbow;
1284
1285 hdr = kzalloc(sizeof(*hdr) + sizeof(*xbow) +
1286 priv->tx_hdr_len, GFP_KERNEL);
1287 if (!hdr)
1288 return -ENOMEM;
1289
1290 hdr = (void *)hdr + priv->tx_hdr_len;
1291 hdr->magic1 = cpu_to_le16(0x8001);
1292 hdr->len = cpu_to_le16(sizeof(*xbow));
1293 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_XBOW_SYNTH_CFG);
1294 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*xbow));
1295
1296 xbow = (struct p54_tx_control_xbow_synth *) hdr->data;
1297 xbow->magic1 = cpu_to_le16(0x1);
1298 xbow->magic2 = cpu_to_le16(0x2);
1299 xbow->freq = cpu_to_le16(5390);
1300
1301 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*xbow), 1);
1302
1303 return 0;
1304}
1305
cc6de669
CL		 1306static void p54_statistics_timer(unsigned long data)
1307{
1308 struct ieee80211_hw *dev = (struct ieee80211_hw *) data;
1309 struct p54_common *priv = dev->priv;
1310 struct p54_control_hdr *hdr;
1311 struct p54_statistics *stats;
1312
1313 BUG_ON(!priv->cached_stats);
1314
1315 hdr = (void *)priv->cached_stats + priv->tx_hdr_len;
1316 hdr->magic1 = cpu_to_le16(0x8000);
1317 hdr->len = cpu_to_le16(sizeof(*stats));
1318 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_STAT_READBACK);
1319 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*stats));
1320
1321 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*stats), 0);
1322}
1323
eff1a59c
MW		 1324static int p54_get_stats(struct ieee80211_hw *dev,
1325 struct ieee80211_low_level_stats *stats)
1326{
cc6de669
CL		 1327 struct p54_common *priv = dev->priv;
1328
1329 del_timer(&priv->stats_timer);
1330 p54_statistics_timer((unsigned long)dev);
1331
1332 if (!wait_for_completion_interruptible_timeout(&priv->stats_comp, HZ)) {
1333 printk(KERN_ERR "%s: device does not respond!\n",
1334 wiphy_name(dev->wiphy));
1335 return -EBUSY;
1336 }
1337
1338 memcpy(stats, &priv->stats, sizeof(*stats));
1339
eff1a59c
MW		 1340 return 0;
1341}
1342
1343static int p54_get_tx_stats(struct ieee80211_hw *dev,
1344 struct ieee80211_tx_queue_stats *stats)
1345{
1346 struct p54_common *priv = dev->priv;
eff1a59c 1347
84df3ed3 1348 memcpy(stats, &priv->tx_stats[4], sizeof(stats[0]) * dev->queues);
eff1a59c
MW		 1349
1350 return 0;
1351}
1352
1353static const struct ieee80211_ops p54_ops = {
1354 .tx = p54_tx,
4150c572
JB		 1355 .start = p54_start,
1356 .stop = p54_stop,
eff1a59c
MW		 1357 .add_interface = p54_add_interface,
1358 .remove_interface = p54_remove_interface,
1359 .config = p54_config,
1360 .config_interface = p54_config_interface,
4150c572 1361 .configure_filter = p54_configure_filter,
eff1a59c
MW		 1362 .conf_tx = p54_conf_tx,
1363 .get_stats = p54_get_stats,
1364 .get_tx_stats = p54_get_tx_stats
1365};
1366
1367struct ieee80211_hw *p54_init_common(size_t priv_data_len)
1368{
1369 struct ieee80211_hw *dev;
1370 struct p54_common *priv;
eff1a59c
MW		 1371
1372 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
1373 if (!dev)
1374 return NULL;
1375
1376 priv = dev->priv;
05c914fe 1377 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
eff1a59c 1378 skb_queue_head_init(&priv->tx_queue);
eff1a59c 1379 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
566bfe5a 1380 IEEE80211_HW_RX_INCLUDES_FCS |
cc6de669
CL		 1381 IEEE80211_HW_SIGNAL_DBM |
1382 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 1383
1384 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1385
eff1a59c 1386 dev->channel_change_time = 1000; /* TODO: find actual value */
eff1a59c 1387
84df3ed3
C		 1388 priv->tx_stats[0].limit = 1;
1389 priv->tx_stats[1].limit = 1;
1390 priv->tx_stats[2].limit = 1;
1391 priv->tx_stats[3].limit = 1;
1392 priv->tx_stats[4].limit = 5;
eff1a59c 1393 dev->queues = 1;
cc6de669 1394 priv->noise = -94;
eff1a59c
MW		 1395 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
1396 sizeof(struct p54_tx_control_allocdata);
1397
6041e2a0 1398 mutex_init(&priv->conf_mutex);
7cb77072 1399 init_completion(&priv->eeprom_comp);
cc6de669
CL		 1400 init_completion(&priv->stats_comp);
1401 setup_timer(&priv->stats_timer, p54_statistics_timer,
1402 (unsigned long)dev);
eff1a59c 1403
eff1a59c
MW		 1404 return dev;
1405}
1406EXPORT_SYMBOL_GPL(p54_init_common);
1407
1408void p54_free_common(struct ieee80211_hw *dev)
1409{
1410 struct p54_common *priv = dev->priv;
cc6de669 1411 kfree(priv->cached_stats);
eff1a59c
MW		 1412 kfree(priv->iq_autocal);
1413 kfree(priv->output_limit);
1414 kfree(priv->curve_data);
1415 kfree(priv->cached_vdcf);
1416}
1417EXPORT_SYMBOL_GPL(p54_free_common);
1418
1419static int __init p54_init(void)
1420{
1421 return 0;
1422}
1423
1424static void __exit p54_exit(void)
1425{
1426}
1427
1428module_init(p54_init);
1429module_exit(p54_exit);
Linux 6.x block layer and io_uring tree(s)