Commit | Line | Data |
---|---|---|
eff1a59c MW |
1 | |
2 | /* | |
3 | * Common code for mac80211 Prism54 drivers | |
4 | * | |
5 | * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> | |
6 | * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de> | |
7 | * | |
8 | * Based on the islsm (softmac prism54) driver, which is: | |
9 | * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/firmware.h> | |
18 | #include <linux/etherdevice.h> | |
19 | ||
20 | #include <net/mac80211.h> | |
21 | ||
22 | #include "p54.h" | |
23 | #include "p54common.h" | |
24 | ||
25 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
26 | MODULE_DESCRIPTION("Softmac Prism54 common code"); | |
27 | MODULE_LICENSE("GPL"); | |
28 | MODULE_ALIAS("prism54common"); | |
29 | ||
1b997534 | 30 | static struct ieee80211_rate p54_bgrates[] = { |
8318d78a JB |
31 | { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, |
32 | { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
33 | { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
34 | { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
35 | { .bitrate = 60, .hw_value = 4, }, | |
36 | { .bitrate = 90, .hw_value = 5, }, | |
37 | { .bitrate = 120, .hw_value = 6, }, | |
38 | { .bitrate = 180, .hw_value = 7, }, | |
39 | { .bitrate = 240, .hw_value = 8, }, | |
40 | { .bitrate = 360, .hw_value = 9, }, | |
41 | { .bitrate = 480, .hw_value = 10, }, | |
42 | { .bitrate = 540, .hw_value = 11, }, | |
43 | }; | |
44 | ||
1b997534 | 45 | static struct ieee80211_channel p54_bgchannels[] = { |
8318d78a JB |
46 | { .center_freq = 2412, .hw_value = 1, }, |
47 | { .center_freq = 2417, .hw_value = 2, }, | |
48 | { .center_freq = 2422, .hw_value = 3, }, | |
49 | { .center_freq = 2427, .hw_value = 4, }, | |
50 | { .center_freq = 2432, .hw_value = 5, }, | |
51 | { .center_freq = 2437, .hw_value = 6, }, | |
52 | { .center_freq = 2442, .hw_value = 7, }, | |
53 | { .center_freq = 2447, .hw_value = 8, }, | |
54 | { .center_freq = 2452, .hw_value = 9, }, | |
55 | { .center_freq = 2457, .hw_value = 10, }, | |
56 | { .center_freq = 2462, .hw_value = 11, }, | |
57 | { .center_freq = 2467, .hw_value = 12, }, | |
58 | { .center_freq = 2472, .hw_value = 13, }, | |
59 | { .center_freq = 2484, .hw_value = 14, }, | |
60 | }; | |
61 | ||
c2976ab0 | 62 | static struct ieee80211_supported_band band_2GHz = { |
1b997534 CL |
63 | .channels = p54_bgchannels, |
64 | .n_channels = ARRAY_SIZE(p54_bgchannels), | |
65 | .bitrates = p54_bgrates, | |
66 | .n_bitrates = ARRAY_SIZE(p54_bgrates), | |
67 | }; | |
68 | ||
69 | static struct ieee80211_rate p54_arates[] = { | |
70 | { .bitrate = 60, .hw_value = 4, }, | |
71 | { .bitrate = 90, .hw_value = 5, }, | |
72 | { .bitrate = 120, .hw_value = 6, }, | |
73 | { .bitrate = 180, .hw_value = 7, }, | |
74 | { .bitrate = 240, .hw_value = 8, }, | |
75 | { .bitrate = 360, .hw_value = 9, }, | |
76 | { .bitrate = 480, .hw_value = 10, }, | |
77 | { .bitrate = 540, .hw_value = 11, }, | |
78 | }; | |
79 | ||
80 | static struct ieee80211_channel p54_achannels[] = { | |
81 | { .center_freq = 4920 }, | |
82 | { .center_freq = 4940 }, | |
83 | { .center_freq = 4960 }, | |
84 | { .center_freq = 4980 }, | |
85 | { .center_freq = 5040 }, | |
86 | { .center_freq = 5060 }, | |
87 | { .center_freq = 5080 }, | |
88 | { .center_freq = 5170 }, | |
89 | { .center_freq = 5180 }, | |
90 | { .center_freq = 5190 }, | |
91 | { .center_freq = 5200 }, | |
92 | { .center_freq = 5210 }, | |
93 | { .center_freq = 5220 }, | |
94 | { .center_freq = 5230 }, | |
95 | { .center_freq = 5240 }, | |
96 | { .center_freq = 5260 }, | |
97 | { .center_freq = 5280 }, | |
98 | { .center_freq = 5300 }, | |
99 | { .center_freq = 5320 }, | |
100 | { .center_freq = 5500 }, | |
101 | { .center_freq = 5520 }, | |
102 | { .center_freq = 5540 }, | |
103 | { .center_freq = 5560 }, | |
104 | { .center_freq = 5580 }, | |
105 | { .center_freq = 5600 }, | |
106 | { .center_freq = 5620 }, | |
107 | { .center_freq = 5640 }, | |
108 | { .center_freq = 5660 }, | |
109 | { .center_freq = 5680 }, | |
110 | { .center_freq = 5700 }, | |
111 | { .center_freq = 5745 }, | |
112 | { .center_freq = 5765 }, | |
113 | { .center_freq = 5785 }, | |
114 | { .center_freq = 5805 }, | |
115 | { .center_freq = 5825 }, | |
116 | }; | |
117 | ||
118 | static struct ieee80211_supported_band band_5GHz = { | |
119 | .channels = p54_achannels, | |
120 | .n_channels = ARRAY_SIZE(p54_achannels), | |
121 | .bitrates = p54_arates, | |
122 | .n_bitrates = ARRAY_SIZE(p54_arates), | |
8318d78a JB |
123 | }; |
124 | ||
4e416a6f | 125 | int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw) |
eff1a59c MW |
126 | { |
127 | struct p54_common *priv = dev->priv; | |
128 | struct bootrec_exp_if *exp_if; | |
129 | struct bootrec *bootrec; | |
130 | u32 *data = (u32 *)fw->data; | |
131 | u32 *end_data = (u32 *)fw->data + (fw->size >> 2); | |
132 | u8 *fw_version = NULL; | |
133 | size_t len; | |
134 | int i; | |
135 | ||
136 | if (priv->rx_start) | |
4e416a6f | 137 | return 0; |
eff1a59c MW |
138 | |
139 | while (data < end_data && *data) | |
140 | data++; | |
141 | ||
142 | while (data < end_data && !*data) | |
143 | data++; | |
144 | ||
145 | bootrec = (struct bootrec *) data; | |
146 | ||
147 | while (bootrec->data <= end_data && | |
148 | (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) { | |
149 | u32 code = le32_to_cpu(bootrec->code); | |
150 | switch (code) { | |
151 | case BR_CODE_COMPONENT_ID: | |
2b80848e CL |
152 | priv->fw_interface = be32_to_cpup(bootrec->data); |
153 | switch (priv->fw_interface) { | |
eff1a59c MW |
154 | case FW_FMAC: |
155 | printk(KERN_INFO "p54: FreeMAC firmware\n"); | |
156 | break; | |
157 | case FW_LM20: | |
158 | printk(KERN_INFO "p54: LM20 firmware\n"); | |
159 | break; | |
160 | case FW_LM86: | |
161 | printk(KERN_INFO "p54: LM86 firmware\n"); | |
162 | break; | |
163 | case FW_LM87: | |
2b80848e | 164 | printk(KERN_INFO "p54: LM87 firmware\n"); |
eff1a59c MW |
165 | break; |
166 | default: | |
167 | printk(KERN_INFO "p54: unknown firmware\n"); | |
168 | break; | |
169 | } | |
170 | break; | |
171 | case BR_CODE_COMPONENT_VERSION: | |
172 | /* 24 bytes should be enough for all firmwares */ | |
173 | if (strnlen((unsigned char*)bootrec->data, 24) < 24) | |
174 | fw_version = (unsigned char*)bootrec->data; | |
175 | break; | |
4e416a6f CL |
176 | case BR_CODE_DESCR: { |
177 | struct bootrec_desc *desc = | |
178 | (struct bootrec_desc *)bootrec->data; | |
179 | priv->rx_start = le32_to_cpu(desc->rx_start); | |
eff1a59c | 180 | /* FIXME add sanity checking */ |
4e416a6f CL |
181 | priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500; |
182 | priv->headroom = desc->headroom; | |
183 | priv->tailroom = desc->tailroom; | |
184 | if (bootrec->len == 11) | |
185 | priv->rx_mtu = (size_t) le16_to_cpu( | |
186 | (__le16)bootrec->data[10]); | |
187 | else | |
188 | priv->rx_mtu = (size_t) | |
189 | 0x620 - priv->tx_hdr_len; | |
eff1a59c | 190 | break; |
4e416a6f | 191 | } |
eff1a59c MW |
192 | case BR_CODE_EXPOSED_IF: |
193 | exp_if = (struct bootrec_exp_if *) bootrec->data; | |
194 | for (i = 0; i < (len * sizeof(*exp_if) / 4); i++) | |
dc73c623 | 195 | if (exp_if[i].if_id == cpu_to_le16(0x1a)) |
eff1a59c MW |
196 | priv->fw_var = le16_to_cpu(exp_if[i].variant); |
197 | break; | |
198 | case BR_CODE_DEPENDENT_IF: | |
199 | break; | |
200 | case BR_CODE_END_OF_BRA: | |
201 | case LEGACY_BR_CODE_END_OF_BRA: | |
202 | end_data = NULL; | |
203 | break; | |
204 | default: | |
205 | break; | |
206 | } | |
207 | bootrec = (struct bootrec *)&bootrec->data[len]; | |
208 | } | |
209 | ||
210 | if (fw_version) | |
211 | printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n", | |
212 | fw_version, priv->fw_var >> 8, priv->fw_var & 0xff); | |
213 | ||
214 | if (priv->fw_var >= 0x300) { | |
215 | /* Firmware supports QoS, use it! */ | |
84df3ed3 C |
216 | priv->tx_stats[4].limit = 3; |
217 | priv->tx_stats[5].limit = 4; | |
218 | priv->tx_stats[6].limit = 3; | |
219 | priv->tx_stats[7].limit = 1; | |
eff1a59c MW |
220 | dev->queues = 4; |
221 | } | |
4e416a6f CL |
222 | |
223 | return 0; | |
eff1a59c MW |
224 | } |
225 | EXPORT_SYMBOL_GPL(p54_parse_firmware); | |
226 | ||
154e3af1 CL |
227 | static int p54_convert_rev0(struct ieee80211_hw *dev, |
228 | struct pda_pa_curve_data *curve_data) | |
eff1a59c MW |
229 | { |
230 | struct p54_common *priv = dev->priv; | |
154e3af1 CL |
231 | struct p54_pa_curve_data_sample *dst; |
232 | struct pda_pa_curve_data_sample_rev0 *src; | |
eff1a59c | 233 | size_t cd_len = sizeof(*curve_data) + |
154e3af1 | 234 | (curve_data->points_per_channel*sizeof(*dst) + 2) * |
eff1a59c MW |
235 | curve_data->channels; |
236 | unsigned int i, j; | |
237 | void *source, *target; | |
238 | ||
239 | priv->curve_data = kmalloc(cd_len, GFP_KERNEL); | |
240 | if (!priv->curve_data) | |
241 | return -ENOMEM; | |
242 | ||
243 | memcpy(priv->curve_data, curve_data, sizeof(*curve_data)); | |
244 | source = curve_data->data; | |
245 | target = priv->curve_data->data; | |
246 | for (i = 0; i < curve_data->channels; i++) { | |
247 | __le16 *freq = source; | |
248 | source += sizeof(__le16); | |
249 | *((__le16 *)target) = *freq; | |
250 | target += sizeof(__le16); | |
251 | for (j = 0; j < curve_data->points_per_channel; j++) { | |
154e3af1 CL |
252 | dst = target; |
253 | src = source; | |
eff1a59c | 254 | |
154e3af1 CL |
255 | dst->rf_power = src->rf_power; |
256 | dst->pa_detector = src->pa_detector; | |
257 | dst->data_64qam = src->pcv; | |
eff1a59c MW |
258 | /* "invent" the points for the other modulations */ |
259 | #define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y) | |
154e3af1 CL |
260 | dst->data_16qam = SUB(src->pcv, 12); |
261 | dst->data_qpsk = SUB(dst->data_16qam, 12); | |
262 | dst->data_bpsk = SUB(dst->data_qpsk, 12); | |
263 | dst->data_barker = SUB(dst->data_bpsk, 14); | |
eff1a59c | 264 | #undef SUB |
154e3af1 CL |
265 | target += sizeof(*dst); |
266 | source += sizeof(*src); | |
eff1a59c MW |
267 | } |
268 | } | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
154e3af1 CL |
273 | static int p54_convert_rev1(struct ieee80211_hw *dev, |
274 | struct pda_pa_curve_data *curve_data) | |
275 | { | |
276 | struct p54_common *priv = dev->priv; | |
277 | struct p54_pa_curve_data_sample *dst; | |
278 | struct pda_pa_curve_data_sample_rev1 *src; | |
279 | size_t cd_len = sizeof(*curve_data) + | |
280 | (curve_data->points_per_channel*sizeof(*dst) + 2) * | |
281 | curve_data->channels; | |
282 | unsigned int i, j; | |
283 | void *source, *target; | |
284 | ||
285 | priv->curve_data = kmalloc(cd_len, GFP_KERNEL); | |
286 | if (!priv->curve_data) | |
287 | return -ENOMEM; | |
288 | ||
289 | memcpy(priv->curve_data, curve_data, sizeof(*curve_data)); | |
290 | source = curve_data->data; | |
291 | target = priv->curve_data->data; | |
292 | for (i = 0; i < curve_data->channels; i++) { | |
293 | __le16 *freq = source; | |
294 | source += sizeof(__le16); | |
295 | *((__le16 *)target) = *freq; | |
296 | target += sizeof(__le16); | |
297 | for (j = 0; j < curve_data->points_per_channel; j++) { | |
298 | memcpy(target, source, sizeof(*src)); | |
299 | ||
300 | target += sizeof(*dst); | |
301 | source += sizeof(*src); | |
302 | } | |
303 | source++; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
7cb77072 CL |
309 | const char* p54_rf_chips[] = { "NULL", "Indigo?", "Duette", |
310 | "Frisbee", "Xbow", "Longbow" }; | |
1b997534 | 311 | static int p54_init_xbow_synth(struct ieee80211_hw *dev); |
7cb77072 | 312 | |
eff1a59c MW |
313 | int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len) |
314 | { | |
315 | struct p54_common *priv = dev->priv; | |
316 | struct eeprom_pda_wrap *wrap = NULL; | |
317 | struct pda_entry *entry; | |
eff1a59c MW |
318 | unsigned int data_len, entry_len; |
319 | void *tmp; | |
320 | int err; | |
c2f2d3a0 | 321 | u8 *end = (u8 *)eeprom + len; |
7cb77072 | 322 | DECLARE_MAC_BUF(mac); |
eff1a59c MW |
323 | |
324 | wrap = (struct eeprom_pda_wrap *) eeprom; | |
8c28293f | 325 | entry = (void *)wrap->data + le16_to_cpu(wrap->len); |
c2f2d3a0 JB |
326 | |
327 | /* verify that at least the entry length/code fits */ | |
328 | while ((u8 *)entry <= end - sizeof(*entry)) { | |
eff1a59c MW |
329 | entry_len = le16_to_cpu(entry->len); |
330 | data_len = ((entry_len - 1) << 1); | |
c2f2d3a0 JB |
331 | |
332 | /* abort if entry exceeds whole structure */ | |
333 | if ((u8 *)entry + sizeof(*entry) + data_len > end) | |
334 | break; | |
335 | ||
eff1a59c MW |
336 | switch (le16_to_cpu(entry->code)) { |
337 | case PDR_MAC_ADDRESS: | |
338 | SET_IEEE80211_PERM_ADDR(dev, entry->data); | |
339 | break; | |
340 | case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS: | |
341 | if (data_len < 2) { | |
342 | err = -EINVAL; | |
343 | goto err; | |
344 | } | |
345 | ||
346 | if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) { | |
347 | err = -EINVAL; | |
348 | goto err; | |
349 | } | |
350 | ||
351 | priv->output_limit = kmalloc(entry->data[1] * | |
352 | sizeof(*priv->output_limit), GFP_KERNEL); | |
353 | ||
354 | if (!priv->output_limit) { | |
355 | err = -ENOMEM; | |
356 | goto err; | |
357 | } | |
358 | ||
359 | memcpy(priv->output_limit, &entry->data[2], | |
360 | entry->data[1]*sizeof(*priv->output_limit)); | |
361 | priv->output_limit_len = entry->data[1]; | |
362 | break; | |
154e3af1 CL |
363 | case PDR_PRISM_PA_CAL_CURVE_DATA: { |
364 | struct pda_pa_curve_data *curve_data = | |
365 | (struct pda_pa_curve_data *)entry->data; | |
366 | if (data_len < sizeof(*curve_data)) { | |
eff1a59c MW |
367 | err = -EINVAL; |
368 | goto err; | |
369 | } | |
370 | ||
154e3af1 CL |
371 | switch (curve_data->cal_method_rev) { |
372 | case 0: | |
373 | err = p54_convert_rev0(dev, curve_data); | |
374 | break; | |
375 | case 1: | |
376 | err = p54_convert_rev1(dev, curve_data); | |
377 | break; | |
378 | default: | |
379 | printk(KERN_ERR "p54: unknown curve data " | |
380 | "revision %d\n", | |
381 | curve_data->cal_method_rev); | |
382 | err = -ENODEV; | |
383 | break; | |
eff1a59c | 384 | } |
154e3af1 CL |
385 | if (err) |
386 | goto err; | |
eff1a59c | 387 | |
154e3af1 | 388 | } |
eff1a59c MW |
389 | case PDR_PRISM_ZIF_TX_IQ_CALIBRATION: |
390 | priv->iq_autocal = kmalloc(data_len, GFP_KERNEL); | |
391 | if (!priv->iq_autocal) { | |
392 | err = -ENOMEM; | |
393 | goto err; | |
394 | } | |
395 | ||
396 | memcpy(priv->iq_autocal, entry->data, data_len); | |
397 | priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry); | |
398 | break; | |
399 | case PDR_INTERFACE_LIST: | |
400 | tmp = entry->data; | |
401 | while ((u8 *)tmp < entry->data + data_len) { | |
402 | struct bootrec_exp_if *exp_if = tmp; | |
403 | if (le16_to_cpu(exp_if->if_id) == 0xF) | |
7cb77072 | 404 | priv->rxhw = le16_to_cpu(exp_if->variant) & 0x07; |
eff1a59c MW |
405 | tmp += sizeof(struct bootrec_exp_if); |
406 | } | |
407 | break; | |
408 | case PDR_HARDWARE_PLATFORM_COMPONENT_ID: | |
409 | priv->version = *(u8 *)(entry->data + 1); | |
410 | break; | |
411 | case PDR_END: | |
c2f2d3a0 JB |
412 | /* make it overrun */ |
413 | entry_len = len; | |
eff1a59c | 414 | break; |
58e30739 FF |
415 | default: |
416 | printk(KERN_INFO "p54: unknown eeprom code : 0x%x\n", | |
417 | le16_to_cpu(entry->code)); | |
418 | break; | |
eff1a59c MW |
419 | } |
420 | ||
421 | entry = (void *)entry + (entry_len + 1)*2; | |
eff1a59c MW |
422 | } |
423 | ||
424 | if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) { | |
425 | printk(KERN_ERR "p54: not all required entries found in eeprom!\n"); | |
426 | err = -EINVAL; | |
427 | goto err; | |
428 | } | |
429 | ||
7cb77072 | 430 | switch (priv->rxhw) { |
1b997534 CL |
431 | case 4: /* XBow */ |
432 | p54_init_xbow_synth(dev); | |
433 | case 1: /* Indigo? */ | |
434 | case 2: /* Duette */ | |
435 | dev->wiphy->bands[IEEE80211_BAND_5GHZ] = &band_5GHz; | |
436 | case 3: /* Frisbee */ | |
437 | case 5: /* Longbow */ | |
438 | dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz; | |
439 | break; | |
440 | default: | |
441 | printk(KERN_ERR "%s: unsupported RF-Chip\n", | |
442 | wiphy_name(dev->wiphy)); | |
443 | err = -EINVAL; | |
444 | goto err; | |
7cb77072 CL |
445 | } |
446 | ||
447 | if (!is_valid_ether_addr(dev->wiphy->perm_addr)) { | |
448 | u8 perm_addr[ETH_ALEN]; | |
449 | ||
450 | printk(KERN_WARNING "%s: Invalid hwaddr! Using randomly generated MAC addr\n", | |
451 | wiphy_name(dev->wiphy)); | |
452 | random_ether_addr(perm_addr); | |
453 | SET_IEEE80211_PERM_ADDR(dev, perm_addr); | |
454 | } | |
455 | ||
456 | printk(KERN_INFO "%s: hwaddr %s, MAC:isl38%02x RF:%s\n", | |
457 | wiphy_name(dev->wiphy), | |
458 | print_mac(mac, dev->wiphy->perm_addr), | |
459 | priv->version, p54_rf_chips[priv->rxhw]); | |
460 | ||
eff1a59c MW |
461 | return 0; |
462 | ||
463 | err: | |
464 | if (priv->iq_autocal) { | |
465 | kfree(priv->iq_autocal); | |
466 | priv->iq_autocal = NULL; | |
467 | } | |
468 | ||
469 | if (priv->output_limit) { | |
470 | kfree(priv->output_limit); | |
471 | priv->output_limit = NULL; | |
472 | } | |
473 | ||
474 | if (priv->curve_data) { | |
475 | kfree(priv->curve_data); | |
476 | priv->curve_data = NULL; | |
477 | } | |
478 | ||
479 | printk(KERN_ERR "p54: eeprom parse failed!\n"); | |
480 | return err; | |
481 | } | |
482 | EXPORT_SYMBOL_GPL(p54_parse_eeprom); | |
483 | ||
cc6de669 CL |
484 | static int p54_rssi_to_dbm(struct ieee80211_hw *dev, int rssi) |
485 | { | |
486 | /* TODO: get the rssi_add & rssi_mul data from the eeprom */ | |
487 | return ((rssi * 0x83) / 64 - 400) / 4; | |
488 | } | |
489 | ||
19c19d54 | 490 | static int p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb) |
eff1a59c | 491 | { |
a0db663f | 492 | struct p54_common *priv = dev->priv; |
eff1a59c MW |
493 | struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data; |
494 | struct ieee80211_rx_status rx_status = {0}; | |
495 | u16 freq = le16_to_cpu(hdr->freq); | |
19c19d54 | 496 | size_t header_len = sizeof(*hdr); |
a0db663f | 497 | u32 tsf32; |
eff1a59c | 498 | |
78d57eb2 CL |
499 | if (!(hdr->magic & cpu_to_le16(0x0001))) { |
500 | if (priv->filter_flags & FIF_FCSFAIL) | |
501 | rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; | |
502 | else | |
503 | return 0; | |
504 | } | |
505 | ||
cc6de669 CL |
506 | rx_status.signal = p54_rssi_to_dbm(dev, hdr->rssi); |
507 | rx_status.noise = priv->noise; | |
8318d78a | 508 | /* XX correct? */ |
18d72605 | 509 | rx_status.qual = (100 * hdr->rssi) / 127; |
8318d78a | 510 | rx_status.rate_idx = hdr->rate & 0xf; |
eff1a59c | 511 | rx_status.freq = freq; |
8318d78a | 512 | rx_status.band = IEEE80211_BAND_2GHZ; |
eff1a59c | 513 | rx_status.antenna = hdr->antenna; |
a0db663f CL |
514 | |
515 | tsf32 = le32_to_cpu(hdr->tsf32); | |
516 | if (tsf32 < priv->tsf_low32) | |
517 | priv->tsf_high32++; | |
518 | rx_status.mactime = ((u64)priv->tsf_high32) << 32 | tsf32; | |
519 | priv->tsf_low32 = tsf32; | |
520 | ||
03bffc13 | 521 | rx_status.flag |= RX_FLAG_TSFT; |
eff1a59c | 522 | |
19c19d54 CL |
523 | if (hdr->magic & cpu_to_le16(0x4000)) |
524 | header_len += hdr->align[0]; | |
525 | ||
526 | skb_pull(skb, header_len); | |
eff1a59c MW |
527 | skb_trim(skb, le16_to_cpu(hdr->len)); |
528 | ||
529 | ieee80211_rx_irqsafe(dev, skb, &rx_status); | |
19c19d54 CL |
530 | |
531 | return -1; | |
eff1a59c MW |
532 | } |
533 | ||
534 | static void inline p54_wake_free_queues(struct ieee80211_hw *dev) | |
535 | { | |
536 | struct p54_common *priv = dev->priv; | |
537 | int i; | |
538 | ||
eff1a59c | 539 | for (i = 0; i < dev->queues; i++) |
84df3ed3 | 540 | if (priv->tx_stats[i + 4].len < priv->tx_stats[i + 4].limit) |
eff1a59c MW |
541 | ieee80211_wake_queue(dev, i); |
542 | } | |
543 | ||
544 | static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb) | |
545 | { | |
546 | struct p54_common *priv = dev->priv; | |
547 | struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data; | |
548 | struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data; | |
549 | struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next; | |
4e416a6f | 550 | u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom; |
eff1a59c MW |
551 | struct memrecord *range = NULL; |
552 | u32 freed = 0; | |
553 | u32 last_addr = priv->rx_start; | |
031d10ee | 554 | unsigned long flags; |
eff1a59c | 555 | |
031d10ee | 556 | spin_lock_irqsave(&priv->tx_queue.lock, flags); |
eff1a59c | 557 | while (entry != (struct sk_buff *)&priv->tx_queue) { |
552fe53f JB |
558 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry); |
559 | range = (void *)info->driver_data; | |
eff1a59c | 560 | if (range->start_addr == addr) { |
eff1a59c MW |
561 | struct p54_control_hdr *entry_hdr; |
562 | struct p54_tx_control_allocdata *entry_data; | |
563 | int pad = 0; | |
564 | ||
552fe53f JB |
565 | if (entry->next != (struct sk_buff *)&priv->tx_queue) { |
566 | struct ieee80211_tx_info *ni; | |
567 | struct memrecord *mr; | |
568 | ||
569 | ni = IEEE80211_SKB_CB(entry->next); | |
570 | mr = (struct memrecord *)ni->driver_data; | |
571 | freed = mr->start_addr - last_addr; | |
572 | } else | |
eff1a59c MW |
573 | freed = priv->rx_end - last_addr; |
574 | ||
575 | last_addr = range->end_addr; | |
576 | __skb_unlink(entry, &priv->tx_queue); | |
031d10ee C |
577 | spin_unlock_irqrestore(&priv->tx_queue.lock, flags); |
578 | ||
e039fa4a | 579 | memset(&info->status, 0, sizeof(info->status)); |
eff1a59c MW |
580 | entry_hdr = (struct p54_control_hdr *) entry->data; |
581 | entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data; | |
582 | if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0) | |
583 | pad = entry_data->align[0]; | |
584 | ||
84df3ed3 | 585 | priv->tx_stats[entry_data->hw_queue].len--; |
e039fa4a | 586 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
eff1a59c | 587 | if (!(payload->status & 0x01)) |
e039fa4a | 588 | info->flags |= IEEE80211_TX_STAT_ACK; |
eff1a59c | 589 | else |
e039fa4a | 590 | info->status.excessive_retries = 1; |
eff1a59c | 591 | } |
e039fa4a | 592 | info->status.retry_count = payload->retries - 1; |
cc6de669 CL |
593 | info->status.ack_signal = p54_rssi_to_dbm(dev, |
594 | le16_to_cpu(payload->ack_rssi)); | |
eff1a59c | 595 | skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data)); |
e039fa4a | 596 | ieee80211_tx_status_irqsafe(dev, entry); |
031d10ee | 597 | goto out; |
eff1a59c MW |
598 | } else |
599 | last_addr = range->end_addr; | |
600 | entry = entry->next; | |
601 | } | |
031d10ee | 602 | spin_unlock_irqrestore(&priv->tx_queue.lock, flags); |
eff1a59c | 603 | |
031d10ee | 604 | out: |
eff1a59c MW |
605 | if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 + |
606 | sizeof(struct p54_control_hdr)) | |
607 | p54_wake_free_queues(dev); | |
608 | } | |
609 | ||
7cb77072 CL |
610 | static void p54_rx_eeprom_readback(struct ieee80211_hw *dev, |
611 | struct sk_buff *skb) | |
612 | { | |
613 | struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data; | |
614 | struct p54_eeprom_lm86 *eeprom = (struct p54_eeprom_lm86 *) hdr->data; | |
615 | struct p54_common *priv = dev->priv; | |
616 | ||
617 | if (!priv->eeprom) | |
618 | return ; | |
619 | ||
620 | memcpy(priv->eeprom, eeprom->data, eeprom->len); | |
621 | ||
622 | complete(&priv->eeprom_comp); | |
623 | } | |
624 | ||
cc6de669 CL |
625 | static void p54_rx_stats(struct ieee80211_hw *dev, struct sk_buff *skb) |
626 | { | |
627 | struct p54_common *priv = dev->priv; | |
628 | struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data; | |
629 | struct p54_statistics *stats = (struct p54_statistics *) hdr->data; | |
630 | u32 tsf32 = le32_to_cpu(stats->tsf32); | |
631 | ||
632 | if (tsf32 < priv->tsf_low32) | |
633 | priv->tsf_high32++; | |
634 | priv->tsf_low32 = tsf32; | |
635 | ||
636 | priv->stats.dot11RTSFailureCount = le32_to_cpu(stats->rts_fail); | |
637 | priv->stats.dot11RTSSuccessCount = le32_to_cpu(stats->rts_success); | |
638 | priv->stats.dot11FCSErrorCount = le32_to_cpu(stats->rx_bad_fcs); | |
639 | ||
640 | priv->noise = p54_rssi_to_dbm(dev, le32_to_cpu(stats->noise)); | |
641 | complete(&priv->stats_comp); | |
642 | ||
643 | mod_timer(&priv->stats_timer, jiffies + 5 * HZ); | |
644 | } | |
645 | ||
19c19d54 | 646 | static int p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb) |
eff1a59c MW |
647 | { |
648 | struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data; | |
649 | ||
650 | switch (le16_to_cpu(hdr->type)) { | |
651 | case P54_CONTROL_TYPE_TXDONE: | |
652 | p54_rx_frame_sent(dev, skb); | |
653 | break; | |
654 | case P54_CONTROL_TYPE_BBP: | |
655 | break; | |
cc6de669 CL |
656 | case P54_CONTROL_TYPE_STAT_READBACK: |
657 | p54_rx_stats(dev, skb); | |
658 | break; | |
7cb77072 CL |
659 | case P54_CONTROL_TYPE_EEPROM_READBACK: |
660 | p54_rx_eeprom_readback(dev, skb); | |
661 | break; | |
eff1a59c MW |
662 | default: |
663 | printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n", | |
664 | wiphy_name(dev->wiphy), le16_to_cpu(hdr->type)); | |
665 | break; | |
666 | } | |
19c19d54 CL |
667 | |
668 | return 0; | |
eff1a59c MW |
669 | } |
670 | ||
671 | /* returns zero if skb can be reused */ | |
672 | int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb) | |
673 | { | |
674 | u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8; | |
19c19d54 CL |
675 | |
676 | if (type == 0x80) | |
677 | return p54_rx_control(dev, skb); | |
678 | else | |
679 | return p54_rx_data(dev, skb); | |
eff1a59c MW |
680 | } |
681 | EXPORT_SYMBOL_GPL(p54_rx); | |
682 | ||
683 | /* | |
684 | * So, the firmware is somewhat stupid and doesn't know what places in its | |
685 | * memory incoming data should go to. By poking around in the firmware, we | |
686 | * can find some unused memory to upload our packets to. However, data that we | |
687 | * want the card to TX needs to stay intact until the card has told us that | |
688 | * it is done with it. This function finds empty places we can upload to and | |
689 | * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees | |
690 | * allocated areas. | |
691 | */ | |
692 | static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb, | |
e039fa4a | 693 | struct p54_control_hdr *data, u32 len) |
eff1a59c MW |
694 | { |
695 | struct p54_common *priv = dev->priv; | |
696 | struct sk_buff *entry = priv->tx_queue.next; | |
697 | struct sk_buff *target_skb = NULL; | |
eff1a59c MW |
698 | u32 last_addr = priv->rx_start; |
699 | u32 largest_hole = 0; | |
700 | u32 target_addr = priv->rx_start; | |
701 | unsigned long flags; | |
702 | unsigned int left; | |
4e416a6f | 703 | len = (len + priv->headroom + priv->tailroom + 3) & ~0x3; |
eff1a59c MW |
704 | |
705 | spin_lock_irqsave(&priv->tx_queue.lock, flags); | |
706 | left = skb_queue_len(&priv->tx_queue); | |
707 | while (left--) { | |
708 | u32 hole_size; | |
e039fa4a JB |
709 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry); |
710 | struct memrecord *range = (void *)info->driver_data; | |
eff1a59c MW |
711 | hole_size = range->start_addr - last_addr; |
712 | if (!target_skb && hole_size >= len) { | |
713 | target_skb = entry->prev; | |
714 | hole_size -= len; | |
715 | target_addr = last_addr; | |
716 | } | |
717 | largest_hole = max(largest_hole, hole_size); | |
718 | last_addr = range->end_addr; | |
719 | entry = entry->next; | |
720 | } | |
721 | if (!target_skb && priv->rx_end - last_addr >= len) { | |
722 | target_skb = priv->tx_queue.prev; | |
723 | largest_hole = max(largest_hole, priv->rx_end - last_addr - len); | |
724 | if (!skb_queue_empty(&priv->tx_queue)) { | |
e039fa4a JB |
725 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(target_skb); |
726 | struct memrecord *range = (void *)info->driver_data; | |
eff1a59c MW |
727 | target_addr = range->end_addr; |
728 | } | |
729 | } else | |
730 | largest_hole = max(largest_hole, priv->rx_end - last_addr); | |
731 | ||
732 | if (skb) { | |
e039fa4a JB |
733 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
734 | struct memrecord *range = (void *)info->driver_data; | |
eff1a59c MW |
735 | range->start_addr = target_addr; |
736 | range->end_addr = target_addr + len; | |
eff1a59c | 737 | __skb_queue_after(&priv->tx_queue, target_skb, skb); |
4e416a6f CL |
738 | if (largest_hole < priv->rx_mtu + priv->headroom + |
739 | priv->tailroom + | |
eff1a59c MW |
740 | sizeof(struct p54_control_hdr)) |
741 | ieee80211_stop_queues(dev); | |
742 | } | |
743 | spin_unlock_irqrestore(&priv->tx_queue.lock, flags); | |
744 | ||
4e416a6f | 745 | data->req_id = cpu_to_le32(target_addr + priv->headroom); |
eff1a59c MW |
746 | } |
747 | ||
7cb77072 CL |
748 | int p54_read_eeprom(struct ieee80211_hw *dev) |
749 | { | |
750 | struct p54_common *priv = dev->priv; | |
751 | struct p54_control_hdr *hdr = NULL; | |
752 | struct p54_eeprom_lm86 *eeprom_hdr; | |
753 | size_t eeprom_size = 0x2020, offset = 0, blocksize; | |
754 | int ret = -ENOMEM; | |
755 | void *eeprom = NULL; | |
756 | ||
757 | hdr = (struct p54_control_hdr *)kzalloc(sizeof(*hdr) + | |
758 | sizeof(*eeprom_hdr) + EEPROM_READBACK_LEN, GFP_KERNEL); | |
759 | if (!hdr) | |
760 | goto free; | |
761 | ||
762 | priv->eeprom = kzalloc(EEPROM_READBACK_LEN, GFP_KERNEL); | |
763 | if (!priv->eeprom) | |
764 | goto free; | |
765 | ||
766 | eeprom = kzalloc(eeprom_size, GFP_KERNEL); | |
767 | if (!eeprom) | |
768 | goto free; | |
769 | ||
770 | hdr->magic1 = cpu_to_le16(0x8000); | |
771 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK); | |
772 | hdr->retry1 = hdr->retry2 = 0; | |
773 | eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data; | |
774 | ||
775 | while (eeprom_size) { | |
776 | blocksize = min(eeprom_size, (size_t)EEPROM_READBACK_LEN); | |
777 | hdr->len = cpu_to_le16(blocksize + sizeof(*eeprom_hdr)); | |
778 | eeprom_hdr->offset = cpu_to_le16(offset); | |
779 | eeprom_hdr->len = cpu_to_le16(blocksize); | |
780 | p54_assign_address(dev, NULL, hdr, hdr->len + sizeof(*hdr)); | |
781 | priv->tx(dev, hdr, hdr->len + sizeof(*hdr), 0); | |
782 | ||
783 | if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) { | |
784 | printk(KERN_ERR "%s: device does not respond!\n", | |
785 | wiphy_name(dev->wiphy)); | |
786 | ret = -EBUSY; | |
787 | goto free; | |
788 | } | |
789 | ||
790 | memcpy(eeprom + offset, priv->eeprom, blocksize); | |
791 | offset += blocksize; | |
792 | eeprom_size -= blocksize; | |
793 | } | |
794 | ||
795 | ret = p54_parse_eeprom(dev, eeprom, offset); | |
796 | free: | |
797 | kfree(priv->eeprom); | |
798 | priv->eeprom = NULL; | |
799 | kfree(hdr); | |
800 | kfree(eeprom); | |
801 | ||
802 | return ret; | |
803 | } | |
804 | EXPORT_SYMBOL_GPL(p54_read_eeprom); | |
805 | ||
e039fa4a | 806 | static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb) |
eff1a59c | 807 | { |
e039fa4a | 808 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
57ffc589 | 809 | struct ieee80211_tx_queue_stats *current_queue; |
eff1a59c MW |
810 | struct p54_common *priv = dev->priv; |
811 | struct p54_control_hdr *hdr; | |
eda0c003 | 812 | struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data; |
eff1a59c | 813 | struct p54_tx_control_allocdata *txhdr; |
eff1a59c MW |
814 | size_t padding, len; |
815 | u8 rate; | |
aaa15535 | 816 | u8 cts_rate = 0x20; |
eff1a59c | 817 | |
84df3ed3 | 818 | current_queue = &priv->tx_stats[skb_get_queue_mapping(skb) + 4]; |
eff1a59c MW |
819 | if (unlikely(current_queue->len > current_queue->limit)) |
820 | return NETDEV_TX_BUSY; | |
821 | current_queue->len++; | |
822 | current_queue->count++; | |
823 | if (current_queue->len == current_queue->limit) | |
e2530083 | 824 | ieee80211_stop_queue(dev, skb_get_queue_mapping(skb)); |
eff1a59c MW |
825 | |
826 | padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3; | |
827 | len = skb->len; | |
828 | ||
eff1a59c MW |
829 | txhdr = (struct p54_tx_control_allocdata *) |
830 | skb_push(skb, sizeof(*txhdr) + padding); | |
831 | hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr)); | |
832 | ||
833 | if (padding) | |
834 | hdr->magic1 = cpu_to_le16(0x4010); | |
835 | else | |
836 | hdr->magic1 = cpu_to_le16(0x0010); | |
837 | hdr->len = cpu_to_le16(len); | |
e039fa4a JB |
838 | hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1); |
839 | hdr->retry1 = hdr->retry2 = info->control.retry_limit; | |
eff1a59c | 840 | |
eff1a59c | 841 | /* TODO: add support for alternate retry TX rates */ |
e039fa4a | 842 | rate = ieee80211_get_tx_rate(dev, info)->hw_value; |
aaa15535 | 843 | if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) { |
8318d78a | 844 | rate |= 0x10; |
aaa15535 CL |
845 | cts_rate |= 0x10; |
846 | } | |
847 | if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) { | |
eff1a59c | 848 | rate |= 0x40; |
aaa15535 CL |
849 | cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value; |
850 | } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) { | |
eff1a59c | 851 | rate |= 0x20; |
aaa15535 CL |
852 | cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value; |
853 | } | |
eff1a59c | 854 | memset(txhdr->rateset, rate, 8); |
aaa15535 CL |
855 | txhdr->key_type = 0; |
856 | txhdr->key_len = 0; | |
857 | txhdr->hw_queue = skb_get_queue_mapping(skb) + 4; | |
858 | txhdr->tx_antenna = (info->antenna_sel_tx == 0) ? | |
e039fa4a | 859 | 2 : info->antenna_sel_tx - 1; |
09adf284 | 860 | txhdr->output_power = priv->output_power; |
aaa15535 CL |
861 | txhdr->cts_rate = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? |
862 | 0 : cts_rate; | |
eff1a59c MW |
863 | if (padding) |
864 | txhdr->align[0] = padding; | |
865 | ||
eda0c003 LF |
866 | /* FIXME: The sequence that follows is needed for this driver to |
867 | * work with mac80211 since "mac80211: fix TX sequence numbers". | |
868 | * As with the temporary code in rt2x00, changes will be needed | |
869 | * to get proper sequence numbers on beacons. In addition, this | |
870 | * patch places the sequence number in the hardware state, which | |
871 | * limits us to a single virtual state. | |
872 | */ | |
873 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
874 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
875 | priv->seqno += 0x10; | |
876 | ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
877 | ieee80211hdr->seq_ctrl |= cpu_to_le16(priv->seqno); | |
878 | } | |
e039fa4a JB |
879 | /* modifies skb->cb and with it info, so must be last! */ |
880 | p54_assign_address(dev, skb, hdr, skb->len); | |
881 | ||
eff1a59c MW |
882 | priv->tx(dev, hdr, skb->len, 0); |
883 | return 0; | |
884 | } | |
885 | ||
886 | static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type, | |
e0a58eac | 887 | const u8 *bssid) |
eff1a59c MW |
888 | { |
889 | struct p54_common *priv = dev->priv; | |
890 | struct p54_control_hdr *hdr; | |
891 | struct p54_tx_control_filter *filter; | |
19c19d54 | 892 | size_t data_len; |
eff1a59c MW |
893 | |
894 | hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) + | |
ba8007ce | 895 | priv->tx_hdr_len, GFP_ATOMIC); |
eff1a59c MW |
896 | if (!hdr) |
897 | return -ENOMEM; | |
898 | ||
899 | hdr = (void *)hdr + priv->tx_hdr_len; | |
900 | ||
901 | filter = (struct p54_tx_control_filter *) hdr->data; | |
902 | hdr->magic1 = cpu_to_le16(0x8001); | |
eff1a59c MW |
903 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET); |
904 | ||
e0a58eac CL |
905 | priv->filter_type = filter->filter_type = cpu_to_le16(filter_type); |
906 | memcpy(filter->mac_addr, priv->mac_addr, ETH_ALEN); | |
907 | if (!bssid) | |
908 | memset(filter->bssid, ~0, ETH_ALEN); | |
eff1a59c | 909 | else |
e0a58eac CL |
910 | memcpy(filter->bssid, bssid, ETH_ALEN); |
911 | ||
912 | filter->rx_antenna = priv->rx_antenna; | |
eff1a59c | 913 | |
19c19d54 CL |
914 | if (priv->fw_var < 0x500) { |
915 | data_len = P54_TX_CONTROL_FILTER_V1_LEN; | |
916 | filter->v1.basic_rate_mask = cpu_to_le32(0x15F); | |
917 | filter->v1.rx_addr = cpu_to_le32(priv->rx_end); | |
918 | filter->v1.max_rx = cpu_to_le16(priv->rx_mtu); | |
919 | filter->v1.rxhw = cpu_to_le16(priv->rxhw); | |
920 | filter->v1.wakeup_timer = cpu_to_le16(500); | |
921 | } else { | |
922 | data_len = P54_TX_CONTROL_FILTER_V2_LEN; | |
923 | filter->v2.rx_addr = cpu_to_le32(priv->rx_end); | |
924 | filter->v2.max_rx = cpu_to_le16(priv->rx_mtu); | |
925 | filter->v2.rxhw = cpu_to_le16(priv->rxhw); | |
926 | filter->v2.timer = cpu_to_le16(1000); | |
927 | } | |
928 | ||
929 | hdr->len = cpu_to_le16(data_len); | |
930 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + data_len); | |
931 | priv->tx(dev, hdr, sizeof(*hdr) + data_len, 1); | |
eff1a59c MW |
932 | return 0; |
933 | } | |
934 | ||
935 | static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq) | |
936 | { | |
937 | struct p54_common *priv = dev->priv; | |
938 | struct p54_control_hdr *hdr; | |
939 | struct p54_tx_control_channel *chan; | |
940 | unsigned int i; | |
19c19d54 | 941 | size_t data_len; |
eff1a59c MW |
942 | void *entry; |
943 | ||
154e3af1 | 944 | hdr = kzalloc(sizeof(*hdr) + sizeof(*chan) + |
eff1a59c MW |
945 | priv->tx_hdr_len, GFP_KERNEL); |
946 | if (!hdr) | |
947 | return -ENOMEM; | |
948 | ||
949 | hdr = (void *)hdr + priv->tx_hdr_len; | |
950 | ||
951 | chan = (struct p54_tx_control_channel *) hdr->data; | |
952 | ||
953 | hdr->magic1 = cpu_to_le16(0x8001); | |
19c19d54 | 954 | |
eff1a59c | 955 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE); |
eff1a59c | 956 | |
154e3af1 CL |
957 | chan->flags = cpu_to_le16(0x1); |
958 | chan->dwell = cpu_to_le16(0x0); | |
eff1a59c MW |
959 | |
960 | for (i = 0; i < priv->iq_autocal_len; i++) { | |
961 | if (priv->iq_autocal[i].freq != freq) | |
962 | continue; | |
963 | ||
964 | memcpy(&chan->iq_autocal, &priv->iq_autocal[i], | |
965 | sizeof(*priv->iq_autocal)); | |
966 | break; | |
967 | } | |
968 | if (i == priv->iq_autocal_len) | |
969 | goto err; | |
970 | ||
971 | for (i = 0; i < priv->output_limit_len; i++) { | |
972 | if (priv->output_limit[i].freq != freq) | |
973 | continue; | |
974 | ||
975 | chan->val_barker = 0x38; | |
154e3af1 CL |
976 | chan->val_bpsk = chan->dup_bpsk = |
977 | priv->output_limit[i].val_bpsk; | |
978 | chan->val_qpsk = chan->dup_qpsk = | |
979 | priv->output_limit[i].val_qpsk; | |
980 | chan->val_16qam = chan->dup_16qam = | |
981 | priv->output_limit[i].val_16qam; | |
982 | chan->val_64qam = chan->dup_64qam = | |
983 | priv->output_limit[i].val_64qam; | |
eff1a59c MW |
984 | break; |
985 | } | |
986 | if (i == priv->output_limit_len) | |
987 | goto err; | |
988 | ||
eff1a59c MW |
989 | entry = priv->curve_data->data; |
990 | for (i = 0; i < priv->curve_data->channels; i++) { | |
991 | if (*((__le16 *)entry) != freq) { | |
992 | entry += sizeof(__le16); | |
154e3af1 CL |
993 | entry += sizeof(struct p54_pa_curve_data_sample) * |
994 | priv->curve_data->points_per_channel; | |
eff1a59c MW |
995 | continue; |
996 | } | |
997 | ||
998 | entry += sizeof(__le16); | |
154e3af1 CL |
999 | chan->pa_points_per_curve = |
1000 | min(priv->curve_data->points_per_channel, (u8) 8); | |
1001 | ||
eff1a59c MW |
1002 | memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) * |
1003 | chan->pa_points_per_curve); | |
1004 | break; | |
1005 | } | |
1006 | ||
19c19d54 CL |
1007 | if (priv->fw_var < 0x500) { |
1008 | data_len = P54_TX_CONTROL_CHANNEL_V1_LEN; | |
1009 | chan->v1.rssical_mul = cpu_to_le16(130); | |
1010 | chan->v1.rssical_add = cpu_to_le16(0xfe70); | |
1011 | } else { | |
1012 | data_len = P54_TX_CONTROL_CHANNEL_V2_LEN; | |
1013 | chan->v2.rssical_mul = cpu_to_le16(130); | |
1014 | chan->v2.rssical_add = cpu_to_le16(0xfe70); | |
1015 | chan->v2.basic_rate_mask = cpu_to_le32(0x15f); | |
1016 | } | |
eff1a59c | 1017 | |
19c19d54 CL |
1018 | hdr->len = cpu_to_le16(data_len); |
1019 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + data_len); | |
1020 | priv->tx(dev, hdr, sizeof(*hdr) + data_len, 1); | |
eff1a59c MW |
1021 | return 0; |
1022 | ||
1023 | err: | |
1024 | printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy)); | |
1025 | kfree(hdr); | |
1026 | return -EINVAL; | |
1027 | } | |
1028 | ||
1029 | static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act) | |
1030 | { | |
1031 | struct p54_common *priv = dev->priv; | |
1032 | struct p54_control_hdr *hdr; | |
1033 | struct p54_tx_control_led *led; | |
1034 | ||
1035 | hdr = kzalloc(sizeof(*hdr) + sizeof(*led) + | |
1036 | priv->tx_hdr_len, GFP_KERNEL); | |
1037 | if (!hdr) | |
1038 | return -ENOMEM; | |
1039 | ||
1040 | hdr = (void *)hdr + priv->tx_hdr_len; | |
1041 | hdr->magic1 = cpu_to_le16(0x8001); | |
1042 | hdr->len = cpu_to_le16(sizeof(*led)); | |
1043 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED); | |
e039fa4a | 1044 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led)); |
eff1a59c MW |
1045 | |
1046 | led = (struct p54_tx_control_led *) hdr->data; | |
1047 | led->mode = cpu_to_le16(mode); | |
1048 | led->led_permanent = cpu_to_le16(link); | |
1049 | led->led_temporary = cpu_to_le16(act); | |
1050 | led->duration = cpu_to_le16(1000); | |
1051 | ||
1052 | priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1); | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
3330d7be | 1057 | #define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \ |
eff1a59c MW |
1058 | do { \ |
1059 | queue.aifs = cpu_to_le16(ai_fs); \ | |
1060 | queue.cwmin = cpu_to_le16(cw_min); \ | |
1061 | queue.cwmax = cpu_to_le16(cw_max); \ | |
3330d7be | 1062 | queue.txop = cpu_to_le16(_txop); \ |
eff1a59c MW |
1063 | } while(0) |
1064 | ||
1065 | static void p54_init_vdcf(struct ieee80211_hw *dev) | |
1066 | { | |
1067 | struct p54_common *priv = dev->priv; | |
1068 | struct p54_control_hdr *hdr; | |
1069 | struct p54_tx_control_vdcf *vdcf; | |
1070 | ||
1071 | /* all USB V1 adapters need a extra headroom */ | |
1072 | hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len; | |
1073 | hdr->magic1 = cpu_to_le16(0x8001); | |
1074 | hdr->len = cpu_to_le16(sizeof(*vdcf)); | |
1075 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT); | |
1076 | hdr->req_id = cpu_to_le32(priv->rx_start); | |
1077 | ||
1078 | vdcf = (struct p54_tx_control_vdcf *) hdr->data; | |
1079 | ||
3330d7be JB |
1080 | P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 47); |
1081 | P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 94); | |
5200e8cd | 1082 | P54_SET_QUEUE(vdcf->queue[2], 0x0003, 0x000f, 0x03ff, 0); |
3330d7be | 1083 | P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0); |
eff1a59c MW |
1084 | } |
1085 | ||
1086 | static void p54_set_vdcf(struct ieee80211_hw *dev) | |
1087 | { | |
1088 | struct p54_common *priv = dev->priv; | |
1089 | struct p54_control_hdr *hdr; | |
1090 | struct p54_tx_control_vdcf *vdcf; | |
1091 | ||
1092 | hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len; | |
1093 | ||
e039fa4a | 1094 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf)); |
eff1a59c MW |
1095 | |
1096 | vdcf = (struct p54_tx_control_vdcf *) hdr->data; | |
1097 | ||
1098 | if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) { | |
1099 | vdcf->slottime = 9; | |
5423b2ed CL |
1100 | vdcf->magic1 = 0x10; |
1101 | vdcf->magic2 = 0x00; | |
eff1a59c MW |
1102 | } else { |
1103 | vdcf->slottime = 20; | |
1104 | vdcf->magic1 = 0x0a; | |
1105 | vdcf->magic2 = 0x06; | |
1106 | } | |
1107 | ||
1108 | /* (see prism54/isl_oid.h for further details) */ | |
1109 | vdcf->frameburst = cpu_to_le16(0); | |
1110 | ||
1111 | priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0); | |
1112 | } | |
1113 | ||
4150c572 JB |
1114 | static int p54_start(struct ieee80211_hw *dev) |
1115 | { | |
1116 | struct p54_common *priv = dev->priv; | |
1117 | int err; | |
1118 | ||
69bbc7dc CL |
1119 | if (!priv->cached_vdcf) { |
1120 | priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf)+ | |
1121 | priv->tx_hdr_len + sizeof(struct p54_control_hdr), | |
1122 | GFP_KERNEL); | |
1123 | ||
1124 | if (!priv->cached_vdcf) | |
1125 | return -ENOMEM; | |
1126 | } | |
1127 | ||
cc6de669 CL |
1128 | if (!priv->cached_stats) { |
1129 | priv->cached_stats = kzalloc(sizeof(struct p54_statistics) + | |
1130 | priv->tx_hdr_len + sizeof(struct p54_control_hdr), | |
1131 | GFP_KERNEL); | |
1132 | ||
1133 | if (!priv->cached_stats) { | |
1134 | kfree(priv->cached_vdcf); | |
1135 | priv->cached_vdcf = NULL; | |
1136 | return -ENOMEM; | |
1137 | } | |
1138 | } | |
1139 | ||
4150c572 JB |
1140 | err = priv->open(dev); |
1141 | if (!err) | |
1142 | priv->mode = IEEE80211_IF_TYPE_MNTR; | |
1143 | ||
69bbc7dc CL |
1144 | p54_init_vdcf(dev); |
1145 | ||
cc6de669 | 1146 | mod_timer(&priv->stats_timer, jiffies + HZ); |
4150c572 JB |
1147 | return err; |
1148 | } | |
1149 | ||
1150 | static void p54_stop(struct ieee80211_hw *dev) | |
1151 | { | |
1152 | struct p54_common *priv = dev->priv; | |
1153 | struct sk_buff *skb; | |
cc6de669 CL |
1154 | |
1155 | del_timer(&priv->stats_timer); | |
e039fa4a | 1156 | while ((skb = skb_dequeue(&priv->tx_queue))) |
4150c572 | 1157 | kfree_skb(skb); |
4150c572 | 1158 | priv->stop(dev); |
a0db663f | 1159 | priv->tsf_high32 = priv->tsf_low32 = 0; |
a2897552 | 1160 | priv->mode = IEEE80211_IF_TYPE_INVALID; |
4150c572 JB |
1161 | } |
1162 | ||
eff1a59c MW |
1163 | static int p54_add_interface(struct ieee80211_hw *dev, |
1164 | struct ieee80211_if_init_conf *conf) | |
1165 | { | |
1166 | struct p54_common *priv = dev->priv; | |
eff1a59c | 1167 | |
4150c572 JB |
1168 | if (priv->mode != IEEE80211_IF_TYPE_MNTR) |
1169 | return -EOPNOTSUPP; | |
eff1a59c MW |
1170 | |
1171 | switch (conf->type) { | |
1172 | case IEEE80211_IF_TYPE_STA: | |
1173 | priv->mode = conf->type; | |
1174 | break; | |
1175 | default: | |
1176 | return -EOPNOTSUPP; | |
1177 | } | |
1178 | ||
4150c572 | 1179 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); |
eff1a59c | 1180 | |
e0a58eac | 1181 | p54_set_filter(dev, 0, NULL); |
eff1a59c MW |
1182 | |
1183 | switch (conf->type) { | |
1184 | case IEEE80211_IF_TYPE_STA: | |
e0a58eac | 1185 | p54_set_filter(dev, 1, NULL); |
eff1a59c | 1186 | break; |
4150c572 JB |
1187 | default: |
1188 | BUG(); /* impossible */ | |
1189 | break; | |
eff1a59c MW |
1190 | } |
1191 | ||
1192 | p54_set_leds(dev, 1, 0, 0); | |
1193 | ||
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static void p54_remove_interface(struct ieee80211_hw *dev, | |
1198 | struct ieee80211_if_init_conf *conf) | |
1199 | { | |
1200 | struct p54_common *priv = dev->priv; | |
4150c572 JB |
1201 | priv->mode = IEEE80211_IF_TYPE_MNTR; |
1202 | memset(priv->mac_addr, 0, ETH_ALEN); | |
e0a58eac | 1203 | p54_set_filter(dev, 0, NULL); |
eff1a59c MW |
1204 | } |
1205 | ||
1206 | static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) | |
1207 | { | |
1208 | int ret; | |
6041e2a0 | 1209 | struct p54_common *priv = dev->priv; |
eff1a59c | 1210 | |
6041e2a0 | 1211 | mutex_lock(&priv->conf_mutex); |
e0a58eac CL |
1212 | priv->rx_antenna = (conf->antenna_sel_rx == 0) ? |
1213 | 2 : conf->antenna_sel_tx - 1; | |
09adf284 | 1214 | priv->output_power = conf->power_level << 2; |
8318d78a | 1215 | ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq)); |
eff1a59c | 1216 | p54_set_vdcf(dev); |
6041e2a0 | 1217 | mutex_unlock(&priv->conf_mutex); |
eff1a59c MW |
1218 | return ret; |
1219 | } | |
1220 | ||
32bfd35d JB |
1221 | static int p54_config_interface(struct ieee80211_hw *dev, |
1222 | struct ieee80211_vif *vif, | |
eff1a59c MW |
1223 | struct ieee80211_if_conf *conf) |
1224 | { | |
1225 | struct p54_common *priv = dev->priv; | |
1226 | ||
6041e2a0 | 1227 | mutex_lock(&priv->conf_mutex); |
e0a58eac | 1228 | p54_set_filter(dev, 0, conf->bssid); |
eff1a59c | 1229 | p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0); |
4150c572 | 1230 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); |
6041e2a0 | 1231 | mutex_unlock(&priv->conf_mutex); |
eff1a59c MW |
1232 | return 0; |
1233 | } | |
1234 | ||
4150c572 JB |
1235 | static void p54_configure_filter(struct ieee80211_hw *dev, |
1236 | unsigned int changed_flags, | |
1237 | unsigned int *total_flags, | |
1238 | int mc_count, struct dev_mc_list *mclist) | |
1239 | { | |
1240 | struct p54_common *priv = dev->priv; | |
1241 | ||
78d57eb2 CL |
1242 | *total_flags &= FIF_BCN_PRBRESP_PROMISC | |
1243 | FIF_PROMISC_IN_BSS | | |
1244 | FIF_FCSFAIL; | |
1245 | ||
1246 | priv->filter_flags = *total_flags; | |
4150c572 JB |
1247 | |
1248 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { | |
1249 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
78d57eb2 CL |
1250 | p54_set_filter(dev, priv->filter_type, NULL); |
1251 | else | |
1252 | p54_set_filter(dev, priv->filter_type, priv->bssid); | |
1253 | } | |
1254 | ||
1255 | if (changed_flags & FIF_PROMISC_IN_BSS) { | |
1256 | if (*total_flags & FIF_PROMISC_IN_BSS) | |
1257 | p54_set_filter(dev, priv->filter_type | | |
1258 | cpu_to_le16(0x8), NULL); | |
4150c572 | 1259 | else |
78d57eb2 CL |
1260 | p54_set_filter(dev, priv->filter_type & |
1261 | ~cpu_to_le16(0x8), priv->bssid); | |
4150c572 JB |
1262 | } |
1263 | } | |
1264 | ||
e100bb64 | 1265 | static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue, |
eff1a59c MW |
1266 | const struct ieee80211_tx_queue_params *params) |
1267 | { | |
1268 | struct p54_common *priv = dev->priv; | |
1269 | struct p54_tx_control_vdcf *vdcf; | |
1270 | ||
1271 | vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *) | |
1272 | ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data); | |
1273 | ||
3df5ee60 | 1274 | if ((params) && !(queue > 4)) { |
eff1a59c | 1275 | P54_SET_QUEUE(vdcf->queue[queue], params->aifs, |
3330d7be | 1276 | params->cw_min, params->cw_max, params->txop); |
eff1a59c MW |
1277 | } else |
1278 | return -EINVAL; | |
1279 | ||
1280 | p54_set_vdcf(dev); | |
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
1b997534 CL |
1285 | static int p54_init_xbow_synth(struct ieee80211_hw *dev) |
1286 | { | |
1287 | struct p54_common *priv = dev->priv; | |
1288 | struct p54_control_hdr *hdr; | |
1289 | struct p54_tx_control_xbow_synth *xbow; | |
1290 | ||
1291 | hdr = kzalloc(sizeof(*hdr) + sizeof(*xbow) + | |
1292 | priv->tx_hdr_len, GFP_KERNEL); | |
1293 | if (!hdr) | |
1294 | return -ENOMEM; | |
1295 | ||
1296 | hdr = (void *)hdr + priv->tx_hdr_len; | |
1297 | hdr->magic1 = cpu_to_le16(0x8001); | |
1298 | hdr->len = cpu_to_le16(sizeof(*xbow)); | |
1299 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_XBOW_SYNTH_CFG); | |
1300 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*xbow)); | |
1301 | ||
1302 | xbow = (struct p54_tx_control_xbow_synth *) hdr->data; | |
1303 | xbow->magic1 = cpu_to_le16(0x1); | |
1304 | xbow->magic2 = cpu_to_le16(0x2); | |
1305 | xbow->freq = cpu_to_le16(5390); | |
1306 | ||
1307 | priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*xbow), 1); | |
1308 | ||
1309 | return 0; | |
1310 | } | |
1311 | ||
cc6de669 CL |
1312 | static void p54_statistics_timer(unsigned long data) |
1313 | { | |
1314 | struct ieee80211_hw *dev = (struct ieee80211_hw *) data; | |
1315 | struct p54_common *priv = dev->priv; | |
1316 | struct p54_control_hdr *hdr; | |
1317 | struct p54_statistics *stats; | |
1318 | ||
1319 | BUG_ON(!priv->cached_stats); | |
1320 | ||
1321 | hdr = (void *)priv->cached_stats + priv->tx_hdr_len; | |
1322 | hdr->magic1 = cpu_to_le16(0x8000); | |
1323 | hdr->len = cpu_to_le16(sizeof(*stats)); | |
1324 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_STAT_READBACK); | |
1325 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*stats)); | |
1326 | ||
1327 | priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*stats), 0); | |
1328 | } | |
1329 | ||
eff1a59c MW |
1330 | static int p54_get_stats(struct ieee80211_hw *dev, |
1331 | struct ieee80211_low_level_stats *stats) | |
1332 | { | |
cc6de669 CL |
1333 | struct p54_common *priv = dev->priv; |
1334 | ||
1335 | del_timer(&priv->stats_timer); | |
1336 | p54_statistics_timer((unsigned long)dev); | |
1337 | ||
1338 | if (!wait_for_completion_interruptible_timeout(&priv->stats_comp, HZ)) { | |
1339 | printk(KERN_ERR "%s: device does not respond!\n", | |
1340 | wiphy_name(dev->wiphy)); | |
1341 | return -EBUSY; | |
1342 | } | |
1343 | ||
1344 | memcpy(stats, &priv->stats, sizeof(*stats)); | |
1345 | ||
eff1a59c MW |
1346 | return 0; |
1347 | } | |
1348 | ||
1349 | static int p54_get_tx_stats(struct ieee80211_hw *dev, | |
1350 | struct ieee80211_tx_queue_stats *stats) | |
1351 | { | |
1352 | struct p54_common *priv = dev->priv; | |
eff1a59c | 1353 | |
84df3ed3 | 1354 | memcpy(stats, &priv->tx_stats[4], sizeof(stats[0]) * dev->queues); |
eff1a59c MW |
1355 | |
1356 | return 0; | |
1357 | } | |
1358 | ||
1359 | static const struct ieee80211_ops p54_ops = { | |
1360 | .tx = p54_tx, | |
4150c572 JB |
1361 | .start = p54_start, |
1362 | .stop = p54_stop, | |
eff1a59c MW |
1363 | .add_interface = p54_add_interface, |
1364 | .remove_interface = p54_remove_interface, | |
1365 | .config = p54_config, | |
1366 | .config_interface = p54_config_interface, | |
4150c572 | 1367 | .configure_filter = p54_configure_filter, |
eff1a59c MW |
1368 | .conf_tx = p54_conf_tx, |
1369 | .get_stats = p54_get_stats, | |
1370 | .get_tx_stats = p54_get_tx_stats | |
1371 | }; | |
1372 | ||
1373 | struct ieee80211_hw *p54_init_common(size_t priv_data_len) | |
1374 | { | |
1375 | struct ieee80211_hw *dev; | |
1376 | struct p54_common *priv; | |
eff1a59c MW |
1377 | |
1378 | dev = ieee80211_alloc_hw(priv_data_len, &p54_ops); | |
1379 | if (!dev) | |
1380 | return NULL; | |
1381 | ||
1382 | priv = dev->priv; | |
a2897552 | 1383 | priv->mode = IEEE80211_IF_TYPE_INVALID; |
eff1a59c | 1384 | skb_queue_head_init(&priv->tx_queue); |
eff1a59c | 1385 | dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */ |
566bfe5a | 1386 | IEEE80211_HW_RX_INCLUDES_FCS | |
cc6de669 CL |
1387 | IEEE80211_HW_SIGNAL_DBM | |
1388 | IEEE80211_HW_NOISE_DBM; | |
f59ac048 LR |
1389 | |
1390 | dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
1391 | ||
eff1a59c | 1392 | dev->channel_change_time = 1000; /* TODO: find actual value */ |
eff1a59c | 1393 | |
84df3ed3 C |
1394 | priv->tx_stats[0].limit = 1; |
1395 | priv->tx_stats[1].limit = 1; | |
1396 | priv->tx_stats[2].limit = 1; | |
1397 | priv->tx_stats[3].limit = 1; | |
1398 | priv->tx_stats[4].limit = 5; | |
eff1a59c | 1399 | dev->queues = 1; |
cc6de669 | 1400 | priv->noise = -94; |
eff1a59c MW |
1401 | dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 + |
1402 | sizeof(struct p54_tx_control_allocdata); | |
1403 | ||
6041e2a0 | 1404 | mutex_init(&priv->conf_mutex); |
7cb77072 | 1405 | init_completion(&priv->eeprom_comp); |
cc6de669 CL |
1406 | init_completion(&priv->stats_comp); |
1407 | setup_timer(&priv->stats_timer, p54_statistics_timer, | |
1408 | (unsigned long)dev); | |
eff1a59c | 1409 | |
eff1a59c MW |
1410 | return dev; |
1411 | } | |
1412 | EXPORT_SYMBOL_GPL(p54_init_common); | |
1413 | ||
1414 | void p54_free_common(struct ieee80211_hw *dev) | |
1415 | { | |
1416 | struct p54_common *priv = dev->priv; | |
cc6de669 | 1417 | kfree(priv->cached_stats); |
eff1a59c MW |
1418 | kfree(priv->iq_autocal); |
1419 | kfree(priv->output_limit); | |
1420 | kfree(priv->curve_data); | |
1421 | kfree(priv->cached_vdcf); | |
1422 | } | |
1423 | EXPORT_SYMBOL_GPL(p54_free_common); | |
1424 | ||
1425 | static int __init p54_init(void) | |
1426 | { | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | static void __exit p54_exit(void) | |
1431 | { | |
1432 | } | |
1433 | ||
1434 | module_init(p54_init); | |
1435 | module_exit(p54_exit); |