Commit | Line | Data |
---|---|---|
eff1a59c MW |
1 | |
2 | /* | |
3 | * Common code for mac80211 Prism54 drivers | |
4 | * | |
5 | * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> | |
6 | * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de> | |
7 | * | |
8 | * Based on the islsm (softmac prism54) driver, which is: | |
9 | * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/firmware.h> | |
18 | #include <linux/etherdevice.h> | |
19 | ||
20 | #include <net/mac80211.h> | |
21 | ||
22 | #include "p54.h" | |
23 | #include "p54common.h" | |
24 | ||
25 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
26 | MODULE_DESCRIPTION("Softmac Prism54 common code"); | |
27 | MODULE_LICENSE("GPL"); | |
28 | MODULE_ALIAS("prism54common"); | |
29 | ||
8318d78a JB |
30 | static struct ieee80211_rate p54_rates[] = { |
31 | { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
32 | { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
33 | { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
34 | { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
35 | { .bitrate = 60, .hw_value = 4, }, | |
36 | { .bitrate = 90, .hw_value = 5, }, | |
37 | { .bitrate = 120, .hw_value = 6, }, | |
38 | { .bitrate = 180, .hw_value = 7, }, | |
39 | { .bitrate = 240, .hw_value = 8, }, | |
40 | { .bitrate = 360, .hw_value = 9, }, | |
41 | { .bitrate = 480, .hw_value = 10, }, | |
42 | { .bitrate = 540, .hw_value = 11, }, | |
43 | }; | |
44 | ||
45 | static struct ieee80211_channel p54_channels[] = { | |
46 | { .center_freq = 2412, .hw_value = 1, }, | |
47 | { .center_freq = 2417, .hw_value = 2, }, | |
48 | { .center_freq = 2422, .hw_value = 3, }, | |
49 | { .center_freq = 2427, .hw_value = 4, }, | |
50 | { .center_freq = 2432, .hw_value = 5, }, | |
51 | { .center_freq = 2437, .hw_value = 6, }, | |
52 | { .center_freq = 2442, .hw_value = 7, }, | |
53 | { .center_freq = 2447, .hw_value = 8, }, | |
54 | { .center_freq = 2452, .hw_value = 9, }, | |
55 | { .center_freq = 2457, .hw_value = 10, }, | |
56 | { .center_freq = 2462, .hw_value = 11, }, | |
57 | { .center_freq = 2467, .hw_value = 12, }, | |
58 | { .center_freq = 2472, .hw_value = 13, }, | |
59 | { .center_freq = 2484, .hw_value = 14, }, | |
60 | }; | |
61 | ||
c2976ab0 | 62 | static struct ieee80211_supported_band band_2GHz = { |
8318d78a JB |
63 | .channels = p54_channels, |
64 | .n_channels = ARRAY_SIZE(p54_channels), | |
65 | .bitrates = p54_rates, | |
66 | .n_bitrates = ARRAY_SIZE(p54_rates), | |
67 | }; | |
68 | ||
4e416a6f | 69 | int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw) |
eff1a59c MW |
70 | { |
71 | struct p54_common *priv = dev->priv; | |
72 | struct bootrec_exp_if *exp_if; | |
73 | struct bootrec *bootrec; | |
74 | u32 *data = (u32 *)fw->data; | |
75 | u32 *end_data = (u32 *)fw->data + (fw->size >> 2); | |
76 | u8 *fw_version = NULL; | |
77 | size_t len; | |
78 | int i; | |
79 | ||
80 | if (priv->rx_start) | |
4e416a6f | 81 | return 0; |
eff1a59c MW |
82 | |
83 | while (data < end_data && *data) | |
84 | data++; | |
85 | ||
86 | while (data < end_data && !*data) | |
87 | data++; | |
88 | ||
89 | bootrec = (struct bootrec *) data; | |
90 | ||
91 | while (bootrec->data <= end_data && | |
92 | (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) { | |
93 | u32 code = le32_to_cpu(bootrec->code); | |
94 | switch (code) { | |
95 | case BR_CODE_COMPONENT_ID: | |
dc73c623 | 96 | switch (be32_to_cpu(*(__be32 *)bootrec->data)) { |
eff1a59c MW |
97 | case FW_FMAC: |
98 | printk(KERN_INFO "p54: FreeMAC firmware\n"); | |
99 | break; | |
100 | case FW_LM20: | |
101 | printk(KERN_INFO "p54: LM20 firmware\n"); | |
102 | break; | |
103 | case FW_LM86: | |
104 | printk(KERN_INFO "p54: LM86 firmware\n"); | |
105 | break; | |
106 | case FW_LM87: | |
107 | printk(KERN_INFO "p54: LM87 firmware - not supported yet!\n"); | |
108 | break; | |
109 | default: | |
110 | printk(KERN_INFO "p54: unknown firmware\n"); | |
111 | break; | |
112 | } | |
113 | break; | |
114 | case BR_CODE_COMPONENT_VERSION: | |
115 | /* 24 bytes should be enough for all firmwares */ | |
116 | if (strnlen((unsigned char*)bootrec->data, 24) < 24) | |
117 | fw_version = (unsigned char*)bootrec->data; | |
118 | break; | |
4e416a6f CL |
119 | case BR_CODE_DESCR: { |
120 | struct bootrec_desc *desc = | |
121 | (struct bootrec_desc *)bootrec->data; | |
122 | priv->rx_start = le32_to_cpu(desc->rx_start); | |
eff1a59c | 123 | /* FIXME add sanity checking */ |
4e416a6f CL |
124 | priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500; |
125 | priv->headroom = desc->headroom; | |
126 | priv->tailroom = desc->tailroom; | |
127 | if (bootrec->len == 11) | |
128 | priv->rx_mtu = (size_t) le16_to_cpu( | |
129 | (__le16)bootrec->data[10]); | |
130 | else | |
131 | priv->rx_mtu = (size_t) | |
132 | 0x620 - priv->tx_hdr_len; | |
eff1a59c | 133 | break; |
4e416a6f | 134 | } |
eff1a59c MW |
135 | case BR_CODE_EXPOSED_IF: |
136 | exp_if = (struct bootrec_exp_if *) bootrec->data; | |
137 | for (i = 0; i < (len * sizeof(*exp_if) / 4); i++) | |
dc73c623 | 138 | if (exp_if[i].if_id == cpu_to_le16(0x1a)) |
eff1a59c MW |
139 | priv->fw_var = le16_to_cpu(exp_if[i].variant); |
140 | break; | |
141 | case BR_CODE_DEPENDENT_IF: | |
142 | break; | |
143 | case BR_CODE_END_OF_BRA: | |
144 | case LEGACY_BR_CODE_END_OF_BRA: | |
145 | end_data = NULL; | |
146 | break; | |
147 | default: | |
148 | break; | |
149 | } | |
150 | bootrec = (struct bootrec *)&bootrec->data[len]; | |
151 | } | |
152 | ||
153 | if (fw_version) | |
154 | printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n", | |
155 | fw_version, priv->fw_var >> 8, priv->fw_var & 0xff); | |
156 | ||
157 | if (priv->fw_var >= 0x300) { | |
158 | /* Firmware supports QoS, use it! */ | |
84df3ed3 C |
159 | priv->tx_stats[4].limit = 3; |
160 | priv->tx_stats[5].limit = 4; | |
161 | priv->tx_stats[6].limit = 3; | |
162 | priv->tx_stats[7].limit = 1; | |
eff1a59c MW |
163 | dev->queues = 4; |
164 | } | |
4e416a6f CL |
165 | |
166 | return 0; | |
eff1a59c MW |
167 | } |
168 | EXPORT_SYMBOL_GPL(p54_parse_firmware); | |
169 | ||
154e3af1 CL |
170 | static int p54_convert_rev0(struct ieee80211_hw *dev, |
171 | struct pda_pa_curve_data *curve_data) | |
eff1a59c MW |
172 | { |
173 | struct p54_common *priv = dev->priv; | |
154e3af1 CL |
174 | struct p54_pa_curve_data_sample *dst; |
175 | struct pda_pa_curve_data_sample_rev0 *src; | |
eff1a59c | 176 | size_t cd_len = sizeof(*curve_data) + |
154e3af1 | 177 | (curve_data->points_per_channel*sizeof(*dst) + 2) * |
eff1a59c MW |
178 | curve_data->channels; |
179 | unsigned int i, j; | |
180 | void *source, *target; | |
181 | ||
182 | priv->curve_data = kmalloc(cd_len, GFP_KERNEL); | |
183 | if (!priv->curve_data) | |
184 | return -ENOMEM; | |
185 | ||
186 | memcpy(priv->curve_data, curve_data, sizeof(*curve_data)); | |
187 | source = curve_data->data; | |
188 | target = priv->curve_data->data; | |
189 | for (i = 0; i < curve_data->channels; i++) { | |
190 | __le16 *freq = source; | |
191 | source += sizeof(__le16); | |
192 | *((__le16 *)target) = *freq; | |
193 | target += sizeof(__le16); | |
194 | for (j = 0; j < curve_data->points_per_channel; j++) { | |
154e3af1 CL |
195 | dst = target; |
196 | src = source; | |
eff1a59c | 197 | |
154e3af1 CL |
198 | dst->rf_power = src->rf_power; |
199 | dst->pa_detector = src->pa_detector; | |
200 | dst->data_64qam = src->pcv; | |
eff1a59c MW |
201 | /* "invent" the points for the other modulations */ |
202 | #define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y) | |
154e3af1 CL |
203 | dst->data_16qam = SUB(src->pcv, 12); |
204 | dst->data_qpsk = SUB(dst->data_16qam, 12); | |
205 | dst->data_bpsk = SUB(dst->data_qpsk, 12); | |
206 | dst->data_barker = SUB(dst->data_bpsk, 14); | |
eff1a59c | 207 | #undef SUB |
154e3af1 CL |
208 | target += sizeof(*dst); |
209 | source += sizeof(*src); | |
eff1a59c MW |
210 | } |
211 | } | |
212 | ||
213 | return 0; | |
214 | } | |
215 | ||
154e3af1 CL |
216 | static int p54_convert_rev1(struct ieee80211_hw *dev, |
217 | struct pda_pa_curve_data *curve_data) | |
218 | { | |
219 | struct p54_common *priv = dev->priv; | |
220 | struct p54_pa_curve_data_sample *dst; | |
221 | struct pda_pa_curve_data_sample_rev1 *src; | |
222 | size_t cd_len = sizeof(*curve_data) + | |
223 | (curve_data->points_per_channel*sizeof(*dst) + 2) * | |
224 | curve_data->channels; | |
225 | unsigned int i, j; | |
226 | void *source, *target; | |
227 | ||
228 | priv->curve_data = kmalloc(cd_len, GFP_KERNEL); | |
229 | if (!priv->curve_data) | |
230 | return -ENOMEM; | |
231 | ||
232 | memcpy(priv->curve_data, curve_data, sizeof(*curve_data)); | |
233 | source = curve_data->data; | |
234 | target = priv->curve_data->data; | |
235 | for (i = 0; i < curve_data->channels; i++) { | |
236 | __le16 *freq = source; | |
237 | source += sizeof(__le16); | |
238 | *((__le16 *)target) = *freq; | |
239 | target += sizeof(__le16); | |
240 | for (j = 0; j < curve_data->points_per_channel; j++) { | |
241 | memcpy(target, source, sizeof(*src)); | |
242 | ||
243 | target += sizeof(*dst); | |
244 | source += sizeof(*src); | |
245 | } | |
246 | source++; | |
247 | } | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
eff1a59c MW |
252 | int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len) |
253 | { | |
254 | struct p54_common *priv = dev->priv; | |
255 | struct eeprom_pda_wrap *wrap = NULL; | |
256 | struct pda_entry *entry; | |
eff1a59c MW |
257 | unsigned int data_len, entry_len; |
258 | void *tmp; | |
259 | int err; | |
c2f2d3a0 | 260 | u8 *end = (u8 *)eeprom + len; |
eff1a59c MW |
261 | |
262 | wrap = (struct eeprom_pda_wrap *) eeprom; | |
8c28293f | 263 | entry = (void *)wrap->data + le16_to_cpu(wrap->len); |
c2f2d3a0 JB |
264 | |
265 | /* verify that at least the entry length/code fits */ | |
266 | while ((u8 *)entry <= end - sizeof(*entry)) { | |
eff1a59c MW |
267 | entry_len = le16_to_cpu(entry->len); |
268 | data_len = ((entry_len - 1) << 1); | |
c2f2d3a0 JB |
269 | |
270 | /* abort if entry exceeds whole structure */ | |
271 | if ((u8 *)entry + sizeof(*entry) + data_len > end) | |
272 | break; | |
273 | ||
eff1a59c MW |
274 | switch (le16_to_cpu(entry->code)) { |
275 | case PDR_MAC_ADDRESS: | |
276 | SET_IEEE80211_PERM_ADDR(dev, entry->data); | |
277 | break; | |
278 | case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS: | |
279 | if (data_len < 2) { | |
280 | err = -EINVAL; | |
281 | goto err; | |
282 | } | |
283 | ||
284 | if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) { | |
285 | err = -EINVAL; | |
286 | goto err; | |
287 | } | |
288 | ||
289 | priv->output_limit = kmalloc(entry->data[1] * | |
290 | sizeof(*priv->output_limit), GFP_KERNEL); | |
291 | ||
292 | if (!priv->output_limit) { | |
293 | err = -ENOMEM; | |
294 | goto err; | |
295 | } | |
296 | ||
297 | memcpy(priv->output_limit, &entry->data[2], | |
298 | entry->data[1]*sizeof(*priv->output_limit)); | |
299 | priv->output_limit_len = entry->data[1]; | |
300 | break; | |
154e3af1 CL |
301 | case PDR_PRISM_PA_CAL_CURVE_DATA: { |
302 | struct pda_pa_curve_data *curve_data = | |
303 | (struct pda_pa_curve_data *)entry->data; | |
304 | if (data_len < sizeof(*curve_data)) { | |
eff1a59c MW |
305 | err = -EINVAL; |
306 | goto err; | |
307 | } | |
308 | ||
154e3af1 CL |
309 | switch (curve_data->cal_method_rev) { |
310 | case 0: | |
311 | err = p54_convert_rev0(dev, curve_data); | |
312 | break; | |
313 | case 1: | |
314 | err = p54_convert_rev1(dev, curve_data); | |
315 | break; | |
316 | default: | |
317 | printk(KERN_ERR "p54: unknown curve data " | |
318 | "revision %d\n", | |
319 | curve_data->cal_method_rev); | |
320 | err = -ENODEV; | |
321 | break; | |
eff1a59c | 322 | } |
154e3af1 CL |
323 | if (err) |
324 | goto err; | |
eff1a59c | 325 | |
154e3af1 | 326 | } |
eff1a59c MW |
327 | case PDR_PRISM_ZIF_TX_IQ_CALIBRATION: |
328 | priv->iq_autocal = kmalloc(data_len, GFP_KERNEL); | |
329 | if (!priv->iq_autocal) { | |
330 | err = -ENOMEM; | |
331 | goto err; | |
332 | } | |
333 | ||
334 | memcpy(priv->iq_autocal, entry->data, data_len); | |
335 | priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry); | |
336 | break; | |
337 | case PDR_INTERFACE_LIST: | |
338 | tmp = entry->data; | |
339 | while ((u8 *)tmp < entry->data + data_len) { | |
340 | struct bootrec_exp_if *exp_if = tmp; | |
341 | if (le16_to_cpu(exp_if->if_id) == 0xF) | |
342 | priv->rxhw = exp_if->variant & cpu_to_le16(0x07); | |
343 | tmp += sizeof(struct bootrec_exp_if); | |
344 | } | |
345 | break; | |
346 | case PDR_HARDWARE_PLATFORM_COMPONENT_ID: | |
347 | priv->version = *(u8 *)(entry->data + 1); | |
348 | break; | |
349 | case PDR_END: | |
c2f2d3a0 JB |
350 | /* make it overrun */ |
351 | entry_len = len; | |
eff1a59c | 352 | break; |
58e30739 FF |
353 | default: |
354 | printk(KERN_INFO "p54: unknown eeprom code : 0x%x\n", | |
355 | le16_to_cpu(entry->code)); | |
356 | break; | |
eff1a59c MW |
357 | } |
358 | ||
359 | entry = (void *)entry + (entry_len + 1)*2; | |
eff1a59c MW |
360 | } |
361 | ||
362 | if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) { | |
363 | printk(KERN_ERR "p54: not all required entries found in eeprom!\n"); | |
364 | err = -EINVAL; | |
365 | goto err; | |
366 | } | |
367 | ||
368 | return 0; | |
369 | ||
370 | err: | |
371 | if (priv->iq_autocal) { | |
372 | kfree(priv->iq_autocal); | |
373 | priv->iq_autocal = NULL; | |
374 | } | |
375 | ||
376 | if (priv->output_limit) { | |
377 | kfree(priv->output_limit); | |
378 | priv->output_limit = NULL; | |
379 | } | |
380 | ||
381 | if (priv->curve_data) { | |
382 | kfree(priv->curve_data); | |
383 | priv->curve_data = NULL; | |
384 | } | |
385 | ||
386 | printk(KERN_ERR "p54: eeprom parse failed!\n"); | |
387 | return err; | |
388 | } | |
389 | EXPORT_SYMBOL_GPL(p54_parse_eeprom); | |
390 | ||
391 | void p54_fill_eeprom_readback(struct p54_control_hdr *hdr) | |
392 | { | |
393 | struct p54_eeprom_lm86 *eeprom_hdr; | |
394 | ||
395 | hdr->magic1 = cpu_to_le16(0x8000); | |
396 | hdr->len = cpu_to_le16(sizeof(*eeprom_hdr) + 0x2000); | |
397 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK); | |
398 | hdr->retry1 = hdr->retry2 = 0; | |
399 | eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data; | |
400 | eeprom_hdr->offset = 0x0; | |
401 | eeprom_hdr->len = cpu_to_le16(0x2000); | |
402 | } | |
403 | EXPORT_SYMBOL_GPL(p54_fill_eeprom_readback); | |
404 | ||
405 | static void p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb) | |
406 | { | |
407 | struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data; | |
408 | struct ieee80211_rx_status rx_status = {0}; | |
409 | u16 freq = le16_to_cpu(hdr->freq); | |
410 | ||
566bfe5a | 411 | rx_status.signal = hdr->rssi; |
8318d78a | 412 | /* XX correct? */ |
18d72605 | 413 | rx_status.qual = (100 * hdr->rssi) / 127; |
8318d78a | 414 | rx_status.rate_idx = hdr->rate & 0xf; |
eff1a59c | 415 | rx_status.freq = freq; |
8318d78a | 416 | rx_status.band = IEEE80211_BAND_2GHZ; |
eff1a59c MW |
417 | rx_status.antenna = hdr->antenna; |
418 | rx_status.mactime = le64_to_cpu(hdr->timestamp); | |
03bffc13 | 419 | rx_status.flag |= RX_FLAG_TSFT; |
eff1a59c MW |
420 | |
421 | skb_pull(skb, sizeof(*hdr)); | |
422 | skb_trim(skb, le16_to_cpu(hdr->len)); | |
423 | ||
424 | ieee80211_rx_irqsafe(dev, skb, &rx_status); | |
425 | } | |
426 | ||
427 | static void inline p54_wake_free_queues(struct ieee80211_hw *dev) | |
428 | { | |
429 | struct p54_common *priv = dev->priv; | |
430 | int i; | |
431 | ||
eff1a59c | 432 | for (i = 0; i < dev->queues; i++) |
84df3ed3 | 433 | if (priv->tx_stats[i + 4].len < priv->tx_stats[i + 4].limit) |
eff1a59c MW |
434 | ieee80211_wake_queue(dev, i); |
435 | } | |
436 | ||
437 | static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb) | |
438 | { | |
439 | struct p54_common *priv = dev->priv; | |
440 | struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data; | |
441 | struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data; | |
442 | struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next; | |
4e416a6f | 443 | u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom; |
eff1a59c MW |
444 | struct memrecord *range = NULL; |
445 | u32 freed = 0; | |
446 | u32 last_addr = priv->rx_start; | |
031d10ee | 447 | unsigned long flags; |
eff1a59c | 448 | |
031d10ee | 449 | spin_lock_irqsave(&priv->tx_queue.lock, flags); |
eff1a59c | 450 | while (entry != (struct sk_buff *)&priv->tx_queue) { |
552fe53f JB |
451 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry); |
452 | range = (void *)info->driver_data; | |
eff1a59c | 453 | if (range->start_addr == addr) { |
eff1a59c MW |
454 | struct p54_control_hdr *entry_hdr; |
455 | struct p54_tx_control_allocdata *entry_data; | |
456 | int pad = 0; | |
457 | ||
552fe53f JB |
458 | if (entry->next != (struct sk_buff *)&priv->tx_queue) { |
459 | struct ieee80211_tx_info *ni; | |
460 | struct memrecord *mr; | |
461 | ||
462 | ni = IEEE80211_SKB_CB(entry->next); | |
463 | mr = (struct memrecord *)ni->driver_data; | |
464 | freed = mr->start_addr - last_addr; | |
465 | } else | |
eff1a59c MW |
466 | freed = priv->rx_end - last_addr; |
467 | ||
468 | last_addr = range->end_addr; | |
469 | __skb_unlink(entry, &priv->tx_queue); | |
031d10ee C |
470 | spin_unlock_irqrestore(&priv->tx_queue.lock, flags); |
471 | ||
e039fa4a | 472 | memset(&info->status, 0, sizeof(info->status)); |
eff1a59c MW |
473 | entry_hdr = (struct p54_control_hdr *) entry->data; |
474 | entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data; | |
475 | if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0) | |
476 | pad = entry_data->align[0]; | |
477 | ||
84df3ed3 | 478 | priv->tx_stats[entry_data->hw_queue].len--; |
e039fa4a | 479 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
eff1a59c | 480 | if (!(payload->status & 0x01)) |
e039fa4a | 481 | info->flags |= IEEE80211_TX_STAT_ACK; |
eff1a59c | 482 | else |
e039fa4a | 483 | info->status.excessive_retries = 1; |
eff1a59c | 484 | } |
e039fa4a JB |
485 | info->status.retry_count = payload->retries - 1; |
486 | info->status.ack_signal = le16_to_cpu(payload->ack_rssi); | |
eff1a59c | 487 | skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data)); |
e039fa4a | 488 | ieee80211_tx_status_irqsafe(dev, entry); |
031d10ee | 489 | goto out; |
eff1a59c MW |
490 | } else |
491 | last_addr = range->end_addr; | |
492 | entry = entry->next; | |
493 | } | |
031d10ee | 494 | spin_unlock_irqrestore(&priv->tx_queue.lock, flags); |
eff1a59c | 495 | |
031d10ee | 496 | out: |
eff1a59c MW |
497 | if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 + |
498 | sizeof(struct p54_control_hdr)) | |
499 | p54_wake_free_queues(dev); | |
500 | } | |
501 | ||
502 | static void p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb) | |
503 | { | |
504 | struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data; | |
505 | ||
506 | switch (le16_to_cpu(hdr->type)) { | |
507 | case P54_CONTROL_TYPE_TXDONE: | |
508 | p54_rx_frame_sent(dev, skb); | |
509 | break; | |
510 | case P54_CONTROL_TYPE_BBP: | |
511 | break; | |
512 | default: | |
513 | printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n", | |
514 | wiphy_name(dev->wiphy), le16_to_cpu(hdr->type)); | |
515 | break; | |
516 | } | |
517 | } | |
518 | ||
519 | /* returns zero if skb can be reused */ | |
520 | int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb) | |
521 | { | |
522 | u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8; | |
523 | switch (type) { | |
524 | case 0x00: | |
525 | case 0x01: | |
526 | p54_rx_data(dev, skb); | |
527 | return -1; | |
528 | case 0x4d: | |
529 | /* TODO: do something better... but then again, I've never seen this happen */ | |
530 | printk(KERN_ERR "%s: Received fault. Probably need to restart hardware now..\n", | |
531 | wiphy_name(dev->wiphy)); | |
532 | break; | |
533 | case 0x80: | |
534 | p54_rx_control(dev, skb); | |
535 | break; | |
536 | default: | |
537 | printk(KERN_ERR "%s: unknown frame RXed (0x%02x)\n", | |
538 | wiphy_name(dev->wiphy), type); | |
539 | break; | |
540 | } | |
541 | return 0; | |
542 | } | |
543 | EXPORT_SYMBOL_GPL(p54_rx); | |
544 | ||
545 | /* | |
546 | * So, the firmware is somewhat stupid and doesn't know what places in its | |
547 | * memory incoming data should go to. By poking around in the firmware, we | |
548 | * can find some unused memory to upload our packets to. However, data that we | |
549 | * want the card to TX needs to stay intact until the card has told us that | |
550 | * it is done with it. This function finds empty places we can upload to and | |
551 | * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees | |
552 | * allocated areas. | |
553 | */ | |
554 | static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb, | |
e039fa4a | 555 | struct p54_control_hdr *data, u32 len) |
eff1a59c MW |
556 | { |
557 | struct p54_common *priv = dev->priv; | |
558 | struct sk_buff *entry = priv->tx_queue.next; | |
559 | struct sk_buff *target_skb = NULL; | |
eff1a59c MW |
560 | u32 last_addr = priv->rx_start; |
561 | u32 largest_hole = 0; | |
562 | u32 target_addr = priv->rx_start; | |
563 | unsigned long flags; | |
564 | unsigned int left; | |
4e416a6f | 565 | len = (len + priv->headroom + priv->tailroom + 3) & ~0x3; |
eff1a59c MW |
566 | |
567 | spin_lock_irqsave(&priv->tx_queue.lock, flags); | |
568 | left = skb_queue_len(&priv->tx_queue); | |
569 | while (left--) { | |
570 | u32 hole_size; | |
e039fa4a JB |
571 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry); |
572 | struct memrecord *range = (void *)info->driver_data; | |
eff1a59c MW |
573 | hole_size = range->start_addr - last_addr; |
574 | if (!target_skb && hole_size >= len) { | |
575 | target_skb = entry->prev; | |
576 | hole_size -= len; | |
577 | target_addr = last_addr; | |
578 | } | |
579 | largest_hole = max(largest_hole, hole_size); | |
580 | last_addr = range->end_addr; | |
581 | entry = entry->next; | |
582 | } | |
583 | if (!target_skb && priv->rx_end - last_addr >= len) { | |
584 | target_skb = priv->tx_queue.prev; | |
585 | largest_hole = max(largest_hole, priv->rx_end - last_addr - len); | |
586 | if (!skb_queue_empty(&priv->tx_queue)) { | |
e039fa4a JB |
587 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(target_skb); |
588 | struct memrecord *range = (void *)info->driver_data; | |
eff1a59c MW |
589 | target_addr = range->end_addr; |
590 | } | |
591 | } else | |
592 | largest_hole = max(largest_hole, priv->rx_end - last_addr); | |
593 | ||
594 | if (skb) { | |
e039fa4a JB |
595 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
596 | struct memrecord *range = (void *)info->driver_data; | |
eff1a59c MW |
597 | range->start_addr = target_addr; |
598 | range->end_addr = target_addr + len; | |
eff1a59c | 599 | __skb_queue_after(&priv->tx_queue, target_skb, skb); |
4e416a6f CL |
600 | if (largest_hole < priv->rx_mtu + priv->headroom + |
601 | priv->tailroom + | |
eff1a59c MW |
602 | sizeof(struct p54_control_hdr)) |
603 | ieee80211_stop_queues(dev); | |
604 | } | |
605 | spin_unlock_irqrestore(&priv->tx_queue.lock, flags); | |
606 | ||
4e416a6f | 607 | data->req_id = cpu_to_le32(target_addr + priv->headroom); |
eff1a59c MW |
608 | } |
609 | ||
e039fa4a | 610 | static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb) |
eff1a59c | 611 | { |
e039fa4a | 612 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
57ffc589 | 613 | struct ieee80211_tx_queue_stats *current_queue; |
eff1a59c MW |
614 | struct p54_common *priv = dev->priv; |
615 | struct p54_control_hdr *hdr; | |
eda0c003 | 616 | struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data; |
eff1a59c | 617 | struct p54_tx_control_allocdata *txhdr; |
eff1a59c MW |
618 | size_t padding, len; |
619 | u8 rate; | |
aaa15535 | 620 | u8 cts_rate = 0x20; |
eff1a59c | 621 | |
84df3ed3 | 622 | current_queue = &priv->tx_stats[skb_get_queue_mapping(skb) + 4]; |
eff1a59c MW |
623 | if (unlikely(current_queue->len > current_queue->limit)) |
624 | return NETDEV_TX_BUSY; | |
625 | current_queue->len++; | |
626 | current_queue->count++; | |
627 | if (current_queue->len == current_queue->limit) | |
e2530083 | 628 | ieee80211_stop_queue(dev, skb_get_queue_mapping(skb)); |
eff1a59c MW |
629 | |
630 | padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3; | |
631 | len = skb->len; | |
632 | ||
eff1a59c MW |
633 | txhdr = (struct p54_tx_control_allocdata *) |
634 | skb_push(skb, sizeof(*txhdr) + padding); | |
635 | hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr)); | |
636 | ||
637 | if (padding) | |
638 | hdr->magic1 = cpu_to_le16(0x4010); | |
639 | else | |
640 | hdr->magic1 = cpu_to_le16(0x0010); | |
641 | hdr->len = cpu_to_le16(len); | |
e039fa4a JB |
642 | hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1); |
643 | hdr->retry1 = hdr->retry2 = info->control.retry_limit; | |
eff1a59c | 644 | |
eff1a59c | 645 | /* TODO: add support for alternate retry TX rates */ |
e039fa4a | 646 | rate = ieee80211_get_tx_rate(dev, info)->hw_value; |
aaa15535 | 647 | if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) { |
8318d78a | 648 | rate |= 0x10; |
aaa15535 CL |
649 | cts_rate |= 0x10; |
650 | } | |
651 | if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) { | |
eff1a59c | 652 | rate |= 0x40; |
aaa15535 CL |
653 | cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value; |
654 | } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) { | |
eff1a59c | 655 | rate |= 0x20; |
aaa15535 CL |
656 | cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value; |
657 | } | |
eff1a59c | 658 | memset(txhdr->rateset, rate, 8); |
aaa15535 CL |
659 | txhdr->key_type = 0; |
660 | txhdr->key_len = 0; | |
661 | txhdr->hw_queue = skb_get_queue_mapping(skb) + 4; | |
662 | txhdr->tx_antenna = (info->antenna_sel_tx == 0) ? | |
e039fa4a | 663 | 2 : info->antenna_sel_tx - 1; |
eff1a59c | 664 | txhdr->output_power = 0x7f; // HW Maximum |
aaa15535 CL |
665 | txhdr->cts_rate = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? |
666 | 0 : cts_rate; | |
eff1a59c MW |
667 | if (padding) |
668 | txhdr->align[0] = padding; | |
669 | ||
eda0c003 LF |
670 | /* FIXME: The sequence that follows is needed for this driver to |
671 | * work with mac80211 since "mac80211: fix TX sequence numbers". | |
672 | * As with the temporary code in rt2x00, changes will be needed | |
673 | * to get proper sequence numbers on beacons. In addition, this | |
674 | * patch places the sequence number in the hardware state, which | |
675 | * limits us to a single virtual state. | |
676 | */ | |
677 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
678 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
679 | priv->seqno += 0x10; | |
680 | ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
681 | ieee80211hdr->seq_ctrl |= cpu_to_le16(priv->seqno); | |
682 | } | |
e039fa4a JB |
683 | /* modifies skb->cb and with it info, so must be last! */ |
684 | p54_assign_address(dev, skb, hdr, skb->len); | |
685 | ||
eff1a59c MW |
686 | priv->tx(dev, hdr, skb->len, 0); |
687 | return 0; | |
688 | } | |
689 | ||
690 | static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type, | |
691 | const u8 *dst, const u8 *src, u8 antenna, | |
692 | u32 magic3, u32 magic8, u32 magic9) | |
693 | { | |
694 | struct p54_common *priv = dev->priv; | |
695 | struct p54_control_hdr *hdr; | |
696 | struct p54_tx_control_filter *filter; | |
697 | ||
698 | hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) + | |
ba8007ce | 699 | priv->tx_hdr_len, GFP_ATOMIC); |
eff1a59c MW |
700 | if (!hdr) |
701 | return -ENOMEM; | |
702 | ||
703 | hdr = (void *)hdr + priv->tx_hdr_len; | |
704 | ||
705 | filter = (struct p54_tx_control_filter *) hdr->data; | |
706 | hdr->magic1 = cpu_to_le16(0x8001); | |
707 | hdr->len = cpu_to_le16(sizeof(*filter)); | |
e039fa4a | 708 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter)); |
eff1a59c MW |
709 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET); |
710 | ||
711 | filter->filter_type = cpu_to_le16(filter_type); | |
712 | memcpy(filter->dst, dst, ETH_ALEN); | |
713 | if (!src) | |
714 | memset(filter->src, ~0, ETH_ALEN); | |
715 | else | |
716 | memcpy(filter->src, src, ETH_ALEN); | |
717 | filter->antenna = antenna; | |
718 | filter->magic3 = cpu_to_le32(magic3); | |
719 | filter->rx_addr = cpu_to_le32(priv->rx_end); | |
4e416a6f | 720 | filter->max_rx = cpu_to_le16(priv->rx_mtu); |
eff1a59c MW |
721 | filter->rxhw = priv->rxhw; |
722 | filter->magic8 = cpu_to_le16(magic8); | |
723 | filter->magic9 = cpu_to_le16(magic9); | |
724 | ||
725 | priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*filter), 1); | |
726 | return 0; | |
727 | } | |
728 | ||
729 | static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq) | |
730 | { | |
731 | struct p54_common *priv = dev->priv; | |
732 | struct p54_control_hdr *hdr; | |
733 | struct p54_tx_control_channel *chan; | |
734 | unsigned int i; | |
eff1a59c MW |
735 | void *entry; |
736 | ||
154e3af1 | 737 | hdr = kzalloc(sizeof(*hdr) + sizeof(*chan) + |
eff1a59c MW |
738 | priv->tx_hdr_len, GFP_KERNEL); |
739 | if (!hdr) | |
740 | return -ENOMEM; | |
741 | ||
742 | hdr = (void *)hdr + priv->tx_hdr_len; | |
743 | ||
744 | chan = (struct p54_tx_control_channel *) hdr->data; | |
745 | ||
746 | hdr->magic1 = cpu_to_le16(0x8001); | |
747 | hdr->len = cpu_to_le16(sizeof(*chan)); | |
748 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE); | |
154e3af1 | 749 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*chan)); |
eff1a59c | 750 | |
154e3af1 CL |
751 | chan->flags = cpu_to_le16(0x1); |
752 | chan->dwell = cpu_to_le16(0x0); | |
eff1a59c MW |
753 | |
754 | for (i = 0; i < priv->iq_autocal_len; i++) { | |
755 | if (priv->iq_autocal[i].freq != freq) | |
756 | continue; | |
757 | ||
758 | memcpy(&chan->iq_autocal, &priv->iq_autocal[i], | |
759 | sizeof(*priv->iq_autocal)); | |
760 | break; | |
761 | } | |
762 | if (i == priv->iq_autocal_len) | |
763 | goto err; | |
764 | ||
765 | for (i = 0; i < priv->output_limit_len; i++) { | |
766 | if (priv->output_limit[i].freq != freq) | |
767 | continue; | |
768 | ||
769 | chan->val_barker = 0x38; | |
154e3af1 CL |
770 | chan->val_bpsk = chan->dup_bpsk = |
771 | priv->output_limit[i].val_bpsk; | |
772 | chan->val_qpsk = chan->dup_qpsk = | |
773 | priv->output_limit[i].val_qpsk; | |
774 | chan->val_16qam = chan->dup_16qam = | |
775 | priv->output_limit[i].val_16qam; | |
776 | chan->val_64qam = chan->dup_64qam = | |
777 | priv->output_limit[i].val_64qam; | |
eff1a59c MW |
778 | break; |
779 | } | |
780 | if (i == priv->output_limit_len) | |
781 | goto err; | |
782 | ||
eff1a59c MW |
783 | entry = priv->curve_data->data; |
784 | for (i = 0; i < priv->curve_data->channels; i++) { | |
785 | if (*((__le16 *)entry) != freq) { | |
786 | entry += sizeof(__le16); | |
154e3af1 CL |
787 | entry += sizeof(struct p54_pa_curve_data_sample) * |
788 | priv->curve_data->points_per_channel; | |
eff1a59c MW |
789 | continue; |
790 | } | |
791 | ||
792 | entry += sizeof(__le16); | |
154e3af1 CL |
793 | chan->pa_points_per_curve = |
794 | min(priv->curve_data->points_per_channel, (u8) 8); | |
795 | ||
eff1a59c MW |
796 | memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) * |
797 | chan->pa_points_per_curve); | |
798 | break; | |
799 | } | |
800 | ||
154e3af1 CL |
801 | chan->rssical_mul = cpu_to_le16(130); |
802 | chan->rssical_add = cpu_to_le16(0xfe70); /* -400 */ | |
eff1a59c | 803 | |
154e3af1 | 804 | priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*chan), 1); |
eff1a59c MW |
805 | return 0; |
806 | ||
807 | err: | |
808 | printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy)); | |
809 | kfree(hdr); | |
810 | return -EINVAL; | |
811 | } | |
812 | ||
813 | static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act) | |
814 | { | |
815 | struct p54_common *priv = dev->priv; | |
816 | struct p54_control_hdr *hdr; | |
817 | struct p54_tx_control_led *led; | |
818 | ||
819 | hdr = kzalloc(sizeof(*hdr) + sizeof(*led) + | |
820 | priv->tx_hdr_len, GFP_KERNEL); | |
821 | if (!hdr) | |
822 | return -ENOMEM; | |
823 | ||
824 | hdr = (void *)hdr + priv->tx_hdr_len; | |
825 | hdr->magic1 = cpu_to_le16(0x8001); | |
826 | hdr->len = cpu_to_le16(sizeof(*led)); | |
827 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED); | |
e039fa4a | 828 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led)); |
eff1a59c MW |
829 | |
830 | led = (struct p54_tx_control_led *) hdr->data; | |
831 | led->mode = cpu_to_le16(mode); | |
832 | led->led_permanent = cpu_to_le16(link); | |
833 | led->led_temporary = cpu_to_le16(act); | |
834 | led->duration = cpu_to_le16(1000); | |
835 | ||
836 | priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1); | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
3330d7be | 841 | #define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \ |
eff1a59c MW |
842 | do { \ |
843 | queue.aifs = cpu_to_le16(ai_fs); \ | |
844 | queue.cwmin = cpu_to_le16(cw_min); \ | |
845 | queue.cwmax = cpu_to_le16(cw_max); \ | |
3330d7be | 846 | queue.txop = cpu_to_le16(_txop); \ |
eff1a59c MW |
847 | } while(0) |
848 | ||
849 | static void p54_init_vdcf(struct ieee80211_hw *dev) | |
850 | { | |
851 | struct p54_common *priv = dev->priv; | |
852 | struct p54_control_hdr *hdr; | |
853 | struct p54_tx_control_vdcf *vdcf; | |
854 | ||
855 | /* all USB V1 adapters need a extra headroom */ | |
856 | hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len; | |
857 | hdr->magic1 = cpu_to_le16(0x8001); | |
858 | hdr->len = cpu_to_le16(sizeof(*vdcf)); | |
859 | hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT); | |
860 | hdr->req_id = cpu_to_le32(priv->rx_start); | |
861 | ||
862 | vdcf = (struct p54_tx_control_vdcf *) hdr->data; | |
863 | ||
3330d7be JB |
864 | P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 47); |
865 | P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 94); | |
5200e8cd | 866 | P54_SET_QUEUE(vdcf->queue[2], 0x0003, 0x000f, 0x03ff, 0); |
3330d7be | 867 | P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0); |
eff1a59c MW |
868 | } |
869 | ||
870 | static void p54_set_vdcf(struct ieee80211_hw *dev) | |
871 | { | |
872 | struct p54_common *priv = dev->priv; | |
873 | struct p54_control_hdr *hdr; | |
874 | struct p54_tx_control_vdcf *vdcf; | |
875 | ||
876 | hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len; | |
877 | ||
e039fa4a | 878 | p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf)); |
eff1a59c MW |
879 | |
880 | vdcf = (struct p54_tx_control_vdcf *) hdr->data; | |
881 | ||
882 | if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) { | |
883 | vdcf->slottime = 9; | |
5423b2ed CL |
884 | vdcf->magic1 = 0x10; |
885 | vdcf->magic2 = 0x00; | |
eff1a59c MW |
886 | } else { |
887 | vdcf->slottime = 20; | |
888 | vdcf->magic1 = 0x0a; | |
889 | vdcf->magic2 = 0x06; | |
890 | } | |
891 | ||
892 | /* (see prism54/isl_oid.h for further details) */ | |
893 | vdcf->frameburst = cpu_to_le16(0); | |
894 | ||
895 | priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0); | |
896 | } | |
897 | ||
4150c572 JB |
898 | static int p54_start(struct ieee80211_hw *dev) |
899 | { | |
900 | struct p54_common *priv = dev->priv; | |
901 | int err; | |
902 | ||
69bbc7dc CL |
903 | if (!priv->cached_vdcf) { |
904 | priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf)+ | |
905 | priv->tx_hdr_len + sizeof(struct p54_control_hdr), | |
906 | GFP_KERNEL); | |
907 | ||
908 | if (!priv->cached_vdcf) | |
909 | return -ENOMEM; | |
910 | } | |
911 | ||
4150c572 JB |
912 | err = priv->open(dev); |
913 | if (!err) | |
914 | priv->mode = IEEE80211_IF_TYPE_MNTR; | |
915 | ||
69bbc7dc CL |
916 | p54_init_vdcf(dev); |
917 | ||
4150c572 JB |
918 | return err; |
919 | } | |
920 | ||
921 | static void p54_stop(struct ieee80211_hw *dev) | |
922 | { | |
923 | struct p54_common *priv = dev->priv; | |
924 | struct sk_buff *skb; | |
e039fa4a | 925 | while ((skb = skb_dequeue(&priv->tx_queue))) |
4150c572 | 926 | kfree_skb(skb); |
4150c572 | 927 | priv->stop(dev); |
a2897552 | 928 | priv->mode = IEEE80211_IF_TYPE_INVALID; |
4150c572 JB |
929 | } |
930 | ||
eff1a59c MW |
931 | static int p54_add_interface(struct ieee80211_hw *dev, |
932 | struct ieee80211_if_init_conf *conf) | |
933 | { | |
934 | struct p54_common *priv = dev->priv; | |
eff1a59c | 935 | |
4150c572 JB |
936 | if (priv->mode != IEEE80211_IF_TYPE_MNTR) |
937 | return -EOPNOTSUPP; | |
eff1a59c MW |
938 | |
939 | switch (conf->type) { | |
940 | case IEEE80211_IF_TYPE_STA: | |
941 | priv->mode = conf->type; | |
942 | break; | |
943 | default: | |
944 | return -EOPNOTSUPP; | |
945 | } | |
946 | ||
4150c572 | 947 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); |
eff1a59c MW |
948 | |
949 | p54_set_filter(dev, 0, priv->mac_addr, NULL, 0, 1, 0, 0xF642); | |
950 | p54_set_filter(dev, 0, priv->mac_addr, NULL, 1, 0, 0, 0xF642); | |
eff1a59c MW |
951 | |
952 | switch (conf->type) { | |
953 | case IEEE80211_IF_TYPE_STA: | |
954 | p54_set_filter(dev, 1, priv->mac_addr, NULL, 0, 0x15F, 0x1F4, 0); | |
955 | break; | |
4150c572 JB |
956 | default: |
957 | BUG(); /* impossible */ | |
958 | break; | |
eff1a59c MW |
959 | } |
960 | ||
961 | p54_set_leds(dev, 1, 0, 0); | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | static void p54_remove_interface(struct ieee80211_hw *dev, | |
967 | struct ieee80211_if_init_conf *conf) | |
968 | { | |
969 | struct p54_common *priv = dev->priv; | |
4150c572 JB |
970 | priv->mode = IEEE80211_IF_TYPE_MNTR; |
971 | memset(priv->mac_addr, 0, ETH_ALEN); | |
972 | p54_set_filter(dev, 0, priv->mac_addr, NULL, 2, 0, 0, 0); | |
eff1a59c MW |
973 | } |
974 | ||
975 | static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) | |
976 | { | |
977 | int ret; | |
6041e2a0 | 978 | struct p54_common *priv = dev->priv; |
eff1a59c | 979 | |
6041e2a0 | 980 | mutex_lock(&priv->conf_mutex); |
8318d78a | 981 | ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq)); |
eff1a59c | 982 | p54_set_vdcf(dev); |
6041e2a0 | 983 | mutex_unlock(&priv->conf_mutex); |
eff1a59c MW |
984 | return ret; |
985 | } | |
986 | ||
32bfd35d JB |
987 | static int p54_config_interface(struct ieee80211_hw *dev, |
988 | struct ieee80211_vif *vif, | |
eff1a59c MW |
989 | struct ieee80211_if_conf *conf) |
990 | { | |
991 | struct p54_common *priv = dev->priv; | |
992 | ||
6041e2a0 | 993 | mutex_lock(&priv->conf_mutex); |
eff1a59c MW |
994 | p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642); |
995 | p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0); | |
996 | p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0); | |
4150c572 | 997 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); |
6041e2a0 | 998 | mutex_unlock(&priv->conf_mutex); |
eff1a59c MW |
999 | return 0; |
1000 | } | |
1001 | ||
4150c572 JB |
1002 | static void p54_configure_filter(struct ieee80211_hw *dev, |
1003 | unsigned int changed_flags, | |
1004 | unsigned int *total_flags, | |
1005 | int mc_count, struct dev_mc_list *mclist) | |
1006 | { | |
1007 | struct p54_common *priv = dev->priv; | |
1008 | ||
1009 | *total_flags &= FIF_BCN_PRBRESP_PROMISC; | |
1010 | ||
1011 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { | |
1012 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
1013 | p54_set_filter(dev, 0, priv->mac_addr, | |
1014 | NULL, 2, 0, 0, 0); | |
1015 | else | |
1016 | p54_set_filter(dev, 0, priv->mac_addr, | |
1017 | priv->bssid, 2, 0, 0, 0); | |
1018 | } | |
1019 | } | |
1020 | ||
e100bb64 | 1021 | static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue, |
eff1a59c MW |
1022 | const struct ieee80211_tx_queue_params *params) |
1023 | { | |
1024 | struct p54_common *priv = dev->priv; | |
1025 | struct p54_tx_control_vdcf *vdcf; | |
1026 | ||
1027 | vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *) | |
1028 | ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data); | |
1029 | ||
3df5ee60 | 1030 | if ((params) && !(queue > 4)) { |
eff1a59c | 1031 | P54_SET_QUEUE(vdcf->queue[queue], params->aifs, |
3330d7be | 1032 | params->cw_min, params->cw_max, params->txop); |
eff1a59c MW |
1033 | } else |
1034 | return -EINVAL; | |
1035 | ||
1036 | p54_set_vdcf(dev); | |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | ||
1041 | static int p54_get_stats(struct ieee80211_hw *dev, | |
1042 | struct ieee80211_low_level_stats *stats) | |
1043 | { | |
1044 | /* TODO */ | |
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | static int p54_get_tx_stats(struct ieee80211_hw *dev, | |
1049 | struct ieee80211_tx_queue_stats *stats) | |
1050 | { | |
1051 | struct p54_common *priv = dev->priv; | |
eff1a59c | 1052 | |
84df3ed3 | 1053 | memcpy(stats, &priv->tx_stats[4], sizeof(stats[0]) * dev->queues); |
eff1a59c MW |
1054 | |
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | static const struct ieee80211_ops p54_ops = { | |
1059 | .tx = p54_tx, | |
4150c572 JB |
1060 | .start = p54_start, |
1061 | .stop = p54_stop, | |
eff1a59c MW |
1062 | .add_interface = p54_add_interface, |
1063 | .remove_interface = p54_remove_interface, | |
1064 | .config = p54_config, | |
1065 | .config_interface = p54_config_interface, | |
4150c572 | 1066 | .configure_filter = p54_configure_filter, |
eff1a59c MW |
1067 | .conf_tx = p54_conf_tx, |
1068 | .get_stats = p54_get_stats, | |
1069 | .get_tx_stats = p54_get_tx_stats | |
1070 | }; | |
1071 | ||
1072 | struct ieee80211_hw *p54_init_common(size_t priv_data_len) | |
1073 | { | |
1074 | struct ieee80211_hw *dev; | |
1075 | struct p54_common *priv; | |
eff1a59c MW |
1076 | |
1077 | dev = ieee80211_alloc_hw(priv_data_len, &p54_ops); | |
1078 | if (!dev) | |
1079 | return NULL; | |
1080 | ||
1081 | priv = dev->priv; | |
a2897552 | 1082 | priv->mode = IEEE80211_IF_TYPE_INVALID; |
eff1a59c | 1083 | skb_queue_head_init(&priv->tx_queue); |
8318d78a | 1084 | dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz; |
eff1a59c | 1085 | dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */ |
566bfe5a BR |
1086 | IEEE80211_HW_RX_INCLUDES_FCS | |
1087 | IEEE80211_HW_SIGNAL_UNSPEC; | |
f59ac048 LR |
1088 | |
1089 | dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
1090 | ||
eff1a59c | 1091 | dev->channel_change_time = 1000; /* TODO: find actual value */ |
566bfe5a | 1092 | dev->max_signal = 127; |
eff1a59c | 1093 | |
84df3ed3 C |
1094 | priv->tx_stats[0].limit = 1; |
1095 | priv->tx_stats[1].limit = 1; | |
1096 | priv->tx_stats[2].limit = 1; | |
1097 | priv->tx_stats[3].limit = 1; | |
1098 | priv->tx_stats[4].limit = 5; | |
eff1a59c | 1099 | dev->queues = 1; |
eff1a59c MW |
1100 | dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 + |
1101 | sizeof(struct p54_tx_control_allocdata); | |
1102 | ||
6041e2a0 | 1103 | mutex_init(&priv->conf_mutex); |
eff1a59c | 1104 | |
eff1a59c MW |
1105 | return dev; |
1106 | } | |
1107 | EXPORT_SYMBOL_GPL(p54_init_common); | |
1108 | ||
1109 | void p54_free_common(struct ieee80211_hw *dev) | |
1110 | { | |
1111 | struct p54_common *priv = dev->priv; | |
1112 | kfree(priv->iq_autocal); | |
1113 | kfree(priv->output_limit); | |
1114 | kfree(priv->curve_data); | |
1115 | kfree(priv->cached_vdcf); | |
1116 | } | |
1117 | EXPORT_SYMBOL_GPL(p54_free_common); | |
1118 | ||
1119 | static int __init p54_init(void) | |
1120 | { | |
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static void __exit p54_exit(void) | |
1125 | { | |
1126 | } | |
1127 | ||
1128 | module_init(p54_init); | |
1129 | module_exit(p54_exit); |