projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
p54: per-device names
[linux-2.6-block.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW		 1/*
2 * Common code for mac80211 Prism54 drivers
3 *
4 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
5 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
c12abae3 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
eff1a59c 7 *
27df605e
JL		 8 * Based on:
9 * - the islsm (softmac prism54) driver, which is:
10 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
11 * - stlc45xx driver
9483407d 12 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
eff1a59c
MW		 13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/init.h>
20#include <linux/firmware.h>
21#include <linux/etherdevice.h>
22
23#include <net/mac80211.h>
24
25#include "p54.h"
26#include "p54common.h"
27
25900ef0
CL		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
eff1a59c
MW		 31MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
32MODULE_DESCRIPTION("Softmac Prism54 common code");
33MODULE_LICENSE("GPL");
34MODULE_ALIAS("prism54common");
35
1b997534 36static struct ieee80211_rate p54_bgrates[] = {
8318d78a
JB		 37 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
38 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
39 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
40 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
41 { .bitrate = 60, .hw_value = 4, },
42 { .bitrate = 90, .hw_value = 5, },
43 { .bitrate = 120, .hw_value = 6, },
44 { .bitrate = 180, .hw_value = 7, },
45 { .bitrate = 240, .hw_value = 8, },
46 { .bitrate = 360, .hw_value = 9, },
47 { .bitrate = 480, .hw_value = 10, },
48 { .bitrate = 540, .hw_value = 11, },
49};
50
1b997534 51static struct ieee80211_channel p54_bgchannels[] = {
8318d78a
JB		 52 { .center_freq = 2412, .hw_value = 1, },
53 { .center_freq = 2417, .hw_value = 2, },
54 { .center_freq = 2422, .hw_value = 3, },
55 { .center_freq = 2427, .hw_value = 4, },
56 { .center_freq = 2432, .hw_value = 5, },
57 { .center_freq = 2437, .hw_value = 6, },
58 { .center_freq = 2442, .hw_value = 7, },
59 { .center_freq = 2447, .hw_value = 8, },
60 { .center_freq = 2452, .hw_value = 9, },
61 { .center_freq = 2457, .hw_value = 10, },
62 { .center_freq = 2462, .hw_value = 11, },
63 { .center_freq = 2467, .hw_value = 12, },
64 { .center_freq = 2472, .hw_value = 13, },
65 { .center_freq = 2484, .hw_value = 14, },
66};
67
c2976ab0 68static struct ieee80211_supported_band band_2GHz = {
1b997534
CL		 69 .channels = p54_bgchannels,
70 .n_channels = ARRAY_SIZE(p54_bgchannels),
71 .bitrates = p54_bgrates,
72 .n_bitrates = ARRAY_SIZE(p54_bgrates),
73};
74
75static struct ieee80211_rate p54_arates[] = {
76 { .bitrate = 60, .hw_value = 4, },
77 { .bitrate = 90, .hw_value = 5, },
78 { .bitrate = 120, .hw_value = 6, },
79 { .bitrate = 180, .hw_value = 7, },
80 { .bitrate = 240, .hw_value = 8, },
81 { .bitrate = 360, .hw_value = 9, },
82 { .bitrate = 480, .hw_value = 10, },
83 { .bitrate = 540, .hw_value = 11, },
84};
85
86static struct ieee80211_channel p54_achannels[] = {
87 { .center_freq = 4920 },
88 { .center_freq = 4940 },
89 { .center_freq = 4960 },
90 { .center_freq = 4980 },
91 { .center_freq = 5040 },
92 { .center_freq = 5060 },
93 { .center_freq = 5080 },
94 { .center_freq = 5170 },
95 { .center_freq = 5180 },
96 { .center_freq = 5190 },
97 { .center_freq = 5200 },
98 { .center_freq = 5210 },
99 { .center_freq = 5220 },
100 { .center_freq = 5230 },
101 { .center_freq = 5240 },
102 { .center_freq = 5260 },
103 { .center_freq = 5280 },
104 { .center_freq = 5300 },
105 { .center_freq = 5320 },
106 { .center_freq = 5500 },
107 { .center_freq = 5520 },
108 { .center_freq = 5540 },
109 { .center_freq = 5560 },
110 { .center_freq = 5580 },
111 { .center_freq = 5600 },
112 { .center_freq = 5620 },
113 { .center_freq = 5640 },
114 { .center_freq = 5660 },
115 { .center_freq = 5680 },
116 { .center_freq = 5700 },
117 { .center_freq = 5745 },
118 { .center_freq = 5765 },
119 { .center_freq = 5785 },
120 { .center_freq = 5805 },
121 { .center_freq = 5825 },
122};
123
124static struct ieee80211_supported_band band_5GHz = {
125 .channels = p54_achannels,
126 .n_channels = ARRAY_SIZE(p54_achannels),
127 .bitrates = p54_arates,
128 .n_bitrates = ARRAY_SIZE(p54_arates),
8318d78a
JB		 129};
130
4e416a6f 131int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
eff1a59c
MW		 132{
133 struct p54_common *priv = dev->priv;
134 struct bootrec_exp_if *exp_if;
135 struct bootrec *bootrec;
136 u32 *data = (u32 *)fw->data;
137 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
138 u8 *fw_version = NULL;
139 size_t len;
140 int i;
141
142 if (priv->rx_start)
4e416a6f 143 return 0;
eff1a59c
MW		 144
145 while (data < end_data && *data)
146 data++;
147
148 while (data < end_data && !*data)
149 data++;
150
151 bootrec = (struct bootrec *) data;
152
153 while (bootrec->data <= end_data &&
154 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
155 u32 code = le32_to_cpu(bootrec->code);
156 switch (code) {
157 case BR_CODE_COMPONENT_ID:
1f1c0e33
LF		 158 priv->fw_interface = be32_to_cpup((__be32 *)
159 bootrec->data);
2b80848e 160 switch (priv->fw_interface) {
eff1a59c 161 case FW_LM86:
02e37ba1
CL		 162 case FW_LM20:
163 case FW_LM87: {
164 char *iftype = (char *)bootrec->data;
165 printk(KERN_INFO "%s: p54 detected a LM%c%c "
166 "firmware\n",
167 wiphy_name(dev->wiphy),
168 iftype[2], iftype[3]);
eff1a59c 169 break;
02e37ba1
CL		 170 }
171 case FW_FMAC:
eff1a59c 172 default:
02e37ba1
CL		 173 printk(KERN_ERR "%s: unsupported firmware\n",
174 wiphy_name(dev->wiphy));
175 return -ENODEV;
eff1a59c
MW		 176 }
177 break;
178 case BR_CODE_COMPONENT_VERSION:
179 /* 24 bytes should be enough for all firmwares */
180 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
181 fw_version = (unsigned char*)bootrec->data;
182 break;
4e416a6f
CL		 183 case BR_CODE_DESCR: {
184 struct bootrec_desc *desc =
185 (struct bootrec_desc *)bootrec->data;
186 priv->rx_start = le32_to_cpu(desc->rx_start);
eff1a59c 187 /* FIXME add sanity checking */
4e416a6f
CL		 188 priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
189 priv->headroom = desc->headroom;
190 priv->tailroom = desc->tailroom;
25900ef0
CL		 191 priv->privacy_caps = desc->privacy_caps;
192 priv->rx_keycache_size = desc->rx_keycache_size;
1f1c0e33 193 if (le32_to_cpu(bootrec->len) == 11)
2e20cc39 194 priv->rx_mtu = le16_to_cpu(desc->rx_mtu);
4e416a6f
CL		 195 else
196 priv->rx_mtu = (size_t)
197 0x620 - priv->tx_hdr_len;
eff1a59c 198 break;
4e416a6f 199 }
eff1a59c
MW		 200 case BR_CODE_EXPOSED_IF:
201 exp_if = (struct bootrec_exp_if *) bootrec->data;
202 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 203 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW		 204 priv->fw_var = le16_to_cpu(exp_if[i].variant);
205 break;
206 case BR_CODE_DEPENDENT_IF:
207 break;
208 case BR_CODE_END_OF_BRA:
209 case LEGACY_BR_CODE_END_OF_BRA:
210 end_data = NULL;
211 break;
212 default:
213 break;
214 }
215 bootrec = (struct bootrec *)&bootrec->data[len];
216 }
217
218 if (fw_version)
02e37ba1
CL		 219 printk(KERN_INFO "%s: FW rev %s - Softmac protocol %x.%x\n",
220 wiphy_name(dev->wiphy), fw_version,
221 priv->fw_var >> 8, priv->fw_var & 0xff);
eff1a59c 222
9a8675d7 223 if (priv->fw_var < 0x500)
02e37ba1 224 printk(KERN_INFO "%s: you are using an obsolete firmware. "
9a8675d7 225 "visit http://wireless.kernel.org/en/users/Drivers/p54 "
02e37ba1
CL		 226 "and grab one for \"kernel >= 2.6.28\"!\n",
227 wiphy_name(dev->wiphy));
9a8675d7 228
eff1a59c
MW		 229 if (priv->fw_var >= 0x300) {
230 /* Firmware supports QoS, use it! */
9e7f3f8e
CL		 231 priv->tx_stats[4].limit = 3; /* AC_VO */
232 priv->tx_stats[5].limit = 4; /* AC_VI */
233 priv->tx_stats[6].limit = 3; /* AC_BE */
234 priv->tx_stats[7].limit = 2; /* AC_BK */
eff1a59c
MW		 235 dev->queues = 4;
236 }
4e416a6f 237
25900ef0
CL		 238 if (!modparam_nohwcrypt)
239 printk(KERN_INFO "%s: cryptographic accelerator "
240 "WEP:%s, TKIP:%s, CCMP:%s\n",
241 wiphy_name(dev->wiphy),
242 (priv->privacy_caps & BR_DESC_PRIV_CAP_WEP) ? "YES" :
243 "no", (priv->privacy_caps & (BR_DESC_PRIV_CAP_TKIP |
244 BR_DESC_PRIV_CAP_MICHAEL)) ? "YES" : "no",
245 (priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP) ?
246 "YES" : "no");
247
4e416a6f 248 return 0;
eff1a59c
MW		 249}
250EXPORT_SYMBOL_GPL(p54_parse_firmware);
251
154e3af1
CL		 252static int p54_convert_rev0(struct ieee80211_hw *dev,
253 struct pda_pa_curve_data *curve_data)
eff1a59c
MW		 254{
255 struct p54_common *priv = dev->priv;
154e3af1
CL		 256 struct p54_pa_curve_data_sample *dst;
257 struct pda_pa_curve_data_sample_rev0 *src;
eff1a59c 258 size_t cd_len = sizeof(*curve_data) +
154e3af1 259 (curve_data->points_per_channel*sizeof(*dst) + 2) *
eff1a59c
MW		 260 curve_data->channels;
261 unsigned int i, j;
262 void *source, *target;
263
264 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
265 if (!priv->curve_data)
266 return -ENOMEM;
267
268 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
269 source = curve_data->data;
270 target = priv->curve_data->data;
271 for (i = 0; i < curve_data->channels; i++) {
272 __le16 *freq = source;
273 source += sizeof(__le16);
274 *((__le16 *)target) = *freq;
275 target += sizeof(__le16);
276 for (j = 0; j < curve_data->points_per_channel; j++) {
154e3af1
CL		 277 dst = target;
278 src = source;
eff1a59c 279
154e3af1
CL		 280 dst->rf_power = src->rf_power;
281 dst->pa_detector = src->pa_detector;
282 dst->data_64qam = src->pcv;
eff1a59c
MW		 283 /* "invent" the points for the other modulations */
284#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
154e3af1
CL		 285 dst->data_16qam = SUB(src->pcv, 12);
286 dst->data_qpsk = SUB(dst->data_16qam, 12);
287 dst->data_bpsk = SUB(dst->data_qpsk, 12);
288 dst->data_barker = SUB(dst->data_bpsk, 14);
eff1a59c 289#undef SUB
154e3af1
CL		 290 target += sizeof(*dst);
291 source += sizeof(*src);
eff1a59c
MW		 292 }
293 }
294
295 return 0;
296}
297
154e3af1
CL		 298static int p54_convert_rev1(struct ieee80211_hw *dev,
299 struct pda_pa_curve_data *curve_data)
300{
301 struct p54_common *priv = dev->priv;
302 struct p54_pa_curve_data_sample *dst;
303 struct pda_pa_curve_data_sample_rev1 *src;
304 size_t cd_len = sizeof(*curve_data) +
305 (curve_data->points_per_channel*sizeof(*dst) + 2) *
306 curve_data->channels;
307 unsigned int i, j;
308 void *source, *target;
309
310 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
311 if (!priv->curve_data)
312 return -ENOMEM;
313
314 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
315 source = curve_data->data;
316 target = priv->curve_data->data;
317 for (i = 0; i < curve_data->channels; i++) {
318 __le16 *freq = source;
319 source += sizeof(__le16);
320 *((__le16 *)target) = *freq;
321 target += sizeof(__le16);
322 for (j = 0; j < curve_data->points_per_channel; j++) {
323 memcpy(target, source, sizeof(*src));
324
325 target += sizeof(*dst);
326 source += sizeof(*src);
327 }
328 source++;
329 }
330
331 return 0;
332}
333
4cc683c9
CL		 334static const char *p54_rf_chips[] = { "NULL", "Duette3", "Duette2",
335 "Frisbee", "Xbow", "Longbow", "NULL", "NULL" };
1b997534 336static int p54_init_xbow_synth(struct ieee80211_hw *dev);
7cb77072 337
1f1c0e33 338static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
eff1a59c
MW		 339{
340 struct p54_common *priv = dev->priv;
341 struct eeprom_pda_wrap *wrap = NULL;
342 struct pda_entry *entry;
eff1a59c
MW		 343 unsigned int data_len, entry_len;
344 void *tmp;
345 int err;
c2f2d3a0 346 u8 *end = (u8 *)eeprom + len;
f2c2e255 347 u16 synth = 0;
eff1a59c
MW		 348
349 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 350 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB		 351
352 /* verify that at least the entry length/code fits */
353 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW		 354 entry_len = le16_to_cpu(entry->len);
355 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB		 356
357 /* abort if entry exceeds whole structure */
358 if ((u8 *)entry + sizeof(*entry) + data_len > end)
359 break;
360
eff1a59c
MW		 361 switch (le16_to_cpu(entry->code)) {
362 case PDR_MAC_ADDRESS:
363 SET_IEEE80211_PERM_ADDR(dev, entry->data);
364 break;
365 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
366 if (data_len < 2) {
367 err = -EINVAL;
368 goto err;
369 }
370
371 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
372 err = -EINVAL;
373 goto err;
374 }
375
376 priv->output_limit = kmalloc(entry->data[1] *
377 sizeof(*priv->output_limit), GFP_KERNEL);
378
379 if (!priv->output_limit) {
380 err = -ENOMEM;
381 goto err;
382 }
383
384 memcpy(priv->output_limit, &entry->data[2],
385 entry->data[1]*sizeof(*priv->output_limit));
386 priv->output_limit_len = entry->data[1];
387 break;
154e3af1
CL		 388 case PDR_PRISM_PA_CAL_CURVE_DATA: {
389 struct pda_pa_curve_data *curve_data =
390 (struct pda_pa_curve_data *)entry->data;
391 if (data_len < sizeof(*curve_data)) {
eff1a59c
MW		 392 err = -EINVAL;
393 goto err;
394 }
395
154e3af1
CL		 396 switch (curve_data->cal_method_rev) {
397 case 0:
398 err = p54_convert_rev0(dev, curve_data);
399 break;
400 case 1:
401 err = p54_convert_rev1(dev, curve_data);
402 break;
403 default:
02e37ba1 404 printk(KERN_ERR "%s: unknown curve data "
154e3af1 405 "revision %d\n",
02e37ba1 406 wiphy_name(dev->wiphy),
154e3af1
CL		 407 curve_data->cal_method_rev);
408 err = -ENODEV;
409 break;
eff1a59c 410 }
154e3af1
CL		 411 if (err)
412 goto err;
eff1a59c 413
154e3af1 414 }
eff1a59c
MW		 415 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
416 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
417 if (!priv->iq_autocal) {
418 err = -ENOMEM;
419 goto err;
420 }
421
422 memcpy(priv->iq_autocal, entry->data, data_len);
423 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
424 break;
425 case PDR_INTERFACE_LIST:
426 tmp = entry->data;
427 while ((u8 *)tmp < entry->data + data_len) {
428 struct bootrec_exp_if *exp_if = tmp;
4cc683c9
CL		 429 if (le16_to_cpu(exp_if->if_id) == 0xf)
430 synth = le16_to_cpu(exp_if->variant);
eff1a59c
MW		 431 tmp += sizeof(struct bootrec_exp_if);
432 }
433 break;
434 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
435 priv->version = *(u8 *)(entry->data + 1);
436 break;
437 case PDR_END:
c2f2d3a0
JB		 438 /* make it overrun */
439 entry_len = len;
eff1a59c 440 break;
c8034c44
PR		 441 case PDR_MANUFACTURING_PART_NUMBER:
442 case PDR_PDA_VERSION:
443 case PDR_NIC_SERIAL_NUMBER:
444 case PDR_REGULATORY_DOMAIN_LIST:
445 case PDR_TEMPERATURE_TYPE:
446 case PDR_PRISM_PCI_IDENTIFIER:
447 case PDR_COUNTRY_INFORMATION:
448 case PDR_OEM_NAME:
449 case PDR_PRODUCT_NAME:
450 case PDR_UTF8_OEM_NAME:
451 case PDR_UTF8_PRODUCT_NAME:
452 case PDR_COUNTRY_LIST:
453 case PDR_DEFAULT_COUNTRY:
454 case PDR_ANTENNA_GAIN:
455 case PDR_PRISM_INDIGO_PA_CALIBRATION_DATA:
456 case PDR_RSSI_LINEAR_APPROXIMATION:
457 case PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND:
458 case PDR_REGULATORY_POWER_LIMITS:
459 case PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED:
460 case PDR_RADIATED_TRANSMISSION_CORRECTION:
461 case PDR_PRISM_TX_IQ_CALIBRATION:
462 case PDR_BASEBAND_REGISTERS:
463 case PDR_PER_CHANNEL_BASEBAND_REGISTERS:
464 break;
58e30739 465 default:
02e37ba1
CL		 466 printk(KERN_INFO "%s: unknown eeprom code : 0x%x\n",
467 wiphy_name(dev->wiphy),
58e30739
FF		 468 le16_to_cpu(entry->code));
469 break;
eff1a59c
MW		 470 }
471
472 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW		 473 }
474
f2c2e255
CL		 475 if (!synth || !priv->iq_autocal || !priv->output_limit ||
476 !priv->curve_data) {
02e37ba1
CL		 477 printk(KERN_ERR "%s: not all required entries found in eeprom!\n",
478 wiphy_name(dev->wiphy));
eff1a59c
MW		 479 err = -EINVAL;
480 goto err;
481 }
482
9e7f3f8e 483 priv->rxhw = synth & PDR_SYNTH_FRONTEND_MASK;
4cc683c9 484 if (priv->rxhw == 4)
1b997534 485 p54_init_xbow_synth(dev);
9e7f3f8e 486 if (!(synth & PDR_SYNTH_24_GHZ_DISABLED))
1b997534 487 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
9e7f3f8e 488 if (!(synth & PDR_SYNTH_5_GHZ_DISABLED))
4cc683c9 489 dev->wiphy->bands[IEEE80211_BAND_5GHZ] = &band_5GHz;
7cb77072
CL		 490
491 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
492 u8 perm_addr[ETH_ALEN];
493
494 printk(KERN_WARNING "%s: Invalid hwaddr! Using randomly generated MAC addr\n",
495 wiphy_name(dev->wiphy));
496 random_ether_addr(perm_addr);
497 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
498 }
499
e174961c 500 printk(KERN_INFO "%s: hwaddr %pM, MAC:isl38%02x RF:%s\n",
7cb77072 501 wiphy_name(dev->wiphy),
e174961c 502 dev->wiphy->perm_addr,
7cb77072
CL		 503 priv->version, p54_rf_chips[priv->rxhw]);
504
eff1a59c
MW		 505 return 0;
506
507 err:
508 if (priv->iq_autocal) {
509 kfree(priv->iq_autocal);
510 priv->iq_autocal = NULL;
511 }
512
513 if (priv->output_limit) {
514 kfree(priv->output_limit);
515 priv->output_limit = NULL;
516 }
517
518 if (priv->curve_data) {
519 kfree(priv->curve_data);
520 priv->curve_data = NULL;
521 }
522
02e37ba1
CL		 523 printk(KERN_ERR "%s: eeprom parse failed!\n",
524 wiphy_name(dev->wiphy));
eff1a59c
MW		 525 return err;
526}
eff1a59c 527
cc6de669
CL		 528static int p54_rssi_to_dbm(struct ieee80211_hw *dev, int rssi)
529{
530 /* TODO: get the rssi_add & rssi_mul data from the eeprom */
531 return ((rssi * 0x83) / 64 - 400) / 4;
532}
533
19c19d54 534static int p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 535{
a0db663f 536 struct p54_common *priv = dev->priv;
27df605e 537 struct p54_rx_data *hdr = (struct p54_rx_data *) skb->data;
eff1a59c
MW		 538 struct ieee80211_rx_status rx_status = {0};
539 u16 freq = le16_to_cpu(hdr->freq);
19c19d54 540 size_t header_len = sizeof(*hdr);
a0db663f 541 u32 tsf32;
eff1a59c 542
27df605e 543 if (!(hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_IN_FCS_GOOD))) {
78d57eb2
CL		 544 if (priv->filter_flags & FIF_FCSFAIL)
545 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
546 else
547 return 0;
548 }
549
25900ef0
CL		 550 if (hdr->decrypt_status == P54_DECRYPT_OK)
551 rx_status.flag |= RX_FLAG_DECRYPTED;
552 if ((hdr->decrypt_status == P54_DECRYPT_FAIL_MICHAEL) ||
553 (hdr->decrypt_status == P54_DECRYPT_FAIL_TKIP))
554 rx_status.flag |= RX_FLAG_MMIC_ERROR;
555
cc6de669
CL		 556 rx_status.signal = p54_rssi_to_dbm(dev, hdr->rssi);
557 rx_status.noise = priv->noise;
8318d78a 558 /* XX correct? */
18d72605 559 rx_status.qual = (100 * hdr->rssi) / 127;
ffed7858
CL		 560 if (hdr->rate & 0x10)
561 rx_status.flag |= RX_FLAG_SHORTPRE;
cf3e74c2
CL		 562 rx_status.rate_idx = (dev->conf.channel->band == IEEE80211_BAND_2GHZ ?
563 hdr->rate : (hdr->rate - 4)) & 0xf;
eff1a59c 564 rx_status.freq = freq;
cf3e74c2 565 rx_status.band = dev->conf.channel->band;
eff1a59c 566 rx_status.antenna = hdr->antenna;
a0db663f
CL		 567
568 tsf32 = le32_to_cpu(hdr->tsf32);
569 if (tsf32 < priv->tsf_low32)
570 priv->tsf_high32++;
571 rx_status.mactime = ((u64)priv->tsf_high32) << 32 | tsf32;
572 priv->tsf_low32 = tsf32;
573
03bffc13 574 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c 575
27df605e 576 if (hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
19c19d54
CL		 577 header_len += hdr->align[0];
578
579 skb_pull(skb, header_len);
eff1a59c
MW		 580 skb_trim(skb, le16_to_cpu(hdr->len));
581
582 ieee80211_rx_irqsafe(dev, skb, &rx_status);
19c19d54
CL		 583
584 return -1;
eff1a59c
MW		 585}
586
587static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
588{
589 struct p54_common *priv = dev->priv;
590 int i;
591
b92f30d6
CL		 592 if (priv->mode == NL80211_IFTYPE_UNSPECIFIED)
593 return ;
594
eff1a59c 595 for (i = 0; i < dev->queues; i++)
84df3ed3 596 if (priv->tx_stats[i + 4].len < priv->tx_stats[i + 4].limit)
eff1a59c
MW		 597 ieee80211_wake_queue(dev, i);
598}
599
b92f30d6
CL		 600void p54_free_skb(struct ieee80211_hw *dev, struct sk_buff *skb)
601{
602 struct p54_common *priv = dev->priv;
603 struct ieee80211_tx_info *info;
604 struct memrecord *range;
605 unsigned long flags;
606 u32 freed = 0, last_addr = priv->rx_start;
607
ffed7858 608 if (unlikely(!skb || !dev || !skb_queue_len(&priv->tx_queue)))
b92f30d6
CL		 609 return;
610
611 spin_lock_irqsave(&priv->tx_queue.lock, flags);
612 info = IEEE80211_SKB_CB(skb);
613 range = (void *)info->rate_driver_data;
614 if (skb->prev != (struct sk_buff *)&priv->tx_queue) {
615 struct ieee80211_tx_info *ni;
616 struct memrecord *mr;
617
618 ni = IEEE80211_SKB_CB(skb->prev);
619 mr = (struct memrecord *)ni->rate_driver_data;
620 last_addr = mr->end_addr;
621 }
622 if (skb->next != (struct sk_buff *)&priv->tx_queue) {
623 struct ieee80211_tx_info *ni;
624 struct memrecord *mr;
625
626 ni = IEEE80211_SKB_CB(skb->next);
627 mr = (struct memrecord *)ni->rate_driver_data;
628 freed = mr->start_addr - last_addr;
629 } else
630 freed = priv->rx_end - last_addr;
631 __skb_unlink(skb, &priv->tx_queue);
632 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
633 kfree_skb(skb);
634
27df605e 635 if (freed >= priv->headroom + sizeof(struct p54_hdr) + 48 +
b92f30d6
CL		 636 IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
637 p54_wake_free_queues(dev);
638}
639EXPORT_SYMBOL_GPL(p54_free_skb);
640
eff1a59c
MW		 641static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
642{
643 struct p54_common *priv = dev->priv;
27df605e
JL		 644 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
645 struct p54_frame_sent *payload = (struct p54_frame_sent *) hdr->data;
eff1a59c 646 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
4e416a6f 647 u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom;
eff1a59c
MW		 648 struct memrecord *range = NULL;
649 u32 freed = 0;
650 u32 last_addr = priv->rx_start;
031d10ee 651 unsigned long flags;
c12abae3 652 int count, idx;
eff1a59c 653
031d10ee 654 spin_lock_irqsave(&priv->tx_queue.lock, flags);
eff1a59c 655 while (entry != (struct sk_buff *)&priv->tx_queue) {
552fe53f 656 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
27df605e
JL		 657 struct p54_hdr *entry_hdr;
658 struct p54_tx_data *entry_data;
9de5776f 659 int pad = 0;
eff1a59c 660
9de5776f
CL		 661 range = (void *)info->rate_driver_data;
662 if (range->start_addr != addr) {
663 last_addr = range->end_addr;
664 entry = entry->next;
665 continue;
666 }
552fe53f 667
9de5776f
CL		 668 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
669 struct ieee80211_tx_info *ni;
670 struct memrecord *mr;
eff1a59c 671
9de5776f
CL		 672 ni = IEEE80211_SKB_CB(entry->next);
673 mr = (struct memrecord *)ni->rate_driver_data;
674 freed = mr->start_addr - last_addr;
675 } else
676 freed = priv->rx_end - last_addr;
677
678 last_addr = range->end_addr;
679 __skb_unlink(entry, &priv->tx_queue);
680 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
681
c772a08b
CL		 682 entry_hdr = (struct p54_hdr *) entry->data;
683 entry_data = (struct p54_tx_data *) entry_hdr->data;
684 priv->tx_stats[entry_data->hw_queue].len--;
685
e5ea92a7
CL		 686 if (unlikely(entry == priv->cached_beacon)) {
687 kfree_skb(entry);
688 priv->cached_beacon = NULL;
689 goto out;
690 }
691
9de5776f
CL		 692 /*
693 * Clear manually, ieee80211_tx_info_clear_status would
694 * clear the counts too and we need them.
695 */
696 memset(&info->status.ampdu_ack_len, 0,
697 sizeof(struct ieee80211_tx_info) -
698 offsetof(struct ieee80211_tx_info, status.ampdu_ack_len));
699 BUILD_BUG_ON(offsetof(struct ieee80211_tx_info,
700 status.ampdu_ack_len) != 23);
701
27df605e 702 if (entry_hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
9de5776f
CL		 703 pad = entry_data->align[0];
704
705 /* walk through the rates array and adjust the counts */
27df605e 706 count = payload->tries;
9de5776f
CL		 707 for (idx = 0; idx < 4; idx++) {
708 if (count >= info->status.rates[idx].count) {
709 count -= info->status.rates[idx].count;
710 } else if (count > 0) {
711 info->status.rates[idx].count = count;
712 count = 0;
713 } else {
714 info->status.rates[idx].idx = -1;
715 info->status.rates[idx].count = 0;
eff1a59c 716 }
9de5776f 717 }
c12abae3 718
9de5776f
CL		 719 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
720 (!payload->status))
721 info->flags |= IEEE80211_TX_STAT_ACK;
9e7f3f8e 722 if (payload->status & P54_TX_PSM_CANCELLED)
9de5776f
CL		 723 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
724 info->status.ack_signal = p54_rssi_to_dbm(dev,
27df605e 725 (int)payload->ack_rssi);
9de5776f
CL		 726 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
727 ieee80211_tx_status_irqsafe(dev, entry);
728 goto out;
eff1a59c 729 }
031d10ee 730 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
eff1a59c 731
031d10ee 732out:
27df605e 733 if (freed >= priv->headroom + sizeof(struct p54_hdr) + 48 +
9de5776f 734 IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
eff1a59c
MW		 735 p54_wake_free_queues(dev);
736}
737
7cb77072
CL		 738static void p54_rx_eeprom_readback(struct ieee80211_hw *dev,
739 struct sk_buff *skb)
740{
27df605e 741 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
7cb77072
CL		 742 struct p54_eeprom_lm86 *eeprom = (struct p54_eeprom_lm86 *) hdr->data;
743 struct p54_common *priv = dev->priv;
744
745 if (!priv->eeprom)
746 return ;
747
64c354dd
CL		 748 if (priv->fw_var >= 0x509) {
749 memcpy(priv->eeprom, eeprom->v2.data,
750 le16_to_cpu(eeprom->v2.len));
751 } else {
752 memcpy(priv->eeprom, eeprom->v1.data,
753 le16_to_cpu(eeprom->v1.len));
754 }
7cb77072
CL		 755
756 complete(&priv->eeprom_comp);
757}
758
cc6de669
CL		 759static void p54_rx_stats(struct ieee80211_hw *dev, struct sk_buff *skb)
760{
761 struct p54_common *priv = dev->priv;
27df605e 762 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
cc6de669
CL		 763 struct p54_statistics *stats = (struct p54_statistics *) hdr->data;
764 u32 tsf32 = le32_to_cpu(stats->tsf32);
765
766 if (tsf32 < priv->tsf_low32)
767 priv->tsf_high32++;
768 priv->tsf_low32 = tsf32;
769
770 priv->stats.dot11RTSFailureCount = le32_to_cpu(stats->rts_fail);
771 priv->stats.dot11RTSSuccessCount = le32_to_cpu(stats->rts_success);
772 priv->stats.dot11FCSErrorCount = le32_to_cpu(stats->rx_bad_fcs);
773
774 priv->noise = p54_rssi_to_dbm(dev, le32_to_cpu(stats->noise));
775 complete(&priv->stats_comp);
776
777 mod_timer(&priv->stats_timer, jiffies + 5 * HZ);
778}
779
e5ea92a7
CL		 780static void p54_rx_trap(struct ieee80211_hw *dev, struct sk_buff *skb)
781{
782 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
783 struct p54_trap *trap = (struct p54_trap *) hdr->data;
784 u16 event = le16_to_cpu(trap->event);
785 u16 freq = le16_to_cpu(trap->frequency);
786
787 switch (event) {
788 case P54_TRAP_BEACON_TX:
789 break;
790 case P54_TRAP_RADAR:
791 printk(KERN_INFO "%s: radar (freq:%d MHz)\n",
792 wiphy_name(dev->wiphy), freq);
793 break;
794 case P54_TRAP_NO_BEACON:
795 break;
796 case P54_TRAP_SCAN:
797 break;
798 case P54_TRAP_TBTT:
799 break;
800 case P54_TRAP_TIMER:
801 break;
802 default:
803 printk(KERN_INFO "%s: received event:%x freq:%d\n",
804 wiphy_name(dev->wiphy), event, freq);
805 break;
806 }
807}
808
19c19d54 809static int p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 810{
27df605e 811 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
eff1a59c
MW		 812
813 switch (le16_to_cpu(hdr->type)) {
814 case P54_CONTROL_TYPE_TXDONE:
815 p54_rx_frame_sent(dev, skb);
816 break;
e5ea92a7
CL		 817 case P54_CONTROL_TYPE_TRAP:
818 p54_rx_trap(dev, skb);
819 break;
eff1a59c
MW		 820 case P54_CONTROL_TYPE_BBP:
821 break;
cc6de669
CL		 822 case P54_CONTROL_TYPE_STAT_READBACK:
823 p54_rx_stats(dev, skb);
824 break;
7cb77072
CL		 825 case P54_CONTROL_TYPE_EEPROM_READBACK:
826 p54_rx_eeprom_readback(dev, skb);
827 break;
eff1a59c
MW		 828 default:
829 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
830 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
831 break;
832 }
19c19d54
CL		 833
834 return 0;
eff1a59c
MW		 835}
836
837/* returns zero if skb can be reused */
838int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
839{
9e7f3f8e 840 u16 type = le16_to_cpu(*((__le16 *)skb->data));
19c19d54 841
9e7f3f8e 842 if (type & P54_HDR_FLAG_CONTROL)
19c19d54
CL		 843 return p54_rx_control(dev, skb);
844 else
845 return p54_rx_data(dev, skb);
eff1a59c
MW		 846}
847EXPORT_SYMBOL_GPL(p54_rx);
848
849/*
850 * So, the firmware is somewhat stupid and doesn't know what places in its
851 * memory incoming data should go to. By poking around in the firmware, we
852 * can find some unused memory to upload our packets to. However, data that we
853 * want the card to TX needs to stay intact until the card has told us that
854 * it is done with it. This function finds empty places we can upload to and
855 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
856 * allocated areas.
857 */
b92f30d6 858static int p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
27df605e 859 struct p54_hdr *data, u32 len)
eff1a59c
MW		 860{
861 struct p54_common *priv = dev->priv;
862 struct sk_buff *entry = priv->tx_queue.next;
863 struct sk_buff *target_skb = NULL;
b92f30d6
CL		 864 struct ieee80211_tx_info *info;
865 struct memrecord *range;
eff1a59c
MW		 866 u32 last_addr = priv->rx_start;
867 u32 largest_hole = 0;
868 u32 target_addr = priv->rx_start;
869 unsigned long flags;
870 unsigned int left;
4e416a6f 871 len = (len + priv->headroom + priv->tailroom + 3) & ~0x3;
eff1a59c 872
b92f30d6
CL		 873 if (!skb)
874 return -EINVAL;
875
eff1a59c
MW		 876 spin_lock_irqsave(&priv->tx_queue.lock, flags);
877 left = skb_queue_len(&priv->tx_queue);
878 while (left--) {
879 u32 hole_size;
b92f30d6
CL		 880 info = IEEE80211_SKB_CB(entry);
881 range = (void *)info->rate_driver_data;
eff1a59c
MW		 882 hole_size = range->start_addr - last_addr;
883 if (!target_skb && hole_size >= len) {
884 target_skb = entry->prev;
885 hole_size -= len;
886 target_addr = last_addr;
887 }
888 largest_hole = max(largest_hole, hole_size);
889 last_addr = range->end_addr;
890 entry = entry->next;
891 }
892 if (!target_skb && priv->rx_end - last_addr >= len) {
893 target_skb = priv->tx_queue.prev;
894 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
895 if (!skb_queue_empty(&priv->tx_queue)) {
b92f30d6
CL		 896 info = IEEE80211_SKB_CB(target_skb);
897 range = (void *)info->rate_driver_data;
eff1a59c
MW		 898 target_addr = range->end_addr;
899 }
900 } else
901 largest_hole = max(largest_hole, priv->rx_end - last_addr);
902
b92f30d6
CL		 903 if (!target_skb) {
904 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
905 ieee80211_stop_queues(dev);
906 return -ENOMEM;
eff1a59c 907 }
b92f30d6
CL		 908
909 info = IEEE80211_SKB_CB(skb);
910 range = (void *)info->rate_driver_data;
911 range->start_addr = target_addr;
912 range->end_addr = target_addr + len;
913 __skb_queue_after(&priv->tx_queue, target_skb, skb);
eff1a59c
MW		 914 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
915
27df605e 916 if (largest_hole < priv->headroom + sizeof(struct p54_hdr) +
b92f30d6
CL		 917 48 + IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
918 ieee80211_stop_queues(dev);
919
4e416a6f 920 data->req_id = cpu_to_le32(target_addr + priv->headroom);
b92f30d6
CL		 921 return 0;
922}
923
924static struct sk_buff *p54_alloc_skb(struct ieee80211_hw *dev,
925 u16 hdr_flags, u16 len, u16 type, gfp_t memflags)
926{
927 struct p54_common *priv = dev->priv;
27df605e 928 struct p54_hdr *hdr;
b92f30d6
CL		 929 struct sk_buff *skb;
930
931 skb = __dev_alloc_skb(len + priv->tx_hdr_len, memflags);
932 if (!skb)
933 return NULL;
934 skb_reserve(skb, priv->tx_hdr_len);
935
27df605e
JL		 936 hdr = (struct p54_hdr *) skb_put(skb, sizeof(*hdr));
937 hdr->flags = cpu_to_le16(hdr_flags);
b92f30d6
CL		 938 hdr->len = cpu_to_le16(len - sizeof(*hdr));
939 hdr->type = cpu_to_le16(type);
27df605e 940 hdr->tries = hdr->rts_tries = 0;
b92f30d6
CL		 941
942 if (unlikely(p54_assign_address(dev, skb, hdr, len))) {
943 kfree_skb(skb);
944 return NULL;
945 }
946 return skb;
eff1a59c
MW		 947}
948
7cb77072
CL		 949int p54_read_eeprom(struct ieee80211_hw *dev)
950{
951 struct p54_common *priv = dev->priv;
27df605e 952 struct p54_hdr *hdr = NULL;
7cb77072 953 struct p54_eeprom_lm86 *eeprom_hdr;
b92f30d6 954 struct sk_buff *skb;
64c354dd 955 size_t eeprom_size = 0x2020, offset = 0, blocksize, maxblocksize;
7cb77072
CL		 956 int ret = -ENOMEM;
957 void *eeprom = NULL;
958
64c354dd
CL		 959 maxblocksize = EEPROM_READBACK_LEN;
960 if (priv->fw_var >= 0x509)
961 maxblocksize -= 0xc;
962 else
963 maxblocksize -= 0x4;
964
965 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL, sizeof(*hdr) +
966 sizeof(*eeprom_hdr) + maxblocksize,
b92f30d6
CL		 967 P54_CONTROL_TYPE_EEPROM_READBACK, GFP_KERNEL);
968 if (!skb)
7cb77072 969 goto free;
7cb77072
CL		 970 priv->eeprom = kzalloc(EEPROM_READBACK_LEN, GFP_KERNEL);
971 if (!priv->eeprom)
972 goto free;
7cb77072
CL		 973 eeprom = kzalloc(eeprom_size, GFP_KERNEL);
974 if (!eeprom)
975 goto free;
976
b92f30d6 977 eeprom_hdr = (struct p54_eeprom_lm86 *) skb_put(skb,
64c354dd 978 sizeof(*eeprom_hdr) + maxblocksize);
7cb77072
CL		 979
980 while (eeprom_size) {
64c354dd
CL		 981 blocksize = min(eeprom_size, maxblocksize);
982 if (priv->fw_var < 0x509) {
983 eeprom_hdr->v1.offset = cpu_to_le16(offset);
984 eeprom_hdr->v1.len = cpu_to_le16(blocksize);
985 } else {
986 eeprom_hdr->v2.offset = cpu_to_le32(offset);
987 eeprom_hdr->v2.len = cpu_to_le16(blocksize);
988 eeprom_hdr->v2.magic2 = 0xf;
989 memcpy(eeprom_hdr->v2.magic, (const char *)"LOCK", 4);
990 }
b92f30d6 991 priv->tx(dev, skb, 0);
7cb77072
CL		 992
993 if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) {
994 printk(KERN_ERR "%s: device does not respond!\n",
995 wiphy_name(dev->wiphy));
996 ret = -EBUSY;
997 goto free;
998 }
999
1000 memcpy(eeprom + offset, priv->eeprom, blocksize);
1001 offset += blocksize;
1002 eeprom_size -= blocksize;
1003 }
1004
1005 ret = p54_parse_eeprom(dev, eeprom, offset);
1006free:
1007 kfree(priv->eeprom);
1008 priv->eeprom = NULL;
b92f30d6 1009 p54_free_skb(dev, skb);
7cb77072
CL		 1010 kfree(eeprom);
1011
1012 return ret;
1013}
1014EXPORT_SYMBOL_GPL(p54_read_eeprom);
1015
e5ea92a7
CL		 1016static int p54_set_tim(struct ieee80211_hw *dev, struct ieee80211_sta *sta,
1017 bool set)
1018{
1019 struct p54_common *priv = dev->priv;
1020 struct sk_buff *skb;
1021 struct p54_tim *tim;
1022
1023 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1024 sizeof(struct p54_hdr) + sizeof(*tim),
1025 P54_CONTROL_TYPE_TIM, GFP_KERNEL);
1026 if (!skb)
1027 return -ENOMEM;
1028
1029 tim = (struct p54_tim *) skb_put(skb, sizeof(*tim));
1030 tim->count = 1;
1031 tim->entry[0] = cpu_to_le16(set ? (sta->aid | 0x8000) : sta->aid);
1032 priv->tx(dev, skb, 1);
1033 return 0;
1034}
1035
1036static int p54_sta_unlock(struct ieee80211_hw *dev, u8 *addr)
1037{
1038 struct p54_common *priv = dev->priv;
1039 struct sk_buff *skb;
1040 struct p54_sta_unlock *sta;
1041
1042 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1043 sizeof(struct p54_hdr) + sizeof(*sta),
1044 P54_CONTROL_TYPE_PSM_STA_UNLOCK, GFP_ATOMIC);
1045 if (!skb)
1046 return -ENOMEM;
1047
1048 sta = (struct p54_sta_unlock *)skb_put(skb, sizeof(*sta));
1049 memcpy(sta->addr, addr, ETH_ALEN);
1050 priv->tx(dev, skb, 1);
1051 return 0;
1052}
1053
c772a08b
CL		 1054static void p54_sta_notify_ps(struct ieee80211_hw *dev,
1055 enum sta_notify_ps_cmd notify_cmd,
1056 struct ieee80211_sta *sta)
1057{
1058 switch (notify_cmd) {
1059 case STA_NOTIFY_AWAKE:
1060 p54_sta_unlock(dev, sta->addr);
1061 break;
1062 default:
1063 break;
1064 }
1065}
1066
1067static void p54_sta_notify(struct ieee80211_hw *dev, struct ieee80211_vif *vif,
1068 enum sta_notify_cmd notify_cmd,
1069 struct ieee80211_sta *sta)
1070{
1071 switch (notify_cmd) {
1072 case STA_NOTIFY_ADD:
1073 case STA_NOTIFY_REMOVE:
1074 /*
1075 * Notify the firmware that we don't want or we don't
1076 * need to buffer frames for this station anymore.
1077 */
1078
1079 p54_sta_unlock(dev, sta->addr);
1080 break;
1081 default:
1082 break;
1083 }
1084}
1085
e5ea92a7
CL		 1086static int p54_tx_cancel(struct ieee80211_hw *dev, struct sk_buff *entry)
1087{
1088 struct p54_common *priv = dev->priv;
1089 struct sk_buff *skb;
1090 struct p54_hdr *hdr;
1091 struct p54_txcancel *cancel;
1092
1093 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1094 sizeof(struct p54_hdr) + sizeof(*cancel),
1095 P54_CONTROL_TYPE_TXCANCEL, GFP_ATOMIC);
1096 if (!skb)
1097 return -ENOMEM;
1098
1099 hdr = (void *)entry->data;
1100 cancel = (struct p54_txcancel *)skb_put(skb, sizeof(*cancel));
1101 cancel->req_id = hdr->req_id;
1102 priv->tx(dev, skb, 1);
1103 return 0;
1104}
1105
94585b09
CL		 1106static int p54_tx_fill(struct ieee80211_hw *dev, struct sk_buff *skb,
1107 struct ieee80211_tx_info *info, u8 *queue, size_t *extra_len,
1108 u16 *flags, u16 *aid)
1109{
1110 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1111 struct p54_common *priv = dev->priv;
1112 int ret = 0;
1113
1114 if (unlikely(ieee80211_is_mgmt(hdr->frame_control))) {
1115 if (ieee80211_is_beacon(hdr->frame_control)) {
1116 *aid = 0;
1117 *queue = 0;
1118 *extra_len = IEEE80211_MAX_TIM_LEN;
1119 *flags = P54_HDR_FLAG_DATA_OUT_TIMESTAMP;
1120 return 0;
1121 } else if (ieee80211_is_probe_resp(hdr->frame_control)) {
1122 *aid = 0;
1123 *queue = 2;
1124 *flags = P54_HDR_FLAG_DATA_OUT_TIMESTAMP |
1125 P54_HDR_FLAG_DATA_OUT_NOCANCEL;
1126 return 0;
1127 } else {
1128 *queue = 2;
1129 ret = 0;
1130 }
1131 } else {
1132 *queue += 4;
1133 ret = 1;
1134 }
1135
1136 switch (priv->mode) {
1137 case NL80211_IFTYPE_STATION:
1138 *aid = 1;
1139 break;
1140 case NL80211_IFTYPE_AP:
1141 case NL80211_IFTYPE_ADHOC:
d131bb59 1142 case NL80211_IFTYPE_MESH_POINT:
94585b09
CL		 1143 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1144 *aid = 0;
1145 *queue = 3;
1146 return 0;
1147 }
1148 if (info->control.sta)
1149 *aid = info->control.sta->aid;
1150 else
c772a08b 1151 *flags |= P54_HDR_FLAG_DATA_OUT_NOCANCEL;
94585b09
CL		 1152 }
1153 return ret;
1154}
1155
25900ef0
CL		 1156static u8 p54_convert_algo(enum ieee80211_key_alg alg)
1157{
1158 switch (alg) {
1159 case ALG_WEP:
1160 return P54_CRYPTO_WEP;
1161 case ALG_TKIP:
1162 return P54_CRYPTO_TKIPMICHAEL;
1163 case ALG_CCMP:
1164 return P54_CRYPTO_AESCCMP;
1165 default:
1166 return 0;
1167 }
1168}
1169
e039fa4a 1170static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 1171{
e039fa4a 1172 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9e7f3f8e 1173 struct ieee80211_tx_queue_stats *current_queue = NULL;
eff1a59c 1174 struct p54_common *priv = dev->priv;
27df605e
JL		 1175 struct p54_hdr *hdr;
1176 struct p54_tx_data *txhdr;
db4186cf 1177 size_t padding, len, tim_len = 0;
c772a08b 1178 int i, j, ridx, ret;
94585b09 1179 u16 hdr_flags = 0, aid = 0;
25900ef0 1180 u8 rate, queue, crypt_offset = 0;
aaa15535 1181 u8 cts_rate = 0x20;
e6a9854b 1182 u8 rc_flags;
c12abae3
JB		 1183 u8 calculated_tries[4];
1184 u8 nrates = 0, nremaining = 8;
eff1a59c 1185
94585b09
CL		 1186 queue = skb_get_queue_mapping(skb);
1187
c772a08b
CL		 1188 ret = p54_tx_fill(dev, skb, info, &queue, &tim_len, &hdr_flags, &aid);
1189 current_queue = &priv->tx_stats[queue];
1190 if (unlikely((current_queue->len > current_queue->limit) && ret))
1191 return NETDEV_TX_BUSY;
1192 current_queue->len++;
1193 current_queue->count++;
1194 if ((current_queue->len == current_queue->limit) && ret)
1195 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
eff1a59c
MW		 1196
1197 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
1198 len = skb->len;
1199
25900ef0
CL		 1200 if (info->control.hw_key) {
1201 crypt_offset = ieee80211_get_hdrlen_from_skb(skb);
1202 if (info->control.hw_key->alg == ALG_TKIP) {
1203 u8 *iv = (u8 *)(skb->data + crypt_offset);
1204 /*
1205 * The firmware excepts that the IV has to have
1206 * this special format
1207 */
1208 iv[1] = iv[0];
1209 iv[0] = iv[2];
1210 iv[2] = 0;
1211 }
1212 }
1213
27df605e
JL		 1214 txhdr = (struct p54_tx_data *) skb_push(skb, sizeof(*txhdr) + padding);
1215 hdr = (struct p54_hdr *) skb_push(skb, sizeof(*hdr));
eff1a59c
MW		 1216
1217 if (padding)
9e7f3f8e 1218 hdr_flags |= P54_HDR_FLAG_DATA_ALIGN;
94585b09 1219 hdr->type = cpu_to_le16(aid);
27df605e 1220 hdr->rts_tries = info->control.rates[0].count;
c12abae3
JB		 1221
1222 /*
1223 * we register the rates in perfect order, and
1224 * RTS/CTS won't happen on 5 GHz
1225 */
1226 cts_rate = info->control.rts_cts_rate_idx;
1227
1228 memset(&txhdr->rateset, 0, sizeof(txhdr->rateset));
1229
1230 /* see how many rates got used */
1231 for (i = 0; i < 4; i++) {
1232 if (info->control.rates[i].idx < 0)
1233 break;
1234 nrates++;
1235 }
1236
1237 /* limit tries to 8/nrates per rate */
1238 for (i = 0; i < nrates; i++) {
1239 /*
1240 * The magic expression here is equivalent to 8/nrates for
1241 * all values that matter, but avoids division and jumps.
1242 * Note that nrates can only take the values 1 through 4.
1243 */
1244 calculated_tries[i] = min_t(int, ((15 >> nrates) | 1) + 1,
1245 info->control.rates[i].count);
1246 nremaining -= calculated_tries[i];
aaa15535 1247 }
c12abae3
JB		 1248
1249 /* if there are tries left, distribute from back to front */
1250 for (i = nrates - 1; nremaining > 0 && i >= 0; i--) {
1251 int tmp = info->control.rates[i].count - calculated_tries[i];
1252
1253 if (tmp <= 0)
1254 continue;
1255 /* RC requested more tries at this rate */
1256
1257 tmp = min_t(int, tmp, nremaining);
1258 calculated_tries[i] += tmp;
1259 nremaining -= tmp;
aaa15535 1260 }
c12abae3
JB		 1261
1262 ridx = 0;
1263 for (i = 0; i < nrates && ridx < 8; i++) {
1264 /* we register the rates in perfect order */
1265 rate = info->control.rates[i].idx;
1266 if (info->band == IEEE80211_BAND_5GHZ)
1267 rate += 4;
1268
1269 /* store the count we actually calculated for TX status */
1270 info->control.rates[i].count = calculated_tries[i];
1271
1272 rc_flags = info->control.rates[i].flags;
1273 if (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) {
1274 rate |= 0x10;
1275 cts_rate |= 0x10;
1276 }
1277 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1278 rate |= 0x40;
1279 else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1280 rate |= 0x20;
1281 for (j = 0; j < calculated_tries[i] && ridx < 8; j++) {
1282 txhdr->rateset[ridx] = rate;
1283 ridx++;
1284 }
1285 }
9e7f3f8e
CL		 1286
1287 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
1288 hdr_flags |= P54_HDR_FLAG_DATA_OUT_SEQNR;
1289
1290 /* TODO: enable bursting */
1291 hdr->flags = cpu_to_le16(hdr_flags);
27df605e 1292 hdr->tries = ridx;
27df605e 1293 txhdr->rts_rate_idx = 0;
25900ef0
CL		 1294 if (info->control.hw_key) {
1295 crypt_offset += info->control.hw_key->iv_len;
1296 txhdr->key_type = p54_convert_algo(info->control.hw_key->alg);
1297 txhdr->key_len = min((u8)16, info->control.hw_key->keylen);
1298 memcpy(txhdr->key, info->control.hw_key->key, txhdr->key_len);
1299 if (info->control.hw_key->alg == ALG_TKIP) {
1300 if (unlikely(skb_tailroom(skb) < 12))
1301 goto err;
1302 /* reserve space for the MIC key */
1303 len += 8;
1304 memcpy(skb_put(skb, 8), &(info->control.hw_key->key
1305 [NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY]), 8);
1306 }
1307 /* reserve some space for ICV */
1308 len += info->control.hw_key->icv_len;
1309 } else {
1310 txhdr->key_type = 0;
1311 txhdr->key_len = 0;
1312 }
1313 txhdr->crypt_offset = crypt_offset;
94585b09 1314 txhdr->hw_queue = queue;
ffed7858
CL		 1315 if (current_queue)
1316 txhdr->backlog = current_queue->len;
1317 else
1318 txhdr->backlog = 0;
27df605e 1319 memset(txhdr->durations, 0, sizeof(txhdr->durations));
aaa15535 1320 txhdr->tx_antenna = (info->antenna_sel_tx == 0) ?
e039fa4a 1321 2 : info->antenna_sel_tx - 1;
09adf284 1322 txhdr->output_power = priv->output_power;
27df605e 1323 txhdr->cts_rate = cts_rate;
eff1a59c
MW		 1324 if (padding)
1325 txhdr->align[0] = padding;
1326
25900ef0 1327 hdr->len = cpu_to_le16(len);
e039fa4a 1328 /* modifies skb->cb and with it info, so must be last! */
25900ef0
CL		 1329 if (unlikely(p54_assign_address(dev, skb, hdr, skb->len + tim_len)))
1330 goto err;
b92f30d6 1331 priv->tx(dev, skb, 0);
eff1a59c 1332 return 0;
25900ef0
CL		 1333
1334 err:
1335 skb_pull(skb, sizeof(*hdr) + sizeof(*txhdr) + padding);
1336 if (current_queue) {
1337 current_queue->len--;
1338 current_queue->count--;
1339 }
1340 return NETDEV_TX_BUSY;
eff1a59c
MW		 1341}
1342
b2023ddc 1343static int p54_setup_mac(struct ieee80211_hw *dev)
eff1a59c
MW		 1344{
1345 struct p54_common *priv = dev->priv;
b92f30d6 1346 struct sk_buff *skb;
5e73444e 1347 struct p54_setup_mac *setup;
b2023ddc 1348 u16 mode;
eff1a59c 1349
27df605e
JL		 1350 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*setup) +
1351 sizeof(struct p54_hdr), P54_CONTROL_TYPE_SETUP,
b92f30d6
CL		 1352 GFP_ATOMIC);
1353 if (!skb)
1354 return -ENOMEM;
eff1a59c 1355
5e73444e 1356 setup = (struct p54_setup_mac *) skb_put(skb, sizeof(*setup));
b2023ddc
CL		 1357 if (dev->conf.radio_enabled) {
1358 switch (priv->mode) {
1359 case NL80211_IFTYPE_STATION:
1360 mode = P54_FILTER_TYPE_STATION;
1361 break;
1362 case NL80211_IFTYPE_AP:
1363 mode = P54_FILTER_TYPE_AP;
1364 break;
1365 case NL80211_IFTYPE_ADHOC:
1366 case NL80211_IFTYPE_MESH_POINT:
1367 mode = P54_FILTER_TYPE_IBSS;
1368 break;
1369 default:
1370 mode = P54_FILTER_TYPE_NONE;
1371 break;
1372 }
1373 if (priv->filter_flags & FIF_PROMISC_IN_BSS)
1374 mode |= P54_FILTER_TYPE_TRANSPARENT;
1375 } else
1376 mode = P54_FILTER_TYPE_RX_DISABLED;
1377
5e73444e
CL		 1378 setup->mac_mode = cpu_to_le16(mode);
1379 memcpy(setup->mac_addr, priv->mac_addr, ETH_ALEN);
b2023ddc
CL		 1380 memcpy(setup->bssid, priv->bssid, ETH_ALEN);
1381 setup->rx_antenna = 2; /* automatic */
9483407d 1382 setup->rx_align = 0;
19c19d54 1383 if (priv->fw_var < 0x500) {
ced09574 1384 setup->v1.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
9483407d 1385 memset(setup->v1.rts_rates, 0, 8);
5e73444e
CL		 1386 setup->v1.rx_addr = cpu_to_le32(priv->rx_end);
1387 setup->v1.max_rx = cpu_to_le16(priv->rx_mtu);
1388 setup->v1.rxhw = cpu_to_le16(priv->rxhw);
ced09574 1389 setup->v1.wakeup_timer = cpu_to_le16(priv->wakeup_timer);
5e73444e 1390 setup->v1.unalloc0 = cpu_to_le16(0);
19c19d54 1391 } else {
5e73444e
CL		 1392 setup->v2.rx_addr = cpu_to_le32(priv->rx_end);
1393 setup->v2.max_rx = cpu_to_le16(priv->rx_mtu);
1394 setup->v2.rxhw = cpu_to_le16(priv->rxhw);
ced09574 1395 setup->v2.timer = cpu_to_le16(priv->wakeup_timer);
5e73444e 1396 setup->v2.truncate = cpu_to_le16(48896);
ced09574 1397 setup->v2.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
5e73444e
CL		 1398 setup->v2.sbss_offset = 0;
1399 setup->v2.mcast_window = 0;
1400 setup->v2.rx_rssi_threshold = 0;
1401 setup->v2.rx_ed_threshold = 0;
1402 setup->v2.ref_clock = cpu_to_le32(644245094);
1403 setup->v2.lpf_bandwidth = cpu_to_le16(65535);
1404 setup->v2.osc_start_delay = cpu_to_le16(65535);
19c19d54 1405 }
b92f30d6 1406 priv->tx(dev, skb, 1);
eff1a59c
MW		 1407 return 0;
1408}
1409
b2023ddc
CL		 1410static int p54_scan(struct ieee80211_hw *dev, u16 mode, u16 dwell,
1411 u16 frequency)
eff1a59c
MW		 1412{
1413 struct p54_common *priv = dev->priv;
b92f30d6 1414 struct sk_buff *skb;
27df605e 1415 struct p54_scan *chan;
eff1a59c 1416 unsigned int i;
eff1a59c 1417 void *entry;
9e7f3f8e 1418 __le16 freq = cpu_to_le16(frequency);
eff1a59c 1419
27df605e
JL		 1420 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*chan) +
1421 sizeof(struct p54_hdr), P54_CONTROL_TYPE_SCAN,
1422 GFP_ATOMIC);
b92f30d6 1423 if (!skb)
eff1a59c
MW		 1424 return -ENOMEM;
1425
27df605e 1426 chan = (struct p54_scan *) skb_put(skb, sizeof(*chan));
b92f30d6 1427 memset(chan->padding1, 0, sizeof(chan->padding1));
b2023ddc
CL		 1428 chan->mode = cpu_to_le16(mode);
1429 chan->dwell = cpu_to_le16(dwell);
eff1a59c
MW		 1430
1431 for (i = 0; i < priv->iq_autocal_len; i++) {
1432 if (priv->iq_autocal[i].freq != freq)
1433 continue;
1434
1435 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
1436 sizeof(*priv->iq_autocal));
1437 break;
1438 }
1439 if (i == priv->iq_autocal_len)
1440 goto err;
1441
1442 for (i = 0; i < priv->output_limit_len; i++) {
1443 if (priv->output_limit[i].freq != freq)
1444 continue;
1445
1446 chan->val_barker = 0x38;
154e3af1
CL		 1447 chan->val_bpsk = chan->dup_bpsk =
1448 priv->output_limit[i].val_bpsk;
1449 chan->val_qpsk = chan->dup_qpsk =
1450 priv->output_limit[i].val_qpsk;
1451 chan->val_16qam = chan->dup_16qam =
1452 priv->output_limit[i].val_16qam;
1453 chan->val_64qam = chan->dup_64qam =
1454 priv->output_limit[i].val_64qam;
eff1a59c
MW		 1455 break;
1456 }
1457 if (i == priv->output_limit_len)
1458 goto err;
1459
eff1a59c
MW		 1460 entry = priv->curve_data->data;
1461 for (i = 0; i < priv->curve_data->channels; i++) {
1462 if (*((__le16 *)entry) != freq) {
1463 entry += sizeof(__le16);
154e3af1
CL		 1464 entry += sizeof(struct p54_pa_curve_data_sample) *
1465 priv->curve_data->points_per_channel;
eff1a59c
MW		 1466 continue;
1467 }
1468
1469 entry += sizeof(__le16);
9483407d
C		 1470 chan->pa_points_per_curve = 8;
1471 memset(chan->curve_data, 0, sizeof(*chan->curve_data));
1472 memcpy(chan->curve_data, entry,
1473 sizeof(struct p54_pa_curve_data_sample) *
1474 min((u8)8, priv->curve_data->points_per_channel));
eff1a59c
MW		 1475 break;
1476 }
1477
19c19d54 1478 if (priv->fw_var < 0x500) {
19c19d54
CL		 1479 chan->v1.rssical_mul = cpu_to_le16(130);
1480 chan->v1.rssical_add = cpu_to_le16(0xfe70);
1481 } else {
19c19d54
CL		 1482 chan->v2.rssical_mul = cpu_to_le16(130);
1483 chan->v2.rssical_add = cpu_to_le16(0xfe70);
ced09574 1484 chan->v2.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
27df605e 1485 memset(chan->v2.rts_rates, 0, 8);
19c19d54 1486 }
b92f30d6 1487 priv->tx(dev, skb, 1);
eff1a59c
MW		 1488 return 0;
1489
1490 err:
1491 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
b92f30d6 1492 kfree_skb(skb);
eff1a59c
MW		 1493 return -EINVAL;
1494}
1495
1496static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
1497{
1498 struct p54_common *priv = dev->priv;
b92f30d6 1499 struct sk_buff *skb;
27df605e 1500 struct p54_led *led;
eff1a59c 1501
27df605e
JL		 1502 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*led) +
1503 sizeof(struct p54_hdr), P54_CONTROL_TYPE_LED,
1504 GFP_ATOMIC);
b92f30d6 1505 if (!skb)
eff1a59c
MW		 1506 return -ENOMEM;
1507
27df605e 1508 led = (struct p54_led *)skb_put(skb, sizeof(*led));
eff1a59c
MW		 1509 led->mode = cpu_to_le16(mode);
1510 led->led_permanent = cpu_to_le16(link);
1511 led->led_temporary = cpu_to_le16(act);
1512 led->duration = cpu_to_le16(1000);
b92f30d6 1513 priv->tx(dev, skb, 1);
eff1a59c
MW		 1514 return 0;
1515}
1516
3330d7be 1517#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW		 1518do { \
1519 queue.aifs = cpu_to_le16(ai_fs); \
1520 queue.cwmin = cpu_to_le16(cw_min); \
1521 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 1522 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW		 1523} while(0)
1524
0fdd7c5d 1525static int p54_set_edcf(struct ieee80211_hw *dev)
eff1a59c
MW		 1526{
1527 struct p54_common *priv = dev->priv;
b92f30d6 1528 struct sk_buff *skb;
0fdd7c5d 1529 struct p54_edcf *edcf;
eff1a59c 1530
27df605e
JL		 1531 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*edcf) +
1532 sizeof(struct p54_hdr), P54_CONTROL_TYPE_DCFINIT,
1533 GFP_ATOMIC);
b92f30d6 1534 if (!skb)
0fdd7c5d
CL		 1535 return -ENOMEM;
1536
b92f30d6 1537 edcf = (struct p54_edcf *)skb_put(skb, sizeof(*edcf));
40333e4f 1538 if (priv->use_short_slot) {
0fdd7c5d
CL		 1539 edcf->slottime = 9;
1540 edcf->sifs = 0x10;
1541 edcf->eofpad = 0x00;
eff1a59c 1542 } else {
0fdd7c5d
CL		 1543 edcf->slottime = 20;
1544 edcf->sifs = 0x0a;
1545 edcf->eofpad = 0x06;
eff1a59c 1546 }
eff1a59c 1547 /* (see prism54/isl_oid.h for further details) */
0fdd7c5d
CL		 1548 edcf->frameburst = cpu_to_le16(0);
1549 edcf->round_trip_delay = cpu_to_le16(0);
9483407d 1550 edcf->flags = 0;
0fdd7c5d
CL		 1551 memset(edcf->mapping, 0, sizeof(edcf->mapping));
1552 memcpy(edcf->queue, priv->qos_params, sizeof(edcf->queue));
b92f30d6 1553 priv->tx(dev, skb, 1);
0fdd7c5d 1554 return 0;
eff1a59c
MW		 1555}
1556
0f1be978 1557static int p54_init_stats(struct ieee80211_hw *dev)
4150c572
JB		 1558{
1559 struct p54_common *priv = dev->priv;
cc6de669 1560
27df605e
JL		 1561 priv->cached_stats = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL,
1562 sizeof(struct p54_hdr) + sizeof(struct p54_statistics),
1563 P54_CONTROL_TYPE_STAT_READBACK, GFP_KERNEL);
0f1be978 1564 if (!priv->cached_stats)
cc6de669 1565 return -ENOMEM;
0f1be978 1566
0f1be978
CL		 1567 mod_timer(&priv->stats_timer, jiffies + HZ);
1568 return 0;
1569}
1570
e5ea92a7
CL		 1571static int p54_beacon_tim(struct sk_buff *skb)
1572{
1573 /*
1574 * the good excuse for this mess is ... the firmware.
1575 * The dummy TIM MUST be at the end of the beacon frame,
1576 * because it'll be overwritten!
1577 */
1578
1579 struct ieee80211_mgmt *mgmt = (void *)skb->data;
1580 u8 *pos, *end;
1581
02e37ba1 1582 if (skb->len <= sizeof(mgmt))
e5ea92a7 1583 return -EINVAL;
e5ea92a7
CL		 1584
1585 pos = (u8 *)mgmt->u.beacon.variable;
1586 end = skb->data + skb->len;
1587 while (pos < end) {
02e37ba1 1588 if (pos + 2 + pos[1] > end)
e5ea92a7 1589 return -EINVAL;
e5ea92a7
CL		 1590
1591 if (pos[0] == WLAN_EID_TIM) {
1592 u8 dtim_len = pos[1];
1593 u8 dtim_period = pos[3];
1594 u8 *next = pos + 2 + dtim_len;
1595
02e37ba1 1596 if (dtim_len < 3)
e5ea92a7 1597 return -EINVAL;
02e37ba1 1598
e5ea92a7
CL		 1599 memmove(pos, next, end - next);
1600
1601 if (dtim_len > 3)
1602 skb_trim(skb, skb->len - (dtim_len - 3));
1603
1604 pos = end - (dtim_len + 2);
1605
1606 /* add the dummy at the end */
1607 pos[0] = WLAN_EID_TIM;
1608 pos[1] = 3;
1609 pos[2] = 0;
1610 pos[3] = dtim_period;
1611 pos[4] = 0;
1612 return 0;
1613 }
1614 pos += 2 + pos[1];
1615 }
1616 return 0;
1617}
1618
1619static int p54_beacon_update(struct ieee80211_hw *dev,
1620 struct ieee80211_vif *vif)
1621{
1622 struct p54_common *priv = dev->priv;
1623 struct sk_buff *beacon;
1624 int ret;
1625
1626 if (priv->cached_beacon) {
1627 p54_tx_cancel(dev, priv->cached_beacon);
1628 /* wait for the last beacon the be freed */
1629 msleep(10);
1630 }
1631
1632 beacon = ieee80211_beacon_get(dev, vif);
1633 if (!beacon)
1634 return -ENOMEM;
1635 ret = p54_beacon_tim(beacon);
1636 if (ret)
1637 return ret;
1638 ret = p54_tx(dev, beacon);
1639 if (ret)
1640 return ret;
1641 priv->cached_beacon = beacon;
1642 priv->tsf_high32 = 0;
1643 priv->tsf_low32 = 0;
1644
1645 return 0;
1646}
1647
0f1be978
CL		 1648static int p54_start(struct ieee80211_hw *dev)
1649{
1650 struct p54_common *priv = dev->priv;
1651 int err;
cc6de669 1652
9e7f3f8e 1653 mutex_lock(&priv->conf_mutex);
4150c572 1654 err = priv->open(dev);
40db0b22
CL		 1655 if (err)
1656 goto out;
0fdd7c5d
CL		 1657 P54_SET_QUEUE(priv->qos_params[0], 0x0002, 0x0003, 0x0007, 47);
1658 P54_SET_QUEUE(priv->qos_params[1], 0x0002, 0x0007, 0x000f, 94);
1659 P54_SET_QUEUE(priv->qos_params[2], 0x0003, 0x000f, 0x03ff, 0);
1660 P54_SET_QUEUE(priv->qos_params[3], 0x0007, 0x000f, 0x03ff, 0);
1661 err = p54_set_edcf(dev);
40db0b22
CL		 1662 if (err)
1663 goto out;
1664 err = p54_init_stats(dev);
1665 if (err)
1666 goto out;
b2023ddc
CL		 1667
1668 memset(priv->bssid, ~0, ETH_ALEN);
40db0b22 1669 priv->mode = NL80211_IFTYPE_MONITOR;
b2023ddc
CL		 1670 err = p54_setup_mac(dev);
1671 if (err) {
1672 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1673 goto out;
1674 }
4150c572 1675
40db0b22 1676out:
9e7f3f8e 1677 mutex_unlock(&priv->conf_mutex);
4150c572
JB		 1678 return err;
1679}
1680
1681static void p54_stop(struct ieee80211_hw *dev)
1682{
1683 struct p54_common *priv = dev->priv;
1684 struct sk_buff *skb;
cc6de669 1685
9e7f3f8e 1686 mutex_lock(&priv->conf_mutex);
cc6de669 1687 del_timer(&priv->stats_timer);
b92f30d6 1688 p54_free_skb(dev, priv->cached_stats);
0f1be978 1689 priv->cached_stats = NULL;
e5ea92a7
CL		 1690 if (priv->cached_beacon)
1691 p54_tx_cancel(dev, priv->cached_beacon);
1692
e039fa4a 1693 while ((skb = skb_dequeue(&priv->tx_queue)))
4150c572 1694 kfree_skb(skb);
b92f30d6 1695
e5ea92a7 1696 priv->cached_beacon = NULL;
4150c572 1697 priv->stop(dev);
a0db663f 1698 priv->tsf_high32 = priv->tsf_low32 = 0;
05c914fe 1699 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
9e7f3f8e 1700 mutex_unlock(&priv->conf_mutex);
4150c572
JB		 1701}
1702
eff1a59c
MW		 1703static int p54_add_interface(struct ieee80211_hw *dev,
1704 struct ieee80211_if_init_conf *conf)
1705{
1706 struct p54_common *priv = dev->priv;
eff1a59c 1707
9e7f3f8e
CL		 1708 mutex_lock(&priv->conf_mutex);
1709 if (priv->mode != NL80211_IFTYPE_MONITOR) {
1710 mutex_unlock(&priv->conf_mutex);
4150c572 1711 return -EOPNOTSUPP;
9e7f3f8e 1712 }
eff1a59c
MW		 1713
1714 switch (conf->type) {
05c914fe 1715 case NL80211_IFTYPE_STATION:
e5ea92a7
CL		 1716 case NL80211_IFTYPE_ADHOC:
1717 case NL80211_IFTYPE_AP:
d131bb59 1718 case NL80211_IFTYPE_MESH_POINT:
eff1a59c
MW		 1719 priv->mode = conf->type;
1720 break;
1721 default:
9e7f3f8e 1722 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1723 return -EOPNOTSUPP;
1724 }
1725
4150c572 1726 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
b2023ddc 1727 p54_setup_mac(dev);
eff1a59c 1728 p54_set_leds(dev, 1, 0, 0);
9e7f3f8e 1729 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1730 return 0;
1731}
1732
1733static void p54_remove_interface(struct ieee80211_hw *dev,
1734 struct ieee80211_if_init_conf *conf)
1735{
1736 struct p54_common *priv = dev->priv;
9e7f3f8e
CL		 1737
1738 mutex_lock(&priv->conf_mutex);
e5ea92a7
CL		 1739 if (priv->cached_beacon)
1740 p54_tx_cancel(dev, priv->cached_beacon);
05c914fe 1741 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 1742 memset(priv->mac_addr, 0, ETH_ALEN);
b2023ddc
CL		 1743 memset(priv->bssid, 0, ETH_ALEN);
1744 p54_setup_mac(dev);
9e7f3f8e 1745 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1746}
1747
e8975581 1748static int p54_config(struct ieee80211_hw *dev, u32 changed)
eff1a59c
MW		 1749{
1750 int ret;
6041e2a0 1751 struct p54_common *priv = dev->priv;
e8975581 1752 struct ieee80211_conf *conf = &dev->conf;
eff1a59c 1753
6041e2a0 1754 mutex_lock(&priv->conf_mutex);
b2023ddc
CL		 1755 if (changed & IEEE80211_CONF_CHANGE_POWER)
1756 priv->output_power = conf->power_level << 2;
1757 if (changed & IEEE80211_CONF_CHANGE_RADIO_ENABLED) {
1758 ret = p54_setup_mac(dev);
1759 if (ret)
1760 goto out;
1761 }
1762 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
1763 ret = p54_scan(dev, P54_SCAN_EXIT, 0,
1764 conf->channel->center_freq);
1765 if (ret)
1766 goto out;
1767 }
1768
1769out:
6041e2a0 1770 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1771 return ret;
1772}
1773
32bfd35d
JB		 1774static int p54_config_interface(struct ieee80211_hw *dev,
1775 struct ieee80211_vif *vif,
eff1a59c
MW		 1776 struct ieee80211_if_conf *conf)
1777{
1778 struct p54_common *priv = dev->priv;
e5ea92a7 1779 int ret = 0;
eff1a59c 1780
6041e2a0 1781 mutex_lock(&priv->conf_mutex);
b2023ddc
CL		 1782 if (conf->changed & IEEE80211_IFCC_BSSID) {
1783 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1784 ret = p54_setup_mac(dev);
e5ea92a7
CL		 1785 if (ret)
1786 goto out;
b2023ddc
CL		 1787 }
1788
1789 if (conf->changed & IEEE80211_IFCC_BEACON) {
1790 ret = p54_scan(dev, P54_SCAN_EXIT, 0,
1791 dev->conf.channel->center_freq);
e5ea92a7
CL		 1792 if (ret)
1793 goto out;
b2023ddc 1794 ret = p54_setup_mac(dev);
e5ea92a7
CL		 1795 if (ret)
1796 goto out;
b2023ddc
CL		 1797 ret = p54_beacon_update(dev, vif);
1798 if (ret)
1799 goto out;
1800 ret = p54_set_edcf(dev);
e5ea92a7
CL		 1801 if (ret)
1802 goto out;
e5ea92a7 1803 }
b2023ddc
CL		 1804
1805 ret = p54_set_leds(dev, 1, !is_multicast_ether_addr(priv->bssid), 0);
1806
e5ea92a7 1807out:
6041e2a0 1808 mutex_unlock(&priv->conf_mutex);
e5ea92a7 1809 return ret;
eff1a59c
MW		 1810}
1811
4150c572
JB		 1812static void p54_configure_filter(struct ieee80211_hw *dev,
1813 unsigned int changed_flags,
1814 unsigned int *total_flags,
1815 int mc_count, struct dev_mc_list *mclist)
1816{
1817 struct p54_common *priv = dev->priv;
1818
b2023ddc
CL		 1819 *total_flags &= FIF_PROMISC_IN_BSS |
1820 (*total_flags & FIF_PROMISC_IN_BSS) ?
1821 FIF_FCSFAIL : 0;
78d57eb2
CL		 1822
1823 priv->filter_flags = *total_flags;
4150c572 1824
b2023ddc
CL		 1825 if (changed_flags & FIF_PROMISC_IN_BSS)
1826 p54_setup_mac(dev);
4150c572
JB		 1827}
1828
e100bb64 1829static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW		 1830 const struct ieee80211_tx_queue_params *params)
1831{
1832 struct p54_common *priv = dev->priv;
9e7f3f8e 1833 int ret;
eff1a59c 1834
9e7f3f8e 1835 mutex_lock(&priv->conf_mutex);
3df5ee60 1836 if ((params) && !(queue > 4)) {
0fdd7c5d 1837 P54_SET_QUEUE(priv->qos_params[queue], params->aifs,
3330d7be 1838 params->cw_min, params->cw_max, params->txop);
b50563a6 1839 ret = p54_set_edcf(dev);
eff1a59c 1840 } else
9e7f3f8e 1841 ret = -EINVAL;
9e7f3f8e
CL		 1842 mutex_unlock(&priv->conf_mutex);
1843 return ret;
eff1a59c
MW		 1844}
1845
1b997534
CL		 1846static int p54_init_xbow_synth(struct ieee80211_hw *dev)
1847{
1848 struct p54_common *priv = dev->priv;
b92f30d6 1849 struct sk_buff *skb;
27df605e 1850 struct p54_xbow_synth *xbow;
1b997534 1851
27df605e
JL		 1852 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*xbow) +
1853 sizeof(struct p54_hdr),
1854 P54_CONTROL_TYPE_XBOW_SYNTH_CFG,
b92f30d6
CL		 1855 GFP_KERNEL);
1856 if (!skb)
1b997534
CL		 1857 return -ENOMEM;
1858
27df605e 1859 xbow = (struct p54_xbow_synth *)skb_put(skb, sizeof(*xbow));
1b997534
CL		 1860 xbow->magic1 = cpu_to_le16(0x1);
1861 xbow->magic2 = cpu_to_le16(0x2);
1862 xbow->freq = cpu_to_le16(5390);
b92f30d6
CL		 1863 memset(xbow->padding, 0, sizeof(xbow->padding));
1864 priv->tx(dev, skb, 1);
1b997534
CL		 1865 return 0;
1866}
1867
cc6de669
CL		 1868static void p54_statistics_timer(unsigned long data)
1869{
1870 struct ieee80211_hw *dev = (struct ieee80211_hw *) data;
1871 struct p54_common *priv = dev->priv;
cc6de669
CL		 1872
1873 BUG_ON(!priv->cached_stats);
cc6de669 1874
b92f30d6 1875 priv->tx(dev, priv->cached_stats, 0);
cc6de669
CL		 1876}
1877
eff1a59c
MW		 1878static int p54_get_stats(struct ieee80211_hw *dev,
1879 struct ieee80211_low_level_stats *stats)
1880{
cc6de669
CL		 1881 struct p54_common *priv = dev->priv;
1882
1883 del_timer(&priv->stats_timer);
1884 p54_statistics_timer((unsigned long)dev);
1885
1886 if (!wait_for_completion_interruptible_timeout(&priv->stats_comp, HZ)) {
1887 printk(KERN_ERR "%s: device does not respond!\n",
1888 wiphy_name(dev->wiphy));
1889 return -EBUSY;
1890 }
1891
1892 memcpy(stats, &priv->stats, sizeof(*stats));
1893
eff1a59c
MW		 1894 return 0;
1895}
1896
1897static int p54_get_tx_stats(struct ieee80211_hw *dev,
1898 struct ieee80211_tx_queue_stats *stats)
1899{
1900 struct p54_common *priv = dev->priv;
eff1a59c 1901
84df3ed3 1902 memcpy(stats, &priv->tx_stats[4], sizeof(stats[0]) * dev->queues);
eff1a59c
MW		 1903
1904 return 0;
1905}
1906
40333e4f
CL		 1907static void p54_bss_info_changed(struct ieee80211_hw *dev,
1908 struct ieee80211_vif *vif,
1909 struct ieee80211_bss_conf *info,
1910 u32 changed)
1911{
1912 struct p54_common *priv = dev->priv;
1913
1914 if (changed & BSS_CHANGED_ERP_SLOT) {
1915 priv->use_short_slot = info->use_short_slot;
0fdd7c5d 1916 p54_set_edcf(dev);
40333e4f 1917 }
ced09574
CL		 1918 if (changed & BSS_CHANGED_BASIC_RATES) {
1919 if (dev->conf.channel->band == IEEE80211_BAND_5GHZ)
1920 priv->basic_rate_mask = (info->basic_rates << 4);
1921 else
1922 priv->basic_rate_mask = info->basic_rates;
b2023ddc 1923 p54_setup_mac(dev);
ced09574 1924 if (priv->fw_var >= 0x500)
b2023ddc
CL		 1925 p54_scan(dev, P54_SCAN_EXIT, 0,
1926 dev->conf.channel->center_freq);
ced09574
CL		 1927 }
1928 if (changed & BSS_CHANGED_ASSOC) {
1929 if (info->assoc) {
1930 priv->aid = info->aid;
1931 priv->wakeup_timer = info->beacon_int *
1932 info->dtim_period * 5;
b2023ddc 1933 p54_setup_mac(dev);
ced09574
CL		 1934 }
1935 }
1936
40333e4f
CL		 1937}
1938
25900ef0
CL		 1939static int p54_set_key(struct ieee80211_hw *dev, enum set_key_cmd cmd,
1940 const u8 *local_address, const u8 *address,
1941 struct ieee80211_key_conf *key)
1942{
1943 struct p54_common *priv = dev->priv;
1944 struct sk_buff *skb;
1945 struct p54_keycache *rxkey;
1946 u8 algo = 0;
1947
1948 if (modparam_nohwcrypt)
1949 return -EOPNOTSUPP;
1950
1951 if (cmd == DISABLE_KEY)
1952 algo = 0;
1953 else {
1954 switch (key->alg) {
1955 case ALG_TKIP:
1956 if (!(priv->privacy_caps & (BR_DESC_PRIV_CAP_MICHAEL |
1957 BR_DESC_PRIV_CAP_TKIP)))
1958 return -EOPNOTSUPP;
1959 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1960 algo = P54_CRYPTO_TKIPMICHAEL;
1961 break;
1962 case ALG_WEP:
1963 if (!(priv->privacy_caps & BR_DESC_PRIV_CAP_WEP))
1964 return -EOPNOTSUPP;
1965 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1966 algo = P54_CRYPTO_WEP;
1967 break;
1968 case ALG_CCMP:
1969 if (!(priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP))
1970 return -EOPNOTSUPP;
1971 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1972 algo = P54_CRYPTO_AESCCMP;
1973 break;
1974 default:
1975 return -EINVAL;
1976 }
1977 }
1978
1979 if (key->keyidx > priv->rx_keycache_size) {
1980 /*
1981 * The device supports the choosen algorithm, but the firmware
1982 * does not provide enough key slots to store all of them.
1983 * So, incoming frames have to be decoded by the mac80211 stack,
1984 * but we can still offload encryption for outgoing frames.
1985 */
1986
1987 return 0;
1988 }
1989
1990 mutex_lock(&priv->conf_mutex);
1991 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*rxkey) +
1992 sizeof(struct p54_hdr), P54_CONTROL_TYPE_RX_KEYCACHE,
1993 GFP_ATOMIC);
1994 if (!skb) {
1995 mutex_unlock(&priv->conf_mutex);
1996 return -ENOMEM;
1997 }
1998
1999 /* TODO: some devices have 4 more free slots for rx keys */
2000 rxkey = (struct p54_keycache *)skb_put(skb, sizeof(*rxkey));
2001 rxkey->entry = key->keyidx;
2002 rxkey->key_id = key->keyidx;
2003 rxkey->key_type = algo;
2004 if (address)
2005 memcpy(rxkey->mac, address, ETH_ALEN);
2006 else
2007 memset(rxkey->mac, ~0, ETH_ALEN);
2008 if (key->alg != ALG_TKIP) {
2009 rxkey->key_len = min((u8)16, key->keylen);
2010 memcpy(rxkey->key, key->key, rxkey->key_len);
2011 } else {
2012 rxkey->key_len = 24;
2013 memcpy(rxkey->key, key->key, 16);
2014 memcpy(&(rxkey->key[16]), &(key->key
2015 [NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]), 8);
2016 }
2017
2018 priv->tx(dev, skb, 1);
2019 mutex_unlock(&priv->conf_mutex);
2020 return 0;
2021}
2022
eff1a59c
MW		 2023static const struct ieee80211_ops p54_ops = {
2024 .tx = p54_tx,
4150c572
JB		 2025 .start = p54_start,
2026 .stop = p54_stop,
eff1a59c
MW		 2027 .add_interface = p54_add_interface,
2028 .remove_interface = p54_remove_interface,
e5ea92a7 2029 .set_tim = p54_set_tim,
c772a08b
CL		 2030 .sta_notify_ps = p54_sta_notify_ps,
2031 .sta_notify = p54_sta_notify,
25900ef0 2032 .set_key = p54_set_key,
eff1a59c
MW		 2033 .config = p54_config,
2034 .config_interface = p54_config_interface,
40333e4f 2035 .bss_info_changed = p54_bss_info_changed,
4150c572 2036 .configure_filter = p54_configure_filter,
eff1a59c
MW		 2037 .conf_tx = p54_conf_tx,
2038 .get_stats = p54_get_stats,
2039 .get_tx_stats = p54_get_tx_stats
2040};
2041
2042struct ieee80211_hw *p54_init_common(size_t priv_data_len)
2043{
2044 struct ieee80211_hw *dev;
2045 struct p54_common *priv;
eff1a59c
MW		 2046
2047 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
2048 if (!dev)
2049 return NULL;
2050
2051 priv = dev->priv;
05c914fe 2052 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
ced09574 2053 priv->basic_rate_mask = 0x15f;
eff1a59c 2054 skb_queue_head_init(&priv->tx_queue);
94585b09 2055 dev->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cc6de669
CL		 2056 IEEE80211_HW_SIGNAL_DBM |
2057 IEEE80211_HW_NOISE_DBM;
f59ac048 2058
d131bb59
CL		 2059 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2060 BIT(NL80211_IFTYPE_ADHOC) |
2061 BIT(NL80211_IFTYPE_AP) |
2062 BIT(NL80211_IFTYPE_MESH_POINT);
f59ac048 2063
eff1a59c 2064 dev->channel_change_time = 1000; /* TODO: find actual value */
9e7f3f8e
CL		 2065 priv->tx_stats[0].limit = 1; /* Beacon queue */
2066 priv->tx_stats[1].limit = 1; /* Probe queue for HW scan */
2067 priv->tx_stats[2].limit = 3; /* queue for MLMEs */
2068 priv->tx_stats[3].limit = 3; /* Broadcast / MC queue */
2069 priv->tx_stats[4].limit = 5; /* Data */
eff1a59c 2070 dev->queues = 1;
cc6de669 2071 priv->noise = -94;
c12abae3
JB		 2072 /*
2073 * We support at most 8 tries no matter which rate they're at,
2074 * we cannot support max_rates * max_rate_tries as we set it
2075 * here, but setting it correctly to 4/2 or so would limit us
2076 * artificially if the RC algorithm wants just two rates, so
2077 * let's say 4/7, we'll redistribute it at TX time, see the
2078 * comments there.
2079 */
2080 dev->max_rates = 4;
2081 dev->max_rate_tries = 7;
27df605e
JL		 2082 dev->extra_tx_headroom = sizeof(struct p54_hdr) + 4 +
2083 sizeof(struct p54_tx_data);
eff1a59c 2084
6041e2a0 2085 mutex_init(&priv->conf_mutex);
7cb77072 2086 init_completion(&priv->eeprom_comp);
cc6de669
CL		 2087 init_completion(&priv->stats_comp);
2088 setup_timer(&priv->stats_timer, p54_statistics_timer,
2089 (unsigned long)dev);
eff1a59c 2090
eff1a59c
MW		 2091 return dev;
2092}
2093EXPORT_SYMBOL_GPL(p54_init_common);
2094
2095void p54_free_common(struct ieee80211_hw *dev)
2096{
2097 struct p54_common *priv = dev->priv;
b92f30d6
CL		 2098 del_timer(&priv->stats_timer);
2099 kfree_skb(priv->cached_stats);
eff1a59c
MW		 2100 kfree(priv->iq_autocal);
2101 kfree(priv->output_limit);
2102 kfree(priv->curve_data);
eff1a59c
MW		 2103}
2104EXPORT_SYMBOL_GPL(p54_free_common);
2105
2106static int __init p54_init(void)
2107{
2108 return 0;
2109}
2110
2111static void __exit p54_exit(void)
2112{
2113}
2114
2115module_init(p54_init);
2116module_exit(p54_exit);
Linux 6.x block layer and io_uring tree(s)