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mwl8k: no need to hold ->tx_lock while setting the hardware interrupt mask
[linux-2.6-block.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da
LB		 4 *
5 * Copyright (C) 2008 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/completion.h>
20#include <linux/etherdevice.h>
21#include <net/mac80211.h>
22#include <linux/moduleparam.h>
23#include <linux/firmware.h>
24#include <linux/workqueue.h>
25
26#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
27#define MWL8K_NAME KBUILD_MODNAME
28#define MWL8K_VERSION "0.9.1"
29
30MODULE_DESCRIPTION(MWL8K_DESC);
31MODULE_VERSION(MWL8K_VERSION);
32MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
33MODULE_LICENSE("GPL");
34
35static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
36 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
37 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
38 { }
39};
40MODULE_DEVICE_TABLE(pci, mwl8k_table);
41
a66098da
LB		 42/* Register definitions */
43#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 44#define MWL8K_MODE_STA 0x0000005a
45#define MWL8K_MODE_AP 0x000000a5
a66098da 46#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 47#define MWL8K_FWSTA_READY 0xf0f1f2f4
48#define MWL8K_FWAP_READY 0xf1f2f4a5
49#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 50#define MWL8K_HIU_SCRATCH 0x00000c40
51
52/* Host->device communications */
53#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
54#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
55#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
56#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
57#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 58#define MWL8K_H2A_INT_DUMMY (1 << 20)
59#define MWL8K_H2A_INT_RESET (1 << 15)
60#define MWL8K_H2A_INT_DOORBELL (1 << 1)
61#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 62
63/* Device->host communications */
64#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
65#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
66#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
67#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
68#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 69#define MWL8K_A2H_INT_DUMMY (1 << 20)
70#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
71#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
72#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
73#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
74#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
75#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
76#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
77#define MWL8K_A2H_INT_RX_READY (1 << 1)
78#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 79
80#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
81 MWL8K_A2H_INT_CHNL_SWITCHED | \
82 MWL8K_A2H_INT_QUEUE_EMPTY | \
83 MWL8K_A2H_INT_RADAR_DETECT | \
84 MWL8K_A2H_INT_RADIO_ON | \
85 MWL8K_A2H_INT_RADIO_OFF | \
86 MWL8K_A2H_INT_MAC_EVENT | \
87 MWL8K_A2H_INT_OPC_DONE | \
88 MWL8K_A2H_INT_RX_READY | \
89 MWL8K_A2H_INT_TX_DONE)
90
91/* WME stream classes */
92#define WME_AC_BE 0 /* best effort */
93#define WME_AC_BK 1 /* background */
94#define WME_AC_VI 2 /* video */
95#define WME_AC_VO 3 /* voice */
96
97#define MWL8K_RX_QUEUES 1
98#define MWL8K_TX_QUEUES 4
99
100struct mwl8k_rx_queue {
101 int rx_desc_count;
102
103 /* hw receives here */
104 int rx_head;
105
106 /* refill descs here */
107 int rx_tail;
108
109 struct mwl8k_rx_desc *rx_desc_area;
110 dma_addr_t rx_desc_dma;
111 struct sk_buff **rx_skb;
112};
113
a66098da
LB		 114struct mwl8k_tx_queue {
115 /* hw transmits here */
116 int tx_head;
117
118 /* sw appends here */
119 int tx_tail;
120
121 struct ieee80211_tx_queue_stats tx_stats;
122 struct mwl8k_tx_desc *tx_desc_area;
123 dma_addr_t tx_desc_dma;
76266b2a 124 struct sk_buff **tx_skb;
a66098da
LB		 125};
126
127/* Pointers to the firmware data and meta information about it. */
128struct mwl8k_firmware {
129 /* Microcode */
130 struct firmware *ucode;
131
132 /* Boot helper code */
133 struct firmware *helper;
134};
135
136struct mwl8k_priv {
137 void __iomem *regs;
138 struct ieee80211_hw *hw;
139
140 struct pci_dev *pdev;
141 u8 name[16];
142 /* firmware access lock */
143 spinlock_t fw_lock;
144
145 /* firmware files and meta data */
146 struct mwl8k_firmware fw;
147 u32 part_num;
148
149 /* lock held over TX and TX reap */
150 spinlock_t tx_lock;
a66098da
LB		 151
152 struct ieee80211_vif *vif;
a66098da
LB		 153
154 struct ieee80211_channel *current_channel;
155
156 /* power management status cookie from firmware */
157 u32 *cookie;
158 dma_addr_t cookie_dma;
159
160 u16 num_mcaddrs;
a66098da
LB		 161 u8 hw_rev;
162 __le32 fw_rev;
a66098da
LB		 163
164 /*
165 * Running count of TX packets in flight, to avoid
166 * iterating over the transmit rings each time.
167 */
168 int pending_tx_pkts;
169
170 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
171 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
172
173 /* PHY parameters */
174 struct ieee80211_supported_band band;
175 struct ieee80211_channel channels[14];
176 struct ieee80211_rate rates[12];
177
c46563b7 178 bool radio_on;
68ce3884 179 bool radio_short_preamble;
0439b1f5 180 bool wmm_enabled;
a66098da
LB		 181
182 /* Set if PHY config is in progress */
183 bool inconfig;
184
185 /* XXX need to convert this to handle multiple interfaces */
186 bool capture_beacon;
d89173f2 187 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 188 struct sk_buff *beacon_skb;
189
190 /*
191 * This FJ worker has to be global as it is scheduled from the
192 * RX handler. At this point we don't know which interface it
193 * belongs to until the list of bssids waiting to complete join
194 * is checked.
195 */
196 struct work_struct finalize_join_worker;
197
198 /* Tasklet to reclaim TX descriptors and buffers after tx */
199 struct tasklet_struct tx_reclaim_task;
200
201 /* Work thread to serialize configuration requests */
202 struct workqueue_struct *config_wq;
203 struct completion *hostcmd_wait;
204 struct completion *tx_wait;
205};
206
207/* Per interface specific private data */
208struct mwl8k_vif {
a66098da
LB		 209 /* backpointer to parent config block */
210 struct mwl8k_priv *priv;
211
212 /* BSS config of AP or IBSS from mac80211*/
213 struct ieee80211_bss_conf bss_info;
214
215 /* BSSID of AP or IBSS */
d89173f2
LB		 216 u8 bssid[ETH_ALEN];
217 u8 mac_addr[ETH_ALEN];
a66098da
LB		 218
219 /*
220 * Subset of supported legacy rates.
221 * Intersection of AP and STA supported rates.
222 */
223 struct ieee80211_rate legacy_rates[12];
224
225 /* number of supported legacy rates */
226 u8 legacy_nrates;
227
a66098da
LB		 228 /* Index into station database.Returned by update_sta_db call */
229 u8 peer_id;
230
231 /* Non AMPDU sequence number assigned by driver */
232 u16 seqno;
a66098da
LB		 233};
234
a94cc97e 235#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 236
237static const struct ieee80211_channel mwl8k_channels[] = {
238 { .center_freq = 2412, .hw_value = 1, },
239 { .center_freq = 2417, .hw_value = 2, },
240 { .center_freq = 2422, .hw_value = 3, },
241 { .center_freq = 2427, .hw_value = 4, },
242 { .center_freq = 2432, .hw_value = 5, },
243 { .center_freq = 2437, .hw_value = 6, },
244 { .center_freq = 2442, .hw_value = 7, },
245 { .center_freq = 2447, .hw_value = 8, },
246 { .center_freq = 2452, .hw_value = 9, },
247 { .center_freq = 2457, .hw_value = 10, },
248 { .center_freq = 2462, .hw_value = 11, },
249};
250
251static const struct ieee80211_rate mwl8k_rates[] = {
252 { .bitrate = 10, .hw_value = 2, },
253 { .bitrate = 20, .hw_value = 4, },
254 { .bitrate = 55, .hw_value = 11, },
255 { .bitrate = 60, .hw_value = 12, },
256 { .bitrate = 90, .hw_value = 18, },
257 { .bitrate = 110, .hw_value = 22, },
258 { .bitrate = 120, .hw_value = 24, },
259 { .bitrate = 180, .hw_value = 36, },
260 { .bitrate = 240, .hw_value = 48, },
261 { .bitrate = 360, .hw_value = 72, },
262 { .bitrate = 480, .hw_value = 96, },
263 { .bitrate = 540, .hw_value = 108, },
264};
265
a66098da
LB		 266/* Set or get info from Firmware */
267#define MWL8K_CMD_SET 0x0001
268#define MWL8K_CMD_GET 0x0000
269
270/* Firmware command codes */
271#define MWL8K_CMD_CODE_DNLD 0x0001
272#define MWL8K_CMD_GET_HW_SPEC 0x0003
273#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
274#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 275#define MWL8K_CMD_RADIO_CONTROL 0x001c
276#define MWL8K_CMD_RF_TX_POWER 0x001e
a66098da
LB		 277#define MWL8K_CMD_SET_PRE_SCAN 0x0107
278#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 279#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
280#define MWL8K_CMD_SET_AID 0x010d
281#define MWL8K_CMD_SET_RATE 0x0110
282#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
283#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 284#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 285#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
286#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 287#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 288#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 289#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
a66098da 290#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 291#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 292
293static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
294{
295#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
296 snprintf(buf, bufsize, "%s", #x);\
297 return buf;\
298 } while (0)
ce9e2e1b 299 switch (cmd & ~0x8000) {
a66098da
LB		 300 MWL8K_CMDNAME(CODE_DNLD);
301 MWL8K_CMDNAME(GET_HW_SPEC);
302 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
303 MWL8K_CMDNAME(GET_STAT);
304 MWL8K_CMDNAME(RADIO_CONTROL);
305 MWL8K_CMDNAME(RF_TX_POWER);
306 MWL8K_CMDNAME(SET_PRE_SCAN);
307 MWL8K_CMDNAME(SET_POST_SCAN);
308 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 309 MWL8K_CMDNAME(SET_AID);
310 MWL8K_CMDNAME(SET_RATE);
311 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
312 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 313 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 314 MWL8K_CMDNAME(SET_EDCA_PARAMS);
315 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 316 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 317 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 318 MWL8K_CMDNAME(ENABLE_SNIFFER);
a66098da 319 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 320 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 321 default:
322 snprintf(buf, bufsize, "0x%x", cmd);
323 }
324#undef MWL8K_CMDNAME
325
326 return buf;
327}
328
329/* Hardware and firmware reset */
330static void mwl8k_hw_reset(struct mwl8k_priv *priv)
331{
332 iowrite32(MWL8K_H2A_INT_RESET,
333 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
334 iowrite32(MWL8K_H2A_INT_RESET,
335 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
336 msleep(20);
337}
338
339/* Release fw image */
340static void mwl8k_release_fw(struct firmware **fw)
341{
342 if (*fw == NULL)
343 return;
344 release_firmware(*fw);
345 *fw = NULL;
346}
347
348static void mwl8k_release_firmware(struct mwl8k_priv *priv)
349{
350 mwl8k_release_fw(&priv->fw.ucode);
351 mwl8k_release_fw(&priv->fw.helper);
352}
353
354/* Request fw image */
355static int mwl8k_request_fw(struct mwl8k_priv *priv,
356 const char *fname, struct firmware **fw)
357{
358 /* release current image */
359 if (*fw != NULL)
360 mwl8k_release_fw(fw);
361
362 return request_firmware((const struct firmware **)fw,
363 fname, &priv->pdev->dev);
364}
365
366static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
367{
368 u8 filename[64];
369 int rc;
370
371 priv->part_num = part_num;
372
373 snprintf(filename, sizeof(filename),
374 "mwl8k/helper_%u.fw", priv->part_num);
375
376 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
377 if (rc) {
378 printk(KERN_ERR
379 "%s Error requesting helper firmware file %s\n",
380 pci_name(priv->pdev), filename);
381 return rc;
382 }
383
384 snprintf(filename, sizeof(filename),
385 "mwl8k/fmimage_%u.fw", priv->part_num);
386
387 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
388 if (rc) {
389 printk(KERN_ERR "%s Error requesting firmware file %s\n",
390 pci_name(priv->pdev), filename);
391 mwl8k_release_fw(&priv->fw.helper);
392 return rc;
393 }
394
395 return 0;
396}
397
398struct mwl8k_cmd_pkt {
399 __le16 code;
400 __le16 length;
401 __le16 seq_num;
402 __le16 result;
403 char payload[0];
404} __attribute__((packed));
405
406/*
407 * Firmware loading.
408 */
409static int
410mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
411{
412 void __iomem *regs = priv->regs;
413 dma_addr_t dma_addr;
a66098da
LB		 414 int loops;
415
416 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
417 if (pci_dma_mapping_error(priv->pdev, dma_addr))
418 return -ENOMEM;
419
420 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
421 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
422 iowrite32(MWL8K_H2A_INT_DOORBELL,
423 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
424 iowrite32(MWL8K_H2A_INT_DUMMY,
425 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
426
a66098da
LB		 427 loops = 1000;
428 do {
429 u32 int_code;
430
431 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
432 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
433 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 434 break;
435 }
436
437 udelay(1);
438 } while (--loops);
439
440 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
441
d4b70570 442 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 443}
444
445static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
446 const u8 *data, size_t length)
447{
448 struct mwl8k_cmd_pkt *cmd;
449 int done;
450 int rc = 0;
451
452 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
453 if (cmd == NULL)
454 return -ENOMEM;
455
456 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
457 cmd->seq_num = 0;
458 cmd->result = 0;
459
460 done = 0;
461 while (length) {
462 int block_size = length > 256 ? 256 : length;
463
464 memcpy(cmd->payload, data + done, block_size);
465 cmd->length = cpu_to_le16(block_size);
466
467 rc = mwl8k_send_fw_load_cmd(priv, cmd,
468 sizeof(*cmd) + block_size);
469 if (rc)
470 break;
471
472 done += block_size;
473 length -= block_size;
474 }
475
476 if (!rc) {
477 cmd->length = 0;
478 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
479 }
480
481 kfree(cmd);
482
483 return rc;
484}
485
486static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
487 const u8 *data, size_t length)
488{
489 unsigned char *buffer;
490 int may_continue, rc = 0;
491 u32 done, prev_block_size;
492
493 buffer = kmalloc(1024, GFP_KERNEL);
494 if (buffer == NULL)
495 return -ENOMEM;
496
497 done = 0;
498 prev_block_size = 0;
499 may_continue = 1000;
500 while (may_continue > 0) {
501 u32 block_size;
502
503 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
504 if (block_size & 1) {
505 block_size &= ~1;
506 may_continue--;
507 } else {
508 done += prev_block_size;
509 length -= prev_block_size;
510 }
511
512 if (block_size > 1024 || block_size > length) {
513 rc = -EOVERFLOW;
514 break;
515 }
516
517 if (length == 0) {
518 rc = 0;
519 break;
520 }
521
522 if (block_size == 0) {
523 rc = -EPROTO;
524 may_continue--;
525 udelay(1);
526 continue;
527 }
528
529 prev_block_size = block_size;
530 memcpy(buffer, data + done, block_size);
531
532 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
533 if (rc)
534 break;
535 }
536
537 if (!rc && length != 0)
538 rc = -EREMOTEIO;
539
540 kfree(buffer);
541
542 return rc;
543}
544
545static int mwl8k_load_firmware(struct mwl8k_priv *priv)
546{
547 int loops, rc;
548
549 const u8 *ucode = priv->fw.ucode->data;
550 size_t ucode_len = priv->fw.ucode->size;
551 const u8 *helper = priv->fw.helper->data;
552 size_t helper_len = priv->fw.helper->size;
553
554 if (!memcmp(ucode, "\x01\x00\x00\x00", 4)) {
555 rc = mwl8k_load_fw_image(priv, helper, helper_len);
556 if (rc) {
557 printk(KERN_ERR "%s: unable to load firmware "
558 "helper image\n", pci_name(priv->pdev));
559 return rc;
560 }
561 msleep(1);
562
563 rc = mwl8k_feed_fw_image(priv, ucode, ucode_len);
564 } else {
565 rc = mwl8k_load_fw_image(priv, ucode, ucode_len);
566 }
567
568 if (rc) {
569 printk(KERN_ERR "%s: unable to load firmware data\n",
570 pci_name(priv->pdev));
571 return rc;
572 }
573
574 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
575 msleep(1);
576
577 loops = 200000;
578 do {
579 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
580 == MWL8K_FWSTA_READY)
581 break;
582 udelay(1);
583 } while (--loops);
584
585 return loops ? 0 : -ETIMEDOUT;
586}
587
588
589/*
590 * Defines shared between transmission and reception.
591 */
592/* HT control fields for firmware */
593struct ewc_ht_info {
594 __le16 control1;
595 __le16 control2;
596 __le16 control3;
597} __attribute__((packed));
598
599/* Firmware Station database operations */
600#define MWL8K_STA_DB_ADD_ENTRY 0
601#define MWL8K_STA_DB_MODIFY_ENTRY 1
602#define MWL8K_STA_DB_DEL_ENTRY 2
603#define MWL8K_STA_DB_FLUSH 3
604
605/* Peer Entry flags - used to define the type of the peer node */
606#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da
LB		 607
608#define MWL8K_IEEE_LEGACY_DATA_RATES 12
609#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 610
611struct peer_capability_info {
612 /* Peer type - AP vs. STA. */
613 __u8 peer_type;
614
615 /* Basic 802.11 capabilities from assoc resp. */
616 __le16 basic_caps;
617
618 /* Set if peer supports 802.11n high throughput (HT). */
619 __u8 ht_support;
620
621 /* Valid if HT is supported. */
622 __le16 ht_caps;
623 __u8 extended_ht_caps;
624 struct ewc_ht_info ewc_info;
625
626 /* Legacy rate table. Intersection of our rates and peer rates. */
627 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
628
629 /* HT rate table. Intersection of our rates and peer rates. */
630 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 631 __u8 pad[16];
a66098da
LB		 632
633 /* If set, interoperability mode, no proprietary extensions. */
634 __u8 interop;
635 __u8 pad2;
636 __u8 station_id;
637 __le16 amsdu_enabled;
638} __attribute__((packed));
639
640/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 641static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
642{
643 u16 val_mask = 1 << 4;
644
645 /* End of Service Period Bit 4 */
646 return qos | val_mask;
647}
648
649static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
650{
651 u16 val_mask = 0x3;
652 u8 shift = 5;
653 u16 qos_mask = ~(val_mask << shift);
654
655 /* Ack Policy Bit 5-6 */
656 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
657}
658
659static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
660{
661 u16 val_mask = 1 << 7;
662
663 /* AMSDU present Bit 7 */
664 return qos | val_mask;
665}
666
667static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
668{
669 u16 val_mask = 0xff;
670 u8 shift = 8;
671 u16 qos_mask = ~(val_mask << shift);
672
673 /* Queue Length Bits 8-15 */
674 return (qos & qos_mask) | ((len & val_mask) << shift);
675}
676
677/* DMA header used by firmware and hardware. */
678struct mwl8k_dma_data {
679 __le16 fwlen;
680 struct ieee80211_hdr wh;
681} __attribute__((packed));
682
683/* Routines to add/remove DMA header from skb. */
76266b2a 684static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
a66098da 685{
76266b2a 686 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
a66098da 687 void *dst, *src = &tr->wh;
76266b2a 688 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
a66098da
LB		 689 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
690
691 dst = (void *)tr + space;
692 if (dst != src) {
693 memmove(dst, src, hdrlen);
694 skb_pull(skb, space);
695 }
a66098da
LB		 696}
697
76266b2a 698static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 699{
700 struct ieee80211_hdr *wh;
701 u32 hdrlen, pktlen;
702 struct mwl8k_dma_data *tr;
703
704 wh = (struct ieee80211_hdr *)skb->data;
705 hdrlen = ieee80211_hdrlen(wh->frame_control);
706 pktlen = skb->len;
707
708 /*
709 * Copy up/down the 802.11 header; the firmware requires
710 * we present a 2-byte payload length followed by a
711 * 4-address header (w/o QoS), followed (optionally) by
712 * any WEP/ExtIV header (but only filled in for CCMP).
713 */
714 if (hdrlen != sizeof(struct mwl8k_dma_data))
715 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
716
717 tr = (struct mwl8k_dma_data *)skb->data;
718 if (wh != &tr->wh)
719 memmove(&tr->wh, wh, hdrlen);
720
721 /* Clear addr4 */
d89173f2 722 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 723
724 /*
725 * Firmware length is the length of the fully formed "802.11
726 * payload". That is, everything except for the 802.11 header.
727 * This includes all crypto material including the MIC.
728 */
729 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 730}
731
732
733/*
734 * Packet reception.
735 */
a66098da 736#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
a66098da
LB		 737
738struct mwl8k_rx_desc {
739 __le16 pkt_len;
740 __u8 link_quality;
741 __u8 noise_level;
742 __le32 pkt_phys_addr;
743 __le32 next_rx_desc_phys_addr;
744 __le16 qos_control;
745 __le16 rate_info;
746 __le32 pad0[4];
747 __u8 rssi;
748 __u8 channel;
749 __le16 pad1;
750 __u8 rx_ctrl;
751 __u8 rx_status;
752 __u8 pad2[2];
753} __attribute__((packed));
754
755#define MWL8K_RX_DESCS 256
756#define MWL8K_RX_MAXSZ 3800
757
758static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
759{
760 struct mwl8k_priv *priv = hw->priv;
761 struct mwl8k_rx_queue *rxq = priv->rxq + index;
762 int size;
763 int i;
764
765 rxq->rx_desc_count = 0;
766 rxq->rx_head = 0;
767 rxq->rx_tail = 0;
768
769 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
770
771 rxq->rx_desc_area =
772 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
773 if (rxq->rx_desc_area == NULL) {
774 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
775 priv->name);
776 return -ENOMEM;
777 }
778 memset(rxq->rx_desc_area, 0, size);
779
780 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
781 sizeof(*rxq->rx_skb), GFP_KERNEL);
782 if (rxq->rx_skb == NULL) {
783 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
784 priv->name);
785 pci_free_consistent(priv->pdev, size,
786 rxq->rx_desc_area, rxq->rx_desc_dma);
787 return -ENOMEM;
788 }
789 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
790
791 for (i = 0; i < MWL8K_RX_DESCS; i++) {
792 struct mwl8k_rx_desc *rx_desc;
793 int nexti;
794
795 rx_desc = rxq->rx_desc_area + i;
796 nexti = (i + 1) % MWL8K_RX_DESCS;
797
798 rx_desc->next_rx_desc_phys_addr =
799 cpu_to_le32(rxq->rx_desc_dma
800 + nexti * sizeof(*rx_desc));
c491bf12 801 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
a66098da
LB		 802 }
803
804 return 0;
805}
806
807static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
808{
809 struct mwl8k_priv *priv = hw->priv;
810 struct mwl8k_rx_queue *rxq = priv->rxq + index;
811 int refilled;
812
813 refilled = 0;
814 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
815 struct sk_buff *skb;
816 int rx;
817
818 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
819 if (skb == NULL)
820 break;
821
822 rxq->rx_desc_count++;
823
824 rx = rxq->rx_tail;
825 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
826
827 rxq->rx_desc_area[rx].pkt_phys_addr =
828 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
829 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
830
831 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
832 rxq->rx_skb[rx] = skb;
833 wmb();
834 rxq->rx_desc_area[rx].rx_ctrl = 0;
835
836 refilled++;
837 }
838
839 return refilled;
840}
841
842/* Must be called only when the card's reception is completely halted */
843static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
844{
845 struct mwl8k_priv *priv = hw->priv;
846 struct mwl8k_rx_queue *rxq = priv->rxq + index;
847 int i;
848
849 for (i = 0; i < MWL8K_RX_DESCS; i++) {
850 if (rxq->rx_skb[i] != NULL) {
851 unsigned long addr;
852
853 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
854 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
855 PCI_DMA_FROMDEVICE);
856 kfree_skb(rxq->rx_skb[i]);
857 rxq->rx_skb[i] = NULL;
858 }
859 }
860
861 kfree(rxq->rx_skb);
862 rxq->rx_skb = NULL;
863
864 pci_free_consistent(priv->pdev,
865 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
866 rxq->rx_desc_area, rxq->rx_desc_dma);
867 rxq->rx_desc_area = NULL;
868}
869
870
871/*
872 * Scan a list of BSSIDs to process for finalize join.
873 * Allows for extension to process multiple BSSIDs.
874 */
875static inline int
876mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
877{
878 return priv->capture_beacon &&
879 ieee80211_is_beacon(wh->frame_control) &&
880 !compare_ether_addr(wh->addr3, priv->capture_bssid);
881}
882
883static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
884 struct sk_buff *skb)
885{
886 priv->capture_beacon = false;
d89173f2 887 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 888
889 /*
890 * Use GFP_ATOMIC as rxq_process is called from
891 * the primary interrupt handler, memory allocation call
892 * must not sleep.
893 */
894 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
895 if (priv->beacon_skb != NULL)
896 queue_work(priv->config_wq,
897 &priv->finalize_join_worker);
898}
899
900static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
901{
902 struct mwl8k_priv *priv = hw->priv;
903 struct mwl8k_rx_queue *rxq = priv->rxq + index;
904 int processed;
905
906 processed = 0;
907 while (rxq->rx_desc_count && limit--) {
908 struct mwl8k_rx_desc *rx_desc;
909 struct sk_buff *skb;
910 struct ieee80211_rx_status status;
911 unsigned long addr;
912 struct ieee80211_hdr *wh;
913
914 rx_desc = rxq->rx_desc_area + rxq->rx_head;
915 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
916 break;
917 rmb();
918
919 skb = rxq->rx_skb[rxq->rx_head];
d25f9f13
LB		 920 if (skb == NULL)
921 break;
a66098da
LB		 922 rxq->rx_skb[rxq->rx_head] = NULL;
923
924 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
925 rxq->rx_desc_count--;
926
927 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
928 pci_unmap_single(priv->pdev, addr,
929 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
930
931 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
76266b2a 932 mwl8k_remove_dma_header(skb);
a66098da
LB		 933
934 wh = (struct ieee80211_hdr *)skb->data;
935
936 /*
937 * Check for pending join operation. save a copy of
938 * the beacon and schedule a tasklet to send finalize
939 * join command to the firmware.
940 */
941 if (mwl8k_capture_bssid(priv, wh))
942 mwl8k_save_beacon(priv, skb);
943
944 memset(&status, 0, sizeof(status));
945 status.mactime = 0;
946 status.signal = -rx_desc->rssi;
947 status.noise = -rx_desc->noise_level;
948 status.qual = rx_desc->link_quality;
949 status.antenna = 1;
950 status.rate_idx = 1;
951 status.flag = 0;
952 status.band = IEEE80211_BAND_2GHZ;
953 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
f1d58c25
JB		 954 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
955 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 956
957 processed++;
958 }
959
960 return processed;
961}
962
963
964/*
965 * Packet transmission.
966 */
967
968/* Transmit queue assignment. */
969enum {
970 MWL8K_WME_AC_BK = 0, /* background access */
971 MWL8K_WME_AC_BE = 1, /* best effort access */
972 MWL8K_WME_AC_VI = 2, /* video access */
973 MWL8K_WME_AC_VO = 3, /* voice access */
974};
975
976/* Transmit packet ACK policy */
977#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 978#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
979
980#define GET_TXQ(_ac) (\
981 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
982 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
983 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
984 MWL8K_WME_AC_BE)
985
a66098da
LB		 986#define MWL8K_TXD_STATUS_OK 0x00000001
987#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
988#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
989#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 990#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 991
992struct mwl8k_tx_desc {
993 __le32 status;
994 __u8 data_rate;
995 __u8 tx_priority;
996 __le16 qos_control;
997 __le32 pkt_phys_addr;
998 __le16 pkt_len;
d89173f2 999 __u8 dest_MAC_addr[ETH_ALEN];
a66098da
LB		 1000 __le32 next_tx_desc_phys_addr;
1001 __le32 reserved;
1002 __le16 rate_info;
1003 __u8 peer_id;
1004 __u8 tx_frag_cnt;
1005} __attribute__((packed));
1006
1007#define MWL8K_TX_DESCS 128
1008
1009static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1010{
1011 struct mwl8k_priv *priv = hw->priv;
1012 struct mwl8k_tx_queue *txq = priv->txq + index;
1013 int size;
1014 int i;
1015
ce9e2e1b 1016 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
a66098da
LB		 1017 txq->tx_stats.limit = MWL8K_TX_DESCS;
1018 txq->tx_head = 0;
1019 txq->tx_tail = 0;
1020
1021 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1022
1023 txq->tx_desc_area =
1024 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1025 if (txq->tx_desc_area == NULL) {
1026 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1027 priv->name);
1028 return -ENOMEM;
1029 }
1030 memset(txq->tx_desc_area, 0, size);
1031
1032 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1033 GFP_KERNEL);
1034 if (txq->tx_skb == NULL) {
1035 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1036 priv->name);
1037 pci_free_consistent(priv->pdev, size,
1038 txq->tx_desc_area, txq->tx_desc_dma);
1039 return -ENOMEM;
1040 }
1041 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1042
1043 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1044 struct mwl8k_tx_desc *tx_desc;
1045 int nexti;
1046
1047 tx_desc = txq->tx_desc_area + i;
1048 nexti = (i + 1) % MWL8K_TX_DESCS;
1049
1050 tx_desc->status = 0;
1051 tx_desc->next_tx_desc_phys_addr =
1052 cpu_to_le32(txq->tx_desc_dma +
1053 nexti * sizeof(*tx_desc));
1054 }
1055
1056 return 0;
1057}
1058
1059static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1060{
1061 iowrite32(MWL8K_H2A_INT_PPA_READY,
1062 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1063 iowrite32(MWL8K_H2A_INT_DUMMY,
1064 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1065 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1066}
1067
1068static inline int mwl8k_txq_busy(struct mwl8k_priv *priv)
1069{
1070 return priv->pending_tx_pkts;
1071}
1072
1073struct mwl8k_txq_info {
1074 u32 fw_owned;
1075 u32 drv_owned;
1076 u32 unused;
1077 u32 len;
1078 u32 head;
1079 u32 tail;
1080};
1081
1082static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1083 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1084{
1085 int count, desc, status;
1086 struct mwl8k_tx_queue *txq;
1087 struct mwl8k_tx_desc *tx_desc;
1088 int ndescs = 0;
1089
c3f967d3
LB		 1090 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1091
a66098da 1092 spin_lock_bh(&priv->tx_lock);
c3f967d3 1093 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da
LB		 1094 txq = priv->txq + count;
1095 txinfo[count].len = txq->tx_stats.len;
1096 txinfo[count].head = txq->tx_head;
1097 txinfo[count].tail = txq->tx_tail;
1098 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1099 tx_desc = txq->tx_desc_area + desc;
1100 status = le32_to_cpu(tx_desc->status);
1101
1102 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1103 txinfo[count].fw_owned++;
1104 else
1105 txinfo[count].drv_owned++;
1106
1107 if (tx_desc->pkt_len == 0)
1108 txinfo[count].unused++;
1109 }
1110 }
1111 spin_unlock_bh(&priv->tx_lock);
1112
1113 return ndescs;
1114}
1115
1116static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw, u32 delay_ms)
1117{
a66098da
LB		 1118 struct mwl8k_priv *priv = hw->priv;
1119 DECLARE_COMPLETION_ONSTACK(cmd_wait);
ce9e2e1b
LB		 1120 u32 count;
1121 unsigned long timeout;
a66098da
LB		 1122
1123 might_sleep();
1124
1125 if (priv->tx_wait != NULL)
1126 printk(KERN_ERR "WARNING Previous TXWaitEmpty instance\n");
1127
1128 spin_lock_bh(&priv->tx_lock);
1129 count = mwl8k_txq_busy(priv);
1130 if (count) {
1131 priv->tx_wait = &cmd_wait;
c46563b7 1132 if (priv->radio_on)
a66098da
LB		 1133 mwl8k_tx_start(priv);
1134 }
1135 spin_unlock_bh(&priv->tx_lock);
1136
1137 if (count) {
c3f967d3 1138 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1139 int index;
1140 int newcount;
1141
1142 timeout = wait_for_completion_timeout(&cmd_wait,
1143 msecs_to_jiffies(delay_ms));
1144 if (timeout)
1145 return 0;
1146
1147 spin_lock_bh(&priv->tx_lock);
1148 priv->tx_wait = NULL;
1149 newcount = mwl8k_txq_busy(priv);
1150 spin_unlock_bh(&priv->tx_lock);
1151
1152 printk(KERN_ERR "%s(%u) TIMEDOUT:%ums Pend:%u-->%u\n",
1153 __func__, __LINE__, delay_ms, count, newcount);
1154
c3f967d3
LB		 1155 mwl8k_scan_tx_ring(priv, txinfo);
1156 for (index = 0; index < MWL8K_TX_QUEUES; index++)
a66098da
LB		 1157 printk(KERN_ERR
1158 "TXQ:%u L:%u H:%u T:%u FW:%u DRV:%u U:%u\n",
1159 index,
1160 txinfo[index].len,
1161 txinfo[index].head,
1162 txinfo[index].tail,
1163 txinfo[index].fw_owned,
1164 txinfo[index].drv_owned,
1165 txinfo[index].unused);
ce9e2e1b 1166
a66098da
LB		 1167 return -ETIMEDOUT;
1168 }
1169
1170 return 0;
1171}
1172
c23b5a69
LB		 1173#define MWL8K_TXD_SUCCESS(status) \
1174 ((status) & (MWL8K_TXD_STATUS_OK | \
1175 MWL8K_TXD_STATUS_OK_RETRY | \
1176 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1177
1178static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1179{
1180 struct mwl8k_priv *priv = hw->priv;
1181 struct mwl8k_tx_queue *txq = priv->txq + index;
1182 int wake = 0;
1183
1184 while (txq->tx_stats.len > 0) {
1185 int tx;
a66098da
LB		 1186 struct mwl8k_tx_desc *tx_desc;
1187 unsigned long addr;
ce9e2e1b 1188 int size;
a66098da
LB		 1189 struct sk_buff *skb;
1190 struct ieee80211_tx_info *info;
1191 u32 status;
1192
a66098da
LB		 1193 tx = txq->tx_head;
1194 tx_desc = txq->tx_desc_area + tx;
1195
1196 status = le32_to_cpu(tx_desc->status);
1197
1198 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1199 if (!force)
1200 break;
1201 tx_desc->status &=
1202 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1203 }
1204
1205 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1206 BUG_ON(txq->tx_stats.len == 0);
1207 txq->tx_stats.len--;
1208 priv->pending_tx_pkts--;
1209
1210 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1211 size = le16_to_cpu(tx_desc->pkt_len);
76266b2a
LB		 1212 skb = txq->tx_skb[tx];
1213 txq->tx_skb[tx] = NULL;
a66098da
LB		 1214
1215 BUG_ON(skb == NULL);
1216 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1217
76266b2a 1218 mwl8k_remove_dma_header(skb);
a66098da
LB		 1219
1220 /* Mark descriptor as unused */
1221 tx_desc->pkt_phys_addr = 0;
1222 tx_desc->pkt_len = 0;
1223
a66098da
LB		 1224 info = IEEE80211_SKB_CB(skb);
1225 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1226 if (MWL8K_TXD_SUCCESS(status))
a66098da 1227 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1228
1229 ieee80211_tx_status_irqsafe(hw, skb);
1230
c46563b7 1231 wake = !priv->inconfig && priv->radio_on;
a66098da
LB		 1232 }
1233
1234 if (wake)
1235 ieee80211_wake_queue(hw, index);
1236}
1237
1238/* must be called only when the card's transmit is completely halted */
1239static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1240{
1241 struct mwl8k_priv *priv = hw->priv;
1242 struct mwl8k_tx_queue *txq = priv->txq + index;
1243
1244 mwl8k_txq_reclaim(hw, index, 1);
1245
1246 kfree(txq->tx_skb);
1247 txq->tx_skb = NULL;
1248
1249 pci_free_consistent(priv->pdev,
1250 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1251 txq->tx_desc_area, txq->tx_desc_dma);
1252 txq->tx_desc_area = NULL;
1253}
1254
1255static int
1256mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1257{
1258 struct mwl8k_priv *priv = hw->priv;
1259 struct ieee80211_tx_info *tx_info;
1260 struct ieee80211_hdr *wh;
1261 struct mwl8k_tx_queue *txq;
1262 struct mwl8k_tx_desc *tx;
1263 struct mwl8k_dma_data *tr;
1264 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1265 dma_addr_t dma;
1266 u16 qos = 0;
1267 bool qosframe = false, ampduframe = false;
1268 bool mcframe = false, eapolframe = false;
1269 bool amsduframe = false;
1270 __le16 fc;
1271
1272 txq = priv->txq + index;
1273 tx = txq->tx_desc_area + txq->tx_tail;
1274
76266b2a 1275 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
a66098da
LB		 1276
1277 /*
76266b2a 1278 * Append HW DMA header to start of packet.
a66098da 1279 */
76266b2a 1280 mwl8k_add_dma_header(skb);
a66098da
LB		 1281
1282 tx_info = IEEE80211_SKB_CB(skb);
1283 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1284 tr = (struct mwl8k_dma_data *)skb->data;
1285 wh = &tr->wh;
1286 fc = wh->frame_control;
1287 qosframe = ieee80211_is_data_qos(fc);
1288 mcframe = is_multicast_ether_addr(wh->addr1);
1289 ampduframe = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1290
1291 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1292 u16 seqno = mwl8k_vif->seqno;
1293 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1294 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1295 mwl8k_vif->seqno = seqno++ % 4096;
1296 }
1297
1298 if (qosframe)
1299 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1300
1301 dma = pci_map_single(priv->pdev, skb->data,
1302 skb->len, PCI_DMA_TODEVICE);
1303
1304 if (pci_dma_mapping_error(priv->pdev, dma)) {
1305 printk(KERN_DEBUG "%s: failed to dma map skb, "
1306 "dropping TX frame.\n", priv->name);
1307
a66098da
LB		 1308 if (skb != NULL)
1309 dev_kfree_skb(skb);
1310 return NETDEV_TX_OK;
1311 }
1312
1313 /* Set desc header, cpu bit order. */
1314 tx->status = 0;
1315 tx->data_rate = 0;
1316 tx->tx_priority = index;
1317 tx->qos_control = 0;
1318 tx->rate_info = 0;
1319 tx->peer_id = mwl8k_vif->peer_id;
1320
1321 amsduframe = !!(qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT);
1322
1323 /* Setup firmware control bit fields for each frame type. */
1324 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
1325 tx->data_rate = 0;
1326 qos = mwl8k_qos_setbit_eosp(qos);
1327 /* Set Queue size to unspecified */
1328 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1329 } else if (ieee80211_is_data(fc)) {
1330 tx->data_rate = 1;
1331 if (mcframe)
1332 tx->status |= MWL8K_TXD_STATUS_MULTICAST_TX;
1333
1334 /*
1335 * Tell firmware to not send EAPOL pkts in an
1336 * aggregate. Verify against mac80211 tx path. If
1337 * stack turns off AMPDU for an EAPOL frame this
1338 * check will be removed.
1339 */
1340 if (eapolframe) {
1341 qos = mwl8k_qos_setbit_ack(qos,
1342 MWL8K_TXD_ACK_POLICY_NORMAL);
1343 } else {
1344 /* Send pkt in an aggregate if AMPDU frame. */
1345 if (ampduframe)
1346 qos = mwl8k_qos_setbit_ack(qos,
1347 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1348 else
1349 qos = mwl8k_qos_setbit_ack(qos,
1350 MWL8K_TXD_ACK_POLICY_NORMAL);
1351
1352 if (amsduframe)
1353 qos = mwl8k_qos_setbit_amsdu(qos);
1354 }
1355 }
1356
1357 /* Convert to little endian */
1358 tx->qos_control = cpu_to_le16(qos);
1359 tx->status = cpu_to_le32(tx->status);
1360 tx->pkt_phys_addr = cpu_to_le32(dma);
1361 tx->pkt_len = cpu_to_le16(skb->len);
1362
76266b2a 1363 txq->tx_skb[txq->tx_tail] = skb;
a66098da
LB		 1364
1365 spin_lock_bh(&priv->tx_lock);
1366
1367 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_OK |
1368 MWL8K_TXD_STATUS_FW_OWNED);
1369 wmb();
1370 txq->tx_stats.len++;
1371 priv->pending_tx_pkts++;
1372 txq->tx_stats.count++;
1373 txq->tx_tail++;
1374
1375 if (txq->tx_tail == MWL8K_TX_DESCS)
1376 txq->tx_tail = 0;
1377 if (txq->tx_head == txq->tx_tail)
1378 ieee80211_stop_queue(hw, index);
1379
1380 if (priv->inconfig) {
1381 /*
1382 * Silently queue packet when we are in the middle of
1383 * a config cycle. Notify firmware only if we are
1384 * waiting for TXQs to empty. If a packet is sent
1385 * before .config() is complete, perhaps it is better
1386 * to drop the packet, as the channel is being changed
1387 * and the packet will end up on the wrong channel.
1388 */
1389 printk(KERN_ERR "%s(): WARNING TX activity while "
1390 "in config\n", __func__);
1391
1392 if (priv->tx_wait != NULL)
1393 mwl8k_tx_start(priv);
1394 } else
1395 mwl8k_tx_start(priv);
1396
1397 spin_unlock_bh(&priv->tx_lock);
1398
1399 return NETDEV_TX_OK;
1400}
1401
1402
1403/*
1404 * Command processing.
1405 */
1406
1407/* Timeout firmware commands after 2000ms */
1408#define MWL8K_CMD_TIMEOUT_MS 2000
1409
1410static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1411{
1412 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1413 struct mwl8k_priv *priv = hw->priv;
1414 void __iomem *regs = priv->regs;
1415 dma_addr_t dma_addr;
1416 unsigned int dma_size;
1417 int rc;
a66098da
LB		 1418 unsigned long timeout = 0;
1419 u8 buf[32];
1420
1421 cmd->result = 0xFFFF;
1422 dma_size = le16_to_cpu(cmd->length);
1423 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1424 PCI_DMA_BIDIRECTIONAL);
1425 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1426 return -ENOMEM;
1427
1428 if (priv->hostcmd_wait != NULL)
1429 printk(KERN_ERR "WARNING host command in progress\n");
1430
1431 spin_lock_irq(&priv->fw_lock);
1432 priv->hostcmd_wait = &cmd_wait;
1433 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1434 iowrite32(MWL8K_H2A_INT_DOORBELL,
1435 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1436 iowrite32(MWL8K_H2A_INT_DUMMY,
1437 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1438 spin_unlock_irq(&priv->fw_lock);
1439
1440 timeout = wait_for_completion_timeout(&cmd_wait,
1441 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1442
37055bd4
LB		 1443 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1444 PCI_DMA_BIDIRECTIONAL);
1445
a66098da
LB		 1446 if (!timeout) {
1447 spin_lock_irq(&priv->fw_lock);
1448 priv->hostcmd_wait = NULL;
1449 spin_unlock_irq(&priv->fw_lock);
1450 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1451 priv->name,
1452 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1453 MWL8K_CMD_TIMEOUT_MS);
1454 rc = -ETIMEDOUT;
1455 } else {
ce9e2e1b 1456 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1457 if (rc)
1458 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1459 priv->name,
1460 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
ce9e2e1b 1461 cmd->result);
a66098da
LB		 1462 }
1463
a66098da
LB		 1464 return rc;
1465}
1466
1467/*
1468 * GET_HW_SPEC.
1469 */
1470struct mwl8k_cmd_get_hw_spec {
1471 struct mwl8k_cmd_pkt header;
1472 __u8 hw_rev;
1473 __u8 host_interface;
1474 __le16 num_mcaddrs;
d89173f2 1475 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1476 __le16 region_code;
1477 __le32 fw_rev;
1478 __le32 ps_cookie;
1479 __le32 caps;
1480 __u8 mcs_bitmap[16];
1481 __le32 rx_queue_ptr;
1482 __le32 num_tx_queues;
1483 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1484 __le32 caps2;
1485 __le32 num_tx_desc_per_queue;
1486 __le32 total_rx_desc;
1487} __attribute__((packed));
1488
1489static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1490{
1491 struct mwl8k_priv *priv = hw->priv;
1492 struct mwl8k_cmd_get_hw_spec *cmd;
1493 int rc;
1494 int i;
1495
1496 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1497 if (cmd == NULL)
1498 return -ENOMEM;
1499
1500 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1501 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1502
1503 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1504 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1505 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
4ff6432e 1506 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da
LB		 1507 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1508 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
4ff6432e
LB		 1509 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1510 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1511
1512 rc = mwl8k_post_cmd(hw, &cmd->header);
1513
1514 if (!rc) {
1515 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1516 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1517 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1518 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1519 }
1520
1521 kfree(cmd);
1522 return rc;
1523}
1524
1525/*
1526 * CMD_MAC_MULTICAST_ADR.
1527 */
1528struct mwl8k_cmd_mac_multicast_adr {
1529 struct mwl8k_cmd_pkt header;
1530 __le16 action;
1531 __le16 numaddr;
ce9e2e1b 1532 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1533};
1534
1535#define MWL8K_ENABLE_RX_MULTICAST 0x000F
ce9e2e1b 1536
e81cd2d6
LB		 1537static struct mwl8k_cmd_pkt *
1538__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1539 int mc_count, struct dev_addr_list *mclist)
a66098da 1540{
e81cd2d6 1541 struct mwl8k_priv *priv = hw->priv;
a66098da 1542 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6
LB		 1543 int size;
1544 int i;
1545
1546 if (mc_count > priv->num_mcaddrs)
1547 mc_count = priv->num_mcaddrs;
1548
1549 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1550
e81cd2d6 1551 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1552 if (cmd == NULL)
e81cd2d6 1553 return NULL;
a66098da
LB		 1554
1555 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1556 cmd->header.length = cpu_to_le16(size);
1557 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1558 cmd->numaddr = cpu_to_le16(mc_count);
ce9e2e1b 1559
e81cd2d6 1560 for (i = 0; i < mc_count && mclist; i++) {
d89173f2 1561 if (mclist->da_addrlen != ETH_ALEN) {
e81cd2d6
LB		 1562 kfree(cmd);
1563 return NULL;
a66098da 1564 }
e81cd2d6 1565 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
a66098da
LB		 1566 mclist = mclist->next;
1567 }
1568
e81cd2d6 1569 return &cmd->header;
a66098da
LB		 1570}
1571
1572/*
1573 * CMD_802_11_GET_STAT.
1574 */
1575struct mwl8k_cmd_802_11_get_stat {
1576 struct mwl8k_cmd_pkt header;
1577 __le16 action;
1578 __le32 stats[64];
1579} __attribute__((packed));
1580
1581#define MWL8K_STAT_ACK_FAILURE 9
1582#define MWL8K_STAT_RTS_FAILURE 12
1583#define MWL8K_STAT_FCS_ERROR 24
1584#define MWL8K_STAT_RTS_SUCCESS 11
1585
1586static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1587 struct ieee80211_low_level_stats *stats)
1588{
1589 struct mwl8k_cmd_802_11_get_stat *cmd;
1590 int rc;
1591
1592 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1593 if (cmd == NULL)
1594 return -ENOMEM;
1595
1596 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1597 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1598 cmd->action = cpu_to_le16(MWL8K_CMD_GET);
1599
1600 rc = mwl8k_post_cmd(hw, &cmd->header);
1601 if (!rc) {
1602 stats->dot11ACKFailureCount =
1603 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1604 stats->dot11RTSFailureCount =
1605 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1606 stats->dot11FCSErrorCount =
1607 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1608 stats->dot11RTSSuccessCount =
1609 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1610 }
1611 kfree(cmd);
1612
1613 return rc;
1614}
1615
1616/*
1617 * CMD_802_11_RADIO_CONTROL.
1618 */
1619struct mwl8k_cmd_802_11_radio_control {
1620 struct mwl8k_cmd_pkt header;
1621 __le16 action;
1622 __le16 control;
1623 __le16 radio_on;
1624} __attribute__((packed));
1625
c46563b7
LB		 1626static int
1627mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1628{
1629 struct mwl8k_priv *priv = hw->priv;
1630 struct mwl8k_cmd_802_11_radio_control *cmd;
1631 int rc;
1632
c46563b7 1633 if (enable == priv->radio_on && !force)
a66098da
LB		 1634 return 0;
1635
a66098da
LB		 1636 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1637 if (cmd == NULL)
1638 return -ENOMEM;
1639
1640 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1641 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1642 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1643 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1644 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1645
1646 rc = mwl8k_post_cmd(hw, &cmd->header);
1647 kfree(cmd);
1648
1649 if (!rc)
c46563b7 1650 priv->radio_on = enable;
a66098da
LB		 1651
1652 return rc;
1653}
1654
c46563b7
LB		 1655static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1656{
1657 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1658}
1659
1660static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1661{
1662 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1663}
1664
a66098da
LB		 1665static int
1666mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1667{
1668 struct mwl8k_priv *priv;
1669
1670 if (hw == NULL || hw->priv == NULL)
1671 return -EINVAL;
1672 priv = hw->priv;
1673
68ce3884 1674 priv->radio_short_preamble = short_preamble;
a66098da 1675
c46563b7 1676 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1677}
1678
1679/*
1680 * CMD_802_11_RF_TX_POWER.
1681 */
1682#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1683
1684struct mwl8k_cmd_802_11_rf_tx_power {
1685 struct mwl8k_cmd_pkt header;
1686 __le16 action;
1687 __le16 support_level;
1688 __le16 current_level;
1689 __le16 reserved;
1690 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1691} __attribute__((packed));
1692
1693static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1694{
1695 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1696 int rc;
1697
1698 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1699 if (cmd == NULL)
1700 return -ENOMEM;
1701
1702 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1703 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1704 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1705 cmd->support_level = cpu_to_le16(dBm);
1706
1707 rc = mwl8k_post_cmd(hw, &cmd->header);
1708 kfree(cmd);
1709
1710 return rc;
1711}
1712
1713/*
1714 * CMD_SET_PRE_SCAN.
1715 */
1716struct mwl8k_cmd_set_pre_scan {
1717 struct mwl8k_cmd_pkt header;
1718} __attribute__((packed));
1719
1720static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1721{
1722 struct mwl8k_cmd_set_pre_scan *cmd;
1723 int rc;
1724
1725 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1726 if (cmd == NULL)
1727 return -ENOMEM;
1728
1729 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1730 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1731
1732 rc = mwl8k_post_cmd(hw, &cmd->header);
1733 kfree(cmd);
1734
1735 return rc;
1736}
1737
1738/*
1739 * CMD_SET_POST_SCAN.
1740 */
1741struct mwl8k_cmd_set_post_scan {
1742 struct mwl8k_cmd_pkt header;
1743 __le32 isibss;
d89173f2 1744 __u8 bssid[ETH_ALEN];
a66098da
LB		 1745} __attribute__((packed));
1746
1747static int
ce9e2e1b 1748mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 1749{
1750 struct mwl8k_cmd_set_post_scan *cmd;
1751 int rc;
1752
1753 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1754 if (cmd == NULL)
1755 return -ENOMEM;
1756
1757 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1758 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1759 cmd->isibss = 0;
d89173f2 1760 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 1761
1762 rc = mwl8k_post_cmd(hw, &cmd->header);
1763 kfree(cmd);
1764
1765 return rc;
1766}
1767
1768/*
1769 * CMD_SET_RF_CHANNEL.
1770 */
1771struct mwl8k_cmd_set_rf_channel {
1772 struct mwl8k_cmd_pkt header;
1773 __le16 action;
1774 __u8 current_channel;
1775 __le32 channel_flags;
1776} __attribute__((packed));
1777
1778static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1779 struct ieee80211_channel *channel)
1780{
1781 struct mwl8k_cmd_set_rf_channel *cmd;
1782 int rc;
1783
1784 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1785 if (cmd == NULL)
1786 return -ENOMEM;
1787
1788 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1789 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1790 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1791 cmd->current_channel = channel->hw_value;
1792 if (channel->band == IEEE80211_BAND_2GHZ)
1793 cmd->channel_flags = cpu_to_le32(0x00000081);
1794 else
1795 cmd->channel_flags = cpu_to_le32(0x00000000);
1796
1797 rc = mwl8k_post_cmd(hw, &cmd->header);
1798 kfree(cmd);
1799
1800 return rc;
1801}
1802
1803/*
1804 * CMD_SET_SLOT.
1805 */
1806struct mwl8k_cmd_set_slot {
1807 struct mwl8k_cmd_pkt header;
1808 __le16 action;
1809 __u8 short_slot;
1810} __attribute__((packed));
1811
5539bb51 1812static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 1813{
1814 struct mwl8k_cmd_set_slot *cmd;
1815 int rc;
1816
1817 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1818 if (cmd == NULL)
1819 return -ENOMEM;
1820
1821 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1822 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1823 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 1824 cmd->short_slot = short_slot_time;
a66098da
LB		 1825
1826 rc = mwl8k_post_cmd(hw, &cmd->header);
1827 kfree(cmd);
1828
1829 return rc;
1830}
1831
1832/*
1833 * CMD_MIMO_CONFIG.
1834 */
1835struct mwl8k_cmd_mimo_config {
1836 struct mwl8k_cmd_pkt header;
1837 __le32 action;
1838 __u8 rx_antenna_map;
1839 __u8 tx_antenna_map;
1840} __attribute__((packed));
1841
1842static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1843{
1844 struct mwl8k_cmd_mimo_config *cmd;
1845 int rc;
1846
1847 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1848 if (cmd == NULL)
1849 return -ENOMEM;
1850
1851 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1852 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1853 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1854 cmd->rx_antenna_map = rx;
1855 cmd->tx_antenna_map = tx;
1856
1857 rc = mwl8k_post_cmd(hw, &cmd->header);
1858 kfree(cmd);
1859
1860 return rc;
1861}
1862
1863/*
1864 * CMD_ENABLE_SNIFFER.
1865 */
1866struct mwl8k_cmd_enable_sniffer {
1867 struct mwl8k_cmd_pkt header;
1868 __le32 action;
1869} __attribute__((packed));
1870
1871static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1872{
1873 struct mwl8k_cmd_enable_sniffer *cmd;
1874 int rc;
1875
1876 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1877 if (cmd == NULL)
1878 return -ENOMEM;
1879
1880 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1881 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 1882 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 1883
1884 rc = mwl8k_post_cmd(hw, &cmd->header);
1885 kfree(cmd);
1886
1887 return rc;
1888}
1889
1890/*
ce9e2e1b 1891 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 1892 */
1893struct mwl8k_cmd_set_rate_adapt_mode {
1894 struct mwl8k_cmd_pkt header;
1895 __le16 action;
1896 __le16 mode;
1897} __attribute__((packed));
1898
1899static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1900{
1901 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1902 int rc;
1903
1904 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1905 if (cmd == NULL)
1906 return -ENOMEM;
1907
1908 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1909 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1910 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1911 cmd->mode = cpu_to_le16(mode);
1912
1913 rc = mwl8k_post_cmd(hw, &cmd->header);
1914 kfree(cmd);
1915
1916 return rc;
1917}
1918
1919/*
1920 * CMD_SET_WMM_MODE.
1921 */
1922struct mwl8k_cmd_set_wmm {
1923 struct mwl8k_cmd_pkt header;
1924 __le16 action;
1925} __attribute__((packed));
1926
1927static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1928{
1929 struct mwl8k_priv *priv = hw->priv;
1930 struct mwl8k_cmd_set_wmm *cmd;
1931 int rc;
1932
1933 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1934 if (cmd == NULL)
1935 return -ENOMEM;
1936
1937 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1938 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 1939 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 1940
1941 rc = mwl8k_post_cmd(hw, &cmd->header);
1942 kfree(cmd);
1943
1944 if (!rc)
0439b1f5 1945 priv->wmm_enabled = enable;
a66098da
LB		 1946
1947 return rc;
1948}
1949
1950/*
1951 * CMD_SET_RTS_THRESHOLD.
1952 */
1953struct mwl8k_cmd_rts_threshold {
1954 struct mwl8k_cmd_pkt header;
1955 __le16 action;
1956 __le16 threshold;
1957} __attribute__((packed));
1958
1959static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
1960 u16 action, u16 *threshold)
1961{
1962 struct mwl8k_cmd_rts_threshold *cmd;
1963 int rc;
1964
1965 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1966 if (cmd == NULL)
1967 return -ENOMEM;
1968
1969 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
1970 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1971 cmd->action = cpu_to_le16(action);
1972 cmd->threshold = cpu_to_le16(*threshold);
1973
1974 rc = mwl8k_post_cmd(hw, &cmd->header);
1975 kfree(cmd);
1976
1977 return rc;
1978}
1979
1980/*
1981 * CMD_SET_EDCA_PARAMS.
1982 */
1983struct mwl8k_cmd_set_edca_params {
1984 struct mwl8k_cmd_pkt header;
1985
1986 /* See MWL8K_SET_EDCA_XXX below */
1987 __le16 action;
1988
1989 /* TX opportunity in units of 32 us */
1990 __le16 txop;
1991
1992 /* Log exponent of max contention period: 0...15*/
1993 __u8 log_cw_max;
1994
1995 /* Log exponent of min contention period: 0...15 */
1996 __u8 log_cw_min;
1997
1998 /* Adaptive interframe spacing in units of 32us */
1999 __u8 aifs;
2000
2001 /* TX queue to configure */
2002 __u8 txq;
2003} __attribute__((packed));
2004
a66098da
LB		 2005#define MWL8K_SET_EDCA_CW 0x01
2006#define MWL8K_SET_EDCA_TXOP 0x02
2007#define MWL8K_SET_EDCA_AIFS 0x04
2008
2009#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2010 MWL8K_SET_EDCA_TXOP | \
2011 MWL8K_SET_EDCA_AIFS)
2012
2013static int
2014mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2015 __u16 cw_min, __u16 cw_max,
2016 __u8 aifs, __u16 txop)
2017{
2018 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2019 int rc;
2020
2021 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2022 if (cmd == NULL)
2023 return -ENOMEM;
2024
a66098da
LB		 2025 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2026 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2027 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2028 cmd->txop = cpu_to_le16(txop);
ce9e2e1b
LB		 2029 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2030 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
a66098da
LB		 2031 cmd->aifs = aifs;
2032 cmd->txq = qnum;
2033
2034 rc = mwl8k_post_cmd(hw, &cmd->header);
2035 kfree(cmd);
2036
2037 return rc;
2038}
2039
2040/*
2041 * CMD_FINALIZE_JOIN.
2042 */
2043
2044/* FJ beacon buffer size is compiled into the firmware. */
2045#define MWL8K_FJ_BEACON_MAXLEN 128
2046
2047struct mwl8k_cmd_finalize_join {
2048 struct mwl8k_cmd_pkt header;
2049 __le32 sleep_interval; /* Number of beacon periods to sleep */
2050 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2051} __attribute__((packed));
2052
2053static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2054 __u16 framelen, __u16 dtim)
2055{
2056 struct mwl8k_cmd_finalize_join *cmd;
2057 struct ieee80211_mgmt *payload = frame;
2058 u16 hdrlen;
2059 u32 payload_len;
2060 int rc;
2061
2062 if (frame == NULL)
2063 return -EINVAL;
2064
2065 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2066 if (cmd == NULL)
2067 return -ENOMEM;
2068
2069 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2070 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2071 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2072
2073 hdrlen = ieee80211_hdrlen(payload->frame_control);
2074
2075 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2076
2077 /* XXX TBD Might just have to abort and return an error */
2078 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2079 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2080 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2081 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2082
ce9e2e1b
LB		 2083 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2084 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2085
2086 if (payload && payload_len)
2087 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2088
2089 rc = mwl8k_post_cmd(hw, &cmd->header);
2090 kfree(cmd);
2091 return rc;
2092}
2093
2094/*
2095 * CMD_UPDATE_STADB.
2096 */
2097struct mwl8k_cmd_update_sta_db {
2098 struct mwl8k_cmd_pkt header;
2099
2100 /* See STADB_ACTION_TYPE */
2101 __le32 action;
2102
2103 /* Peer MAC address */
d89173f2 2104 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2105
2106 __le32 reserved;
2107
2108 /* Peer info - valid during add/update. */
2109 struct peer_capability_info peer_info;
2110} __attribute__((packed));
2111
2112static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2113 struct ieee80211_vif *vif, __u32 action)
2114{
2115 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2116 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2117 struct mwl8k_cmd_update_sta_db *cmd;
2118 struct peer_capability_info *peer_info;
2119 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2120 int rc;
2121 __u8 count, *rates;
2122
2123 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2124 if (cmd == NULL)
2125 return -ENOMEM;
2126
2127 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2128 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2129
2130 cmd->action = cpu_to_le32(action);
2131 peer_info = &cmd->peer_info;
d89173f2 2132 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2133
2134 switch (action) {
2135 case MWL8K_STA_DB_ADD_ENTRY:
2136 case MWL8K_STA_DB_MODIFY_ENTRY:
2137 /* Build peer_info block */
2138 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2139 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2140 peer_info->interop = 1;
2141 peer_info->amsdu_enabled = 0;
2142
2143 rates = peer_info->legacy_rates;
ce9e2e1b 2144 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2145 rates[count] = bitrates[count].hw_value;
2146
2147 rc = mwl8k_post_cmd(hw, &cmd->header);
2148 if (rc == 0)
2149 mv_vif->peer_id = peer_info->station_id;
2150
2151 break;
2152
2153 case MWL8K_STA_DB_DEL_ENTRY:
2154 case MWL8K_STA_DB_FLUSH:
2155 default:
2156 rc = mwl8k_post_cmd(hw, &cmd->header);
2157 if (rc == 0)
2158 mv_vif->peer_id = 0;
2159 break;
2160 }
2161 kfree(cmd);
2162
2163 return rc;
2164}
2165
2166/*
2167 * CMD_SET_AID.
2168 */
a66098da
LB		 2169#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2170
2171#define MWL8K_FRAME_PROT_DISABLED 0x00
2172#define MWL8K_FRAME_PROT_11G 0x07
2173#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2174#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2175
2176struct mwl8k_cmd_update_set_aid {
2177 struct mwl8k_cmd_pkt header;
2178 __le16 aid;
2179
2180 /* AP's MAC address (BSSID) */
d89173f2 2181 __u8 bssid[ETH_ALEN];
a66098da
LB		 2182 __le16 protection_mode;
2183 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2184} __attribute__((packed));
2185
2186static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2187 struct ieee80211_vif *vif)
2188{
2189 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2190 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2191 struct mwl8k_cmd_update_set_aid *cmd;
2192 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2193 int count;
2194 u16 prot_mode;
2195 int rc;
2196
2197 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2198 if (cmd == NULL)
2199 return -ENOMEM;
2200
2201 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2202 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2203 cmd->aid = cpu_to_le16(info->aid);
2204
d89173f2 2205 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2206
a66098da
LB		 2207 if (info->use_cts_prot) {
2208 prot_mode = MWL8K_FRAME_PROT_11G;
2209 } else {
9ed6bcce 2210 switch (info->ht_operation_mode &
a66098da
LB		 2211 IEEE80211_HT_OP_MODE_PROTECTION) {
2212 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2213 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2214 break;
2215 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2216 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2217 break;
2218 default:
2219 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2220 break;
2221 }
2222 }
a66098da
LB		 2223 cmd->protection_mode = cpu_to_le16(prot_mode);
2224
2225 for (count = 0; count < mv_vif->legacy_nrates; count++)
2226 cmd->supp_rates[count] = bitrates[count].hw_value;
2227
2228 rc = mwl8k_post_cmd(hw, &cmd->header);
2229 kfree(cmd);
2230
2231 return rc;
2232}
2233
2234/*
2235 * CMD_SET_RATE.
2236 */
2237struct mwl8k_cmd_update_rateset {
2238 struct mwl8k_cmd_pkt header;
2239 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2240
2241 /* Bitmap for supported MCS codes. */
2242 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2243 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2244} __attribute__((packed));
2245
2246static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2247 struct ieee80211_vif *vif)
2248{
2249 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2250 struct mwl8k_cmd_update_rateset *cmd;
2251 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2252 int count;
2253 int rc;
2254
2255 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2256 if (cmd == NULL)
2257 return -ENOMEM;
2258
2259 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2260 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2261
2262 for (count = 0; count < mv_vif->legacy_nrates; count++)
2263 cmd->legacy_rates[count] = bitrates[count].hw_value;
2264
2265 rc = mwl8k_post_cmd(hw, &cmd->header);
2266 kfree(cmd);
2267
2268 return rc;
2269}
2270
2271/*
2272 * CMD_USE_FIXED_RATE.
2273 */
2274#define MWL8K_RATE_TABLE_SIZE 8
2275#define MWL8K_UCAST_RATE 0
a66098da
LB		 2276#define MWL8K_USE_AUTO_RATE 0x0002
2277
2278struct mwl8k_rate_entry {
2279 /* Set to 1 if HT rate, 0 if legacy. */
2280 __le32 is_ht_rate;
2281
2282 /* Set to 1 to use retry_count field. */
2283 __le32 enable_retry;
2284
2285 /* Specified legacy rate or MCS. */
2286 __le32 rate;
2287
2288 /* Number of allowed retries. */
2289 __le32 retry_count;
2290} __attribute__((packed));
2291
2292struct mwl8k_rate_table {
2293 /* 1 to allow specified rate and below */
2294 __le32 allow_rate_drop;
2295 __le32 num_rates;
2296 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2297} __attribute__((packed));
2298
2299struct mwl8k_cmd_use_fixed_rate {
2300 struct mwl8k_cmd_pkt header;
2301 __le32 action;
2302 struct mwl8k_rate_table rate_table;
2303
2304 /* Unicast, Broadcast or Multicast */
2305 __le32 rate_type;
2306 __le32 reserved1;
2307 __le32 reserved2;
2308} __attribute__((packed));
2309
2310static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2311 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2312{
2313 struct mwl8k_cmd_use_fixed_rate *cmd;
2314 int count;
2315 int rc;
2316
2317 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2318 if (cmd == NULL)
2319 return -ENOMEM;
2320
2321 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2322 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2323
2324 cmd->action = cpu_to_le32(action);
2325 cmd->rate_type = cpu_to_le32(rate_type);
2326
2327 if (rate_table != NULL) {
2328 /* Copy over each field manually so
2329 * that bitflipping can be done
2330 */
2331 cmd->rate_table.allow_rate_drop =
2332 cpu_to_le32(rate_table->allow_rate_drop);
2333 cmd->rate_table.num_rates =
2334 cpu_to_le32(rate_table->num_rates);
2335
2336 for (count = 0; count < rate_table->num_rates; count++) {
2337 struct mwl8k_rate_entry *dst =
2338 &cmd->rate_table.rate_entry[count];
2339 struct mwl8k_rate_entry *src =
2340 &rate_table->rate_entry[count];
2341
2342 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2343 dst->enable_retry = cpu_to_le32(src->enable_retry);
2344 dst->rate = cpu_to_le32(src->rate);
2345 dst->retry_count = cpu_to_le32(src->retry_count);
2346 }
2347 }
2348
2349 rc = mwl8k_post_cmd(hw, &cmd->header);
2350 kfree(cmd);
2351
2352 return rc;
2353}
2354
2355
2356/*
2357 * Interrupt handling.
2358 */
2359static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2360{
2361 struct ieee80211_hw *hw = dev_id;
2362 struct mwl8k_priv *priv = hw->priv;
2363 u32 status;
2364
2365 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2366 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2367
a66098da
LB		 2368 if (!status)
2369 return IRQ_NONE;
2370
2371 if (status & MWL8K_A2H_INT_TX_DONE)
2372 tasklet_schedule(&priv->tx_reclaim_task);
2373
2374 if (status & MWL8K_A2H_INT_RX_READY) {
2375 while (rxq_process(hw, 0, 1))
2376 rxq_refill(hw, 0, 1);
2377 }
2378
2379 if (status & MWL8K_A2H_INT_OPC_DONE) {
2380 if (priv->hostcmd_wait != NULL) {
2381 complete(priv->hostcmd_wait);
2382 priv->hostcmd_wait = NULL;
2383 }
2384 }
2385
2386 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2387 if (!priv->inconfig &&
c46563b7 2388 priv->radio_on &&
a66098da
LB		 2389 mwl8k_txq_busy(priv))
2390 mwl8k_tx_start(priv);
2391 }
2392
2393 return IRQ_HANDLED;
2394}
2395
2396
2397/*
2398 * Core driver operations.
2399 */
2400static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2401{
2402 struct mwl8k_priv *priv = hw->priv;
2403 int index = skb_get_queue_mapping(skb);
2404 int rc;
2405
2406 if (priv->current_channel == NULL) {
2407 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2408 "disabled\n", priv->name);
2409 dev_kfree_skb(skb);
2410 return NETDEV_TX_OK;
2411 }
2412
2413 rc = mwl8k_txq_xmit(hw, index, skb);
2414
2415 return rc;
2416}
2417
2418struct mwl8k_work_struct {
2419 /* Initialized by mwl8k_queue_work(). */
2420 struct work_struct wt;
2421
2422 /* Required field passed in to mwl8k_queue_work(). */
2423 struct ieee80211_hw *hw;
2424
2425 /* Required field passed in to mwl8k_queue_work(). */
2426 int (*wfunc)(struct work_struct *w);
2427
2428 /* Initialized by mwl8k_queue_work(). */
2429 struct completion *cmd_wait;
2430
2431 /* Result code. */
2432 int rc;
2433
2434 /*
2435 * Optional field. Refer to explanation of MWL8K_WQ_XXX_XXX
2436 * flags for explanation. Defaults to MWL8K_WQ_DEFAULT_OPTIONS.
2437 */
2438 u32 options;
2439
2440 /* Optional field. Defaults to MWL8K_CONFIG_TIMEOUT_MS. */
2441 unsigned long timeout_ms;
2442
2443 /* Optional field. Defaults to MWL8K_WQ_TXWAIT_ATTEMPTS. */
2444 u32 txwait_attempts;
2445
2446 /* Optional field. Defaults to MWL8K_TXWAIT_MS. */
2447 u32 tx_timeout_ms;
2448 u32 step;
2449};
2450
2451/* Flags controlling behavior of config queue requests */
2452
2453/* Caller spins while waiting for completion. */
2454#define MWL8K_WQ_SPIN 0x00000001
2455
2456/* Wait for TX queues to empty before proceeding with configuration. */
2457#define MWL8K_WQ_TX_WAIT_EMPTY 0x00000002
2458
2459/* Queue request and return immediately. */
2460#define MWL8K_WQ_POST_REQUEST 0x00000004
2461
2462/*
2463 * Caller sleeps and waits for task complete notification.
2464 * Do not use in atomic context.
2465 */
2466#define MWL8K_WQ_SLEEP 0x00000008
2467
2468/* Free work struct when task is done. */
2469#define MWL8K_WQ_FREE_WORKSTRUCT 0x00000010
2470
2471/*
2472 * Config request is queued and returns to caller imediately. Use
2473 * this in atomic context. Work struct is freed by mwl8k_queue_work()
2474 * when this flag is set.
2475 */
2476#define MWL8K_WQ_QUEUE_ONLY (MWL8K_WQ_POST_REQUEST | \
2477 MWL8K_WQ_FREE_WORKSTRUCT)
2478
2479/* Default work queue behavior is to sleep and wait for tx completion. */
2480#define MWL8K_WQ_DEFAULT_OPTIONS (MWL8K_WQ_SLEEP | MWL8K_WQ_TX_WAIT_EMPTY)
2481
2482/*
2483 * Default config request timeout. Add adjustments to make sure the
2484 * config thread waits long enough for both tx wait and cmd wait before
2485 * timing out.
2486 */
2487
2488/* Time to wait for all TXQs to drain. TX Doorbell is pressed each time. */
2489#define MWL8K_TXWAIT_TIMEOUT_MS 1000
2490
2491/* Default number of TX wait attempts. */
2492#define MWL8K_WQ_TXWAIT_ATTEMPTS 4
2493
2494/* Total time to wait for TXQ to drain. */
2495#define MWL8K_TXWAIT_MS (MWL8K_TXWAIT_TIMEOUT_MS * \
2496 MWL8K_WQ_TXWAIT_ATTEMPTS)
2497
2498/* Scheduling slop. */
2499#define MWL8K_OS_SCHEDULE_OVERHEAD_MS 200
2500
2501#define MWL8K_CONFIG_TIMEOUT_MS (MWL8K_CMD_TIMEOUT_MS + \
2502 MWL8K_TXWAIT_MS + \
2503 MWL8K_OS_SCHEDULE_OVERHEAD_MS)
2504
2505static void mwl8k_config_thread(struct work_struct *wt)
2506{
2507 struct mwl8k_work_struct *worker = (struct mwl8k_work_struct *)wt;
2508 struct ieee80211_hw *hw = worker->hw;
2509 struct mwl8k_priv *priv = hw->priv;
2510 int rc = 0;
2511
2512 spin_lock_irq(&priv->tx_lock);
2513 priv->inconfig = true;
2514 spin_unlock_irq(&priv->tx_lock);
2515
2516 ieee80211_stop_queues(hw);
2517
2518 /*
2519 * Wait for host queues to drain before doing PHY
2520 * reconfiguration. This avoids interrupting any in-flight
2521 * DMA transfers to the hardware.
2522 */
2523 if (worker->options & MWL8K_WQ_TX_WAIT_EMPTY) {
2524 u32 timeout;
2525 u32 time_remaining;
2526 u32 iter;
2527 u32 tx_wait_attempts = worker->txwait_attempts;
2528
2529 time_remaining = worker->tx_timeout_ms;
2530 if (!tx_wait_attempts)
2531 tx_wait_attempts = 1;
2532
2533 timeout = worker->tx_timeout_ms/tx_wait_attempts;
2534 if (!timeout)
2535 timeout = 1;
2536
2537 iter = tx_wait_attempts;
2538 do {
2539 int wait_time;
2540
2541 if (time_remaining > timeout) {
2542 time_remaining -= timeout;
2543 wait_time = timeout;
2544 } else
2545 wait_time = time_remaining;
2546
2547 if (!wait_time)
2548 wait_time = 1;
2549
2550 rc = mwl8k_tx_wait_empty(hw, wait_time);
2551 if (rc)
2552 printk(KERN_ERR "%s() txwait timeout=%ums "
2553 "Retry:%u/%u\n", __func__, timeout,
2554 tx_wait_attempts - iter + 1,
2555 tx_wait_attempts);
2556
2557 } while (rc && --iter);
2558
2559 rc = iter ? 0 : -ETIMEDOUT;
2560 }
2561 if (!rc)
2562 rc = worker->wfunc(wt);
2563
2564 spin_lock_irq(&priv->tx_lock);
2565 priv->inconfig = false;
c46563b7 2566 if (priv->pending_tx_pkts && priv->radio_on)
a66098da
LB		 2567 mwl8k_tx_start(priv);
2568 spin_unlock_irq(&priv->tx_lock);
2569 ieee80211_wake_queues(hw);
2570
2571 worker->rc = rc;
2572 if (worker->options & MWL8K_WQ_SLEEP)
2573 complete(worker->cmd_wait);
2574
2575 if (worker->options & MWL8K_WQ_FREE_WORKSTRUCT)
2576 kfree(wt);
2577}
2578
2579static int mwl8k_queue_work(struct ieee80211_hw *hw,
2580 struct mwl8k_work_struct *worker,
2581 struct workqueue_struct *wqueue,
2582 int (*wfunc)(struct work_struct *w))
2583{
2584 unsigned long timeout = 0;
2585 int rc = 0;
2586
2587 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2588
2589 if (!worker->timeout_ms)
2590 worker->timeout_ms = MWL8K_CONFIG_TIMEOUT_MS;
2591
2592 if (!worker->options)
2593 worker->options = MWL8K_WQ_DEFAULT_OPTIONS;
2594
2595 if (!worker->txwait_attempts)
2596 worker->txwait_attempts = MWL8K_WQ_TXWAIT_ATTEMPTS;
2597
2598 if (!worker->tx_timeout_ms)
2599 worker->tx_timeout_ms = MWL8K_TXWAIT_MS;
2600
2601 worker->hw = hw;
2602 worker->cmd_wait = &cmd_wait;
2603 worker->rc = 1;
2604 worker->wfunc = wfunc;
2605
2606 INIT_WORK(&worker->wt, mwl8k_config_thread);
2607 queue_work(wqueue, &worker->wt);
2608
2609 if (worker->options & MWL8K_WQ_POST_REQUEST) {
2610 rc = 0;
2611 } else {
2612 if (worker->options & MWL8K_WQ_SPIN) {
2613 timeout = worker->timeout_ms;
2614 while (timeout && (worker->rc > 0)) {
2615 mdelay(1);
2616 timeout--;
2617 }
2618 } else if (worker->options & MWL8K_WQ_SLEEP)
2619 timeout = wait_for_completion_timeout(&cmd_wait,
2620 msecs_to_jiffies(worker->timeout_ms));
2621
2622 if (timeout)
2623 rc = worker->rc;
2624 else {
2625 cancel_work_sync(&worker->wt);
2626 rc = -ETIMEDOUT;
2627 }
2628 }
2629
2630 return rc;
2631}
2632
2633struct mwl8k_start_worker {
2634 struct mwl8k_work_struct header;
2635};
2636
2637static int mwl8k_start_wt(struct work_struct *wt)
2638{
2639 struct mwl8k_start_worker *worker = (struct mwl8k_start_worker *)wt;
2640 struct ieee80211_hw *hw = worker->header.hw;
2641 struct mwl8k_priv *priv = hw->priv;
2642 int rc = 0;
2643
2644 if (priv->vif != NULL) {
2645 rc = -EIO;
2646 goto mwl8k_start_exit;
2647 }
2648
2649 /* Turn on radio */
c46563b7 2650 if (mwl8k_cmd_802_11_radio_enable(hw)) {
a66098da
LB		 2651 rc = -EIO;
2652 goto mwl8k_start_exit;
2653 }
2654
2655 /* Purge TX/RX HW queues */
2656 if (mwl8k_cmd_set_pre_scan(hw)) {
2657 rc = -EIO;
2658 goto mwl8k_start_exit;
2659 }
2660
2661 if (mwl8k_cmd_set_post_scan(hw, "\x00\x00\x00\x00\x00\x00")) {
2662 rc = -EIO;
2663 goto mwl8k_start_exit;
2664 }
2665
2666 /* Enable firmware rate adaptation */
2667 if (mwl8k_cmd_setrateadaptmode(hw, 0)) {
2668 rc = -EIO;
2669 goto mwl8k_start_exit;
2670 }
2671
2672 /* Disable WMM. WMM gets enabled when stack sends WMM parms */
0439b1f5 2673 if (mwl8k_set_wmm(hw, 0)) {
a66098da
LB		 2674 rc = -EIO;
2675 goto mwl8k_start_exit;
2676 }
2677
2678 /* Disable sniffer mode */
2679 if (mwl8k_enable_sniffer(hw, 0))
2680 rc = -EIO;
2681
2682mwl8k_start_exit:
2683 return rc;
2684}
2685
2686static int mwl8k_start(struct ieee80211_hw *hw)
2687{
2688 struct mwl8k_start_worker *worker;
2689 struct mwl8k_priv *priv = hw->priv;
2690 int rc;
2691
2692 /* Enable tx reclaim tasklet */
2693 tasklet_enable(&priv->tx_reclaim_task);
2694
2695 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2696 IRQF_SHARED, MWL8K_NAME, hw);
2697 if (rc) {
2698 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2699 priv->name);
2700 rc = -EIO;
2701 goto mwl8k_start_disable_tasklet;
2702 }
2703
2704 /* Enable interrupts */
c23b5a69 2705 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2706
2707 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2708 if (worker == NULL) {
2709 rc = -ENOMEM;
2710 goto mwl8k_start_disable_irq;
2711 }
2712
2713 rc = mwl8k_queue_work(hw, &worker->header,
2714 priv->config_wq, mwl8k_start_wt);
2715 kfree(worker);
2716 if (!rc)
2717 return rc;
2718
2719 if (rc == -ETIMEDOUT)
2720 printk(KERN_ERR "%s() timed out\n", __func__);
2721
2722 rc = -EIO;
2723
2724mwl8k_start_disable_irq:
2725 spin_lock_irq(&priv->tx_lock);
2726 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2727 spin_unlock_irq(&priv->tx_lock);
2728 free_irq(priv->pdev->irq, hw);
2729
2730mwl8k_start_disable_tasklet:
2731 tasklet_disable(&priv->tx_reclaim_task);
2732
2733 return rc;
2734}
2735
2736struct mwl8k_stop_worker {
2737 struct mwl8k_work_struct header;
2738};
2739
2740static int mwl8k_stop_wt(struct work_struct *wt)
2741{
2742 struct mwl8k_stop_worker *worker = (struct mwl8k_stop_worker *)wt;
2743 struct ieee80211_hw *hw = worker->header.hw;
a66098da 2744
c46563b7 2745 return mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2746}
2747
2748static void mwl8k_stop(struct ieee80211_hw *hw)
2749{
2750 int rc;
2751 struct mwl8k_stop_worker *worker;
2752 struct mwl8k_priv *priv = hw->priv;
2753 int i;
2754
2755 if (priv->vif != NULL)
2756 return;
2757
2758 ieee80211_stop_queues(hw);
2759
2760 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2761 if (worker == NULL)
2762 return;
2763
2764 rc = mwl8k_queue_work(hw, &worker->header,
2765 priv->config_wq, mwl8k_stop_wt);
2766 kfree(worker);
2767 if (rc == -ETIMEDOUT)
2768 printk(KERN_ERR "%s() timed out\n", __func__);
2769
2770 /* Disable interrupts */
a66098da 2771 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2772 free_irq(priv->pdev->irq, hw);
2773
2774 /* Stop finalize join worker */
2775 cancel_work_sync(&priv->finalize_join_worker);
2776 if (priv->beacon_skb != NULL)
2777 dev_kfree_skb(priv->beacon_skb);
2778
2779 /* Stop tx reclaim tasklet */
2780 tasklet_disable(&priv->tx_reclaim_task);
2781
2782 /* Stop config thread */
2783 flush_workqueue(priv->config_wq);
2784
2785 /* Return all skbs to mac80211 */
2786 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2787 mwl8k_txq_reclaim(hw, i, 1);
2788}
2789
2790static int mwl8k_add_interface(struct ieee80211_hw *hw,
2791 struct ieee80211_if_init_conf *conf)
2792{
2793 struct mwl8k_priv *priv = hw->priv;
2794 struct mwl8k_vif *mwl8k_vif;
2795
2796 /*
2797 * We only support one active interface at a time.
2798 */
2799 if (priv->vif != NULL)
2800 return -EBUSY;
2801
2802 /*
2803 * We only support managed interfaces for now.
2804 */
240e86ef 2805 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2806 return -EINVAL;
2807
2808 /* Clean out driver private area */
2809 mwl8k_vif = MWL8K_VIF(conf->vif);
2810 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2811
2812 /* Save the mac address */
d89173f2 2813 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2814
2815 /* Back pointer to parent config block */
2816 mwl8k_vif->priv = priv;
2817
2818 /* Setup initial PHY parameters */
ce9e2e1b 2819 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2820 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2821 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2822
2823 /* Set Initial sequence number to zero */
2824 mwl8k_vif->seqno = 0;
2825
2826 priv->vif = conf->vif;
2827 priv->current_channel = NULL;
2828
2829 return 0;
2830}
2831
2832static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2833 struct ieee80211_if_init_conf *conf)
2834{
2835 struct mwl8k_priv *priv = hw->priv;
2836
2837 if (priv->vif == NULL)
2838 return;
2839
2840 priv->vif = NULL;
2841}
2842
2843struct mwl8k_config_worker {
2844 struct mwl8k_work_struct header;
2845 u32 changed;
2846};
2847
2848static int mwl8k_config_wt(struct work_struct *wt)
2849{
2850 struct mwl8k_config_worker *worker =
2851 (struct mwl8k_config_worker *)wt;
2852 struct ieee80211_hw *hw = worker->header.hw;
2853 struct ieee80211_conf *conf = &hw->conf;
2854 struct mwl8k_priv *priv = hw->priv;
2855 int rc = 0;
2856
c46563b7 2857 if (mwl8k_cmd_802_11_radio_enable(hw)) {
a66098da
LB		 2858 rc = -EINVAL;
2859 goto mwl8k_config_exit;
2860 }
2861
2862 priv->current_channel = conf->channel;
2863
2864 if (mwl8k_cmd_set_rf_channel(hw, conf->channel)) {
2865 rc = -EINVAL;
2866 goto mwl8k_config_exit;
2867 }
2868
2869 if (conf->power_level > 18)
2870 conf->power_level = 18;
2871 if (mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level)) {
2872 rc = -EINVAL;
2873 goto mwl8k_config_exit;
2874 }
2875
2876 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2877 rc = -EINVAL;
2878
2879mwl8k_config_exit:
2880 return rc;
2881}
2882
2883static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2884{
2885 int rc = 0;
2886 struct mwl8k_config_worker *worker;
2887 struct mwl8k_priv *priv = hw->priv;
2888
2889 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2890 if (worker == NULL)
2891 return -ENOMEM;
2892
2893 worker->changed = changed;
2894 rc = mwl8k_queue_work(hw, &worker->header,
2895 priv->config_wq, mwl8k_config_wt);
2896 if (rc == -ETIMEDOUT) {
2897 printk(KERN_ERR "%s() timed out.\n", __func__);
2898 rc = -EINVAL;
2899 }
2900
2901 kfree(worker);
2902
2903 /*
2904 * mac80211 will crash on anything other than -EINVAL on
2905 * error. Looks like wireless extensions which calls mac80211
2906 * may be the actual culprit...
2907 */
2908 return rc ? -EINVAL : 0;
2909}
2910
a66098da
LB		 2911struct mwl8k_bss_info_changed_worker {
2912 struct mwl8k_work_struct header;
2913 struct ieee80211_vif *vif;
2914 struct ieee80211_bss_conf *info;
2915 u32 changed;
2916};
2917
2918static int mwl8k_bss_info_changed_wt(struct work_struct *wt)
2919{
2920 struct mwl8k_bss_info_changed_worker *worker =
2921 (struct mwl8k_bss_info_changed_worker *)wt;
2922 struct ieee80211_hw *hw = worker->header.hw;
2923 struct ieee80211_vif *vif = worker->vif;
2924 struct ieee80211_bss_conf *info = worker->info;
2925 u32 changed;
2926 int rc;
2927
2928 struct mwl8k_priv *priv = hw->priv;
2929 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2930
2931 changed = worker->changed;
2932 priv->capture_beacon = false;
2933
2934 if (info->assoc) {
2935 memcpy(&mwl8k_vif->bss_info, info,
2936 sizeof(struct ieee80211_bss_conf));
2937
2938 /* Install rates */
2939 if (mwl8k_update_rateset(hw, vif))
2940 goto mwl8k_bss_info_changed_exit;
2941
2942 /* Turn on rate adaptation */
2943 if (mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2944 MWL8K_UCAST_RATE, NULL))
2945 goto mwl8k_bss_info_changed_exit;
2946
2947 /* Set radio preamble */
68ce3884 2948 if (mwl8k_set_radio_preamble(hw, info->use_short_preamble))
a66098da
LB		 2949 goto mwl8k_bss_info_changed_exit;
2950
2951 /* Set slot time */
5539bb51 2952 if (mwl8k_cmd_set_slot(hw, info->use_short_slot))
a66098da
LB		 2953 goto mwl8k_bss_info_changed_exit;
2954
2955 /* Update peer rate info */
2956 if (mwl8k_cmd_update_sta_db(hw, vif,
2957 MWL8K_STA_DB_MODIFY_ENTRY))
2958 goto mwl8k_bss_info_changed_exit;
2959
2960 /* Set AID */
2961 if (mwl8k_cmd_set_aid(hw, vif))
2962 goto mwl8k_bss_info_changed_exit;
2963
2964 /*
2965 * Finalize the join. Tell rx handler to process
2966 * next beacon from our BSSID.
2967 */
d89173f2 2968 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 2969 priv->capture_beacon = true;
2970 } else {
2971 mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2972 memset(&mwl8k_vif->bss_info, 0,
2973 sizeof(struct ieee80211_bss_conf));
d89173f2 2974 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 2975 }
2976
2977mwl8k_bss_info_changed_exit:
2978 rc = 0;
2979 return rc;
2980}
2981
2982static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2983 struct ieee80211_vif *vif,
2984 struct ieee80211_bss_conf *info,
2985 u32 changed)
2986{
2987 struct mwl8k_bss_info_changed_worker *worker;
2988 struct mwl8k_priv *priv = hw->priv;
2d0ddec5 2989 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
a66098da
LB		 2990 int rc;
2991
2d0ddec5 2992 if (changed & BSS_CHANGED_BSSID)
d89173f2 2993 memcpy(mv_vif->bssid, info->bssid, ETH_ALEN);
2d0ddec5 2994
a66098da
LB		 2995 if ((changed & BSS_CHANGED_ASSOC) == 0)
2996 return;
2997
2998 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2999 if (worker == NULL)
3000 return;
3001
3002 worker->vif = vif;
3003 worker->info = info;
3004 worker->changed = changed;
3005 rc = mwl8k_queue_work(hw, &worker->header,
3006 priv->config_wq,
3007 mwl8k_bss_info_changed_wt);
3008 kfree(worker);
3009 if (rc == -ETIMEDOUT)
3010 printk(KERN_ERR "%s() timed out\n", __func__);
3011}
3012
e81cd2d6
LB		 3013static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3014 int mc_count, struct dev_addr_list *mclist)
3015{
3016 struct mwl8k_cmd_pkt *cmd;
3017
3018 cmd = __mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist);
3019
3020 return (unsigned long)cmd;
3021}
3022
a66098da
LB		 3023struct mwl8k_configure_filter_worker {
3024 struct mwl8k_work_struct header;
3025 unsigned int changed_flags;
e81cd2d6
LB		 3026 unsigned int total_flags;
3027 struct mwl8k_cmd_pkt *multicast_adr_cmd;
a66098da
LB		 3028};
3029
3030#define MWL8K_SUPPORTED_IF_FLAGS FIF_BCN_PRBRESP_PROMISC
3031
3032static int mwl8k_configure_filter_wt(struct work_struct *wt)
3033{
3034 struct mwl8k_configure_filter_worker *worker =
3035 (struct mwl8k_configure_filter_worker *)wt;
a66098da 3036 struct ieee80211_hw *hw = worker->header.hw;
a66098da 3037 struct mwl8k_priv *priv = hw->priv;
a66098da
LB		 3038 int rc = 0;
3039
e81cd2d6
LB		 3040 if (worker->changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3041 if (worker->total_flags & FIF_BCN_PRBRESP_PROMISC)
a66098da
LB		 3042 rc = mwl8k_cmd_set_pre_scan(hw);
3043 else {
a94cc97e
LB		 3044 u8 *bssid;
3045
3046 bssid = "\x00\x00\x00\x00\x00\x00";
3047 if (priv->vif != NULL)
3048 bssid = MWL8K_VIF(priv->vif)->bssid;
3049
3050 rc = mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3051 }
3052 }
3053
e81cd2d6
LB		 3054 if (!rc && worker->multicast_adr_cmd != NULL)
3055 rc = mwl8k_post_cmd(hw, worker->multicast_adr_cmd);
3056 kfree(worker->multicast_adr_cmd);
ce9e2e1b 3057
a66098da
LB		 3058 return rc;
3059}
3060
3061static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3062 unsigned int changed_flags,
3063 unsigned int *total_flags,
3ac64bee 3064 u64 multicast)
a66098da 3065{
a66098da 3066 struct mwl8k_priv *priv = hw->priv;
e81cd2d6 3067 struct mwl8k_configure_filter_worker *worker;
a66098da
LB		 3068
3069 /* Clear unsupported feature flags */
3070 *total_flags &= MWL8K_SUPPORTED_IF_FLAGS;
3071
3ac64bee 3072 if (!(changed_flags & MWL8K_SUPPORTED_IF_FLAGS))
a66098da
LB		 3073 return;
3074
e81cd2d6 3075 worker = kzalloc(sizeof(*worker), GFP_ATOMIC);
a66098da
LB		 3076 if (worker == NULL)
3077 return;
3078
a66098da 3079 worker->changed_flags = changed_flags;
e81cd2d6
LB		 3080 worker->total_flags = *total_flags;
3081 worker->multicast_adr_cmd = (void *)(unsigned long)multicast;
a66098da
LB		 3082
3083 mwl8k_queue_work(hw, &worker->header, priv->config_wq,
3084 mwl8k_configure_filter_wt);
3085}
3086
3087struct mwl8k_set_rts_threshold_worker {
3088 struct mwl8k_work_struct header;
3089 u32 value;
3090};
3091
3092static int mwl8k_set_rts_threshold_wt(struct work_struct *wt)
3093{
3094 struct mwl8k_set_rts_threshold_worker *worker =
3095 (struct mwl8k_set_rts_threshold_worker *)wt;
3096
3097 struct ieee80211_hw *hw = worker->header.hw;
3098 u16 threshold = (u16)(worker->value);
3099 int rc;
3100
3101 rc = mwl8k_rts_threshold(hw, MWL8K_CMD_SET, &threshold);
3102
3103 return rc;
3104}
3105
3106static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3107{
3108 int rc;
3109 struct mwl8k_set_rts_threshold_worker *worker;
3110 struct mwl8k_priv *priv = hw->priv;
3111
3112 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3113 if (worker == NULL)
3114 return -ENOMEM;
3115
3116 worker->value = value;
3117
3118 rc = mwl8k_queue_work(hw, &worker->header,
3119 priv->config_wq,
3120 mwl8k_set_rts_threshold_wt);
3121 kfree(worker);
3122
3123 if (rc == -ETIMEDOUT) {
3124 printk(KERN_ERR "%s() timed out\n", __func__);
3125 rc = -EINVAL;
3126 }
3127
3128 return rc;
3129}
3130
3131struct mwl8k_conf_tx_worker {
3132 struct mwl8k_work_struct header;
3133 u16 queue;
3134 const struct ieee80211_tx_queue_params *params;
3135};
3136
3137static int mwl8k_conf_tx_wt(struct work_struct *wt)
3138{
3139 struct mwl8k_conf_tx_worker *worker =
3140 (struct mwl8k_conf_tx_worker *)wt;
3141
3142 struct ieee80211_hw *hw = worker->header.hw;
3143 u16 queue = worker->queue;
3144 const struct ieee80211_tx_queue_params *params = worker->params;
3145
3146 struct mwl8k_priv *priv = hw->priv;
3147 int rc = 0;
3148
0439b1f5
LB		 3149 if (!priv->wmm_enabled) {
3150 if (mwl8k_set_wmm(hw, 1)) {
a66098da
LB		 3151 rc = -EINVAL;
3152 goto mwl8k_conf_tx_exit;
0439b1f5 3153 }
a66098da
LB		 3154 }
3155
3156 if (mwl8k_set_edca_params(hw, GET_TXQ(queue), params->cw_min,
3157 params->cw_max, params->aifs, params->txop))
3158 rc = -EINVAL;
3159mwl8k_conf_tx_exit:
3160 return rc;
3161}
3162
3163static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3164 const struct ieee80211_tx_queue_params *params)
3165{
3166 int rc;
3167 struct mwl8k_conf_tx_worker *worker;
3168 struct mwl8k_priv *priv = hw->priv;
3169
3170 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3171 if (worker == NULL)
3172 return -ENOMEM;
3173
3174 worker->queue = queue;
3175 worker->params = params;
3176 rc = mwl8k_queue_work(hw, &worker->header,
3177 priv->config_wq, mwl8k_conf_tx_wt);
3178 kfree(worker);
3179 if (rc == -ETIMEDOUT) {
3180 printk(KERN_ERR "%s() timed out\n", __func__);
3181 rc = -EINVAL;
3182 }
3183 return rc;
3184}
3185
3186static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3187 struct ieee80211_tx_queue_stats *stats)
3188{
3189 struct mwl8k_priv *priv = hw->priv;
3190 struct mwl8k_tx_queue *txq;
3191 int index;
3192
3193 spin_lock_bh(&priv->tx_lock);
3194 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3195 txq = priv->txq + index;
3196 memcpy(&stats[index], &txq->tx_stats,
3197 sizeof(struct ieee80211_tx_queue_stats));
3198 }
3199 spin_unlock_bh(&priv->tx_lock);
3200 return 0;
3201}
3202
3203struct mwl8k_get_stats_worker {
3204 struct mwl8k_work_struct header;
3205 struct ieee80211_low_level_stats *stats;
3206};
3207
3208static int mwl8k_get_stats_wt(struct work_struct *wt)
3209{
3210 struct mwl8k_get_stats_worker *worker =
3211 (struct mwl8k_get_stats_worker *)wt;
3212
3213 return mwl8k_cmd_802_11_get_stat(worker->header.hw, worker->stats);
3214}
3215
3216static int mwl8k_get_stats(struct ieee80211_hw *hw,
3217 struct ieee80211_low_level_stats *stats)
3218{
3219 int rc;
3220 struct mwl8k_get_stats_worker *worker;
3221 struct mwl8k_priv *priv = hw->priv;
3222
3223 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3224 if (worker == NULL)
3225 return -ENOMEM;
3226
3227 worker->stats = stats;
3228 rc = mwl8k_queue_work(hw, &worker->header,
3229 priv->config_wq, mwl8k_get_stats_wt);
3230
3231 kfree(worker);
3232 if (rc == -ETIMEDOUT) {
3233 printk(KERN_ERR "%s() timed out\n", __func__);
3234 rc = -EINVAL;
3235 }
3236
3237 return rc;
3238}
3239
3240static const struct ieee80211_ops mwl8k_ops = {
3241 .tx = mwl8k_tx,
3242 .start = mwl8k_start,
3243 .stop = mwl8k_stop,
3244 .add_interface = mwl8k_add_interface,
3245 .remove_interface = mwl8k_remove_interface,
3246 .config = mwl8k_config,
a66098da 3247 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3248 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3249 .configure_filter = mwl8k_configure_filter,
3250 .set_rts_threshold = mwl8k_set_rts_threshold,
3251 .conf_tx = mwl8k_conf_tx,
3252 .get_tx_stats = mwl8k_get_tx_stats,
3253 .get_stats = mwl8k_get_stats,
3254};
3255
3256static void mwl8k_tx_reclaim_handler(unsigned long data)
3257{
3258 int i;
3259 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3260 struct mwl8k_priv *priv = hw->priv;
3261
3262 spin_lock_bh(&priv->tx_lock);
3263 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3264 mwl8k_txq_reclaim(hw, i, 0);
3265
ce9e2e1b
LB		 3266 if (priv->tx_wait != NULL && mwl8k_txq_busy(priv) == 0) {
3267 complete(priv->tx_wait);
3268 priv->tx_wait = NULL;
a66098da
LB		 3269 }
3270 spin_unlock_bh(&priv->tx_lock);
3271}
3272
3273static void mwl8k_finalize_join_worker(struct work_struct *work)
3274{
3275 struct mwl8k_priv *priv =
3276 container_of(work, struct mwl8k_priv, finalize_join_worker);
3277 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3278 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3279
3280 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3281 dev_kfree_skb(skb);
3282
3283 priv->beacon_skb = NULL;
3284}
3285
3286static int __devinit mwl8k_probe(struct pci_dev *pdev,
3287 const struct pci_device_id *id)
3288{
3289 struct ieee80211_hw *hw;
3290 struct mwl8k_priv *priv;
a66098da
LB		 3291 int rc;
3292 int i;
3293 u8 *fw;
3294
3295 rc = pci_enable_device(pdev);
3296 if (rc) {
3297 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3298 MWL8K_NAME);
3299 return rc;
3300 }
3301
3302 rc = pci_request_regions(pdev, MWL8K_NAME);
3303 if (rc) {
3304 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3305 MWL8K_NAME);
3306 return rc;
3307 }
3308
3309 pci_set_master(pdev);
3310
3311 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3312 if (hw == NULL) {
3313 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3314 rc = -ENOMEM;
3315 goto err_free_reg;
3316 }
3317
3318 priv = hw->priv;
3319 priv->hw = hw;
3320 priv->pdev = pdev;
3321 priv->hostcmd_wait = NULL;
3322 priv->tx_wait = NULL;
3323 priv->inconfig = false;
0439b1f5 3324 priv->wmm_enabled = false;
a66098da
LB		 3325 priv->pending_tx_pkts = 0;
3326 strncpy(priv->name, MWL8K_NAME, sizeof(priv->name));
3327
3328 spin_lock_init(&priv->fw_lock);
3329
3330 SET_IEEE80211_DEV(hw, &pdev->dev);
3331 pci_set_drvdata(pdev, hw);
3332
3333 priv->regs = pci_iomap(pdev, 1, 0x10000);
3334 if (priv->regs == NULL) {
3335 printk(KERN_ERR "%s: Cannot map device memory\n", priv->name);
3336 goto err_iounmap;
3337 }
3338
3339 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3340 priv->band.band = IEEE80211_BAND_2GHZ;
3341 priv->band.channels = priv->channels;
3342 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3343 priv->band.bitrates = priv->rates;
3344 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3345 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3346
3347 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3348 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3349
3350 /*
3351 * Extra headroom is the size of the required DMA header
3352 * minus the size of the smallest 802.11 frame (CTS frame).
3353 */
3354 hw->extra_tx_headroom =
3355 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3356
3357 hw->channel_change_time = 10;
3358
3359 hw->queues = MWL8K_TX_QUEUES;
3360
240e86ef 3361 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
a66098da
LB		 3362
3363 /* Set rssi and noise values to dBm */
ce9e2e1b 3364 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3365 hw->vif_data_size = sizeof(struct mwl8k_vif);
3366 priv->vif = NULL;
3367
3368 /* Set default radio state and preamble */
c46563b7 3369 priv->radio_on = 0;
68ce3884 3370 priv->radio_short_preamble = 0;
a66098da
LB		 3371
3372 /* Finalize join worker */
3373 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3374
3375 /* TX reclaim tasklet */
3376 tasklet_init(&priv->tx_reclaim_task,
3377 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3378 tasklet_disable(&priv->tx_reclaim_task);
3379
3380 /* Config workthread */
3381 priv->config_wq = create_singlethread_workqueue("mwl8k_config");
3382 if (priv->config_wq == NULL)
3383 goto err_iounmap;
3384
3385 /* Power management cookie */
3386 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3387 if (priv->cookie == NULL)
3388 goto err_iounmap;
3389
3390 rc = mwl8k_rxq_init(hw, 0);
3391 if (rc)
3392 goto err_iounmap;
3393 rxq_refill(hw, 0, INT_MAX);
3394
3395 spin_lock_init(&priv->tx_lock);
3396
3397 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3398 rc = mwl8k_txq_init(hw, i);
3399 if (rc)
3400 goto err_free_queues;
3401 }
3402
3403 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3404 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3405 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3406 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3407
3408 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3409 IRQF_SHARED, MWL8K_NAME, hw);
3410 if (rc) {
3411 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3412 priv->name);
3413 goto err_free_queues;
3414 }
3415
3416 /* Reset firmware and hardware */
3417 mwl8k_hw_reset(priv);
3418
3419 /* Ask userland hotplug daemon for the device firmware */
3420 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3421 if (rc) {
3422 printk(KERN_ERR "%s: Firmware files not found\n", priv->name);
3423 goto err_free_irq;
3424 }
3425
3426 /* Load firmware into hardware */
3427 rc = mwl8k_load_firmware(priv);
3428 if (rc) {
3429 printk(KERN_ERR "%s: Cannot start firmware\n", priv->name);
3430 goto err_stop_firmware;
3431 }
3432
3433 /* Reclaim memory once firmware is successfully loaded */
3434 mwl8k_release_firmware(priv);
3435
3436 /*
3437 * Temporarily enable interrupts. Initial firmware host
3438 * commands use interrupts and avoids polling. Disable
3439 * interrupts when done.
3440 */
c23b5a69 3441 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3442
3443 /* Get config data, mac addrs etc */
3444 rc = mwl8k_cmd_get_hw_spec(hw);
3445 if (rc) {
3446 printk(KERN_ERR "%s: Cannot initialise firmware\n", priv->name);
3447 goto err_stop_firmware;
3448 }
3449
3450 /* Turn radio off */
c46563b7 3451 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 3452 if (rc) {
3453 printk(KERN_ERR "%s: Cannot disable\n", priv->name);
3454 goto err_stop_firmware;
3455 }
3456
3457 /* Disable interrupts */
a66098da 3458 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3459 free_irq(priv->pdev->irq, hw);
3460
3461 rc = ieee80211_register_hw(hw);
3462 if (rc) {
3463 printk(KERN_ERR "%s: Cannot register device\n", priv->name);
3464 goto err_stop_firmware;
3465 }
3466
3467 fw = (u8 *)&priv->fw_rev;
3468 printk(KERN_INFO "%s: 88W%u %s\n", priv->name, priv->part_num,
3469 MWL8K_DESC);
3470 printk(KERN_INFO "%s: Driver Ver:%s Firmware Ver:%u.%u.%u.%u\n",
3471 priv->name, MWL8K_VERSION, fw[3], fw[2], fw[1], fw[0]);
e91d8334
JB		 3472 printk(KERN_INFO "%s: MAC Address: %pM\n", priv->name,
3473 hw->wiphy->perm_addr);
a66098da
LB		 3474
3475 return 0;
3476
3477err_stop_firmware:
3478 mwl8k_hw_reset(priv);
3479 mwl8k_release_firmware(priv);
3480
3481err_free_irq:
a66098da 3482 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3483 free_irq(priv->pdev->irq, hw);
3484
3485err_free_queues:
3486 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3487 mwl8k_txq_deinit(hw, i);
3488 mwl8k_rxq_deinit(hw, 0);
3489
3490err_iounmap:
3491 if (priv->cookie != NULL)
3492 pci_free_consistent(priv->pdev, 4,
3493 priv->cookie, priv->cookie_dma);
3494
3495 if (priv->regs != NULL)
3496 pci_iounmap(pdev, priv->regs);
3497
3498 if (priv->config_wq != NULL)
3499 destroy_workqueue(priv->config_wq);
3500
3501 pci_set_drvdata(pdev, NULL);
3502 ieee80211_free_hw(hw);
3503
3504err_free_reg:
3505 pci_release_regions(pdev);
3506 pci_disable_device(pdev);
3507
3508 return rc;
3509}
3510
230f7af0 3511static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3512{
3513 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3514}
3515
230f7af0 3516static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3517{
3518 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3519 struct mwl8k_priv *priv;
3520 int i;
3521
3522 if (hw == NULL)
3523 return;
3524 priv = hw->priv;
3525
3526 ieee80211_stop_queues(hw);
3527
60aa569f
LB		 3528 ieee80211_unregister_hw(hw);
3529
a66098da
LB		 3530 /* Remove tx reclaim tasklet */
3531 tasklet_kill(&priv->tx_reclaim_task);
3532
3533 /* Stop config thread */
3534 destroy_workqueue(priv->config_wq);
3535
3536 /* Stop hardware */
3537 mwl8k_hw_reset(priv);
3538
3539 /* Return all skbs to mac80211 */
3540 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3541 mwl8k_txq_reclaim(hw, i, 1);
3542
a66098da
LB		 3543 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3544 mwl8k_txq_deinit(hw, i);
3545
3546 mwl8k_rxq_deinit(hw, 0);
3547
3548 pci_free_consistent(priv->pdev, 4,
3549 priv->cookie, priv->cookie_dma);
3550
3551 pci_iounmap(pdev, priv->regs);
3552 pci_set_drvdata(pdev, NULL);
3553 ieee80211_free_hw(hw);
3554 pci_release_regions(pdev);
3555 pci_disable_device(pdev);
3556}
3557
3558static struct pci_driver mwl8k_driver = {
3559 .name = MWL8K_NAME,
3560 .id_table = mwl8k_table,
3561 .probe = mwl8k_probe,
3562 .remove = __devexit_p(mwl8k_remove),
3563 .shutdown = __devexit_p(mwl8k_shutdown),
3564};
3565
3566static int __init mwl8k_init(void)
3567{
3568 return pci_register_driver(&mwl8k_driver);
3569}
3570
3571static void __exit mwl8k_exit(void)
3572{
3573 pci_unregister_driver(&mwl8k_driver);
3574}
3575
3576module_init(mwl8k_init);
3577module_exit(mwl8k_exit);
Linux 6.x block layer and io_uring tree(s)