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mwl8k: prevent corruption of QoS field on receive
[linux-2.6-block.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
54bc3a0d 95 struct rxd_ops *rxd_ops;
547810e3 96 u16 modes;
45a390dd
LB		 97};
98
a66098da 99struct mwl8k_rx_queue {
45eb400d 100 int rxd_count;
a66098da
LB		 101
102 /* hw receives here */
45eb400d 103 int head;
a66098da
LB		 104
105 /* refill descs here */
45eb400d 106 int tail;
a66098da 107
54bc3a0d 108 void *rxd;
45eb400d 109 dma_addr_t rxd_dma;
788838eb
LB		 110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
a66098da
LB		 114};
115
a66098da
LB		 116struct mwl8k_tx_queue {
117 /* hw transmits here */
45eb400d 118 int head;
a66098da
LB		 119
120 /* sw appends here */
45eb400d 121 int tail;
a66098da 122
45eb400d
LB		 123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
a66098da
LB		 127};
128
129/* Pointers to the firmware data and meta information about it. */
130struct mwl8k_firmware {
a66098da
LB		 131 /* Boot helper code */
132 struct firmware *helper;
a74b295e
LB		 133
134 /* Microcode */
135 struct firmware *ucode;
a66098da
LB		 136};
137
138struct mwl8k_priv {
5b9482dd 139 void __iomem *sram;
a66098da
LB		 140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
a66098da 144
45a390dd 145 struct mwl8k_device_info *device_info;
eae74e65 146 bool ap_fw;
54bc3a0d 147 struct rxd_ops *rxd_ops;
45a390dd 148
a66098da
LB		 149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
a66098da 151
618952a7
LB		 152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
618952a7
LB		 156 struct completion *hostcmd_wait;
157
a66098da
LB		 158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
a66098da 160
88de754a
LB		 161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
a66098da 164 struct ieee80211_vif *vif;
a66098da
LB		 165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
a66098da 173 u8 hw_rev;
2aa7b01f 174 u32 fw_rev;
a66098da
LB		 175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
140eb5e2 188 struct ieee80211_rate rates[14];
a66098da 189
c46563b7 190 bool radio_on;
68ce3884 191 bool radio_short_preamble;
a43c49a8 192 bool sniffer_enabled;
0439b1f5 193 bool wmm_enabled;
a66098da 194
a66098da
LB		 195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
d89173f2 197 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 210};
211
212/* Per interface specific private data */
213struct mwl8k_vif {
a66098da
LB		 214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
d89173f2
LB		 221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
a66098da 223
a66098da
LB		 224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
a66098da
LB		 229};
230
a94cc97e 231#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 232
233static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245};
246
247static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 261 { .bitrate = 720, .hw_value = 144, },
262};
263
264static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
a66098da
LB		 266};
267
a66098da
LB		 268/* Set or get info from Firmware */
269#define MWL8K_CMD_SET 0x0001
270#define MWL8K_CMD_GET 0x0000
271
272/* Firmware command codes */
273#define MWL8K_CMD_CODE_DNLD 0x0001
274#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 275#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 276#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 278#define MWL8K_CMD_RADIO_CONTROL 0x001c
279#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 280#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 281#define MWL8K_CMD_SET_PRE_SCAN 0x0107
282#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 283#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284#define MWL8K_CMD_SET_AID 0x010d
285#define MWL8K_CMD_SET_RATE 0x0110
286#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 288#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 289#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 291#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 292#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 293#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 294#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 295#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 296#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 297
298static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299{
300#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
ce9e2e1b 304 switch (cmd & ~0x8000) {
a66098da
LB		 305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 307 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 312 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 320 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 323 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 324 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 325 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 326 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 328 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332#undef MWL8K_CMDNAME
333
334 return buf;
335}
336
337/* Hardware and firmware reset */
338static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339{
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345}
346
347/* Release fw image */
348static void mwl8k_release_fw(struct firmware **fw)
349{
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354}
355
356static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357{
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360}
361
362/* Request fw image */
363static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 364 const char *fname, struct firmware **fw)
a66098da
LB		 365{
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
c2c357ce 371 fname, &priv->pdev->dev);
a66098da
LB		 372}
373
45a390dd 374static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 375{
a74b295e 376 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 377 int rc;
378
a74b295e
LB		 379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
a66098da
LB		 387 }
388
a74b295e 389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 390 if (rc) {
c2c357ce 391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 392 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398}
399
7e75b942
BH		 400MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
a66098da
LB		 403struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409} __attribute__((packed));
410
411/*
412 * Firmware loading.
413 */
414static int
415mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416{
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
a66098da
LB		 419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
a66098da
LB		 432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 439 break;
440 }
441
3d76e82c 442 cond_resched();
a66098da
LB		 443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
d4b70570 448 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 449}
450
451static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453{
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490}
491
492static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494{
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549}
550
c2c357ce 551static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 552{
c2c357ce
LB		 553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
eae74e65 555 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
a66098da 561
c2c357ce
LB		 562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
a66098da 567
c2c357ce 568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 571 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 572 return rc;
573 }
574 msleep(1);
575
c2c357ce 576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 577 } else {
c2c357ce 578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 579 }
580
581 if (rc) {
c2c357ce
LB		 582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
a66098da
LB		 584 return rc;
585 }
586
eae74e65
LB		 587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da
LB		 591 msleep(1);
592
593 loops = 200000;
594 do {
eae74e65
LB		 595 u32 ready_code;
596
597 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
598 if (ready_code == MWL8K_FWAP_READY) {
599 priv->ap_fw = 1;
600 break;
601 } else if (ready_code == MWL8K_FWSTA_READY) {
602 priv->ap_fw = 0;
a66098da 603 break;
eae74e65
LB		 604 }
605
606 cond_resched();
a66098da
LB		 607 udelay(1);
608 } while (--loops);
609
610 return loops ? 0 : -ETIMEDOUT;
611}
612
613
614/*
615 * Defines shared between transmission and reception.
616 */
617/* HT control fields for firmware */
618struct ewc_ht_info {
619 __le16 control1;
620 __le16 control2;
621 __le16 control3;
622} __attribute__((packed));
623
624/* Firmware Station database operations */
625#define MWL8K_STA_DB_ADD_ENTRY 0
626#define MWL8K_STA_DB_MODIFY_ENTRY 1
627#define MWL8K_STA_DB_DEL_ENTRY 2
628#define MWL8K_STA_DB_FLUSH 3
629
630/* Peer Entry flags - used to define the type of the peer node */
631#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 632
a66098da
LB		 633struct peer_capability_info {
634 /* Peer type - AP vs. STA. */
635 __u8 peer_type;
636
637 /* Basic 802.11 capabilities from assoc resp. */
638 __le16 basic_caps;
639
640 /* Set if peer supports 802.11n high throughput (HT). */
641 __u8 ht_support;
642
643 /* Valid if HT is supported. */
644 __le16 ht_caps;
645 __u8 extended_ht_caps;
646 struct ewc_ht_info ewc_info;
647
648 /* Legacy rate table. Intersection of our rates and peer rates. */
140eb5e2 649 __u8 legacy_rates[12];
a66098da
LB		 650
651 /* HT rate table. Intersection of our rates and peer rates. */
0b5351a8 652 __u8 ht_rates[16];
c23b5a69 653 __u8 pad[16];
a66098da
LB		 654
655 /* If set, interoperability mode, no proprietary extensions. */
656 __u8 interop;
657 __u8 pad2;
658 __u8 station_id;
659 __le16 amsdu_enabled;
660} __attribute__((packed));
661
662/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 663static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
664{
665 u16 val_mask = 1 << 4;
666
667 /* End of Service Period Bit 4 */
668 return qos | val_mask;
669}
670
671static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
672{
673 u16 val_mask = 0x3;
674 u8 shift = 5;
675 u16 qos_mask = ~(val_mask << shift);
676
677 /* Ack Policy Bit 5-6 */
678 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
679}
680
681static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
682{
683 u16 val_mask = 1 << 7;
684
685 /* AMSDU present Bit 7 */
686 return qos | val_mask;
687}
688
689static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
690{
691 u16 val_mask = 0xff;
692 u8 shift = 8;
693 u16 qos_mask = ~(val_mask << shift);
694
695 /* Queue Length Bits 8-15 */
696 return (qos & qos_mask) | ((len & val_mask) << shift);
697}
698
699/* DMA header used by firmware and hardware. */
700struct mwl8k_dma_data {
701 __le16 fwlen;
702 struct ieee80211_hdr wh;
20f09c3d 703 char data[0];
a66098da
LB		 704} __attribute__((packed));
705
706/* Routines to add/remove DMA header from skb. */
20f09c3d 707static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 708{
20f09c3d
LB		 709 struct mwl8k_dma_data *tr;
710 int hdrlen;
711
712 tr = (struct mwl8k_dma_data *)skb->data;
713 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
714
715 if (hdrlen != sizeof(tr->wh)) {
716 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
717 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
718 *((__le16 *)(tr->data - 2)) = qos;
719 } else {
720 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
721 }
a66098da 722 }
20f09c3d
LB		 723
724 if (hdrlen != sizeof(*tr))
725 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 726}
727
76266b2a 728static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 729{
730 struct ieee80211_hdr *wh;
731 u32 hdrlen, pktlen;
732 struct mwl8k_dma_data *tr;
733
734 wh = (struct ieee80211_hdr *)skb->data;
735 hdrlen = ieee80211_hdrlen(wh->frame_control);
736 pktlen = skb->len;
737
738 /*
739 * Copy up/down the 802.11 header; the firmware requires
740 * we present a 2-byte payload length followed by a
741 * 4-address header (w/o QoS), followed (optionally) by
742 * any WEP/ExtIV header (but only filled in for CCMP).
743 */
744 if (hdrlen != sizeof(struct mwl8k_dma_data))
745 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
746
747 tr = (struct mwl8k_dma_data *)skb->data;
748 if (wh != &tr->wh)
749 memmove(&tr->wh, wh, hdrlen);
750
751 /* Clear addr4 */
d89173f2 752 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 753
754 /*
755 * Firmware length is the length of the fully formed "802.11
756 * payload". That is, everything except for the 802.11 header.
757 * This includes all crypto material including the MIC.
758 */
759 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 760}
761
762
763/*
6f6d1e9a
LB		 764 * Packet reception for 88w8366.
765 */
766struct mwl8k_rxd_8366 {
767 __le16 pkt_len;
768 __u8 sq2;
769 __u8 rate;
770 __le32 pkt_phys_addr;
771 __le32 next_rxd_phys_addr;
772 __le16 qos_control;
773 __le16 htsig2;
774 __le32 hw_rssi_info;
775 __le32 hw_noise_floor_info;
776 __u8 noise_floor;
777 __u8 pad0[3];
778 __u8 rssi;
779 __u8 rx_status;
780 __u8 channel;
781 __u8 rx_ctrl;
782} __attribute__((packed));
783
784#define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
785
786static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
787{
788 struct mwl8k_rxd_8366 *rxd = _rxd;
789
790 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
791 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
792}
793
794static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
795{
796 struct mwl8k_rxd_8366 *rxd = _rxd;
797
798 rxd->pkt_len = cpu_to_le16(len);
799 rxd->pkt_phys_addr = cpu_to_le32(addr);
800 wmb();
801 rxd->rx_ctrl = 0;
802}
803
804static int
20f09c3d
LB		 805mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
806 __le16 *qos)
6f6d1e9a
LB		 807{
808 struct mwl8k_rxd_8366 *rxd = _rxd;
809
810 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
811 return -1;
812 rmb();
813
814 memset(status, 0, sizeof(*status));
815
816 status->signal = -rxd->rssi;
817 status->noise = -rxd->noise_floor;
818
819 if (rxd->rate & 0x80) {
820 status->flag |= RX_FLAG_HT;
821 status->rate_idx = rxd->rate & 0x7f;
822 } else {
823 int i;
824
825 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
826 if (mwl8k_rates[i].hw_value == rxd->rate) {
827 status->rate_idx = i;
828 break;
829 }
830 }
831 }
832
833 status->band = IEEE80211_BAND_2GHZ;
834 status->freq = ieee80211_channel_to_frequency(rxd->channel);
835
20f09c3d
LB		 836 *qos = rxd->qos_control;
837
6f6d1e9a
LB		 838 return le16_to_cpu(rxd->pkt_len);
839}
840
841static struct rxd_ops rxd_8366_ops = {
842 .rxd_size = sizeof(struct mwl8k_rxd_8366),
843 .rxd_init = mwl8k_rxd_8366_init,
844 .rxd_refill = mwl8k_rxd_8366_refill,
845 .rxd_process = mwl8k_rxd_8366_process,
846};
847
848/*
849 * Packet reception for 88w8687.
a66098da 850 */
54bc3a0d 851struct mwl8k_rxd_8687 {
a66098da
LB		 852 __le16 pkt_len;
853 __u8 link_quality;
854 __u8 noise_level;
855 __le32 pkt_phys_addr;
45eb400d 856 __le32 next_rxd_phys_addr;
a66098da
LB		 857 __le16 qos_control;
858 __le16 rate_info;
859 __le32 pad0[4];
860 __u8 rssi;
861 __u8 channel;
862 __le16 pad1;
863 __u8 rx_ctrl;
864 __u8 rx_status;
865 __u8 pad2[2];
866} __attribute__((packed));
867
54bc3a0d
LB		 868#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
869#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
870#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
871#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
872#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
873#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
874
875#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
876
877static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
878{
879 struct mwl8k_rxd_8687 *rxd = _rxd;
880
881 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
882 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
883}
884
885static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
886{
887 struct mwl8k_rxd_8687 *rxd = _rxd;
888
889 rxd->pkt_len = cpu_to_le16(len);
890 rxd->pkt_phys_addr = cpu_to_le32(addr);
891 wmb();
892 rxd->rx_ctrl = 0;
893}
894
895static int
20f09c3d
LB		 896mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
897 __le16 *qos)
54bc3a0d
LB		 898{
899 struct mwl8k_rxd_8687 *rxd = _rxd;
900 u16 rate_info;
901
902 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
903 return -1;
904 rmb();
905
906 rate_info = le16_to_cpu(rxd->rate_info);
907
908 memset(status, 0, sizeof(*status));
909
910 status->signal = -rxd->rssi;
911 status->noise = -rxd->noise_level;
912 status->qual = rxd->link_quality;
913 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
914 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
915
916 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
917 status->flag |= RX_FLAG_SHORTPRE;
918 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
919 status->flag |= RX_FLAG_40MHZ;
920 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
921 status->flag |= RX_FLAG_SHORT_GI;
922 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
923 status->flag |= RX_FLAG_HT;
924
925 status->band = IEEE80211_BAND_2GHZ;
926 status->freq = ieee80211_channel_to_frequency(rxd->channel);
927
20f09c3d
LB		 928 *qos = rxd->qos_control;
929
54bc3a0d
LB		 930 return le16_to_cpu(rxd->pkt_len);
931}
932
933static struct rxd_ops rxd_8687_ops = {
934 .rxd_size = sizeof(struct mwl8k_rxd_8687),
935 .rxd_init = mwl8k_rxd_8687_init,
936 .rxd_refill = mwl8k_rxd_8687_refill,
937 .rxd_process = mwl8k_rxd_8687_process,
938};
939
940
a66098da
LB		 941#define MWL8K_RX_DESCS 256
942#define MWL8K_RX_MAXSZ 3800
943
944static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
945{
946 struct mwl8k_priv *priv = hw->priv;
947 struct mwl8k_rx_queue *rxq = priv->rxq + index;
948 int size;
949 int i;
950
45eb400d
LB		 951 rxq->rxd_count = 0;
952 rxq->head = 0;
953 rxq->tail = 0;
a66098da 954
54bc3a0d 955 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 956
45eb400d
LB		 957 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
958 if (rxq->rxd == NULL) {
a66098da 959 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 960 wiphy_name(hw->wiphy));
a66098da
LB		 961 return -ENOMEM;
962 }
45eb400d 963 memset(rxq->rxd, 0, size);
a66098da 964
788838eb
LB		 965 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
966 if (rxq->buf == NULL) {
a66098da 967 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 968 wiphy_name(hw->wiphy));
45eb400d 969 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 970 return -ENOMEM;
971 }
788838eb 972 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 973
974 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 975 int desc_size;
976 void *rxd;
a66098da 977 int nexti;
54bc3a0d
LB		 978 dma_addr_t next_dma_addr;
979
980 desc_size = priv->rxd_ops->rxd_size;
981 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 982
54bc3a0d
LB		 983 nexti = i + 1;
984 if (nexti == MWL8K_RX_DESCS)
985 nexti = 0;
986 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 987
54bc3a0d 988 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 989 }
990
991 return 0;
992}
993
994static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
995{
996 struct mwl8k_priv *priv = hw->priv;
997 struct mwl8k_rx_queue *rxq = priv->rxq + index;
998 int refilled;
999
1000 refilled = 0;
45eb400d 1001 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1002 struct sk_buff *skb;
788838eb 1003 dma_addr_t addr;
a66098da 1004 int rx;
54bc3a0d 1005 void *rxd;
a66098da
LB		 1006
1007 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1008 if (skb == NULL)
1009 break;
1010
788838eb
LB		 1011 addr = pci_map_single(priv->pdev, skb->data,
1012 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1013
54bc3a0d
LB		 1014 rxq->rxd_count++;
1015 rx = rxq->tail++;
1016 if (rxq->tail == MWL8K_RX_DESCS)
1017 rxq->tail = 0;
788838eb
LB		 1018 rxq->buf[rx].skb = skb;
1019 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1020
1021 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1022 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1023
1024 refilled++;
1025 }
1026
1027 return refilled;
1028}
1029
1030/* Must be called only when the card's reception is completely halted */
1031static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1032{
1033 struct mwl8k_priv *priv = hw->priv;
1034 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1035 int i;
1036
1037 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1038 if (rxq->buf[i].skb != NULL) {
1039 pci_unmap_single(priv->pdev,
1040 pci_unmap_addr(&rxq->buf[i], dma),
1041 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1042 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1043
1044 kfree_skb(rxq->buf[i].skb);
1045 rxq->buf[i].skb = NULL;
a66098da
LB		 1046 }
1047 }
1048
788838eb
LB		 1049 kfree(rxq->buf);
1050 rxq->buf = NULL;
a66098da
LB		 1051
1052 pci_free_consistent(priv->pdev,
54bc3a0d 1053 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1054 rxq->rxd, rxq->rxd_dma);
1055 rxq->rxd = NULL;
a66098da
LB		 1056}
1057
1058
1059/*
1060 * Scan a list of BSSIDs to process for finalize join.
1061 * Allows for extension to process multiple BSSIDs.
1062 */
1063static inline int
1064mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1065{
1066 return priv->capture_beacon &&
1067 ieee80211_is_beacon(wh->frame_control) &&
1068 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1069}
1070
3779752d
LB		 1071static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1072 struct sk_buff *skb)
a66098da 1073{
3779752d
LB		 1074 struct mwl8k_priv *priv = hw->priv;
1075
a66098da 1076 priv->capture_beacon = false;
d89173f2 1077 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1078
1079 /*
1080 * Use GFP_ATOMIC as rxq_process is called from
1081 * the primary interrupt handler, memory allocation call
1082 * must not sleep.
1083 */
1084 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1085 if (priv->beacon_skb != NULL)
3779752d 1086 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1087}
1088
1089static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1090{
1091 struct mwl8k_priv *priv = hw->priv;
1092 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1093 int processed;
1094
1095 processed = 0;
45eb400d 1096 while (rxq->rxd_count && limit--) {
a66098da 1097 struct sk_buff *skb;
54bc3a0d
LB		 1098 void *rxd;
1099 int pkt_len;
a66098da 1100 struct ieee80211_rx_status status;
20f09c3d 1101 __le16 qos;
a66098da 1102
788838eb 1103 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1104 if (skb == NULL)
1105 break;
54bc3a0d
LB		 1106
1107 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1108
20f09c3d 1109 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1110 if (pkt_len < 0)
1111 break;
1112
788838eb
LB		 1113 rxq->buf[rxq->head].skb = NULL;
1114
1115 pci_unmap_single(priv->pdev,
1116 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1117 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1118 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1119
54bc3a0d
LB		 1120 rxq->head++;
1121 if (rxq->head == MWL8K_RX_DESCS)
1122 rxq->head = 0;
1123
45eb400d 1124 rxq->rxd_count--;
a66098da 1125
54bc3a0d 1126 skb_put(skb, pkt_len);
20f09c3d 1127 mwl8k_remove_dma_header(skb, qos);
a66098da 1128
a66098da 1129 /*
c2c357ce
LB		 1130 * Check for a pending join operation. Save a
1131 * copy of the beacon and schedule a tasklet to
1132 * send a FINALIZE_JOIN command to the firmware.
a66098da 1133 */
54bc3a0d 1134 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1135 mwl8k_save_beacon(hw, skb);
a66098da 1136
f1d58c25
JB		 1137 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1138 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1139
1140 processed++;
1141 }
1142
1143 return processed;
1144}
1145
1146
1147/*
1148 * Packet transmission.
1149 */
1150
a66098da
LB		 1151/* Transmit packet ACK policy */
1152#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1153#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1154
a66098da
LB		 1155#define MWL8K_TXD_STATUS_OK 0x00000001
1156#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1157#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1158#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1159#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1160
1161struct mwl8k_tx_desc {
1162 __le32 status;
1163 __u8 data_rate;
1164 __u8 tx_priority;
1165 __le16 qos_control;
1166 __le32 pkt_phys_addr;
1167 __le16 pkt_len;
d89173f2 1168 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1169 __le32 next_txd_phys_addr;
a66098da
LB		 1170 __le32 reserved;
1171 __le16 rate_info;
1172 __u8 peer_id;
1173 __u8 tx_frag_cnt;
1174} __attribute__((packed));
1175
1176#define MWL8K_TX_DESCS 128
1177
1178static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1179{
1180 struct mwl8k_priv *priv = hw->priv;
1181 struct mwl8k_tx_queue *txq = priv->txq + index;
1182 int size;
1183 int i;
1184
45eb400d
LB		 1185 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1186 txq->stats.limit = MWL8K_TX_DESCS;
1187 txq->head = 0;
1188 txq->tail = 0;
a66098da
LB		 1189
1190 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1191
45eb400d
LB		 1192 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1193 if (txq->txd == NULL) {
a66098da 1194 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1195 wiphy_name(hw->wiphy));
a66098da
LB		 1196 return -ENOMEM;
1197 }
45eb400d 1198 memset(txq->txd, 0, size);
a66098da 1199
45eb400d
LB		 1200 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1201 if (txq->skb == NULL) {
a66098da 1202 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1203 wiphy_name(hw->wiphy));
45eb400d 1204 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1205 return -ENOMEM;
1206 }
45eb400d 1207 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1208
1209 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1210 struct mwl8k_tx_desc *tx_desc;
1211 int nexti;
1212
45eb400d 1213 tx_desc = txq->txd + i;
a66098da
LB		 1214 nexti = (i + 1) % MWL8K_TX_DESCS;
1215
1216 tx_desc->status = 0;
45eb400d
LB		 1217 tx_desc->next_txd_phys_addr =
1218 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1219 }
1220
1221 return 0;
1222}
1223
1224static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1225{
1226 iowrite32(MWL8K_H2A_INT_PPA_READY,
1227 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1228 iowrite32(MWL8K_H2A_INT_DUMMY,
1229 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1230 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1231}
1232
a66098da
LB		 1233struct mwl8k_txq_info {
1234 u32 fw_owned;
1235 u32 drv_owned;
1236 u32 unused;
1237 u32 len;
1238 u32 head;
1239 u32 tail;
1240};
1241
1242static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1243 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1244{
1245 int count, desc, status;
1246 struct mwl8k_tx_queue *txq;
1247 struct mwl8k_tx_desc *tx_desc;
1248 int ndescs = 0;
1249
c3f967d3
LB		 1250 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1251
c3f967d3 1252 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da 1253 txq = priv->txq + count;
45eb400d
LB		 1254 txinfo[count].len = txq->stats.len;
1255 txinfo[count].head = txq->head;
1256 txinfo[count].tail = txq->tail;
a66098da 1257 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
45eb400d 1258 tx_desc = txq->txd + desc;
a66098da
LB		 1259 status = le32_to_cpu(tx_desc->status);
1260
1261 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1262 txinfo[count].fw_owned++;
1263 else
1264 txinfo[count].drv_owned++;
1265
1266 if (tx_desc->pkt_len == 0)
1267 txinfo[count].unused++;
1268 }
1269 }
a66098da
LB		 1270
1271 return ndescs;
1272}
1273
618952a7 1274/*
88de754a 1275 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1276 */
950d5b01 1277static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1278{
a66098da 1279 struct mwl8k_priv *priv = hw->priv;
88de754a 1280 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1281 u32 count;
1282 unsigned long timeout;
a66098da
LB		 1283
1284 might_sleep();
1285
a66098da 1286 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1287 count = priv->pending_tx_pkts;
1288 if (count)
1289 priv->tx_wait = &tx_wait;
a66098da
LB		 1290 spin_unlock_bh(&priv->tx_lock);
1291
1292 if (count) {
c3f967d3 1293 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1294 int index;
1295 int newcount;
1296
88de754a 1297 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1298 msecs_to_jiffies(5000));
a66098da
LB		 1299 if (timeout)
1300 return 0;
1301
1302 spin_lock_bh(&priv->tx_lock);
1303 priv->tx_wait = NULL;
88de754a
LB		 1304 newcount = priv->pending_tx_pkts;
1305 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1306 spin_unlock_bh(&priv->tx_lock);
1307
618952a7 1308 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1309 __func__, __LINE__, count, newcount);
a66098da 1310
c3f967d3 1311 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1312 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1313 "DRV:%u U:%u\n",
a66098da
LB		 1314 index,
1315 txinfo[index].len,
1316 txinfo[index].head,
1317 txinfo[index].tail,
1318 txinfo[index].fw_owned,
1319 txinfo[index].drv_owned,
1320 txinfo[index].unused);
ce9e2e1b 1321
a66098da
LB		 1322 return -ETIMEDOUT;
1323 }
1324
1325 return 0;
1326}
1327
c23b5a69
LB		 1328#define MWL8K_TXD_SUCCESS(status) \
1329 ((status) & (MWL8K_TXD_STATUS_OK | \
1330 MWL8K_TXD_STATUS_OK_RETRY | \
1331 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1332
1333static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1334{
1335 struct mwl8k_priv *priv = hw->priv;
1336 struct mwl8k_tx_queue *txq = priv->txq + index;
1337 int wake = 0;
1338
45eb400d 1339 while (txq->stats.len > 0) {
a66098da 1340 int tx;
a66098da
LB		 1341 struct mwl8k_tx_desc *tx_desc;
1342 unsigned long addr;
ce9e2e1b 1343 int size;
a66098da
LB		 1344 struct sk_buff *skb;
1345 struct ieee80211_tx_info *info;
1346 u32 status;
1347
45eb400d
LB		 1348 tx = txq->head;
1349 tx_desc = txq->txd + tx;
a66098da
LB		 1350
1351 status = le32_to_cpu(tx_desc->status);
1352
1353 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1354 if (!force)
1355 break;
1356 tx_desc->status &=
1357 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1358 }
1359
45eb400d
LB		 1360 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1361 BUG_ON(txq->stats.len == 0);
1362 txq->stats.len--;
a66098da
LB		 1363 priv->pending_tx_pkts--;
1364
1365 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1366 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1367 skb = txq->skb[tx];
1368 txq->skb[tx] = NULL;
a66098da
LB		 1369
1370 BUG_ON(skb == NULL);
1371 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1372
20f09c3d 1373 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1374
1375 /* Mark descriptor as unused */
1376 tx_desc->pkt_phys_addr = 0;
1377 tx_desc->pkt_len = 0;
1378
a66098da
LB		 1379 info = IEEE80211_SKB_CB(skb);
1380 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1381 if (MWL8K_TXD_SUCCESS(status))
a66098da 1382 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1383
1384 ieee80211_tx_status_irqsafe(hw, skb);
1385
618952a7 1386 wake = 1;
a66098da
LB		 1387 }
1388
618952a7 1389 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1390 ieee80211_wake_queue(hw, index);
1391}
1392
1393/* must be called only when the card's transmit is completely halted */
1394static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1395{
1396 struct mwl8k_priv *priv = hw->priv;
1397 struct mwl8k_tx_queue *txq = priv->txq + index;
1398
1399 mwl8k_txq_reclaim(hw, index, 1);
1400
45eb400d
LB		 1401 kfree(txq->skb);
1402 txq->skb = NULL;
a66098da
LB		 1403
1404 pci_free_consistent(priv->pdev,
1405 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1406 txq->txd, txq->txd_dma);
1407 txq->txd = NULL;
a66098da
LB		 1408}
1409
1410static int
1411mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1412{
1413 struct mwl8k_priv *priv = hw->priv;
1414 struct ieee80211_tx_info *tx_info;
23b33906 1415 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1416 struct ieee80211_hdr *wh;
1417 struct mwl8k_tx_queue *txq;
1418 struct mwl8k_tx_desc *tx;
a66098da 1419 dma_addr_t dma;
23b33906
LB		 1420 u32 txstatus;
1421 u8 txdatarate;
1422 u16 qos;
a66098da 1423
23b33906
LB		 1424 wh = (struct ieee80211_hdr *)skb->data;
1425 if (ieee80211_is_data_qos(wh->frame_control))
1426 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1427 else
1428 qos = 0;
a66098da 1429
76266b2a 1430 mwl8k_add_dma_header(skb);
23b33906 1431 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1432
1433 tx_info = IEEE80211_SKB_CB(skb);
1434 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1435
1436 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1437 u16 seqno = mwl8k_vif->seqno;
23b33906 1438
a66098da
LB		 1439 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1440 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1441 mwl8k_vif->seqno = seqno++ % 4096;
1442 }
1443
23b33906
LB		 1444 /* Setup firmware control bit fields for each frame type. */
1445 txstatus = 0;
1446 txdatarate = 0;
1447 if (ieee80211_is_mgmt(wh->frame_control) ||
1448 ieee80211_is_ctl(wh->frame_control)) {
1449 txdatarate = 0;
1450 qos = mwl8k_qos_setbit_eosp(qos);
1451 /* Set Queue size to unspecified */
1452 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1453 } else if (ieee80211_is_data(wh->frame_control)) {
1454 txdatarate = 1;
1455 if (is_multicast_ether_addr(wh->addr1))
1456 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1457
1458 /* Send pkt in an aggregate if AMPDU frame. */
1459 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1460 qos = mwl8k_qos_setbit_ack(qos,
1461 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1462 else
1463 qos = mwl8k_qos_setbit_ack(qos,
1464 MWL8K_TXD_ACK_POLICY_NORMAL);
1465
1466 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1467 qos = mwl8k_qos_setbit_amsdu(qos);
1468 }
a66098da
LB		 1469
1470 dma = pci_map_single(priv->pdev, skb->data,
1471 skb->len, PCI_DMA_TODEVICE);
1472
1473 if (pci_dma_mapping_error(priv->pdev, dma)) {
1474 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1475 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1476 dev_kfree_skb(skb);
a66098da
LB		 1477 return NETDEV_TX_OK;
1478 }
1479
23b33906 1480 spin_lock_bh(&priv->tx_lock);
a66098da 1481
23b33906 1482 txq = priv->txq + index;
a66098da 1483
45eb400d
LB		 1484 BUG_ON(txq->skb[txq->tail] != NULL);
1485 txq->skb[txq->tail] = skb;
a66098da 1486
45eb400d 1487 tx = txq->txd + txq->tail;
23b33906
LB		 1488 tx->data_rate = txdatarate;
1489 tx->tx_priority = index;
a66098da 1490 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1491 tx->pkt_phys_addr = cpu_to_le32(dma);
1492 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1493 tx->rate_info = 0;
1494 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1495 wmb();
23b33906
LB		 1496 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1497
45eb400d
LB		 1498 txq->stats.count++;
1499 txq->stats.len++;
a66098da 1500 priv->pending_tx_pkts++;
a66098da 1501
45eb400d
LB		 1502 txq->tail++;
1503 if (txq->tail == MWL8K_TX_DESCS)
1504 txq->tail = 0;
23b33906 1505
45eb400d 1506 if (txq->head == txq->tail)
a66098da
LB		 1507 ieee80211_stop_queue(hw, index);
1508
23b33906 1509 mwl8k_tx_start(priv);
a66098da
LB		 1510
1511 spin_unlock_bh(&priv->tx_lock);
1512
1513 return NETDEV_TX_OK;
1514}
1515
1516
618952a7
LB		 1517/*
1518 * Firmware access.
1519 *
1520 * We have the following requirements for issuing firmware commands:
1521 * - Some commands require that the packet transmit path is idle when
1522 * the command is issued. (For simplicity, we'll just quiesce the
1523 * transmit path for every command.)
1524 * - There are certain sequences of commands that need to be issued to
1525 * the hardware sequentially, with no other intervening commands.
1526 *
1527 * This leads to an implementation of a "firmware lock" as a mutex that
1528 * can be taken recursively, and which is taken by both the low-level
1529 * command submission function (mwl8k_post_cmd) as well as any users of
1530 * that function that require issuing of an atomic sequence of commands,
1531 * and quiesces the transmit path whenever it's taken.
1532 */
1533static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1534{
1535 struct mwl8k_priv *priv = hw->priv;
1536
1537 if (priv->fw_mutex_owner != current) {
1538 int rc;
1539
1540 mutex_lock(&priv->fw_mutex);
1541 ieee80211_stop_queues(hw);
1542
1543 rc = mwl8k_tx_wait_empty(hw);
1544 if (rc) {
1545 ieee80211_wake_queues(hw);
1546 mutex_unlock(&priv->fw_mutex);
1547
1548 return rc;
1549 }
1550
1551 priv->fw_mutex_owner = current;
1552 }
1553
1554 priv->fw_mutex_depth++;
1555
1556 return 0;
1557}
1558
1559static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1560{
1561 struct mwl8k_priv *priv = hw->priv;
1562
1563 if (!--priv->fw_mutex_depth) {
1564 ieee80211_wake_queues(hw);
1565 priv->fw_mutex_owner = NULL;
1566 mutex_unlock(&priv->fw_mutex);
1567 }
1568}
1569
1570
a66098da
LB		 1571/*
1572 * Command processing.
1573 */
1574
1575/* Timeout firmware commands after 2000ms */
1576#define MWL8K_CMD_TIMEOUT_MS 2000
1577
1578static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1579{
1580 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1581 struct mwl8k_priv *priv = hw->priv;
1582 void __iomem *regs = priv->regs;
1583 dma_addr_t dma_addr;
1584 unsigned int dma_size;
1585 int rc;
a66098da
LB		 1586 unsigned long timeout = 0;
1587 u8 buf[32];
1588
c2c357ce 1589 cmd->result = 0xffff;
a66098da
LB		 1590 dma_size = le16_to_cpu(cmd->length);
1591 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1592 PCI_DMA_BIDIRECTIONAL);
1593 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1594 return -ENOMEM;
1595
618952a7 1596 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1597 if (rc) {
1598 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1599 PCI_DMA_BIDIRECTIONAL);
618952a7 1600 return rc;
39a1e42e 1601 }
a66098da 1602
a66098da
LB		 1603 priv->hostcmd_wait = &cmd_wait;
1604 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1605 iowrite32(MWL8K_H2A_INT_DOORBELL,
1606 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1607 iowrite32(MWL8K_H2A_INT_DUMMY,
1608 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1609
1610 timeout = wait_for_completion_timeout(&cmd_wait,
1611 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1612
618952a7
LB		 1613 priv->hostcmd_wait = NULL;
1614
1615 mwl8k_fw_unlock(hw);
1616
37055bd4
LB		 1617 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1618 PCI_DMA_BIDIRECTIONAL);
1619
a66098da 1620 if (!timeout) {
a66098da 1621 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1622 wiphy_name(hw->wiphy),
a66098da
LB		 1623 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1624 MWL8K_CMD_TIMEOUT_MS);
1625 rc = -ETIMEDOUT;
1626 } else {
ce9e2e1b 1627 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1628 if (rc)
1629 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1630 wiphy_name(hw->wiphy),
a66098da 1631 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1632 le16_to_cpu(cmd->result));
a66098da
LB		 1633 }
1634
a66098da
LB		 1635 return rc;
1636}
1637
1638/*
04b147b1 1639 * CMD_GET_HW_SPEC (STA version).
a66098da 1640 */
04b147b1 1641struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1642 struct mwl8k_cmd_pkt header;
1643 __u8 hw_rev;
1644 __u8 host_interface;
1645 __le16 num_mcaddrs;
d89173f2 1646 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1647 __le16 region_code;
1648 __le32 fw_rev;
1649 __le32 ps_cookie;
1650 __le32 caps;
1651 __u8 mcs_bitmap[16];
1652 __le32 rx_queue_ptr;
1653 __le32 num_tx_queues;
1654 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1655 __le32 caps2;
1656 __le32 num_tx_desc_per_queue;
45eb400d 1657 __le32 total_rxd;
a66098da
LB		 1658} __attribute__((packed));
1659
04b147b1 1660static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1661{
1662 struct mwl8k_priv *priv = hw->priv;
04b147b1 1663 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1664 int rc;
1665 int i;
1666
1667 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1668 if (cmd == NULL)
1669 return -ENOMEM;
1670
1671 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1672 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1673
1674 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1675 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1676 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1677 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1678 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1679 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1680 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1681 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1682
1683 rc = mwl8k_post_cmd(hw, &cmd->header);
1684
1685 if (!rc) {
1686 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1687 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1688 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1689 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1690 }
1691
1692 kfree(cmd);
1693 return rc;
1694}
1695
42fba21d
LB		 1696/*
1697 * CMD_GET_HW_SPEC (AP version).
1698 */
1699struct mwl8k_cmd_get_hw_spec_ap {
1700 struct mwl8k_cmd_pkt header;
1701 __u8 hw_rev;
1702 __u8 host_interface;
1703 __le16 num_wcb;
1704 __le16 num_mcaddrs;
1705 __u8 perm_addr[ETH_ALEN];
1706 __le16 region_code;
1707 __le16 num_antenna;
1708 __le32 fw_rev;
1709 __le32 wcbbase0;
1710 __le32 rxwrptr;
1711 __le32 rxrdptr;
1712 __le32 ps_cookie;
1713 __le32 wcbbase1;
1714 __le32 wcbbase2;
1715 __le32 wcbbase3;
1716} __attribute__((packed));
1717
1718static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1719{
1720 struct mwl8k_priv *priv = hw->priv;
1721 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1722 int rc;
1723
1724 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1725 if (cmd == NULL)
1726 return -ENOMEM;
1727
1728 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1729 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1730
1731 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1732 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1733
1734 rc = mwl8k_post_cmd(hw, &cmd->header);
1735
1736 if (!rc) {
1737 int off;
1738
1739 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1740 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1741 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1742 priv->hw_rev = cmd->hw_rev;
1743
1744 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1745 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1746
1747 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1748 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1749
1750 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1751 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1752
1753 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1754 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1755
1756 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1757 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1758
1759 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1760 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1761 }
1762
1763 kfree(cmd);
1764 return rc;
1765}
1766
1767/*
1768 * CMD_SET_HW_SPEC.
1769 */
1770struct mwl8k_cmd_set_hw_spec {
1771 struct mwl8k_cmd_pkt header;
1772 __u8 hw_rev;
1773 __u8 host_interface;
1774 __le16 num_mcaddrs;
1775 __u8 perm_addr[ETH_ALEN];
1776 __le16 region_code;
1777 __le32 fw_rev;
1778 __le32 ps_cookie;
1779 __le32 caps;
1780 __le32 rx_queue_ptr;
1781 __le32 num_tx_queues;
1782 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1783 __le32 flags;
1784 __le32 num_tx_desc_per_queue;
1785 __le32 total_rxd;
1786} __attribute__((packed));
1787
1788#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1789
1790static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1791{
1792 struct mwl8k_priv *priv = hw->priv;
1793 struct mwl8k_cmd_set_hw_spec *cmd;
1794 int rc;
1795 int i;
1796
1797 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1798 if (cmd == NULL)
1799 return -ENOMEM;
1800
1801 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1802 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1803
1804 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1805 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1806 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1807 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1808 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1809 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1810 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1811 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1812
1813 rc = mwl8k_post_cmd(hw, &cmd->header);
1814 kfree(cmd);
1815
1816 return rc;
1817}
1818
a66098da
LB		 1819/*
1820 * CMD_MAC_MULTICAST_ADR.
1821 */
1822struct mwl8k_cmd_mac_multicast_adr {
1823 struct mwl8k_cmd_pkt header;
1824 __le16 action;
1825 __le16 numaddr;
ce9e2e1b 1826 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1827};
1828
d5e30845
LB		 1829#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1830#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1831#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1832#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1833
e81cd2d6 1834static struct mwl8k_cmd_pkt *
447ced07 1835__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1836 int mc_count, struct dev_addr_list *mclist)
a66098da 1837{
e81cd2d6 1838 struct mwl8k_priv *priv = hw->priv;
a66098da 1839 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1840 int size;
e81cd2d6 1841
447ced07 1842 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1843 allmulti = 1;
1844 mc_count = 0;
1845 }
e81cd2d6
LB		 1846
1847 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1848
e81cd2d6 1849 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1850 if (cmd == NULL)
e81cd2d6 1851 return NULL;
a66098da
LB		 1852
1853 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1854 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1855 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1856 MWL8K_ENABLE_RX_BROADCAST);
1857
1858 if (allmulti) {
1859 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1860 } else if (mc_count) {
1861 int i;
1862
1863 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1864 cmd->numaddr = cpu_to_le16(mc_count);
1865 for (i = 0; i < mc_count && mclist; i++) {
1866 if (mclist->da_addrlen != ETH_ALEN) {
1867 kfree(cmd);
1868 return NULL;
1869 }
1870 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1871 mclist = mclist->next;
a66098da 1872 }
a66098da
LB		 1873 }
1874
e81cd2d6 1875 return &cmd->header;
a66098da
LB		 1876}
1877
1878/*
1879 * CMD_802_11_GET_STAT.
1880 */
1881struct mwl8k_cmd_802_11_get_stat {
1882 struct mwl8k_cmd_pkt header;
a66098da
LB		 1883 __le32 stats[64];
1884} __attribute__((packed));
1885
1886#define MWL8K_STAT_ACK_FAILURE 9
1887#define MWL8K_STAT_RTS_FAILURE 12
1888#define MWL8K_STAT_FCS_ERROR 24
1889#define MWL8K_STAT_RTS_SUCCESS 11
1890
1891static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1892 struct ieee80211_low_level_stats *stats)
1893{
1894 struct mwl8k_cmd_802_11_get_stat *cmd;
1895 int rc;
1896
1897 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1898 if (cmd == NULL)
1899 return -ENOMEM;
1900
1901 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1902 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1903
1904 rc = mwl8k_post_cmd(hw, &cmd->header);
1905 if (!rc) {
1906 stats->dot11ACKFailureCount =
1907 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1908 stats->dot11RTSFailureCount =
1909 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1910 stats->dot11FCSErrorCount =
1911 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1912 stats->dot11RTSSuccessCount =
1913 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1914 }
1915 kfree(cmd);
1916
1917 return rc;
1918}
1919
1920/*
1921 * CMD_802_11_RADIO_CONTROL.
1922 */
1923struct mwl8k_cmd_802_11_radio_control {
1924 struct mwl8k_cmd_pkt header;
1925 __le16 action;
1926 __le16 control;
1927 __le16 radio_on;
1928} __attribute__((packed));
1929
c46563b7
LB		 1930static int
1931mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1932{
1933 struct mwl8k_priv *priv = hw->priv;
1934 struct mwl8k_cmd_802_11_radio_control *cmd;
1935 int rc;
1936
c46563b7 1937 if (enable == priv->radio_on && !force)
a66098da
LB		 1938 return 0;
1939
a66098da
LB		 1940 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1941 if (cmd == NULL)
1942 return -ENOMEM;
1943
1944 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1945 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1946 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1947 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1948 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1949
1950 rc = mwl8k_post_cmd(hw, &cmd->header);
1951 kfree(cmd);
1952
1953 if (!rc)
c46563b7 1954 priv->radio_on = enable;
a66098da
LB		 1955
1956 return rc;
1957}
1958
c46563b7
LB		 1959static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1960{
1961 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1962}
1963
1964static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1965{
1966 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1967}
1968
a66098da
LB		 1969static int
1970mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1971{
1972 struct mwl8k_priv *priv;
1973
1974 if (hw == NULL || hw->priv == NULL)
1975 return -EINVAL;
1976 priv = hw->priv;
1977
68ce3884 1978 priv->radio_short_preamble = short_preamble;
a66098da 1979
c46563b7 1980 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1981}
1982
1983/*
1984 * CMD_802_11_RF_TX_POWER.
1985 */
1986#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1987
1988struct mwl8k_cmd_802_11_rf_tx_power {
1989 struct mwl8k_cmd_pkt header;
1990 __le16 action;
1991 __le16 support_level;
1992 __le16 current_level;
1993 __le16 reserved;
1994 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1995} __attribute__((packed));
1996
1997static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1998{
1999 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2000 int rc;
2001
2002 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2003 if (cmd == NULL)
2004 return -ENOMEM;
2005
2006 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2007 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2008 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2009 cmd->support_level = cpu_to_le16(dBm);
2010
2011 rc = mwl8k_post_cmd(hw, &cmd->header);
2012 kfree(cmd);
2013
2014 return rc;
2015}
2016
08b06347
LB		 2017/*
2018 * CMD_RF_ANTENNA.
2019 */
2020struct mwl8k_cmd_rf_antenna {
2021 struct mwl8k_cmd_pkt header;
2022 __le16 antenna;
2023 __le16 mode;
2024} __attribute__((packed));
2025
2026#define MWL8K_RF_ANTENNA_RX 1
2027#define MWL8K_RF_ANTENNA_TX 2
2028
2029static int
2030mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2031{
2032 struct mwl8k_cmd_rf_antenna *cmd;
2033 int rc;
2034
2035 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2036 if (cmd == NULL)
2037 return -ENOMEM;
2038
2039 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2040 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2041 cmd->antenna = cpu_to_le16(antenna);
2042 cmd->mode = cpu_to_le16(mask);
2043
2044 rc = mwl8k_post_cmd(hw, &cmd->header);
2045 kfree(cmd);
2046
2047 return rc;
2048}
2049
a66098da
LB		 2050/*
2051 * CMD_SET_PRE_SCAN.
2052 */
2053struct mwl8k_cmd_set_pre_scan {
2054 struct mwl8k_cmd_pkt header;
2055} __attribute__((packed));
2056
2057static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2058{
2059 struct mwl8k_cmd_set_pre_scan *cmd;
2060 int rc;
2061
2062 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2063 if (cmd == NULL)
2064 return -ENOMEM;
2065
2066 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2067 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2068
2069 rc = mwl8k_post_cmd(hw, &cmd->header);
2070 kfree(cmd);
2071
2072 return rc;
2073}
2074
2075/*
2076 * CMD_SET_POST_SCAN.
2077 */
2078struct mwl8k_cmd_set_post_scan {
2079 struct mwl8k_cmd_pkt header;
2080 __le32 isibss;
d89173f2 2081 __u8 bssid[ETH_ALEN];
a66098da
LB		 2082} __attribute__((packed));
2083
2084static int
ce9e2e1b 2085mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 2086{
2087 struct mwl8k_cmd_set_post_scan *cmd;
2088 int rc;
2089
2090 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2091 if (cmd == NULL)
2092 return -ENOMEM;
2093
2094 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2095 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2096 cmd->isibss = 0;
d89173f2 2097 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2098
2099 rc = mwl8k_post_cmd(hw, &cmd->header);
2100 kfree(cmd);
2101
2102 return rc;
2103}
2104
2105/*
2106 * CMD_SET_RF_CHANNEL.
2107 */
2108struct mwl8k_cmd_set_rf_channel {
2109 struct mwl8k_cmd_pkt header;
2110 __le16 action;
2111 __u8 current_channel;
2112 __le32 channel_flags;
2113} __attribute__((packed));
2114
2115static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2116 struct ieee80211_channel *channel)
2117{
2118 struct mwl8k_cmd_set_rf_channel *cmd;
2119 int rc;
2120
2121 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2122 if (cmd == NULL)
2123 return -ENOMEM;
2124
2125 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2126 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2127 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2128 cmd->current_channel = channel->hw_value;
2129 if (channel->band == IEEE80211_BAND_2GHZ)
2130 cmd->channel_flags = cpu_to_le32(0x00000081);
2131 else
2132 cmd->channel_flags = cpu_to_le32(0x00000000);
2133
2134 rc = mwl8k_post_cmd(hw, &cmd->header);
2135 kfree(cmd);
2136
2137 return rc;
2138}
2139
2140/*
2141 * CMD_SET_SLOT.
2142 */
2143struct mwl8k_cmd_set_slot {
2144 struct mwl8k_cmd_pkt header;
2145 __le16 action;
2146 __u8 short_slot;
2147} __attribute__((packed));
2148
5539bb51 2149static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 2150{
2151 struct mwl8k_cmd_set_slot *cmd;
2152 int rc;
2153
2154 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2155 if (cmd == NULL)
2156 return -ENOMEM;
2157
2158 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2159 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2160 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 2161 cmd->short_slot = short_slot_time;
a66098da
LB		 2162
2163 rc = mwl8k_post_cmd(hw, &cmd->header);
2164 kfree(cmd);
2165
2166 return rc;
2167}
2168
2169/*
2170 * CMD_MIMO_CONFIG.
2171 */
2172struct mwl8k_cmd_mimo_config {
2173 struct mwl8k_cmd_pkt header;
2174 __le32 action;
2175 __u8 rx_antenna_map;
2176 __u8 tx_antenna_map;
2177} __attribute__((packed));
2178
2179static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2180{
2181 struct mwl8k_cmd_mimo_config *cmd;
2182 int rc;
2183
2184 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2185 if (cmd == NULL)
2186 return -ENOMEM;
2187
2188 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2189 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2190 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2191 cmd->rx_antenna_map = rx;
2192 cmd->tx_antenna_map = tx;
2193
2194 rc = mwl8k_post_cmd(hw, &cmd->header);
2195 kfree(cmd);
2196
2197 return rc;
2198}
2199
2200/*
2201 * CMD_ENABLE_SNIFFER.
2202 */
2203struct mwl8k_cmd_enable_sniffer {
2204 struct mwl8k_cmd_pkt header;
2205 __le32 action;
2206} __attribute__((packed));
2207
2208static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2209{
2210 struct mwl8k_cmd_enable_sniffer *cmd;
2211 int rc;
2212
2213 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2214 if (cmd == NULL)
2215 return -ENOMEM;
2216
2217 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2218 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2219 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 2220
2221 rc = mwl8k_post_cmd(hw, &cmd->header);
2222 kfree(cmd);
2223
2224 return rc;
2225}
2226
32060e1b
LB		 2227/*
2228 * CMD_SET_MAC_ADDR.
2229 */
2230struct mwl8k_cmd_set_mac_addr {
2231 struct mwl8k_cmd_pkt header;
259a8e7d
LB		 2232 union {
2233 struct {
2234 __le16 mac_type;
2235 __u8 mac_addr[ETH_ALEN];
2236 } mbss;
2237 __u8 mac_addr[ETH_ALEN];
2238 };
32060e1b
LB		 2239} __attribute__((packed));
2240
2241static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2242{
259a8e7d 2243 struct mwl8k_priv *priv = hw->priv;
32060e1b
LB		 2244 struct mwl8k_cmd_set_mac_addr *cmd;
2245 int rc;
2246
2247 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2248 if (cmd == NULL)
2249 return -ENOMEM;
2250
2251 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2252 cmd->header.length = cpu_to_le16(sizeof(*cmd));
259a8e7d
LB		 2253 if (priv->ap_fw) {
2254 cmd->mbss.mac_type = 0;
2255 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2256 } else {
2257 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2258 }
32060e1b
LB		 2259
2260 rc = mwl8k_post_cmd(hw, &cmd->header);
2261 kfree(cmd);
2262
2263 return rc;
2264}
2265
2266
a66098da 2267/*
ce9e2e1b 2268 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2269 */
2270struct mwl8k_cmd_set_rate_adapt_mode {
2271 struct mwl8k_cmd_pkt header;
2272 __le16 action;
2273 __le16 mode;
2274} __attribute__((packed));
2275
2276static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2277{
2278 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2279 int rc;
2280
2281 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2282 if (cmd == NULL)
2283 return -ENOMEM;
2284
2285 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2286 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2287 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2288 cmd->mode = cpu_to_le16(mode);
2289
2290 rc = mwl8k_post_cmd(hw, &cmd->header);
2291 kfree(cmd);
2292
2293 return rc;
2294}
2295
2296/*
2297 * CMD_SET_WMM_MODE.
2298 */
2299struct mwl8k_cmd_set_wmm {
2300 struct mwl8k_cmd_pkt header;
2301 __le16 action;
2302} __attribute__((packed));
2303
2304static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2305{
2306 struct mwl8k_priv *priv = hw->priv;
2307 struct mwl8k_cmd_set_wmm *cmd;
2308 int rc;
2309
2310 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2311 if (cmd == NULL)
2312 return -ENOMEM;
2313
2314 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2315 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2316 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2317
2318 rc = mwl8k_post_cmd(hw, &cmd->header);
2319 kfree(cmd);
2320
2321 if (!rc)
0439b1f5 2322 priv->wmm_enabled = enable;
a66098da
LB		 2323
2324 return rc;
2325}
2326
2327/*
2328 * CMD_SET_RTS_THRESHOLD.
2329 */
2330struct mwl8k_cmd_rts_threshold {
2331 struct mwl8k_cmd_pkt header;
2332 __le16 action;
2333 __le16 threshold;
2334} __attribute__((packed));
2335
2336static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2337 u16 action, u16 threshold)
a66098da
LB		 2338{
2339 struct mwl8k_cmd_rts_threshold *cmd;
2340 int rc;
2341
2342 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2343 if (cmd == NULL)
2344 return -ENOMEM;
2345
2346 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2347 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2348 cmd->action = cpu_to_le16(action);
733d3067 2349 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2350
2351 rc = mwl8k_post_cmd(hw, &cmd->header);
2352 kfree(cmd);
2353
2354 return rc;
2355}
2356
2357/*
2358 * CMD_SET_EDCA_PARAMS.
2359 */
2360struct mwl8k_cmd_set_edca_params {
2361 struct mwl8k_cmd_pkt header;
2362
2363 /* See MWL8K_SET_EDCA_XXX below */
2364 __le16 action;
2365
2366 /* TX opportunity in units of 32 us */
2367 __le16 txop;
2368
2e484c89
LB		 2369 union {
2370 struct {
2371 /* Log exponent of max contention period: 0...15 */
2372 __le32 log_cw_max;
2373
2374 /* Log exponent of min contention period: 0...15 */
2375 __le32 log_cw_min;
2376
2377 /* Adaptive interframe spacing in units of 32us */
2378 __u8 aifs;
2379
2380 /* TX queue to configure */
2381 __u8 txq;
2382 } ap;
2383 struct {
2384 /* Log exponent of max contention period: 0...15 */
2385 __u8 log_cw_max;
a66098da 2386
2e484c89
LB		 2387 /* Log exponent of min contention period: 0...15 */
2388 __u8 log_cw_min;
a66098da 2389
2e484c89
LB		 2390 /* Adaptive interframe spacing in units of 32us */
2391 __u8 aifs;
a66098da 2392
2e484c89
LB		 2393 /* TX queue to configure */
2394 __u8 txq;
2395 } sta;
2396 };
a66098da
LB		 2397} __attribute__((packed));
2398
a66098da
LB		 2399#define MWL8K_SET_EDCA_CW 0x01
2400#define MWL8K_SET_EDCA_TXOP 0x02
2401#define MWL8K_SET_EDCA_AIFS 0x04
2402
2403#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2404 MWL8K_SET_EDCA_TXOP | \
2405 MWL8K_SET_EDCA_AIFS)
2406
2407static int
2408mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2409 __u16 cw_min, __u16 cw_max,
2410 __u8 aifs, __u16 txop)
2411{
2e484c89 2412 struct mwl8k_priv *priv = hw->priv;
a66098da 2413 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2414 int rc;
2415
2416 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2417 if (cmd == NULL)
2418 return -ENOMEM;
2419
22995b24
LB		 2420 /*
2421 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2422 * this call.
2423 */
2424 qnum ^= !(qnum >> 1);
2425
a66098da
LB		 2426 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2427 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2428 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2429 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2430 if (priv->ap_fw) {
2431 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2432 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2433 cmd->ap.aifs = aifs;
2434 cmd->ap.txq = qnum;
2435 } else {
2436 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2437 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2438 cmd->sta.aifs = aifs;
2439 cmd->sta.txq = qnum;
2440 }
a66098da
LB		 2441
2442 rc = mwl8k_post_cmd(hw, &cmd->header);
2443 kfree(cmd);
2444
2445 return rc;
2446}
2447
2448/*
2449 * CMD_FINALIZE_JOIN.
2450 */
2451
2452/* FJ beacon buffer size is compiled into the firmware. */
2453#define MWL8K_FJ_BEACON_MAXLEN 128
2454
2455struct mwl8k_cmd_finalize_join {
2456 struct mwl8k_cmd_pkt header;
2457 __le32 sleep_interval; /* Number of beacon periods to sleep */
2458 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2459} __attribute__((packed));
2460
2461static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2462 __u16 framelen, __u16 dtim)
2463{
2464 struct mwl8k_cmd_finalize_join *cmd;
2465 struct ieee80211_mgmt *payload = frame;
2466 u16 hdrlen;
2467 u32 payload_len;
2468 int rc;
2469
2470 if (frame == NULL)
2471 return -EINVAL;
2472
2473 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2474 if (cmd == NULL)
2475 return -ENOMEM;
2476
2477 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2478 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2479 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2480
2481 hdrlen = ieee80211_hdrlen(payload->frame_control);
2482
2483 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2484
2485 /* XXX TBD Might just have to abort and return an error */
2486 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2487 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2488 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2489 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2490
ce9e2e1b
LB		 2491 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2492 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2493
2494 if (payload && payload_len)
2495 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2496
2497 rc = mwl8k_post_cmd(hw, &cmd->header);
2498 kfree(cmd);
2499 return rc;
2500}
2501
2502/*
2503 * CMD_UPDATE_STADB.
2504 */
2505struct mwl8k_cmd_update_sta_db {
2506 struct mwl8k_cmd_pkt header;
2507
2508 /* See STADB_ACTION_TYPE */
2509 __le32 action;
2510
2511 /* Peer MAC address */
d89173f2 2512 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2513
2514 __le32 reserved;
2515
2516 /* Peer info - valid during add/update. */
2517 struct peer_capability_info peer_info;
2518} __attribute__((packed));
2519
2520static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2521 struct ieee80211_vif *vif, __u32 action)
2522{
2523 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2524 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2525 struct mwl8k_cmd_update_sta_db *cmd;
2526 struct peer_capability_info *peer_info;
a66098da 2527 int rc;
a66098da
LB		 2528
2529 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2530 if (cmd == NULL)
2531 return -ENOMEM;
2532
2533 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2534 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2535
2536 cmd->action = cpu_to_le32(action);
2537 peer_info = &cmd->peer_info;
d89173f2 2538 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2539
2540 switch (action) {
2541 case MWL8K_STA_DB_ADD_ENTRY:
2542 case MWL8K_STA_DB_MODIFY_ENTRY:
2543 /* Build peer_info block */
2544 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2545 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
140eb5e2
LB		 2546 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2547 sizeof(mwl8k_rateids));
a66098da
LB		 2548 peer_info->interop = 1;
2549 peer_info->amsdu_enabled = 0;
2550
a66098da
LB		 2551 rc = mwl8k_post_cmd(hw, &cmd->header);
2552 if (rc == 0)
2553 mv_vif->peer_id = peer_info->station_id;
2554
2555 break;
2556
2557 case MWL8K_STA_DB_DEL_ENTRY:
2558 case MWL8K_STA_DB_FLUSH:
2559 default:
2560 rc = mwl8k_post_cmd(hw, &cmd->header);
2561 if (rc == 0)
2562 mv_vif->peer_id = 0;
2563 break;
2564 }
2565 kfree(cmd);
2566
2567 return rc;
2568}
2569
2570/*
2571 * CMD_SET_AID.
2572 */
a66098da
LB		 2573#define MWL8K_FRAME_PROT_DISABLED 0x00
2574#define MWL8K_FRAME_PROT_11G 0x07
2575#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2576#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2577
2578struct mwl8k_cmd_update_set_aid {
2579 struct mwl8k_cmd_pkt header;
2580 __le16 aid;
2581
2582 /* AP's MAC address (BSSID) */
d89173f2 2583 __u8 bssid[ETH_ALEN];
a66098da 2584 __le16 protection_mode;
140eb5e2 2585 __u8 supp_rates[14];
a66098da
LB		 2586} __attribute__((packed));
2587
2588static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2589 struct ieee80211_vif *vif)
2590{
2591 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2592 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2593 struct mwl8k_cmd_update_set_aid *cmd;
a66098da
LB		 2594 u16 prot_mode;
2595 int rc;
2596
2597 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2598 if (cmd == NULL)
2599 return -ENOMEM;
2600
2601 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2602 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2603 cmd->aid = cpu_to_le16(info->aid);
2604
d89173f2 2605 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2606
a66098da
LB		 2607 if (info->use_cts_prot) {
2608 prot_mode = MWL8K_FRAME_PROT_11G;
2609 } else {
9ed6bcce 2610 switch (info->ht_operation_mode &
a66098da
LB		 2611 IEEE80211_HT_OP_MODE_PROTECTION) {
2612 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2613 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2614 break;
2615 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2616 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2617 break;
2618 default:
2619 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2620 break;
2621 }
2622 }
a66098da
LB		 2623 cmd->protection_mode = cpu_to_le16(prot_mode);
2624
140eb5e2 2625 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2626
2627 rc = mwl8k_post_cmd(hw, &cmd->header);
2628 kfree(cmd);
2629
2630 return rc;
2631}
2632
2633/*
2634 * CMD_SET_RATE.
2635 */
2636struct mwl8k_cmd_update_rateset {
2637 struct mwl8k_cmd_pkt header;
140eb5e2 2638 __u8 legacy_rates[14];
a66098da
LB		 2639
2640 /* Bitmap for supported MCS codes. */
0b5351a8
LB		 2641 __u8 mcs_set[16];
2642 __u8 reserved[16];
a66098da
LB		 2643} __attribute__((packed));
2644
2645static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2646 struct ieee80211_vif *vif)
2647{
a66098da 2648 struct mwl8k_cmd_update_rateset *cmd;
a66098da
LB		 2649 int rc;
2650
2651 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2652 if (cmd == NULL)
2653 return -ENOMEM;
2654
2655 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2656 cmd->header.length = cpu_to_le16(sizeof(*cmd));
140eb5e2 2657 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2658
2659 rc = mwl8k_post_cmd(hw, &cmd->header);
2660 kfree(cmd);
2661
2662 return rc;
2663}
2664
2665/*
2666 * CMD_USE_FIXED_RATE.
2667 */
2668#define MWL8K_RATE_TABLE_SIZE 8
2669#define MWL8K_UCAST_RATE 0
a66098da
LB		 2670#define MWL8K_USE_AUTO_RATE 0x0002
2671
2672struct mwl8k_rate_entry {
2673 /* Set to 1 if HT rate, 0 if legacy. */
2674 __le32 is_ht_rate;
2675
2676 /* Set to 1 to use retry_count field. */
2677 __le32 enable_retry;
2678
2679 /* Specified legacy rate or MCS. */
2680 __le32 rate;
2681
2682 /* Number of allowed retries. */
2683 __le32 retry_count;
2684} __attribute__((packed));
2685
2686struct mwl8k_rate_table {
2687 /* 1 to allow specified rate and below */
2688 __le32 allow_rate_drop;
2689 __le32 num_rates;
2690 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2691} __attribute__((packed));
2692
2693struct mwl8k_cmd_use_fixed_rate {
2694 struct mwl8k_cmd_pkt header;
2695 __le32 action;
2696 struct mwl8k_rate_table rate_table;
2697
2698 /* Unicast, Broadcast or Multicast */
2699 __le32 rate_type;
2700 __le32 reserved1;
2701 __le32 reserved2;
2702} __attribute__((packed));
2703
2704static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2705 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2706{
2707 struct mwl8k_cmd_use_fixed_rate *cmd;
2708 int count;
2709 int rc;
2710
2711 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2712 if (cmd == NULL)
2713 return -ENOMEM;
2714
2715 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2716 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2717
2718 cmd->action = cpu_to_le32(action);
2719 cmd->rate_type = cpu_to_le32(rate_type);
2720
2721 if (rate_table != NULL) {
c2c357ce
LB		 2722 /*
2723 * Copy over each field manually so that endian
2724 * conversion can be done.
2725 */
a66098da
LB		 2726 cmd->rate_table.allow_rate_drop =
2727 cpu_to_le32(rate_table->allow_rate_drop);
2728 cmd->rate_table.num_rates =
2729 cpu_to_le32(rate_table->num_rates);
2730
2731 for (count = 0; count < rate_table->num_rates; count++) {
2732 struct mwl8k_rate_entry *dst =
2733 &cmd->rate_table.rate_entry[count];
2734 struct mwl8k_rate_entry *src =
2735 &rate_table->rate_entry[count];
2736
2737 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2738 dst->enable_retry = cpu_to_le32(src->enable_retry);
2739 dst->rate = cpu_to_le32(src->rate);
2740 dst->retry_count = cpu_to_le32(src->retry_count);
2741 }
2742 }
2743
2744 rc = mwl8k_post_cmd(hw, &cmd->header);
2745 kfree(cmd);
2746
2747 return rc;
2748}
2749
2750
2751/*
2752 * Interrupt handling.
2753 */
2754static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2755{
2756 struct ieee80211_hw *hw = dev_id;
2757 struct mwl8k_priv *priv = hw->priv;
2758 u32 status;
2759
2760 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2761 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2762
a66098da
LB		 2763 if (!status)
2764 return IRQ_NONE;
2765
2766 if (status & MWL8K_A2H_INT_TX_DONE)
2767 tasklet_schedule(&priv->tx_reclaim_task);
2768
2769 if (status & MWL8K_A2H_INT_RX_READY) {
2770 while (rxq_process(hw, 0, 1))
2771 rxq_refill(hw, 0, 1);
2772 }
2773
2774 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2775 if (priv->hostcmd_wait != NULL)
a66098da 2776 complete(priv->hostcmd_wait);
a66098da
LB		 2777 }
2778
2779 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2780 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2781 priv->radio_on && priv->pending_tx_pkts)
618952a7 2782 mwl8k_tx_start(priv);
a66098da
LB		 2783 }
2784
2785 return IRQ_HANDLED;
2786}
2787
2788
2789/*
2790 * Core driver operations.
2791 */
2792static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2793{
2794 struct mwl8k_priv *priv = hw->priv;
2795 int index = skb_get_queue_mapping(skb);
2796 int rc;
2797
2798 if (priv->current_channel == NULL) {
2799 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2800 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2801 dev_kfree_skb(skb);
2802 return NETDEV_TX_OK;
2803 }
2804
2805 rc = mwl8k_txq_xmit(hw, index, skb);
2806
2807 return rc;
2808}
2809
a66098da
LB		 2810static int mwl8k_start(struct ieee80211_hw *hw)
2811{
a66098da
LB		 2812 struct mwl8k_priv *priv = hw->priv;
2813 int rc;
2814
a0607fd3 2815 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 2816 IRQF_SHARED, MWL8K_NAME, hw);
2817 if (rc) {
2818 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2819 wiphy_name(hw->wiphy));
2ec610cb 2820 return -EIO;
a66098da
LB		 2821 }
2822
2ec610cb
LB		 2823 /* Enable tx reclaim tasklet */
2824 tasklet_enable(&priv->tx_reclaim_task);
2825
a66098da 2826 /* Enable interrupts */
c23b5a69 2827 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2828
2ec610cb
LB		 2829 rc = mwl8k_fw_lock(hw);
2830 if (!rc) {
2831 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2832
5e4cf166
LB		 2833 if (!priv->ap_fw) {
2834 if (!rc)
2835 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2836
5e4cf166
LB		 2837 if (!rc)
2838 rc = mwl8k_cmd_set_pre_scan(hw);
2839
2840 if (!rc)
2841 rc = mwl8k_cmd_set_post_scan(hw,
2842 "\x00\x00\x00\x00\x00\x00");
2843 }
2ec610cb
LB		 2844
2845 if (!rc)
2846 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2847
2ec610cb
LB		 2848 if (!rc)
2849 rc = mwl8k_set_wmm(hw, 0);
a66098da 2850
2ec610cb
LB		 2851 mwl8k_fw_unlock(hw);
2852 }
2853
2854 if (rc) {
2855 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2856 free_irq(priv->pdev->irq, hw);
2857 tasklet_disable(&priv->tx_reclaim_task);
2858 }
a66098da
LB		 2859
2860 return rc;
2861}
2862
a66098da
LB		 2863static void mwl8k_stop(struct ieee80211_hw *hw)
2864{
a66098da
LB		 2865 struct mwl8k_priv *priv = hw->priv;
2866 int i;
2867
d3cea0b8 2868 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2869
2870 ieee80211_stop_queues(hw);
2871
a66098da 2872 /* Disable interrupts */
a66098da 2873 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2874 free_irq(priv->pdev->irq, hw);
2875
2876 /* Stop finalize join worker */
2877 cancel_work_sync(&priv->finalize_join_worker);
2878 if (priv->beacon_skb != NULL)
2879 dev_kfree_skb(priv->beacon_skb);
2880
2881 /* Stop tx reclaim tasklet */
2882 tasklet_disable(&priv->tx_reclaim_task);
2883
a66098da
LB		 2884 /* Return all skbs to mac80211 */
2885 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2886 mwl8k_txq_reclaim(hw, i, 1);
2887}
2888
2889static int mwl8k_add_interface(struct ieee80211_hw *hw,
2890 struct ieee80211_if_init_conf *conf)
2891{
2892 struct mwl8k_priv *priv = hw->priv;
2893 struct mwl8k_vif *mwl8k_vif;
2894
2895 /*
2896 * We only support one active interface at a time.
2897 */
2898 if (priv->vif != NULL)
2899 return -EBUSY;
2900
2901 /*
2902 * We only support managed interfaces for now.
2903 */
240e86ef 2904 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2905 return -EINVAL;
2906
a43c49a8
LB		 2907 /*
2908 * Reject interface creation if sniffer mode is active, as
2909 * STA operation is mutually exclusive with hardware sniffer
2910 * mode.
2911 */
2912 if (priv->sniffer_enabled) {
2913 printk(KERN_INFO "%s: unable to create STA "
2914 "interface due to sniffer mode being enabled\n",
2915 wiphy_name(hw->wiphy));
2916 return -EINVAL;
2917 }
2918
a66098da
LB		 2919 /* Clean out driver private area */
2920 mwl8k_vif = MWL8K_VIF(conf->vif);
2921 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2922
32060e1b
LB		 2923 /* Set and save the mac address */
2924 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2925 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2926
2927 /* Back pointer to parent config block */
2928 mwl8k_vif->priv = priv;
2929
a66098da
LB		 2930 /* Set Initial sequence number to zero */
2931 mwl8k_vif->seqno = 0;
2932
2933 priv->vif = conf->vif;
2934 priv->current_channel = NULL;
2935
2936 return 0;
2937}
2938
2939static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2940 struct ieee80211_if_init_conf *conf)
2941{
2942 struct mwl8k_priv *priv = hw->priv;
2943
2944 if (priv->vif == NULL)
2945 return;
2946
32060e1b
LB		 2947 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2948
a66098da
LB		 2949 priv->vif = NULL;
2950}
2951
ee03a932 2952static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2953{
a66098da
LB		 2954 struct ieee80211_conf *conf = &hw->conf;
2955 struct mwl8k_priv *priv = hw->priv;
ee03a932 2956 int rc;
a66098da 2957
7595d67a
LB		 2958 if (conf->flags & IEEE80211_CONF_IDLE) {
2959 mwl8k_cmd_802_11_radio_disable(hw);
2960 priv->current_channel = NULL;
ee03a932 2961 return 0;
7595d67a
LB		 2962 }
2963
ee03a932
LB		 2964 rc = mwl8k_fw_lock(hw);
2965 if (rc)
2966 return rc;
a66098da 2967
ee03a932
LB		 2968 rc = mwl8k_cmd_802_11_radio_enable(hw);
2969 if (rc)
2970 goto out;
a66098da 2971
ee03a932
LB		 2972 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2973 if (rc)
2974 goto out;
2975
2976 priv->current_channel = conf->channel;
a66098da
LB		 2977
2978 if (conf->power_level > 18)
2979 conf->power_level = 18;
ee03a932
LB		 2980 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2981 if (rc)
2982 goto out;
a66098da 2983
08b06347
LB		 2984 if (priv->ap_fw) {
2985 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2986 if (!rc)
2987 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2988 } else {
2989 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2990 }
a66098da 2991
ee03a932
LB		 2992out:
2993 mwl8k_fw_unlock(hw);
a66098da 2994
ee03a932 2995 return rc;
a66098da
LB		 2996}
2997
3a980d0a
LB		 2998static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2999 struct ieee80211_vif *vif,
3000 struct ieee80211_bss_conf *info,
3001 u32 changed)
a66098da 3002{
a66098da
LB		 3003 struct mwl8k_priv *priv = hw->priv;
3004 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 3005 int rc;
3006
3007 if (changed & BSS_CHANGED_BSSID)
3008 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3009
3010 if ((changed & BSS_CHANGED_ASSOC) == 0)
3011 return;
a66098da 3012
a66098da
LB		 3013 priv->capture_beacon = false;
3014
3a980d0a 3015 rc = mwl8k_fw_lock(hw);
942457d6 3016 if (rc)
3a980d0a
LB		 3017 return;
3018
a66098da
LB		 3019 if (info->assoc) {
3020 memcpy(&mwl8k_vif->bss_info, info,
3021 sizeof(struct ieee80211_bss_conf));
3022
3023 /* Install rates */
3a980d0a
LB		 3024 rc = mwl8k_update_rateset(hw, vif);
3025 if (rc)
3026 goto out;
a66098da
LB		 3027
3028 /* Turn on rate adaptation */
3a980d0a
LB		 3029 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3030 MWL8K_UCAST_RATE, NULL);
3031 if (rc)
3032 goto out;
a66098da
LB		 3033
3034 /* Set radio preamble */
3a980d0a
LB		 3035 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3036 if (rc)
3037 goto out;
a66098da
LB		 3038
3039 /* Set slot time */
3a980d0a
LB		 3040 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3041 if (rc)
3042 goto out;
a66098da
LB		 3043
3044 /* Update peer rate info */
3a980d0a
LB		 3045 rc = mwl8k_cmd_update_sta_db(hw, vif,
3046 MWL8K_STA_DB_MODIFY_ENTRY);
3047 if (rc)
3048 goto out;
a66098da
LB		 3049
3050 /* Set AID */
3a980d0a
LB		 3051 rc = mwl8k_cmd_set_aid(hw, vif);
3052 if (rc)
3053 goto out;
a66098da
LB		 3054
3055 /*
3056 * Finalize the join. Tell rx handler to process
3057 * next beacon from our BSSID.
3058 */
d89173f2 3059 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 3060 priv->capture_beacon = true;
3061 } else {
3a980d0a 3062 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 3063 memset(&mwl8k_vif->bss_info, 0,
3064 sizeof(struct ieee80211_bss_conf));
d89173f2 3065 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 3066 }
3067
3a980d0a
LB		 3068out:
3069 mwl8k_fw_unlock(hw);
a66098da
LB		 3070}
3071
e81cd2d6
LB		 3072static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3073 int mc_count, struct dev_addr_list *mclist)
3074{
3075 struct mwl8k_cmd_pkt *cmd;
3076
447ced07
LB		 3077 /*
3078 * Synthesize and return a command packet that programs the
3079 * hardware multicast address filter. At this point we don't
3080 * know whether FIF_ALLMULTI is being requested, but if it is,
3081 * we'll end up throwing this packet away and creating a new
3082 * one in mwl8k_configure_filter().
3083 */
3084 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3085
3086 return (unsigned long)cmd;
3087}
3088
a43c49a8
LB		 3089static int
3090mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3091 unsigned int changed_flags,
3092 unsigned int *total_flags)
3093{
3094 struct mwl8k_priv *priv = hw->priv;
3095
3096 /*
3097 * Hardware sniffer mode is mutually exclusive with STA
3098 * operation, so refuse to enable sniffer mode if a STA
3099 * interface is active.
3100 */
3101 if (priv->vif != NULL) {
3102 if (net_ratelimit())
3103 printk(KERN_INFO "%s: not enabling sniffer "
3104 "mode because STA interface is active\n",
3105 wiphy_name(hw->wiphy));
3106 return 0;
3107 }
3108
3109 if (!priv->sniffer_enabled) {
3110 if (mwl8k_enable_sniffer(hw, 1))
3111 return 0;
3112 priv->sniffer_enabled = true;
3113 }
3114
3115 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3116 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3117 FIF_OTHER_BSS;
3118
3119 return 1;
3120}
3121
e6935ea1
LB		 3122static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3123 unsigned int changed_flags,
3124 unsigned int *total_flags,
3125 u64 multicast)
3126{
3127 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3128 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3129
c0adae2c
LB		 3130 /*
3131 * AP firmware doesn't allow fine-grained control over
3132 * the receive filter.
3133 */
3134 if (priv->ap_fw) {
3135 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3136 kfree(cmd);
3137 return;
3138 }
3139
a43c49a8
LB		 3140 /*
3141 * Enable hardware sniffer mode if FIF_CONTROL or
3142 * FIF_OTHER_BSS is requested.
3143 */
3144 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3145 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3146 kfree(cmd);
3147 return;
3148 }
a66098da 3149
e6935ea1 3150 /* Clear unsupported feature flags */
447ced07 3151 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3152
e6935ea1
LB		 3153 if (mwl8k_fw_lock(hw))
3154 return;
a66098da 3155
a43c49a8
LB		 3156 if (priv->sniffer_enabled) {
3157 mwl8k_enable_sniffer(hw, 0);
3158 priv->sniffer_enabled = false;
3159 }
3160
e6935ea1 3161 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3162 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3163 /*
3164 * Disable the BSS filter.
3165 */
e6935ea1 3166 mwl8k_cmd_set_pre_scan(hw);
77165d88 3167 } else {
a94cc97e
LB		 3168 u8 *bssid;
3169
77165d88
LB		 3170 /*
3171 * Enable the BSS filter.
3172 *
3173 * If there is an active STA interface, use that
3174 * interface's BSSID, otherwise use a dummy one
3175 * (where the OUI part needs to be nonzero for
3176 * the BSSID to be accepted by POST_SCAN).
3177 */
3178 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 3179 if (priv->vif != NULL)
3180 bssid = MWL8K_VIF(priv->vif)->bssid;
3181
e6935ea1 3182 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3183 }
3184 }
3185
447ced07
LB		 3186 /*
3187 * If FIF_ALLMULTI is being requested, throw away the command
3188 * packet that ->prepare_multicast() built and replace it with
3189 * a command packet that enables reception of all multicast
3190 * packets.
3191 */
3192 if (*total_flags & FIF_ALLMULTI) {
3193 kfree(cmd);
3194 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3195 }
3196
3197 if (cmd != NULL) {
3198 mwl8k_post_cmd(hw, cmd);
3199 kfree(cmd);
e6935ea1 3200 }
a66098da 3201
e6935ea1 3202 mwl8k_fw_unlock(hw);
a66098da
LB		 3203}
3204
a66098da
LB		 3205static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3206{
733d3067 3207 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3208}
3209
a66098da
LB		 3210static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3211 const struct ieee80211_tx_queue_params *params)
3212{
3e4f542c 3213 struct mwl8k_priv *priv = hw->priv;
a66098da 3214 int rc;
a66098da 3215
3e4f542c
LB		 3216 rc = mwl8k_fw_lock(hw);
3217 if (!rc) {
3218 if (!priv->wmm_enabled)
3219 rc = mwl8k_set_wmm(hw, 1);
a66098da 3220
3e4f542c
LB		 3221 if (!rc)
3222 rc = mwl8k_set_edca_params(hw, queue,
3223 params->cw_min,
3224 params->cw_max,
3225 params->aifs,
3226 params->txop);
3227
3228 mwl8k_fw_unlock(hw);
a66098da 3229 }
3e4f542c 3230
a66098da
LB		 3231 return rc;
3232}
3233
3234static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3235 struct ieee80211_tx_queue_stats *stats)
3236{
3237 struct mwl8k_priv *priv = hw->priv;
3238 struct mwl8k_tx_queue *txq;
3239 int index;
3240
3241 spin_lock_bh(&priv->tx_lock);
3242 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3243 txq = priv->txq + index;
45eb400d 3244 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3245 sizeof(struct ieee80211_tx_queue_stats));
3246 }
3247 spin_unlock_bh(&priv->tx_lock);
a66098da 3248
954ef509 3249 return 0;
a66098da
LB		 3250}
3251
3252static int mwl8k_get_stats(struct ieee80211_hw *hw,
3253 struct ieee80211_low_level_stats *stats)
3254{
954ef509 3255 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 3256}
3257
3258static const struct ieee80211_ops mwl8k_ops = {
3259 .tx = mwl8k_tx,
3260 .start = mwl8k_start,
3261 .stop = mwl8k_stop,
3262 .add_interface = mwl8k_add_interface,
3263 .remove_interface = mwl8k_remove_interface,
3264 .config = mwl8k_config,
a66098da 3265 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3266 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3267 .configure_filter = mwl8k_configure_filter,
3268 .set_rts_threshold = mwl8k_set_rts_threshold,
3269 .conf_tx = mwl8k_conf_tx,
3270 .get_tx_stats = mwl8k_get_tx_stats,
3271 .get_stats = mwl8k_get_stats,
3272};
3273
3274static void mwl8k_tx_reclaim_handler(unsigned long data)
3275{
3276 int i;
3277 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3278 struct mwl8k_priv *priv = hw->priv;
3279
3280 spin_lock_bh(&priv->tx_lock);
3281 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3282 mwl8k_txq_reclaim(hw, i, 0);
3283
88de754a 3284 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3285 complete(priv->tx_wait);
3286 priv->tx_wait = NULL;
a66098da
LB		 3287 }
3288 spin_unlock_bh(&priv->tx_lock);
3289}
3290
3291static void mwl8k_finalize_join_worker(struct work_struct *work)
3292{
3293 struct mwl8k_priv *priv =
3294 container_of(work, struct mwl8k_priv, finalize_join_worker);
3295 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3296 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3297
3298 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3299 dev_kfree_skb(skb);
3300
3301 priv->beacon_skb = NULL;
3302}
3303
bcb628d5
JL		 3304enum {
3305 MWL8687 = 0,
3306 MWL8366,
6f6d1e9a
LB		 3307};
3308
bcb628d5
JL		 3309static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3310 {
3311 .part_name = "88w8687",
3312 .helper_image = "mwl8k/helper_8687.fw",
3313 .fw_image = "mwl8k/fmimage_8687.fw",
3314 .rxd_ops = &rxd_8687_ops,
3315 .modes = BIT(NL80211_IFTYPE_STATION),
3316 },
3317 {
3318 .part_name = "88w8366",
3319 .helper_image = "mwl8k/helper_8366.fw",
3320 .fw_image = "mwl8k/fmimage_8366.fw",
3321 .rxd_ops = &rxd_8366_ops,
3322 .modes = 0,
3323 },
45a390dd
LB		 3324};
3325
3326static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
bcb628d5
JL		 3327 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3328 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3329 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3330 { },
45a390dd
LB		 3331};
3332MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3333
a66098da
LB		 3334static int __devinit mwl8k_probe(struct pci_dev *pdev,
3335 const struct pci_device_id *id)
3336{
2aa7b01f 3337 static int printed_version = 0;
a66098da
LB		 3338 struct ieee80211_hw *hw;
3339 struct mwl8k_priv *priv;
a66098da
LB		 3340 int rc;
3341 int i;
2aa7b01f
LB		 3342
3343 if (!printed_version) {
3344 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3345 printed_version = 1;
3346 }
a66098da
LB		 3347
3348 rc = pci_enable_device(pdev);
3349 if (rc) {
3350 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3351 MWL8K_NAME);
3352 return rc;
3353 }
3354
3355 rc = pci_request_regions(pdev, MWL8K_NAME);
3356 if (rc) {
3357 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3358 MWL8K_NAME);
3359 return rc;
3360 }
3361
3362 pci_set_master(pdev);
3363
3364 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3365 if (hw == NULL) {
3366 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3367 rc = -ENOMEM;
3368 goto err_free_reg;
3369 }
3370
3371 priv = hw->priv;
3372 priv->hw = hw;
3373 priv->pdev = pdev;
bcb628d5 3374 priv->device_info = &mwl8k_info_tbl[id->driver_data];
54bc3a0d 3375 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3376 priv->sniffer_enabled = false;
0439b1f5 3377 priv->wmm_enabled = false;
a66098da 3378 priv->pending_tx_pkts = 0;
a66098da 3379
a66098da
LB		 3380 SET_IEEE80211_DEV(hw, &pdev->dev);
3381 pci_set_drvdata(pdev, hw);
3382
5b9482dd
LB		 3383 priv->sram = pci_iomap(pdev, 0, 0x10000);
3384 if (priv->sram == NULL) {
3385 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3386 wiphy_name(hw->wiphy));
a66098da
LB		 3387 goto err_iounmap;
3388 }
3389
5b9482dd
LB		 3390 /*
3391 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3392 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3393 */
3394 priv->regs = pci_iomap(pdev, 1, 0x10000);
3395 if (priv->regs == NULL) {
3396 priv->regs = pci_iomap(pdev, 2, 0x10000);
3397 if (priv->regs == NULL) {
3398 printk(KERN_ERR "%s: Cannot map device registers\n",
3399 wiphy_name(hw->wiphy));
3400 goto err_iounmap;
3401 }
3402 }
3403
a66098da
LB		 3404 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3405 priv->band.band = IEEE80211_BAND_2GHZ;
3406 priv->band.channels = priv->channels;
3407 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3408 priv->band.bitrates = priv->rates;
3409 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3410 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3411
3412 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3413 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3414
3415 /*
3416 * Extra headroom is the size of the required DMA header
3417 * minus the size of the smallest 802.11 frame (CTS frame).
3418 */
3419 hw->extra_tx_headroom =
3420 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3421
3422 hw->channel_change_time = 10;
3423
3424 hw->queues = MWL8K_TX_QUEUES;
3425
547810e3 3426 hw->wiphy->interface_modes = priv->device_info->modes;
a66098da
LB		 3427
3428 /* Set rssi and noise values to dBm */
ce9e2e1b 3429 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3430 hw->vif_data_size = sizeof(struct mwl8k_vif);
3431 priv->vif = NULL;
3432
3433 /* Set default radio state and preamble */
c46563b7 3434 priv->radio_on = 0;
68ce3884 3435 priv->radio_short_preamble = 0;
a66098da
LB		 3436
3437 /* Finalize join worker */
3438 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3439
3440 /* TX reclaim tasklet */
3441 tasklet_init(&priv->tx_reclaim_task,
3442 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3443 tasklet_disable(&priv->tx_reclaim_task);
3444
a66098da
LB		 3445 /* Power management cookie */
3446 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3447 if (priv->cookie == NULL)
3448 goto err_iounmap;
3449
3450 rc = mwl8k_rxq_init(hw, 0);
3451 if (rc)
3452 goto err_iounmap;
3453 rxq_refill(hw, 0, INT_MAX);
3454
618952a7
LB		 3455 mutex_init(&priv->fw_mutex);
3456 priv->fw_mutex_owner = NULL;
3457 priv->fw_mutex_depth = 0;
618952a7
LB		 3458 priv->hostcmd_wait = NULL;
3459
a66098da
LB		 3460 spin_lock_init(&priv->tx_lock);
3461
88de754a
LB		 3462 priv->tx_wait = NULL;
3463
a66098da
LB		 3464 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3465 rc = mwl8k_txq_init(hw, i);
3466 if (rc)
3467 goto err_free_queues;
3468 }
3469
3470 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3471 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3472 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3473 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3474
a0607fd3 3475 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3476 IRQF_SHARED, MWL8K_NAME, hw);
3477 if (rc) {
3478 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3479 wiphy_name(hw->wiphy));
a66098da
LB		 3480 goto err_free_queues;
3481 }
3482
3483 /* Reset firmware and hardware */
3484 mwl8k_hw_reset(priv);
3485
3486 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3487 rc = mwl8k_request_firmware(priv);
a66098da 3488 if (rc) {
c2c357ce
LB		 3489 printk(KERN_ERR "%s: Firmware files not found\n",
3490 wiphy_name(hw->wiphy));
a66098da
LB		 3491 goto err_free_irq;
3492 }
3493
3494 /* Load firmware into hardware */
c2c357ce 3495 rc = mwl8k_load_firmware(hw);
a66098da 3496 if (rc) {
c2c357ce
LB		 3497 printk(KERN_ERR "%s: Cannot start firmware\n",
3498 wiphy_name(hw->wiphy));
a66098da
LB		 3499 goto err_stop_firmware;
3500 }
3501
3502 /* Reclaim memory once firmware is successfully loaded */
3503 mwl8k_release_firmware(priv);
3504
3505 /*
3506 * Temporarily enable interrupts. Initial firmware host
3507 * commands use interrupts and avoids polling. Disable
3508 * interrupts when done.
3509 */
c23b5a69 3510 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3511
3512 /* Get config data, mac addrs etc */
42fba21d
LB		 3513 if (priv->ap_fw) {
3514 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3515 if (!rc)
3516 rc = mwl8k_cmd_set_hw_spec(hw);
3517 } else {
3518 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3519 }
a66098da 3520 if (rc) {
c2c357ce
LB		 3521 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3522 wiphy_name(hw->wiphy));
a66098da
LB		 3523 goto err_stop_firmware;
3524 }
3525
3526 /* Turn radio off */
c46563b7 3527 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3528 if (rc) {
c2c357ce 3529 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3530 goto err_stop_firmware;
3531 }
3532
32060e1b
LB		 3533 /* Clear MAC address */
3534 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3535 if (rc) {
3536 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3537 wiphy_name(hw->wiphy));
3538 goto err_stop_firmware;
3539 }
3540
a66098da 3541 /* Disable interrupts */
a66098da 3542 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3543 free_irq(priv->pdev->irq, hw);
3544
3545 rc = ieee80211_register_hw(hw);
3546 if (rc) {
c2c357ce
LB		 3547 printk(KERN_ERR "%s: Cannot register device\n",
3548 wiphy_name(hw->wiphy));
a66098da
LB		 3549 goto err_stop_firmware;
3550 }
3551
eae74e65 3552 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3553 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3554 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3555 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3556 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3557 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3558
3559 return 0;
3560
3561err_stop_firmware:
3562 mwl8k_hw_reset(priv);
3563 mwl8k_release_firmware(priv);
3564
3565err_free_irq:
a66098da 3566 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3567 free_irq(priv->pdev->irq, hw);
3568
3569err_free_queues:
3570 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3571 mwl8k_txq_deinit(hw, i);
3572 mwl8k_rxq_deinit(hw, 0);
3573
3574err_iounmap:
3575 if (priv->cookie != NULL)
3576 pci_free_consistent(priv->pdev, 4,
3577 priv->cookie, priv->cookie_dma);
3578
3579 if (priv->regs != NULL)
3580 pci_iounmap(pdev, priv->regs);
3581
5b9482dd
LB		 3582 if (priv->sram != NULL)
3583 pci_iounmap(pdev, priv->sram);
3584
a66098da
LB		 3585 pci_set_drvdata(pdev, NULL);
3586 ieee80211_free_hw(hw);
3587
3588err_free_reg:
3589 pci_release_regions(pdev);
3590 pci_disable_device(pdev);
3591
3592 return rc;
3593}
3594
230f7af0 3595static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3596{
3597 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3598}
3599
230f7af0 3600static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3601{
3602 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3603 struct mwl8k_priv *priv;
3604 int i;
3605
3606 if (hw == NULL)
3607 return;
3608 priv = hw->priv;
3609
3610 ieee80211_stop_queues(hw);
3611
60aa569f
LB		 3612 ieee80211_unregister_hw(hw);
3613
a66098da
LB		 3614 /* Remove tx reclaim tasklet */
3615 tasklet_kill(&priv->tx_reclaim_task);
3616
a66098da
LB		 3617 /* Stop hardware */
3618 mwl8k_hw_reset(priv);
3619
3620 /* Return all skbs to mac80211 */
3621 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3622 mwl8k_txq_reclaim(hw, i, 1);
3623
a66098da
LB		 3624 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3625 mwl8k_txq_deinit(hw, i);
3626
3627 mwl8k_rxq_deinit(hw, 0);
3628
c2c357ce 3629 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3630
3631 pci_iounmap(pdev, priv->regs);
5b9482dd 3632 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3633 pci_set_drvdata(pdev, NULL);
3634 ieee80211_free_hw(hw);
3635 pci_release_regions(pdev);
3636 pci_disable_device(pdev);
3637}
3638
3639static struct pci_driver mwl8k_driver = {
3640 .name = MWL8K_NAME,
45a390dd 3641 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3642 .probe = mwl8k_probe,
3643 .remove = __devexit_p(mwl8k_remove),
3644 .shutdown = __devexit_p(mwl8k_shutdown),
3645};
3646
3647static int __init mwl8k_init(void)
3648{
3649 return pci_register_driver(&mwl8k_driver);
3650}
3651
3652static void __exit mwl8k_exit(void)
3653{
3654 pci_unregister_driver(&mwl8k_driver);
3655}
3656
3657module_init(mwl8k_init);
3658module_exit(mwl8k_exit);
c2c357ce
LB		 3659
3660MODULE_DESCRIPTION(MWL8K_DESC);
3661MODULE_VERSION(MWL8K_VERSION);
3662MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3663MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)