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Merge branches 'amd-iommu/fixes' and 'dma-debug/fixes' into iommu/fixes
[linux-2.6-block.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
54bc3a0d 95 struct rxd_ops *rxd_ops;
547810e3 96 u16 modes;
45a390dd
LB		 97};
98
a66098da 99struct mwl8k_rx_queue {
45eb400d 100 int rxd_count;
a66098da
LB		 101
102 /* hw receives here */
45eb400d 103 int head;
a66098da
LB		 104
105 /* refill descs here */
45eb400d 106 int tail;
a66098da 107
54bc3a0d 108 void *rxd;
45eb400d 109 dma_addr_t rxd_dma;
788838eb
LB		 110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
a66098da
LB		 114};
115
a66098da
LB		 116struct mwl8k_tx_queue {
117 /* hw transmits here */
45eb400d 118 int head;
a66098da
LB		 119
120 /* sw appends here */
45eb400d 121 int tail;
a66098da 122
45eb400d
LB		 123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
a66098da
LB		 127};
128
129/* Pointers to the firmware data and meta information about it. */
130struct mwl8k_firmware {
a66098da
LB		 131 /* Boot helper code */
132 struct firmware *helper;
a74b295e
LB		 133
134 /* Microcode */
135 struct firmware *ucode;
a66098da
LB		 136};
137
138struct mwl8k_priv {
5b9482dd 139 void __iomem *sram;
a66098da
LB		 140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
a66098da 144
45a390dd 145 struct mwl8k_device_info *device_info;
eae74e65 146 bool ap_fw;
54bc3a0d 147 struct rxd_ops *rxd_ops;
45a390dd 148
a66098da
LB		 149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
a66098da 151
618952a7
LB		 152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
618952a7
LB		 156 struct completion *hostcmd_wait;
157
a66098da
LB		 158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
a66098da 160
88de754a
LB		 161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
a66098da 164 struct ieee80211_vif *vif;
a66098da
LB		 165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
a66098da 173 u8 hw_rev;
2aa7b01f 174 u32 fw_rev;
a66098da
LB		 175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
140eb5e2 188 struct ieee80211_rate rates[14];
a66098da 189
c46563b7 190 bool radio_on;
68ce3884 191 bool radio_short_preamble;
a43c49a8 192 bool sniffer_enabled;
0439b1f5 193 bool wmm_enabled;
a66098da 194
a66098da
LB		 195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
d89173f2 197 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 210};
211
212/* Per interface specific private data */
213struct mwl8k_vif {
a66098da
LB		 214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
d89173f2
LB		 221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
a66098da 223
a66098da
LB		 224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
a66098da
LB		 229};
230
a94cc97e 231#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 232
233static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245};
246
247static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 261 { .bitrate = 720, .hw_value = 144, },
262};
263
264static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
a66098da
LB		 266};
267
a66098da
LB		 268/* Set or get info from Firmware */
269#define MWL8K_CMD_SET 0x0001
270#define MWL8K_CMD_GET 0x0000
271
272/* Firmware command codes */
273#define MWL8K_CMD_CODE_DNLD 0x0001
274#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 275#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 276#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 278#define MWL8K_CMD_RADIO_CONTROL 0x001c
279#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 280#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 281#define MWL8K_CMD_SET_PRE_SCAN 0x0107
282#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 283#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284#define MWL8K_CMD_SET_AID 0x010d
285#define MWL8K_CMD_SET_RATE 0x0110
286#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 288#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 289#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 291#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 292#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 293#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 294#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 295#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 296#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 297
298static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299{
300#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
ce9e2e1b 304 switch (cmd & ~0x8000) {
a66098da
LB		 305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 307 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 312 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 320 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 323 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 324 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 325 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 326 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 328 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332#undef MWL8K_CMDNAME
333
334 return buf;
335}
336
337/* Hardware and firmware reset */
338static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339{
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345}
346
347/* Release fw image */
348static void mwl8k_release_fw(struct firmware **fw)
349{
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354}
355
356static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357{
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360}
361
362/* Request fw image */
363static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 364 const char *fname, struct firmware **fw)
a66098da
LB		 365{
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
c2c357ce 371 fname, &priv->pdev->dev);
a66098da
LB		 372}
373
45a390dd 374static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 375{
a74b295e 376 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 377 int rc;
378
a74b295e
LB		 379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
a66098da
LB		 387 }
388
a74b295e 389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 390 if (rc) {
c2c357ce 391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 392 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398}
399
7e75b942
BH		 400MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
a66098da
LB		 403struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409} __attribute__((packed));
410
411/*
412 * Firmware loading.
413 */
414static int
415mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416{
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
a66098da
LB		 419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
a66098da
LB		 432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 439 break;
440 }
441
3d76e82c 442 cond_resched();
a66098da
LB		 443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
d4b70570 448 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 449}
450
451static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453{
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490}
491
492static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494{
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549}
550
c2c357ce 551static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 552{
c2c357ce
LB		 553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
eae74e65 555 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
a66098da 561
c2c357ce
LB		 562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
a66098da 567
c2c357ce 568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 571 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 572 return rc;
573 }
89b872e2 574 msleep(5);
a66098da 575
c2c357ce 576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 577 } else {
c2c357ce 578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 579 }
580
581 if (rc) {
c2c357ce
LB		 582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
a66098da
LB		 584 return rc;
585 }
586
eae74e65
LB		 587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 591
89b872e2 592 loops = 500000;
a66098da 593 do {
eae74e65
LB		 594 u32 ready_code;
595
596 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
597 if (ready_code == MWL8K_FWAP_READY) {
598 priv->ap_fw = 1;
599 break;
600 } else if (ready_code == MWL8K_FWSTA_READY) {
601 priv->ap_fw = 0;
a66098da 602 break;
eae74e65
LB		 603 }
604
605 cond_resched();
a66098da
LB		 606 udelay(1);
607 } while (--loops);
608
609 return loops ? 0 : -ETIMEDOUT;
610}
611
612
613/*
614 * Defines shared between transmission and reception.
615 */
616/* HT control fields for firmware */
617struct ewc_ht_info {
618 __le16 control1;
619 __le16 control2;
620 __le16 control3;
621} __attribute__((packed));
622
623/* Firmware Station database operations */
624#define MWL8K_STA_DB_ADD_ENTRY 0
625#define MWL8K_STA_DB_MODIFY_ENTRY 1
626#define MWL8K_STA_DB_DEL_ENTRY 2
627#define MWL8K_STA_DB_FLUSH 3
628
629/* Peer Entry flags - used to define the type of the peer node */
630#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 631
a66098da
LB		 632struct peer_capability_info {
633 /* Peer type - AP vs. STA. */
634 __u8 peer_type;
635
636 /* Basic 802.11 capabilities from assoc resp. */
637 __le16 basic_caps;
638
639 /* Set if peer supports 802.11n high throughput (HT). */
640 __u8 ht_support;
641
642 /* Valid if HT is supported. */
643 __le16 ht_caps;
644 __u8 extended_ht_caps;
645 struct ewc_ht_info ewc_info;
646
647 /* Legacy rate table. Intersection of our rates and peer rates. */
140eb5e2 648 __u8 legacy_rates[12];
a66098da
LB		 649
650 /* HT rate table. Intersection of our rates and peer rates. */
0b5351a8 651 __u8 ht_rates[16];
c23b5a69 652 __u8 pad[16];
a66098da
LB		 653
654 /* If set, interoperability mode, no proprietary extensions. */
655 __u8 interop;
656 __u8 pad2;
657 __u8 station_id;
658 __le16 amsdu_enabled;
659} __attribute__((packed));
660
661/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 662static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
663{
664 u16 val_mask = 1 << 4;
665
666 /* End of Service Period Bit 4 */
667 return qos | val_mask;
668}
669
670static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
671{
672 u16 val_mask = 0x3;
673 u8 shift = 5;
674 u16 qos_mask = ~(val_mask << shift);
675
676 /* Ack Policy Bit 5-6 */
677 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
678}
679
680static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
681{
682 u16 val_mask = 1 << 7;
683
684 /* AMSDU present Bit 7 */
685 return qos | val_mask;
686}
687
688static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
689{
690 u16 val_mask = 0xff;
691 u8 shift = 8;
692 u16 qos_mask = ~(val_mask << shift);
693
694 /* Queue Length Bits 8-15 */
695 return (qos & qos_mask) | ((len & val_mask) << shift);
696}
697
698/* DMA header used by firmware and hardware. */
699struct mwl8k_dma_data {
700 __le16 fwlen;
701 struct ieee80211_hdr wh;
20f09c3d 702 char data[0];
a66098da
LB		 703} __attribute__((packed));
704
705/* Routines to add/remove DMA header from skb. */
20f09c3d 706static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 707{
20f09c3d
LB		 708 struct mwl8k_dma_data *tr;
709 int hdrlen;
710
711 tr = (struct mwl8k_dma_data *)skb->data;
712 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
713
714 if (hdrlen != sizeof(tr->wh)) {
715 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
716 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
717 *((__le16 *)(tr->data - 2)) = qos;
718 } else {
719 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
720 }
a66098da 721 }
20f09c3d
LB		 722
723 if (hdrlen != sizeof(*tr))
724 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 725}
726
76266b2a 727static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 728{
729 struct ieee80211_hdr *wh;
ca009301 730 int hdrlen;
a66098da
LB		 731 struct mwl8k_dma_data *tr;
732
ca009301
LB		 733 /*
734 * Add a firmware DMA header; the firmware requires that we
735 * present a 2-byte payload length followed by a 4-address
736 * header (without QoS field), followed (optionally) by any
737 * WEP/ExtIV header (but only filled in for CCMP).
738 */
a66098da 739 wh = (struct ieee80211_hdr *)skb->data;
ca009301 740
a66098da 741 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 742 if (hdrlen != sizeof(*tr))
743 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 744
ca009301
LB		 745 if (ieee80211_is_data_qos(wh->frame_control))
746 hdrlen -= 2;
a66098da
LB		 747
748 tr = (struct mwl8k_dma_data *)skb->data;
749 if (wh != &tr->wh)
750 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 751 if (hdrlen != sizeof(tr->wh))
752 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 753
754 /*
755 * Firmware length is the length of the fully formed "802.11
756 * payload". That is, everything except for the 802.11 header.
757 * This includes all crypto material including the MIC.
758 */
ca009301 759 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 760}
761
762
763/*
6f6d1e9a
LB		 764 * Packet reception for 88w8366.
765 */
766struct mwl8k_rxd_8366 {
767 __le16 pkt_len;
768 __u8 sq2;
769 __u8 rate;
770 __le32 pkt_phys_addr;
771 __le32 next_rxd_phys_addr;
772 __le16 qos_control;
773 __le16 htsig2;
774 __le32 hw_rssi_info;
775 __le32 hw_noise_floor_info;
776 __u8 noise_floor;
777 __u8 pad0[3];
778 __u8 rssi;
779 __u8 rx_status;
780 __u8 channel;
781 __u8 rx_ctrl;
782} __attribute__((packed));
783
8e9f33f0
LB		 784#define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
785#define MWL8K_8366_RATE_INFO_40MHZ 0x40
786#define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
787
6f6d1e9a
LB		 788#define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
789
790static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
791{
792 struct mwl8k_rxd_8366 *rxd = _rxd;
793
794 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
795 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
796}
797
798static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
799{
800 struct mwl8k_rxd_8366 *rxd = _rxd;
801
802 rxd->pkt_len = cpu_to_le16(len);
803 rxd->pkt_phys_addr = cpu_to_le32(addr);
804 wmb();
805 rxd->rx_ctrl = 0;
806}
807
808static int
20f09c3d
LB		 809mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
810 __le16 *qos)
6f6d1e9a
LB		 811{
812 struct mwl8k_rxd_8366 *rxd = _rxd;
813
814 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
815 return -1;
816 rmb();
817
818 memset(status, 0, sizeof(*status));
819
820 status->signal = -rxd->rssi;
821 status->noise = -rxd->noise_floor;
822
8e9f33f0 823 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 824 status->flag |= RX_FLAG_HT;
8e9f33f0
LB		 825 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
826 status->flag |= RX_FLAG_40MHZ;
827 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 828 } else {
829 int i;
830
831 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
832 if (mwl8k_rates[i].hw_value == rxd->rate) {
833 status->rate_idx = i;
834 break;
835 }
836 }
837 }
838
839 status->band = IEEE80211_BAND_2GHZ;
840 status->freq = ieee80211_channel_to_frequency(rxd->channel);
841
20f09c3d
LB		 842 *qos = rxd->qos_control;
843
6f6d1e9a
LB		 844 return le16_to_cpu(rxd->pkt_len);
845}
846
847static struct rxd_ops rxd_8366_ops = {
848 .rxd_size = sizeof(struct mwl8k_rxd_8366),
849 .rxd_init = mwl8k_rxd_8366_init,
850 .rxd_refill = mwl8k_rxd_8366_refill,
851 .rxd_process = mwl8k_rxd_8366_process,
852};
853
854/*
855 * Packet reception for 88w8687.
a66098da 856 */
54bc3a0d 857struct mwl8k_rxd_8687 {
a66098da
LB		 858 __le16 pkt_len;
859 __u8 link_quality;
860 __u8 noise_level;
861 __le32 pkt_phys_addr;
45eb400d 862 __le32 next_rxd_phys_addr;
a66098da
LB		 863 __le16 qos_control;
864 __le16 rate_info;
865 __le32 pad0[4];
866 __u8 rssi;
867 __u8 channel;
868 __le16 pad1;
869 __u8 rx_ctrl;
870 __u8 rx_status;
871 __u8 pad2[2];
872} __attribute__((packed));
873
54bc3a0d
LB		 874#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
875#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
876#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
877#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
878#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
879#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
880
881#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
882
883static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
884{
885 struct mwl8k_rxd_8687 *rxd = _rxd;
886
887 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
888 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
889}
890
891static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
892{
893 struct mwl8k_rxd_8687 *rxd = _rxd;
894
895 rxd->pkt_len = cpu_to_le16(len);
896 rxd->pkt_phys_addr = cpu_to_le32(addr);
897 wmb();
898 rxd->rx_ctrl = 0;
899}
900
901static int
20f09c3d
LB		 902mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
903 __le16 *qos)
54bc3a0d
LB		 904{
905 struct mwl8k_rxd_8687 *rxd = _rxd;
906 u16 rate_info;
907
908 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
909 return -1;
910 rmb();
911
912 rate_info = le16_to_cpu(rxd->rate_info);
913
914 memset(status, 0, sizeof(*status));
915
916 status->signal = -rxd->rssi;
917 status->noise = -rxd->noise_level;
54bc3a0d
LB		 918 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
919 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
920
921 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
922 status->flag |= RX_FLAG_SHORTPRE;
923 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
924 status->flag |= RX_FLAG_40MHZ;
925 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
926 status->flag |= RX_FLAG_SHORT_GI;
927 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
928 status->flag |= RX_FLAG_HT;
929
930 status->band = IEEE80211_BAND_2GHZ;
931 status->freq = ieee80211_channel_to_frequency(rxd->channel);
932
20f09c3d
LB		 933 *qos = rxd->qos_control;
934
54bc3a0d
LB		 935 return le16_to_cpu(rxd->pkt_len);
936}
937
938static struct rxd_ops rxd_8687_ops = {
939 .rxd_size = sizeof(struct mwl8k_rxd_8687),
940 .rxd_init = mwl8k_rxd_8687_init,
941 .rxd_refill = mwl8k_rxd_8687_refill,
942 .rxd_process = mwl8k_rxd_8687_process,
943};
944
945
a66098da
LB		 946#define MWL8K_RX_DESCS 256
947#define MWL8K_RX_MAXSZ 3800
948
949static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
950{
951 struct mwl8k_priv *priv = hw->priv;
952 struct mwl8k_rx_queue *rxq = priv->rxq + index;
953 int size;
954 int i;
955
45eb400d
LB		 956 rxq->rxd_count = 0;
957 rxq->head = 0;
958 rxq->tail = 0;
a66098da 959
54bc3a0d 960 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 961
45eb400d
LB		 962 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
963 if (rxq->rxd == NULL) {
a66098da 964 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 965 wiphy_name(hw->wiphy));
a66098da
LB		 966 return -ENOMEM;
967 }
45eb400d 968 memset(rxq->rxd, 0, size);
a66098da 969
788838eb
LB		 970 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
971 if (rxq->buf == NULL) {
a66098da 972 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 973 wiphy_name(hw->wiphy));
45eb400d 974 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 975 return -ENOMEM;
976 }
788838eb 977 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 978
979 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 980 int desc_size;
981 void *rxd;
a66098da 982 int nexti;
54bc3a0d
LB		 983 dma_addr_t next_dma_addr;
984
985 desc_size = priv->rxd_ops->rxd_size;
986 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 987
54bc3a0d
LB		 988 nexti = i + 1;
989 if (nexti == MWL8K_RX_DESCS)
990 nexti = 0;
991 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 992
54bc3a0d 993 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 994 }
995
996 return 0;
997}
998
999static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1000{
1001 struct mwl8k_priv *priv = hw->priv;
1002 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1003 int refilled;
1004
1005 refilled = 0;
45eb400d 1006 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1007 struct sk_buff *skb;
788838eb 1008 dma_addr_t addr;
a66098da 1009 int rx;
54bc3a0d 1010 void *rxd;
a66098da
LB		 1011
1012 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1013 if (skb == NULL)
1014 break;
1015
788838eb
LB		 1016 addr = pci_map_single(priv->pdev, skb->data,
1017 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1018
54bc3a0d
LB		 1019 rxq->rxd_count++;
1020 rx = rxq->tail++;
1021 if (rxq->tail == MWL8K_RX_DESCS)
1022 rxq->tail = 0;
788838eb
LB		 1023 rxq->buf[rx].skb = skb;
1024 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1025
1026 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1027 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1028
1029 refilled++;
1030 }
1031
1032 return refilled;
1033}
1034
1035/* Must be called only when the card's reception is completely halted */
1036static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1037{
1038 struct mwl8k_priv *priv = hw->priv;
1039 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1040 int i;
1041
1042 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1043 if (rxq->buf[i].skb != NULL) {
1044 pci_unmap_single(priv->pdev,
1045 pci_unmap_addr(&rxq->buf[i], dma),
1046 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1047 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1048
1049 kfree_skb(rxq->buf[i].skb);
1050 rxq->buf[i].skb = NULL;
a66098da
LB		 1051 }
1052 }
1053
788838eb
LB		 1054 kfree(rxq->buf);
1055 rxq->buf = NULL;
a66098da
LB		 1056
1057 pci_free_consistent(priv->pdev,
54bc3a0d 1058 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1059 rxq->rxd, rxq->rxd_dma);
1060 rxq->rxd = NULL;
a66098da
LB		 1061}
1062
1063
1064/*
1065 * Scan a list of BSSIDs to process for finalize join.
1066 * Allows for extension to process multiple BSSIDs.
1067 */
1068static inline int
1069mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1070{
1071 return priv->capture_beacon &&
1072 ieee80211_is_beacon(wh->frame_control) &&
1073 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1074}
1075
3779752d
LB		 1076static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1077 struct sk_buff *skb)
a66098da 1078{
3779752d
LB		 1079 struct mwl8k_priv *priv = hw->priv;
1080
a66098da 1081 priv->capture_beacon = false;
d89173f2 1082 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1083
1084 /*
1085 * Use GFP_ATOMIC as rxq_process is called from
1086 * the primary interrupt handler, memory allocation call
1087 * must not sleep.
1088 */
1089 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1090 if (priv->beacon_skb != NULL)
3779752d 1091 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1092}
1093
1094static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1095{
1096 struct mwl8k_priv *priv = hw->priv;
1097 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1098 int processed;
1099
1100 processed = 0;
45eb400d 1101 while (rxq->rxd_count && limit--) {
a66098da 1102 struct sk_buff *skb;
54bc3a0d
LB		 1103 void *rxd;
1104 int pkt_len;
a66098da 1105 struct ieee80211_rx_status status;
20f09c3d 1106 __le16 qos;
a66098da 1107
788838eb 1108 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1109 if (skb == NULL)
1110 break;
54bc3a0d
LB		 1111
1112 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1113
20f09c3d 1114 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1115 if (pkt_len < 0)
1116 break;
1117
788838eb
LB		 1118 rxq->buf[rxq->head].skb = NULL;
1119
1120 pci_unmap_single(priv->pdev,
1121 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1122 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1123 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1124
54bc3a0d
LB		 1125 rxq->head++;
1126 if (rxq->head == MWL8K_RX_DESCS)
1127 rxq->head = 0;
1128
45eb400d 1129 rxq->rxd_count--;
a66098da 1130
54bc3a0d 1131 skb_put(skb, pkt_len);
20f09c3d 1132 mwl8k_remove_dma_header(skb, qos);
a66098da 1133
a66098da 1134 /*
c2c357ce
LB		 1135 * Check for a pending join operation. Save a
1136 * copy of the beacon and schedule a tasklet to
1137 * send a FINALIZE_JOIN command to the firmware.
a66098da 1138 */
54bc3a0d 1139 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1140 mwl8k_save_beacon(hw, skb);
a66098da 1141
f1d58c25
JB		 1142 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1143 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1144
1145 processed++;
1146 }
1147
1148 return processed;
1149}
1150
1151
1152/*
1153 * Packet transmission.
1154 */
1155
a66098da
LB		 1156/* Transmit packet ACK policy */
1157#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1158#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1159
a66098da
LB		 1160#define MWL8K_TXD_STATUS_OK 0x00000001
1161#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1162#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1163#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1164#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1165
1166struct mwl8k_tx_desc {
1167 __le32 status;
1168 __u8 data_rate;
1169 __u8 tx_priority;
1170 __le16 qos_control;
1171 __le32 pkt_phys_addr;
1172 __le16 pkt_len;
d89173f2 1173 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1174 __le32 next_txd_phys_addr;
a66098da
LB		 1175 __le32 reserved;
1176 __le16 rate_info;
1177 __u8 peer_id;
1178 __u8 tx_frag_cnt;
1179} __attribute__((packed));
1180
1181#define MWL8K_TX_DESCS 128
1182
1183static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1184{
1185 struct mwl8k_priv *priv = hw->priv;
1186 struct mwl8k_tx_queue *txq = priv->txq + index;
1187 int size;
1188 int i;
1189
45eb400d
LB		 1190 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1191 txq->stats.limit = MWL8K_TX_DESCS;
1192 txq->head = 0;
1193 txq->tail = 0;
a66098da
LB		 1194
1195 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1196
45eb400d
LB		 1197 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1198 if (txq->txd == NULL) {
a66098da 1199 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1200 wiphy_name(hw->wiphy));
a66098da
LB		 1201 return -ENOMEM;
1202 }
45eb400d 1203 memset(txq->txd, 0, size);
a66098da 1204
45eb400d
LB		 1205 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1206 if (txq->skb == NULL) {
a66098da 1207 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1208 wiphy_name(hw->wiphy));
45eb400d 1209 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1210 return -ENOMEM;
1211 }
45eb400d 1212 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1213
1214 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1215 struct mwl8k_tx_desc *tx_desc;
1216 int nexti;
1217
45eb400d 1218 tx_desc = txq->txd + i;
a66098da
LB		 1219 nexti = (i + 1) % MWL8K_TX_DESCS;
1220
1221 tx_desc->status = 0;
45eb400d
LB		 1222 tx_desc->next_txd_phys_addr =
1223 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1224 }
1225
1226 return 0;
1227}
1228
1229static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1230{
1231 iowrite32(MWL8K_H2A_INT_PPA_READY,
1232 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1233 iowrite32(MWL8K_H2A_INT_DUMMY,
1234 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1235 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1236}
1237
7e1112d3 1238static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1239{
7e1112d3
LB		 1240 struct mwl8k_priv *priv = hw->priv;
1241 int i;
1242
1243 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1244 struct mwl8k_tx_queue *txq = priv->txq + i;
1245 int fw_owned = 0;
1246 int drv_owned = 0;
1247 int unused = 0;
1248 int desc;
1249
a66098da 1250 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1251 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1252 u32 status;
a66098da 1253
7e1112d3 1254 status = le32_to_cpu(tx_desc->status);
a66098da 1255 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1256 fw_owned++;
a66098da 1257 else
7e1112d3 1258 drv_owned++;
a66098da
LB		 1259
1260 if (tx_desc->pkt_len == 0)
7e1112d3 1261 unused++;
a66098da 1262 }
a66098da 1263
7e1112d3
LB		 1264 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1265 "fw_owned=%d drv_owned=%d unused=%d\n",
1266 wiphy_name(hw->wiphy), i,
1267 txq->stats.len, txq->head, txq->tail,
1268 fw_owned, drv_owned, unused);
1269 }
a66098da
LB		 1270}
1271
618952a7 1272/*
88de754a 1273 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1274 */
7e1112d3
LB		 1275#define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1276
950d5b01 1277static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1278{
a66098da 1279 struct mwl8k_priv *priv = hw->priv;
88de754a 1280 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1281 int retry;
1282 int rc;
a66098da
LB		 1283
1284 might_sleep();
1285
7e1112d3
LB		 1286 /*
1287 * The TX queues are stopped at this point, so this test
1288 * doesn't need to take ->tx_lock.
1289 */
1290 if (!priv->pending_tx_pkts)
1291 return 0;
1292
1293 retry = 0;
1294 rc = 0;
1295
a66098da 1296 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1297 priv->tx_wait = &tx_wait;
1298 while (!rc) {
1299 int oldcount;
1300 unsigned long timeout;
a66098da 1301
7e1112d3 1302 oldcount = priv->pending_tx_pkts;
a66098da 1303
7e1112d3 1304 spin_unlock_bh(&priv->tx_lock);
88de754a 1305 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1306 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1307 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1308
1309 if (timeout) {
1310 WARN_ON(priv->pending_tx_pkts);
1311 if (retry) {
1312 printk(KERN_NOTICE "%s: tx rings drained\n",
1313 wiphy_name(hw->wiphy));
1314 }
1315 break;
1316 }
1317
1318 if (priv->pending_tx_pkts < oldcount) {
1319 printk(KERN_NOTICE "%s: timeout waiting for tx "
1320 "rings to drain (%d -> %d pkts), retrying\n",
1321 wiphy_name(hw->wiphy), oldcount,
1322 priv->pending_tx_pkts);
1323 retry = 1;
1324 continue;
1325 }
1326
a66098da 1327 priv->tx_wait = NULL;
a66098da 1328
7e1112d3
LB		 1329 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1330 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1331 mwl8k_dump_tx_rings(hw);
1332
1333 rc = -ETIMEDOUT;
a66098da 1334 }
7e1112d3 1335 spin_unlock_bh(&priv->tx_lock);
a66098da 1336
7e1112d3 1337 return rc;
a66098da
LB		 1338}
1339
c23b5a69
LB		 1340#define MWL8K_TXD_SUCCESS(status) \
1341 ((status) & (MWL8K_TXD_STATUS_OK | \
1342 MWL8K_TXD_STATUS_OK_RETRY | \
1343 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1344
1345static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1346{
1347 struct mwl8k_priv *priv = hw->priv;
1348 struct mwl8k_tx_queue *txq = priv->txq + index;
1349 int wake = 0;
1350
45eb400d 1351 while (txq->stats.len > 0) {
a66098da 1352 int tx;
a66098da
LB		 1353 struct mwl8k_tx_desc *tx_desc;
1354 unsigned long addr;
ce9e2e1b 1355 int size;
a66098da
LB		 1356 struct sk_buff *skb;
1357 struct ieee80211_tx_info *info;
1358 u32 status;
1359
45eb400d
LB		 1360 tx = txq->head;
1361 tx_desc = txq->txd + tx;
a66098da
LB		 1362
1363 status = le32_to_cpu(tx_desc->status);
1364
1365 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1366 if (!force)
1367 break;
1368 tx_desc->status &=
1369 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1370 }
1371
45eb400d
LB		 1372 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1373 BUG_ON(txq->stats.len == 0);
1374 txq->stats.len--;
a66098da
LB		 1375 priv->pending_tx_pkts--;
1376
1377 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1378 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1379 skb = txq->skb[tx];
1380 txq->skb[tx] = NULL;
a66098da
LB		 1381
1382 BUG_ON(skb == NULL);
1383 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1384
20f09c3d 1385 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1386
1387 /* Mark descriptor as unused */
1388 tx_desc->pkt_phys_addr = 0;
1389 tx_desc->pkt_len = 0;
1390
a66098da
LB		 1391 info = IEEE80211_SKB_CB(skb);
1392 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1393 if (MWL8K_TXD_SUCCESS(status))
a66098da 1394 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1395
1396 ieee80211_tx_status_irqsafe(hw, skb);
1397
618952a7 1398 wake = 1;
a66098da
LB		 1399 }
1400
618952a7 1401 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1402 ieee80211_wake_queue(hw, index);
1403}
1404
1405/* must be called only when the card's transmit is completely halted */
1406static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1407{
1408 struct mwl8k_priv *priv = hw->priv;
1409 struct mwl8k_tx_queue *txq = priv->txq + index;
1410
1411 mwl8k_txq_reclaim(hw, index, 1);
1412
45eb400d
LB		 1413 kfree(txq->skb);
1414 txq->skb = NULL;
a66098da
LB		 1415
1416 pci_free_consistent(priv->pdev,
1417 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1418 txq->txd, txq->txd_dma);
1419 txq->txd = NULL;
a66098da
LB		 1420}
1421
1422static int
1423mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1424{
1425 struct mwl8k_priv *priv = hw->priv;
1426 struct ieee80211_tx_info *tx_info;
23b33906 1427 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1428 struct ieee80211_hdr *wh;
1429 struct mwl8k_tx_queue *txq;
1430 struct mwl8k_tx_desc *tx;
a66098da 1431 dma_addr_t dma;
23b33906
LB		 1432 u32 txstatus;
1433 u8 txdatarate;
1434 u16 qos;
a66098da 1435
23b33906
LB		 1436 wh = (struct ieee80211_hdr *)skb->data;
1437 if (ieee80211_is_data_qos(wh->frame_control))
1438 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1439 else
1440 qos = 0;
a66098da 1441
76266b2a 1442 mwl8k_add_dma_header(skb);
23b33906 1443 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1444
1445 tx_info = IEEE80211_SKB_CB(skb);
1446 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1447
1448 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1449 u16 seqno = mwl8k_vif->seqno;
23b33906 1450
a66098da
LB		 1451 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1452 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1453 mwl8k_vif->seqno = seqno++ % 4096;
1454 }
1455
23b33906
LB		 1456 /* Setup firmware control bit fields for each frame type. */
1457 txstatus = 0;
1458 txdatarate = 0;
1459 if (ieee80211_is_mgmt(wh->frame_control) ||
1460 ieee80211_is_ctl(wh->frame_control)) {
1461 txdatarate = 0;
1462 qos = mwl8k_qos_setbit_eosp(qos);
1463 /* Set Queue size to unspecified */
1464 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1465 } else if (ieee80211_is_data(wh->frame_control)) {
1466 txdatarate = 1;
1467 if (is_multicast_ether_addr(wh->addr1))
1468 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1469
1470 /* Send pkt in an aggregate if AMPDU frame. */
1471 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1472 qos = mwl8k_qos_setbit_ack(qos,
1473 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1474 else
1475 qos = mwl8k_qos_setbit_ack(qos,
1476 MWL8K_TXD_ACK_POLICY_NORMAL);
1477
1478 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1479 qos = mwl8k_qos_setbit_amsdu(qos);
1480 }
a66098da
LB		 1481
1482 dma = pci_map_single(priv->pdev, skb->data,
1483 skb->len, PCI_DMA_TODEVICE);
1484
1485 if (pci_dma_mapping_error(priv->pdev, dma)) {
1486 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1487 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1488 dev_kfree_skb(skb);
a66098da
LB		 1489 return NETDEV_TX_OK;
1490 }
1491
23b33906 1492 spin_lock_bh(&priv->tx_lock);
a66098da 1493
23b33906 1494 txq = priv->txq + index;
a66098da 1495
45eb400d
LB		 1496 BUG_ON(txq->skb[txq->tail] != NULL);
1497 txq->skb[txq->tail] = skb;
a66098da 1498
45eb400d 1499 tx = txq->txd + txq->tail;
23b33906
LB		 1500 tx->data_rate = txdatarate;
1501 tx->tx_priority = index;
a66098da 1502 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1503 tx->pkt_phys_addr = cpu_to_le32(dma);
1504 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1505 tx->rate_info = 0;
1506 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1507 wmb();
23b33906
LB		 1508 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1509
45eb400d
LB		 1510 txq->stats.count++;
1511 txq->stats.len++;
a66098da 1512 priv->pending_tx_pkts++;
a66098da 1513
45eb400d
LB		 1514 txq->tail++;
1515 if (txq->tail == MWL8K_TX_DESCS)
1516 txq->tail = 0;
23b33906 1517
45eb400d 1518 if (txq->head == txq->tail)
a66098da
LB		 1519 ieee80211_stop_queue(hw, index);
1520
23b33906 1521 mwl8k_tx_start(priv);
a66098da
LB		 1522
1523 spin_unlock_bh(&priv->tx_lock);
1524
1525 return NETDEV_TX_OK;
1526}
1527
1528
618952a7
LB		 1529/*
1530 * Firmware access.
1531 *
1532 * We have the following requirements for issuing firmware commands:
1533 * - Some commands require that the packet transmit path is idle when
1534 * the command is issued. (For simplicity, we'll just quiesce the
1535 * transmit path for every command.)
1536 * - There are certain sequences of commands that need to be issued to
1537 * the hardware sequentially, with no other intervening commands.
1538 *
1539 * This leads to an implementation of a "firmware lock" as a mutex that
1540 * can be taken recursively, and which is taken by both the low-level
1541 * command submission function (mwl8k_post_cmd) as well as any users of
1542 * that function that require issuing of an atomic sequence of commands,
1543 * and quiesces the transmit path whenever it's taken.
1544 */
1545static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1546{
1547 struct mwl8k_priv *priv = hw->priv;
1548
1549 if (priv->fw_mutex_owner != current) {
1550 int rc;
1551
1552 mutex_lock(&priv->fw_mutex);
1553 ieee80211_stop_queues(hw);
1554
1555 rc = mwl8k_tx_wait_empty(hw);
1556 if (rc) {
1557 ieee80211_wake_queues(hw);
1558 mutex_unlock(&priv->fw_mutex);
1559
1560 return rc;
1561 }
1562
1563 priv->fw_mutex_owner = current;
1564 }
1565
1566 priv->fw_mutex_depth++;
1567
1568 return 0;
1569}
1570
1571static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1572{
1573 struct mwl8k_priv *priv = hw->priv;
1574
1575 if (!--priv->fw_mutex_depth) {
1576 ieee80211_wake_queues(hw);
1577 priv->fw_mutex_owner = NULL;
1578 mutex_unlock(&priv->fw_mutex);
1579 }
1580}
1581
1582
a66098da
LB		 1583/*
1584 * Command processing.
1585 */
1586
0c9cc640
LB		 1587/* Timeout firmware commands after 10s */
1588#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1589
1590static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1591{
1592 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1593 struct mwl8k_priv *priv = hw->priv;
1594 void __iomem *regs = priv->regs;
1595 dma_addr_t dma_addr;
1596 unsigned int dma_size;
1597 int rc;
a66098da
LB		 1598 unsigned long timeout = 0;
1599 u8 buf[32];
1600
c2c357ce 1601 cmd->result = 0xffff;
a66098da
LB		 1602 dma_size = le16_to_cpu(cmd->length);
1603 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1604 PCI_DMA_BIDIRECTIONAL);
1605 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1606 return -ENOMEM;
1607
618952a7 1608 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1609 if (rc) {
1610 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1611 PCI_DMA_BIDIRECTIONAL);
618952a7 1612 return rc;
39a1e42e 1613 }
a66098da 1614
a66098da
LB		 1615 priv->hostcmd_wait = &cmd_wait;
1616 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1617 iowrite32(MWL8K_H2A_INT_DOORBELL,
1618 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1619 iowrite32(MWL8K_H2A_INT_DUMMY,
1620 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1621
1622 timeout = wait_for_completion_timeout(&cmd_wait,
1623 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1624
618952a7
LB		 1625 priv->hostcmd_wait = NULL;
1626
1627 mwl8k_fw_unlock(hw);
1628
37055bd4
LB		 1629 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1630 PCI_DMA_BIDIRECTIONAL);
1631
a66098da 1632 if (!timeout) {
a66098da 1633 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1634 wiphy_name(hw->wiphy),
a66098da
LB		 1635 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1636 MWL8K_CMD_TIMEOUT_MS);
1637 rc = -ETIMEDOUT;
1638 } else {
0c9cc640
LB		 1639 int ms;
1640
1641 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1642
ce9e2e1b 1643 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1644 if (rc)
1645 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1646 wiphy_name(hw->wiphy),
a66098da 1647 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1648 le16_to_cpu(cmd->result));
0c9cc640
LB		 1649 else if (ms > 2000)
1650 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1651 wiphy_name(hw->wiphy),
1652 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1653 ms);
a66098da
LB		 1654 }
1655
a66098da
LB		 1656 return rc;
1657}
1658
1659/*
04b147b1 1660 * CMD_GET_HW_SPEC (STA version).
a66098da 1661 */
04b147b1 1662struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1663 struct mwl8k_cmd_pkt header;
1664 __u8 hw_rev;
1665 __u8 host_interface;
1666 __le16 num_mcaddrs;
d89173f2 1667 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1668 __le16 region_code;
1669 __le32 fw_rev;
1670 __le32 ps_cookie;
1671 __le32 caps;
1672 __u8 mcs_bitmap[16];
1673 __le32 rx_queue_ptr;
1674 __le32 num_tx_queues;
1675 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1676 __le32 caps2;
1677 __le32 num_tx_desc_per_queue;
45eb400d 1678 __le32 total_rxd;
a66098da
LB		 1679} __attribute__((packed));
1680
04b147b1 1681static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1682{
1683 struct mwl8k_priv *priv = hw->priv;
04b147b1 1684 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1685 int rc;
1686 int i;
1687
1688 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1689 if (cmd == NULL)
1690 return -ENOMEM;
1691
1692 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1693 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1694
1695 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1696 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1697 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1698 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1699 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1700 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1701 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1702 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1703
1704 rc = mwl8k_post_cmd(hw, &cmd->header);
1705
1706 if (!rc) {
1707 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1708 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1709 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1710 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1711 }
1712
1713 kfree(cmd);
1714 return rc;
1715}
1716
42fba21d
LB		 1717/*
1718 * CMD_GET_HW_SPEC (AP version).
1719 */
1720struct mwl8k_cmd_get_hw_spec_ap {
1721 struct mwl8k_cmd_pkt header;
1722 __u8 hw_rev;
1723 __u8 host_interface;
1724 __le16 num_wcb;
1725 __le16 num_mcaddrs;
1726 __u8 perm_addr[ETH_ALEN];
1727 __le16 region_code;
1728 __le16 num_antenna;
1729 __le32 fw_rev;
1730 __le32 wcbbase0;
1731 __le32 rxwrptr;
1732 __le32 rxrdptr;
1733 __le32 ps_cookie;
1734 __le32 wcbbase1;
1735 __le32 wcbbase2;
1736 __le32 wcbbase3;
1737} __attribute__((packed));
1738
1739static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1740{
1741 struct mwl8k_priv *priv = hw->priv;
1742 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1743 int rc;
1744
1745 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1746 if (cmd == NULL)
1747 return -ENOMEM;
1748
1749 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1750 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1751
1752 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1753 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1754
1755 rc = mwl8k_post_cmd(hw, &cmd->header);
1756
1757 if (!rc) {
1758 int off;
1759
1760 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1761 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1762 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1763 priv->hw_rev = cmd->hw_rev;
1764
1765 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1766 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1767
1768 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1769 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1770
1771 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1772 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1773
1774 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1775 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1776
1777 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1778 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1779
1780 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1781 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1782 }
1783
1784 kfree(cmd);
1785 return rc;
1786}
1787
1788/*
1789 * CMD_SET_HW_SPEC.
1790 */
1791struct mwl8k_cmd_set_hw_spec {
1792 struct mwl8k_cmd_pkt header;
1793 __u8 hw_rev;
1794 __u8 host_interface;
1795 __le16 num_mcaddrs;
1796 __u8 perm_addr[ETH_ALEN];
1797 __le16 region_code;
1798 __le32 fw_rev;
1799 __le32 ps_cookie;
1800 __le32 caps;
1801 __le32 rx_queue_ptr;
1802 __le32 num_tx_queues;
1803 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1804 __le32 flags;
1805 __le32 num_tx_desc_per_queue;
1806 __le32 total_rxd;
1807} __attribute__((packed));
1808
1809#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1810
1811static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1812{
1813 struct mwl8k_priv *priv = hw->priv;
1814 struct mwl8k_cmd_set_hw_spec *cmd;
1815 int rc;
1816 int i;
1817
1818 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1819 if (cmd == NULL)
1820 return -ENOMEM;
1821
1822 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1823 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1824
1825 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1826 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1827 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1828 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1829 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1830 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1831 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1832 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1833
1834 rc = mwl8k_post_cmd(hw, &cmd->header);
1835 kfree(cmd);
1836
1837 return rc;
1838}
1839
a66098da
LB		 1840/*
1841 * CMD_MAC_MULTICAST_ADR.
1842 */
1843struct mwl8k_cmd_mac_multicast_adr {
1844 struct mwl8k_cmd_pkt header;
1845 __le16 action;
1846 __le16 numaddr;
ce9e2e1b 1847 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1848};
1849
d5e30845
LB		 1850#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1851#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1852#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1853#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1854
e81cd2d6 1855static struct mwl8k_cmd_pkt *
447ced07 1856__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1857 int mc_count, struct dev_addr_list *mclist)
a66098da 1858{
e81cd2d6 1859 struct mwl8k_priv *priv = hw->priv;
a66098da 1860 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1861 int size;
e81cd2d6 1862
447ced07 1863 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1864 allmulti = 1;
1865 mc_count = 0;
1866 }
e81cd2d6
LB		 1867
1868 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1869
e81cd2d6 1870 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1871 if (cmd == NULL)
e81cd2d6 1872 return NULL;
a66098da
LB		 1873
1874 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1875 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1876 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1877 MWL8K_ENABLE_RX_BROADCAST);
1878
1879 if (allmulti) {
1880 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1881 } else if (mc_count) {
1882 int i;
1883
1884 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1885 cmd->numaddr = cpu_to_le16(mc_count);
1886 for (i = 0; i < mc_count && mclist; i++) {
1887 if (mclist->da_addrlen != ETH_ALEN) {
1888 kfree(cmd);
1889 return NULL;
1890 }
1891 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1892 mclist = mclist->next;
a66098da 1893 }
a66098da
LB		 1894 }
1895
e81cd2d6 1896 return &cmd->header;
a66098da
LB		 1897}
1898
1899/*
1900 * CMD_802_11_GET_STAT.
1901 */
1902struct mwl8k_cmd_802_11_get_stat {
1903 struct mwl8k_cmd_pkt header;
a66098da
LB		 1904 __le32 stats[64];
1905} __attribute__((packed));
1906
1907#define MWL8K_STAT_ACK_FAILURE 9
1908#define MWL8K_STAT_RTS_FAILURE 12
1909#define MWL8K_STAT_FCS_ERROR 24
1910#define MWL8K_STAT_RTS_SUCCESS 11
1911
1912static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1913 struct ieee80211_low_level_stats *stats)
1914{
1915 struct mwl8k_cmd_802_11_get_stat *cmd;
1916 int rc;
1917
1918 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1919 if (cmd == NULL)
1920 return -ENOMEM;
1921
1922 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1923 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1924
1925 rc = mwl8k_post_cmd(hw, &cmd->header);
1926 if (!rc) {
1927 stats->dot11ACKFailureCount =
1928 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1929 stats->dot11RTSFailureCount =
1930 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1931 stats->dot11FCSErrorCount =
1932 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1933 stats->dot11RTSSuccessCount =
1934 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1935 }
1936 kfree(cmd);
1937
1938 return rc;
1939}
1940
1941/*
1942 * CMD_802_11_RADIO_CONTROL.
1943 */
1944struct mwl8k_cmd_802_11_radio_control {
1945 struct mwl8k_cmd_pkt header;
1946 __le16 action;
1947 __le16 control;
1948 __le16 radio_on;
1949} __attribute__((packed));
1950
c46563b7
LB		 1951static int
1952mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1953{
1954 struct mwl8k_priv *priv = hw->priv;
1955 struct mwl8k_cmd_802_11_radio_control *cmd;
1956 int rc;
1957
c46563b7 1958 if (enable == priv->radio_on && !force)
a66098da
LB		 1959 return 0;
1960
a66098da
LB		 1961 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1962 if (cmd == NULL)
1963 return -ENOMEM;
1964
1965 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1966 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1967 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1968 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1969 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1970
1971 rc = mwl8k_post_cmd(hw, &cmd->header);
1972 kfree(cmd);
1973
1974 if (!rc)
c46563b7 1975 priv->radio_on = enable;
a66098da
LB		 1976
1977 return rc;
1978}
1979
c46563b7
LB		 1980static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1981{
1982 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1983}
1984
1985static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1986{
1987 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1988}
1989
a66098da
LB		 1990static int
1991mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1992{
1993 struct mwl8k_priv *priv;
1994
1995 if (hw == NULL || hw->priv == NULL)
1996 return -EINVAL;
1997 priv = hw->priv;
1998
68ce3884 1999 priv->radio_short_preamble = short_preamble;
a66098da 2000
c46563b7 2001 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 2002}
2003
2004/*
2005 * CMD_802_11_RF_TX_POWER.
2006 */
2007#define MWL8K_TX_POWER_LEVEL_TOTAL 8
2008
2009struct mwl8k_cmd_802_11_rf_tx_power {
2010 struct mwl8k_cmd_pkt header;
2011 __le16 action;
2012 __le16 support_level;
2013 __le16 current_level;
2014 __le16 reserved;
2015 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2016} __attribute__((packed));
2017
2018static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2019{
2020 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2021 int rc;
2022
2023 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2024 if (cmd == NULL)
2025 return -ENOMEM;
2026
2027 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2028 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2029 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2030 cmd->support_level = cpu_to_le16(dBm);
2031
2032 rc = mwl8k_post_cmd(hw, &cmd->header);
2033 kfree(cmd);
2034
2035 return rc;
2036}
2037
08b06347
LB		 2038/*
2039 * CMD_RF_ANTENNA.
2040 */
2041struct mwl8k_cmd_rf_antenna {
2042 struct mwl8k_cmd_pkt header;
2043 __le16 antenna;
2044 __le16 mode;
2045} __attribute__((packed));
2046
2047#define MWL8K_RF_ANTENNA_RX 1
2048#define MWL8K_RF_ANTENNA_TX 2
2049
2050static int
2051mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2052{
2053 struct mwl8k_cmd_rf_antenna *cmd;
2054 int rc;
2055
2056 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2057 if (cmd == NULL)
2058 return -ENOMEM;
2059
2060 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2061 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2062 cmd->antenna = cpu_to_le16(antenna);
2063 cmd->mode = cpu_to_le16(mask);
2064
2065 rc = mwl8k_post_cmd(hw, &cmd->header);
2066 kfree(cmd);
2067
2068 return rc;
2069}
2070
a66098da
LB		 2071/*
2072 * CMD_SET_PRE_SCAN.
2073 */
2074struct mwl8k_cmd_set_pre_scan {
2075 struct mwl8k_cmd_pkt header;
2076} __attribute__((packed));
2077
2078static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2079{
2080 struct mwl8k_cmd_set_pre_scan *cmd;
2081 int rc;
2082
2083 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2084 if (cmd == NULL)
2085 return -ENOMEM;
2086
2087 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2088 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2089
2090 rc = mwl8k_post_cmd(hw, &cmd->header);
2091 kfree(cmd);
2092
2093 return rc;
2094}
2095
2096/*
2097 * CMD_SET_POST_SCAN.
2098 */
2099struct mwl8k_cmd_set_post_scan {
2100 struct mwl8k_cmd_pkt header;
2101 __le32 isibss;
d89173f2 2102 __u8 bssid[ETH_ALEN];
a66098da
LB		 2103} __attribute__((packed));
2104
2105static int
ce9e2e1b 2106mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 2107{
2108 struct mwl8k_cmd_set_post_scan *cmd;
2109 int rc;
2110
2111 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2112 if (cmd == NULL)
2113 return -ENOMEM;
2114
2115 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2116 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2117 cmd->isibss = 0;
d89173f2 2118 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2119
2120 rc = mwl8k_post_cmd(hw, &cmd->header);
2121 kfree(cmd);
2122
2123 return rc;
2124}
2125
2126/*
2127 * CMD_SET_RF_CHANNEL.
2128 */
2129struct mwl8k_cmd_set_rf_channel {
2130 struct mwl8k_cmd_pkt header;
2131 __le16 action;
2132 __u8 current_channel;
2133 __le32 channel_flags;
2134} __attribute__((packed));
2135
2136static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2137 struct ieee80211_channel *channel)
2138{
2139 struct mwl8k_cmd_set_rf_channel *cmd;
2140 int rc;
2141
2142 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2143 if (cmd == NULL)
2144 return -ENOMEM;
2145
2146 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2147 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2148 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2149 cmd->current_channel = channel->hw_value;
2150 if (channel->band == IEEE80211_BAND_2GHZ)
2151 cmd->channel_flags = cpu_to_le32(0x00000081);
2152 else
2153 cmd->channel_flags = cpu_to_le32(0x00000000);
2154
2155 rc = mwl8k_post_cmd(hw, &cmd->header);
2156 kfree(cmd);
2157
2158 return rc;
2159}
2160
2161/*
2162 * CMD_SET_SLOT.
2163 */
2164struct mwl8k_cmd_set_slot {
2165 struct mwl8k_cmd_pkt header;
2166 __le16 action;
2167 __u8 short_slot;
2168} __attribute__((packed));
2169
5539bb51 2170static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 2171{
2172 struct mwl8k_cmd_set_slot *cmd;
2173 int rc;
2174
2175 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2176 if (cmd == NULL)
2177 return -ENOMEM;
2178
2179 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2180 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2181 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 2182 cmd->short_slot = short_slot_time;
a66098da
LB		 2183
2184 rc = mwl8k_post_cmd(hw, &cmd->header);
2185 kfree(cmd);
2186
2187 return rc;
2188}
2189
2190/*
2191 * CMD_MIMO_CONFIG.
2192 */
2193struct mwl8k_cmd_mimo_config {
2194 struct mwl8k_cmd_pkt header;
2195 __le32 action;
2196 __u8 rx_antenna_map;
2197 __u8 tx_antenna_map;
2198} __attribute__((packed));
2199
2200static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2201{
2202 struct mwl8k_cmd_mimo_config *cmd;
2203 int rc;
2204
2205 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2206 if (cmd == NULL)
2207 return -ENOMEM;
2208
2209 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2210 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2211 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2212 cmd->rx_antenna_map = rx;
2213 cmd->tx_antenna_map = tx;
2214
2215 rc = mwl8k_post_cmd(hw, &cmd->header);
2216 kfree(cmd);
2217
2218 return rc;
2219}
2220
2221/*
2222 * CMD_ENABLE_SNIFFER.
2223 */
2224struct mwl8k_cmd_enable_sniffer {
2225 struct mwl8k_cmd_pkt header;
2226 __le32 action;
2227} __attribute__((packed));
2228
2229static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2230{
2231 struct mwl8k_cmd_enable_sniffer *cmd;
2232 int rc;
2233
2234 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2235 if (cmd == NULL)
2236 return -ENOMEM;
2237
2238 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2239 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2240 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 2241
2242 rc = mwl8k_post_cmd(hw, &cmd->header);
2243 kfree(cmd);
2244
2245 return rc;
2246}
2247
32060e1b
LB		 2248/*
2249 * CMD_SET_MAC_ADDR.
2250 */
2251struct mwl8k_cmd_set_mac_addr {
2252 struct mwl8k_cmd_pkt header;
259a8e7d
LB		 2253 union {
2254 struct {
2255 __le16 mac_type;
2256 __u8 mac_addr[ETH_ALEN];
2257 } mbss;
2258 __u8 mac_addr[ETH_ALEN];
2259 };
32060e1b
LB		 2260} __attribute__((packed));
2261
2262static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2263{
259a8e7d 2264 struct mwl8k_priv *priv = hw->priv;
32060e1b
LB		 2265 struct mwl8k_cmd_set_mac_addr *cmd;
2266 int rc;
2267
2268 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2269 if (cmd == NULL)
2270 return -ENOMEM;
2271
2272 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2273 cmd->header.length = cpu_to_le16(sizeof(*cmd));
259a8e7d
LB		 2274 if (priv->ap_fw) {
2275 cmd->mbss.mac_type = 0;
2276 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2277 } else {
2278 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2279 }
32060e1b
LB		 2280
2281 rc = mwl8k_post_cmd(hw, &cmd->header);
2282 kfree(cmd);
2283
2284 return rc;
2285}
2286
2287
a66098da 2288/*
ce9e2e1b 2289 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2290 */
2291struct mwl8k_cmd_set_rate_adapt_mode {
2292 struct mwl8k_cmd_pkt header;
2293 __le16 action;
2294 __le16 mode;
2295} __attribute__((packed));
2296
2297static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2298{
2299 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2300 int rc;
2301
2302 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2303 if (cmd == NULL)
2304 return -ENOMEM;
2305
2306 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2307 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2308 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2309 cmd->mode = cpu_to_le16(mode);
2310
2311 rc = mwl8k_post_cmd(hw, &cmd->header);
2312 kfree(cmd);
2313
2314 return rc;
2315}
2316
2317/*
2318 * CMD_SET_WMM_MODE.
2319 */
2320struct mwl8k_cmd_set_wmm {
2321 struct mwl8k_cmd_pkt header;
2322 __le16 action;
2323} __attribute__((packed));
2324
2325static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2326{
2327 struct mwl8k_priv *priv = hw->priv;
2328 struct mwl8k_cmd_set_wmm *cmd;
2329 int rc;
2330
2331 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2332 if (cmd == NULL)
2333 return -ENOMEM;
2334
2335 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2336 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2337 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2338
2339 rc = mwl8k_post_cmd(hw, &cmd->header);
2340 kfree(cmd);
2341
2342 if (!rc)
0439b1f5 2343 priv->wmm_enabled = enable;
a66098da
LB		 2344
2345 return rc;
2346}
2347
2348/*
2349 * CMD_SET_RTS_THRESHOLD.
2350 */
2351struct mwl8k_cmd_rts_threshold {
2352 struct mwl8k_cmd_pkt header;
2353 __le16 action;
2354 __le16 threshold;
2355} __attribute__((packed));
2356
2357static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2358 u16 action, u16 threshold)
a66098da
LB		 2359{
2360 struct mwl8k_cmd_rts_threshold *cmd;
2361 int rc;
2362
2363 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2364 if (cmd == NULL)
2365 return -ENOMEM;
2366
2367 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2368 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2369 cmd->action = cpu_to_le16(action);
733d3067 2370 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2371
2372 rc = mwl8k_post_cmd(hw, &cmd->header);
2373 kfree(cmd);
2374
2375 return rc;
2376}
2377
2378/*
2379 * CMD_SET_EDCA_PARAMS.
2380 */
2381struct mwl8k_cmd_set_edca_params {
2382 struct mwl8k_cmd_pkt header;
2383
2384 /* See MWL8K_SET_EDCA_XXX below */
2385 __le16 action;
2386
2387 /* TX opportunity in units of 32 us */
2388 __le16 txop;
2389
2e484c89
LB		 2390 union {
2391 struct {
2392 /* Log exponent of max contention period: 0...15 */
2393 __le32 log_cw_max;
2394
2395 /* Log exponent of min contention period: 0...15 */
2396 __le32 log_cw_min;
2397
2398 /* Adaptive interframe spacing in units of 32us */
2399 __u8 aifs;
2400
2401 /* TX queue to configure */
2402 __u8 txq;
2403 } ap;
2404 struct {
2405 /* Log exponent of max contention period: 0...15 */
2406 __u8 log_cw_max;
a66098da 2407
2e484c89
LB		 2408 /* Log exponent of min contention period: 0...15 */
2409 __u8 log_cw_min;
a66098da 2410
2e484c89
LB		 2411 /* Adaptive interframe spacing in units of 32us */
2412 __u8 aifs;
a66098da 2413
2e484c89
LB		 2414 /* TX queue to configure */
2415 __u8 txq;
2416 } sta;
2417 };
a66098da
LB		 2418} __attribute__((packed));
2419
a66098da
LB		 2420#define MWL8K_SET_EDCA_CW 0x01
2421#define MWL8K_SET_EDCA_TXOP 0x02
2422#define MWL8K_SET_EDCA_AIFS 0x04
2423
2424#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2425 MWL8K_SET_EDCA_TXOP | \
2426 MWL8K_SET_EDCA_AIFS)
2427
2428static int
2429mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2430 __u16 cw_min, __u16 cw_max,
2431 __u8 aifs, __u16 txop)
2432{
2e484c89 2433 struct mwl8k_priv *priv = hw->priv;
a66098da 2434 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2435 int rc;
2436
2437 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2438 if (cmd == NULL)
2439 return -ENOMEM;
2440
22995b24
LB		 2441 /*
2442 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2443 * this call.
2444 */
2445 qnum ^= !(qnum >> 1);
2446
a66098da
LB		 2447 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2448 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2449 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2450 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2451 if (priv->ap_fw) {
2452 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2453 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2454 cmd->ap.aifs = aifs;
2455 cmd->ap.txq = qnum;
2456 } else {
2457 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2458 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2459 cmd->sta.aifs = aifs;
2460 cmd->sta.txq = qnum;
2461 }
a66098da
LB		 2462
2463 rc = mwl8k_post_cmd(hw, &cmd->header);
2464 kfree(cmd);
2465
2466 return rc;
2467}
2468
2469/*
2470 * CMD_FINALIZE_JOIN.
2471 */
a66098da
LB		 2472#define MWL8K_FJ_BEACON_MAXLEN 128
2473
2474struct mwl8k_cmd_finalize_join {
2475 struct mwl8k_cmd_pkt header;
2476 __le32 sleep_interval; /* Number of beacon periods to sleep */
2477 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2478} __attribute__((packed));
2479
2480static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
16cec43d 2481 int framelen, int dtim)
a66098da
LB		 2482{
2483 struct mwl8k_cmd_finalize_join *cmd;
2484 struct ieee80211_mgmt *payload = frame;
16cec43d 2485 int payload_len;
a66098da
LB		 2486 int rc;
2487
a66098da
LB		 2488 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2489 if (cmd == NULL)
2490 return -ENOMEM;
2491
2492 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2493 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2494 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da 2495
16cec43d
LB		 2496 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2497 if (payload_len < 0)
2498 payload_len = 0;
2499 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
ce9e2e1b 2500 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da 2501
16cec43d 2502 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2503
2504 rc = mwl8k_post_cmd(hw, &cmd->header);
2505 kfree(cmd);
16cec43d 2506
a66098da
LB		 2507 return rc;
2508}
2509
2510/*
2511 * CMD_UPDATE_STADB.
2512 */
2513struct mwl8k_cmd_update_sta_db {
2514 struct mwl8k_cmd_pkt header;
2515
2516 /* See STADB_ACTION_TYPE */
2517 __le32 action;
2518
2519 /* Peer MAC address */
d89173f2 2520 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2521
2522 __le32 reserved;
2523
2524 /* Peer info - valid during add/update. */
2525 struct peer_capability_info peer_info;
2526} __attribute__((packed));
2527
2528static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2529 struct ieee80211_vif *vif, __u32 action)
2530{
2531 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2532 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2533 struct mwl8k_cmd_update_sta_db *cmd;
2534 struct peer_capability_info *peer_info;
a66098da 2535 int rc;
a66098da
LB		 2536
2537 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2538 if (cmd == NULL)
2539 return -ENOMEM;
2540
2541 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2542 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2543
2544 cmd->action = cpu_to_le32(action);
2545 peer_info = &cmd->peer_info;
d89173f2 2546 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2547
2548 switch (action) {
2549 case MWL8K_STA_DB_ADD_ENTRY:
2550 case MWL8K_STA_DB_MODIFY_ENTRY:
2551 /* Build peer_info block */
2552 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2553 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
140eb5e2
LB		 2554 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2555 sizeof(mwl8k_rateids));
a66098da
LB		 2556 peer_info->interop = 1;
2557 peer_info->amsdu_enabled = 0;
2558
a66098da
LB		 2559 rc = mwl8k_post_cmd(hw, &cmd->header);
2560 if (rc == 0)
2561 mv_vif->peer_id = peer_info->station_id;
2562
2563 break;
2564
2565 case MWL8K_STA_DB_DEL_ENTRY:
2566 case MWL8K_STA_DB_FLUSH:
2567 default:
2568 rc = mwl8k_post_cmd(hw, &cmd->header);
2569 if (rc == 0)
2570 mv_vif->peer_id = 0;
2571 break;
2572 }
2573 kfree(cmd);
2574
2575 return rc;
2576}
2577
2578/*
2579 * CMD_SET_AID.
2580 */
a66098da
LB		 2581#define MWL8K_FRAME_PROT_DISABLED 0x00
2582#define MWL8K_FRAME_PROT_11G 0x07
2583#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2584#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2585
2586struct mwl8k_cmd_update_set_aid {
2587 struct mwl8k_cmd_pkt header;
2588 __le16 aid;
2589
2590 /* AP's MAC address (BSSID) */
d89173f2 2591 __u8 bssid[ETH_ALEN];
a66098da 2592 __le16 protection_mode;
140eb5e2 2593 __u8 supp_rates[14];
a66098da
LB		 2594} __attribute__((packed));
2595
2596static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2597 struct ieee80211_vif *vif)
2598{
2599 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2600 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2601 struct mwl8k_cmd_update_set_aid *cmd;
a66098da
LB		 2602 u16 prot_mode;
2603 int rc;
2604
2605 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2606 if (cmd == NULL)
2607 return -ENOMEM;
2608
2609 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2610 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2611 cmd->aid = cpu_to_le16(info->aid);
2612
d89173f2 2613 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2614
a66098da
LB		 2615 if (info->use_cts_prot) {
2616 prot_mode = MWL8K_FRAME_PROT_11G;
2617 } else {
9ed6bcce 2618 switch (info->ht_operation_mode &
a66098da
LB		 2619 IEEE80211_HT_OP_MODE_PROTECTION) {
2620 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2621 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2622 break;
2623 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2624 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2625 break;
2626 default:
2627 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2628 break;
2629 }
2630 }
a66098da
LB		 2631 cmd->protection_mode = cpu_to_le16(prot_mode);
2632
140eb5e2 2633 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2634
2635 rc = mwl8k_post_cmd(hw, &cmd->header);
2636 kfree(cmd);
2637
2638 return rc;
2639}
2640
2641/*
2642 * CMD_SET_RATE.
2643 */
2644struct mwl8k_cmd_update_rateset {
2645 struct mwl8k_cmd_pkt header;
140eb5e2 2646 __u8 legacy_rates[14];
a66098da
LB		 2647
2648 /* Bitmap for supported MCS codes. */
0b5351a8
LB		 2649 __u8 mcs_set[16];
2650 __u8 reserved[16];
a66098da
LB		 2651} __attribute__((packed));
2652
2653static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2654 struct ieee80211_vif *vif)
2655{
a66098da 2656 struct mwl8k_cmd_update_rateset *cmd;
a66098da
LB		 2657 int rc;
2658
2659 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2660 if (cmd == NULL)
2661 return -ENOMEM;
2662
2663 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2664 cmd->header.length = cpu_to_le16(sizeof(*cmd));
140eb5e2 2665 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2666
2667 rc = mwl8k_post_cmd(hw, &cmd->header);
2668 kfree(cmd);
2669
2670 return rc;
2671}
2672
2673/*
2674 * CMD_USE_FIXED_RATE.
2675 */
2676#define MWL8K_RATE_TABLE_SIZE 8
2677#define MWL8K_UCAST_RATE 0
a66098da
LB		 2678#define MWL8K_USE_AUTO_RATE 0x0002
2679
2680struct mwl8k_rate_entry {
2681 /* Set to 1 if HT rate, 0 if legacy. */
2682 __le32 is_ht_rate;
2683
2684 /* Set to 1 to use retry_count field. */
2685 __le32 enable_retry;
2686
2687 /* Specified legacy rate or MCS. */
2688 __le32 rate;
2689
2690 /* Number of allowed retries. */
2691 __le32 retry_count;
2692} __attribute__((packed));
2693
2694struct mwl8k_rate_table {
2695 /* 1 to allow specified rate and below */
2696 __le32 allow_rate_drop;
2697 __le32 num_rates;
2698 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2699} __attribute__((packed));
2700
2701struct mwl8k_cmd_use_fixed_rate {
2702 struct mwl8k_cmd_pkt header;
2703 __le32 action;
2704 struct mwl8k_rate_table rate_table;
2705
2706 /* Unicast, Broadcast or Multicast */
2707 __le32 rate_type;
2708 __le32 reserved1;
2709 __le32 reserved2;
2710} __attribute__((packed));
2711
2712static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2713 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2714{
2715 struct mwl8k_cmd_use_fixed_rate *cmd;
2716 int count;
2717 int rc;
2718
2719 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2720 if (cmd == NULL)
2721 return -ENOMEM;
2722
2723 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2724 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2725
2726 cmd->action = cpu_to_le32(action);
2727 cmd->rate_type = cpu_to_le32(rate_type);
2728
2729 if (rate_table != NULL) {
c2c357ce
LB		 2730 /*
2731 * Copy over each field manually so that endian
2732 * conversion can be done.
2733 */
a66098da
LB		 2734 cmd->rate_table.allow_rate_drop =
2735 cpu_to_le32(rate_table->allow_rate_drop);
2736 cmd->rate_table.num_rates =
2737 cpu_to_le32(rate_table->num_rates);
2738
2739 for (count = 0; count < rate_table->num_rates; count++) {
2740 struct mwl8k_rate_entry *dst =
2741 &cmd->rate_table.rate_entry[count];
2742 struct mwl8k_rate_entry *src =
2743 &rate_table->rate_entry[count];
2744
2745 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2746 dst->enable_retry = cpu_to_le32(src->enable_retry);
2747 dst->rate = cpu_to_le32(src->rate);
2748 dst->retry_count = cpu_to_le32(src->retry_count);
2749 }
2750 }
2751
2752 rc = mwl8k_post_cmd(hw, &cmd->header);
2753 kfree(cmd);
2754
2755 return rc;
2756}
2757
2758
2759/*
2760 * Interrupt handling.
2761 */
2762static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2763{
2764 struct ieee80211_hw *hw = dev_id;
2765 struct mwl8k_priv *priv = hw->priv;
2766 u32 status;
2767
2768 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2769 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2770
a66098da
LB		 2771 if (!status)
2772 return IRQ_NONE;
2773
2774 if (status & MWL8K_A2H_INT_TX_DONE)
2775 tasklet_schedule(&priv->tx_reclaim_task);
2776
2777 if (status & MWL8K_A2H_INT_RX_READY) {
2778 while (rxq_process(hw, 0, 1))
2779 rxq_refill(hw, 0, 1);
2780 }
2781
2782 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2783 if (priv->hostcmd_wait != NULL)
a66098da 2784 complete(priv->hostcmd_wait);
a66098da
LB		 2785 }
2786
2787 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2788 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2789 priv->radio_on && priv->pending_tx_pkts)
618952a7 2790 mwl8k_tx_start(priv);
a66098da
LB		 2791 }
2792
2793 return IRQ_HANDLED;
2794}
2795
2796
2797/*
2798 * Core driver operations.
2799 */
2800static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2801{
2802 struct mwl8k_priv *priv = hw->priv;
2803 int index = skb_get_queue_mapping(skb);
2804 int rc;
2805
2806 if (priv->current_channel == NULL) {
2807 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2808 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2809 dev_kfree_skb(skb);
2810 return NETDEV_TX_OK;
2811 }
2812
2813 rc = mwl8k_txq_xmit(hw, index, skb);
2814
2815 return rc;
2816}
2817
a66098da
LB		 2818static int mwl8k_start(struct ieee80211_hw *hw)
2819{
a66098da
LB		 2820 struct mwl8k_priv *priv = hw->priv;
2821 int rc;
2822
a0607fd3 2823 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 2824 IRQF_SHARED, MWL8K_NAME, hw);
2825 if (rc) {
2826 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2827 wiphy_name(hw->wiphy));
2ec610cb 2828 return -EIO;
a66098da
LB		 2829 }
2830
2ec610cb
LB		 2831 /* Enable tx reclaim tasklet */
2832 tasklet_enable(&priv->tx_reclaim_task);
2833
a66098da 2834 /* Enable interrupts */
c23b5a69 2835 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2836
2ec610cb
LB		 2837 rc = mwl8k_fw_lock(hw);
2838 if (!rc) {
2839 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2840
5e4cf166
LB		 2841 if (!priv->ap_fw) {
2842 if (!rc)
2843 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2844
5e4cf166
LB		 2845 if (!rc)
2846 rc = mwl8k_cmd_set_pre_scan(hw);
2847
2848 if (!rc)
2849 rc = mwl8k_cmd_set_post_scan(hw,
2850 "\x00\x00\x00\x00\x00\x00");
2851 }
2ec610cb
LB		 2852
2853 if (!rc)
2854 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2855
2ec610cb
LB		 2856 if (!rc)
2857 rc = mwl8k_set_wmm(hw, 0);
a66098da 2858
2ec610cb
LB		 2859 mwl8k_fw_unlock(hw);
2860 }
2861
2862 if (rc) {
2863 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2864 free_irq(priv->pdev->irq, hw);
2865 tasklet_disable(&priv->tx_reclaim_task);
2866 }
a66098da
LB		 2867
2868 return rc;
2869}
2870
a66098da
LB		 2871static void mwl8k_stop(struct ieee80211_hw *hw)
2872{
a66098da
LB		 2873 struct mwl8k_priv *priv = hw->priv;
2874 int i;
2875
d3cea0b8 2876 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2877
2878 ieee80211_stop_queues(hw);
2879
a66098da 2880 /* Disable interrupts */
a66098da 2881 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2882 free_irq(priv->pdev->irq, hw);
2883
2884 /* Stop finalize join worker */
2885 cancel_work_sync(&priv->finalize_join_worker);
2886 if (priv->beacon_skb != NULL)
2887 dev_kfree_skb(priv->beacon_skb);
2888
2889 /* Stop tx reclaim tasklet */
2890 tasklet_disable(&priv->tx_reclaim_task);
2891
a66098da
LB		 2892 /* Return all skbs to mac80211 */
2893 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2894 mwl8k_txq_reclaim(hw, i, 1);
2895}
2896
2897static int mwl8k_add_interface(struct ieee80211_hw *hw,
2898 struct ieee80211_if_init_conf *conf)
2899{
2900 struct mwl8k_priv *priv = hw->priv;
2901 struct mwl8k_vif *mwl8k_vif;
2902
2903 /*
2904 * We only support one active interface at a time.
2905 */
2906 if (priv->vif != NULL)
2907 return -EBUSY;
2908
2909 /*
2910 * We only support managed interfaces for now.
2911 */
240e86ef 2912 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2913 return -EINVAL;
2914
a43c49a8
LB		 2915 /*
2916 * Reject interface creation if sniffer mode is active, as
2917 * STA operation is mutually exclusive with hardware sniffer
2918 * mode.
2919 */
2920 if (priv->sniffer_enabled) {
2921 printk(KERN_INFO "%s: unable to create STA "
2922 "interface due to sniffer mode being enabled\n",
2923 wiphy_name(hw->wiphy));
2924 return -EINVAL;
2925 }
2926
a66098da
LB		 2927 /* Clean out driver private area */
2928 mwl8k_vif = MWL8K_VIF(conf->vif);
2929 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2930
32060e1b
LB		 2931 /* Set and save the mac address */
2932 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2933 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2934
2935 /* Back pointer to parent config block */
2936 mwl8k_vif->priv = priv;
2937
a66098da
LB		 2938 /* Set Initial sequence number to zero */
2939 mwl8k_vif->seqno = 0;
2940
2941 priv->vif = conf->vif;
2942 priv->current_channel = NULL;
2943
2944 return 0;
2945}
2946
2947static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2948 struct ieee80211_if_init_conf *conf)
2949{
2950 struct mwl8k_priv *priv = hw->priv;
2951
2952 if (priv->vif == NULL)
2953 return;
2954
32060e1b
LB		 2955 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2956
a66098da
LB		 2957 priv->vif = NULL;
2958}
2959
ee03a932 2960static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2961{
a66098da
LB		 2962 struct ieee80211_conf *conf = &hw->conf;
2963 struct mwl8k_priv *priv = hw->priv;
ee03a932 2964 int rc;
a66098da 2965
7595d67a
LB		 2966 if (conf->flags & IEEE80211_CONF_IDLE) {
2967 mwl8k_cmd_802_11_radio_disable(hw);
2968 priv->current_channel = NULL;
ee03a932 2969 return 0;
7595d67a
LB		 2970 }
2971
ee03a932
LB		 2972 rc = mwl8k_fw_lock(hw);
2973 if (rc)
2974 return rc;
a66098da 2975
ee03a932
LB		 2976 rc = mwl8k_cmd_802_11_radio_enable(hw);
2977 if (rc)
2978 goto out;
a66098da 2979
ee03a932
LB		 2980 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2981 if (rc)
2982 goto out;
2983
2984 priv->current_channel = conf->channel;
a66098da
LB		 2985
2986 if (conf->power_level > 18)
2987 conf->power_level = 18;
ee03a932
LB		 2988 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2989 if (rc)
2990 goto out;
a66098da 2991
08b06347
LB		 2992 if (priv->ap_fw) {
2993 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2994 if (!rc)
2995 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2996 } else {
2997 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2998 }
a66098da 2999
ee03a932
LB		 3000out:
3001 mwl8k_fw_unlock(hw);
a66098da 3002
ee03a932 3003 return rc;
a66098da
LB		 3004}
3005
3a980d0a
LB		 3006static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3007 struct ieee80211_vif *vif,
3008 struct ieee80211_bss_conf *info,
3009 u32 changed)
a66098da 3010{
a66098da
LB		 3011 struct mwl8k_priv *priv = hw->priv;
3012 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 3013 int rc;
3014
3a980d0a
LB		 3015 if ((changed & BSS_CHANGED_ASSOC) == 0)
3016 return;
a66098da 3017
a66098da
LB		 3018 priv->capture_beacon = false;
3019
3a980d0a 3020 rc = mwl8k_fw_lock(hw);
942457d6 3021 if (rc)
3a980d0a
LB		 3022 return;
3023
a66098da
LB		 3024 if (info->assoc) {
3025 memcpy(&mwl8k_vif->bss_info, info,
3026 sizeof(struct ieee80211_bss_conf));
3027
d1844d77
LB		 3028 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3029
a66098da 3030 /* Install rates */
3a980d0a
LB		 3031 rc = mwl8k_update_rateset(hw, vif);
3032 if (rc)
3033 goto out;
a66098da
LB		 3034
3035 /* Turn on rate adaptation */
3a980d0a
LB		 3036 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3037 MWL8K_UCAST_RATE, NULL);
3038 if (rc)
3039 goto out;
a66098da
LB		 3040
3041 /* Set radio preamble */
3a980d0a
LB		 3042 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3043 if (rc)
3044 goto out;
a66098da
LB		 3045
3046 /* Set slot time */
3a980d0a
LB		 3047 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3048 if (rc)
3049 goto out;
a66098da
LB		 3050
3051 /* Update peer rate info */
3a980d0a
LB		 3052 rc = mwl8k_cmd_update_sta_db(hw, vif,
3053 MWL8K_STA_DB_MODIFY_ENTRY);
3054 if (rc)
3055 goto out;
a66098da
LB		 3056
3057 /* Set AID */
3a980d0a
LB		 3058 rc = mwl8k_cmd_set_aid(hw, vif);
3059 if (rc)
3060 goto out;
a66098da
LB		 3061
3062 /*
3063 * Finalize the join. Tell rx handler to process
3064 * next beacon from our BSSID.
3065 */
d89173f2 3066 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 3067 priv->capture_beacon = true;
3068 } else {
3a980d0a 3069 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 3070 memset(&mwl8k_vif->bss_info, 0,
3071 sizeof(struct ieee80211_bss_conf));
d89173f2 3072 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 3073 }
3074
3a980d0a
LB		 3075out:
3076 mwl8k_fw_unlock(hw);
a66098da
LB		 3077}
3078
e81cd2d6
LB		 3079static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3080 int mc_count, struct dev_addr_list *mclist)
3081{
3082 struct mwl8k_cmd_pkt *cmd;
3083
447ced07
LB		 3084 /*
3085 * Synthesize and return a command packet that programs the
3086 * hardware multicast address filter. At this point we don't
3087 * know whether FIF_ALLMULTI is being requested, but if it is,
3088 * we'll end up throwing this packet away and creating a new
3089 * one in mwl8k_configure_filter().
3090 */
3091 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3092
3093 return (unsigned long)cmd;
3094}
3095
a43c49a8
LB		 3096static int
3097mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3098 unsigned int changed_flags,
3099 unsigned int *total_flags)
3100{
3101 struct mwl8k_priv *priv = hw->priv;
3102
3103 /*
3104 * Hardware sniffer mode is mutually exclusive with STA
3105 * operation, so refuse to enable sniffer mode if a STA
3106 * interface is active.
3107 */
3108 if (priv->vif != NULL) {
3109 if (net_ratelimit())
3110 printk(KERN_INFO "%s: not enabling sniffer "
3111 "mode because STA interface is active\n",
3112 wiphy_name(hw->wiphy));
3113 return 0;
3114 }
3115
3116 if (!priv->sniffer_enabled) {
3117 if (mwl8k_enable_sniffer(hw, 1))
3118 return 0;
3119 priv->sniffer_enabled = true;
3120 }
3121
3122 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3123 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3124 FIF_OTHER_BSS;
3125
3126 return 1;
3127}
3128
e6935ea1
LB		 3129static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3130 unsigned int changed_flags,
3131 unsigned int *total_flags,
3132 u64 multicast)
3133{
3134 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3135 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3136
c0adae2c
LB		 3137 /*
3138 * AP firmware doesn't allow fine-grained control over
3139 * the receive filter.
3140 */
3141 if (priv->ap_fw) {
3142 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3143 kfree(cmd);
3144 return;
3145 }
3146
a43c49a8
LB		 3147 /*
3148 * Enable hardware sniffer mode if FIF_CONTROL or
3149 * FIF_OTHER_BSS is requested.
3150 */
3151 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3152 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3153 kfree(cmd);
3154 return;
3155 }
a66098da 3156
e6935ea1 3157 /* Clear unsupported feature flags */
447ced07 3158 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3159
90852f7a
LB		 3160 if (mwl8k_fw_lock(hw)) {
3161 kfree(cmd);
e6935ea1 3162 return;
90852f7a 3163 }
a66098da 3164
a43c49a8
LB		 3165 if (priv->sniffer_enabled) {
3166 mwl8k_enable_sniffer(hw, 0);
3167 priv->sniffer_enabled = false;
3168 }
3169
e6935ea1 3170 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3171 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3172 /*
3173 * Disable the BSS filter.
3174 */
e6935ea1 3175 mwl8k_cmd_set_pre_scan(hw);
77165d88 3176 } else {
a94cc97e
LB		 3177 u8 *bssid;
3178
77165d88
LB		 3179 /*
3180 * Enable the BSS filter.
3181 *
3182 * If there is an active STA interface, use that
3183 * interface's BSSID, otherwise use a dummy one
3184 * (where the OUI part needs to be nonzero for
3185 * the BSSID to be accepted by POST_SCAN).
3186 */
3187 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 3188 if (priv->vif != NULL)
3189 bssid = MWL8K_VIF(priv->vif)->bssid;
3190
e6935ea1 3191 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3192 }
3193 }
3194
447ced07
LB		 3195 /*
3196 * If FIF_ALLMULTI is being requested, throw away the command
3197 * packet that ->prepare_multicast() built and replace it with
3198 * a command packet that enables reception of all multicast
3199 * packets.
3200 */
3201 if (*total_flags & FIF_ALLMULTI) {
3202 kfree(cmd);
3203 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3204 }
3205
3206 if (cmd != NULL) {
3207 mwl8k_post_cmd(hw, cmd);
3208 kfree(cmd);
e6935ea1 3209 }
a66098da 3210
e6935ea1 3211 mwl8k_fw_unlock(hw);
a66098da
LB		 3212}
3213
a66098da
LB		 3214static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3215{
733d3067 3216 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3217}
3218
a66098da
LB		 3219static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3220 const struct ieee80211_tx_queue_params *params)
3221{
3e4f542c 3222 struct mwl8k_priv *priv = hw->priv;
a66098da 3223 int rc;
a66098da 3224
3e4f542c
LB		 3225 rc = mwl8k_fw_lock(hw);
3226 if (!rc) {
3227 if (!priv->wmm_enabled)
3228 rc = mwl8k_set_wmm(hw, 1);
a66098da 3229
3e4f542c
LB		 3230 if (!rc)
3231 rc = mwl8k_set_edca_params(hw, queue,
3232 params->cw_min,
3233 params->cw_max,
3234 params->aifs,
3235 params->txop);
3236
3237 mwl8k_fw_unlock(hw);
a66098da 3238 }
3e4f542c 3239
a66098da
LB		 3240 return rc;
3241}
3242
3243static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3244 struct ieee80211_tx_queue_stats *stats)
3245{
3246 struct mwl8k_priv *priv = hw->priv;
3247 struct mwl8k_tx_queue *txq;
3248 int index;
3249
3250 spin_lock_bh(&priv->tx_lock);
3251 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3252 txq = priv->txq + index;
45eb400d 3253 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3254 sizeof(struct ieee80211_tx_queue_stats));
3255 }
3256 spin_unlock_bh(&priv->tx_lock);
a66098da 3257
954ef509 3258 return 0;
a66098da
LB		 3259}
3260
3261static int mwl8k_get_stats(struct ieee80211_hw *hw,
3262 struct ieee80211_low_level_stats *stats)
3263{
954ef509 3264 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 3265}
3266
3267static const struct ieee80211_ops mwl8k_ops = {
3268 .tx = mwl8k_tx,
3269 .start = mwl8k_start,
3270 .stop = mwl8k_stop,
3271 .add_interface = mwl8k_add_interface,
3272 .remove_interface = mwl8k_remove_interface,
3273 .config = mwl8k_config,
a66098da 3274 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3275 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3276 .configure_filter = mwl8k_configure_filter,
3277 .set_rts_threshold = mwl8k_set_rts_threshold,
3278 .conf_tx = mwl8k_conf_tx,
3279 .get_tx_stats = mwl8k_get_tx_stats,
3280 .get_stats = mwl8k_get_stats,
3281};
3282
3283static void mwl8k_tx_reclaim_handler(unsigned long data)
3284{
3285 int i;
3286 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3287 struct mwl8k_priv *priv = hw->priv;
3288
3289 spin_lock_bh(&priv->tx_lock);
3290 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3291 mwl8k_txq_reclaim(hw, i, 0);
3292
88de754a 3293 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3294 complete(priv->tx_wait);
3295 priv->tx_wait = NULL;
a66098da
LB		 3296 }
3297 spin_unlock_bh(&priv->tx_lock);
3298}
3299
3300static void mwl8k_finalize_join_worker(struct work_struct *work)
3301{
3302 struct mwl8k_priv *priv =
3303 container_of(work, struct mwl8k_priv, finalize_join_worker);
3304 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3305 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3306
3307 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3308 dev_kfree_skb(skb);
3309
3310 priv->beacon_skb = NULL;
3311}
3312
bcb628d5
JL		 3313enum {
3314 MWL8687 = 0,
3315 MWL8366,
6f6d1e9a
LB		 3316};
3317
bcb628d5
JL		 3318static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3319 {
3320 .part_name = "88w8687",
3321 .helper_image = "mwl8k/helper_8687.fw",
3322 .fw_image = "mwl8k/fmimage_8687.fw",
3323 .rxd_ops = &rxd_8687_ops,
3324 .modes = BIT(NL80211_IFTYPE_STATION),
3325 },
3326 {
3327 .part_name = "88w8366",
3328 .helper_image = "mwl8k/helper_8366.fw",
3329 .fw_image = "mwl8k/fmimage_8366.fw",
3330 .rxd_ops = &rxd_8366_ops,
3331 .modes = 0,
3332 },
45a390dd
LB		 3333};
3334
3335static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
bcb628d5
JL		 3336 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3337 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3338 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3339 { },
45a390dd
LB		 3340};
3341MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3342
a66098da
LB		 3343static int __devinit mwl8k_probe(struct pci_dev *pdev,
3344 const struct pci_device_id *id)
3345{
2aa7b01f 3346 static int printed_version = 0;
a66098da
LB		 3347 struct ieee80211_hw *hw;
3348 struct mwl8k_priv *priv;
a66098da
LB		 3349 int rc;
3350 int i;
2aa7b01f
LB		 3351
3352 if (!printed_version) {
3353 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3354 printed_version = 1;
3355 }
a66098da
LB		 3356
3357 rc = pci_enable_device(pdev);
3358 if (rc) {
3359 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3360 MWL8K_NAME);
3361 return rc;
3362 }
3363
3364 rc = pci_request_regions(pdev, MWL8K_NAME);
3365 if (rc) {
3366 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3367 MWL8K_NAME);
3db95e50 3368 goto err_disable_device;
a66098da
LB		 3369 }
3370
3371 pci_set_master(pdev);
3372
3373 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3374 if (hw == NULL) {
3375 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3376 rc = -ENOMEM;
3377 goto err_free_reg;
3378 }
3379
3380 priv = hw->priv;
3381 priv->hw = hw;
3382 priv->pdev = pdev;
bcb628d5 3383 priv->device_info = &mwl8k_info_tbl[id->driver_data];
54bc3a0d 3384 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3385 priv->sniffer_enabled = false;
0439b1f5 3386 priv->wmm_enabled = false;
a66098da 3387 priv->pending_tx_pkts = 0;
a66098da 3388
a66098da
LB		 3389 SET_IEEE80211_DEV(hw, &pdev->dev);
3390 pci_set_drvdata(pdev, hw);
3391
5b9482dd
LB		 3392 priv->sram = pci_iomap(pdev, 0, 0x10000);
3393 if (priv->sram == NULL) {
3394 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3395 wiphy_name(hw->wiphy));
a66098da
LB		 3396 goto err_iounmap;
3397 }
3398
5b9482dd
LB		 3399 /*
3400 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3401 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3402 */
3403 priv->regs = pci_iomap(pdev, 1, 0x10000);
3404 if (priv->regs == NULL) {
3405 priv->regs = pci_iomap(pdev, 2, 0x10000);
3406 if (priv->regs == NULL) {
3407 printk(KERN_ERR "%s: Cannot map device registers\n",
3408 wiphy_name(hw->wiphy));
3409 goto err_iounmap;
3410 }
3411 }
3412
a66098da
LB		 3413 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3414 priv->band.band = IEEE80211_BAND_2GHZ;
3415 priv->band.channels = priv->channels;
3416 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3417 priv->band.bitrates = priv->rates;
3418 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3419 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3420
3421 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3422 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3423
3424 /*
3425 * Extra headroom is the size of the required DMA header
3426 * minus the size of the smallest 802.11 frame (CTS frame).
3427 */
3428 hw->extra_tx_headroom =
3429 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3430
3431 hw->channel_change_time = 10;
3432
3433 hw->queues = MWL8K_TX_QUEUES;
3434
547810e3 3435 hw->wiphy->interface_modes = priv->device_info->modes;
a66098da
LB		 3436
3437 /* Set rssi and noise values to dBm */
ce9e2e1b 3438 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3439 hw->vif_data_size = sizeof(struct mwl8k_vif);
3440 priv->vif = NULL;
3441
3442 /* Set default radio state and preamble */
c46563b7 3443 priv->radio_on = 0;
68ce3884 3444 priv->radio_short_preamble = 0;
a66098da
LB		 3445
3446 /* Finalize join worker */
3447 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3448
3449 /* TX reclaim tasklet */
3450 tasklet_init(&priv->tx_reclaim_task,
3451 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3452 tasklet_disable(&priv->tx_reclaim_task);
3453
a66098da
LB		 3454 /* Power management cookie */
3455 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3456 if (priv->cookie == NULL)
3457 goto err_iounmap;
3458
3459 rc = mwl8k_rxq_init(hw, 0);
3460 if (rc)
3461 goto err_iounmap;
3462 rxq_refill(hw, 0, INT_MAX);
3463
618952a7
LB		 3464 mutex_init(&priv->fw_mutex);
3465 priv->fw_mutex_owner = NULL;
3466 priv->fw_mutex_depth = 0;
618952a7
LB		 3467 priv->hostcmd_wait = NULL;
3468
a66098da
LB		 3469 spin_lock_init(&priv->tx_lock);
3470
88de754a
LB		 3471 priv->tx_wait = NULL;
3472
a66098da
LB		 3473 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3474 rc = mwl8k_txq_init(hw, i);
3475 if (rc)
3476 goto err_free_queues;
3477 }
3478
3479 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3480 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3481 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3482 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3483
a0607fd3 3484 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3485 IRQF_SHARED, MWL8K_NAME, hw);
3486 if (rc) {
3487 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3488 wiphy_name(hw->wiphy));
a66098da
LB		 3489 goto err_free_queues;
3490 }
3491
3492 /* Reset firmware and hardware */
3493 mwl8k_hw_reset(priv);
3494
3495 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3496 rc = mwl8k_request_firmware(priv);
a66098da 3497 if (rc) {
c2c357ce
LB		 3498 printk(KERN_ERR "%s: Firmware files not found\n",
3499 wiphy_name(hw->wiphy));
a66098da
LB		 3500 goto err_free_irq;
3501 }
3502
3503 /* Load firmware into hardware */
c2c357ce 3504 rc = mwl8k_load_firmware(hw);
a66098da 3505 if (rc) {
c2c357ce
LB		 3506 printk(KERN_ERR "%s: Cannot start firmware\n",
3507 wiphy_name(hw->wiphy));
a66098da
LB		 3508 goto err_stop_firmware;
3509 }
3510
3511 /* Reclaim memory once firmware is successfully loaded */
3512 mwl8k_release_firmware(priv);
3513
3514 /*
3515 * Temporarily enable interrupts. Initial firmware host
3516 * commands use interrupts and avoids polling. Disable
3517 * interrupts when done.
3518 */
c23b5a69 3519 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3520
3521 /* Get config data, mac addrs etc */
42fba21d
LB		 3522 if (priv->ap_fw) {
3523 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3524 if (!rc)
3525 rc = mwl8k_cmd_set_hw_spec(hw);
3526 } else {
3527 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3528 }
a66098da 3529 if (rc) {
c2c357ce
LB		 3530 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3531 wiphy_name(hw->wiphy));
a66098da
LB		 3532 goto err_stop_firmware;
3533 }
3534
3535 /* Turn radio off */
c46563b7 3536 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3537 if (rc) {
c2c357ce 3538 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3539 goto err_stop_firmware;
3540 }
3541
32060e1b
LB		 3542 /* Clear MAC address */
3543 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3544 if (rc) {
3545 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3546 wiphy_name(hw->wiphy));
3547 goto err_stop_firmware;
3548 }
3549
a66098da 3550 /* Disable interrupts */
a66098da 3551 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3552 free_irq(priv->pdev->irq, hw);
3553
3554 rc = ieee80211_register_hw(hw);
3555 if (rc) {
c2c357ce
LB		 3556 printk(KERN_ERR "%s: Cannot register device\n",
3557 wiphy_name(hw->wiphy));
a66098da
LB		 3558 goto err_stop_firmware;
3559 }
3560
eae74e65 3561 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3562 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3563 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3564 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3565 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3566 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3567
3568 return 0;
3569
3570err_stop_firmware:
3571 mwl8k_hw_reset(priv);
3572 mwl8k_release_firmware(priv);
3573
3574err_free_irq:
a66098da 3575 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3576 free_irq(priv->pdev->irq, hw);
3577
3578err_free_queues:
3579 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3580 mwl8k_txq_deinit(hw, i);
3581 mwl8k_rxq_deinit(hw, 0);
3582
3583err_iounmap:
3584 if (priv->cookie != NULL)
3585 pci_free_consistent(priv->pdev, 4,
3586 priv->cookie, priv->cookie_dma);
3587
3588 if (priv->regs != NULL)
3589 pci_iounmap(pdev, priv->regs);
3590
5b9482dd
LB		 3591 if (priv->sram != NULL)
3592 pci_iounmap(pdev, priv->sram);
3593
a66098da
LB		 3594 pci_set_drvdata(pdev, NULL);
3595 ieee80211_free_hw(hw);
3596
3597err_free_reg:
3598 pci_release_regions(pdev);
3db95e50
LB		 3599
3600err_disable_device:
a66098da
LB		 3601 pci_disable_device(pdev);
3602
3603 return rc;
3604}
3605
230f7af0 3606static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3607{
3608 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3609}
3610
230f7af0 3611static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3612{
3613 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3614 struct mwl8k_priv *priv;
3615 int i;
3616
3617 if (hw == NULL)
3618 return;
3619 priv = hw->priv;
3620
3621 ieee80211_stop_queues(hw);
3622
60aa569f
LB		 3623 ieee80211_unregister_hw(hw);
3624
a66098da
LB		 3625 /* Remove tx reclaim tasklet */
3626 tasklet_kill(&priv->tx_reclaim_task);
3627
a66098da
LB		 3628 /* Stop hardware */
3629 mwl8k_hw_reset(priv);
3630
3631 /* Return all skbs to mac80211 */
3632 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3633 mwl8k_txq_reclaim(hw, i, 1);
3634
a66098da
LB		 3635 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3636 mwl8k_txq_deinit(hw, i);
3637
3638 mwl8k_rxq_deinit(hw, 0);
3639
c2c357ce 3640 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3641
3642 pci_iounmap(pdev, priv->regs);
5b9482dd 3643 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3644 pci_set_drvdata(pdev, NULL);
3645 ieee80211_free_hw(hw);
3646 pci_release_regions(pdev);
3647 pci_disable_device(pdev);
3648}
3649
3650static struct pci_driver mwl8k_driver = {
3651 .name = MWL8K_NAME,
45a390dd 3652 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3653 .probe = mwl8k_probe,
3654 .remove = __devexit_p(mwl8k_remove),
3655 .shutdown = __devexit_p(mwl8k_shutdown),
3656};
3657
3658static int __init mwl8k_init(void)
3659{
3660 return pci_register_driver(&mwl8k_driver);
3661}
3662
3663static void __exit mwl8k_exit(void)
3664{
3665 pci_unregister_driver(&mwl8k_driver);
3666}
3667
3668module_init(mwl8k_init);
3669module_exit(mwl8k_exit);
c2c357ce
LB		 3670
3671MODULE_DESCRIPTION(MWL8K_DESC);
3672MODULE_VERSION(MWL8K_VERSION);
3673MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3674MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)