mt76: move mt76x02_bss_info_changed in mt76x02-lib module
[linux-2.6-block.git] / drivers / net / wireless / mediatek / mt76 / mt76x02_dfs.h
CommitLineData
e40803f2
LB
1/*
2 * Copyright (C) 2016 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef __MT76x02_DFS_H
18#define __MT76x02_DFS_H
19
20#include <linux/types.h>
21#include <linux/nl80211.h>
22
23#define MT_DFS_GP_INTERVAL (10 << 4) /* 64 us unit */
24#define MT_DFS_NUM_ENGINES 4
25
26/* bbp params */
27#define MT_DFS_SYM_ROUND 0
28#define MT_DFS_DELTA_DELAY 2
29#define MT_DFS_VGA_MASK 0
30#define MT_DFS_PWR_GAIN_OFFSET 3
31#define MT_DFS_PWR_DOWN_TIME 0xf
32#define MT_DFS_RX_PE_MASK 0xff
33#define MT_DFS_PKT_END_MASK 0
34#define MT_DFS_CH_EN 0xf
35
36/* sw detector params */
37#define MT_DFS_EVENT_LOOP 64
38#define MT_DFS_SW_TIMEOUT (HZ / 20)
39#define MT_DFS_EVENT_WINDOW (HZ / 5)
40#define MT_DFS_SEQUENCE_WINDOW (200 * (1 << 20))
41#define MT_DFS_EVENT_TIME_MARGIN 2000
42#define MT_DFS_PRI_MARGIN 4
43#define MT_DFS_SEQUENCE_TH 6
44
45#define MT_DFS_FCC_MAX_PRI ((28570 << 1) + 1000)
46#define MT_DFS_FCC_MIN_PRI (3000 - 2)
47#define MT_DFS_JP_MAX_PRI ((80000 << 1) + 1000)
48#define MT_DFS_JP_MIN_PRI (28500 - 2)
49#define MT_DFS_ETSI_MAX_PRI (133333 + 125000 + 117647 + 1000)
50#define MT_DFS_ETSI_MIN_PRI (4500 - 20)
51
52struct mt76x02_radar_specs {
53 u8 mode;
54 u16 avg_len;
55 u16 e_low;
56 u16 e_high;
57 u16 w_low;
58 u16 w_high;
59 u16 w_margin;
60 u32 t_low;
61 u32 t_high;
62 u16 t_margin;
63 u32 b_low;
64 u32 b_high;
65 u32 event_expiration;
66 u16 pwr_jmp;
67};
68
69#define MT_DFS_CHECK_EVENT(x) ((x) != GENMASK(31, 0))
70#define MT_DFS_EVENT_ENGINE(x) (((x) & BIT(31)) ? 2 : 0)
71#define MT_DFS_EVENT_TIMESTAMP(x) ((x) & GENMASK(21, 0))
72#define MT_DFS_EVENT_WIDTH(x) ((x) & GENMASK(11, 0))
73struct mt76x02_dfs_event {
74 unsigned long fetch_ts;
75 u32 ts;
76 u16 width;
77 u8 engine;
78};
79
80#define MT_DFS_EVENT_BUFLEN 256
81struct mt76x02_dfs_event_rb {
82 struct mt76x02_dfs_event data[MT_DFS_EVENT_BUFLEN];
83 int h_rb, t_rb;
84};
85
86struct mt76x02_dfs_sequence {
87 struct list_head head;
88 u32 first_ts;
89 u32 last_ts;
90 u32 pri;
91 u16 count;
92 u8 engine;
93};
94
95struct mt76x02_dfs_hw_pulse {
96 u8 engine;
97 u32 period;
98 u32 w1;
99 u32 w2;
100 u32 burst;
101};
102
103struct mt76x02_dfs_sw_detector_params {
104 u32 min_pri;
105 u32 max_pri;
106 u32 pri_margin;
107};
108
109struct mt76x02_dfs_engine_stats {
110 u32 hw_pattern;
111 u32 hw_pulse_discarded;
112 u32 sw_pattern;
113};
114
115struct mt76x02_dfs_seq_stats {
116 u32 seq_pool_len;
117 u32 seq_len;
118};
119
120struct mt76x02_dfs_pattern_detector {
121 enum nl80211_dfs_regions region;
122
123 u8 chirp_pulse_cnt;
124 u32 chirp_pulse_ts;
125
126 struct mt76x02_dfs_sw_detector_params sw_dpd_params;
127 struct mt76x02_dfs_event_rb event_rb[2];
128
129 struct list_head sequences;
130 struct list_head seq_pool;
131 struct mt76x02_dfs_seq_stats seq_stats;
132
133 unsigned long last_sw_check;
134 u32 last_event_ts;
135
136 struct mt76x02_dfs_engine_stats stats[MT_DFS_NUM_ENGINES];
137 struct tasklet_struct dfs_tasklet;
138};
139
140#endif /* __MT76x02_DFS_H */