projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mt76: mt7615: move mt7615_mac_get_key_info in mac.c
[linux-2.6-block.git] / drivers / net / wireless / mediatek / mt76 / mt7615 / mac.c
CommitLineData
04b8e659
RL		 1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
8 */
9
10#include <linux/etherdevice.h>
11#include <linux/timekeeping.h>
12#include "mt7615.h"
13#include "../dma.h"
14#include "mac.h"
15
bf92e768
RL		 16static inline s8 to_rssi(u32 field, u32 rxv)
17{
18 return (FIELD_GET(field, rxv) - 220) / 2;
19}
20
04b8e659
RL		 21static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
22 u8 idx, bool unicast)
23{
24 struct mt7615_sta *sta;
25 struct mt76_wcid *wcid;
26
27 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
28 return NULL;
29
30 wcid = rcu_dereference(dev->mt76.wcid[idx]);
31 if (unicast || !wcid)
32 return wcid;
33
34 if (!wcid->sta)
35 return NULL;
36
37 sta = container_of(wcid, struct mt7615_sta, wcid);
38 if (!sta->vif)
39 return NULL;
40
41 return &sta->vif->sta.wcid;
42}
43
04b8e659
RL		 44int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
45{
46 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
47 struct ieee80211_supported_band *sband;
48 struct ieee80211_hdr *hdr;
49 __le32 *rxd = (__le32 *)skb->data;
50 u32 rxd0 = le32_to_cpu(rxd[0]);
51 u32 rxd1 = le32_to_cpu(rxd[1]);
52 u32 rxd2 = le32_to_cpu(rxd[2]);
53 bool unicast, remove_pad, insert_ccmp_hdr = false;
54 int i, idx;
55
2dcb79cd
LB		 56 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state))
57 return -EINVAL;
58
04b8e659
RL		 59 memset(status, 0, sizeof(*status));
60
61 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
62 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
63 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
64
65 /* TODO: properly support DBDC */
66 status->freq = dev->mt76.chandef.chan->center_freq;
67 status->band = dev->mt76.chandef.chan->band;
68 if (status->band == NL80211_BAND_5GHZ)
69 sband = &dev->mt76.sband_5g.sband;
70 else
71 sband = &dev->mt76.sband_2g.sband;
72
73 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
74 status->flag |= RX_FLAG_FAILED_FCS_CRC;
75
76 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
77 status->flag |= RX_FLAG_MMIC_ERROR;
78
79 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
80 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
81 status->flag |= RX_FLAG_DECRYPTED;
82 status->flag |= RX_FLAG_IV_STRIPPED;
83 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
84 }
85
86 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
87
88 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
89 return -EINVAL;
90
91 if (!sband->channels)
92 return -EINVAL;
93
94 rxd += 4;
95 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
96 rxd += 4;
97 if ((u8 *)rxd - skb->data >= skb->len)
98 return -EINVAL;
99 }
100
101 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
102 u8 *data = (u8 *)rxd;
103
104 if (status->flag & RX_FLAG_DECRYPTED) {
105 status->iv[0] = data[5];
106 status->iv[1] = data[4];
107 status->iv[2] = data[3];
108 status->iv[3] = data[2];
109 status->iv[4] = data[1];
110 status->iv[5] = data[0];
111
112 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
113 }
114 rxd += 4;
115 if ((u8 *)rxd - skb->data >= skb->len)
116 return -EINVAL;
117 }
118
119 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
120 rxd += 2;
121 if ((u8 *)rxd - skb->data >= skb->len)
122 return -EINVAL;
123 }
124
125 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
126 u32 rxdg0 = le32_to_cpu(rxd[0]);
127 u32 rxdg1 = le32_to_cpu(rxd[1]);
bf92e768 128 u32 rxdg3 = le32_to_cpu(rxd[3]);
04b8e659
RL		 129 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
130 bool cck = false;
131
132 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
133 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
134 case MT_PHY_TYPE_CCK:
135 cck = true;
136 /* fall through */
137 case MT_PHY_TYPE_OFDM:
d2679d65 138 i = mt76_get_rate(&dev->mt76, sband, i, cck);
04b8e659
RL		 139 break;
140 case MT_PHY_TYPE_HT_GF:
141 case MT_PHY_TYPE_HT:
142 status->encoding = RX_ENC_HT;
143 if (i > 31)
144 return -EINVAL;
145 break;
146 case MT_PHY_TYPE_VHT:
147 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
148 status->encoding = RX_ENC_VHT;
149 break;
150 default:
151 return -EINVAL;
152 }
153 status->rate_idx = i;
154
155 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
156 case MT_PHY_BW_20:
157 break;
158 case MT_PHY_BW_40:
159 status->bw = RATE_INFO_BW_40;
160 break;
161 case MT_PHY_BW_80:
162 status->bw = RATE_INFO_BW_80;
163 break;
164 case MT_PHY_BW_160:
165 status->bw = RATE_INFO_BW_160;
166 break;
167 default:
168 return -EINVAL;
169 }
170
171 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
172 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
173 if (rxdg0 & MT_RXV1_HT_AD_CODE)
174 status->enc_flags |= RX_ENC_FLAG_LDPC;
175
176 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
177
bf92e768
RL		 178 status->chains = dev->mt76.antenna_mask;
179 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
180 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
181 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
182 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
183 status->signal = status->chain_signal[0];
184
185 for (i = 1; i < hweight8(dev->mt76.antenna_mask); i++) {
186 if (!(status->chains & BIT(i)))
187 continue;
188
189 status->signal = max(status->signal,
190 status->chain_signal[i]);
191 }
192
04b8e659
RL		 193 rxd += 6;
194 if ((u8 *)rxd - skb->data >= skb->len)
195 return -EINVAL;
196 }
197
198 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
199
200 if (insert_ccmp_hdr) {
201 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
202
eadfd98f 203 mt76_insert_ccmp_hdr(skb, key_id);
04b8e659
RL		 204 }
205
206 hdr = (struct ieee80211_hdr *)skb->data;
207 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
208 return 0;
209
210 status->aggr = unicast &&
211 !ieee80211_is_qos_nullfunc(hdr->frame_control);
212 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
e8027946 213 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
04b8e659
RL		 214
215 return 0;
216}
217
218void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
219{
220}
221
222void mt7615_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
223 struct mt76_queue_entry *e)
224{
225 if (!e->txwi) {
226 dev_kfree_skb_any(e->skb);
227 return;
228 }
229
230 /* error path */
231 if (e->skb == DMA_DUMMY_DATA) {
232 struct mt76_txwi_cache *t;
233 struct mt7615_dev *dev;
234 struct mt7615_txp *txp;
235 u8 *txwi_ptr;
236
237 txwi_ptr = mt76_get_txwi_ptr(mdev, e->txwi);
238 txp = (struct mt7615_txp *)(txwi_ptr + MT_TXD_SIZE);
239 dev = container_of(mdev, struct mt7615_dev, mt76);
240
241 spin_lock_bh(&dev->token_lock);
242 t = idr_remove(&dev->token, le16_to_cpu(txp->token));
243 spin_unlock_bh(&dev->token_lock);
244 e->skb = t ? t->skb : NULL;
245 }
246
247 if (e->skb)
248 mt76_tx_complete_skb(mdev, e->skb);
249}
250
592ed85d
FF		 251static u16
252mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
253 const struct ieee80211_tx_rate *rate,
254 bool stbc, u8 *bw)
04b8e659
RL		 255{
256 u8 phy, nss, rate_idx;
3eb514dd 257 u16 rateval = 0;
04b8e659
RL		 258
259 *bw = 0;
260
261 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
262 rate_idx = ieee80211_rate_get_vht_mcs(rate);
263 nss = ieee80211_rate_get_vht_nss(rate);
264 phy = MT_PHY_TYPE_VHT;
265 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
266 *bw = 1;
267 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
268 *bw = 2;
269 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
270 *bw = 3;
271 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
272 rate_idx = rate->idx;
273 nss = 1 + (rate->idx >> 3);
274 phy = MT_PHY_TYPE_HT;
275 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
276 phy = MT_PHY_TYPE_HT_GF;
277 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
278 *bw = 1;
279 } else {
280 const struct ieee80211_rate *r;
281 int band = dev->mt76.chandef.chan->band;
282 u16 val;
283
284 nss = 1;
285 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
286 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
287 val = r->hw_value_short;
288 else
289 val = r->hw_value;
290
291 phy = val >> 8;
292 rate_idx = val & 0xff;
293 }
294
3eb514dd
FF		 295 if (stbc && nss == 1) {
296 nss++;
04b8e659 297 rateval |= MT_TX_RATE_STBC;
3eb514dd
FF		 298 }
299
300 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
301 FIELD_PREP(MT_TX_RATE_MODE, phy) |
302 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
04b8e659
RL		 303
304 return rateval;
305}
306
307int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
308 struct sk_buff *skb, struct mt76_wcid *wcid,
309 struct ieee80211_sta *sta, int pid,
310 struct ieee80211_key_conf *key)
311{
312 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
313 struct ieee80211_tx_rate *rate = &info->control.rates[0];
314 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
315 struct ieee80211_vif *vif = info->control.vif;
316 int tx_count = 8;
317 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0;
e8027946 318 __le16 fc = hdr->frame_control;
04b8e659
RL		 319 u16 seqno = 0;
320 u32 val;
321
322 if (vif) {
323 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
324
325 omac_idx = mvif->omac_idx;
326 }
327
328 if (sta) {
329 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
330
331 tx_count = msta->rate_count;
332 }
333
e8027946
RL		 334 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
335 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
04b8e659 336
1f5581df 337 if (ieee80211_is_data(fc) || ieee80211_is_bufferable_mmpdu(fc)) {
04b8e659
RL		 338 q_idx = skb_get_queue_mapping(skb);
339 p_fmt = MT_TX_TYPE_CT;
340 } else if (ieee80211_is_beacon(fc)) {
341 q_idx = MT_LMAC_BCN0;
342 p_fmt = MT_TX_TYPE_FW;
343 } else {
344 q_idx = MT_LMAC_ALTX0;
345 p_fmt = MT_TX_TYPE_CT;
346 }
347
348 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
349 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
350 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
351 txwi[0] = cpu_to_le32(val);
352
353 val = MT_TXD1_LONG_FORMAT |
354 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
355 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
356 FIELD_PREP(MT_TXD1_HDR_INFO,
357 ieee80211_get_hdrlen_from_skb(skb) / 2) |
358 FIELD_PREP(MT_TXD1_TID,
359 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
360 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
361 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
362 txwi[1] = cpu_to_le32(val);
363
364 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
365 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
366 FIELD_PREP(MT_TXD2_MULTICAST,
367 is_multicast_ether_addr(hdr->addr1));
368 txwi[2] = cpu_to_le32(val);
369
370 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
371 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
372
373 txwi[4] = 0;
374 txwi[6] = 0;
375
376 if (rate->idx >= 0 && rate->count &&
377 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
378 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
379 u8 bw;
380 u16 rateval = mt7615_mac_tx_rate_val(dev, rate, stbc, &bw);
381
382 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
383
384 val = MT_TXD6_FIXED_BW |
385 FIELD_PREP(MT_TXD6_BW, bw) |
386 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
387 txwi[6] |= cpu_to_le32(val);
388
389 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
390 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
391
392 if (info->flags & IEEE80211_TX_CTL_LDPC)
393 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
394
395 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
396 IEEE80211_TX_RC_VHT_MCS)))
397 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
398
399 tx_count = rate->count;
400 }
401
402 if (!ieee80211_is_beacon(fc)) {
403 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
404 FIELD_PREP(MT_TXD5_PID, pid);
405 txwi[5] = cpu_to_le32(val);
406 } else {
407 txwi[5] = 0;
408 /* use maximum tx count for beacons */
409 tx_count = 0x1f;
410 }
411
412 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
413 if (ieee80211_is_data_qos(hdr->frame_control)) {
414 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
415 val |= MT_TXD3_SN_VALID;
416 } else if (ieee80211_is_back_req(hdr->frame_control)) {
417 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
418
419 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
420 val |= MT_TXD3_SN_VALID;
421 }
422 val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
423
424 txwi[3] = cpu_to_le32(val);
425
426 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
427 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
428
429 if (key)
430 txwi[3] |= cpu_to_le32(MT_TXD3_PROTECT_FRAME);
431
432 txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
433 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
434
435 return 0;
436}
437
438void mt7615_txp_skb_unmap(struct mt76_dev *dev,
439 struct mt76_txwi_cache *t)
440{
441 struct mt7615_txp *txp;
442 u8 *txwi;
443 int i;
444
445 txwi = mt76_get_txwi_ptr(dev, t);
446 txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
447 for (i = 1; i < txp->nbuf; i++)
448 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
e8027946 449 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
04b8e659
RL		 450}
451
592ed85d
FF		 452void mt7615_mac_set_rates(struct mt7615_dev *dev, struct mt7615_sta *sta,
453 struct ieee80211_tx_rate *probe_rate,
454 struct ieee80211_tx_rate *rates)
455{
4af81f02 456 struct ieee80211_tx_rate *ref;
592ed85d
FF		 457 int wcid = sta->wcid.idx;
458 u32 addr = MT_WTBL_BASE + wcid * MT_WTBL_ENTRY_SIZE;
459 bool stbc = false;
460 int n_rates = sta->n_rates;
461 u8 bw, bw_prev, bw_idx = 0;
462 u16 val[4];
463 u16 probe_val;
464 u32 w5, w27;
4af81f02
FF		 465 bool rateset;
466 int i, k;
592ed85d
FF		 467
468 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
469 return;
470
471 for (i = n_rates; i < 4; i++)
472 rates[i] = rates[n_rates - 1];
473
4af81f02
FF		 474 rateset = !(sta->rate_set_tsf & BIT(0));
475 memcpy(sta->rateset[rateset].rates, rates,
476 sizeof(sta->rateset[rateset].rates));
477 if (probe_rate) {
478 sta->rateset[rateset].probe_rate = *probe_rate;
479 ref = &sta->rateset[rateset].probe_rate;
480 } else {
481 sta->rateset[rateset].probe_rate.idx = -1;
482 ref = &sta->rateset[rateset].rates[0];
483 }
484
485 rates = sta->rateset[rateset].rates;
486 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
487 /*
488 * We don't support switching between short and long GI
489 * within the rate set. For accurate tx status reporting, we
490 * need to make sure that flags match.
491 * For improved performance, avoid duplicate entries by
492 * decrementing the MCS index if necessary
493 */
494 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
495 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
496
497 for (k = 0; k < i; k++) {
498 if (rates[i].idx != rates[k].idx)
499 continue;
500 if ((rates[i].flags ^ rates[k].flags) &
501 (IEEE80211_TX_RC_40_MHZ_WIDTH |
502 IEEE80211_TX_RC_80_MHZ_WIDTH |
503 IEEE80211_TX_RC_160_MHZ_WIDTH))
504 continue;
505
f4635f66
FF		 506 if (!rates[i].idx)
507 continue;
508
4af81f02
FF		 509 rates[i].idx--;
510 }
511
512 }
513
592ed85d
FF		 514 val[0] = mt7615_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
515 bw_prev = bw;
516
517 if (probe_rate) {
518 probe_val = mt7615_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
519 if (bw)
520 bw_idx = 1;
521 else
522 bw_prev = 0;
523 } else {
524 probe_val = val[0];
525 }
526
527 val[1] = mt7615_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
528 if (bw_prev) {
529 bw_idx = 3;
530 bw_prev = bw;
531 }
532
533 val[2] = mt7615_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
534 if (bw_prev) {
535 bw_idx = 5;
536 bw_prev = bw;
537 }
538
539 val[3] = mt7615_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
540 if (bw_prev)
541 bw_idx = 7;
542
543 w27 = mt76_rr(dev, addr + 27 * 4);
544 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
545 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, bw);
546
547 w5 = mt76_rr(dev, addr + 5 * 4);
5f3413fc
FF		 548 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
549 MT_WTBL_W5_MPDU_OK_COUNT |
550 MT_WTBL_W5_MPDU_FAIL_COUNT |
551 MT_WTBL_W5_RATE_IDX);
592ed85d
FF		 552 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, bw) |
553 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, bw_idx ? bw_idx - 1 : 7);
554
555 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
556
557 mt76_wr(dev, MT_WTBL_RIUCR1,
558 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
559 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
4af81f02 560 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
592ed85d
FF		 561
562 mt76_wr(dev, MT_WTBL_RIUCR2,
4af81f02 563 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
592ed85d 564 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
4af81f02 565 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
592ed85d
FF		 566 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
567
568 mt76_wr(dev, MT_WTBL_RIUCR3,
569 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
4af81f02 570 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
592ed85d
FF		 571 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
572
573 mt76_wr(dev, MT_WTBL_UPDATE,
574 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
575 MT_WTBL_UPDATE_RATE_UPDATE |
576 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
577
578 mt76_wr(dev, addr + 27 * 4, w27);
579
4af81f02
FF		 580 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
581 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;
582
592ed85d
FF		 583 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
584 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
585
586 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
587 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
588}
92671eb9
LB		 589
590enum mt7615_cipher_type
591mt7615_mac_get_key_info(struct ieee80211_key_conf *key,
592 u8 *key_data)
593{
594 if (!key || key->keylen > 32)
595 return MT_CIPHER_NONE;
596
597 memcpy(key_data, key->key, key->keylen);
598
599 switch (key->cipher) {
600 case WLAN_CIPHER_SUITE_WEP40:
601 return MT_CIPHER_WEP40;
602 case WLAN_CIPHER_SUITE_WEP104:
603 return MT_CIPHER_WEP104;
604 case WLAN_CIPHER_SUITE_TKIP:
605 /* Rx/Tx MIC keys are swapped */
606 memcpy(key_data + 16, key->key + 24, 8);
607 memcpy(key_data + 24, key->key + 16, 8);
608 return MT_CIPHER_TKIP;
609 case WLAN_CIPHER_SUITE_CCMP:
610 return MT_CIPHER_AES_CCMP;
611 case WLAN_CIPHER_SUITE_CCMP_256:
612 return MT_CIPHER_CCMP_256;
613 case WLAN_CIPHER_SUITE_GCMP:
614 return MT_CIPHER_GCMP;
615 case WLAN_CIPHER_SUITE_GCMP_256:
616 return MT_CIPHER_GCMP_256;
617 case WLAN_CIPHER_SUITE_SMS4:
618 return MT_CIPHER_WAPI;
619 default:
620 return MT_CIPHER_NONE;
621 }
622}
623
04b8e659
RL		 624int mt7615_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
625 enum mt76_txq_id qid, struct mt76_wcid *wcid,
626 struct ieee80211_sta *sta,
627 struct mt76_tx_info *tx_info)
628{
629 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
630 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
631 struct mt7615_sta *msta = container_of(wcid, struct mt7615_sta, wcid);
632 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
633 struct ieee80211_key_conf *key = info->control.hw_key;
634 struct ieee80211_vif *vif = info->control.vif;
635 int i, pid, id, nbuf = tx_info->nbuf - 1;
636 u8 *txwi = (u8 *)txwi_ptr;
637 struct mt76_txwi_cache *t;
638 struct mt7615_txp *txp;
639
640 if (!wcid)
641 wcid = &dev->mt76.global_wcid;
642
643 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
644
645 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
646 spin_lock_bh(&dev->mt76.lock);
592ed85d 647 mt7615_mac_set_rates(dev, msta, &info->control.rates[0],
04b8e659 648 msta->rates);
4af81f02 649 msta->rate_probe = true;
04b8e659
RL		 650 spin_unlock_bh(&dev->mt76.lock);
651 }
652
653 mt7615_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, sta,
654 pid, key);
655
656 txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
657 for (i = 0; i < nbuf; i++) {
658 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
e8027946 659 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
04b8e659
RL		 660 }
661 txp->nbuf = nbuf;
662
663 /* pass partial skb header to fw */
664 tx_info->buf[1].len = MT_CT_PARSE_LEN;
665 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
666
667 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
668
669 if (!key)
670 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
671
672 if (ieee80211_is_mgmt(hdr->frame_control))
673 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
674
675 if (vif) {
676 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
677
678 txp->bss_idx = mvif->idx;
679 }
680
681 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
682 t->skb = tx_info->skb;
683
684 spin_lock_bh(&dev->token_lock);
685 id = idr_alloc(&dev->token, t, 0, MT7615_TOKEN_SIZE, GFP_ATOMIC);
686 spin_unlock_bh(&dev->token_lock);
687 if (id < 0)
688 return id;
689
690 txp->token = cpu_to_le16(id);
691 txp->rept_wds_wcid = 0xff;
692 tx_info->skb = DMA_DUMMY_DATA;
693
694 return 0;
695}
696
697static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
698 struct ieee80211_tx_info *info, __le32 *txs_data)
699{
700 struct ieee80211_supported_band *sband;
4af81f02
FF		 701 struct mt7615_rate_set *rs;
702 int first_idx = 0, last_idx;
703 int i, idx, count;
d3edd108 704 bool fixed_rate, ack_timeout;
04b8e659 705 bool probe, ampdu, cck = false;
4af81f02
FF		 706 bool rs_idx;
707 u32 rate_set_tsf;
04b8e659 708 u32 final_rate, final_rate_flags, final_nss, txs;
04b8e659
RL		 709
710 fixed_rate = info->status.rates[0].count;
711 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
712
713 txs = le32_to_cpu(txs_data[1]);
04b8e659
RL		 714 ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU);
715
716 txs = le32_to_cpu(txs_data[3]);
717 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
4af81f02 718 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
04b8e659
RL		 719
720 txs = le32_to_cpu(txs_data[0]);
04b8e659
RL		 721 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
722 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
723
724 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
725 return false;
726
727 if (txs & MT_TXS0_QUEUE_TIMEOUT)
728 return false;
729
730 if (!ack_timeout)
731 info->flags |= IEEE80211_TX_STAT_ACK;
732
733 info->status.ampdu_len = 1;
734 info->status.ampdu_ack_len = !!(info->flags &
735 IEEE80211_TX_STAT_ACK);
736
737 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
738 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
739
4af81f02
FF		 740 first_idx = max_t(int, 0, last_idx - (count + 1) / MT7615_RATE_RETRY);
741
04b8e659
RL		 742 if (fixed_rate && !probe) {
743 info->status.rates[0].count = count;
4af81f02 744 i = 0;
04b8e659
RL		 745 goto out;
746 }
747
4af81f02
FF		 748 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
749 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
750 rate_set_tsf) < 1000000);
751 rs_idx ^= rate_set_tsf & BIT(0);
752 rs = &sta->rateset[rs_idx];
04b8e659 753
4af81f02
FF		 754 if (!first_idx && rs->probe_rate.idx >= 0) {
755 info->status.rates[0] = rs->probe_rate;
04b8e659 756
4af81f02
FF		 757 spin_lock_bh(&dev->mt76.lock);
758 if (sta->rate_probe) {
759 mt7615_mac_set_rates(dev, sta, NULL, sta->rates);
760 sta->rate_probe = false;
04b8e659 761 }
4af81f02
FF		 762 spin_unlock_bh(&dev->mt76.lock);
763 } else
764 info->status.rates[0] = rs->rates[first_idx / 2];
765 info->status.rates[0].count = 0;
04b8e659 766
4af81f02
FF		 767 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
768 struct ieee80211_tx_rate *cur_rate;
769 int cur_count;
04b8e659 770
4af81f02
FF		 771 cur_rate = &rs->rates[idx / 2];
772 cur_count = min_t(int, MT7615_RATE_RETRY, count);
04b8e659 773 count -= cur_count;
4af81f02
FF		 774
775 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
776 cur_rate->flags != info->status.rates[i].flags)) {
777 i++;
778 if (i == ARRAY_SIZE(info->status.rates))
779 break;
780
781 info->status.rates[i] = *cur_rate;
782 info->status.rates[i].count = 0;
783 }
784
785 info->status.rates[i].count += cur_count;
04b8e659
RL		 786 }
787
788out:
4af81f02 789 final_rate_flags = info->status.rates[i].flags;
04b8e659
RL		 790
791 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
792 case MT_PHY_TYPE_CCK:
793 cck = true;
794 /* fall through */
795 case MT_PHY_TYPE_OFDM:
796 if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ)
797 sband = &dev->mt76.sband_5g.sband;
798 else
799 sband = &dev->mt76.sband_2g.sband;
800 final_rate &= MT_TX_RATE_IDX;
d2679d65
LB		 801 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
802 cck);
04b8e659
RL		 803 final_rate_flags = 0;
804 break;
805 case MT_PHY_TYPE_HT_GF:
806 case MT_PHY_TYPE_HT:
807 final_rate_flags |= IEEE80211_TX_RC_MCS;
808 final_rate &= MT_TX_RATE_IDX;
809 if (final_rate > 31)
810 return false;
811 break;
812 case MT_PHY_TYPE_VHT:
813 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
3eb514dd
FF		 814
815 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
816 final_nss--;
817
04b8e659
RL		 818 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
819 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
820 break;
821 default:
822 return false;
823 }
824
4af81f02
FF		 825 info->status.rates[i].idx = final_rate;
826 info->status.rates[i].flags = final_rate_flags;
04b8e659
RL		 827
828 return true;
829}
830
831static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
832 struct mt7615_sta *sta, int pid,
833 __le32 *txs_data)
834{
835 struct mt76_dev *mdev = &dev->mt76;
836 struct sk_buff_head list;
837 struct sk_buff *skb;
838
839 if (pid < MT_PACKET_ID_FIRST)
840 return false;
841
842 mt76_tx_status_lock(mdev, &list);
843 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
844 if (skb) {
845 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
846
04b8e659
RL		 847 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
848 ieee80211_tx_info_clear_status(info);
849 info->status.rates[0].idx = -1;
850 }
851
852 mt76_tx_status_skb_done(mdev, skb, &list);
853 }
854 mt76_tx_status_unlock(mdev, &list);
855
856 return !!skb;
857}
858
859void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
860{
861 struct ieee80211_tx_info info = {};
862 struct ieee80211_sta *sta = NULL;
863 struct mt7615_sta *msta = NULL;
864 struct mt76_wcid *wcid;
865 __le32 *txs_data = data;
866 u32 txs;
867 u8 wcidx;
868 u8 pid;
869
870 txs = le32_to_cpu(txs_data[0]);
871 pid = FIELD_GET(MT_TXS0_PID, txs);
872 txs = le32_to_cpu(txs_data[2]);
873 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
874
875 if (pid == MT_PACKET_ID_NO_ACK)
876 return;
877
878 if (wcidx >= ARRAY_SIZE(dev->mt76.wcid))
879 return;
880
881 rcu_read_lock();
882
883 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
884 if (!wcid)
885 goto out;
886
887 msta = container_of(wcid, struct mt7615_sta, wcid);
888 sta = wcid_to_sta(wcid);
889
890 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
891 goto out;
892
893 if (wcidx >= MT7615_WTBL_STA || !sta)
894 goto out;
895
896 if (mt7615_fill_txs(dev, msta, &info, txs_data))
897 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
898
899out:
900 rcu_read_unlock();
901}
902
903void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
904{
905 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
906 struct mt76_dev *mdev = &dev->mt76;
907 struct mt76_txwi_cache *txwi;
908 u8 i, count;
909
910 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
911 for (i = 0; i < count; i++) {
912 spin_lock_bh(&dev->token_lock);
913 txwi = idr_remove(&dev->token, le16_to_cpu(free->token[i]));
914 spin_unlock_bh(&dev->token_lock);
915
916 if (!txwi)
917 continue;
918
919 mt7615_txp_skb_unmap(mdev, txwi);
920 if (txwi->skb) {
921 mt76_tx_complete_skb(mdev, txwi->skb);
922 txwi->skb = NULL;
923 }
924
925 mt76_put_txwi(mdev, txwi);
926 }
927 dev_kfree_skb(skb);
928}
929
930void mt7615_mac_work(struct work_struct *work)
931{
932 struct mt7615_dev *dev;
933
934 dev = (struct mt7615_dev *)container_of(work, struct mt76_dev,
935 mac_work.work);
936
937 mt76_tx_status_check(&dev->mt76, NULL, false);
938 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work,
939 MT7615_WATCHDOG_TIME);
940}
d67a6646
LB		 941
942int mt7615_dfs_stop_radar_detector(struct mt7615_dev *dev)
943{
944 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
945 int err;
946
947 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD0,
948 MT_RX_SEL0, 0);
949 if (err < 0)
950 return err;
951
952 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
953 chandef->width == NL80211_CHAN_WIDTH_80P80)
954 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD1,
955 MT_RX_SEL0, 0);
956 return err;
957}
958
959static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
960{
961 int err;
962
963 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
964 if (err < 0)
965 return err;
966
967 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
968 MT_RX_SEL0, 1);
969}
970
971int mt7615_dfs_start_radar_detector(struct mt7615_dev *dev)
972{
973 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
974 int err;
975
976 /* start CAC */
977 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, MT_HW_RDD0,
978 MT_RX_SEL0, 0);
979 if (err < 0)
980 return err;
981
982 /* TODO: DBDC support */
983
984 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD0);
985 if (err < 0)
986 return err;
987
988 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
989 chandef->width == NL80211_CHAN_WIDTH_80P80) {
990 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD1);
991 if (err < 0)
992 return err;
993 }
994
995 return 0;
996}
997
998int mt7615_dfs_init_radar_detector(struct mt7615_dev *dev)
999{
1000 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
1001 int err;
1002
1003 if (dev->mt76.region == NL80211_DFS_UNSET)
1004 return 0;
1005
1006 if (test_bit(MT76_SCANNING, &dev->mt76.state))
1007 return 0;
1008
1009 if (dev->dfs_state == chandef->chan->dfs_state)
1010 return 0;
1011
1012 dev->dfs_state = chandef->chan->dfs_state;
1013
1014 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
1015 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
1016 return mt7615_dfs_start_radar_detector(dev);
1017 else
1018 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, MT_HW_RDD0,
1019 MT_RX_SEL0, 0);
1020 } else {
1021 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START,
1022 MT_HW_RDD0, MT_RX_SEL0, 0);
1023 if (err < 0)
1024 return err;
1025
1026 return mt7615_dfs_stop_radar_detector(dev);
1027 }
1028}
Linux 6.x block layer and io_uring tree(s)