projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mt76: mt7615: move mt7615_mcu_set_rates to mac.c
[linux-2.6-block.git] / drivers / net / wireless / mediatek / mt76 / mt7615 / mac.c
CommitLineData
04b8e659
RL		 1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
8 */
9
10#include <linux/etherdevice.h>
11#include <linux/timekeeping.h>
12#include "mt7615.h"
13#include "../dma.h"
14#include "mac.h"
15
bf92e768
RL		 16static inline s8 to_rssi(u32 field, u32 rxv)
17{
18 return (FIELD_GET(field, rxv) - 220) / 2;
19}
20
04b8e659
RL		 21static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
22 u8 idx, bool unicast)
23{
24 struct mt7615_sta *sta;
25 struct mt76_wcid *wcid;
26
27 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
28 return NULL;
29
30 wcid = rcu_dereference(dev->mt76.wcid[idx]);
31 if (unicast || !wcid)
32 return wcid;
33
34 if (!wcid->sta)
35 return NULL;
36
37 sta = container_of(wcid, struct mt7615_sta, wcid);
38 if (!sta->vif)
39 return NULL;
40
41 return &sta->vif->sta.wcid;
42}
43
04b8e659
RL		 44int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
45{
46 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
47 struct ieee80211_supported_band *sband;
48 struct ieee80211_hdr *hdr;
49 __le32 *rxd = (__le32 *)skb->data;
50 u32 rxd0 = le32_to_cpu(rxd[0]);
51 u32 rxd1 = le32_to_cpu(rxd[1]);
52 u32 rxd2 = le32_to_cpu(rxd[2]);
53 bool unicast, remove_pad, insert_ccmp_hdr = false;
54 int i, idx;
55
2dcb79cd
LB		 56 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state))
57 return -EINVAL;
58
04b8e659
RL		 59 memset(status, 0, sizeof(*status));
60
61 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
62 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
63 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
64
65 /* TODO: properly support DBDC */
66 status->freq = dev->mt76.chandef.chan->center_freq;
67 status->band = dev->mt76.chandef.chan->band;
68 if (status->band == NL80211_BAND_5GHZ)
69 sband = &dev->mt76.sband_5g.sband;
70 else
71 sband = &dev->mt76.sband_2g.sband;
72
73 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
74 status->flag |= RX_FLAG_FAILED_FCS_CRC;
75
76 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
77 status->flag |= RX_FLAG_MMIC_ERROR;
78
79 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
80 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
81 status->flag |= RX_FLAG_DECRYPTED;
82 status->flag |= RX_FLAG_IV_STRIPPED;
83 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
84 }
85
86 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
87
88 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
89 return -EINVAL;
90
91 if (!sband->channels)
92 return -EINVAL;
93
94 rxd += 4;
95 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
96 rxd += 4;
97 if ((u8 *)rxd - skb->data >= skb->len)
98 return -EINVAL;
99 }
100
101 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
102 u8 *data = (u8 *)rxd;
103
104 if (status->flag & RX_FLAG_DECRYPTED) {
105 status->iv[0] = data[5];
106 status->iv[1] = data[4];
107 status->iv[2] = data[3];
108 status->iv[3] = data[2];
109 status->iv[4] = data[1];
110 status->iv[5] = data[0];
111
112 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
113 }
114 rxd += 4;
115 if ((u8 *)rxd - skb->data >= skb->len)
116 return -EINVAL;
117 }
118
119 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
120 rxd += 2;
121 if ((u8 *)rxd - skb->data >= skb->len)
122 return -EINVAL;
123 }
124
125 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
126 u32 rxdg0 = le32_to_cpu(rxd[0]);
127 u32 rxdg1 = le32_to_cpu(rxd[1]);
bf92e768 128 u32 rxdg3 = le32_to_cpu(rxd[3]);
04b8e659
RL		 129 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
130 bool cck = false;
131
132 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
133 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
134 case MT_PHY_TYPE_CCK:
135 cck = true;
136 /* fall through */
137 case MT_PHY_TYPE_OFDM:
d2679d65 138 i = mt76_get_rate(&dev->mt76, sband, i, cck);
04b8e659
RL		 139 break;
140 case MT_PHY_TYPE_HT_GF:
141 case MT_PHY_TYPE_HT:
142 status->encoding = RX_ENC_HT;
143 if (i > 31)
144 return -EINVAL;
145 break;
146 case MT_PHY_TYPE_VHT:
147 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
148 status->encoding = RX_ENC_VHT;
149 break;
150 default:
151 return -EINVAL;
152 }
153 status->rate_idx = i;
154
155 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
156 case MT_PHY_BW_20:
157 break;
158 case MT_PHY_BW_40:
159 status->bw = RATE_INFO_BW_40;
160 break;
161 case MT_PHY_BW_80:
162 status->bw = RATE_INFO_BW_80;
163 break;
164 case MT_PHY_BW_160:
165 status->bw = RATE_INFO_BW_160;
166 break;
167 default:
168 return -EINVAL;
169 }
170
171 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
172 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
173 if (rxdg0 & MT_RXV1_HT_AD_CODE)
174 status->enc_flags |= RX_ENC_FLAG_LDPC;
175
176 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
177
bf92e768
RL		 178 status->chains = dev->mt76.antenna_mask;
179 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
180 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
181 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
182 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
183 status->signal = status->chain_signal[0];
184
185 for (i = 1; i < hweight8(dev->mt76.antenna_mask); i++) {
186 if (!(status->chains & BIT(i)))
187 continue;
188
189 status->signal = max(status->signal,
190 status->chain_signal[i]);
191 }
192
04b8e659
RL		 193 rxd += 6;
194 if ((u8 *)rxd - skb->data >= skb->len)
195 return -EINVAL;
196 }
197
198 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
199
200 if (insert_ccmp_hdr) {
201 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
202
eadfd98f 203 mt76_insert_ccmp_hdr(skb, key_id);
04b8e659
RL		 204 }
205
206 hdr = (struct ieee80211_hdr *)skb->data;
207 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
208 return 0;
209
210 status->aggr = unicast &&
211 !ieee80211_is_qos_nullfunc(hdr->frame_control);
212 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
e8027946 213 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
04b8e659
RL		 214
215 return 0;
216}
217
218void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
219{
220}
221
222void mt7615_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
223 struct mt76_queue_entry *e)
224{
225 if (!e->txwi) {
226 dev_kfree_skb_any(e->skb);
227 return;
228 }
229
230 /* error path */
231 if (e->skb == DMA_DUMMY_DATA) {
232 struct mt76_txwi_cache *t;
233 struct mt7615_dev *dev;
234 struct mt7615_txp *txp;
235 u8 *txwi_ptr;
236
237 txwi_ptr = mt76_get_txwi_ptr(mdev, e->txwi);
238 txp = (struct mt7615_txp *)(txwi_ptr + MT_TXD_SIZE);
239 dev = container_of(mdev, struct mt7615_dev, mt76);
240
241 spin_lock_bh(&dev->token_lock);
242 t = idr_remove(&dev->token, le16_to_cpu(txp->token));
243 spin_unlock_bh(&dev->token_lock);
244 e->skb = t ? t->skb : NULL;
245 }
246
247 if (e->skb)
248 mt76_tx_complete_skb(mdev, e->skb);
249}
250
592ed85d
FF		 251static u16
252mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
253 const struct ieee80211_tx_rate *rate,
254 bool stbc, u8 *bw)
04b8e659
RL		 255{
256 u8 phy, nss, rate_idx;
257 u16 rateval;
258
259 *bw = 0;
260
261 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
262 rate_idx = ieee80211_rate_get_vht_mcs(rate);
263 nss = ieee80211_rate_get_vht_nss(rate);
264 phy = MT_PHY_TYPE_VHT;
265 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
266 *bw = 1;
267 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
268 *bw = 2;
269 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
270 *bw = 3;
271 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
272 rate_idx = rate->idx;
273 nss = 1 + (rate->idx >> 3);
274 phy = MT_PHY_TYPE_HT;
275 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
276 phy = MT_PHY_TYPE_HT_GF;
277 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
278 *bw = 1;
279 } else {
280 const struct ieee80211_rate *r;
281 int band = dev->mt76.chandef.chan->band;
282 u16 val;
283
284 nss = 1;
285 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
286 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
287 val = r->hw_value_short;
288 else
289 val = r->hw_value;
290
291 phy = val >> 8;
292 rate_idx = val & 0xff;
293 }
294
295 rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
296 FIELD_PREP(MT_TX_RATE_MODE, phy) |
297 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
298
299 if (stbc && nss == 1)
300 rateval |= MT_TX_RATE_STBC;
301
302 return rateval;
303}
304
305int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
306 struct sk_buff *skb, struct mt76_wcid *wcid,
307 struct ieee80211_sta *sta, int pid,
308 struct ieee80211_key_conf *key)
309{
310 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
311 struct ieee80211_tx_rate *rate = &info->control.rates[0];
312 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
313 struct ieee80211_vif *vif = info->control.vif;
314 int tx_count = 8;
315 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0;
e8027946 316 __le16 fc = hdr->frame_control;
04b8e659
RL		 317 u16 seqno = 0;
318 u32 val;
319
320 if (vif) {
321 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
322
323 omac_idx = mvif->omac_idx;
324 }
325
326 if (sta) {
327 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
328
329 tx_count = msta->rate_count;
330 }
331
e8027946
RL		 332 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
333 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
04b8e659
RL		 334
335 if (ieee80211_is_data(fc)) {
336 q_idx = skb_get_queue_mapping(skb);
337 p_fmt = MT_TX_TYPE_CT;
338 } else if (ieee80211_is_beacon(fc)) {
339 q_idx = MT_LMAC_BCN0;
340 p_fmt = MT_TX_TYPE_FW;
341 } else {
342 q_idx = MT_LMAC_ALTX0;
343 p_fmt = MT_TX_TYPE_CT;
344 }
345
346 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
347 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
348 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
349 txwi[0] = cpu_to_le32(val);
350
351 val = MT_TXD1_LONG_FORMAT |
352 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
353 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
354 FIELD_PREP(MT_TXD1_HDR_INFO,
355 ieee80211_get_hdrlen_from_skb(skb) / 2) |
356 FIELD_PREP(MT_TXD1_TID,
357 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
358 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
359 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
360 txwi[1] = cpu_to_le32(val);
361
362 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
363 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
364 FIELD_PREP(MT_TXD2_MULTICAST,
365 is_multicast_ether_addr(hdr->addr1));
366 txwi[2] = cpu_to_le32(val);
367
368 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
369 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
370
371 txwi[4] = 0;
372 txwi[6] = 0;
373
374 if (rate->idx >= 0 && rate->count &&
375 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
376 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
377 u8 bw;
378 u16 rateval = mt7615_mac_tx_rate_val(dev, rate, stbc, &bw);
379
380 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
381
382 val = MT_TXD6_FIXED_BW |
383 FIELD_PREP(MT_TXD6_BW, bw) |
384 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
385 txwi[6] |= cpu_to_le32(val);
386
387 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
388 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
389
390 if (info->flags & IEEE80211_TX_CTL_LDPC)
391 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
392
393 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
394 IEEE80211_TX_RC_VHT_MCS)))
395 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
396
397 tx_count = rate->count;
398 }
399
400 if (!ieee80211_is_beacon(fc)) {
401 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
402 FIELD_PREP(MT_TXD5_PID, pid);
403 txwi[5] = cpu_to_le32(val);
404 } else {
405 txwi[5] = 0;
406 /* use maximum tx count for beacons */
407 tx_count = 0x1f;
408 }
409
410 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
411 if (ieee80211_is_data_qos(hdr->frame_control)) {
412 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
413 val |= MT_TXD3_SN_VALID;
414 } else if (ieee80211_is_back_req(hdr->frame_control)) {
415 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
416
417 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
418 val |= MT_TXD3_SN_VALID;
419 }
420 val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
421
422 txwi[3] = cpu_to_le32(val);
423
424 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
425 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
426
427 if (key)
428 txwi[3] |= cpu_to_le32(MT_TXD3_PROTECT_FRAME);
429
430 txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
431 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
432
433 return 0;
434}
435
436void mt7615_txp_skb_unmap(struct mt76_dev *dev,
437 struct mt76_txwi_cache *t)
438{
439 struct mt7615_txp *txp;
440 u8 *txwi;
441 int i;
442
443 txwi = mt76_get_txwi_ptr(dev, t);
444 txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
445 for (i = 1; i < txp->nbuf; i++)
446 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
e8027946 447 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
04b8e659
RL		 448}
449
592ed85d
FF		 450void mt7615_mac_set_rates(struct mt7615_dev *dev, struct mt7615_sta *sta,
451 struct ieee80211_tx_rate *probe_rate,
452 struct ieee80211_tx_rate *rates)
453{
454 int wcid = sta->wcid.idx;
455 u32 addr = MT_WTBL_BASE + wcid * MT_WTBL_ENTRY_SIZE;
456 bool stbc = false;
457 int n_rates = sta->n_rates;
458 u8 bw, bw_prev, bw_idx = 0;
459 u16 val[4];
460 u16 probe_val;
461 u32 w5, w27;
462 int i;
463
464 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
465 return;
466
467 for (i = n_rates; i < 4; i++)
468 rates[i] = rates[n_rates - 1];
469
470 val[0] = mt7615_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
471 bw_prev = bw;
472
473 if (probe_rate) {
474 probe_val = mt7615_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
475 if (bw)
476 bw_idx = 1;
477 else
478 bw_prev = 0;
479 } else {
480 probe_val = val[0];
481 }
482
483 val[1] = mt7615_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
484 if (bw_prev) {
485 bw_idx = 3;
486 bw_prev = bw;
487 }
488
489 val[2] = mt7615_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
490 if (bw_prev) {
491 bw_idx = 5;
492 bw_prev = bw;
493 }
494
495 val[3] = mt7615_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
496 if (bw_prev)
497 bw_idx = 7;
498
499 w27 = mt76_rr(dev, addr + 27 * 4);
500 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
501 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, bw);
502
503 w5 = mt76_rr(dev, addr + 5 * 4);
504 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE);
505 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, bw) |
506 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, bw_idx ? bw_idx - 1 : 7);
507
508 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
509
510 mt76_wr(dev, MT_WTBL_RIUCR1,
511 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
512 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
513 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[0]));
514
515 mt76_wr(dev, MT_WTBL_RIUCR2,
516 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[0] >> 8) |
517 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
518 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[1]) |
519 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
520
521 mt76_wr(dev, MT_WTBL_RIUCR3,
522 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
523 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[2]) |
524 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
525
526 mt76_wr(dev, MT_WTBL_UPDATE,
527 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
528 MT_WTBL_UPDATE_RATE_UPDATE |
529 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
530
531 mt76_wr(dev, addr + 27 * 4, w27);
532
533 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
534 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
535
536 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
537 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
538}
04b8e659
RL		 539int mt7615_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
540 enum mt76_txq_id qid, struct mt76_wcid *wcid,
541 struct ieee80211_sta *sta,
542 struct mt76_tx_info *tx_info)
543{
544 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
545 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
546 struct mt7615_sta *msta = container_of(wcid, struct mt7615_sta, wcid);
547 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
548 struct ieee80211_key_conf *key = info->control.hw_key;
549 struct ieee80211_vif *vif = info->control.vif;
550 int i, pid, id, nbuf = tx_info->nbuf - 1;
551 u8 *txwi = (u8 *)txwi_ptr;
552 struct mt76_txwi_cache *t;
553 struct mt7615_txp *txp;
554
555 if (!wcid)
556 wcid = &dev->mt76.global_wcid;
557
558 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
559
560 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
561 spin_lock_bh(&dev->mt76.lock);
562 msta->rate_probe = true;
592ed85d 563 mt7615_mac_set_rates(dev, msta, &info->control.rates[0],
04b8e659
RL		 564 msta->rates);
565 spin_unlock_bh(&dev->mt76.lock);
566 }
567
568 mt7615_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, sta,
569 pid, key);
570
571 txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
572 for (i = 0; i < nbuf; i++) {
573 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
e8027946 574 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
04b8e659
RL		 575 }
576 txp->nbuf = nbuf;
577
578 /* pass partial skb header to fw */
579 tx_info->buf[1].len = MT_CT_PARSE_LEN;
580 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
581
582 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
583
584 if (!key)
585 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
586
587 if (ieee80211_is_mgmt(hdr->frame_control))
588 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
589
590 if (vif) {
591 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
592
593 txp->bss_idx = mvif->idx;
594 }
595
596 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
597 t->skb = tx_info->skb;
598
599 spin_lock_bh(&dev->token_lock);
600 id = idr_alloc(&dev->token, t, 0, MT7615_TOKEN_SIZE, GFP_ATOMIC);
601 spin_unlock_bh(&dev->token_lock);
602 if (id < 0)
603 return id;
604
605 txp->token = cpu_to_le16(id);
606 txp->rept_wds_wcid = 0xff;
607 tx_info->skb = DMA_DUMMY_DATA;
608
609 return 0;
610}
611
612static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
613 struct ieee80211_tx_info *info, __le32 *txs_data)
614{
615 struct ieee80211_supported_band *sband;
616 int i, idx, count, final_idx = 0;
d3edd108 617 bool fixed_rate, ack_timeout;
04b8e659
RL		 618 bool probe, ampdu, cck = false;
619 u32 final_rate, final_rate_flags, final_nss, txs;
04b8e659
RL		 620
621 fixed_rate = info->status.rates[0].count;
622 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
623
624 txs = le32_to_cpu(txs_data[1]);
04b8e659
RL		 625 ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU);
626
627 txs = le32_to_cpu(txs_data[3]);
628 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
629
630 txs = le32_to_cpu(txs_data[0]);
04b8e659
RL		 631 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
632 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
633
634 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
635 return false;
636
637 if (txs & MT_TXS0_QUEUE_TIMEOUT)
638 return false;
639
640 if (!ack_timeout)
641 info->flags |= IEEE80211_TX_STAT_ACK;
642
643 info->status.ampdu_len = 1;
644 info->status.ampdu_ack_len = !!(info->flags &
645 IEEE80211_TX_STAT_ACK);
646
647 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
648 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
649
650 if (fixed_rate && !probe) {
651 info->status.rates[0].count = count;
652 goto out;
653 }
654
655 for (i = 0, idx = 0; i < ARRAY_SIZE(info->status.rates); i++) {
656 int cur_count = min_t(int, count, 2 * MT7615_RATE_RETRY);
657
658 if (!i && probe) {
659 cur_count = 1;
660 } else {
661 info->status.rates[i] = sta->rates[idx];
662 idx++;
663 }
664
665 if (i && info->status.rates[i].idx < 0) {
666 info->status.rates[i - 1].count += count;
667 break;
668 }
669
670 if (!count) {
671 info->status.rates[i].idx = -1;
672 break;
673 }
674
675 info->status.rates[i].count = cur_count;
676 final_idx = i;
677 count -= cur_count;
678 }
679
680out:
681 final_rate_flags = info->status.rates[final_idx].flags;
682
683 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
684 case MT_PHY_TYPE_CCK:
685 cck = true;
686 /* fall through */
687 case MT_PHY_TYPE_OFDM:
688 if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ)
689 sband = &dev->mt76.sband_5g.sband;
690 else
691 sband = &dev->mt76.sband_2g.sband;
692 final_rate &= MT_TX_RATE_IDX;
d2679d65
LB		 693 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
694 cck);
04b8e659
RL		 695 final_rate_flags = 0;
696 break;
697 case MT_PHY_TYPE_HT_GF:
698 case MT_PHY_TYPE_HT:
699 final_rate_flags |= IEEE80211_TX_RC_MCS;
700 final_rate &= MT_TX_RATE_IDX;
701 if (final_rate > 31)
702 return false;
703 break;
704 case MT_PHY_TYPE_VHT:
705 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
706 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
707 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
708 break;
709 default:
710 return false;
711 }
712
713 info->status.rates[final_idx].idx = final_rate;
714 info->status.rates[final_idx].flags = final_rate_flags;
715
716 return true;
717}
718
719static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
720 struct mt7615_sta *sta, int pid,
721 __le32 *txs_data)
722{
723 struct mt76_dev *mdev = &dev->mt76;
724 struct sk_buff_head list;
725 struct sk_buff *skb;
726
727 if (pid < MT_PACKET_ID_FIRST)
728 return false;
729
730 mt76_tx_status_lock(mdev, &list);
731 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
732 if (skb) {
733 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
734
735 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
736 spin_lock_bh(&dev->mt76.lock);
737 if (sta->rate_probe) {
592ed85d 738 mt7615_mac_set_rates(dev, sta, NULL,
04b8e659
RL		 739 sta->rates);
740 sta->rate_probe = false;
741 }
742 spin_unlock_bh(&dev->mt76.lock);
743 }
744
745 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
746 ieee80211_tx_info_clear_status(info);
747 info->status.rates[0].idx = -1;
748 }
749
750 mt76_tx_status_skb_done(mdev, skb, &list);
751 }
752 mt76_tx_status_unlock(mdev, &list);
753
754 return !!skb;
755}
756
757void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
758{
759 struct ieee80211_tx_info info = {};
760 struct ieee80211_sta *sta = NULL;
761 struct mt7615_sta *msta = NULL;
762 struct mt76_wcid *wcid;
763 __le32 *txs_data = data;
764 u32 txs;
765 u8 wcidx;
766 u8 pid;
767
768 txs = le32_to_cpu(txs_data[0]);
769 pid = FIELD_GET(MT_TXS0_PID, txs);
770 txs = le32_to_cpu(txs_data[2]);
771 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
772
773 if (pid == MT_PACKET_ID_NO_ACK)
774 return;
775
776 if (wcidx >= ARRAY_SIZE(dev->mt76.wcid))
777 return;
778
779 rcu_read_lock();
780
781 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
782 if (!wcid)
783 goto out;
784
785 msta = container_of(wcid, struct mt7615_sta, wcid);
786 sta = wcid_to_sta(wcid);
787
788 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
789 goto out;
790
791 if (wcidx >= MT7615_WTBL_STA || !sta)
792 goto out;
793
794 if (mt7615_fill_txs(dev, msta, &info, txs_data))
795 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
796
797out:
798 rcu_read_unlock();
799}
800
801void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
802{
803 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
804 struct mt76_dev *mdev = &dev->mt76;
805 struct mt76_txwi_cache *txwi;
806 u8 i, count;
807
808 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
809 for (i = 0; i < count; i++) {
810 spin_lock_bh(&dev->token_lock);
811 txwi = idr_remove(&dev->token, le16_to_cpu(free->token[i]));
812 spin_unlock_bh(&dev->token_lock);
813
814 if (!txwi)
815 continue;
816
817 mt7615_txp_skb_unmap(mdev, txwi);
818 if (txwi->skb) {
819 mt76_tx_complete_skb(mdev, txwi->skb);
820 txwi->skb = NULL;
821 }
822
823 mt76_put_txwi(mdev, txwi);
824 }
825 dev_kfree_skb(skb);
826}
827
828void mt7615_mac_work(struct work_struct *work)
829{
830 struct mt7615_dev *dev;
831
832 dev = (struct mt7615_dev *)container_of(work, struct mt76_dev,
833 mac_work.work);
834
835 mt76_tx_status_check(&dev->mt76, NULL, false);
836 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work,
837 MT7615_WATCHDOG_TIME);
838}
d67a6646
LB		 839
840int mt7615_dfs_stop_radar_detector(struct mt7615_dev *dev)
841{
842 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
843 int err;
844
845 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD0,
846 MT_RX_SEL0, 0);
847 if (err < 0)
848 return err;
849
850 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
851 chandef->width == NL80211_CHAN_WIDTH_80P80)
852 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD1,
853 MT_RX_SEL0, 0);
854 return err;
855}
856
857static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
858{
859 int err;
860
861 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
862 if (err < 0)
863 return err;
864
865 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
866 MT_RX_SEL0, 1);
867}
868
869int mt7615_dfs_start_radar_detector(struct mt7615_dev *dev)
870{
871 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
872 int err;
873
874 /* start CAC */
875 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, MT_HW_RDD0,
876 MT_RX_SEL0, 0);
877 if (err < 0)
878 return err;
879
880 /* TODO: DBDC support */
881
882 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD0);
883 if (err < 0)
884 return err;
885
886 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
887 chandef->width == NL80211_CHAN_WIDTH_80P80) {
888 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD1);
889 if (err < 0)
890 return err;
891 }
892
893 return 0;
894}
895
896int mt7615_dfs_init_radar_detector(struct mt7615_dev *dev)
897{
898 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
899 int err;
900
901 if (dev->mt76.region == NL80211_DFS_UNSET)
902 return 0;
903
904 if (test_bit(MT76_SCANNING, &dev->mt76.state))
905 return 0;
906
907 if (dev->dfs_state == chandef->chan->dfs_state)
908 return 0;
909
910 dev->dfs_state = chandef->chan->dfs_state;
911
912 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
913 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
914 return mt7615_dfs_start_radar_detector(dev);
915 else
916 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, MT_HW_RDD0,
917 MT_RX_SEL0, 0);
918 } else {
919 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START,
920 MT_HW_RDD0, MT_RX_SEL0, 0);
921 if (err < 0)
922 return err;
923
924 return mt7615_dfs_stop_radar_detector(dev);
925 }
926}
Linux 6.x block layer and io_uring tree(s)