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Merge tag 'qcom-soc-for-4.7-2' into net-next
[linux-2.6-block.git] / drivers / net / wireless / marvell / mwifiex / pcie.c
CommitLineData
d930faee
AK		 1/*
2 * Marvell Wireless LAN device driver: PCIE specific handling
3 *
65da33f5 4 * Copyright (C) 2011-2014, Marvell International Ltd.
d930faee
AK		 5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#include <linux/firmware.h>
21
22#include "decl.h"
23#include "ioctl.h"
24#include "util.h"
25#include "fw.h"
26#include "main.h"
27#include "wmm.h"
28#include "11n.h"
29#include "pcie.h"
30
31#define PCIE_VERSION "1.0"
32#define DRV_NAME "Marvell mwifiex PCIe"
33
34static u8 user_rmmod;
35
36static struct mwifiex_if_ops pcie_ops;
37
38static struct semaphore add_remove_card_sem;
d930faee 39
fc331460
AP		 40static int
41mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
dbccc92b 42 size_t size, int flags)
d930faee 43{
fc331460 44 struct pcie_service_card *card = adapter->card;
dbccc92b 45 struct mwifiex_dma_mapping mapping;
d930faee 46
dbccc92b
AD		 47 mapping.addr = pci_map_single(card->dev, skb->data, size, flags);
48 if (pci_dma_mapping_error(card->dev, mapping.addr)) {
acebe8c1 49 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n");
fc331460
AP		 50 return -1;
51 }
dbccc92b 52 mapping.len = size;
bca463e8 53 mwifiex_store_mapping(skb, &mapping);
fc331460 54 return 0;
d930faee
AK		 55}
56
dbccc92b
AD		 57static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter,
58 struct sk_buff *skb, int flags)
59{
60 struct pcie_service_card *card = adapter->card;
61 struct mwifiex_dma_mapping mapping;
62
bca463e8 63 mwifiex_get_mapping(skb, &mapping);
dbccc92b
AD		 64 pci_unmap_single(card->dev, mapping.addr, mapping.len, flags);
65}
66
d930faee
AK		 67/*
68 * This function reads sleep cookie and checks if FW is ready
69 */
70static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
71{
72 u32 *cookie_addr;
73 struct pcie_service_card *card = adapter->card;
52301a81
AP		 74 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
75
76 if (!reg->sleep_cookie)
77 return true;
d930faee 78
fc331460
AP		 79 if (card->sleep_cookie_vbase) {
80 cookie_addr = (u32 *)card->sleep_cookie_vbase;
acebe8c1
ZL		 81 mwifiex_dbg(adapter, INFO,
82 "info: ACCESS_HW: sleep cookie=0x%x\n",
83 *cookie_addr);
d930faee
AK		 84 if (*cookie_addr == FW_AWAKE_COOKIE)
85 return true;
86 }
87
88 return false;
89}
90
3266d732 91#ifdef CONFIG_PM_SLEEP
fcca8d5a
BZ		 92/*
93 * Kernel needs to suspend all functions separately. Therefore all
94 * registered functions must have drivers with suspend and resume
95 * methods. Failing that the kernel simply removes the whole card.
96 *
97 * If already not suspended, this function allocates and sends a host
98 * sleep activate request to the firmware and turns off the traffic.
99 */
3266d732 100static int mwifiex_pcie_suspend(struct device *dev)
fcca8d5a
BZ		 101{
102 struct mwifiex_adapter *adapter;
103 struct pcie_service_card *card;
104 int hs_actived;
3266d732 105 struct pci_dev *pdev = to_pci_dev(dev);
fcca8d5a
BZ		 106
107 if (pdev) {
b2a31204 108 card = pci_get_drvdata(pdev);
fcca8d5a
BZ		 109 if (!card || !card->adapter) {
110 pr_err("Card or adapter structure is not valid\n");
111 return 0;
112 }
113 } else {
114 pr_err("PCIE device is not specified\n");
115 return 0;
116 }
117
118 adapter = card->adapter;
119
120 hs_actived = mwifiex_enable_hs(adapter);
121
122 /* Indicate device suspended */
123 adapter->is_suspended = true;
c0dbba66 124 adapter->hs_enabling = false;
fcca8d5a
BZ		 125
126 return 0;
127}
128
129/*
130 * Kernel needs to suspend all functions separately. Therefore all
131 * registered functions must have drivers with suspend and resume
132 * methods. Failing that the kernel simply removes the whole card.
133 *
134 * If already not resumed, this function turns on the traffic and
135 * sends a host sleep cancel request to the firmware.
136 */
3266d732 137static int mwifiex_pcie_resume(struct device *dev)
fcca8d5a
BZ		 138{
139 struct mwifiex_adapter *adapter;
140 struct pcie_service_card *card;
3266d732 141 struct pci_dev *pdev = to_pci_dev(dev);
fcca8d5a
BZ		 142
143 if (pdev) {
b2a31204 144 card = pci_get_drvdata(pdev);
fcca8d5a
BZ		 145 if (!card || !card->adapter) {
146 pr_err("Card or adapter structure is not valid\n");
147 return 0;
148 }
149 } else {
150 pr_err("PCIE device is not specified\n");
151 return 0;
152 }
153
154 adapter = card->adapter;
155
156 if (!adapter->is_suspended) {
acebe8c1
ZL		 157 mwifiex_dbg(adapter, WARN,
158 "Device already resumed\n");
fcca8d5a
BZ		 159 return 0;
160 }
161
162 adapter->is_suspended = false;
163
164 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
165 MWIFIEX_ASYNC_CMD);
166
167 return 0;
168}
8509e820 169#endif
fcca8d5a 170
d930faee
AK		 171/*
172 * This function probes an mwifiex device and registers it. It allocates
173 * the card structure, enables PCIE function number and initiates the
174 * device registration and initialization procedure by adding a logical
175 * interface.
176 */
177static int mwifiex_pcie_probe(struct pci_dev *pdev,
178 const struct pci_device_id *ent)
179{
180 struct pcie_service_card *card;
181
182 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
f57c1edc 183 pdev->vendor, pdev->device, pdev->revision);
d930faee
AK		 184
185 card = kzalloc(sizeof(struct pcie_service_card), GFP_KERNEL);
e404decb 186 if (!card)
d930faee 187 return -ENOMEM;
d930faee
AK		 188
189 card->dev = pdev;
190
dd04e6ac
AP		 191 if (ent->driver_data) {
192 struct mwifiex_pcie_device *data = (void *)ent->driver_data;
dd04e6ac
AP		 193 card->pcie.reg = data->reg;
194 card->pcie.blksz_fw_dl = data->blksz_fw_dl;
828cf222 195 card->pcie.tx_buf_size = data->tx_buf_size;
b4e8aebb 196 card->pcie.can_dump_fw = data->can_dump_fw;
50632092
XH		 197 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl;
198 card->pcie.num_mem_types = data->num_mem_types;
1fe192d8 199 card->pcie.can_ext_scan = data->can_ext_scan;
dd04e6ac
AP		 200 }
201
d930faee
AK		 202 if (mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops,
203 MWIFIEX_PCIE)) {
204 pr_err("%s failed\n", __func__);
205 kfree(card);
206 return -1;
207 }
208
209 return 0;
210}
211
212/*
213 * This function removes the interface and frees up the card structure.
214 */
215static void mwifiex_pcie_remove(struct pci_dev *pdev)
216{
217 struct pcie_service_card *card;
218 struct mwifiex_adapter *adapter;
f57c1edc 219 struct mwifiex_private *priv;
d930faee
AK		 220
221 card = pci_get_drvdata(pdev);
222 if (!card)
223 return;
224
225 adapter = card->adapter;
226 if (!adapter || !adapter->priv_num)
227 return;
228
229 if (user_rmmod) {
3266d732 230#ifdef CONFIG_PM_SLEEP
d930faee 231 if (adapter->is_suspended)
3266d732 232 mwifiex_pcie_resume(&pdev->dev);
d930faee
AK		 233#endif
234
848819f4 235 mwifiex_deauthenticate_all(adapter);
d930faee 236
f57c1edc 237 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
d930faee 238
f57c1edc
YAP		 239 mwifiex_disable_auto_ds(priv);
240
241 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
d930faee
AK		 242 }
243
244 mwifiex_remove_card(card->adapter, &add_remove_card_sem);
d930faee
AK		 245}
246
43ba6b9f
AK		 247static void mwifiex_pcie_shutdown(struct pci_dev *pdev)
248{
249 user_rmmod = 1;
250 mwifiex_pcie_remove(pdev);
251
252 return;
253}
254
9baa3c34 255static const struct pci_device_id mwifiex_ids[] = {
d930faee
AK		 256 {
257 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6d85ef00 259 .driver_data = (unsigned long)&mwifiex_pcie8766,
d930faee 260 },
ca8f2112
AP		 261 {
262 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6d85ef00
ZL		 264 .driver_data = (unsigned long)&mwifiex_pcie8897,
265 },
266 {
267 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 .driver_data = (unsigned long)&mwifiex_pcie8997,
ca8f2112 270 },
a362e16b
SL		 271 {
272 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 .driver_data = (unsigned long)&mwifiex_pcie8997,
275 },
d930faee
AK		 276 {},
277};
278
279MODULE_DEVICE_TABLE(pci, mwifiex_ids);
280
3266d732
SK		 281#ifdef CONFIG_PM_SLEEP
282/* Power Management Hooks */
283static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend,
284 mwifiex_pcie_resume);
285#endif
286
d930faee
AK		 287/* PCI Device Driver */
288static struct pci_driver __refdata mwifiex_pcie = {
289 .name = "mwifiex_pcie",
290 .id_table = mwifiex_ids,
291 .probe = mwifiex_pcie_probe,
292 .remove = mwifiex_pcie_remove,
3266d732
SK		 293#ifdef CONFIG_PM_SLEEP
294 .driver = {
295 .pm = &mwifiex_pcie_pm_ops,
296 },
d930faee 297#endif
43ba6b9f 298 .shutdown = mwifiex_pcie_shutdown,
d930faee
AK		 299};
300
301/*
302 * This function writes data into PCIE card register.
303 */
304static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data)
305{
306 struct pcie_service_card *card = adapter->card;
307
308 iowrite32(data, card->pci_mmap1 + reg);
309
310 return 0;
311}
312
313/*
314 * This function reads data from PCIE card register.
315 */
316static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data)
317{
318 struct pcie_service_card *card = adapter->card;
319
320 *data = ioread32(card->pci_mmap1 + reg);
af051483
XH		 321 if (*data == 0xffffffff)
322 return 0xffffffff;
d930faee
AK		 323
324 return 0;
325}
326
92c2538f
AK		 327/* This function reads u8 data from PCIE card register. */
328static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter,
329 int reg, u8 *data)
330{
331 struct pcie_service_card *card = adapter->card;
332
333 *data = ioread8(card->pci_mmap1 + reg);
334
335 return 0;
336}
337
d930faee 338/*
c0880a29 339 * This function adds delay loop to ensure FW is awake before proceeding.
d930faee 340 */
c0880a29 341static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter)
d930faee
AK		 342{
343 int i = 0;
344
c0880a29 345 while (mwifiex_pcie_ok_to_access_hw(adapter)) {
d930faee 346 i++;
e7891ba2 347 usleep_range(10, 20);
d930faee 348 /* 50ms max wait */
3e7a4ff7 349 if (i == 5000)
d930faee
AK		 350 break;
351 }
352
c0880a29
AP		 353 return;
354}
355
c4bc980f
AP		 356static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter,
357 u32 max_delay_loop_cnt)
358{
359 struct pcie_service_card *card = adapter->card;
360 u8 *buffer;
361 u32 sleep_cookie, count;
362
363 for (count = 0; count < max_delay_loop_cnt; count++) {
364 buffer = card->cmdrsp_buf->data - INTF_HEADER_LEN;
365 sleep_cookie = *(u32 *)buffer;
366
367 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) {
acebe8c1
ZL		 368 mwifiex_dbg(adapter, INFO,
369 "sleep cookie found at count %d\n", count);
c4bc980f
AP		 370 break;
371 }
372 usleep_range(20, 30);
373 }
374
375 if (count >= max_delay_loop_cnt)
acebe8c1
ZL		 376 mwifiex_dbg(adapter, INFO,
377 "max count reached while accessing sleep cookie\n");
c4bc980f
AP		 378}
379
c0880a29
AP		 380/* This function wakes up the card by reading fw_status register. */
381static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
382{
383 u32 fw_status;
384 struct pcie_service_card *card = adapter->card;
385 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
386
acebe8c1
ZL		 387 mwifiex_dbg(adapter, EVENT,
388 "event: Wakeup device...\n");
d930faee 389
c0880a29
AP		 390 if (reg->sleep_cookie)
391 mwifiex_pcie_dev_wakeup_delay(adapter);
392
393 /* Reading fw_status register will wakeup device */
394 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) {
acebe8c1
ZL		 395 mwifiex_dbg(adapter, ERROR,
396 "Reading fw_status register failed\n");
d930faee
AK		 397 return -1;
398 }
399
c0880a29
AP		 400 if (reg->sleep_cookie) {
401 mwifiex_pcie_dev_wakeup_delay(adapter);
acebe8c1
ZL		 402 mwifiex_dbg(adapter, INFO,
403 "PCIE wakeup: Setting PS_STATE_AWAKE\n");
c0880a29
AP		 404 adapter->ps_state = PS_STATE_AWAKE;
405 }
d930faee
AK		 406
407 return 0;
408}
409
410/*
411 * This function is called after the card has woken up.
412 *
413 * The card configuration register is reset.
414 */
415static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
416{
acebe8c1
ZL		 417 mwifiex_dbg(adapter, CMD,
418 "cmd: Wakeup device completed\n");
d930faee
AK		 419
420 return 0;
421}
422
423/*
424 * This function disables the host interrupt.
425 *
426 * The host interrupt mask is read, the disable bit is reset and
427 * written back to the card host interrupt mask register.
428 */
429static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter)
430{
431 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
432 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
433 0x00000000)) {
acebe8c1
ZL		 434 mwifiex_dbg(adapter, ERROR,
435 "Disable host interrupt failed\n");
d930faee
AK		 436 return -1;
437 }
438 }
439
440 return 0;
441}
442
443/*
444 * This function enables the host interrupt.
445 *
446 * The host interrupt enable mask is written to the card
447 * host interrupt mask register.
448 */
449static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter)
450{
451 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
452 /* Simply write the mask to the register */
453 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
454 HOST_INTR_MASK)) {
acebe8c1
ZL		 455 mwifiex_dbg(adapter, ERROR,
456 "Enable host interrupt failed\n");
d930faee
AK		 457 return -1;
458 }
459 }
460
461 return 0;
462}
463
464/*
0732484b
AP		 465 * This function initializes TX buffer ring descriptors
466 */
467static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter)
468{
469 struct pcie_service_card *card = adapter->card;
ca8f2112 470 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b 471 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 472 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 473 int i;
474
475 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
476 card->tx_buf_list[i] = NULL;
ca8f2112
AP		 477 if (reg->pfu_enabled) {
478 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
479 (sizeof(*desc2) * i);
480 desc2 = card->txbd_ring[i];
481 memset(desc2, 0, sizeof(*desc2));
482 } else {
483 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
484 (sizeof(*desc) * i);
485 desc = card->txbd_ring[i];
486 memset(desc, 0, sizeof(*desc));
487 }
0732484b
AP		 488 }
489
490 return 0;
491}
492
493/* This function initializes RX buffer ring descriptors. Each SKB is allocated
494 * here and after mapping PCI memory, its physical address is assigned to
495 * PCIE Rx buffer descriptor's physical address.
496 */
497static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter)
498{
499 struct pcie_service_card *card = adapter->card;
ca8f2112 500 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b
AP		 501 struct sk_buff *skb;
502 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 503 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 504 dma_addr_t buf_pa;
505 int i;
506
507 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
508 /* Allocate skb here so that firmware can DMA data from it */
62159944
AP		 509 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
510 GFP_KERNEL | GFP_DMA);
0732484b 511 if (!skb) {
acebe8c1
ZL		 512 mwifiex_dbg(adapter, ERROR,
513 "Unable to allocate skb for RX ring.\n");
0732484b
AP		 514 kfree(card->rxbd_ring_vbase);
515 return -ENOMEM;
516 }
517
518 if (mwifiex_map_pci_memory(adapter, skb,
519 MWIFIEX_RX_DATA_BUF_SIZE,
520 PCI_DMA_FROMDEVICE))
521 return -1;
522
dbccc92b 523 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
0732484b 524
acebe8c1
ZL		 525 mwifiex_dbg(adapter, INFO,
526 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
527 skb, skb->len, skb->data, (u32)buf_pa,
528 (u32)((u64)buf_pa >> 32));
0732484b
AP		 529
530 card->rx_buf_list[i] = skb;
ca8f2112
AP		 531 if (reg->pfu_enabled) {
532 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase +
533 (sizeof(*desc2) * i);
534 desc2 = card->rxbd_ring[i];
535 desc2->paddr = buf_pa;
536 desc2->len = (u16)skb->len;
537 desc2->frag_len = (u16)skb->len;
538 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop;
539 desc2->offset = 0;
540 } else {
541 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase +
542 (sizeof(*desc) * i));
543 desc = card->rxbd_ring[i];
544 desc->paddr = buf_pa;
545 desc->len = (u16)skb->len;
546 desc->flags = 0;
547 }
0732484b
AP		 548 }
549
550 return 0;
551}
552
553/* This function initializes event buffer ring descriptors. Each SKB is
554 * allocated here and after mapping PCI memory, its physical address is assigned
555 * to PCIE Rx buffer descriptor's physical address
556 */
557static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
558{
559 struct pcie_service_card *card = adapter->card;
e05dc3e9 560 struct mwifiex_evt_buf_desc *desc;
0732484b
AP		 561 struct sk_buff *skb;
562 dma_addr_t buf_pa;
563 int i;
564
565 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
566 /* Allocate skb here so that firmware can DMA data from it */
567 skb = dev_alloc_skb(MAX_EVENT_SIZE);
568 if (!skb) {
acebe8c1
ZL		 569 mwifiex_dbg(adapter, ERROR,
570 "Unable to allocate skb for EVENT buf.\n");
0732484b
AP		 571 kfree(card->evtbd_ring_vbase);
572 return -ENOMEM;
573 }
574 skb_put(skb, MAX_EVENT_SIZE);
575
576 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
577 PCI_DMA_FROMDEVICE))
578 return -1;
579
dbccc92b 580 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
0732484b 581
acebe8c1
ZL		 582 mwifiex_dbg(adapter, EVENT,
583 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
584 skb, skb->len, skb->data, (u32)buf_pa,
585 (u32)((u64)buf_pa >> 32));
0732484b
AP		 586
587 card->evt_buf_list[i] = skb;
588 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase +
589 (sizeof(*desc) * i));
0732484b
AP		 590 desc = card->evtbd_ring[i];
591 desc->paddr = buf_pa;
592 desc->len = (u16)skb->len;
593 desc->flags = 0;
594 }
595
596 return 0;
597}
598
599/* This function cleans up TX buffer rings. If any of the buffer list has valid
600 * SKB address, associated SKB is freed.
601 */
602static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter)
603{
604 struct pcie_service_card *card = adapter->card;
ca8f2112 605 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b
AP		 606 struct sk_buff *skb;
607 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 608 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 609 int i;
610
611 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
ca8f2112
AP		 612 if (reg->pfu_enabled) {
613 desc2 = card->txbd_ring[i];
614 if (card->tx_buf_list[i]) {
615 skb = card->tx_buf_list[i];
dbccc92b
AD		 616 mwifiex_unmap_pci_memory(adapter, skb,
617 PCI_DMA_TODEVICE);
ca8f2112
AP		 618 dev_kfree_skb_any(skb);
619 }
620 memset(desc2, 0, sizeof(*desc2));
621 } else {
622 desc = card->txbd_ring[i];
623 if (card->tx_buf_list[i]) {
624 skb = card->tx_buf_list[i];
dbccc92b
AD		 625 mwifiex_unmap_pci_memory(adapter, skb,
626 PCI_DMA_TODEVICE);
ca8f2112
AP		 627 dev_kfree_skb_any(skb);
628 }
629 memset(desc, 0, sizeof(*desc));
0732484b
AP		 630 }
631 card->tx_buf_list[i] = NULL;
0732484b
AP		 632 }
633
634 return;
635}
636
637/* This function cleans up RX buffer rings. If any of the buffer list has valid
638 * SKB address, associated SKB is freed.
639 */
640static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter)
641{
642 struct pcie_service_card *card = adapter->card;
ca8f2112 643 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b 644 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 645 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 646 struct sk_buff *skb;
647 int i;
648
649 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
ca8f2112
AP		 650 if (reg->pfu_enabled) {
651 desc2 = card->rxbd_ring[i];
652 if (card->rx_buf_list[i]) {
653 skb = card->rx_buf_list[i];
dbccc92b
AD		 654 mwifiex_unmap_pci_memory(adapter, skb,
655 PCI_DMA_FROMDEVICE);
ca8f2112
AP		 656 dev_kfree_skb_any(skb);
657 }
658 memset(desc2, 0, sizeof(*desc2));
659 } else {
660 desc = card->rxbd_ring[i];
661 if (card->rx_buf_list[i]) {
662 skb = card->rx_buf_list[i];
dbccc92b
AD		 663 mwifiex_unmap_pci_memory(adapter, skb,
664 PCI_DMA_FROMDEVICE);
ca8f2112
AP		 665 dev_kfree_skb_any(skb);
666 }
667 memset(desc, 0, sizeof(*desc));
0732484b 668 }
ca8f2112 669 card->rx_buf_list[i] = NULL;
0732484b
AP		 670 }
671
672 return;
673}
674
675/* This function cleans up event buffer rings. If any of the buffer list has
676 * valid SKB address, associated SKB is freed.
677 */
678static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter)
679{
680 struct pcie_service_card *card = adapter->card;
e05dc3e9 681 struct mwifiex_evt_buf_desc *desc;
0732484b
AP		 682 struct sk_buff *skb;
683 int i;
684
685 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
686 desc = card->evtbd_ring[i];
687 if (card->evt_buf_list[i]) {
688 skb = card->evt_buf_list[i];
dbccc92b
AD		 689 mwifiex_unmap_pci_memory(adapter, skb,
690 PCI_DMA_FROMDEVICE);
0732484b
AP		 691 dev_kfree_skb_any(skb);
692 }
693 card->evt_buf_list[i] = NULL;
694 memset(desc, 0, sizeof(*desc));
695 }
696
697 return;
698}
699
700/* This function creates buffer descriptor ring for TX
d930faee
AK		 701 */
702static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter)
703{
704 struct pcie_service_card *card = adapter->card;
dd04e6ac 705 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 706
707 /*
708 * driver maintaines the write pointer and firmware maintaines the read
709 * pointer. The write pointer starts at 0 (zero) while the read pointer
710 * starts at zero with rollover bit set
711 */
712 card->txbd_wrptr = 0;
ca8f2112
AP		 713
714 if (reg->pfu_enabled)
715 card->txbd_rdptr = 0;
716 else
717 card->txbd_rdptr |= reg->tx_rollover_ind;
d930faee
AK		 718
719 /* allocate shared memory for the BD ring and divide the same in to
720 several descriptors */
ca8f2112
AP		 721 if (reg->pfu_enabled)
722 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
723 MWIFIEX_MAX_TXRX_BD;
724 else
725 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
726 MWIFIEX_MAX_TXRX_BD;
727
acebe8c1
ZL		 728 mwifiex_dbg(adapter, INFO,
729 "info: txbd_ring: Allocating %d bytes\n",
730 card->txbd_ring_size);
fc331460
AP		 731 card->txbd_ring_vbase = pci_alloc_consistent(card->dev,
732 card->txbd_ring_size,
733 &card->txbd_ring_pbase);
d930faee 734 if (!card->txbd_ring_vbase) {
acebe8c1
ZL		 735 mwifiex_dbg(adapter, ERROR,
736 "allocate consistent memory (%d bytes) failed!\n",
737 card->txbd_ring_size);
8c53e42d 738 return -ENOMEM;
d930faee 739 }
acebe8c1
ZL		 740 mwifiex_dbg(adapter, DATA,
741 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %x\n",
742 card->txbd_ring_vbase, (unsigned int)card->txbd_ring_pbase,
743 (u32)((u64)card->txbd_ring_pbase >> 32),
744 card->txbd_ring_size);
d930faee 745
0732484b 746 return mwifiex_init_txq_ring(adapter);
d930faee
AK		 747}
748
749static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter)
750{
751 struct pcie_service_card *card = adapter->card;
dd04e6ac 752 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 753
0732484b 754 mwifiex_cleanup_txq_ring(adapter);
d930faee 755
fc331460
AP		 756 if (card->txbd_ring_vbase)
757 pci_free_consistent(card->dev, card->txbd_ring_size,
758 card->txbd_ring_vbase,
759 card->txbd_ring_pbase);
d930faee
AK		 760 card->txbd_ring_size = 0;
761 card->txbd_wrptr = 0;
dd04e6ac 762 card->txbd_rdptr = 0 | reg->tx_rollover_ind;
d930faee 763 card->txbd_ring_vbase = NULL;
fc331460 764 card->txbd_ring_pbase = 0;
d930faee
AK		 765
766 return 0;
767}
768
769/*
770 * This function creates buffer descriptor ring for RX
771 */
772static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter)
773{
774 struct pcie_service_card *card = adapter->card;
dd04e6ac 775 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 776
777 /*
778 * driver maintaines the read pointer and firmware maintaines the write
779 * pointer. The write pointer starts at 0 (zero) while the read pointer
780 * starts at zero with rollover bit set
781 */
782 card->rxbd_wrptr = 0;
dd04e6ac 783 card->rxbd_rdptr = reg->rx_rollover_ind;
d930faee 784
ca8f2112
AP		 785 if (reg->pfu_enabled)
786 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
787 MWIFIEX_MAX_TXRX_BD;
788 else
789 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
790 MWIFIEX_MAX_TXRX_BD;
791
acebe8c1
ZL		 792 mwifiex_dbg(adapter, INFO,
793 "info: rxbd_ring: Allocating %d bytes\n",
794 card->rxbd_ring_size);
fc331460
AP		 795 card->rxbd_ring_vbase = pci_alloc_consistent(card->dev,
796 card->rxbd_ring_size,
797 &card->rxbd_ring_pbase);
d930faee 798 if (!card->rxbd_ring_vbase) {
acebe8c1
ZL		 799 mwifiex_dbg(adapter, ERROR,
800 "allocate consistent memory (%d bytes) failed!\n",
801 card->rxbd_ring_size);
8c53e42d 802 return -ENOMEM;
d930faee 803 }
d930faee 804
acebe8c1
ZL		 805 mwifiex_dbg(adapter, DATA,
806 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
807 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase,
808 (u32)((u64)card->rxbd_ring_pbase >> 32),
809 card->rxbd_ring_size);
d930faee 810
0732484b 811 return mwifiex_init_rxq_ring(adapter);
d930faee
AK		 812}
813
814/*
815 * This function deletes Buffer descriptor ring for RX
816 */
817static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter)
818{
819 struct pcie_service_card *card = adapter->card;
dd04e6ac 820 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 821
0732484b 822 mwifiex_cleanup_rxq_ring(adapter);
d930faee 823
fc331460
AP		 824 if (card->rxbd_ring_vbase)
825 pci_free_consistent(card->dev, card->rxbd_ring_size,
826 card->rxbd_ring_vbase,
827 card->rxbd_ring_pbase);
d930faee
AK		 828 card->rxbd_ring_size = 0;
829 card->rxbd_wrptr = 0;
dd04e6ac 830 card->rxbd_rdptr = 0 | reg->rx_rollover_ind;
d930faee 831 card->rxbd_ring_vbase = NULL;
fc331460 832 card->rxbd_ring_pbase = 0;
d930faee
AK		 833
834 return 0;
835}
836
837/*
838 * This function creates buffer descriptor ring for Events
839 */
840static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter)
841{
842 struct pcie_service_card *card = adapter->card;
dd04e6ac 843 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 844
845 /*
846 * driver maintaines the read pointer and firmware maintaines the write
847 * pointer. The write pointer starts at 0 (zero) while the read pointer
848 * starts at zero with rollover bit set
849 */
850 card->evtbd_wrptr = 0;
dd04e6ac 851 card->evtbd_rdptr = reg->evt_rollover_ind;
d930faee 852
e05dc3e9 853 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) *
ca8f2112
AP		 854 MWIFIEX_MAX_EVT_BD;
855
acebe8c1
ZL		 856 mwifiex_dbg(adapter, INFO,
857 "info: evtbd_ring: Allocating %d bytes\n",
f57c1edc 858 card->evtbd_ring_size);
fc331460
AP		 859 card->evtbd_ring_vbase = pci_alloc_consistent(card->dev,
860 card->evtbd_ring_size,
861 &card->evtbd_ring_pbase);
d930faee 862 if (!card->evtbd_ring_vbase) {
acebe8c1
ZL		 863 mwifiex_dbg(adapter, ERROR,
864 "allocate consistent memory (%d bytes) failed!\n",
865 card->evtbd_ring_size);
8c53e42d 866 return -ENOMEM;
d930faee 867 }
d930faee 868
acebe8c1
ZL		 869 mwifiex_dbg(adapter, EVENT,
870 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n",
871 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase,
872 (u32)((u64)card->evtbd_ring_pbase >> 32),
873 card->evtbd_ring_size);
d930faee 874
0732484b 875 return mwifiex_pcie_init_evt_ring(adapter);
d930faee
AK		 876}
877
878/*
879 * This function deletes Buffer descriptor ring for Events
880 */
881static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter)
882{
883 struct pcie_service_card *card = adapter->card;
dd04e6ac 884 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 885
0732484b 886 mwifiex_cleanup_evt_ring(adapter);
d930faee 887
fc331460
AP		 888 if (card->evtbd_ring_vbase)
889 pci_free_consistent(card->dev, card->evtbd_ring_size,
890 card->evtbd_ring_vbase,
891 card->evtbd_ring_pbase);
d930faee 892 card->evtbd_wrptr = 0;
dd04e6ac 893 card->evtbd_rdptr = 0 | reg->evt_rollover_ind;
d930faee
AK		 894 card->evtbd_ring_size = 0;
895 card->evtbd_ring_vbase = NULL;
fc331460 896 card->evtbd_ring_pbase = 0;
d930faee
AK		 897
898 return 0;
899}
900
901/*
902 * This function allocates a buffer for CMDRSP
903 */
904static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter)
905{
906 struct pcie_service_card *card = adapter->card;
907 struct sk_buff *skb;
908
909 /* Allocate memory for receiving command response data */
910 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
911 if (!skb) {
acebe8c1
ZL		 912 mwifiex_dbg(adapter, ERROR,
913 "Unable to allocate skb for command response data.\n");
d930faee
AK		 914 return -ENOMEM;
915 }
d930faee 916 skb_put(skb, MWIFIEX_UPLD_SIZE);
fc331460
AP		 917 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
918 PCI_DMA_FROMDEVICE))
919 return -1;
d930faee 920
fc331460 921 card->cmdrsp_buf = skb;
d930faee
AK		 922
923 return 0;
924}
925
926/*
927 * This function deletes a buffer for CMDRSP
928 */
929static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter)
930{
931 struct pcie_service_card *card;
932
933 if (!adapter)
934 return 0;
935
936 card = adapter->card;
937
fc331460 938 if (card && card->cmdrsp_buf) {
dbccc92b
AD		 939 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf,
940 PCI_DMA_FROMDEVICE);
d930faee 941 dev_kfree_skb_any(card->cmdrsp_buf);
fc331460 942 }
d930faee 943
fc331460 944 if (card && card->cmd_buf) {
dbccc92b
AD		 945 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
946 PCI_DMA_TODEVICE);
fc331460 947 }
d930faee
AK		 948 return 0;
949}
950
951/*
952 * This function allocates a buffer for sleep cookie
953 */
954static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter)
955{
d930faee
AK		 956 struct pcie_service_card *card = adapter->card;
957
fc331460
AP		 958 card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32),
959 &card->sleep_cookie_pbase);
960 if (!card->sleep_cookie_vbase) {
acebe8c1
ZL		 961 mwifiex_dbg(adapter, ERROR,
962 "pci_alloc_consistent failed!\n");
d930faee
AK		 963 return -ENOMEM;
964 }
d930faee 965 /* Init val of Sleep Cookie */
fc331460 966 *(u32 *)card->sleep_cookie_vbase = FW_AWAKE_COOKIE;
d930faee 967
acebe8c1
ZL		 968 mwifiex_dbg(adapter, INFO,
969 "alloc_scook: sleep cookie=0x%x\n",
970 *((u32 *)card->sleep_cookie_vbase));
d930faee
AK		 971
972 return 0;
973}
974
975/*
976 * This function deletes buffer for sleep cookie
977 */
978static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter)
979{
980 struct pcie_service_card *card;
981
982 if (!adapter)
983 return 0;
984
985 card = adapter->card;
986
fc331460
AP		 987 if (card && card->sleep_cookie_vbase) {
988 pci_free_consistent(card->dev, sizeof(u32),
989 card->sleep_cookie_vbase,
990 card->sleep_cookie_pbase);
991 card->sleep_cookie_vbase = NULL;
d930faee
AK		 992 }
993
994 return 0;
995}
996
fbd7e7ac
AP		 997/* This function flushes the TX buffer descriptor ring
998 * This function defined as handler is also called while cleaning TXRX
999 * during disconnect/ bss stop.
1000 */
1001static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter)
1002{
1003 struct pcie_service_card *card = adapter->card;
fbd7e7ac 1004
48f4d916 1005 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) {
fbd7e7ac
AP		 1006 card->txbd_flush = 1;
1007 /* write pointer already set at last send
1008 * send dnld-rdy intr again, wait for completion.
1009 */
1010 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1011 CPU_INTR_DNLD_RDY)) {
acebe8c1
ZL		 1012 mwifiex_dbg(adapter, ERROR,
1013 "failed to assert dnld-rdy interrupt.\n");
fbd7e7ac
AP		 1014 return -1;
1015 }
1016 }
1017 return 0;
1018}
1019
d930faee 1020/*
e7f767a7 1021 * This function unmaps and frees downloaded data buffer
d930faee 1022 */
e7f767a7 1023static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter)
d930faee 1024{
e7f767a7 1025 struct sk_buff *skb;
ca8f2112 1026 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0;
e05dc3e9 1027 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 1028 struct mwifiex_pfu_buf_desc *desc2;
d930faee 1029 struct pcie_service_card *card = adapter->card;
dd04e6ac 1030 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1031
1032 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1033 mwifiex_pm_wakeup_card(adapter);
1034
1035 /* Read the TX ring read pointer set by firmware */
dd04e6ac 1036 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) {
acebe8c1
ZL		 1037 mwifiex_dbg(adapter, ERROR,
1038 "SEND COMP: failed to read reg->tx_rdptr\n");
d930faee
AK		 1039 return -1;
1040 }
1041
acebe8c1
ZL		 1042 mwifiex_dbg(adapter, DATA,
1043 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n",
1044 card->txbd_rdptr, rdptr);
d930faee 1045
ca8f2112 1046 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
e7f767a7 1047 /* free from previous txbd_rdptr to current txbd_rdptr */
dd04e6ac
AP		 1048 while (((card->txbd_rdptr & reg->tx_mask) !=
1049 (rdptr & reg->tx_mask)) ||
1050 ((card->txbd_rdptr & reg->tx_rollover_ind) !=
1051 (rdptr & reg->tx_rollover_ind))) {
ca8f2112
AP		 1052 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >>
1053 reg->tx_start_ptr;
e7f767a7
AP		 1054
1055 skb = card->tx_buf_list[wrdoneidx];
dbccc92b 1056
e7f767a7 1057 if (skb) {
acebe8c1
ZL		 1058 mwifiex_dbg(adapter, DATA,
1059 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n",
1060 skb, wrdoneidx);
dbccc92b
AD		 1061 mwifiex_unmap_pci_memory(adapter, skb,
1062 PCI_DMA_TODEVICE);
e7f767a7
AP		 1063
1064 unmap_count++;
1065
1066 if (card->txbd_flush)
1067 mwifiex_write_data_complete(adapter, skb, 0,
1068 -1);
1069 else
1070 mwifiex_write_data_complete(adapter, skb, 0, 0);
1071 }
1072
1073 card->tx_buf_list[wrdoneidx] = NULL;
ca8f2112
AP		 1074
1075 if (reg->pfu_enabled) {
45d18c56 1076 desc2 = card->txbd_ring[wrdoneidx];
ca8f2112
AP		 1077 memset(desc2, 0, sizeof(*desc2));
1078 } else {
1079 desc = card->txbd_ring[wrdoneidx];
1080 memset(desc, 0, sizeof(*desc));
1081 }
1082 switch (card->dev->device) {
1083 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1084 card->txbd_rdptr++;
1085 break;
1086 case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00 1087 case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112
AP		 1088 card->txbd_rdptr += reg->ring_tx_start_ptr;
1089 break;
1090 }
1091
e7f767a7 1092
dd04e6ac 1093 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs)
e7f767a7 1094 card->txbd_rdptr = ((card->txbd_rdptr &
dd04e6ac
AP		 1095 reg->tx_rollover_ind) ^
1096 reg->tx_rollover_ind);
e7f767a7
AP		 1097 }
1098
1099 if (unmap_count)
1100 adapter->data_sent = false;
1101
1102 if (card->txbd_flush) {
3d482038 1103 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr))
e7f767a7
AP		 1104 card->txbd_flush = 0;
1105 else
1106 mwifiex_clean_pcie_ring_buf(adapter);
1107 }
1108
1109 return 0;
1110}
1111
1112/* This function sends data buffer to device. First 4 bytes of payload
1113 * are filled with payload length and payload type. Then this payload
1114 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly.
1115 * Download ready interrupt to FW is deffered if Tx ring is not full and
1116 * additional payload can be accomodated.
8d767dcb 1117 * Caller must ensure tx_param parameter to this function is not NULL.
e7f767a7
AP		 1118 */
1119static int
1120mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb,
1121 struct mwifiex_tx_param *tx_param)
1122{
1123 struct pcie_service_card *card = adapter->card;
dd04e6ac 1124 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1125 u32 wrindx, num_tx_buffs, rx_val;
e7f767a7
AP		 1126 int ret;
1127 dma_addr_t buf_pa;
9931078e
BZ		 1128 struct mwifiex_pcie_buf_desc *desc = NULL;
1129 struct mwifiex_pfu_buf_desc *desc2 = NULL;
e7f767a7
AP		 1130 __le16 *tmp;
1131
1132 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1133 mwifiex_dbg(adapter, ERROR,
1134 "%s(): invalid parameter <%p, %#x>\n",
1135 __func__, skb->data, skb->len);
e7f767a7
AP		 1136 return -1;
1137 }
1138
1139 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1140 mwifiex_pm_wakeup_card(adapter);
1141
ca8f2112 1142 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
acebe8c1
ZL		 1143 mwifiex_dbg(adapter, DATA,
1144 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n",
e7f767a7
AP		 1145 card->txbd_rdptr, card->txbd_wrptr);
1146 if (mwifiex_pcie_txbd_not_full(card)) {
d930faee
AK		 1147 u8 *payload;
1148
1149 adapter->data_sent = true;
e7f767a7 1150 payload = skb->data;
d930faee
AK		 1151 tmp = (__le16 *)&payload[0];
1152 *tmp = cpu_to_le16((u16)skb->len);
1153 tmp = (__le16 *)&payload[2];
1154 *tmp = cpu_to_le16(MWIFIEX_TYPE_DATA);
e7f767a7 1155
dbccc92b 1156 if (mwifiex_map_pci_memory(adapter, skb, skb->len,
e7f767a7
AP		 1157 PCI_DMA_TODEVICE))
1158 return -1;
1159
ca8f2112 1160 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr;
dbccc92b 1161 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
e7f767a7 1162 card->tx_buf_list[wrindx] = skb;
d930faee 1163
ca8f2112 1164 if (reg->pfu_enabled) {
45d18c56 1165 desc2 = card->txbd_ring[wrindx];
ca8f2112
AP		 1166 desc2->paddr = buf_pa;
1167 desc2->len = (u16)skb->len;
1168 desc2->frag_len = (u16)skb->len;
1169 desc2->offset = 0;
1170 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1171 MWIFIEX_BD_FLAG_LAST_DESC;
1172 } else {
1173 desc = card->txbd_ring[wrindx];
1174 desc->paddr = buf_pa;
1175 desc->len = (u16)skb->len;
1176 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1177 MWIFIEX_BD_FLAG_LAST_DESC;
1178 }
1179
1180 switch (card->dev->device) {
1181 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1182 card->txbd_wrptr++;
1183 break;
1184 case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00 1185 case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112
AP		 1186 card->txbd_wrptr += reg->ring_tx_start_ptr;
1187 break;
1188 }
1189
1190 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs)
d930faee 1191 card->txbd_wrptr = ((card->txbd_wrptr &
dd04e6ac
AP		 1192 reg->tx_rollover_ind) ^
1193 reg->tx_rollover_ind);
d930faee 1194
ca8f2112 1195 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask;
dd04e6ac
AP		 1196 /* Write the TX ring write pointer in to reg->tx_wrptr */
1197 if (mwifiex_write_reg(adapter, reg->tx_wrptr,
ca8f2112 1198 card->txbd_wrptr | rx_val)) {
acebe8c1
ZL		 1199 mwifiex_dbg(adapter, ERROR,
1200 "SEND DATA: failed to write reg->tx_wrptr\n");
e7f767a7
AP		 1201 ret = -1;
1202 goto done_unmap;
d930faee 1203 }
e7f767a7
AP		 1204 if ((mwifiex_pcie_txbd_not_full(card)) &&
1205 tx_param->next_pkt_len) {
1206 /* have more packets and TxBD still can hold more */
acebe8c1
ZL		 1207 mwifiex_dbg(adapter, DATA,
1208 "SEND DATA: delay dnld-rdy interrupt.\n");
e7f767a7
AP		 1209 adapter->data_sent = false;
1210 } else {
1211 /* Send the TX ready interrupt */
1212 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1213 CPU_INTR_DNLD_RDY)) {
acebe8c1
ZL		 1214 mwifiex_dbg(adapter, ERROR,
1215 "SEND DATA: failed to assert dnld-rdy interrupt.\n");
e7f767a7
AP		 1216 ret = -1;
1217 goto done_unmap;
1218 }
d930faee 1219 }
acebe8c1
ZL		 1220 mwifiex_dbg(adapter, DATA,
1221 "info: SEND DATA: Updated <Rd: %#x, Wr:\t"
1222 "%#x> and sent packet to firmware successfully\n",
1223 card->txbd_rdptr, card->txbd_wrptr);
d930faee 1224 } else {
acebe8c1
ZL		 1225 mwifiex_dbg(adapter, DATA,
1226 "info: TX Ring full, can't send packets to fw\n");
d930faee
AK		 1227 adapter->data_sent = true;
1228 /* Send the TX ready interrupt */
1229 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1230 CPU_INTR_DNLD_RDY))
acebe8c1
ZL		 1231 mwifiex_dbg(adapter, ERROR,
1232 "SEND DATA: failed to assert door-bell intr\n");
d930faee
AK		 1233 return -EBUSY;
1234 }
1235
e7f767a7
AP		 1236 return -EINPROGRESS;
1237done_unmap:
dbccc92b 1238 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
e7f767a7 1239 card->tx_buf_list[wrindx] = NULL;
ca8f2112
AP		 1240 if (reg->pfu_enabled)
1241 memset(desc2, 0, sizeof(*desc2));
1242 else
1243 memset(desc, 0, sizeof(*desc));
1244
e7f767a7 1245 return ret;
d930faee
AK		 1246}
1247
1248/*
1249 * This function handles received buffer ring and
1250 * dispatches packets to upper
1251 */
1252static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter)
1253{
1254 struct pcie_service_card *card = adapter->card;
dd04e6ac 1255 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1256 u32 wrptr, rd_index, tx_val;
e7f767a7 1257 dma_addr_t buf_pa;
d930faee
AK		 1258 int ret = 0;
1259 struct sk_buff *skb_tmp = NULL;
e05dc3e9 1260 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 1261 struct mwifiex_pfu_buf_desc *desc2;
d930faee 1262
e7f767a7
AP		 1263 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1264 mwifiex_pm_wakeup_card(adapter);
1265
d930faee 1266 /* Read the RX ring Write pointer set by firmware */
dd04e6ac 1267 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
acebe8c1
ZL		 1268 mwifiex_dbg(adapter, ERROR,
1269 "RECV DATA: failed to read reg->rx_wrptr\n");
d930faee
AK		 1270 ret = -1;
1271 goto done;
1272 }
e7f767a7 1273 card->rxbd_wrptr = wrptr;
d930faee 1274
dd04e6ac
AP		 1275 while (((wrptr & reg->rx_mask) !=
1276 (card->rxbd_rdptr & reg->rx_mask)) ||
1277 ((wrptr & reg->rx_rollover_ind) ==
1278 (card->rxbd_rdptr & reg->rx_rollover_ind))) {
d930faee
AK		 1279 struct sk_buff *skb_data;
1280 u16 rx_len;
e7f767a7 1281 __le16 pkt_len;
d930faee 1282
dd04e6ac 1283 rd_index = card->rxbd_rdptr & reg->rx_mask;
d930faee
AK		 1284 skb_data = card->rx_buf_list[rd_index];
1285
bb8e6a1e
AK		 1286 /* If skb allocation was failed earlier for Rx packet,
1287 * rx_buf_list[rd_index] would have been left with a NULL.
1288 */
1289 if (!skb_data)
1290 return -ENOMEM;
1291
dbccc92b 1292 mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE);
e7f767a7
AP		 1293 card->rx_buf_list[rd_index] = NULL;
1294
d930faee 1295 /* Get data length from interface header -
e7f767a7
AP		 1296 * first 2 bytes for len, next 2 bytes is for type
1297 */
1298 pkt_len = *((__le16 *)skb_data->data);
1299 rx_len = le16_to_cpu(pkt_len);
42a028aa
AP		 1300 if (WARN_ON(rx_len <= INTF_HEADER_LEN ||
1301 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) {
acebe8c1
ZL		 1302 mwifiex_dbg(adapter, ERROR,
1303 "Invalid RX len %d, Rd=%#x, Wr=%#x\n",
1304 rx_len, card->rxbd_rdptr, wrptr);
42a028aa
AP		 1305 dev_kfree_skb_any(skb_data);
1306 } else {
1307 skb_put(skb_data, rx_len);
acebe8c1
ZL		 1308 mwifiex_dbg(adapter, DATA,
1309 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n",
1310 card->rxbd_rdptr, wrptr, rx_len);
42a028aa 1311 skb_pull(skb_data, INTF_HEADER_LEN);
6e251174 1312 if (adapter->rx_work_enabled) {
6e251174 1313 skb_queue_tail(&adapter->rx_data_q, skb_data);
6e251174
AP		 1314 adapter->data_received = true;
1315 atomic_inc(&adapter->rx_pending);
1316 } else {
1317 mwifiex_handle_rx_packet(adapter, skb_data);
1318 }
42a028aa 1319 }
e7f767a7 1320
62159944
AP		 1321 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
1322 GFP_KERNEL | GFP_DMA);
d930faee 1323 if (!skb_tmp) {
acebe8c1
ZL		 1324 mwifiex_dbg(adapter, ERROR,
1325 "Unable to allocate skb.\n");
e7f767a7 1326 return -ENOMEM;
d930faee
AK		 1327 }
1328
e7f767a7
AP		 1329 if (mwifiex_map_pci_memory(adapter, skb_tmp,
1330 MWIFIEX_RX_DATA_BUF_SIZE,
1331 PCI_DMA_FROMDEVICE))
1332 return -1;
1333
dbccc92b 1334 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp);
e7f767a7 1335
acebe8c1
ZL		 1336 mwifiex_dbg(adapter, INFO,
1337 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n",
1338 skb_tmp, rd_index);
e7f767a7 1339 card->rx_buf_list[rd_index] = skb_tmp;
ca8f2112
AP		 1340
1341 if (reg->pfu_enabled) {
45d18c56 1342 desc2 = card->rxbd_ring[rd_index];
ca8f2112
AP		 1343 desc2->paddr = buf_pa;
1344 desc2->len = skb_tmp->len;
1345 desc2->frag_len = skb_tmp->len;
1346 desc2->offset = 0;
1347 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop;
1348 } else {
1349 desc = card->rxbd_ring[rd_index];
1350 desc->paddr = buf_pa;
1351 desc->len = skb_tmp->len;
1352 desc->flags = 0;
1353 }
d930faee 1354
dd04e6ac 1355 if ((++card->rxbd_rdptr & reg->rx_mask) ==
d930faee
AK		 1356 MWIFIEX_MAX_TXRX_BD) {
1357 card->rxbd_rdptr = ((card->rxbd_rdptr &
dd04e6ac
AP		 1358 reg->rx_rollover_ind) ^
1359 reg->rx_rollover_ind);
d930faee 1360 }
acebe8c1
ZL		 1361 mwifiex_dbg(adapter, DATA,
1362 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n",
1363 card->rxbd_rdptr, wrptr);
d930faee 1364
ca8f2112 1365 tx_val = card->txbd_wrptr & reg->tx_wrap_mask;
dd04e6ac
AP		 1366 /* Write the RX ring read pointer in to reg->rx_rdptr */
1367 if (mwifiex_write_reg(adapter, reg->rx_rdptr,
ca8f2112 1368 card->rxbd_rdptr | tx_val)) {
acebe8c1
ZL		 1369 mwifiex_dbg(adapter, DATA,
1370 "RECV DATA: failed to write reg->rx_rdptr\n");
d930faee
AK		 1371 ret = -1;
1372 goto done;
1373 }
1374
1375 /* Read the RX ring Write pointer set by firmware */
dd04e6ac 1376 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
acebe8c1
ZL		 1377 mwifiex_dbg(adapter, ERROR,
1378 "RECV DATA: failed to read reg->rx_wrptr\n");
d930faee
AK		 1379 ret = -1;
1380 goto done;
1381 }
acebe8c1
ZL		 1382 mwifiex_dbg(adapter, DATA,
1383 "info: RECV DATA: Rcvd packet from fw successfully\n");
e7f767a7 1384 card->rxbd_wrptr = wrptr;
d930faee
AK		 1385 }
1386
1387done:
d930faee
AK		 1388 return ret;
1389}
1390
1391/*
1392 * This function downloads the boot command to device
1393 */
1394static int
1395mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1396{
fc331460
AP		 1397 dma_addr_t buf_pa;
1398 struct pcie_service_card *card = adapter->card;
dd04e6ac 1399 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 1400
fc331460 1401 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1402 mwifiex_dbg(adapter, ERROR,
1403 "Invalid parameter in %s <%p. len %d>\n",
1404 __func__, skb->data, skb->len);
d930faee
AK		 1405 return -1;
1406 }
1407
3a968d76 1408 if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
fc331460
AP		 1409 return -1;
1410
dbccc92b 1411 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
fc331460 1412
dd04e6ac
AP		 1413 /* Write the lower 32bits of the physical address to low command
1414 * address scratch register
1415 */
1416 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) {
acebe8c1
ZL		 1417 mwifiex_dbg(adapter, ERROR,
1418 "%s: failed to write download command to boot code.\n",
1419 __func__);
dbccc92b 1420 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1421 return -1;
1422 }
1423
dd04e6ac
AP		 1424 /* Write the upper 32bits of the physical address to high command
1425 * address scratch register
1426 */
1427 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
fc331460 1428 (u32)((u64)buf_pa >> 32))) {
acebe8c1
ZL		 1429 mwifiex_dbg(adapter, ERROR,
1430 "%s: failed to write download command to boot code.\n",
1431 __func__);
dbccc92b 1432 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1433 return -1;
1434 }
1435
dd04e6ac
AP		 1436 /* Write the command length to cmd_size scratch register */
1437 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) {
acebe8c1
ZL		 1438 mwifiex_dbg(adapter, ERROR,
1439 "%s: failed to write command len to cmd_size scratch reg\n",
1440 __func__);
dbccc92b 1441 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1442 return -1;
1443 }
1444
1445 /* Ring the door bell */
1446 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1447 CPU_INTR_DOOR_BELL)) {
acebe8c1
ZL		 1448 mwifiex_dbg(adapter, ERROR,
1449 "%s: failed to assert door-bell intr\n", __func__);
dbccc92b 1450 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1451 return -1;
1452 }
1453
1454 return 0;
1455}
1456
c6d1d87a
AP		 1457/* This function init rx port in firmware which in turn enables to receive data
1458 * from device before transmitting any packet.
1459 */
1460static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter)
1461{
1462 struct pcie_service_card *card = adapter->card;
dd04e6ac 1463 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1464 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask;
c6d1d87a 1465
dd04e6ac 1466 /* Write the RX ring read pointer in to reg->rx_rdptr */
ca8f2112
AP		 1467 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr |
1468 tx_wrap)) {
acebe8c1
ZL		 1469 mwifiex_dbg(adapter, ERROR,
1470 "RECV DATA: failed to write reg->rx_rdptr\n");
c6d1d87a
AP		 1471 return -1;
1472 }
1473 return 0;
1474}
1475
1476/* This function downloads commands to the device
d930faee
AK		 1477 */
1478static int
1479mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1480{
1481 struct pcie_service_card *card = adapter->card;
dd04e6ac 1482 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 1483 int ret = 0;
fc331460
AP		 1484 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa;
1485 u8 *payload = (u8 *)skb->data;
d930faee
AK		 1486
1487 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1488 mwifiex_dbg(adapter, ERROR,
1489 "Invalid parameter in %s <%p, %#x>\n",
1490 __func__, skb->data, skb->len);
d930faee
AK		 1491 return -1;
1492 }
1493
1494 /* Make sure a command response buffer is available */
1495 if (!card->cmdrsp_buf) {
acebe8c1
ZL		 1496 mwifiex_dbg(adapter, ERROR,
1497 "No response buffer available, send command failed\n");
d930faee
AK		 1498 return -EBUSY;
1499 }
1500
fc331460
AP		 1501 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1502 mwifiex_pm_wakeup_card(adapter);
d930faee
AK		 1503
1504 adapter->cmd_sent = true;
fc331460
AP		 1505
1506 *(__le16 *)&payload[0] = cpu_to_le16((u16)skb->len);
1507 *(__le16 *)&payload[2] = cpu_to_le16(MWIFIEX_TYPE_CMD);
1508
1509 if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
1510 return -1;
1511
1512 card->cmd_buf = skb;
d930faee
AK		 1513
1514 /* To send a command, the driver will:
1515 1. Write the 64bit physical address of the data buffer to
dd04e6ac 1516 cmd response address low + cmd response address high
d930faee
AK		 1517 2. Ring the door bell (i.e. set the door bell interrupt)
1518
1519 In response to door bell interrupt, the firmware will perform
1520 the DMA of the command packet (first header to obtain the total
1521 length and then rest of the command).
1522 */
1523
1524 if (card->cmdrsp_buf) {
dbccc92b 1525 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf);
d930faee
AK		 1526 /* Write the lower 32bits of the cmdrsp buffer physical
1527 address */
dd04e6ac 1528 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo,
fc331460 1529 (u32)cmdrsp_buf_pa)) {
acebe8c1
ZL		 1530 mwifiex_dbg(adapter, ERROR,
1531 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1532 ret = -1;
1533 goto done;
1534 }
1535 /* Write the upper 32bits of the cmdrsp buffer physical
1536 address */
dd04e6ac 1537 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi,
fc331460 1538 (u32)((u64)cmdrsp_buf_pa >> 32))) {
acebe8c1
ZL		 1539 mwifiex_dbg(adapter, ERROR,
1540 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1541 ret = -1;
1542 goto done;
1543 }
1544 }
1545
dbccc92b 1546 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf);
dd04e6ac
AP		 1547 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */
1548 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo,
1549 (u32)cmd_buf_pa)) {
acebe8c1
ZL		 1550 mwifiex_dbg(adapter, ERROR,
1551 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1552 ret = -1;
1553 goto done;
1554 }
dd04e6ac
AP		 1555 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */
1556 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
fc331460 1557 (u32)((u64)cmd_buf_pa >> 32))) {
acebe8c1
ZL		 1558 mwifiex_dbg(adapter, ERROR,
1559 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1560 ret = -1;
1561 goto done;
1562 }
1563
dd04e6ac
AP		 1564 /* Write the command length to reg->cmd_size */
1565 if (mwifiex_write_reg(adapter, reg->cmd_size,
1566 card->cmd_buf->len)) {
acebe8c1
ZL		 1567 mwifiex_dbg(adapter, ERROR,
1568 "Failed to write cmd len to reg->cmd_size\n");
d930faee
AK		 1569 ret = -1;
1570 goto done;
1571 }
1572
1573 /* Ring the door bell */
1574 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1575 CPU_INTR_DOOR_BELL)) {
acebe8c1
ZL		 1576 mwifiex_dbg(adapter, ERROR,
1577 "Failed to assert door-bell intr\n");
d930faee
AK		 1578 ret = -1;
1579 goto done;
1580 }
1581
1582done:
1583 if (ret)
1584 adapter->cmd_sent = false;
1585
1586 return 0;
1587}
1588
1589/*
1590 * This function handles command complete interrupt
1591 */
1592static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
1593{
1594 struct pcie_service_card *card = adapter->card;
dd04e6ac 1595 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
f57c1edc 1596 struct sk_buff *skb = card->cmdrsp_buf;
d930faee 1597 int count = 0;
fc331460
AP		 1598 u16 rx_len;
1599 __le16 pkt_len;
d930faee 1600
acebe8c1
ZL		 1601 mwifiex_dbg(adapter, CMD,
1602 "info: Rx CMD Response\n");
d930faee 1603
dbccc92b 1604 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE);
fc331460 1605
189b3299
AD		 1606 /* Unmap the command as a response has been received. */
1607 if (card->cmd_buf) {
1608 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1609 PCI_DMA_TODEVICE);
1610 card->cmd_buf = NULL;
1611 }
1612
fc331460
AP		 1613 pkt_len = *((__le16 *)skb->data);
1614 rx_len = le16_to_cpu(pkt_len);
1615 skb_trim(skb, rx_len);
1616 skb_pull(skb, INTF_HEADER_LEN);
1617
d930faee 1618 if (!adapter->curr_cmd) {
d930faee 1619 if (adapter->ps_state == PS_STATE_SLEEP_CFM) {
f57c1edc
YAP		 1620 mwifiex_process_sleep_confirm_resp(adapter, skb->data,
1621 skb->len);
1c97560f
AK		 1622 mwifiex_pcie_enable_host_int(adapter);
1623 if (mwifiex_write_reg(adapter,
1624 PCIE_CPU_INT_EVENT,
1625 CPU_INTR_SLEEP_CFM_DONE)) {
acebe8c1
ZL		 1626 mwifiex_dbg(adapter, ERROR,
1627 "Write register failed\n");
1c97560f
AK		 1628 return -1;
1629 }
c4bc980f
AP		 1630 mwifiex_delay_for_sleep_cookie(adapter,
1631 MWIFIEX_MAX_DELAY_COUNT);
52301a81
AP		 1632 while (reg->sleep_cookie && (count++ < 10) &&
1633 mwifiex_pcie_ok_to_access_hw(adapter))
e7891ba2 1634 usleep_range(50, 60);
d930faee 1635 } else {
acebe8c1
ZL		 1636 mwifiex_dbg(adapter, ERROR,
1637 "There is no command but got cmdrsp\n");
d930faee 1638 }
f57c1edc
YAP		 1639 memcpy(adapter->upld_buf, skb->data,
1640 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
0f49d64c 1641 skb_push(skb, INTF_HEADER_LEN);
fc331460
AP		 1642 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1643 PCI_DMA_FROMDEVICE))
1644 return -1;
d930faee 1645 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) {
f57c1edc 1646 adapter->curr_cmd->resp_skb = skb;
d930faee
AK		 1647 adapter->cmd_resp_received = true;
1648 /* Take the pointer and set it to CMD node and will
1649 return in the response complete callback */
1650 card->cmdrsp_buf = NULL;
1651
1652 /* Clear the cmd-rsp buffer address in scratch registers. This
1653 will prevent firmware from writing to the same response
1654 buffer again. */
dd04e6ac 1655 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) {
acebe8c1
ZL		 1656 mwifiex_dbg(adapter, ERROR,
1657 "cmd_done: failed to clear cmd_rsp_addr_lo\n");
d930faee
AK		 1658 return -1;
1659 }
1660 /* Write the upper 32bits of the cmdrsp buffer physical
1661 address */
dd04e6ac 1662 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) {
acebe8c1
ZL		 1663 mwifiex_dbg(adapter, ERROR,
1664 "cmd_done: failed to clear cmd_rsp_addr_hi\n");
d930faee
AK		 1665 return -1;
1666 }
1667 }
1668
1669 return 0;
1670}
1671
1672/*
1673 * Command Response processing complete handler
1674 */
1675static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter,
1676 struct sk_buff *skb)
1677{
1678 struct pcie_service_card *card = adapter->card;
1679
1680 if (skb) {
1681 card->cmdrsp_buf = skb;
1682 skb_push(card->cmdrsp_buf, INTF_HEADER_LEN);
fc331460
AP		 1683 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1684 PCI_DMA_FROMDEVICE))
1685 return -1;
1686 }
1687
d930faee
AK		 1688 return 0;
1689}
1690
1691/*
1692 * This function handles firmware event ready interrupt
1693 */
1694static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
1695{
1696 struct pcie_service_card *card = adapter->card;
dd04e6ac 1697 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1698 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
1699 u32 wrptr, event;
e05dc3e9 1700 struct mwifiex_evt_buf_desc *desc;
fc331460
AP		 1701
1702 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1703 mwifiex_pm_wakeup_card(adapter);
d930faee
AK		 1704
1705 if (adapter->event_received) {
acebe8c1
ZL		 1706 mwifiex_dbg(adapter, EVENT,
1707 "info: Event being processed,\t"
1708 "do not process this interrupt just yet\n");
d930faee
AK		 1709 return 0;
1710 }
1711
1712 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
acebe8c1
ZL		 1713 mwifiex_dbg(adapter, ERROR,
1714 "info: Invalid read pointer...\n");
d930faee
AK		 1715 return -1;
1716 }
1717
1718 /* Read the event ring write pointer set by firmware */
dd04e6ac 1719 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
acebe8c1
ZL		 1720 mwifiex_dbg(adapter, ERROR,
1721 "EventReady: failed to read reg->evt_wrptr\n");
d930faee
AK		 1722 return -1;
1723 }
1724
acebe8c1
ZL		 1725 mwifiex_dbg(adapter, EVENT,
1726 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>",
1727 card->evtbd_rdptr, wrptr);
f57c1edc
YAP		 1728 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr
1729 & MWIFIEX_EVTBD_MASK)) ||
dd04e6ac
AP		 1730 ((wrptr & reg->evt_rollover_ind) ==
1731 (card->evtbd_rdptr & reg->evt_rollover_ind))) {
d930faee
AK		 1732 struct sk_buff *skb_cmd;
1733 __le16 data_len = 0;
1734 u16 evt_len;
1735
acebe8c1
ZL		 1736 mwifiex_dbg(adapter, INFO,
1737 "info: Read Index: %d\n", rdptr);
d930faee 1738 skb_cmd = card->evt_buf_list[rdptr];
dbccc92b 1739 mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE);
fc331460 1740
d930faee
AK		 1741 /* Take the pointer and set it to event pointer in adapter
1742 and will return back after event handling callback */
1743 card->evt_buf_list[rdptr] = NULL;
e05dc3e9
AP		 1744 desc = card->evtbd_ring[rdptr];
1745 memset(desc, 0, sizeof(*desc));
d930faee
AK		 1746
1747 event = *(u32 *) &skb_cmd->data[INTF_HEADER_LEN];
1748 adapter->event_cause = event;
1749 /* The first 4bytes will be the event transfer header
1750 len is 2 bytes followed by type which is 2 bytes */
1751 memcpy(&data_len, skb_cmd->data, sizeof(__le16));
1752 evt_len = le16_to_cpu(data_len);
868093a9 1753 skb_trim(skb_cmd, evt_len);
d930faee 1754 skb_pull(skb_cmd, INTF_HEADER_LEN);
acebe8c1
ZL		 1755 mwifiex_dbg(adapter, EVENT,
1756 "info: Event length: %d\n", evt_len);
d930faee
AK		 1757
1758 if ((evt_len > 0) && (evt_len < MAX_EVENT_SIZE))
1759 memcpy(adapter->event_body, skb_cmd->data +
1760 MWIFIEX_EVENT_HEADER_LEN, evt_len -
1761 MWIFIEX_EVENT_HEADER_LEN);
1762
1763 adapter->event_received = true;
1764 adapter->event_skb = skb_cmd;
1765
1766 /* Do not update the event read pointer here, wait till the
1767 buffer is released. This is just to make things simpler,
1768 we need to find a better method of managing these buffers.
1769 */
2703a668
AP		 1770 } else {
1771 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1772 CPU_INTR_EVENT_DONE)) {
acebe8c1
ZL		 1773 mwifiex_dbg(adapter, ERROR,
1774 "Write register failed\n");
2703a668
AP		 1775 return -1;
1776 }
d930faee
AK		 1777 }
1778
1779 return 0;
1780}
1781
1782/*
1783 * Event processing complete handler
1784 */
1785static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter,
1786 struct sk_buff *skb)
1787{
1788 struct pcie_service_card *card = adapter->card;
dd04e6ac 1789 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1790 int ret = 0;
1791 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
1792 u32 wrptr;
e05dc3e9 1793 struct mwifiex_evt_buf_desc *desc;
d930faee
AK		 1794
1795 if (!skb)
1796 return 0;
1797
1eb54c8a 1798 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
acebe8c1
ZL		 1799 mwifiex_dbg(adapter, ERROR,
1800 "event_complete: Invalid rdptr 0x%x\n",
1801 rdptr);
8c53e42d 1802 return -EINVAL;
1eb54c8a 1803 }
d930faee
AK		 1804
1805 /* Read the event ring write pointer set by firmware */
dd04e6ac 1806 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
acebe8c1
ZL		 1807 mwifiex_dbg(adapter, ERROR,
1808 "event_complete: failed to read reg->evt_wrptr\n");
8c53e42d 1809 return -1;
d930faee
AK		 1810 }
1811
1812 if (!card->evt_buf_list[rdptr]) {
1813 skb_push(skb, INTF_HEADER_LEN);
2728cecd 1814 skb_put(skb, MAX_EVENT_SIZE - skb->len);
fc331460
AP		 1815 if (mwifiex_map_pci_memory(adapter, skb,
1816 MAX_EVENT_SIZE,
1817 PCI_DMA_FROMDEVICE))
1818 return -1;
d930faee 1819 card->evt_buf_list[rdptr] = skb;
e05dc3e9 1820 desc = card->evtbd_ring[rdptr];
dbccc92b 1821 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb);
e05dc3e9
AP		 1822 desc->len = (u16)skb->len;
1823 desc->flags = 0;
d930faee
AK		 1824 skb = NULL;
1825 } else {
acebe8c1
ZL		 1826 mwifiex_dbg(adapter, ERROR,
1827 "info: ERROR: buf still valid at index %d, <%p, %p>\n",
1828 rdptr, card->evt_buf_list[rdptr], skb);
d930faee
AK		 1829 }
1830
1831 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) {
1832 card->evtbd_rdptr = ((card->evtbd_rdptr &
dd04e6ac
AP		 1833 reg->evt_rollover_ind) ^
1834 reg->evt_rollover_ind);
d930faee
AK		 1835 }
1836
acebe8c1
ZL		 1837 mwifiex_dbg(adapter, EVENT,
1838 "info: Updated <Rd: 0x%x, Wr: 0x%x>",
1839 card->evtbd_rdptr, wrptr);
d930faee 1840
dd04e6ac
AP		 1841 /* Write the event ring read pointer in to reg->evt_rdptr */
1842 if (mwifiex_write_reg(adapter, reg->evt_rdptr,
1843 card->evtbd_rdptr)) {
acebe8c1
ZL		 1844 mwifiex_dbg(adapter, ERROR,
1845 "event_complete: failed to read reg->evt_rdptr\n");
8c53e42d 1846 return -1;
d930faee
AK		 1847 }
1848
acebe8c1
ZL		 1849 mwifiex_dbg(adapter, EVENT,
1850 "info: Check Events Again\n");
d930faee
AK		 1851 ret = mwifiex_pcie_process_event_ready(adapter);
1852
1853 return ret;
1854}
1855
1856/*
1857 * This function downloads the firmware to the card.
1858 *
1859 * Firmware is downloaded to the card in blocks. Every block download
1860 * is tested for CRC errors, and retried a number of times before
1861 * returning failure.
1862 */
1863static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter,
1864 struct mwifiex_fw_image *fw)
1865{
1866 int ret;
1867 u8 *firmware = fw->fw_buf;
1868 u32 firmware_len = fw->fw_len;
1869 u32 offset = 0;
1870 struct sk_buff *skb;
1871 u32 txlen, tx_blocks = 0, tries, len;
1872 u32 block_retry_cnt = 0;
fc331460 1873 struct pcie_service_card *card = adapter->card;
dd04e6ac 1874 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1875
1876 if (!firmware || !firmware_len) {
acebe8c1
ZL		 1877 mwifiex_dbg(adapter, ERROR,
1878 "No firmware image found! Terminating download\n");
d930faee
AK		 1879 return -1;
1880 }
1881
acebe8c1
ZL		 1882 mwifiex_dbg(adapter, INFO,
1883 "info: Downloading FW image (%d bytes)\n",
1884 firmware_len);
d930faee
AK		 1885
1886 if (mwifiex_pcie_disable_host_int(adapter)) {
acebe8c1
ZL		 1887 mwifiex_dbg(adapter, ERROR,
1888 "%s: Disabling interrupts failed.\n", __func__);
d930faee
AK		 1889 return -1;
1890 }
1891
1892 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
1893 if (!skb) {
1894 ret = -ENOMEM;
1895 goto done;
1896 }
d930faee
AK		 1897
1898 /* Perform firmware data transfer */
1899 do {
1900 u32 ireg_intr = 0;
1901
1902 /* More data? */
1903 if (offset >= firmware_len)
1904 break;
1905
1906 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
dd04e6ac 1907 ret = mwifiex_read_reg(adapter, reg->cmd_size,
d930faee
AK		 1908 &len);
1909 if (ret) {
acebe8c1
ZL		 1910 mwifiex_dbg(adapter, FATAL,
1911 "Failed reading len from boot code\n");
d930faee
AK		 1912 goto done;
1913 }
1914 if (len)
1915 break;
e7891ba2 1916 usleep_range(10, 20);
d930faee
AK		 1917 }
1918
1919 if (!len) {
1920 break;
1921 } else if (len > MWIFIEX_UPLD_SIZE) {
acebe8c1
ZL		 1922 mwifiex_dbg(adapter, ERROR,
1923 "FW download failure @ %d, invalid length %d\n",
1924 offset, len);
d930faee
AK		 1925 ret = -1;
1926 goto done;
1927 }
1928
1929 txlen = len;
1930
1931 if (len & BIT(0)) {
1932 block_retry_cnt++;
1933 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) {
acebe8c1
ZL		 1934 mwifiex_dbg(adapter, ERROR,
1935 "FW download failure @ %d, over max\t"
1936 "retry count\n", offset);
d930faee
AK		 1937 ret = -1;
1938 goto done;
1939 }
acebe8c1
ZL		 1940 mwifiex_dbg(adapter, ERROR,
1941 "FW CRC error indicated by the\t"
1942 "helper: len = 0x%04X, txlen = %d\n",
1943 len, txlen);
d930faee
AK		 1944 len &= ~BIT(0);
1945 /* Setting this to 0 to resend from same offset */
1946 txlen = 0;
1947 } else {
1948 block_retry_cnt = 0;
1949 /* Set blocksize to transfer - checking for
1950 last block */
1951 if (firmware_len - offset < txlen)
1952 txlen = firmware_len - offset;
1953
acebe8c1 1954 mwifiex_dbg(adapter, INFO, ".");
d930faee 1955
dd04e6ac
AP		 1956 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) /
1957 card->pcie.blksz_fw_dl;
d930faee
AK		 1958
1959 /* Copy payload to buffer */
1960 memmove(skb->data, &firmware[offset], txlen);
1961 }
1962
1963 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
dd04e6ac 1964 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl);
d930faee
AK		 1965
1966 /* Send the boot command to device */
1967 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) {
acebe8c1
ZL		 1968 mwifiex_dbg(adapter, ERROR,
1969 "Failed to send firmware download command\n");
d930faee
AK		 1970 ret = -1;
1971 goto done;
1972 }
fc331460 1973
d930faee
AK		 1974 /* Wait for the command done interrupt */
1975 do {
1976 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS,
1977 &ireg_intr)) {
acebe8c1
ZL		 1978 mwifiex_dbg(adapter, ERROR,
1979 "%s: Failed to read\t"
1980 "interrupt status during fw dnld.\n",
1981 __func__);
dbccc92b
AD		 1982 mwifiex_unmap_pci_memory(adapter, skb,
1983 PCI_DMA_TODEVICE);
d930faee
AK		 1984 ret = -1;
1985 goto done;
1986 }
1987 } while ((ireg_intr & CPU_INTR_DOOR_BELL) ==
1988 CPU_INTR_DOOR_BELL);
fc331460 1989
dbccc92b 1990 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
fc331460 1991
d930faee
AK		 1992 offset += txlen;
1993 } while (true);
1994
acebe8c1
ZL		 1995 mwifiex_dbg(adapter, MSG,
1996 "info: FW download over, size %d bytes\n", offset);
d930faee
AK		 1997
1998 ret = 0;
1999
2000done:
2001 dev_kfree_skb_any(skb);
2002 return ret;
2003}
2004
2005/*
2006 * This function checks the firmware status in card.
d930faee
AK		 2007 */
2008static int
2009mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num)
2010{
2011 int ret = 0;
2fd5c6ed 2012 u32 firmware_stat;
dd04e6ac
AP		 2013 struct pcie_service_card *card = adapter->card;
2014 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 2015 u32 tries;
2016
2017 /* Mask spurios interrupts */
2018 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK,
f57c1edc 2019 HOST_INTR_MASK)) {
acebe8c1
ZL		 2020 mwifiex_dbg(adapter, ERROR,
2021 "Write register failed\n");
d930faee
AK		 2022 return -1;
2023 }
2024
acebe8c1
ZL		 2025 mwifiex_dbg(adapter, INFO,
2026 "Setting driver ready signature\n");
dd04e6ac
AP		 2027 if (mwifiex_write_reg(adapter, reg->drv_rdy,
2028 FIRMWARE_READY_PCIE)) {
acebe8c1
ZL		 2029 mwifiex_dbg(adapter, ERROR,
2030 "Failed to write driver ready signature\n");
d930faee
AK		 2031 return -1;
2032 }
2033
2034 /* Wait for firmware initialization event */
2035 for (tries = 0; tries < poll_num; tries++) {
dd04e6ac 2036 if (mwifiex_read_reg(adapter, reg->fw_status,
d930faee
AK		 2037 &firmware_stat))
2038 ret = -1;
2039 else
2040 ret = 0;
2041 if (ret)
2042 continue;
2043 if (firmware_stat == FIRMWARE_READY_PCIE) {
2044 ret = 0;
2045 break;
2046 } else {
a76b20e5 2047 msleep(100);
d930faee
AK		 2048 ret = -1;
2049 }
2050 }
2051
2fd5c6ed 2052 return ret;
2053}
2054
2055/* This function checks if WLAN is the winner.
2056 */
2057static int
2058mwifiex_check_winner_status(struct mwifiex_adapter *adapter)
2059{
2060 u32 winner = 0;
2061 int ret = 0;
2062 struct pcie_service_card *card = adapter->card;
2063 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2064
2065 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) {
2066 ret = -1;
2067 } else if (!winner) {
2068 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n");
2069 adapter->winner = 1;
2070 } else {
2071 mwifiex_dbg(adapter, ERROR,
2072 "PCI-E is not the winner <%#x,%d>, exit dnld\n",
2073 ret, adapter->winner);
d930faee
AK		 2074 }
2075
2076 return ret;
2077}
2078
2079/*
2080 * This function reads the interrupt status from card.
2081 */
99074fc1
XH		 2082static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter,
2083 int msg_id)
d930faee
AK		 2084{
2085 u32 pcie_ireg;
2086 unsigned long flags;
99074fc1 2087 struct pcie_service_card *card = adapter->card;
d930faee
AK		 2088
2089 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2090 return;
2091
99074fc1
XH		 2092 if (card->msix_enable && msg_id >= 0) {
2093 pcie_ireg = BIT(msg_id);
2094 } else {
2095 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2096 &pcie_ireg)) {
2097 mwifiex_dbg(adapter, ERROR, "Read register failed\n");
2098 return;
2099 }
2100
2101 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg)
2102 return;
d930faee 2103
d930faee
AK		 2104
2105 mwifiex_pcie_disable_host_int(adapter);
2106
2107 /* Clear the pending interrupts */
2108 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS,
2109 ~pcie_ireg)) {
acebe8c1
ZL		 2110 mwifiex_dbg(adapter, ERROR,
2111 "Write register failed\n");
d930faee
AK		 2112 return;
2113 }
99074fc1
XH		 2114 }
2115
99074fc1
XH		 2116 if (!adapter->pps_uapsd_mode &&
2117 adapter->ps_state == PS_STATE_SLEEP &&
2118 mwifiex_pcie_ok_to_access_hw(adapter)) {
2119 /* Potentially for PCIe we could get other
2120 * interrupts like shared. Don't change power
2121 * state until cookie is set
2122 */
2123 adapter->ps_state = PS_STATE_AWAKE;
2124 adapter->pm_wakeup_fw_try = false;
2125 del_timer(&adapter->wakeup_timer);
d930faee 2126 }
dc896b15
SL		 2127
2128 spin_lock_irqsave(&adapter->int_lock, flags);
2129 adapter->int_status |= pcie_ireg;
2130 spin_unlock_irqrestore(&adapter->int_lock, flags);
2131 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg);
d930faee
AK		 2132}
2133
2134/*
2135 * Interrupt handler for PCIe root port
2136 *
2137 * This function reads the interrupt status from firmware and assigns
2138 * the main process in workqueue which will handle the interrupt.
2139 */
2140static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context)
2141{
99074fc1
XH		 2142 struct mwifiex_msix_context *ctx = context;
2143 struct pci_dev *pdev = ctx->dev;
d930faee
AK		 2144 struct pcie_service_card *card;
2145 struct mwifiex_adapter *adapter;
2146
2147 if (!pdev) {
91442431 2148 pr_err("info: %s: pdev is NULL\n", __func__);
d930faee
AK		 2149 goto exit;
2150 }
2151
b2a31204 2152 card = pci_get_drvdata(pdev);
d930faee 2153 if (!card || !card->adapter) {
91442431
XH		 2154 pr_err("info: %s: card=%p adapter=%p\n", __func__, card,
2155 card ? card->adapter : NULL);
d930faee
AK		 2156 goto exit;
2157 }
2158 adapter = card->adapter;
2159
2160 if (adapter->surprise_removed)
2161 goto exit;
2162
99074fc1
XH		 2163 if (card->msix_enable)
2164 mwifiex_interrupt_status(adapter, ctx->msg_id);
2165 else
2166 mwifiex_interrupt_status(adapter, -1);
2167
b2713f67 2168 mwifiex_queue_main_work(adapter);
d930faee
AK		 2169
2170exit:
2171 return IRQ_HANDLED;
2172}
2173
2174/*
2175 * This function checks the current interrupt status.
2176 *
2177 * The following interrupts are checked and handled by this function -
2178 * - Data sent
2179 * - Command sent
2180 * - Command received
2181 * - Packets received
2182 * - Events received
2183 *
2184 * In case of Rx packets received, the packets are uploaded from card to
2185 * host and processed accordingly.
2186 */
99074fc1 2187static int mwifiex_process_pcie_int(struct mwifiex_adapter *adapter)
d930faee
AK		 2188{
2189 int ret;
659c4788 2190 u32 pcie_ireg;
d930faee
AK		 2191 unsigned long flags;
2192
2193 spin_lock_irqsave(&adapter->int_lock, flags);
2194 /* Clear out unused interrupts */
659c4788
AP		 2195 pcie_ireg = adapter->int_status;
2196 adapter->int_status = 0;
d930faee
AK		 2197 spin_unlock_irqrestore(&adapter->int_lock, flags);
2198
659c4788
AP		 2199 while (pcie_ireg & HOST_INTR_MASK) {
2200 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2201 pcie_ireg &= ~HOST_INTR_DNLD_DONE;
acebe8c1
ZL		 2202 mwifiex_dbg(adapter, INTR,
2203 "info: TX DNLD Done\n");
e7f767a7
AP		 2204 ret = mwifiex_pcie_send_data_complete(adapter);
2205 if (ret)
2206 return ret;
d930faee 2207 }
659c4788
AP		 2208 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2209 pcie_ireg &= ~HOST_INTR_UPLD_RDY;
acebe8c1
ZL		 2210 mwifiex_dbg(adapter, INTR,
2211 "info: Rx DATA\n");
d930faee
AK		 2212 ret = mwifiex_pcie_process_recv_data(adapter);
2213 if (ret)
2214 return ret;
2215 }
659c4788
AP		 2216 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2217 pcie_ireg &= ~HOST_INTR_EVENT_RDY;
acebe8c1
ZL		 2218 mwifiex_dbg(adapter, INTR,
2219 "info: Rx EVENT\n");
d930faee
AK		 2220 ret = mwifiex_pcie_process_event_ready(adapter);
2221 if (ret)
2222 return ret;
2223 }
2224
659c4788
AP		 2225 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2226 pcie_ireg &= ~HOST_INTR_CMD_DONE;
d930faee 2227 if (adapter->cmd_sent) {
acebe8c1
ZL		 2228 mwifiex_dbg(adapter, INTR,
2229 "info: CMD sent Interrupt\n");
d930faee
AK		 2230 adapter->cmd_sent = false;
2231 }
2232 /* Handle command response */
2233 ret = mwifiex_pcie_process_cmd_complete(adapter);
2234 if (ret)
2235 return ret;
2236 }
2237
2238 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
2239 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2240 &pcie_ireg)) {
acebe8c1
ZL		 2241 mwifiex_dbg(adapter, ERROR,
2242 "Read register failed\n");
d930faee
AK		 2243 return -1;
2244 }
2245
2246 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
2247 if (mwifiex_write_reg(adapter,
f57c1edc
YAP		 2248 PCIE_HOST_INT_STATUS,
2249 ~pcie_ireg)) {
acebe8c1
ZL		 2250 mwifiex_dbg(adapter, ERROR,
2251 "Write register failed\n");
d930faee
AK		 2252 return -1;
2253 }
d930faee
AK		 2254 }
2255
2256 }
2257 }
acebe8c1
ZL		 2258 mwifiex_dbg(adapter, INTR,
2259 "info: cmd_sent=%d data_sent=%d\n",
2260 adapter->cmd_sent, adapter->data_sent);
b2fda1f6
AP		 2261 if (adapter->ps_state != PS_STATE_SLEEP)
2262 mwifiex_pcie_enable_host_int(adapter);
d930faee
AK		 2263
2264 return 0;
2265}
2266
99074fc1
XH		 2267static int mwifiex_process_msix_int(struct mwifiex_adapter *adapter)
2268{
2269 int ret;
2270 u32 pcie_ireg;
2271 unsigned long flags;
2272
2273 spin_lock_irqsave(&adapter->int_lock, flags);
2274 /* Clear out unused interrupts */
2275 pcie_ireg = adapter->int_status;
2276 adapter->int_status = 0;
2277 spin_unlock_irqrestore(&adapter->int_lock, flags);
2278
2279 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2280 mwifiex_dbg(adapter, INTR,
2281 "info: TX DNLD Done\n");
2282 ret = mwifiex_pcie_send_data_complete(adapter);
2283 if (ret)
2284 return ret;
2285 }
2286 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2287 mwifiex_dbg(adapter, INTR,
2288 "info: Rx DATA\n");
2289 ret = mwifiex_pcie_process_recv_data(adapter);
2290 if (ret)
2291 return ret;
2292 }
2293 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2294 mwifiex_dbg(adapter, INTR,
2295 "info: Rx EVENT\n");
2296 ret = mwifiex_pcie_process_event_ready(adapter);
2297 if (ret)
2298 return ret;
2299 }
2300
2301 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2302 if (adapter->cmd_sent) {
2303 mwifiex_dbg(adapter, INTR,
2304 "info: CMD sent Interrupt\n");
2305 adapter->cmd_sent = false;
2306 }
2307 /* Handle command response */
2308 ret = mwifiex_pcie_process_cmd_complete(adapter);
2309 if (ret)
2310 return ret;
2311 }
2312
2313 mwifiex_dbg(adapter, INTR,
2314 "info: cmd_sent=%d data_sent=%d\n",
2315 adapter->cmd_sent, adapter->data_sent);
2316
2317 return 0;
2318}
2319
2320static int mwifiex_process_int_status(struct mwifiex_adapter *adapter)
2321{
2322 struct pcie_service_card *card = adapter->card;
2323
2324 if (card->msix_enable)
2325 return mwifiex_process_msix_int(adapter);
2326 else
2327 return mwifiex_process_pcie_int(adapter);
2328}
2329
d930faee
AK		 2330/*
2331 * This function downloads data from driver to card.
2332 *
2333 * Both commands and data packets are transferred to the card by this
2334 * function.
2335 *
2336 * This function adds the PCIE specific header to the front of the buffer
2337 * before transferring. The header contains the length of the packet and
2338 * the type. The firmware handles the packets based upon this set type.
2339 */
2340static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type,
2341 struct sk_buff *skb,
2342 struct mwifiex_tx_param *tx_param)
2343{
fa161cb7 2344 if (!skb) {
acebe8c1
ZL		 2345 mwifiex_dbg(adapter, ERROR,
2346 "Passed NULL skb to %s\n", __func__);
d930faee
AK		 2347 return -1;
2348 }
2349
2350 if (type == MWIFIEX_TYPE_DATA)
e7f767a7 2351 return mwifiex_pcie_send_data(adapter, skb, tx_param);
d930faee
AK		 2352 else if (type == MWIFIEX_TYPE_CMD)
2353 return mwifiex_pcie_send_cmd(adapter, skb);
2354
2355 return 0;
2356}
2357
4646968b
XH		 2358/* Function to dump PCIE scratch registers in case of FW crash
2359 */
2360static int
2361mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf)
2362{
2363 char *p = drv_buf;
2364 char buf[256], *ptr;
2365 int i;
2366 u32 value;
2367 struct pcie_service_card *card = adapter->card;
2368 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2369 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG,
2370 PCIE_SCRATCH_13_REG,
2371 PCIE_SCRATCH_14_REG};
2372
2373 if (!p)
2374 return 0;
2375
2376 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n");
2377
2378 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) {
2379 mwifiex_dbg(adapter, ERROR, "failed to read firmware status");
2380 return 0;
2381 }
2382
2383 ptr = buf;
2384 mwifiex_dbg(adapter, MSG, "pcie scratch register:");
2385 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) {
2386 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value);
2387 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n",
2388 pcie_scratch_reg[i], value);
2389 }
2390
2391 mwifiex_dbg(adapter, MSG, "%s\n", buf);
2392 p += sprintf(p, "%s\n", buf);
2393
2394 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n");
2395
2396 return p - drv_buf;
2397}
2398
92c2538f
AK		 2399/* This function read/write firmware */
2400static enum rdwr_status
2401mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag)
2402{
2403 int ret, tries;
2404 u8 ctrl_data;
0172404d 2405 u32 fw_status;
92c2538f
AK		 2406 struct pcie_service_card *card = adapter->card;
2407 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2408
0172404d
XH		 2409 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status))
2410 return RDWR_STATUS_FAILURE;
2411
50632092
XH		 2412 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2413 reg->fw_dump_host_ready);
92c2538f 2414 if (ret) {
acebe8c1
ZL		 2415 mwifiex_dbg(adapter, ERROR,
2416 "PCIE write err\n");
92c2538f
AK		 2417 return RDWR_STATUS_FAILURE;
2418 }
2419
2420 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2421 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data);
2422 if (ctrl_data == FW_DUMP_DONE)
2423 return RDWR_STATUS_SUCCESS;
2424 if (doneflag && ctrl_data == doneflag)
2425 return RDWR_STATUS_DONE;
50632092 2426 if (ctrl_data != reg->fw_dump_host_ready) {
acebe8c1
ZL		 2427 mwifiex_dbg(adapter, WARN,
2428 "The ctrl reg was changed, re-try again!\n");
24716876 2429 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
50632092 2430 reg->fw_dump_host_ready);
92c2538f 2431 if (ret) {
acebe8c1
ZL		 2432 mwifiex_dbg(adapter, ERROR,
2433 "PCIE write err\n");
92c2538f
AK		 2434 return RDWR_STATUS_FAILURE;
2435 }
2436 }
2437 usleep_range(100, 200);
2438 }
2439
acebe8c1 2440 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n");
92c2538f
AK		 2441 return RDWR_STATUS_FAILURE;
2442}
2443
2444/* This function dump firmware memory to file */
fc697159 2445static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter)
92c2538f
AK		 2446{
2447 struct pcie_service_card *card = adapter->card;
2448 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg;
2449 unsigned int reg, reg_start, reg_end;
11e70824 2450 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num;
56486026 2451 u8 idx, i, read_reg, doneflag = 0;
92c2538f
AK		 2452 enum rdwr_status stat;
2453 u32 memory_size;
24716876 2454 int ret;
92c2538f 2455
b4e8aebb 2456 if (!card->pcie.can_dump_fw)
92c2538f
AK		 2457 return;
2458
50632092
XH		 2459 for (idx = 0; idx < adapter->num_mem_types; idx++) {
2460 struct memory_type_mapping *entry =
2461 &adapter->mem_type_mapping_tbl[idx];
92c2538f
AK		 2462
2463 if (entry->mem_ptr) {
2464 vfree(entry->mem_ptr);
2465 entry->mem_ptr = NULL;
2466 }
2467 entry->mem_size = 0;
2468 }
2469
03f0f7cd 2470 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n");
92c2538f
AK		 2471
2472 /* Read the number of the memories which will dump */
2473 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2474 if (stat == RDWR_STATUS_FAILURE)
57670ee8 2475 return;
92c2538f
AK		 2476
2477 reg = creg->fw_dump_start;
11e70824
XH		 2478 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num);
2479
2480 /* W8997 chipset firmware dump will be restore in single region*/
2481 if (fw_dump_num == 0)
2482 dump_num = 1;
2483 else
2484 dump_num = fw_dump_num;
92c2538f
AK		 2485
2486 /* Read the length of every memory which will dump */
2487 for (idx = 0; idx < dump_num; idx++) {
50632092
XH		 2488 struct memory_type_mapping *entry =
2489 &adapter->mem_type_mapping_tbl[idx];
92c2538f 2490 memory_size = 0;
11e70824
XH		 2491 if (fw_dump_num != 0) {
2492 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2493 if (stat == RDWR_STATUS_FAILURE)
2494 return;
2495
2496 reg = creg->fw_dump_start;
2497 for (i = 0; i < 4; i++) {
2498 mwifiex_read_reg_byte(adapter, reg, &read_reg);
2499 memory_size |= (read_reg << (i * 8));
ccf5fa4f 2500 reg++;
11e70824
XH		 2501 }
2502 } else {
2503 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE;
92c2538f
AK		 2504 }
2505
2506 if (memory_size == 0) {
acebe8c1 2507 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n");
7e174833 2508 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl,
50632092 2509 creg->fw_dump_read_done);
7e174833 2510 if (ret) {
acebe8c1 2511 mwifiex_dbg(adapter, ERROR, "PCIE write err\n");
57670ee8 2512 return;
7e174833 2513 }
92c2538f
AK		 2514 break;
2515 }
2516
acebe8c1
ZL		 2517 mwifiex_dbg(adapter, DUMP,
2518 "%s_SIZE=0x%x\n", entry->mem_name, memory_size);
92c2538f
AK		 2519 entry->mem_ptr = vmalloc(memory_size + 1);
2520 entry->mem_size = memory_size;
2521 if (!entry->mem_ptr) {
acebe8c1
ZL		 2522 mwifiex_dbg(adapter, ERROR,
2523 "Vmalloc %s failed\n", entry->mem_name);
57670ee8 2524 return;
92c2538f
AK		 2525 }
2526 dbg_ptr = entry->mem_ptr;
2527 end_ptr = dbg_ptr + memory_size;
2528
2529 doneflag = entry->done_flag;
acebe8c1
ZL		 2530 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n",
2531 entry->mem_name);
92c2538f
AK		 2532
2533 do {
2534 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2535 if (RDWR_STATUS_FAILURE == stat)
57670ee8 2536 return;
92c2538f
AK		 2537
2538 reg_start = creg->fw_dump_start;
2539 reg_end = creg->fw_dump_end;
2540 for (reg = reg_start; reg <= reg_end; reg++) {
2541 mwifiex_read_reg_byte(adapter, reg, dbg_ptr);
24716876 2542 if (dbg_ptr < end_ptr) {
92c2538f 2543 dbg_ptr++;
56486026 2544 continue;
24716876 2545 }
56486026
XH		 2546 mwifiex_dbg(adapter, ERROR,
2547 "pre-allocated buf not enough\n");
2548 tmp_ptr =
2549 vzalloc(memory_size + MWIFIEX_SIZE_4K);
2550 if (!tmp_ptr)
2551 return;
2552 memcpy(tmp_ptr, entry->mem_ptr, memory_size);
2553 vfree(entry->mem_ptr);
2554 entry->mem_ptr = tmp_ptr;
2555 tmp_ptr = NULL;
2556 dbg_ptr = entry->mem_ptr + memory_size;
2557 memory_size += MWIFIEX_SIZE_4K;
2558 end_ptr = entry->mem_ptr + memory_size;
92c2538f
AK		 2559 }
2560
2561 if (stat != RDWR_STATUS_DONE)
2562 continue;
2563
acebe8c1
ZL		 2564 mwifiex_dbg(adapter, DUMP,
2565 "%s done: size=0x%tx\n",
2566 entry->mem_name, dbg_ptr - entry->mem_ptr);
92c2538f
AK		 2567 break;
2568 } while (true);
2569 }
03f0f7cd 2570 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n");
92c2538f
AK		 2571}
2572
fc697159
AK		 2573static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter)
2574{
2575 mwifiex_drv_info_dump(adapter);
2576 mwifiex_pcie_fw_dump(adapter);
57670ee8 2577 mwifiex_upload_device_dump(adapter);
fc697159
AK		 2578}
2579
2f5872b6
MH		 2580static unsigned long iface_work_flags;
2581static struct mwifiex_adapter *save_adapter;
92c2538f
AK		 2582static void mwifiex_pcie_work(struct work_struct *work)
2583{
fc697159 2584 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
2f5872b6 2585 &iface_work_flags))
fc697159 2586 mwifiex_pcie_device_dump_work(save_adapter);
92c2538f
AK		 2587}
2588
2f5872b6 2589static DECLARE_WORK(pcie_work, mwifiex_pcie_work);
92c2538f 2590/* This function dumps FW information */
fc697159 2591static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter)
92c2538f 2592{
2f5872b6 2593 save_adapter = adapter;
fc697159 2594 if (test_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &iface_work_flags))
92c2538f
AK		 2595 return;
2596
fc697159 2597 set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &iface_work_flags);
92c2538f 2598
2f5872b6 2599 schedule_work(&pcie_work);
92c2538f
AK		 2600}
2601
d930faee
AK		 2602/*
2603 * This function initializes the PCI-E host memory space, WCB rings, etc.
2604 *
2605 * The following initializations steps are followed -
2606 * - Allocate TXBD ring buffers
2607 * - Allocate RXBD ring buffers
2608 * - Allocate event BD ring buffers
2609 * - Allocate command response ring buffer
2610 * - Allocate sleep cookie buffer
2611 */
2612static int mwifiex_pcie_init(struct mwifiex_adapter *adapter)
2613{
2614 struct pcie_service_card *card = adapter->card;
2615 int ret;
2616 struct pci_dev *pdev = card->dev;
52301a81 2617 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 2618
2619 pci_set_drvdata(pdev, card);
2620
2621 ret = pci_enable_device(pdev);
2622 if (ret)
2623 goto err_enable_dev;
2624
2625 pci_set_master(pdev);
2626
fdb1e28e 2627 pr_notice("try set_consistent_dma_mask(32)\n");
d930faee
AK		 2628 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2629 if (ret) {
fdb1e28e 2630 pr_err("set_dma_mask(32) failed\n");
d930faee
AK		 2631 goto err_set_dma_mask;
2632 }
2633
2634 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2635 if (ret) {
fdb1e28e 2636 pr_err("set_consistent_dma_mask(64) failed\n");
d930faee
AK		 2637 goto err_set_dma_mask;
2638 }
2639
2640 ret = pci_request_region(pdev, 0, DRV_NAME);
2641 if (ret) {
fdb1e28e 2642 pr_err("req_reg(0) error\n");
d930faee
AK		 2643 goto err_req_region0;
2644 }
2645 card->pci_mmap = pci_iomap(pdev, 0, 0);
2646 if (!card->pci_mmap) {
fdb1e28e 2647 pr_err("iomap(0) error\n");
3220712d 2648 ret = -EIO;
d930faee
AK		 2649 goto err_iomap0;
2650 }
2651 ret = pci_request_region(pdev, 2, DRV_NAME);
2652 if (ret) {
fdb1e28e 2653 pr_err("req_reg(2) error\n");
d930faee
AK		 2654 goto err_req_region2;
2655 }
2656 card->pci_mmap1 = pci_iomap(pdev, 2, 0);
2657 if (!card->pci_mmap1) {
fdb1e28e 2658 pr_err("iomap(2) error\n");
3220712d 2659 ret = -EIO;
d930faee
AK		 2660 goto err_iomap2;
2661 }
2662
fdb1e28e
XH		 2663 pr_notice("PCI memory map Virt0: %p PCI memory map Virt2: %p\n",
2664 card->pci_mmap, card->pci_mmap1);
d930faee
AK		 2665
2666 card->cmdrsp_buf = NULL;
2667 ret = mwifiex_pcie_create_txbd_ring(adapter);
2668 if (ret)
2669 goto err_cre_txbd;
2670 ret = mwifiex_pcie_create_rxbd_ring(adapter);
2671 if (ret)
2672 goto err_cre_rxbd;
2673 ret = mwifiex_pcie_create_evtbd_ring(adapter);
2674 if (ret)
2675 goto err_cre_evtbd;
2676 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter);
2677 if (ret)
2678 goto err_alloc_cmdbuf;
52301a81
AP		 2679 if (reg->sleep_cookie) {
2680 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter);
2681 if (ret)
2682 goto err_alloc_cookie;
2683 } else {
2684 card->sleep_cookie_vbase = NULL;
2685 }
d930faee
AK		 2686 return ret;
2687
2688err_alloc_cookie:
2689 mwifiex_pcie_delete_cmdrsp_buf(adapter);
2690err_alloc_cmdbuf:
2691 mwifiex_pcie_delete_evtbd_ring(adapter);
2692err_cre_evtbd:
2693 mwifiex_pcie_delete_rxbd_ring(adapter);
2694err_cre_rxbd:
2695 mwifiex_pcie_delete_txbd_ring(adapter);
2696err_cre_txbd:
2697 pci_iounmap(pdev, card->pci_mmap1);
2698err_iomap2:
2699 pci_release_region(pdev, 2);
2700err_req_region2:
2701 pci_iounmap(pdev, card->pci_mmap);
2702err_iomap0:
2703 pci_release_region(pdev, 0);
2704err_req_region0:
2705err_set_dma_mask:
2706 pci_disable_device(pdev);
2707err_enable_dev:
2708 pci_set_drvdata(pdev, NULL);
2709 return ret;
2710}
2711
2712/*
2713 * This function cleans up the allocated card buffers.
2714 *
2715 * The following are freed by this function -
2716 * - TXBD ring buffers
2717 * - RXBD ring buffers
2718 * - Event BD ring buffers
2719 * - Command response ring buffer
2720 * - Sleep cookie buffer
2721 */
2722static void mwifiex_pcie_cleanup(struct mwifiex_adapter *adapter)
2723{
2724 struct pcie_service_card *card = adapter->card;
2725 struct pci_dev *pdev = card->dev;
dd04e6ac 2726 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 2727
d930faee 2728 if (user_rmmod) {
acebe8c1
ZL		 2729 mwifiex_dbg(adapter, INFO,
2730 "Clearing driver ready signature\n");
dd04e6ac 2731 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
acebe8c1
ZL		 2732 mwifiex_dbg(adapter, ERROR,
2733 "Failed to write driver not-ready signature\n");
d930faee
AK		 2734 }
2735
2736 if (pdev) {
2737 pci_iounmap(pdev, card->pci_mmap);
2738 pci_iounmap(pdev, card->pci_mmap1);
5b0d9b21 2739 pci_disable_device(pdev);
c380aafb
YAP		 2740 pci_release_region(pdev, 2);
2741 pci_release_region(pdev, 0);
d930faee
AK		 2742 pci_set_drvdata(pdev, NULL);
2743 }
3c59e328 2744 kfree(card);
d930faee
AK		 2745}
2746
7be0f5b5
AP		 2747static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter)
2748{
99074fc1 2749 int ret, i, j;
7be0f5b5
AP		 2750 struct pcie_service_card *card = adapter->card;
2751 struct pci_dev *pdev = card->dev;
2752
99074fc1
XH		 2753 if (card->pcie.reg->msix_support) {
2754 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
2755 card->msix_entries[i].entry = i;
2756 ret = pci_enable_msix_exact(pdev, card->msix_entries,
2757 MWIFIEX_NUM_MSIX_VECTORS);
2758 if (!ret) {
2759 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) {
2760 card->msix_ctx[i].dev = pdev;
2761 card->msix_ctx[i].msg_id = i;
2762
2763 ret = request_irq(card->msix_entries[i].vector,
2764 mwifiex_pcie_interrupt, 0,
2765 "MWIFIEX_PCIE_MSIX",
2766 &card->msix_ctx[i]);
2767 if (ret)
2768 break;
2769 }
2770
2771 if (ret) {
2772 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n",
2773 ret);
2774 for (j = 0; j < i; j++)
2775 free_irq(card->msix_entries[j].vector,
2776 &card->msix_ctx[i]);
2777 pci_disable_msix(pdev);
2778 } else {
2779 mwifiex_dbg(adapter, MSG, "MSIx enabled!");
2780 card->msix_enable = 1;
2781 return 0;
2782 }
2783 }
2784 }
2785
7be0f5b5
AP		 2786 if (pci_enable_msi(pdev) != 0)
2787 pci_disable_msi(pdev);
2788 else
2789 card->msi_enable = 1;
2790
2791 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable);
2792
99074fc1
XH		 2793 card->share_irq_ctx.dev = pdev;
2794 card->share_irq_ctx.msg_id = -1;
7be0f5b5 2795 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED,
99074fc1 2796 "MRVL_PCIE", &card->share_irq_ctx);
7be0f5b5
AP		 2797 if (ret) {
2798 pr_err("request_irq failed: ret=%d\n", ret);
2799 adapter->card = NULL;
2800 return -1;
2801 }
2802
2803 return 0;
2804}
2805
a362e16b
SL		 2806/*
2807 * This function get firmare name for downloading by revision id
2808 *
2809 * Read revision id register to get revision id
2810 */
2811static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter)
2812{
2813 int revision_id = 0;
e87650bc 2814 int version;
a362e16b
SL		 2815 struct pcie_service_card *card = adapter->card;
2816
2817 switch (card->dev->device) {
2818 case PCIE_DEVICE_ID_MARVELL_88W8766P:
2819 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME);
2820 break;
2821 case PCIE_DEVICE_ID_MARVELL_88W8897:
2822 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000);
2823 mwifiex_read_reg(adapter, 0x0c58, &revision_id);
2824 revision_id &= 0xff00;
2825 switch (revision_id) {
2826 case PCIE8897_A0:
2827 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME);
2828 break;
2829 case PCIE8897_B0:
2830 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME);
2831 break;
2832 default:
b9db3978
SL		 2833 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME);
2834
a362e16b
SL		 2835 break;
2836 }
c865a700 2837 break;
a362e16b
SL		 2838 case PCIE_DEVICE_ID_MARVELL_88W8997:
2839 mwifiex_read_reg(adapter, 0x0c48, &revision_id);
e87650bc
SL		 2840 mwifiex_read_reg(adapter, 0x0cd0, &version);
2841 version &= 0x7;
a362e16b
SL		 2842 switch (revision_id) {
2843 case PCIE8997_V2:
e87650bc
SL		 2844 if (version == CHIP_VER_PCIEUSB)
2845 strcpy(adapter->fw_name,
2846 PCIEUSB8997_FW_NAME_V2);
2847 else
2848 strcpy(adapter->fw_name,
2849 PCIEUART8997_FW_NAME_V2);
a362e16b
SL		 2850 break;
2851 case PCIE8997_Z:
e87650bc
SL		 2852 if (version == CHIP_VER_PCIEUSB)
2853 strcpy(adapter->fw_name,
2854 PCIEUSB8997_FW_NAME_Z);
2855 else
2856 strcpy(adapter->fw_name,
2857 PCIEUART8997_FW_NAME_Z);
a362e16b
SL		 2858 break;
2859 default:
b9db3978 2860 strcpy(adapter->fw_name, PCIE8997_DEFAULT_FW_NAME);
a362e16b
SL		 2861 break;
2862 }
2863 default:
2864 break;
2865 }
2866}
2867
d930faee
AK		 2868/*
2869 * This function registers the PCIE device.
2870 *
2871 * PCIE IRQ is claimed, block size is set and driver data is initialized.
2872 */
2873static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
2874{
d930faee
AK		 2875 struct pcie_service_card *card = adapter->card;
2876 struct pci_dev *pdev = card->dev;
2877
2878 /* save adapter pointer in card */
2879 card->adapter = adapter;
fdb1e28e 2880 adapter->dev = &pdev->dev;
d930faee 2881
7be0f5b5 2882 if (mwifiex_pcie_request_irq(adapter))
d930faee 2883 return -1;
d930faee 2884
828cf222 2885 adapter->tx_buf_size = card->pcie.tx_buf_size;
50632092
XH		 2886 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl;
2887 adapter->num_mem_types = card->pcie.num_mem_types;
1fe192d8 2888 adapter->ext_scan = card->pcie.can_ext_scan;
a362e16b 2889 mwifiex_pcie_get_fw_name(adapter);
d930faee
AK		 2890
2891 return 0;
2892}
2893
2894/*
2895 * This function unregisters the PCIE device.
2896 *
2897 * The PCIE IRQ is released, the function is disabled and driver
2898 * data is set to null.
2899 */
2900static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter)
2901{
2902 struct pcie_service_card *card = adapter->card;
52301a81 2903 const struct mwifiex_pcie_card_reg *reg;
99074fc1
XH		 2904 struct pci_dev *pdev = card->dev;
2905 int i;
d930faee
AK		 2906
2907 if (card) {
99074fc1
XH		 2908 if (card->msix_enable) {
2909 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
2910 synchronize_irq(card->msix_entries[i].vector);
2911
2912 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
2913 free_irq(card->msix_entries[i].vector,
2914 &card->msix_ctx[i]);
2915
2916 card->msix_enable = 0;
2917 pci_disable_msix(pdev);
2918 } else {
2919 mwifiex_dbg(adapter, INFO,
2920 "%s(): calling free_irq()\n", __func__);
2921 free_irq(card->dev->irq, &card->share_irq_ctx);
2922
2923 if (card->msi_enable)
2924 pci_disable_msi(pdev);
2925 }
fc331460 2926
52301a81
AP		 2927 reg = card->pcie.reg;
2928 if (reg->sleep_cookie)
2929 mwifiex_pcie_delete_sleep_cookie_buf(adapter);
2930
fc331460
AP		 2931 mwifiex_pcie_delete_cmdrsp_buf(adapter);
2932 mwifiex_pcie_delete_evtbd_ring(adapter);
2933 mwifiex_pcie_delete_rxbd_ring(adapter);
2934 mwifiex_pcie_delete_txbd_ring(adapter);
2935 card->cmdrsp_buf = NULL;
d930faee
AK		 2936 }
2937}
2938
2939static struct mwifiex_if_ops pcie_ops = {
2940 .init_if = mwifiex_pcie_init,
2941 .cleanup_if = mwifiex_pcie_cleanup,
2942 .check_fw_status = mwifiex_check_fw_status,
2fd5c6ed 2943 .check_winner_status = mwifiex_check_winner_status,
d930faee
AK		 2944 .prog_fw = mwifiex_prog_fw_w_helper,
2945 .register_dev = mwifiex_register_dev,
2946 .unregister_dev = mwifiex_unregister_dev,
2947 .enable_int = mwifiex_pcie_enable_host_int,
2948 .process_int_status = mwifiex_process_int_status,
2949 .host_to_card = mwifiex_pcie_host_to_card,
2950 .wakeup = mwifiex_pm_wakeup_card,
2951 .wakeup_complete = mwifiex_pm_wakeup_card_complete,
2952
2953 /* PCIE specific */
2954 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete,
2955 .event_complete = mwifiex_pcie_event_complete,
2956 .update_mp_end_port = NULL,
2957 .cleanup_mpa_buf = NULL,
c6d1d87a 2958 .init_fw_port = mwifiex_pcie_init_fw_port,
fbd7e7ac 2959 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf,
4646968b 2960 .reg_dump = mwifiex_pcie_reg_dump,
fc697159 2961 .device_dump = mwifiex_pcie_device_dump,
d930faee
AK		 2962};
2963
2964/*
2965 * This function initializes the PCIE driver module.
2966 *
2967 * This initiates the semaphore and registers the device with
2968 * PCIE bus.
2969 */
2970static int mwifiex_pcie_init_module(void)
2971{
2972 int ret;
2973
ca8f2112 2974 pr_debug("Marvell PCIe Driver\n");
d930faee
AK		 2975
2976 sema_init(&add_remove_card_sem, 1);
2977
2978 /* Clear the flag in case user removes the card. */
2979 user_rmmod = 0;
2980
2981 ret = pci_register_driver(&mwifiex_pcie);
2982 if (ret)
2983 pr_err("Driver register failed!\n");
2984 else
2985 pr_debug("info: Driver registered successfully!\n");
2986
2987 return ret;
2988}
2989
2990/*
2991 * This function cleans up the PCIE driver.
2992 *
2993 * The following major steps are followed for cleanup -
2994 * - Resume the device if its suspended
2995 * - Disconnect the device if connected
2996 * - Shutdown the firmware
2997 * - Unregister the device from PCIE bus.
2998 */
2999static void mwifiex_pcie_cleanup_module(void)
3000{
3001 if (!down_interruptible(&add_remove_card_sem))
3002 up(&add_remove_card_sem);
3003
3004 /* Set the flag as user is removing this module. */
3005 user_rmmod = 1;
3006
2f5872b6 3007 cancel_work_sync(&pcie_work);
d930faee
AK		 3008 pci_unregister_driver(&mwifiex_pcie);
3009}
3010
3011module_init(mwifiex_pcie_init_module);
3012module_exit(mwifiex_pcie_cleanup_module);
3013
3014MODULE_AUTHOR("Marvell International Ltd.");
3015MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION);
3016MODULE_VERSION(PCIE_VERSION);
3017MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)