Commit | Line | Data |
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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
128e63ef | 8 | * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 25 | * in the file called COPYING. |
c85eb619 EG |
26 | * |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
128e63ef | 33 | * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
82575102 | 71 | #include "iwl-drv.h" |
c85eb619 | 72 | #include "iwl-trans.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
7a10e3e4 | 75 | #include "iwl-agn-hw.h" |
6468a01a | 76 | #include "internal.h" |
0439bb62 | 77 | |
e139dc4a LE |
78 | static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, |
79 | u32 reg, u32 mask, u32 value) | |
80 | { | |
81 | u32 v; | |
82 | ||
83 | #ifdef CONFIG_IWLWIFI_DEBUG | |
84 | WARN_ON_ONCE(value & ~mask); | |
85 | #endif | |
86 | ||
87 | v = iwl_read32(trans, reg); | |
88 | v &= ~mask; | |
89 | v |= value; | |
90 | iwl_write32(trans, reg, v); | |
91 | } | |
92 | ||
93 | static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, | |
94 | u32 reg, u32 mask) | |
95 | { | |
96 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); | |
97 | } | |
98 | ||
99 | static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, | |
100 | u32 reg, u32 mask) | |
101 | { | |
102 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); | |
103 | } | |
104 | ||
ddaf5a5b | 105 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 106 | { |
ddaf5a5b JB |
107 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
108 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
109 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
110 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
111 | else | |
112 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
113 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
114 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
115 | } |
116 | ||
af634bee EG |
117 | /* PCI registers */ |
118 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 119 | |
7afe3705 | 120 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 121 | { |
20d3b647 | 122 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 123 | u16 lctl; |
af634bee | 124 | |
af634bee EG |
125 | /* |
126 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
127 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
128 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
129 | * costs negligible amount of power savings. | |
130 | * If not (unlikely), enable L0S, so there is at least some | |
131 | * power savings, even without L1. | |
132 | */ | |
7afe3705 | 133 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
438a0f0a | 134 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { |
af634bee EG |
135 | /* L1-ASPM enabled; disable(!) L0S */ |
136 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 137 | dev_info(trans->dev, "L1 Enabled; Disabling L0S\n"); |
af634bee EG |
138 | } else { |
139 | /* L1-ASPM disabled; enable(!) L0S */ | |
140 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 141 | dev_info(trans->dev, "L1 Disabled; Enabling L0S\n"); |
af634bee | 142 | } |
438a0f0a | 143 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
af634bee EG |
144 | } |
145 | ||
a6c684ee EG |
146 | /* |
147 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 148 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
149 | * NOTE: This does not load uCode nor start the embedded processor |
150 | */ | |
7afe3705 | 151 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee EG |
152 | { |
153 | int ret = 0; | |
154 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
155 | ||
156 | /* | |
157 | * Use "set_bit" below rather than "write", to preserve any hardware | |
158 | * bits already set by default after reset. | |
159 | */ | |
160 | ||
161 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
162 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 163 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
a6c684ee EG |
164 | |
165 | /* | |
166 | * Disable L0s without affecting L1; | |
167 | * don't wait for ICH L0s (ICH bug W/A) | |
168 | */ | |
169 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 170 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
171 | |
172 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
173 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
174 | ||
175 | /* | |
176 | * Enable HAP INTA (interrupt from management bus) to | |
177 | * wake device's PCI Express link L1a -> L0s | |
178 | */ | |
179 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 180 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 181 | |
7afe3705 | 182 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
183 | |
184 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 185 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 186 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 187 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
188 | |
189 | /* | |
190 | * Set "initialization complete" bit to move adapter from | |
191 | * D0U* --> D0A* (powered-up active) state. | |
192 | */ | |
193 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
194 | ||
195 | /* | |
196 | * Wait for clock stabilization; once stabilized, access to | |
197 | * device-internal resources is supported, e.g. iwl_write_prph() | |
198 | * and accesses to uCode SRAM. | |
199 | */ | |
200 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
201 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
202 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
203 | if (ret < 0) { |
204 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
205 | goto out; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Enable DMA clock and wait for it to stabilize. | |
210 | * | |
211 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
212 | * do not disable clocks. This preserves any hardware bits already | |
213 | * set by default in "CLK_CTRL_REG" after reset. | |
214 | */ | |
215 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
216 | udelay(20); | |
217 | ||
218 | /* Disable L1-Active */ | |
219 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
220 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
221 | ||
889b1696 EG |
222 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ |
223 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL); | |
224 | ||
eb7ff77e | 225 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); |
a6c684ee EG |
226 | |
227 | out: | |
228 | return ret; | |
229 | } | |
230 | ||
7afe3705 | 231 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
232 | { |
233 | int ret = 0; | |
234 | ||
235 | /* stop device's busmaster DMA activity */ | |
236 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
237 | ||
238 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
239 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
240 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
cc56feb2 EG |
241 | if (ret) |
242 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
243 | ||
244 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
245 | ||
246 | return ret; | |
247 | } | |
248 | ||
7afe3705 | 249 | static void iwl_pcie_apm_stop(struct iwl_trans *trans) |
cc56feb2 EG |
250 | { |
251 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
252 | ||
eb7ff77e | 253 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); |
cc56feb2 EG |
254 | |
255 | /* Stop device's DMA activity */ | |
7afe3705 | 256 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 EG |
257 | |
258 | /* Reset the entire device */ | |
259 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
260 | ||
261 | udelay(10); | |
262 | ||
263 | /* | |
264 | * Clear "initialization complete" bit to move adapter from | |
265 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
266 | */ | |
267 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
268 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
269 | } | |
270 | ||
7afe3705 | 271 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 272 | { |
7b11488f | 273 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
274 | unsigned long flags; |
275 | ||
276 | /* nic_init */ | |
7b11488f | 277 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
7afe3705 | 278 | iwl_pcie_apm_init(trans); |
392f8b78 | 279 | |
7b11488f | 280 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 281 | |
ddaf5a5b | 282 | iwl_pcie_set_pwr(trans, false); |
392f8b78 | 283 | |
ecdb975c | 284 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
285 | |
286 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 287 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
288 | |
289 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 290 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
291 | return -ENOMEM; |
292 | ||
035f7ff2 | 293 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 294 | /* enable shadow regs in HW */ |
20d3b647 | 295 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 296 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
297 | } |
298 | ||
392f8b78 EG |
299 | return 0; |
300 | } | |
301 | ||
302 | #define HW_READY_TIMEOUT (50) | |
303 | ||
304 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 305 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
306 | { |
307 | int ret; | |
308 | ||
1042db2a | 309 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 310 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
311 | |
312 | /* See if we got it */ | |
1042db2a | 313 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
314 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
315 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
316 | HW_READY_TIMEOUT); | |
392f8b78 | 317 | |
6d8f6eeb | 318 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
319 | return ret; |
320 | } | |
321 | ||
322 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 323 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
324 | { |
325 | int ret; | |
289e5501 | 326 | int t = 0; |
392f8b78 | 327 | |
6d8f6eeb | 328 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 329 | |
7afe3705 | 330 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 331 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
332 | if (ret >= 0) |
333 | return 0; | |
334 | ||
335 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 336 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 337 | CSR_HW_IF_CONFIG_REG_PREPARE); |
392f8b78 | 338 | |
289e5501 | 339 | do { |
7afe3705 | 340 | ret = iwl_pcie_set_hw_ready(trans); |
289e5501 EG |
341 | if (ret >= 0) |
342 | return 0; | |
392f8b78 | 343 | |
289e5501 EG |
344 | usleep_range(200, 1000); |
345 | t += 200; | |
346 | } while (t < 150000); | |
392f8b78 | 347 | |
392f8b78 EG |
348 | return ret; |
349 | } | |
350 | ||
cf614297 EG |
351 | /* |
352 | * ucode | |
353 | */ | |
7afe3705 | 354 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 355 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 356 | { |
13df1aab | 357 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
358 | int ret; |
359 | ||
13df1aab | 360 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
361 | |
362 | iwl_write_direct32(trans, | |
20d3b647 JB |
363 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
364 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
365 | |
366 | iwl_write_direct32(trans, | |
20d3b647 JB |
367 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
368 | dst_addr); | |
cf614297 EG |
369 | |
370 | iwl_write_direct32(trans, | |
83f84d7b JB |
371 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
372 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
373 | |
374 | iwl_write_direct32(trans, | |
20d3b647 JB |
375 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
376 | (iwl_get_dma_hi_addr(phy_addr) | |
377 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
378 | |
379 | iwl_write_direct32(trans, | |
20d3b647 JB |
380 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
381 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
382 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
383 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
384 | |
385 | iwl_write_direct32(trans, | |
20d3b647 JB |
386 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
387 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
388 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
389 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 390 | |
13df1aab JB |
391 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
392 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 393 | if (!ret) { |
83f84d7b | 394 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
395 | return -ETIMEDOUT; |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
7afe3705 | 401 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 402 | const struct fw_desc *section) |
cf614297 | 403 | { |
83f84d7b JB |
404 | u8 *v_addr; |
405 | dma_addr_t p_addr; | |
c571573a | 406 | u32 offset, chunk_sz = section->len; |
cf614297 EG |
407 | int ret = 0; |
408 | ||
83f84d7b JB |
409 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
410 | section_num); | |
411 | ||
c571573a EG |
412 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, |
413 | GFP_KERNEL | __GFP_NOWARN); | |
414 | if (!v_addr) { | |
415 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); | |
416 | chunk_sz = PAGE_SIZE; | |
417 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, | |
418 | &p_addr, GFP_KERNEL); | |
419 | if (!v_addr) | |
420 | return -ENOMEM; | |
421 | } | |
83f84d7b | 422 | |
c571573a | 423 | for (offset = 0; offset < section->len; offset += chunk_sz) { |
83f84d7b JB |
424 | u32 copy_size; |
425 | ||
c571573a | 426 | copy_size = min_t(u32, chunk_sz, section->len - offset); |
cf614297 | 427 | |
83f84d7b | 428 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
7afe3705 EG |
429 | ret = iwl_pcie_load_firmware_chunk(trans, |
430 | section->offset + offset, | |
431 | p_addr, copy_size); | |
83f84d7b JB |
432 | if (ret) { |
433 | IWL_ERR(trans, | |
434 | "Could not load the [%d] uCode section\n", | |
435 | section_num); | |
436 | break; | |
6dfa8d01 | 437 | } |
83f84d7b JB |
438 | } |
439 | ||
c571573a | 440 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); |
83f84d7b JB |
441 | return ret; |
442 | } | |
443 | ||
e2d6f4e7 EH |
444 | static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu) |
445 | { | |
446 | int shift_param; | |
447 | u32 address; | |
448 | int ret = 0; | |
449 | ||
450 | if (cpu == 1) { | |
451 | shift_param = 0; | |
452 | address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR; | |
453 | } else { | |
454 | shift_param = 16; | |
455 | address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR; | |
456 | } | |
457 | ||
458 | /* set CPU to started */ | |
459 | iwl_trans_set_bits_mask(trans, | |
460 | CSR_UCODE_LOAD_STATUS_ADDR, | |
461 | CSR_CPU_STATUS_LOADING_STARTED << shift_param, | |
462 | 1); | |
463 | ||
464 | /* set last complete descriptor number */ | |
465 | iwl_trans_set_bits_mask(trans, | |
466 | CSR_UCODE_LOAD_STATUS_ADDR, | |
467 | CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED | |
468 | << shift_param, | |
469 | 1); | |
470 | ||
471 | /* set last loaded block */ | |
472 | iwl_trans_set_bits_mask(trans, | |
473 | CSR_UCODE_LOAD_STATUS_ADDR, | |
474 | CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK | |
475 | << shift_param, | |
476 | 1); | |
477 | ||
478 | /* image loading complete */ | |
479 | iwl_trans_set_bits_mask(trans, | |
480 | CSR_UCODE_LOAD_STATUS_ADDR, | |
481 | CSR_CPU_STATUS_LOADING_COMPLETED | |
482 | << shift_param, | |
483 | 1); | |
484 | ||
485 | /* set FH_TCSR_0_REG */ | |
486 | iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1); | |
487 | ||
488 | /* verify image verification started */ | |
489 | ret = iwl_poll_bit(trans, address, | |
490 | CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS, | |
491 | CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS, | |
492 | CSR_SECURE_TIME_OUT); | |
493 | if (ret < 0) { | |
494 | IWL_ERR(trans, "secure boot process didn't start\n"); | |
495 | return ret; | |
496 | } | |
497 | ||
498 | /* wait for image verification to complete */ | |
499 | ret = iwl_poll_bit(trans, address, | |
500 | CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED, | |
501 | CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED, | |
502 | CSR_SECURE_TIME_OUT); | |
503 | ||
504 | if (ret < 0) { | |
505 | IWL_ERR(trans, "Time out on secure boot process\n"); | |
506 | return ret; | |
507 | } | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
7afe3705 | 512 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 513 | const struct fw_img *image) |
cf614297 | 514 | { |
2d1c0044 | 515 | int i, ret = 0; |
cf614297 | 516 | |
e2d6f4e7 EH |
517 | IWL_DEBUG_FW(trans, |
518 | "working with %s image\n", | |
519 | image->is_secure ? "Secured" : "Non Secured"); | |
520 | IWL_DEBUG_FW(trans, | |
521 | "working with %s CPU\n", | |
522 | image->is_dual_cpus ? "Dual" : "Single"); | |
523 | ||
524 | /* configure the ucode to be ready to get the secured image */ | |
525 | if (image->is_secure) { | |
526 | /* set secure boot inspector addresses */ | |
527 | iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0); | |
528 | iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0); | |
529 | ||
530 | /* release CPU1 reset if secure inspector image burned in OTP */ | |
531 | iwl_write32(trans, CSR_RESET, 0); | |
532 | } | |
533 | ||
534 | /* load to FW the binary sections of CPU1 */ | |
535 | IWL_DEBUG_INFO(trans, "Loading CPU1\n"); | |
536 | for (i = 0; | |
537 | i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU; | |
538 | i++) { | |
83f84d7b | 539 | if (!image->sec[i].data) |
2d1c0044 | 540 | break; |
7afe3705 | 541 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
2d1c0044 JB |
542 | if (ret) |
543 | return ret; | |
544 | } | |
cf614297 | 545 | |
e2d6f4e7 EH |
546 | /* configure the ucode to start secure process on CPU1 */ |
547 | if (image->is_secure) { | |
548 | /* config CPU1 to start secure protocol */ | |
549 | ret = iwl_pcie_secure_set(trans, 1); | |
550 | if (ret) | |
551 | return ret; | |
552 | } else { | |
553 | /* Remove all resets to allow NIC to operate */ | |
554 | iwl_write32(trans, CSR_RESET, 0); | |
555 | } | |
556 | ||
557 | if (image->is_dual_cpus) { | |
558 | /* load to FW the binary sections of CPU2 */ | |
559 | IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n"); | |
560 | for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU; | |
561 | i < IWL_UCODE_SECTION_MAX; i++) { | |
562 | if (!image->sec[i].data) | |
563 | break; | |
564 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); | |
565 | if (ret) | |
566 | return ret; | |
567 | } | |
568 | ||
569 | if (image->is_secure) { | |
570 | /* set CPU2 for secure protocol */ | |
571 | ret = iwl_pcie_secure_set(trans, 2); | |
572 | if (ret) | |
573 | return ret; | |
574 | } | |
575 | } | |
cf614297 EG |
576 | |
577 | return 0; | |
578 | } | |
579 | ||
0692fe41 | 580 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
6ae02f3e | 581 | const struct fw_img *fw, bool run_in_rfkill) |
392f8b78 EG |
582 | { |
583 | int ret; | |
c9eec95c | 584 | bool hw_rfkill; |
392f8b78 | 585 | |
496bab39 | 586 | /* This may fail if AMT took ownership of the device */ |
7afe3705 | 587 | if (iwl_pcie_prepare_card_hw(trans)) { |
6d8f6eeb | 588 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
589 | return -EIO; |
590 | } | |
591 | ||
eb7ff77e | 592 | clear_bit(STATUS_FW_ERROR, &trans->status); |
d18aa87f | 593 | |
8c46bb70 EG |
594 | iwl_enable_rfkill_int(trans); |
595 | ||
392f8b78 | 596 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 597 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 598 | if (hw_rfkill) |
eb7ff77e | 599 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 600 | else |
eb7ff77e | 601 | clear_bit(STATUS_RFKILL, &trans->status); |
c9eec95c | 602 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
6ae02f3e | 603 | if (hw_rfkill && !run_in_rfkill) |
392f8b78 | 604 | return -ERFKILL; |
392f8b78 | 605 | |
1042db2a | 606 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 607 | |
7afe3705 | 608 | ret = iwl_pcie_nic_init(trans); |
392f8b78 | 609 | if (ret) { |
6d8f6eeb | 610 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
611 | return ret; |
612 | } | |
613 | ||
614 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
615 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
616 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
617 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
618 | ||
619 | /* clear (again), then enable host interrupts */ | |
1042db2a | 620 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 621 | iwl_enable_interrupts(trans); |
392f8b78 EG |
622 | |
623 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
624 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
625 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 626 | |
cf614297 | 627 | /* Load the given image to the HW */ |
7afe3705 | 628 | return iwl_pcie_load_given_ucode(trans, fw); |
b3c2ce13 EG |
629 | } |
630 | ||
adca1235 | 631 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 632 | { |
990aa6d7 | 633 | iwl_pcie_reset_ict(trans); |
f02831be | 634 | iwl_pcie_tx_start(trans, scd_addr); |
c170b867 EG |
635 | } |
636 | ||
43e58856 | 637 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 638 | { |
43e58856 | 639 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
20d3b647 | 640 | unsigned long flags; |
a4082843 | 641 | bool hw_rfkill; |
ae2c30bf | 642 | |
43e58856 | 643 | /* tell the device to stop sending interrupts */ |
7b11488f | 644 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 645 | iwl_disable_interrupts(trans); |
7b11488f | 646 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 647 | |
ab6cf8e8 | 648 | /* device going down, Stop using ICT table */ |
990aa6d7 | 649 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
650 | |
651 | /* | |
652 | * If a HW restart happens during firmware loading, | |
653 | * then the firmware loading might call this function | |
654 | * and later it might be called again due to the | |
655 | * restart. So don't process again if the device is | |
656 | * already dead. | |
657 | */ | |
eb7ff77e | 658 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) { |
f02831be | 659 | iwl_pcie_tx_stop(trans); |
9805c446 | 660 | iwl_pcie_rx_stop(trans); |
6379103e | 661 | |
ab6cf8e8 | 662 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 663 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
664 | APMG_CLK_VAL_DMA_CLK_RQT); |
665 | udelay(5); | |
666 | } | |
667 | ||
668 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 669 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 670 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
671 | |
672 | /* Stop the device, and put it in low power state */ | |
7afe3705 | 673 | iwl_pcie_apm_stop(trans); |
43e58856 EG |
674 | |
675 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
676 | * Clean again the interrupt here | |
677 | */ | |
7b11488f | 678 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 679 | iwl_disable_interrupts(trans); |
7b11488f | 680 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 | 681 | |
43e58856 | 682 | /* stop and reset the on-board processor */ |
1042db2a | 683 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
74fda971 DF |
684 | |
685 | /* clear all status bits */ | |
eb7ff77e AN |
686 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
687 | clear_bit(STATUS_INT_ENABLED, &trans->status); | |
688 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); | |
689 | clear_bit(STATUS_TPOWER_PMI, &trans->status); | |
690 | clear_bit(STATUS_RFKILL, &trans->status); | |
a4082843 AN |
691 | |
692 | /* | |
693 | * Even if we stop the HW, we still want the RF kill | |
694 | * interrupt | |
695 | */ | |
696 | iwl_enable_rfkill_int(trans); | |
697 | ||
698 | /* | |
699 | * Check again since the RF kill state may have changed while | |
700 | * all the interrupts were disabled, in this case we couldn't | |
701 | * receive the RF kill interrupt and update the state in the | |
702 | * op_mode. | |
703 | */ | |
704 | hw_rfkill = iwl_is_rfkill_set(trans); | |
705 | if (hw_rfkill) | |
eb7ff77e | 706 | set_bit(STATUS_RFKILL, &trans->status); |
a4082843 | 707 | else |
eb7ff77e | 708 | clear_bit(STATUS_RFKILL, &trans->status); |
a4082843 | 709 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
ab6cf8e8 EG |
710 | } |
711 | ||
debff618 | 712 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) |
2dd4f9f7 | 713 | { |
2dd4f9f7 | 714 | iwl_disable_interrupts(trans); |
debff618 JB |
715 | |
716 | /* | |
717 | * in testing mode, the host stays awake and the | |
718 | * hardware won't be reset (not even partially) | |
719 | */ | |
720 | if (test) | |
721 | return; | |
722 | ||
ddaf5a5b JB |
723 | iwl_pcie_disable_ict(trans); |
724 | ||
2dd4f9f7 JB |
725 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
726 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ddaf5a5b JB |
727 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
728 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
729 | ||
730 | /* | |
731 | * reset TX queues -- some of their registers reset during S3 | |
732 | * so if we don't reset everything here the D3 image would try | |
733 | * to execute some invalid memory upon resume | |
734 | */ | |
735 | iwl_trans_pcie_tx_reset(trans); | |
736 | ||
737 | iwl_pcie_set_pwr(trans, true); | |
738 | } | |
739 | ||
740 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
debff618 JB |
741 | enum iwl_d3_status *status, |
742 | bool test) | |
ddaf5a5b JB |
743 | { |
744 | u32 val; | |
745 | int ret; | |
746 | ||
debff618 JB |
747 | if (test) { |
748 | iwl_enable_interrupts(trans); | |
749 | *status = IWL_D3_STATUS_ALIVE; | |
750 | return 0; | |
751 | } | |
752 | ||
ddaf5a5b JB |
753 | iwl_pcie_set_pwr(trans, false); |
754 | ||
755 | val = iwl_read32(trans, CSR_RESET); | |
756 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) { | |
757 | *status = IWL_D3_STATUS_RESET; | |
758 | return 0; | |
759 | } | |
760 | ||
761 | /* | |
762 | * Also enables interrupts - none will happen as the device doesn't | |
763 | * know we're waking it up, only when the opmode actually tells it | |
764 | * after this call. | |
765 | */ | |
766 | iwl_pcie_reset_ict(trans); | |
767 | ||
768 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
769 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
770 | ||
771 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
772 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
773 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
774 | 25000); | |
775 | if (ret) { | |
776 | IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); | |
777 | return ret; | |
778 | } | |
779 | ||
780 | iwl_trans_pcie_tx_reset(trans); | |
781 | ||
782 | ret = iwl_pcie_rx_init(trans); | |
783 | if (ret) { | |
784 | IWL_ERR(trans, "Failed to resume the device (RX reset)\n"); | |
785 | return ret; | |
786 | } | |
787 | ||
ddaf5a5b JB |
788 | *status = IWL_D3_STATUS_ALIVE; |
789 | return 0; | |
2dd4f9f7 JB |
790 | } |
791 | ||
57a1dc89 | 792 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 793 | { |
c9eec95c | 794 | bool hw_rfkill; |
a8b691e6 | 795 | int err; |
e6bb4c9c | 796 | |
7afe3705 | 797 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 798 | if (err) { |
d6f1c316 | 799 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
a8b691e6 | 800 | return err; |
ebb7678d | 801 | } |
a6c684ee | 802 | |
2997494f EG |
803 | /* Reset the entire device */ |
804 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
805 | ||
806 | usleep_range(10, 15); | |
807 | ||
7afe3705 | 808 | iwl_pcie_apm_init(trans); |
a6c684ee | 809 | |
226c02ca EG |
810 | /* From now on, the op_mode will be kept updated about RF kill state */ |
811 | iwl_enable_rfkill_int(trans); | |
812 | ||
8d425517 | 813 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 814 | if (hw_rfkill) |
eb7ff77e | 815 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 816 | else |
eb7ff77e | 817 | clear_bit(STATUS_RFKILL, &trans->status); |
c9eec95c | 818 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
d48e2074 | 819 | |
a8b691e6 | 820 | return 0; |
e6bb4c9c EG |
821 | } |
822 | ||
a4082843 | 823 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 824 | { |
20d3b647 | 825 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
218733cf | 826 | unsigned long flags; |
d23f78e6 | 827 | |
a4082843 | 828 | /* disable interrupts - don't enable HW RF kill interrupt */ |
ee7d737c DS |
829 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
830 | iwl_disable_interrupts(trans); | |
831 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
832 | ||
7afe3705 | 833 | iwl_pcie_apm_stop(trans); |
cc56feb2 | 834 | |
218733cf EG |
835 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
836 | iwl_disable_interrupts(trans); | |
837 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1df06bdc | 838 | |
8d96bb61 | 839 | iwl_pcie_disable_ict(trans); |
cc56feb2 EG |
840 | } |
841 | ||
03905495 EG |
842 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
843 | { | |
05f5b97e | 844 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
845 | } |
846 | ||
847 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
848 | { | |
05f5b97e | 849 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
850 | } |
851 | ||
852 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
853 | { | |
05f5b97e | 854 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
855 | } |
856 | ||
6a06b6c1 EG |
857 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
858 | { | |
f9477c17 AP |
859 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, |
860 | ((reg & 0x000FFFFF) | (3 << 24))); | |
6a06b6c1 EG |
861 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); |
862 | } | |
863 | ||
864 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
865 | u32 val) | |
866 | { | |
867 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
f9477c17 | 868 | ((addr & 0x000FFFFF) | (3 << 24))); |
6a06b6c1 EG |
869 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); |
870 | } | |
871 | ||
c6f600fc | 872 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 873 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
874 | { |
875 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
876 | ||
877 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 878 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
d663ee73 JB |
879 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
880 | trans_pcie->n_no_reclaim_cmds = 0; | |
881 | else | |
882 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
883 | if (trans_pcie->n_no_reclaim_cmds) | |
884 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
885 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 886 | |
b2cf410c JB |
887 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
888 | if (trans_pcie->rx_buf_size_8k) | |
889 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
890 | else | |
891 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
892 | |
893 | trans_pcie->wd_timeout = | |
894 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
895 | |
896 | trans_pcie->command_names = trans_cfg->command_names; | |
046db346 | 897 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
c6f600fc MV |
898 | } |
899 | ||
d1ff5253 | 900 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 901 | { |
20d3b647 | 902 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 903 | |
0aa86df6 | 904 | synchronize_irq(trans_pcie->pci_dev->irq); |
0aa86df6 | 905 | |
f02831be | 906 | iwl_pcie_tx_free(trans); |
9805c446 | 907 | iwl_pcie_rx_free(trans); |
6379103e | 908 | |
a8b691e6 JB |
909 | free_irq(trans_pcie->pci_dev->irq, trans); |
910 | iwl_pcie_free_ict(trans); | |
a42a1844 EG |
911 | |
912 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 913 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
914 | pci_release_regions(trans_pcie->pci_dev); |
915 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 916 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 917 | |
6d8f6eeb | 918 | kfree(trans); |
34c1b7ba EG |
919 | } |
920 | ||
47107e84 DF |
921 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
922 | { | |
47107e84 | 923 | if (state) |
eb7ff77e | 924 | set_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 | 925 | else |
eb7ff77e | 926 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 DF |
927 | } |
928 | ||
e56b04ef LE |
929 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, |
930 | unsigned long *flags) | |
7a65d170 EG |
931 | { |
932 | int ret; | |
cfb4e624 JB |
933 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
934 | ||
935 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); | |
7a65d170 EG |
936 | |
937 | /* this bit wakes up the NIC */ | |
e139dc4a LE |
938 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
939 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
940 | |
941 | /* | |
942 | * These bits say the device is running, and should keep running for | |
943 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
944 | * but they do not indicate that embedded SRAM is restored yet; | |
945 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
946 | * to/from host DRAM when sleeping/waking for power-saving. | |
947 | * Each direction takes approximately 1/4 millisecond; with this | |
948 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
949 | * series of register accesses are expected (e.g. reading Event Log), | |
950 | * to keep device from sleeping. | |
951 | * | |
952 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
953 | * SRAM is okay/restored. We don't check that here because this call | |
954 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
955 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
956 | * | |
957 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
958 | * and do not save/restore SRAM when power cycling. | |
959 | */ | |
960 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
961 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
962 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
963 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
964 | if (unlikely(ret < 0)) { | |
965 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
966 | if (!silent) { | |
967 | u32 val = iwl_read32(trans, CSR_GP_CNTRL); | |
968 | WARN_ONCE(1, | |
969 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
970 | val); | |
cfb4e624 | 971 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
972 | return false; |
973 | } | |
974 | } | |
975 | ||
e56b04ef LE |
976 | /* |
977 | * Fool sparse by faking we release the lock - sparse will | |
978 | * track nic_access anyway. | |
979 | */ | |
cfb4e624 | 980 | __release(&trans_pcie->reg_lock); |
7a65d170 EG |
981 | return true; |
982 | } | |
983 | ||
e56b04ef LE |
984 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
985 | unsigned long *flags) | |
7a65d170 | 986 | { |
cfb4e624 | 987 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e56b04ef | 988 | |
cfb4e624 | 989 | lockdep_assert_held(&trans_pcie->reg_lock); |
e56b04ef LE |
990 | |
991 | /* | |
992 | * Fool sparse by faking we acquiring the lock - sparse will | |
993 | * track nic_access anyway. | |
994 | */ | |
cfb4e624 | 995 | __acquire(&trans_pcie->reg_lock); |
e56b04ef | 996 | |
e139dc4a LE |
997 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
998 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
999 | /* |
1000 | * Above we read the CSR_GP_CNTRL register, which will flush | |
1001 | * any previous writes, but we need the write that clears the | |
1002 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
1003 | * scheduled on different CPUs (after we drop reg_lock). | |
1004 | */ | |
1005 | mmiowb(); | |
cfb4e624 | 1006 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
1007 | } |
1008 | ||
4fd442db EG |
1009 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
1010 | void *buf, int dwords) | |
1011 | { | |
1012 | unsigned long flags; | |
1013 | int offs, ret = 0; | |
1014 | u32 *vals = buf; | |
1015 | ||
e56b04ef | 1016 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
1017 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
1018 | for (offs = 0; offs < dwords; offs++) | |
1019 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 1020 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1021 | } else { |
1022 | ret = -EBUSY; | |
1023 | } | |
4fd442db EG |
1024 | return ret; |
1025 | } | |
1026 | ||
1027 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 1028 | const void *buf, int dwords) |
4fd442db EG |
1029 | { |
1030 | unsigned long flags; | |
1031 | int offs, ret = 0; | |
bf0fd5da | 1032 | const u32 *vals = buf; |
4fd442db | 1033 | |
e56b04ef | 1034 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
1035 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
1036 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
1037 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
1038 | vals ? vals[offs] : 0); | |
e56b04ef | 1039 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1040 | } else { |
1041 | ret = -EBUSY; | |
1042 | } | |
4fd442db EG |
1043 | return ret; |
1044 | } | |
7a65d170 | 1045 | |
5f178cd2 EG |
1046 | #define IWL_FLUSH_WAIT_MS 2000 |
1047 | ||
990aa6d7 | 1048 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans) |
5f178cd2 | 1049 | { |
8ad71bef | 1050 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1051 | struct iwl_txq *txq; |
5f178cd2 EG |
1052 | struct iwl_queue *q; |
1053 | int cnt; | |
1054 | unsigned long now = jiffies; | |
1c3fea82 EG |
1055 | u32 scd_sram_addr; |
1056 | u8 buf[16]; | |
5f178cd2 EG |
1057 | int ret = 0; |
1058 | ||
1059 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 1060 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
9ba1947a | 1061 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 1062 | continue; |
8ad71bef | 1063 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
1064 | q = &txq->q; |
1065 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1066 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1067 | msleep(1); | |
1068 | ||
1069 | if (q->read_ptr != q->write_ptr) { | |
1c3fea82 EG |
1070 | IWL_ERR(trans, |
1071 | "fail to flush all tx fifo queues Q %d\n", cnt); | |
5f178cd2 EG |
1072 | ret = -ETIMEDOUT; |
1073 | break; | |
1074 | } | |
1075 | } | |
1c3fea82 EG |
1076 | |
1077 | if (!ret) | |
1078 | return 0; | |
1079 | ||
1080 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
1081 | txq->q.read_ptr, txq->q.write_ptr); | |
1082 | ||
1083 | scd_sram_addr = trans_pcie->scd_base_addr + | |
1084 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
1085 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
1086 | ||
1087 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
1088 | ||
1089 | for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) | |
1090 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, | |
1091 | iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); | |
1092 | ||
1093 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
1094 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); | |
1095 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
1096 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
1097 | u32 tbl_dw = | |
1098 | iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + | |
1099 | SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); | |
1100 | ||
1101 | if (cnt & 0x1) | |
1102 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
1103 | else | |
1104 | tbl_dw = tbl_dw & 0x0000FFFF; | |
1105 | ||
1106 | IWL_ERR(trans, | |
1107 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
1108 | cnt, active ? "" : "in", fifo, tbl_dw, | |
1109 | iwl_read_prph(trans, | |
1110 | SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1), | |
1111 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); | |
1112 | } | |
1113 | ||
5f178cd2 EG |
1114 | return ret; |
1115 | } | |
1116 | ||
e139dc4a LE |
1117 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
1118 | u32 mask, u32 value) | |
1119 | { | |
e56b04ef | 1120 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
1121 | unsigned long flags; |
1122 | ||
e56b04ef | 1123 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 1124 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 1125 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
1126 | } |
1127 | ||
ff620849 EG |
1128 | static const char *get_csr_string(int cmd) |
1129 | { | |
d9fb6465 | 1130 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1131 | switch (cmd) { |
1132 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1133 | IWL_CMD(CSR_INT_COALESCING); | |
1134 | IWL_CMD(CSR_INT); | |
1135 | IWL_CMD(CSR_INT_MASK); | |
1136 | IWL_CMD(CSR_FH_INT_STATUS); | |
1137 | IWL_CMD(CSR_GPIO_IN); | |
1138 | IWL_CMD(CSR_RESET); | |
1139 | IWL_CMD(CSR_GP_CNTRL); | |
1140 | IWL_CMD(CSR_HW_REV); | |
1141 | IWL_CMD(CSR_EEPROM_REG); | |
1142 | IWL_CMD(CSR_EEPROM_GP); | |
1143 | IWL_CMD(CSR_OTP_GP_REG); | |
1144 | IWL_CMD(CSR_GIO_REG); | |
1145 | IWL_CMD(CSR_GP_UCODE_REG); | |
1146 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1147 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1148 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1149 | IWL_CMD(CSR_LED_REG); | |
1150 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1151 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1152 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1153 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1154 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1155 | default: | |
1156 | return "UNKNOWN"; | |
1157 | } | |
d9fb6465 | 1158 | #undef IWL_CMD |
ff620849 EG |
1159 | } |
1160 | ||
990aa6d7 | 1161 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
1162 | { |
1163 | int i; | |
1164 | static const u32 csr_tbl[] = { | |
1165 | CSR_HW_IF_CONFIG_REG, | |
1166 | CSR_INT_COALESCING, | |
1167 | CSR_INT, | |
1168 | CSR_INT_MASK, | |
1169 | CSR_FH_INT_STATUS, | |
1170 | CSR_GPIO_IN, | |
1171 | CSR_RESET, | |
1172 | CSR_GP_CNTRL, | |
1173 | CSR_HW_REV, | |
1174 | CSR_EEPROM_REG, | |
1175 | CSR_EEPROM_GP, | |
1176 | CSR_OTP_GP_REG, | |
1177 | CSR_GIO_REG, | |
1178 | CSR_GP_UCODE_REG, | |
1179 | CSR_GP_DRIVER_REG, | |
1180 | CSR_UCODE_DRV_GP1, | |
1181 | CSR_UCODE_DRV_GP2, | |
1182 | CSR_LED_REG, | |
1183 | CSR_DRAM_INT_TBL_REG, | |
1184 | CSR_GIO_CHICKEN_BITS, | |
1185 | CSR_ANA_PLL_CFG, | |
1186 | CSR_HW_REV_WA_REG, | |
1187 | CSR_DBG_HPET_MEM_REG | |
1188 | }; | |
1189 | IWL_ERR(trans, "CSR values:\n"); | |
1190 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1191 | "CSR_INT_PERIODIC_REG)\n"); | |
1192 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1193 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1194 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1195 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1196 | } |
1197 | } | |
1198 | ||
87e5666c EG |
1199 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1200 | /* create and remove of files */ | |
1201 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1202 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 1203 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 1204 | goto err; \ |
87e5666c EG |
1205 | } while (0) |
1206 | ||
1207 | /* file operation */ | |
87e5666c | 1208 | #define DEBUGFS_READ_FILE_OPS(name) \ |
87e5666c EG |
1209 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1210 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1211 | .open = simple_open, \ |
87e5666c EG |
1212 | .llseek = generic_file_llseek, \ |
1213 | }; | |
1214 | ||
16db88ba | 1215 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
16db88ba EG |
1216 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1217 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1218 | .open = simple_open, \ |
16db88ba EG |
1219 | .llseek = generic_file_llseek, \ |
1220 | }; | |
1221 | ||
87e5666c | 1222 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
87e5666c EG |
1223 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1224 | .write = iwl_dbgfs_##name##_write, \ | |
1225 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1226 | .open = simple_open, \ |
87e5666c EG |
1227 | .llseek = generic_file_llseek, \ |
1228 | }; | |
1229 | ||
87e5666c | 1230 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1231 | char __user *user_buf, |
1232 | size_t count, loff_t *ppos) | |
8ad71bef | 1233 | { |
5a878bf6 | 1234 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1235 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1236 | struct iwl_txq *txq; |
87e5666c EG |
1237 | struct iwl_queue *q; |
1238 | char *buf; | |
1239 | int pos = 0; | |
1240 | int cnt; | |
1241 | int ret; | |
1745e440 WYG |
1242 | size_t bufsz; |
1243 | ||
035f7ff2 | 1244 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1245 | |
f9e75447 | 1246 | if (!trans_pcie->txq) |
87e5666c | 1247 | return -EAGAIN; |
f9e75447 | 1248 | |
87e5666c EG |
1249 | buf = kzalloc(bufsz, GFP_KERNEL); |
1250 | if (!buf) | |
1251 | return -ENOMEM; | |
1252 | ||
035f7ff2 | 1253 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1254 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1255 | q = &txq->q; |
1256 | pos += scnprintf(buf + pos, bufsz - pos, | |
9eae88fa | 1257 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", |
87e5666c | 1258 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa JB |
1259 | !!test_bit(cnt, trans_pcie->queue_used), |
1260 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
87e5666c EG |
1261 | } |
1262 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1263 | kfree(buf); | |
1264 | return ret; | |
1265 | } | |
1266 | ||
1267 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1268 | char __user *user_buf, |
1269 | size_t count, loff_t *ppos) | |
1270 | { | |
5a878bf6 | 1271 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1272 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1273 | struct iwl_rxq *rxq = &trans_pcie->rxq; |
87e5666c EG |
1274 | char buf[256]; |
1275 | int pos = 0; | |
1276 | const size_t bufsz = sizeof(buf); | |
1277 | ||
1278 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1279 | rxq->read); | |
1280 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1281 | rxq->write); | |
1282 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1283 | rxq->free_count); | |
1284 | if (rxq->rb_stts) { | |
1285 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1286 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1287 | } else { | |
1288 | pos += scnprintf(buf + pos, bufsz - pos, | |
1289 | "closed_rb_num: Not Allocated\n"); | |
1290 | } | |
1291 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1292 | } | |
1293 | ||
1f7b6172 EG |
1294 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1295 | char __user *user_buf, | |
20d3b647 JB |
1296 | size_t count, loff_t *ppos) |
1297 | { | |
1f7b6172 | 1298 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1299 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1300 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1301 | ||
1302 | int pos = 0; | |
1303 | char *buf; | |
1304 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1305 | ssize_t ret; | |
1306 | ||
1307 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1308 | if (!buf) |
1f7b6172 | 1309 | return -ENOMEM; |
1f7b6172 EG |
1310 | |
1311 | pos += scnprintf(buf + pos, bufsz - pos, | |
1312 | "Interrupt Statistics Report:\n"); | |
1313 | ||
1314 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1315 | isr_stats->hw); | |
1316 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1317 | isr_stats->sw); | |
1318 | if (isr_stats->sw || isr_stats->hw) { | |
1319 | pos += scnprintf(buf + pos, bufsz - pos, | |
1320 | "\tLast Restarting Code: 0x%X\n", | |
1321 | isr_stats->err_code); | |
1322 | } | |
1323 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1324 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1325 | isr_stats->sch); | |
1326 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1327 | isr_stats->alive); | |
1328 | #endif | |
1329 | pos += scnprintf(buf + pos, bufsz - pos, | |
1330 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1331 | ||
1332 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1333 | isr_stats->ctkill); | |
1334 | ||
1335 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1336 | isr_stats->wakeup); | |
1337 | ||
1338 | pos += scnprintf(buf + pos, bufsz - pos, | |
1339 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1340 | ||
1341 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1342 | isr_stats->tx); | |
1343 | ||
1344 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1345 | isr_stats->unhandled); | |
1346 | ||
1347 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1348 | kfree(buf); | |
1349 | return ret; | |
1350 | } | |
1351 | ||
1352 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1353 | const char __user *user_buf, | |
1354 | size_t count, loff_t *ppos) | |
1355 | { | |
1356 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1357 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1358 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1359 | ||
1360 | char buf[8]; | |
1361 | int buf_size; | |
1362 | u32 reset_flag; | |
1363 | ||
1364 | memset(buf, 0, sizeof(buf)); | |
1365 | buf_size = min(count, sizeof(buf) - 1); | |
1366 | if (copy_from_user(buf, user_buf, buf_size)) | |
1367 | return -EFAULT; | |
1368 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1369 | return -EFAULT; | |
1370 | if (reset_flag == 0) | |
1371 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1372 | ||
1373 | return count; | |
1374 | } | |
1375 | ||
16db88ba | 1376 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1377 | const char __user *user_buf, |
1378 | size_t count, loff_t *ppos) | |
16db88ba EG |
1379 | { |
1380 | struct iwl_trans *trans = file->private_data; | |
1381 | char buf[8]; | |
1382 | int buf_size; | |
1383 | int csr; | |
1384 | ||
1385 | memset(buf, 0, sizeof(buf)); | |
1386 | buf_size = min(count, sizeof(buf) - 1); | |
1387 | if (copy_from_user(buf, user_buf, buf_size)) | |
1388 | return -EFAULT; | |
1389 | if (sscanf(buf, "%d", &csr) != 1) | |
1390 | return -EFAULT; | |
1391 | ||
990aa6d7 | 1392 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
1393 | |
1394 | return count; | |
1395 | } | |
1396 | ||
16db88ba | 1397 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1398 | char __user *user_buf, |
1399 | size_t count, loff_t *ppos) | |
16db88ba EG |
1400 | { |
1401 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 1402 | char *buf = NULL; |
16db88ba EG |
1403 | int pos = 0; |
1404 | ssize_t ret = -EFAULT; | |
1405 | ||
313b0a29 | 1406 | ret = pos = iwl_dump_fh(trans, &buf); |
16db88ba EG |
1407 | if (buf) { |
1408 | ret = simple_read_from_buffer(user_buf, | |
1409 | count, ppos, buf, pos); | |
1410 | kfree(buf); | |
1411 | } | |
1412 | ||
1413 | return ret; | |
1414 | } | |
1415 | ||
1f7b6172 | 1416 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1417 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1418 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1419 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1420 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c EG |
1421 | |
1422 | /* | |
1423 | * Create the debugfs files and directories | |
1424 | * | |
1425 | */ | |
1426 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 1427 | struct dentry *dir) |
87e5666c | 1428 | { |
87e5666c EG |
1429 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1430 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 1431 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1432 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1433 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c | 1434 | return 0; |
9da987ac MV |
1435 | |
1436 | err: | |
1437 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1438 | return -ENOMEM; | |
87e5666c EG |
1439 | } |
1440 | #else | |
1441 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 JB |
1442 | struct dentry *dir) |
1443 | { | |
1444 | return 0; | |
1445 | } | |
87e5666c EG |
1446 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
1447 | ||
d1ff5253 | 1448 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 1449 | .start_hw = iwl_trans_pcie_start_hw, |
a4082843 | 1450 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, |
ed6a3803 | 1451 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 1452 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 1453 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 1454 | |
ddaf5a5b JB |
1455 | .d3_suspend = iwl_trans_pcie_d3_suspend, |
1456 | .d3_resume = iwl_trans_pcie_d3_resume, | |
2dd4f9f7 | 1457 | |
f02831be | 1458 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 1459 | |
e6bb4c9c | 1460 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 1461 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1462 | |
d0624be6 | 1463 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 1464 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 1465 | |
87e5666c | 1466 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 | 1467 | |
990aa6d7 | 1468 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
5f178cd2 | 1469 | |
03905495 EG |
1470 | .write8 = iwl_trans_pcie_write8, |
1471 | .write32 = iwl_trans_pcie_write32, | |
1472 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
1473 | .read_prph = iwl_trans_pcie_read_prph, |
1474 | .write_prph = iwl_trans_pcie_write_prph, | |
4fd442db EG |
1475 | .read_mem = iwl_trans_pcie_read_mem, |
1476 | .write_mem = iwl_trans_pcie_write_mem, | |
c6f600fc | 1477 | .configure = iwl_trans_pcie_configure, |
47107e84 | 1478 | .set_pmi = iwl_trans_pcie_set_pmi, |
7a65d170 | 1479 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
e139dc4a LE |
1480 | .release_nic_access = iwl_trans_pcie_release_nic_access, |
1481 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, | |
e6bb4c9c | 1482 | }; |
a42a1844 | 1483 | |
87ce05a2 | 1484 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
1485 | const struct pci_device_id *ent, |
1486 | const struct iwl_cfg *cfg) | |
a42a1844 | 1487 | { |
a42a1844 EG |
1488 | struct iwl_trans_pcie *trans_pcie; |
1489 | struct iwl_trans *trans; | |
1490 | u16 pci_cmd; | |
1491 | int err; | |
1492 | ||
1493 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 1494 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
6965a354 LC |
1495 | if (!trans) { |
1496 | err = -ENOMEM; | |
1497 | goto out; | |
1498 | } | |
a42a1844 EG |
1499 | |
1500 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1501 | ||
1502 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 1503 | trans->cfg = cfg; |
2bfb5092 | 1504 | trans_lockdep_init(trans); |
a42a1844 | 1505 | trans_pcie->trans = trans; |
7b11488f | 1506 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 1507 | spin_lock_init(&trans_pcie->reg_lock); |
13df1aab | 1508 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 | 1509 | |
d819c6cf JB |
1510 | err = pci_enable_device(pdev); |
1511 | if (err) | |
1512 | goto out_no_pci; | |
1513 | ||
f2532b04 EG |
1514 | if (!cfg->base_params->pcie_l1_allowed) { |
1515 | /* | |
1516 | * W/A - seems to solve weird behavior. We need to remove this | |
1517 | * if we don't want to stay in L1 all the time. This wastes a | |
1518 | * lot of power. | |
1519 | */ | |
1520 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | | |
1521 | PCIE_LINK_STATE_L1 | | |
1522 | PCIE_LINK_STATE_CLKPM); | |
1523 | } | |
a42a1844 | 1524 | |
a42a1844 EG |
1525 | pci_set_master(pdev); |
1526 | ||
1527 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1528 | if (!err) | |
1529 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1530 | if (err) { | |
1531 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1532 | if (!err) | |
1533 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 1534 | DMA_BIT_MASK(32)); |
a42a1844 EG |
1535 | /* both attempts failed: */ |
1536 | if (err) { | |
6a4b09f8 | 1537 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
a42a1844 EG |
1538 | goto out_pci_disable_device; |
1539 | } | |
1540 | } | |
1541 | ||
1542 | err = pci_request_regions(pdev, DRV_NAME); | |
1543 | if (err) { | |
6a4b09f8 | 1544 | dev_err(&pdev->dev, "pci_request_regions failed\n"); |
a42a1844 EG |
1545 | goto out_pci_disable_device; |
1546 | } | |
1547 | ||
05f5b97e | 1548 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 1549 | if (!trans_pcie->hw_base) { |
6a4b09f8 | 1550 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
1551 | err = -ENODEV; |
1552 | goto out_pci_release_regions; | |
1553 | } | |
1554 | ||
a42a1844 EG |
1555 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
1556 | * PCI Tx retries from interfering with C3 CPU state */ | |
1557 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
1558 | ||
1559 | err = pci_enable_msi(pdev); | |
9f904b38 | 1560 | if (err) { |
6a4b09f8 | 1561 | dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err); |
9f904b38 EG |
1562 | /* enable rfkill interrupt: hw bug w/a */ |
1563 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1564 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1565 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1566 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1567 | } | |
1568 | } | |
a42a1844 EG |
1569 | |
1570 | trans->dev = &pdev->dev; | |
a42a1844 | 1571 | trans_pcie->pci_dev = pdev; |
08079a49 | 1572 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 1573 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
1574 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
1575 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 1576 | |
69a10b29 | 1577 | /* Initialize the wait queue for commands */ |
f946b529 | 1578 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 1579 | |
3ec45882 JB |
1580 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
1581 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
1582 | |
1583 | trans->dev_cmd_headroom = 0; | |
1584 | trans->dev_cmd_pool = | |
3ec45882 | 1585 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
1586 | sizeof(struct iwl_device_cmd) |
1587 | + trans->dev_cmd_headroom, | |
1588 | sizeof(void *), | |
1589 | SLAB_HWCACHE_ALIGN, | |
1590 | NULL); | |
1591 | ||
6965a354 LC |
1592 | if (!trans->dev_cmd_pool) { |
1593 | err = -ENOMEM; | |
59c647b6 | 1594 | goto out_pci_disable_msi; |
6965a354 | 1595 | } |
59c647b6 | 1596 | |
a8b691e6 JB |
1597 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1598 | ||
a8b691e6 JB |
1599 | if (iwl_pcie_alloc_ict(trans)) |
1600 | goto out_free_cmd_pool; | |
1601 | ||
6965a354 LC |
1602 | err = request_threaded_irq(pdev->irq, iwl_pcie_isr_ict, |
1603 | iwl_pcie_irq_handler, | |
1604 | IRQF_SHARED, DRV_NAME, trans); | |
1605 | if (err) { | |
a8b691e6 JB |
1606 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); |
1607 | goto out_free_ict; | |
1608 | } | |
1609 | ||
a42a1844 EG |
1610 | return trans; |
1611 | ||
a8b691e6 JB |
1612 | out_free_ict: |
1613 | iwl_pcie_free_ict(trans); | |
1614 | out_free_cmd_pool: | |
1615 | kmem_cache_destroy(trans->dev_cmd_pool); | |
59c647b6 EG |
1616 | out_pci_disable_msi: |
1617 | pci_disable_msi(pdev); | |
a42a1844 EG |
1618 | out_pci_release_regions: |
1619 | pci_release_regions(pdev); | |
1620 | out_pci_disable_device: | |
1621 | pci_disable_device(pdev); | |
1622 | out_no_pci: | |
1623 | kfree(trans); | |
6965a354 LC |
1624 | out: |
1625 | return ERR_PTR(err); | |
a42a1844 | 1626 | } |