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iwlwifi: mvm: Use the AP station for non_sta transmit
[linux-block.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
553452e5
LK		 34 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
cb6bb128 78#include "iwl-scd.h"
7a10e3e4 79#include "iwl-agn-hw.h"
4d075007 80#include "iwl-fw-error-dump.h"
6468a01a 81#include "internal.h"
06d51e0d 82#include "iwl-fh.h"
0439bb62 83
fe45773b
AN		 84/* extended range in FW SRAM */
85#define IWL_FW_MEM_EXTENDED_START 0x40000
86#define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
c2d20201
EG		 88static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89{
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102}
103
96c285da 104static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 105{
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 107 struct page *page = NULL;
c2d20201 108 dma_addr_t phys;
96c285da 109 u32 size = 0;
c2d20201
EG		 110 u8 power;
111
96c285da
EG		 112 if (!max_power) {
113 /* default max_power is maximum */
114 max_power = 26;
115 } else {
116 max_power += 11;
117 }
118
119 if (WARN(max_power > 26,
120 "External buffer size for monitor is too big %d, check the FW TLV\n",
121 max_power))
122 return;
123
c2d20201
EG		 124 if (trans_pcie->fw_mon_page) {
125 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
126 trans_pcie->fw_mon_size,
127 DMA_FROM_DEVICE);
128 return;
129 }
130
131 phys = 0;
96c285da 132 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 133 int order;
134
135 size = BIT(power);
136 order = get_order(size);
137 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
138 order);
139 if (!page)
140 continue;
141
142 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
143 DMA_FROM_DEVICE);
144 if (dma_mapping_error(trans->dev, phys)) {
145 __free_pages(page, order);
553452e5 146 page = NULL;
c2d20201
EG		 147 continue;
148 }
149 IWL_INFO(trans,
150 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
151 size, order);
152 break;
153 }
154
40a76905 155 if (WARN_ON_ONCE(!page))
c2d20201
EG		 156 return;
157
96c285da
EG		 158 if (power != max_power)
159 IWL_ERR(trans,
160 "Sorry - debug buffer is only %luK while you requested %luK\n",
161 (unsigned long)BIT(power - 10),
162 (unsigned long)BIT(max_power - 10));
163
c2d20201
EG		 164 trans_pcie->fw_mon_page = page;
165 trans_pcie->fw_mon_phys = phys;
166 trans_pcie->fw_mon_size = size;
167}
168
a812cba9
AB		 169static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
170{
171 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
172 ((reg & 0x0000ffff) | (2 << 28)));
173 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
174}
175
176static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
177{
178 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
179 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
180 ((reg & 0x0000ffff) | (3 << 28)));
181}
182
ddaf5a5b 183static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 184{
95411d04
AA		 185 if (!trans->cfg->apmg_not_supported)
186 return;
187
ddaf5a5b
JB		 188 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
189 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
190 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
191 ~APMG_PS_CTRL_MSK_PWR_SRC);
192 else
193 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
194 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
195 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 196}
197
af634bee
EG		 198/* PCI registers */
199#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 200
7afe3705 201static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 202{
20d3b647 203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 204 u16 lctl;
9180ac50 205 u16 cap;
af634bee 206
af634bee
EG		 207 /*
208 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
209 * Check if BIOS (or OS) enabled L1-ASPM on this device.
210 * If so (likely), disable L0S, so device moves directly L0->L1;
211 * costs negligible amount of power savings.
212 * If not (unlikely), enable L0S, so there is at least some
213 * power savings, even without L1.
214 */
7afe3705 215 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 216 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 217 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 218 else
af634bee 219 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 220 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 221
222 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
223 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
224 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
225 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
226 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 227}
228
a6c684ee
EG		 229/*
230 * Start up NIC's basic functionality after it has been reset
7afe3705 231 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 232 * NOTE: This does not load uCode nor start the embedded processor
233 */
7afe3705 234static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 235{
236 int ret = 0;
237 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
238
239 /*
240 * Use "set_bit" below rather than "write", to preserve any hardware
241 * bits already set by default after reset.
242 */
243
244 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 245 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
246 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
247 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 248
249 /*
250 * Disable L0s without affecting L1;
251 * don't wait for ICH L0s (ICH bug W/A)
252 */
253 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 254 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 255
256 /* Set FH wait threshold to maximum (HW error during stress W/A) */
257 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
258
259 /*
260 * Enable HAP INTA (interrupt from management bus) to
261 * wake device's PCI Express link L1a -> L0s
262 */
263 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 264 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 265
7afe3705 266 iwl_pcie_apm_config(trans);
a6c684ee
EG		 267
268 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 269 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 270 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 271 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 272
273 /*
274 * Set "initialization complete" bit to move adapter from
275 * D0U* --> D0A* (powered-up active) state.
276 */
277 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
278
279 /*
280 * Wait for clock stabilization; once stabilized, access to
281 * device-internal resources is supported, e.g. iwl_write_prph()
282 * and accesses to uCode SRAM.
283 */
284 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 285 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
286 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 287 if (ret < 0) {
288 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
289 goto out;
290 }
291
2d93aee1
EG		 292 if (trans->cfg->host_interrupt_operation_mode) {
293 /*
294 * This is a bit of an abuse - This is needed for 7260 / 3160
295 * only check host_interrupt_operation_mode even if this is
296 * not related to host_interrupt_operation_mode.
297 *
298 * Enable the oscillator to count wake up time for L1 exit. This
299 * consumes slightly more power (100uA) - but allows to be sure
300 * that we wake up from L1 on time.
301 *
302 * This looks weird: read twice the same register, discard the
303 * value, set a bit, and yet again, read that same register
304 * just to discard the value. But that's the way the hardware
305 * seems to like it.
306 */
307 iwl_read_prph(trans, OSC_CLK);
308 iwl_read_prph(trans, OSC_CLK);
309 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 }
313
a6c684ee
EG		 314 /*
315 * Enable DMA clock and wait for it to stabilize.
316 *
3073d8c0
EH		 317 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
318 * bits do not disable clocks. This preserves any hardware
319 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 320 */
95411d04 321 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 322 iwl_write_prph(trans, APMG_CLK_EN_REG,
323 APMG_CLK_VAL_DMA_CLK_RQT);
324 udelay(20);
325
326 /* Disable L1-Active */
327 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
328 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
329
330 /* Clear the interrupt in APMG if the NIC is in RFKILL */
331 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
332 APMG_RTC_INT_STT_RFKILL);
333 }
889b1696 334
eb7ff77e 335 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 336
337out:
338 return ret;
339}
340
a812cba9
AB		 341/*
342 * Enable LP XTAL to avoid HW bug where device may consume much power if
343 * FW is not loaded after device reset. LP XTAL is disabled by default
344 * after device HW reset. Do it only if XTAL is fed by internal source.
345 * Configure device's "persistence" mode to avoid resetting XTAL again when
346 * SHRD_HW_RST occurs in S3.
347 */
348static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
349{
350 int ret;
351 u32 apmg_gp1_reg;
352 u32 apmg_xtal_cfg_reg;
353 u32 dl_cfg_reg;
354
355 /* Force XTAL ON */
356 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
357 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
358
359 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
360 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
361
362 udelay(10);
363
364 /*
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
367 */
368 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
369
370 /*
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is possible.
373 */
374 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 25000);
378 if (WARN_ON(ret < 0)) {
379 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
380 /* Release XTAL ON request */
381 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383 return;
384 }
385
386 /*
387 * Clear "disable persistence" to avoid LP XTAL resetting when
388 * SHRD_HW_RST is applied in S3.
389 */
390 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
391 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
392
393 /*
394 * Force APMG XTAL to be active to prevent its disabling by HW
395 * caused by APMG idle state.
396 */
397 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
398 SHR_APMG_XTAL_CFG_REG);
399 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
400 apmg_xtal_cfg_reg |
401 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
402
403 /*
404 * Reset entire device again - do controller reset (results in
405 * SHRD_HW_RST). Turn MAC off before proceeding.
406 */
407 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
408
409 udelay(10);
410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
7afe3705 451static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
b7aaeae4 469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
b7aaeae4
EG		 473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
482 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
483 CSR_HW_IF_CONFIG_REG_PREPARE |
484 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
485 mdelay(5);
486 }
487
eb7ff77e 488 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 489
490 /* Stop device's DMA activity */
7afe3705 491 iwl_pcie_apm_stop_master(trans);
cc56feb2 492
a812cba9
AB		 493 if (trans->cfg->lp_xtal_workaround) {
494 iwl_pcie_apm_lp_xtal_enable(trans);
495 return;
496 }
497
cc56feb2
EG		 498 /* Reset the entire device */
499 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
500
501 udelay(10);
502
503 /*
504 * Clear "initialization complete" bit to move adapter from
505 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
506 */
507 iwl_clear_bit(trans, CSR_GP_CNTRL,
508 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
509}
510
7afe3705 511static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 512{
7b11488f 513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 514
515 /* nic_init */
7b70bd63 516 spin_lock(&trans_pcie->irq_lock);
7afe3705 517 iwl_pcie_apm_init(trans);
392f8b78 518
7b70bd63 519 spin_unlock(&trans_pcie->irq_lock);
392f8b78 520
95411d04 521 iwl_pcie_set_pwr(trans, false);
392f8b78 522
ecdb975c 523 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 524
525 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 526 iwl_pcie_rx_init(trans);
392f8b78
EG		 527
528 /* Allocate or reset and init all Tx and Command queues */
f02831be 529 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 530 return -ENOMEM;
531
035f7ff2 532 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 533 /* enable shadow regs in HW */
20d3b647 534 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 535 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 536 }
537
392f8b78
EG		 538 return 0;
539}
540
541#define HW_READY_TIMEOUT (50)
542
543/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 544static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 545{
546 int ret;
547
1042db2a 548 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 549 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 550
551 /* See if we got it */
1042db2a 552 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 553 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
555 HW_READY_TIMEOUT);
392f8b78 556
6a08f514
EG		 557 if (ret >= 0)
558 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
559
6d8f6eeb 560 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 561 return ret;
562}
563
564/* Note: returns standard 0/-ERROR code */
7afe3705 565static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 566{
567 int ret;
289e5501 568 int t = 0;
501fd989 569 int iter;
392f8b78 570
6d8f6eeb 571 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 572
7afe3705 573 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 574 /* If the card is ready, exit 0 */
392f8b78
EG		 575 if (ret >= 0)
576 return 0;
577
501fd989
EG		 578 for (iter = 0; iter < 10; iter++) {
579 /* If HW is not ready, prepare the conditions to check again */
580 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
581 CSR_HW_IF_CONFIG_REG_PREPARE);
582
583 do {
584 ret = iwl_pcie_set_hw_ready(trans);
585 if (ret >= 0)
586 return 0;
392f8b78 587
501fd989
EG		 588 usleep_range(200, 1000);
589 t += 200;
590 } while (t < 150000);
591 msleep(25);
592 }
392f8b78 593
7f2ac8fb 594 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 595
392f8b78
EG		 596 return ret;
597}
598
cf614297
EG		 599/*
600 * ucode
601 */
7afe3705 602static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 603 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 604{
13df1aab 605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 606 int ret;
607
13df1aab 608 trans_pcie->ucode_write_complete = false;
cf614297
EG		 609
610 iwl_write_direct32(trans,
20d3b647
JB		 611 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
612 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 613
614 iwl_write_direct32(trans,
20d3b647
JB		 615 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
616 dst_addr);
cf614297
EG		 617
618 iwl_write_direct32(trans,
83f84d7b
JB		 619 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
620 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 621
622 iwl_write_direct32(trans,
20d3b647
JB		 623 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
624 (iwl_get_dma_hi_addr(phy_addr)
625 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 626
627 iwl_write_direct32(trans,
20d3b647
JB		 628 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
630 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 632
633 iwl_write_direct32(trans,
20d3b647
JB		 634 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
637 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 638
13df1aab
JB		 639 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
640 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 641 if (!ret) {
83f84d7b 642 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 643 return -ETIMEDOUT;
644 }
645
646 return 0;
647}
648
7afe3705 649static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 650 const struct fw_desc *section)
cf614297 651{
83f84d7b
JB		 652 u8 *v_addr;
653 dma_addr_t p_addr;
baa21e83 654 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 655 int ret = 0;
656
83f84d7b
JB		 657 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
658 section_num);
659
c571573a
EG		 660 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
661 GFP_KERNEL | __GFP_NOWARN);
662 if (!v_addr) {
663 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
664 chunk_sz = PAGE_SIZE;
665 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
666 &p_addr, GFP_KERNEL);
667 if (!v_addr)
668 return -ENOMEM;
669 }
83f84d7b 670
c571573a 671 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 672 u32 copy_size, dst_addr;
673 bool extended_addr = false;
83f84d7b 674
c571573a 675 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 676 dst_addr = section->offset + offset;
677
678 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
679 dst_addr <= IWL_FW_MEM_EXTENDED_END)
680 extended_addr = true;
681
682 if (extended_addr)
683 iwl_set_bits_prph(trans, LMPM_CHICK,
684 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 685
83f84d7b 686 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 687 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
688 copy_size);
689
690 if (extended_addr)
691 iwl_clear_bits_prph(trans, LMPM_CHICK,
692 LMPM_CHICK_EXTENDED_ADDR_SPACE);
693
83f84d7b
JB		 694 if (ret) {
695 IWL_ERR(trans,
696 "Could not load the [%d] uCode section\n",
697 section_num);
698 break;
6dfa8d01 699 }
83f84d7b
JB		 700 }
701
c571573a 702 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 703 return ret;
704}
705
16bc119b
EH		 706/*
707 * Driver Takes the ownership on secure machine before FW load
708 * and prevent race with the BT load.
709 * W/A for ROM bug. (should be remove in the next Si step)
710 */
711static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
712{
713 u32 val, loop = 1000;
714
1e167071
EH		 715 /*
716 * Check the RSA semaphore is accessible.
717 * If the HW isn't locked and the rsa semaphore isn't accessible,
718 * we are in trouble.
719 */
16bc119b
EH		 720 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
721 if (val & (BIT(1) | BIT(17))) {
1e167071
EH		 722 IWL_INFO(trans,
723 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 724 return 0;
725 }
726
727 /* take ownership on the AUX IF */
728 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
729 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
730
731 do {
732 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
733 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
734 if (val == 0x1) {
735 iwl_write_prph(trans, RSA_ENABLE, 0);
736 return 0;
737 }
738
739 udelay(10);
740 loop--;
741 } while (loop > 0);
742
743 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
744 return -EIO;
745}
746
5dd9c68a
EG		 747static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
748 const struct fw_img *image,
749 int cpu,
750 int *first_ucode_section)
e2d6f4e7
EH		 751{
752 int shift_param;
dcab8ecd
EH		 753 int i, ret = 0, sec_num = 0x1;
754 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 755
756 if (cpu == 1) {
757 shift_param = 0;
034846cf 758 *first_ucode_section = 0;
e2d6f4e7
EH		 759 } else {
760 shift_param = 16;
034846cf 761 (*first_ucode_section)++;
e2d6f4e7
EH		 762 }
763
034846cf
EH		 764 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
765 last_read_idx = i;
766
767 if (!image->sec[i].data ||
768 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
769 IWL_DEBUG_FW(trans,
770 "Break since Data not valid or Empty section, sec = %d\n",
771 i);
189fa2fa 772 break;
034846cf
EH		 773 }
774
189fa2fa
EH		 775 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
776 if (ret)
777 return ret;
dcab8ecd
EH		 778
779 /* Notify the ucode of the loaded section number and status */
780 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
781 val = val | (sec_num << shift_param);
782 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
783 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 784 }
785
034846cf
EH		 786 *first_ucode_section = last_read_idx;
787
afb88917
EH		 788 if (cpu == 1)
789 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
790 else
791 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
792
189fa2fa
EH		 793 return 0;
794}
e2d6f4e7 795
189fa2fa
EH		 796static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
797 const struct fw_img *image,
034846cf
EH		 798 int cpu,
799 int *first_ucode_section)
189fa2fa
EH		 800{
801 int shift_param;
189fa2fa 802 int i, ret = 0;
034846cf 803 u32 last_read_idx = 0;
189fa2fa
EH		 804
805 if (cpu == 1) {
806 shift_param = 0;
034846cf 807 *first_ucode_section = 0;
189fa2fa
EH		 808 } else {
809 shift_param = 16;
034846cf 810 (*first_ucode_section)++;
189fa2fa
EH		 811 }
812
034846cf
EH		 813 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
814 last_read_idx = i;
815
816 if (!image->sec[i].data ||
817 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
818 IWL_DEBUG_FW(trans,
819 "Break since Data not valid or Empty section, sec = %d\n",
820 i);
189fa2fa 821 break;
034846cf
EH		 822 }
823
189fa2fa
EH		 824 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
825 if (ret)
826 return ret;
e2d6f4e7
EH		 827 }
828
189fa2fa
EH		 829 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
830 iwl_set_bits_prph(trans,
831 CSR_UCODE_LOAD_STATUS_ADDR,
832 (LMPM_CPU_UCODE_LOADING_COMPLETED |
833 LMPM_CPU_HDRS_LOADING_COMPLETED |
834 LMPM_CPU_UCODE_LOADING_STARTED) <<
835 shift_param);
836
034846cf
EH		 837 *first_ucode_section = last_read_idx;
838
e2d6f4e7
EH		 839 return 0;
840}
841
09e350f7
LK		 842static void iwl_pcie_apply_destination(struct iwl_trans *trans)
843{
844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
845 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
846 int i;
847
848 if (dest->version)
849 IWL_ERR(trans,
850 "DBG DEST version is %d - expect issues\n",
851 dest->version);
852
853 IWL_INFO(trans, "Applying debug destination %s\n",
854 get_fw_dbg_mode_string(dest->monitor_mode));
855
856 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 857 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 858 else
859 IWL_WARN(trans, "PCI should have external buffer debug\n");
860
861 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
862 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
863 u32 val = le32_to_cpu(dest->reg_ops[i].val);
864
865 switch (dest->reg_ops[i].op) {
866 case CSR_ASSIGN:
867 iwl_write32(trans, addr, val);
868 break;
869 case CSR_SETBIT:
870 iwl_set_bit(trans, addr, BIT(val));
871 break;
872 case CSR_CLEARBIT:
873 iwl_clear_bit(trans, addr, BIT(val));
874 break;
875 case PRPH_ASSIGN:
876 iwl_write_prph(trans, addr, val);
877 break;
878 case PRPH_SETBIT:
879 iwl_set_bits_prph(trans, addr, BIT(val));
880 break;
881 case PRPH_CLEARBIT:
882 iwl_clear_bits_prph(trans, addr, BIT(val));
883 break;
884 default:
885 IWL_ERR(trans, "FW debug - unknown OP %d\n",
886 dest->reg_ops[i].op);
887 break;
888 }
889 }
890
891 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
892 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
893 trans_pcie->fw_mon_phys >> dest->base_shift);
894 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
895 (trans_pcie->fw_mon_phys +
896 trans_pcie->fw_mon_size) >> dest->end_shift);
897 }
898}
899
7afe3705 900static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 901 const struct fw_img *image)
cf614297 902{
c2d20201 903 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 904 int ret = 0;
034846cf 905 int first_ucode_section;
cf614297 906
dcab8ecd 907 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 908 image->is_dual_cpus ? "Dual" : "Single");
909
dcab8ecd
EH		 910 /* load to FW the binary non secured sections of CPU1 */
911 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
912 if (ret)
913 return ret;
e2d6f4e7
EH		 914
915 if (image->is_dual_cpus) {
189fa2fa
EH		 916 /* set CPU2 header address */
917 iwl_write_prph(trans,
918 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
919 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 920
189fa2fa 921 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 922 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
923 &first_ucode_section);
189fa2fa
EH		 924 if (ret)
925 return ret;
e2d6f4e7 926 }
cf614297 927
c2d20201
EG		 928 /* supported for 7000 only for the moment */
929 if (iwlwifi_mod_params.fw_monitor &&
930 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 931 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 932
933 if (trans_pcie->fw_mon_size) {
934 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
935 trans_pcie->fw_mon_phys >> 4);
936 iwl_write_prph(trans, MON_BUFF_END_ADDR,
937 (trans_pcie->fw_mon_phys +
938 trans_pcie->fw_mon_size) >> 4);
939 }
09e350f7
LK		 940 } else if (trans->dbg_dest_tlv) {
941 iwl_pcie_apply_destination(trans);
c2d20201
EG		 942 }
943
e12ba844 944 /* release CPU reset */
5dd9c68a 945 iwl_write32(trans, CSR_RESET, 0);
e12ba844 946
dcab8ecd
EH		 947 return 0;
948}
189fa2fa 949
5dd9c68a
EG		 950static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
951 const struct fw_img *image)
dcab8ecd
EH		 952{
953 int ret = 0;
954 int first_ucode_section;
dcab8ecd
EH		 955
956 IWL_DEBUG_FW(trans, "working with %s CPU\n",
957 image->is_dual_cpus ? "Dual" : "Single");
958
a2227ce2
EG		 959 if (trans->dbg_dest_tlv)
960 iwl_pcie_apply_destination(trans);
961
16bc119b
EH		 962 /* TODO: remove in the next Si step */
963 ret = iwl_pcie_rsa_race_bug_wa(trans);
964 if (ret)
965 return ret;
966
dcab8ecd
EH		 967 /* configure the ucode to be ready to get the secured image */
968 /* release CPU reset */
969 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
970
971 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 972 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
973 &first_ucode_section);
dcab8ecd
EH		 974 if (ret)
975 return ret;
976
977 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 978 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
979 &first_ucode_section);
cf614297
EG		 980}
981
0692fe41 982static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 983 const struct fw_img *fw, bool run_in_rfkill)
392f8b78 984{
fa9f3281 985 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 986 bool hw_rfkill;
fa9f3281
EG		 987 int ret;
988
989 mutex_lock(&trans_pcie->mutex);
990
991 /* Someone called stop_device, don't try to start_fw */
992 if (trans_pcie->is_down) {
993 IWL_WARN(trans,
994 "Can't start_fw since the HW hasn't been started\n");
995 ret = EIO;
996 goto out;
997 }
392f8b78 998
496bab39 999 /* This may fail if AMT took ownership of the device */
7afe3705 1000 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 1001 IWL_WARN(trans, "Exit HW not ready\n");
fa9f3281
EG		 1002 ret = -EIO;
1003 goto out;
392f8b78
EG		 1004 }
1005
8c46bb70
EG		 1006 iwl_enable_rfkill_int(trans);
1007
392f8b78 1008 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 1009 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1010 if (hw_rfkill)
eb7ff77e 1011 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1012 else
eb7ff77e 1013 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1014 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
fa9f3281
EG		 1015 if (hw_rfkill && !run_in_rfkill) {
1016 ret = -ERFKILL;
1017 goto out;
1018 }
392f8b78 1019
1042db2a 1020 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 1021
7afe3705 1022 ret = iwl_pcie_nic_init(trans);
392f8b78 1023 if (ret) {
6d8f6eeb 1024 IWL_ERR(trans, "Unable to init nic\n");
fa9f3281 1025 goto out;
392f8b78
EG		 1026 }
1027
1028 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 1029 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1030 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 1031 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1032
1033 /* clear (again), then enable host interrupts */
1042db2a 1034 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 1035 iwl_enable_interrupts(trans);
392f8b78
EG		 1036
1037 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 1038 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1039 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 1040
cf614297 1041 /* Load the given image to the HW */
5dd9c68a 1042 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
fa9f3281 1043 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
dcab8ecd 1044 else
fa9f3281
EG		 1045 ret = iwl_pcie_load_given_ucode(trans, fw);
1046
1047out:
1048 mutex_unlock(&trans_pcie->mutex);
1049 return ret;
b3c2ce13
EG		 1050}
1051
adca1235 1052static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 1053{
990aa6d7 1054 iwl_pcie_reset_ict(trans);
f02831be 1055 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 1056}
1057
fa9f3281 1058static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1059{
43e58856 1060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1061 bool hw_rfkill, was_hw_rfkill;
1062
fa9f3281
EG		 1063 lockdep_assert_held(&trans_pcie->mutex);
1064
1065 if (trans_pcie->is_down)
1066 return;
1067
1068 trans_pcie->is_down = true;
1069
3dc3374f 1070 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1071
43e58856 1072 /* tell the device to stop sending interrupts */
7b70bd63 1073 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1074 iwl_disable_interrupts(trans);
7b70bd63 1075 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1076
ab6cf8e8 1077 /* device going down, Stop using ICT table */
990aa6d7 1078 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1079
1080 /*
1081 * If a HW restart happens during firmware loading,
1082 * then the firmware loading might call this function
1083 * and later it might be called again due to the
1084 * restart. So don't process again if the device is
1085 * already dead.
1086 */
31b8b343
EG		 1087 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1088 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1089 iwl_pcie_tx_stop(trans);
9805c446 1090 iwl_pcie_rx_stop(trans);
6379103e 1091
ab6cf8e8 1092 /* Power-down device's busmaster DMA clocks */
95411d04 1093 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1094 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1095 APMG_CLK_VAL_DMA_CLK_RQT);
1096 udelay(5);
1097 }
ab6cf8e8
EG		 1098 }
1099
1100 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1101 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1102 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1103
1104 /* Stop the device, and put it in low power state */
b7aaeae4 1105 iwl_pcie_apm_stop(trans, false);
43e58856 1106
03d6c3b0
EG		 1107 /* stop and reset the on-board processor */
1108 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1109 udelay(20);
1110
1111 /*
1112 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1113 * This is a bug in certain verions of the hardware.
1114 * Certain devices also keep sending HW RF kill interrupt all
1115 * the time, unless the interrupt is ACKed even if the interrupt
1116 * should be masked. Re-ACK all the interrupts here.
43e58856 1117 */
7b70bd63 1118 spin_lock(&trans_pcie->irq_lock);
43e58856 1119 iwl_disable_interrupts(trans);
7b70bd63 1120 spin_unlock(&trans_pcie->irq_lock);
43e58856 1121
74fda971
DF		 1122
1123 /* clear all status bits */
eb7ff77e
AN		 1124 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1125 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1126 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1127 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1128
1129 /*
1130 * Even if we stop the HW, we still want the RF kill
1131 * interrupt
1132 */
1133 iwl_enable_rfkill_int(trans);
1134
1135 /*
1136 * Check again since the RF kill state may have changed while
1137 * all the interrupts were disabled, in this case we couldn't
1138 * receive the RF kill interrupt and update the state in the
1139 * op_mode.
3dc3374f
EG		 1140 * Don't call the op_mode if the rkfill state hasn't changed.
1141 * This allows the op_mode to call stop_device from the rfkill
1142 * notification without endless recursion. Under very rare
1143 * circumstances, we might have a small recursion if the rfkill
1144 * state changed exactly now while we were called from stop_device.
1145 * This is very unlikely but can happen and is supported.
a4082843
AN		 1146 */
1147 hw_rfkill = iwl_is_rfkill_set(trans);
1148 if (hw_rfkill)
eb7ff77e 1149 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1150 else
eb7ff77e 1151 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1152 if (hw_rfkill != was_hw_rfkill)
14cfca71 1153 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1154
1155 /* re-take ownership to prevent other users from stealing the deivce */
1156 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1157}
1158
fa9f3281
EG		 1159static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1160{
1161 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1162
1163 mutex_lock(&trans_pcie->mutex);
1164 _iwl_trans_pcie_stop_device(trans, low_power);
1165 mutex_unlock(&trans_pcie->mutex);
1166}
1167
14cfca71
JB		 1168void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1169{
fa9f3281
EG		 1170 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1171 IWL_TRANS_GET_PCIE_TRANS(trans);
1172
1173 lockdep_assert_held(&trans_pcie->mutex);
1174
14cfca71 1175 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1176 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1177}
1178
debff618 1179static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1180{
33b56af1
EG		 1181 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1182
2dd4f9f7 1183 iwl_disable_interrupts(trans);
debff618
JB		 1184
1185 /*
1186 * in testing mode, the host stays awake and the
1187 * hardware won't be reset (not even partially)
1188 */
1189 if (test)
1190 return;
1191
ddaf5a5b
JB		 1192 iwl_pcie_disable_ict(trans);
1193
33b56af1
EG		 1194 synchronize_irq(trans_pcie->pci_dev->irq);
1195
2dd4f9f7
JB		 1196 iwl_clear_bit(trans, CSR_GP_CNTRL,
1197 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1198 iwl_clear_bit(trans, CSR_GP_CNTRL,
1199 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1200
1201 /*
1202 * reset TX queues -- some of their registers reset during S3
1203 * so if we don't reset everything here the D3 image would try
1204 * to execute some invalid memory upon resume
1205 */
1206 iwl_trans_pcie_tx_reset(trans);
1207
1208 iwl_pcie_set_pwr(trans, true);
1209}
1210
1211static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1212 enum iwl_d3_status *status,
1213 bool test)
ddaf5a5b
JB		 1214{
1215 u32 val;
1216 int ret;
1217
debff618
JB		 1218 if (test) {
1219 iwl_enable_interrupts(trans);
1220 *status = IWL_D3_STATUS_ALIVE;
1221 return 0;
1222 }
1223
ddaf5a5b
JB		 1224 /*
1225 * Also enables interrupts - none will happen as the device doesn't
1226 * know we're waking it up, only when the opmode actually tells it
1227 * after this call.
1228 */
1229 iwl_pcie_reset_ict(trans);
1230
1231 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1232 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1233
01e58a28
EG		 1234 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1235 udelay(2);
1236
ddaf5a5b
JB		 1237 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1238 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1239 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1240 25000);
7f2ac8fb 1241 if (ret < 0) {
ddaf5a5b
JB		 1242 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1243 return ret;
1244 }
1245
a3ead656
EG		 1246 iwl_pcie_set_pwr(trans, false);
1247
ddaf5a5b
JB		 1248 iwl_trans_pcie_tx_reset(trans);
1249
1250 ret = iwl_pcie_rx_init(trans);
1251 if (ret) {
1252 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1253 return ret;
1254 }
1255
a3ead656
EG		 1256 val = iwl_read32(trans, CSR_RESET);
1257 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1258 *status = IWL_D3_STATUS_RESET;
1259 else
1260 *status = IWL_D3_STATUS_ALIVE;
1261
ddaf5a5b 1262 return 0;
2dd4f9f7
JB		 1263}
1264
fa9f3281 1265static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1266{
fa9f3281 1267 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1268 bool hw_rfkill;
a8b691e6 1269 int err;
e6bb4c9c 1270
fa9f3281
EG		 1271 lockdep_assert_held(&trans_pcie->mutex);
1272
7afe3705 1273 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1274 if (err) {
d6f1c316 1275 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1276 return err;
ebb7678d 1277 }
a6c684ee 1278
2997494f 1279 /* Reset the entire device */
ce836c76 1280 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1281
1282 usleep_range(10, 15);
1283
7afe3705 1284 iwl_pcie_apm_init(trans);
a6c684ee 1285
226c02ca
EG		 1286 /* From now on, the op_mode will be kept updated about RF kill state */
1287 iwl_enable_rfkill_int(trans);
1288
fa9f3281
EG		 1289 /* Set is_down to false here so that...*/
1290 trans_pcie->is_down = false;
1291
8d425517 1292 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1293 if (hw_rfkill)
eb7ff77e 1294 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1295 else
eb7ff77e 1296 clear_bit(STATUS_RFKILL, &trans->status);
fa9f3281 1297 /* ... rfkill can call stop_device and set it false if needed */
14cfca71 1298 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1299
a8b691e6 1300 return 0;
e6bb4c9c
EG		 1301}
1302
fa9f3281
EG		 1303static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1304{
1305 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1306 int ret;
1307
1308 mutex_lock(&trans_pcie->mutex);
1309 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1310 mutex_unlock(&trans_pcie->mutex);
1311
1312 return ret;
1313}
1314
a4082843 1315static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1316{
20d3b647 1317 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1318
fa9f3281
EG		 1319 mutex_lock(&trans_pcie->mutex);
1320
a4082843 1321 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1322 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1323 iwl_disable_interrupts(trans);
7b70bd63 1324 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1325
b7aaeae4 1326 iwl_pcie_apm_stop(trans, true);
cc56feb2 1327
7b70bd63 1328 spin_lock(&trans_pcie->irq_lock);
218733cf 1329 iwl_disable_interrupts(trans);
7b70bd63 1330 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1331
8d96bb61 1332 iwl_pcie_disable_ict(trans);
33b56af1 1333
fa9f3281 1334 mutex_unlock(&trans_pcie->mutex);
33b56af1
EG		 1335
1336 synchronize_irq(trans_pcie->pci_dev->irq);
cc56feb2
EG		 1337}
1338
03905495
EG		 1339static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1340{
05f5b97e 1341 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1342}
1343
1344static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1345{
05f5b97e 1346 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1347}
1348
1349static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1350{
05f5b97e 1351 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1352}
1353
6a06b6c1
EG		 1354static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1355{
f9477c17
AP		 1356 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1357 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1358 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1359}
1360
1361static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1362 u32 val)
1363{
1364 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1365 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1366 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1367}
1368
f14d6b39
JB		 1369static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1370{
1371 WARN_ON(1);
1372 return 0;
1373}
1374
c6f600fc 1375static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1376 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1377{
1378 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1379
1380 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1381 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1382 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1383 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1384 trans_pcie->n_no_reclaim_cmds = 0;
1385 else
1386 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1387 if (trans_pcie->n_no_reclaim_cmds)
1388 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1389 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1390
b2cf410c
JB		 1391 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1392 if (trans_pcie->rx_buf_size_8k)
1393 trans_pcie->rx_page_order = get_order(8 * 1024);
1394 else
1395 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8 1396
ab02165c 1397 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
d9fb6465 1398 trans_pcie->command_names = trans_cfg->command_names;
046db346 1399 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1400 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39 1401
483f3ab1
EP		 1402 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1403 trans_pcie->ref_count = 1;
1404
f14d6b39
JB		 1405 /* Initialize NAPI here - it should be before registering to mac80211
1406 * in the opmode but after the HW struct is allocated.
1407 * As this function may be called again in some corner cases don't
1408 * do anything if NAPI was already initialized.
1409 */
1410 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1411 init_dummy_netdev(&trans_pcie->napi_dev);
1412 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1413 &trans_pcie->napi_dev,
1414 iwl_pcie_dummy_napi_poll, 64);
1415 }
c6f600fc
MV		 1416}
1417
d1ff5253 1418void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1419{
20d3b647 1420 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1421
0aa86df6 1422 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1423
f02831be 1424 iwl_pcie_tx_free(trans);
9805c446 1425 iwl_pcie_rx_free(trans);
6379103e 1426
a8b691e6
JB		 1427 free_irq(trans_pcie->pci_dev->irq, trans);
1428 iwl_pcie_free_ict(trans);
a42a1844
EG		 1429
1430 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1431 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1432 pci_release_regions(trans_pcie->pci_dev);
1433 pci_disable_device(trans_pcie->pci_dev);
1434
f14d6b39
JB		 1435 if (trans_pcie->napi.poll)
1436 netif_napi_del(&trans_pcie->napi);
1437
c2d20201
EG		 1438 iwl_pcie_free_fw_monitor(trans);
1439
7b501d10 1440 iwl_trans_free(trans);
34c1b7ba
EG		 1441}
1442
47107e84
DF		 1443static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1444{
47107e84 1445 if (state)
eb7ff77e 1446 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1447 else
eb7ff77e 1448 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1449}
1450
e56b04ef
LE		 1451static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1452 unsigned long *flags)
7a65d170
EG		 1453{
1454 int ret;
cfb4e624
JB		 1455 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1456
1457 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1458
fc8a350d 1459 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1460 goto out;
1461
7a65d170 1462 /* this bit wakes up the NIC */
e139dc4a
LE		 1463 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1464 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1465 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1466 udelay(2);
7a65d170
EG		 1467
1468 /*
1469 * These bits say the device is running, and should keep running for
1470 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1471 * but they do not indicate that embedded SRAM is restored yet;
1472 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1473 * to/from host DRAM when sleeping/waking for power-saving.
1474 * Each direction takes approximately 1/4 millisecond; with this
1475 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1476 * series of register accesses are expected (e.g. reading Event Log),
1477 * to keep device from sleeping.
1478 *
1479 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1480 * SRAM is okay/restored. We don't check that here because this call
1481 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1482 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1483 *
1484 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1485 * and do not save/restore SRAM when power cycling.
1486 */
1487 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1488 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1489 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1490 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1491 if (unlikely(ret < 0)) {
1492 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1493 if (!silent) {
1494 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1495 WARN_ONCE(1,
1496 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1497 val);
cfb4e624 1498 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1499 return false;
1500 }
1501 }
1502
b9439491 1503out:
e56b04ef
LE		 1504 /*
1505 * Fool sparse by faking we release the lock - sparse will
1506 * track nic_access anyway.
1507 */
cfb4e624 1508 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1509 return true;
1510}
1511
e56b04ef
LE		 1512static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1513 unsigned long *flags)
7a65d170 1514{
cfb4e624 1515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1516
cfb4e624 1517 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1518
1519 /*
1520 * Fool sparse by faking we acquiring the lock - sparse will
1521 * track nic_access anyway.
1522 */
cfb4e624 1523 __acquire(&trans_pcie->reg_lock);
e56b04ef 1524
fc8a350d 1525 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1526 goto out;
1527
e139dc4a
LE		 1528 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1529 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1530 /*
1531 * Above we read the CSR_GP_CNTRL register, which will flush
1532 * any previous writes, but we need the write that clears the
1533 * MAC_ACCESS_REQ bit to be performed before any other writes
1534 * scheduled on different CPUs (after we drop reg_lock).
1535 */
1536 mmiowb();
b9439491 1537out:
cfb4e624 1538 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1539}
1540
4fd442db
EG		 1541static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1542 void *buf, int dwords)
1543{
1544 unsigned long flags;
1545 int offs, ret = 0;
1546 u32 *vals = buf;
1547
e56b04ef 1548 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1549 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1550 for (offs = 0; offs < dwords; offs++)
1551 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1552 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1553 } else {
1554 ret = -EBUSY;
1555 }
4fd442db
EG		 1556 return ret;
1557}
1558
1559static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1560 const void *buf, int dwords)
4fd442db
EG		 1561{
1562 unsigned long flags;
1563 int offs, ret = 0;
bf0fd5da 1564 const u32 *vals = buf;
4fd442db 1565
e56b04ef 1566 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1567 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1568 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1569 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1570 vals ? vals[offs] : 0);
e56b04ef 1571 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1572 } else {
1573 ret = -EBUSY;
1574 }
4fd442db
EG		 1575 return ret;
1576}
7a65d170 1577
e0b8d405
EG		 1578static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1579 unsigned long txqs,
1580 bool freeze)
1581{
1582 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1583 int queue;
1584
1585 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1586 struct iwl_txq *txq = &trans_pcie->txq[queue];
1587 unsigned long now;
1588
1589 spin_lock_bh(&txq->lock);
1590
1591 now = jiffies;
1592
1593 if (txq->frozen == freeze)
1594 goto next_queue;
1595
1596 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1597 freeze ? "Freezing" : "Waking", queue);
1598
1599 txq->frozen = freeze;
1600
1601 if (txq->q.read_ptr == txq->q.write_ptr)
1602 goto next_queue;
1603
1604 if (freeze) {
1605 if (unlikely(time_after(now,
1606 txq->stuck_timer.expires))) {
1607 /*
1608 * The timer should have fired, maybe it is
1609 * spinning right now on the lock.
1610 */
1611 goto next_queue;
1612 }
1613 /* remember how long until the timer fires */
1614 txq->frozen_expiry_remainder =
1615 txq->stuck_timer.expires - now;
1616 del_timer(&txq->stuck_timer);
1617 goto next_queue;
1618 }
1619
1620 /*
1621 * Wake a non-empty queue -> arm timer with the
1622 * remainder before it froze
1623 */
1624 mod_timer(&txq->stuck_timer,
1625 now + txq->frozen_expiry_remainder);
1626
1627next_queue:
1628 spin_unlock_bh(&txq->lock);
1629 }
1630}
1631
5f178cd2
EG		 1632#define IWL_FLUSH_WAIT_MS 2000
1633
3cafdbe6 1634static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1635{
8ad71bef 1636 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1637 struct iwl_txq *txq;
5f178cd2
EG		 1638 struct iwl_queue *q;
1639 int cnt;
1640 unsigned long now = jiffies;
1c3fea82
EG		 1641 u32 scd_sram_addr;
1642 u8 buf[16];
5f178cd2
EG		 1643 int ret = 0;
1644
1645 /* waiting for all the tx frames complete might take a while */
035f7ff2 1646 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1647 u8 wr_ptr;
1648
9ba1947a 1649 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1650 continue;
3cafdbe6
EG		 1651 if (!test_bit(cnt, trans_pcie->queue_used))
1652 continue;
1653 if (!(BIT(cnt) & txq_bm))
1654 continue;
748fa67c
EG		 1655
1656 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1657 txq = &trans_pcie->txq[cnt];
5f178cd2 1658 q = &txq->q;
fa1a91fd
EG		 1659 wr_ptr = ACCESS_ONCE(q->write_ptr);
1660
1661 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1662 !time_after(jiffies,
1663 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1664 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1665
1666 if (WARN_ONCE(wr_ptr != write_ptr,
1667 "WR pointer moved while flushing %d -> %d\n",
1668 wr_ptr, write_ptr))
1669 return -ETIMEDOUT;
5f178cd2 1670 msleep(1);
fa1a91fd 1671 }
5f178cd2
EG		 1672
1673 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1674 IWL_ERR(trans,
1675 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1676 ret = -ETIMEDOUT;
1677 break;
1678 }
748fa67c 1679 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1680 }
1c3fea82
EG		 1681
1682 if (!ret)
1683 return 0;
1684
1685 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1686 txq->q.read_ptr, txq->q.write_ptr);
1687
1688 scd_sram_addr = trans_pcie->scd_base_addr +
1689 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1690 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1691
1692 iwl_print_hex_error(trans, buf, sizeof(buf));
1693
1694 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1695 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1696 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1697
1698 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1699 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1700 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1701 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1702 u32 tbl_dw =
1703 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1704 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1705
1706 if (cnt & 0x1)
1707 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1708 else
1709 tbl_dw = tbl_dw & 0x0000FFFF;
1710
1711 IWL_ERR(trans,
1712 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1713 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1714 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1715 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1716 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1717 }
1718
5f178cd2
EG		 1719 return ret;
1720}
1721
e139dc4a
LE		 1722static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1723 u32 mask, u32 value)
1724{
e56b04ef 1725 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1726 unsigned long flags;
1727
e56b04ef 1728 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1729 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1730 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1731}
1732
7616f334
EP		 1733void iwl_trans_pcie_ref(struct iwl_trans *trans)
1734{
1735 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1736 unsigned long flags;
1737
1738 if (iwlwifi_mod_params.d0i3_disable)
1739 return;
1740
1741 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1742 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1743 trans_pcie->ref_count++;
1744 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1745}
1746
1747void iwl_trans_pcie_unref(struct iwl_trans *trans)
1748{
1749 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1750 unsigned long flags;
1751
1752 if (iwlwifi_mod_params.d0i3_disable)
1753 return;
1754
1755 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1756 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1757 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1758 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1759 return;
1760 }
1761 trans_pcie->ref_count--;
1762 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1763}
1764
ff620849
EG		 1765static const char *get_csr_string(int cmd)
1766{
d9fb6465 1767#define IWL_CMD(x) case x: return #x
ff620849
EG		 1768 switch (cmd) {
1769 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1770 IWL_CMD(CSR_INT_COALESCING);
1771 IWL_CMD(CSR_INT);
1772 IWL_CMD(CSR_INT_MASK);
1773 IWL_CMD(CSR_FH_INT_STATUS);
1774 IWL_CMD(CSR_GPIO_IN);
1775 IWL_CMD(CSR_RESET);
1776 IWL_CMD(CSR_GP_CNTRL);
1777 IWL_CMD(CSR_HW_REV);
1778 IWL_CMD(CSR_EEPROM_REG);
1779 IWL_CMD(CSR_EEPROM_GP);
1780 IWL_CMD(CSR_OTP_GP_REG);
1781 IWL_CMD(CSR_GIO_REG);
1782 IWL_CMD(CSR_GP_UCODE_REG);
1783 IWL_CMD(CSR_GP_DRIVER_REG);
1784 IWL_CMD(CSR_UCODE_DRV_GP1);
1785 IWL_CMD(CSR_UCODE_DRV_GP2);
1786 IWL_CMD(CSR_LED_REG);
1787 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1788 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1789 IWL_CMD(CSR_ANA_PLL_CFG);
1790 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1791 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1792 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1793 default:
1794 return "UNKNOWN";
1795 }
d9fb6465 1796#undef IWL_CMD
ff620849
EG		 1797}
1798
990aa6d7 1799void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1800{
1801 int i;
1802 static const u32 csr_tbl[] = {
1803 CSR_HW_IF_CONFIG_REG,
1804 CSR_INT_COALESCING,
1805 CSR_INT,
1806 CSR_INT_MASK,
1807 CSR_FH_INT_STATUS,
1808 CSR_GPIO_IN,
1809 CSR_RESET,
1810 CSR_GP_CNTRL,
1811 CSR_HW_REV,
1812 CSR_EEPROM_REG,
1813 CSR_EEPROM_GP,
1814 CSR_OTP_GP_REG,
1815 CSR_GIO_REG,
1816 CSR_GP_UCODE_REG,
1817 CSR_GP_DRIVER_REG,
1818 CSR_UCODE_DRV_GP1,
1819 CSR_UCODE_DRV_GP2,
1820 CSR_LED_REG,
1821 CSR_DRAM_INT_TBL_REG,
1822 CSR_GIO_CHICKEN_BITS,
1823 CSR_ANA_PLL_CFG,
a812cba9 1824 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1825 CSR_HW_REV_WA_REG,
1826 CSR_DBG_HPET_MEM_REG
1827 };
1828 IWL_ERR(trans, "CSR values:\n");
1829 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1830 "CSR_INT_PERIODIC_REG)\n");
1831 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1832 IWL_ERR(trans, " %25s: 0X%08x\n",
1833 get_csr_string(csr_tbl[i]),
1042db2a 1834 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1835 }
1836}
1837
87e5666c
EG		 1838#ifdef CONFIG_IWLWIFI_DEBUGFS
1839/* create and remove of files */
1840#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1841 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1842 &iwl_dbgfs_##name##_ops)) \
9da987ac 1843 goto err; \
87e5666c
EG		 1844} while (0)
1845
1846/* file operation */
87e5666c 1847#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1848static const struct file_operations iwl_dbgfs_##name##_ops = { \
1849 .read = iwl_dbgfs_##name##_read, \
234e3405 1850 .open = simple_open, \
87e5666c
EG		 1851 .llseek = generic_file_llseek, \
1852};
1853
16db88ba 1854#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1855static const struct file_operations iwl_dbgfs_##name##_ops = { \
1856 .write = iwl_dbgfs_##name##_write, \
234e3405 1857 .open = simple_open, \
16db88ba
EG		 1858 .llseek = generic_file_llseek, \
1859};
1860
87e5666c 1861#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1862static const struct file_operations iwl_dbgfs_##name##_ops = { \
1863 .write = iwl_dbgfs_##name##_write, \
1864 .read = iwl_dbgfs_##name##_read, \
234e3405 1865 .open = simple_open, \
87e5666c
EG		 1866 .llseek = generic_file_llseek, \
1867};
1868
87e5666c 1869static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1870 char __user *user_buf,
1871 size_t count, loff_t *ppos)
8ad71bef 1872{
5a878bf6 1873 struct iwl_trans *trans = file->private_data;
8ad71bef 1874 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1875 struct iwl_txq *txq;
87e5666c
EG		 1876 struct iwl_queue *q;
1877 char *buf;
1878 int pos = 0;
1879 int cnt;
1880 int ret;
1745e440
WYG		 1881 size_t bufsz;
1882
e0b8d405 1883 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 1884
f9e75447 1885 if (!trans_pcie->txq)
87e5666c 1886 return -EAGAIN;
f9e75447 1887
87e5666c
EG		 1888 buf = kzalloc(bufsz, GFP_KERNEL);
1889 if (!buf)
1890 return -ENOMEM;
1891
035f7ff2 1892 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1893 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1894 q = &txq->q;
1895 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 1896 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 1897 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1898 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 1899 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 1900 txq->need_update, txq->frozen,
f40faf62 1901 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1902 }
1903 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1904 kfree(buf);
1905 return ret;
1906}
1907
1908static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1909 char __user *user_buf,
1910 size_t count, loff_t *ppos)
1911{
5a878bf6 1912 struct iwl_trans *trans = file->private_data;
20d3b647 1913 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1914 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1915 char buf[256];
1916 int pos = 0;
1917 const size_t bufsz = sizeof(buf);
1918
1919 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1920 rxq->read);
1921 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1922 rxq->write);
f40faf62
AL		 1923 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1924 rxq->write_actual);
1925 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1926 rxq->need_update);
87e5666c
EG		 1927 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1928 rxq->free_count);
1929 if (rxq->rb_stts) {
1930 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1931 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1932 } else {
1933 pos += scnprintf(buf + pos, bufsz - pos,
1934 "closed_rb_num: Not Allocated\n");
1935 }
1936 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1937}
1938
1f7b6172
EG		 1939static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1940 char __user *user_buf,
20d3b647
JB		 1941 size_t count, loff_t *ppos)
1942{
1f7b6172 1943 struct iwl_trans *trans = file->private_data;
20d3b647 1944 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1945 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1946
1947 int pos = 0;
1948 char *buf;
1949 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1950 ssize_t ret;
1951
1952 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1953 if (!buf)
1f7b6172 1954 return -ENOMEM;
1f7b6172
EG		 1955
1956 pos += scnprintf(buf + pos, bufsz - pos,
1957 "Interrupt Statistics Report:\n");
1958
1959 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1960 isr_stats->hw);
1961 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1962 isr_stats->sw);
1963 if (isr_stats->sw || isr_stats->hw) {
1964 pos += scnprintf(buf + pos, bufsz - pos,
1965 "\tLast Restarting Code: 0x%X\n",
1966 isr_stats->err_code);
1967 }
1968#ifdef CONFIG_IWLWIFI_DEBUG
1969 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1970 isr_stats->sch);
1971 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1972 isr_stats->alive);
1973#endif
1974 pos += scnprintf(buf + pos, bufsz - pos,
1975 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1976
1977 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1978 isr_stats->ctkill);
1979
1980 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1981 isr_stats->wakeup);
1982
1983 pos += scnprintf(buf + pos, bufsz - pos,
1984 "Rx command responses:\t\t %u\n", isr_stats->rx);
1985
1986 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1987 isr_stats->tx);
1988
1989 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1990 isr_stats->unhandled);
1991
1992 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1993 kfree(buf);
1994 return ret;
1995}
1996
1997static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1998 const char __user *user_buf,
1999 size_t count, loff_t *ppos)
2000{
2001 struct iwl_trans *trans = file->private_data;
20d3b647 2002 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2003 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2004
2005 char buf[8];
2006 int buf_size;
2007 u32 reset_flag;
2008
2009 memset(buf, 0, sizeof(buf));
2010 buf_size = min(count, sizeof(buf) - 1);
2011 if (copy_from_user(buf, user_buf, buf_size))
2012 return -EFAULT;
2013 if (sscanf(buf, "%x", &reset_flag) != 1)
2014 return -EFAULT;
2015 if (reset_flag == 0)
2016 memset(isr_stats, 0, sizeof(*isr_stats));
2017
2018 return count;
2019}
2020
16db88ba 2021static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2022 const char __user *user_buf,
2023 size_t count, loff_t *ppos)
16db88ba
EG		 2024{
2025 struct iwl_trans *trans = file->private_data;
2026 char buf[8];
2027 int buf_size;
2028 int csr;
2029
2030 memset(buf, 0, sizeof(buf));
2031 buf_size = min(count, sizeof(buf) - 1);
2032 if (copy_from_user(buf, user_buf, buf_size))
2033 return -EFAULT;
2034 if (sscanf(buf, "%d", &csr) != 1)
2035 return -EFAULT;
2036
990aa6d7 2037 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2038
2039 return count;
2040}
2041
16db88ba 2042static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2043 char __user *user_buf,
2044 size_t count, loff_t *ppos)
16db88ba
EG		 2045{
2046 struct iwl_trans *trans = file->private_data;
94543a8d 2047 char *buf = NULL;
56c2477f 2048 ssize_t ret;
16db88ba 2049
56c2477f
JB		 2050 ret = iwl_dump_fh(trans, &buf);
2051 if (ret < 0)
2052 return ret;
2053 if (!buf)
2054 return -EINVAL;
2055 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2056 kfree(buf);
16db88ba
EG		 2057 return ret;
2058}
2059
1f7b6172 2060DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2061DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2062DEBUGFS_READ_FILE_OPS(rx_queue);
2063DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2064DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 2065
2066/*
2067 * Create the debugfs files and directories
2068 *
2069 */
2070static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 2071 struct dentry *dir)
87e5666c 2072{
87e5666c
EG		 2073 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2074 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2075 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2076 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2077 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2078 return 0;
9da987ac
MV		 2079
2080err:
2081 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2082 return -ENOMEM;
87e5666c 2083}
aadede6e
JB		 2084#else
2085static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2086 struct dentry *dir)
2087{
2088 return 0;
2089}
2090#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2091
2092static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2093{
2094 u32 cmdlen = 0;
2095 int i;
2096
2097 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2098 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2099
2100 return cmdlen;
2101}
2102
67c65f2c
EG		 2103static const struct {
2104 u32 start, end;
2105} iwl_prph_dump_addr[] = {
2106 { .start = 0x00a00000, .end = 0x00a00000 },
2107 { .start = 0x00a0000c, .end = 0x00a00024 },
2108 { .start = 0x00a0002c, .end = 0x00a0003c },
2109 { .start = 0x00a00410, .end = 0x00a00418 },
2110 { .start = 0x00a00420, .end = 0x00a00420 },
2111 { .start = 0x00a00428, .end = 0x00a00428 },
2112 { .start = 0x00a00430, .end = 0x00a0043c },
2113 { .start = 0x00a00444, .end = 0x00a00444 },
2114 { .start = 0x00a004c0, .end = 0x00a004cc },
2115 { .start = 0x00a004d8, .end = 0x00a004d8 },
2116 { .start = 0x00a004e0, .end = 0x00a004f0 },
2117 { .start = 0x00a00840, .end = 0x00a00840 },
2118 { .start = 0x00a00850, .end = 0x00a00858 },
2119 { .start = 0x00a01004, .end = 0x00a01008 },
2120 { .start = 0x00a01010, .end = 0x00a01010 },
2121 { .start = 0x00a01018, .end = 0x00a01018 },
2122 { .start = 0x00a01024, .end = 0x00a01024 },
2123 { .start = 0x00a0102c, .end = 0x00a01034 },
2124 { .start = 0x00a0103c, .end = 0x00a01040 },
2125 { .start = 0x00a01048, .end = 0x00a01094 },
2126 { .start = 0x00a01c00, .end = 0x00a01c20 },
2127 { .start = 0x00a01c58, .end = 0x00a01c58 },
2128 { .start = 0x00a01c7c, .end = 0x00a01c7c },
2129 { .start = 0x00a01c28, .end = 0x00a01c54 },
2130 { .start = 0x00a01c5c, .end = 0x00a01c5c },
6a65bd53 2131 { .start = 0x00a01c60, .end = 0x00a01cdc },
67c65f2c
EG		 2132 { .start = 0x00a01ce0, .end = 0x00a01d0c },
2133 { .start = 0x00a01d18, .end = 0x00a01d20 },
2134 { .start = 0x00a01d2c, .end = 0x00a01d30 },
2135 { .start = 0x00a01d40, .end = 0x00a01d5c },
2136 { .start = 0x00a01d80, .end = 0x00a01d80 },
6a65bd53
EG		 2137 { .start = 0x00a01d98, .end = 0x00a01d9c },
2138 { .start = 0x00a01da8, .end = 0x00a01da8 },
2139 { .start = 0x00a01db8, .end = 0x00a01df4 },
67c65f2c
EG		 2140 { .start = 0x00a01dc0, .end = 0x00a01dfc },
2141 { .start = 0x00a01e00, .end = 0x00a01e2c },
2142 { .start = 0x00a01e40, .end = 0x00a01e60 },
6a65bd53
EG		 2143 { .start = 0x00a01e68, .end = 0x00a01e6c },
2144 { .start = 0x00a01e74, .end = 0x00a01e74 },
67c65f2c
EG		 2145 { .start = 0x00a01e84, .end = 0x00a01e90 },
2146 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
6a65bd53
EG		 2147 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2148 { .start = 0x00a01f00, .end = 0x00a01f1c },
2149 { .start = 0x00a01f44, .end = 0x00a01ffc },
67c65f2c
EG		 2150 { .start = 0x00a02000, .end = 0x00a02048 },
2151 { .start = 0x00a02068, .end = 0x00a020f0 },
2152 { .start = 0x00a02100, .end = 0x00a02118 },
2153 { .start = 0x00a02140, .end = 0x00a0214c },
2154 { .start = 0x00a02168, .end = 0x00a0218c },
2155 { .start = 0x00a021c0, .end = 0x00a021c0 },
2156 { .start = 0x00a02400, .end = 0x00a02410 },
2157 { .start = 0x00a02418, .end = 0x00a02420 },
2158 { .start = 0x00a02428, .end = 0x00a0242c },
2159 { .start = 0x00a02434, .end = 0x00a02434 },
2160 { .start = 0x00a02440, .end = 0x00a02460 },
2161 { .start = 0x00a02468, .end = 0x00a024b0 },
2162 { .start = 0x00a024c8, .end = 0x00a024cc },
2163 { .start = 0x00a02500, .end = 0x00a02504 },
2164 { .start = 0x00a0250c, .end = 0x00a02510 },
2165 { .start = 0x00a02540, .end = 0x00a02554 },
2166 { .start = 0x00a02580, .end = 0x00a025f4 },
2167 { .start = 0x00a02600, .end = 0x00a0260c },
2168 { .start = 0x00a02648, .end = 0x00a02650 },
2169 { .start = 0x00a02680, .end = 0x00a02680 },
2170 { .start = 0x00a026c0, .end = 0x00a026d0 },
2171 { .start = 0x00a02700, .end = 0x00a0270c },
2172 { .start = 0x00a02804, .end = 0x00a02804 },
2173 { .start = 0x00a02818, .end = 0x00a0281c },
2174 { .start = 0x00a02c00, .end = 0x00a02db4 },
2175 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2176 { .start = 0x00a03000, .end = 0x00a03014 },
2177 { .start = 0x00a0301c, .end = 0x00a0302c },
2178 { .start = 0x00a03034, .end = 0x00a03038 },
2179 { .start = 0x00a03040, .end = 0x00a03048 },
2180 { .start = 0x00a03060, .end = 0x00a03068 },
2181 { .start = 0x00a03070, .end = 0x00a03074 },
2182 { .start = 0x00a0307c, .end = 0x00a0307c },
2183 { .start = 0x00a03080, .end = 0x00a03084 },
2184 { .start = 0x00a0308c, .end = 0x00a03090 },
2185 { .start = 0x00a03098, .end = 0x00a03098 },
2186 { .start = 0x00a030a0, .end = 0x00a030a0 },
2187 { .start = 0x00a030a8, .end = 0x00a030b4 },
2188 { .start = 0x00a030bc, .end = 0x00a030bc },
2189 { .start = 0x00a030c0, .end = 0x00a0312c },
2190 { .start = 0x00a03c00, .end = 0x00a03c5c },
2191 { .start = 0x00a04400, .end = 0x00a04454 },
2192 { .start = 0x00a04460, .end = 0x00a04474 },
2193 { .start = 0x00a044c0, .end = 0x00a044ec },
2194 { .start = 0x00a04500, .end = 0x00a04504 },
2195 { .start = 0x00a04510, .end = 0x00a04538 },
2196 { .start = 0x00a04540, .end = 0x00a04548 },
2197 { .start = 0x00a04560, .end = 0x00a0457c },
2198 { .start = 0x00a04590, .end = 0x00a04598 },
2199 { .start = 0x00a045c0, .end = 0x00a045f4 },
2200};
2201
2202static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2203 struct iwl_fw_error_dump_data **data)
2204{
2205 struct iwl_fw_error_dump_prph *prph;
2206 unsigned long flags;
2207 u32 prph_len = 0, i;
2208
2209 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2210 return 0;
2211
2212 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2213 /* The range includes both boundaries */
2214 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2215 iwl_prph_dump_addr[i].start + 4;
2216 int reg;
2217 __le32 *val;
2218
87dd634a 2219 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 2220
2221 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2222 (*data)->len = cpu_to_le32(sizeof(*prph) +
2223 num_bytes_in_chunk);
2224 prph = (void *)(*data)->data;
2225 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2226 val = (void *)prph->data;
2227
2228 for (reg = iwl_prph_dump_addr[i].start;
2229 reg <= iwl_prph_dump_addr[i].end;
2230 reg += 4)
2231 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2232 reg));
2233 *data = iwl_fw_error_next_data(*data);
2234 }
2235
2236 iwl_trans_release_nic_access(trans, &flags);
2237
2238 return prph_len;
2239}
2240
473ad712
EG		 2241#define IWL_CSR_TO_DUMP (0x250)
2242
2243static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2244 struct iwl_fw_error_dump_data **data)
2245{
2246 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2247 __le32 *val;
2248 int i;
2249
2250 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2251 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2252 val = (void *)(*data)->data;
2253
2254 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2255 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2256
2257 *data = iwl_fw_error_next_data(*data);
2258
2259 return csr_len;
2260}
2261
06d51e0d
LK		 2262static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2263 struct iwl_fw_error_dump_data **data)
2264{
2265 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2266 unsigned long flags;
2267 __le32 *val;
2268 int i;
2269
2270 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2271 return 0;
2272
2273 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2274 (*data)->len = cpu_to_le32(fh_regs_len);
2275 val = (void *)(*data)->data;
2276
2277 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2278 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2279
2280 iwl_trans_release_nic_access(trans, &flags);
2281
2282 *data = iwl_fw_error_next_data(*data);
2283
2284 return sizeof(**data) + fh_regs_len;
2285}
2286
cc79ef66
LK		 2287static u32
2288iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2289 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2290 u32 monitor_len)
2291{
2292 u32 buf_size_in_dwords = (monitor_len >> 2);
2293 u32 *buffer = (u32 *)fw_mon_data->data;
2294 unsigned long flags;
2295 u32 i;
2296
2297 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2298 return 0;
2299
2300 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2301 for (i = 0; i < buf_size_in_dwords; i++)
2302 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2303 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2304
2305 iwl_trans_release_nic_access(trans, &flags);
2306
2307 return monitor_len;
2308}
2309
48eb7b34
EG		 2310static
2311struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
4d075007
JB		 2312{
2313 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2314 struct iwl_fw_error_dump_data *data;
2315 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2316 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2317 struct iwl_trans_dump_data *dump_data;
4d075007 2318 u32 len;
99684ae3 2319 u32 monitor_len;
4d075007
JB		 2320 int i, ptr;
2321
473ad712
EG		 2322 /* transport dump header */
2323 len = sizeof(*dump_data);
2324
2325 /* host commands */
2326 len += sizeof(*data) +
c2d20201
EG		 2327 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2328
473ad712
EG		 2329 /* CSR registers */
2330 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2331
2332 /* PRPH registers */
67c65f2c
EG		 2333 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2334 /* The range includes both boundaries */
2335 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2336 iwl_prph_dump_addr[i].start + 4;
2337
2338 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2339 num_bytes_in_chunk;
2340 }
2341
06d51e0d
LK		 2342 /* FH registers */
2343 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2344
473ad712 2345 /* FW monitor */
99684ae3 2346 if (trans_pcie->fw_mon_page) {
c544e9c4 2347 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2348 trans_pcie->fw_mon_size;
2349 monitor_len = trans_pcie->fw_mon_size;
2350 } else if (trans->dbg_dest_tlv) {
2351 u32 base, end;
2352
2353 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2354 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2355
2356 base = iwl_read_prph(trans, base) <<
2357 trans->dbg_dest_tlv->base_shift;
2358 end = iwl_read_prph(trans, end) <<
2359 trans->dbg_dest_tlv->end_shift;
2360
2361 /* Make "end" point to the actual end */
cc79ef66
LK		 2362 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2363 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2364 end += (1 << trans->dbg_dest_tlv->end_shift);
2365 monitor_len = end - base;
2366 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2367 monitor_len;
2368 } else {
2369 monitor_len = 0;
2370 }
c2d20201 2371
48eb7b34
EG		 2372 dump_data = vzalloc(len);
2373 if (!dump_data)
2374 return NULL;
4d075007
JB		 2375
2376 len = 0;
48eb7b34 2377 data = (void *)dump_data->data;
4d075007
JB		 2378 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2379 txcmd = (void *)data->data;
2380 spin_lock_bh(&cmdq->lock);
2381 ptr = cmdq->q.write_ptr;
2382 for (i = 0; i < cmdq->q.n_window; i++) {
2383 u8 idx = get_cmd_index(&cmdq->q, ptr);
2384 u32 caplen, cmdlen;
2385
2386 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2387 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2388
2389 if (cmdlen) {
2390 len += sizeof(*txcmd) + caplen;
2391 txcmd->cmdlen = cpu_to_le32(cmdlen);
2392 txcmd->caplen = cpu_to_le32(caplen);
2393 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2394 txcmd = (void *)((u8 *)txcmd->data + caplen);
2395 }
2396
2397 ptr = iwl_queue_dec_wrap(ptr);
2398 }
2399 spin_unlock_bh(&cmdq->lock);
2400
2401 data->len = cpu_to_le32(len);
c2d20201 2402 len += sizeof(*data);
67c65f2c
EG		 2403 data = iwl_fw_error_next_data(data);
2404
2405 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2406 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2407 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
67c65f2c 2408 /* data is already pointing to the next section */
c2d20201 2409
99684ae3
LK		 2410 if ((trans_pcie->fw_mon_page &&
2411 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2412 trans->dbg_dest_tlv) {
c544e9c4 2413 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
99684ae3
LK		 2414 u32 base, write_ptr, wrap_cnt;
2415
2416 /* If there was a dest TLV - use the values from there */
2417 if (trans->dbg_dest_tlv) {
2418 write_ptr =
2419 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2420 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2421 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2422 } else {
2423 base = MON_BUFF_BASE_ADDR;
2424 write_ptr = MON_BUFF_WRPTR;
2425 wrap_cnt = MON_BUFF_CYCLE_CNT;
2426 }
c2d20201 2427
c2d20201 2428 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
c2d20201
EG		 2429 fw_mon_data = (void *)data->data;
2430 fw_mon_data->fw_mon_wr_ptr =
99684ae3 2431 cpu_to_le32(iwl_read_prph(trans, write_ptr));
c2d20201 2432 fw_mon_data->fw_mon_cycle_cnt =
99684ae3 2433 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
c2d20201 2434 fw_mon_data->fw_mon_base_ptr =
99684ae3
LK		 2435 cpu_to_le32(iwl_read_prph(trans, base));
2436
2437 len += sizeof(*data) + sizeof(*fw_mon_data);
2438 if (trans_pcie->fw_mon_page) {
99684ae3
LK		 2439 /*
2440 * The firmware is now asserted, it won't write anything
2441 * to the buffer. CPU can take ownership to fetch the
2442 * data. The buffer will be handed back to the device
2443 * before the firmware will be restarted.
2444 */
2445 dma_sync_single_for_cpu(trans->dev,
2446 trans_pcie->fw_mon_phys,
2447 trans_pcie->fw_mon_size,
2448 DMA_FROM_DEVICE);
2449 memcpy(fw_mon_data->data,
2450 page_address(trans_pcie->fw_mon_page),
2451 trans_pcie->fw_mon_size);
2452
cc79ef66
LK		 2453 monitor_len = trans_pcie->fw_mon_size;
2454 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
99684ae3
LK		 2455 /*
2456 * Update pointers to reflect actual values after
2457 * shifting
2458 */
2459 base = iwl_read_prph(trans, base) <<
2460 trans->dbg_dest_tlv->base_shift;
2461 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2462 monitor_len / sizeof(u32));
cc79ef66
LK		 2463 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2464 monitor_len =
2465 iwl_trans_pci_dump_marbh_monitor(trans,
2466 fw_mon_data,
2467 monitor_len);
2468 } else {
2469 /* Didn't match anything - output no monitor data */
2470 monitor_len = 0;
99684ae3 2471 }
cc79ef66
LK		 2472
2473 len += monitor_len;
2474 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
c2d20201
EG		 2475 }
2476
48eb7b34
EG		 2477 dump_data->len = len;
2478
2479 return dump_data;
4d075007 2480}
87e5666c 2481
d1ff5253 2482static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2483 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2484 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2485 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2486 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2487 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2488
ddaf5a5b
JB		 2489 .d3_suspend = iwl_trans_pcie_d3_suspend,
2490 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2491
f02831be 2492 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2493
e6bb4c9c 2494 .tx = iwl_trans_pcie_tx,
a0eaad71 2495 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2496
d0624be6 2497 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2498 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2499
87e5666c 2500 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2501
990aa6d7 2502 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2503 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
5f178cd2 2504
03905495
EG		 2505 .write8 = iwl_trans_pcie_write8,
2506 .write32 = iwl_trans_pcie_write32,
2507 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2508 .read_prph = iwl_trans_pcie_read_prph,
2509 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2510 .read_mem = iwl_trans_pcie_read_mem,
2511 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2512 .configure = iwl_trans_pcie_configure,
47107e84 2513 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2514 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2515 .release_nic_access = iwl_trans_pcie_release_nic_access,
2516 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2517
7616f334
EP		 2518 .ref = iwl_trans_pcie_ref,
2519 .unref = iwl_trans_pcie_unref,
2520
4d075007 2521 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2522};
a42a1844 2523
87ce05a2 2524struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2525 const struct pci_device_id *ent,
2526 const struct iwl_cfg *cfg)
a42a1844 2527{
a42a1844
EG		 2528 struct iwl_trans_pcie *trans_pcie;
2529 struct iwl_trans *trans;
2530 u16 pci_cmd;
2531 int err;
2532
7b501d10
JB		 2533 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2534 &pdev->dev, cfg, &trans_ops_pcie, 0);
2535 if (!trans)
2536 return ERR_PTR(-ENOMEM);
a42a1844
EG		 2537
2538 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2539
a42a1844 2540 trans_pcie->trans = trans;
7b11488f 2541 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2542 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2543 spin_lock_init(&trans_pcie->ref_lock);
fa9f3281 2544 mutex_init(&trans_pcie->mutex);
13df1aab 2545 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2546
d819c6cf
JB		 2547 err = pci_enable_device(pdev);
2548 if (err)
2549 goto out_no_pci;
2550
f2532b04
EG		 2551 if (!cfg->base_params->pcie_l1_allowed) {
2552 /*
2553 * W/A - seems to solve weird behavior. We need to remove this
2554 * if we don't want to stay in L1 all the time. This wastes a
2555 * lot of power.
2556 */
2557 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2558 PCIE_LINK_STATE_L1 |
2559 PCIE_LINK_STATE_CLKPM);
2560 }
a42a1844 2561
a42a1844
EG		 2562 pci_set_master(pdev);
2563
2564 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2565 if (!err)
2566 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2567 if (err) {
2568 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2569 if (!err)
2570 err = pci_set_consistent_dma_mask(pdev,
20d3b647 2571 DMA_BIT_MASK(32));
a42a1844
EG		 2572 /* both attempts failed: */
2573 if (err) {
6a4b09f8 2574 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2575 goto out_pci_disable_device;
2576 }
2577 }
2578
2579 err = pci_request_regions(pdev, DRV_NAME);
2580 if (err) {
6a4b09f8 2581 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2582 goto out_pci_disable_device;
2583 }
2584
05f5b97e 2585 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2586 if (!trans_pcie->hw_base) {
6a4b09f8 2587 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
a42a1844
EG		 2588 err = -ENODEV;
2589 goto out_pci_release_regions;
2590 }
2591
a42a1844
EG		 2592 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2593 * PCI Tx retries from interfering with C3 CPU state */
2594 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2595
83f7a85f
EG		 2596 trans->dev = &pdev->dev;
2597 trans_pcie->pci_dev = pdev;
2598 iwl_disable_interrupts(trans);
2599
a42a1844 2600 err = pci_enable_msi(pdev);
9f904b38 2601 if (err) {
6a4b09f8 2602 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
9f904b38
EG		 2603 /* enable rfkill interrupt: hw bug w/a */
2604 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2605 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2606 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2607 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2608 }
2609 }
a42a1844 2610
08079a49 2611 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2612 /*
2613 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2614 * changed, and now the revision step also includes bit 0-1 (no more
2615 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2616 * in the old format.
2617 */
7a42baa6
EH		 2618 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2619 unsigned long flags;
2620 int ret;
2621
b513ee7f 2622 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2623 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2624
7a42baa6
EH		 2625 /*
2626 * in-order to recognize C step driver should read chip version
2627 * id located at the AUX bus MISC address space.
2628 */
2629 iwl_set_bit(trans, CSR_GP_CNTRL,
2630 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2631 udelay(2);
2632
2633 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2634 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2635 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2636 25000);
2637 if (ret < 0) {
2638 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2639 goto out_pci_disable_msi;
2640 }
2641
2642 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2643 u32 hw_step;
2644
2645 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2646 hw_step |= ENABLE_WFPM;
2647 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2648 hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2649 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2650 if (hw_step == 0x3)
2651 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2652 (SILICON_C_STEP << 2);
2653 iwl_trans_release_nic_access(trans, &flags);
2654 }
2655 }
2656
99673ee5 2657 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2658 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2659 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2660
69a10b29 2661 /* Initialize the wait queue for commands */
f946b529 2662 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2663
a8b691e6 2664 if (iwl_pcie_alloc_ict(trans))
7b501d10 2665 goto out_pci_disable_msi;
a8b691e6 2666
85bf9da1 2667 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2668 iwl_pcie_irq_handler,
2669 IRQF_SHARED, DRV_NAME, trans);
2670 if (err) {
a8b691e6
JB		 2671 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2672 goto out_free_ict;
2673 }
2674
83f7a85f 2675 trans_pcie->inta_mask = CSR_INI_SET_MASK;
6735943f 2676 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
83f7a85f 2677
a42a1844
EG		 2678 return trans;
2679
a8b691e6
JB		 2680out_free_ict:
2681 iwl_pcie_free_ict(trans);
59c647b6
EG		 2682out_pci_disable_msi:
2683 pci_disable_msi(pdev);
a42a1844
EG		 2684out_pci_release_regions:
2685 pci_release_regions(pdev);
2686out_pci_disable_device:
2687 pci_disable_device(pdev);
2688out_no_pci:
7b501d10 2689 iwl_trans_free(trans);
6965a354 2690 return ERR_PTR(err);
a42a1844 2691}
Linux 6.x block layer and io_uring tree(s)