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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
4e318262 | 8 | * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
4e318262 | 33 | * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
82575102 | 71 | #include "iwl-drv.h" |
c85eb619 | 72 | #include "iwl-trans.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
7a10e3e4 | 75 | #include "iwl-agn-hw.h" |
6468a01a | 76 | #include "internal.h" |
0439bb62 | 77 | |
7afe3705 | 78 | static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans) |
392f8b78 EG |
79 | { |
80 | /* | |
81 | * (for documentation purposes) | |
82 | * to set power to V_AUX, do: | |
83 | ||
84 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
1042db2a | 85 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
86 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
87 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
88 | */ | |
89 | ||
1042db2a | 90 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
91 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
92 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
93 | } | |
94 | ||
af634bee EG |
95 | /* PCI registers */ |
96 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 97 | |
7afe3705 | 98 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 99 | { |
20d3b647 | 100 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 101 | u16 lctl; |
af634bee | 102 | |
af634bee EG |
103 | /* |
104 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
105 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
106 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
107 | * costs negligible amount of power savings. | |
108 | * If not (unlikely), enable L0S, so there is at least some | |
109 | * power savings, even without L1. | |
110 | */ | |
7afe3705 | 111 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
438a0f0a | 112 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { |
af634bee EG |
113 | /* L1-ASPM enabled; disable(!) L0S */ |
114 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 115 | dev_info(trans->dev, "L1 Enabled; Disabling L0S\n"); |
af634bee EG |
116 | } else { |
117 | /* L1-ASPM disabled; enable(!) L0S */ | |
118 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 119 | dev_info(trans->dev, "L1 Disabled; Enabling L0S\n"); |
af634bee | 120 | } |
438a0f0a | 121 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
af634bee EG |
122 | } |
123 | ||
a6c684ee EG |
124 | /* |
125 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 126 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
127 | * NOTE: This does not load uCode nor start the embedded processor |
128 | */ | |
7afe3705 | 129 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee | 130 | { |
83626404 | 131 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a6c684ee EG |
132 | int ret = 0; |
133 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
134 | ||
135 | /* | |
136 | * Use "set_bit" below rather than "write", to preserve any hardware | |
137 | * bits already set by default after reset. | |
138 | */ | |
139 | ||
140 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
141 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 142 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
a6c684ee EG |
143 | |
144 | /* | |
145 | * Disable L0s without affecting L1; | |
146 | * don't wait for ICH L0s (ICH bug W/A) | |
147 | */ | |
148 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 149 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
150 | |
151 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
152 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
153 | ||
154 | /* | |
155 | * Enable HAP INTA (interrupt from management bus) to | |
156 | * wake device's PCI Express link L1a -> L0s | |
157 | */ | |
158 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 159 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 160 | |
7afe3705 | 161 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
162 | |
163 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 164 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 165 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 166 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
167 | |
168 | /* | |
169 | * Set "initialization complete" bit to move adapter from | |
170 | * D0U* --> D0A* (powered-up active) state. | |
171 | */ | |
172 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
173 | ||
174 | /* | |
175 | * Wait for clock stabilization; once stabilized, access to | |
176 | * device-internal resources is supported, e.g. iwl_write_prph() | |
177 | * and accesses to uCode SRAM. | |
178 | */ | |
179 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
180 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
181 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
182 | if (ret < 0) { |
183 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
184 | goto out; | |
185 | } | |
186 | ||
187 | /* | |
188 | * Enable DMA clock and wait for it to stabilize. | |
189 | * | |
190 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
191 | * do not disable clocks. This preserves any hardware bits already | |
192 | * set by default in "CLK_CTRL_REG" after reset. | |
193 | */ | |
194 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
195 | udelay(20); | |
196 | ||
197 | /* Disable L1-Active */ | |
198 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
199 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
200 | ||
83626404 | 201 | set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
a6c684ee EG |
202 | |
203 | out: | |
204 | return ret; | |
205 | } | |
206 | ||
7afe3705 | 207 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
208 | { |
209 | int ret = 0; | |
210 | ||
211 | /* stop device's busmaster DMA activity */ | |
212 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
213 | ||
214 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
215 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
216 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
cc56feb2 EG |
217 | if (ret) |
218 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
219 | ||
220 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
221 | ||
222 | return ret; | |
223 | } | |
224 | ||
7afe3705 | 225 | static void iwl_pcie_apm_stop(struct iwl_trans *trans) |
cc56feb2 | 226 | { |
83626404 | 227 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cc56feb2 EG |
228 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); |
229 | ||
83626404 | 230 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
cc56feb2 EG |
231 | |
232 | /* Stop device's DMA activity */ | |
7afe3705 | 233 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 EG |
234 | |
235 | /* Reset the entire device */ | |
236 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
237 | ||
238 | udelay(10); | |
239 | ||
240 | /* | |
241 | * Clear "initialization complete" bit to move adapter from | |
242 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
243 | */ | |
244 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
245 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
246 | } | |
247 | ||
7afe3705 | 248 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 249 | { |
7b11488f | 250 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
251 | unsigned long flags; |
252 | ||
253 | /* nic_init */ | |
7b11488f | 254 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
7afe3705 | 255 | iwl_pcie_apm_init(trans); |
392f8b78 EG |
256 | |
257 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
20d3b647 | 258 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
392f8b78 | 259 | |
7b11488f | 260 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 261 | |
7afe3705 | 262 | iwl_pcie_set_pwr_vmain(trans); |
392f8b78 | 263 | |
ecdb975c | 264 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
265 | |
266 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 267 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
268 | |
269 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 270 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
271 | return -ENOMEM; |
272 | ||
035f7ff2 | 273 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 274 | /* enable shadow regs in HW */ |
20d3b647 | 275 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 276 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
277 | } |
278 | ||
392f8b78 EG |
279 | return 0; |
280 | } | |
281 | ||
282 | #define HW_READY_TIMEOUT (50) | |
283 | ||
284 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 285 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
286 | { |
287 | int ret; | |
288 | ||
1042db2a | 289 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 290 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
291 | |
292 | /* See if we got it */ | |
1042db2a | 293 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
294 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
295 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
296 | HW_READY_TIMEOUT); | |
392f8b78 | 297 | |
6d8f6eeb | 298 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
299 | return ret; |
300 | } | |
301 | ||
302 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 303 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
304 | { |
305 | int ret; | |
289e5501 | 306 | int t = 0; |
392f8b78 | 307 | |
6d8f6eeb | 308 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 309 | |
7afe3705 | 310 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 311 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
312 | if (ret >= 0) |
313 | return 0; | |
314 | ||
315 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 316 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 317 | CSR_HW_IF_CONFIG_REG_PREPARE); |
392f8b78 | 318 | |
289e5501 | 319 | do { |
7afe3705 | 320 | ret = iwl_pcie_set_hw_ready(trans); |
289e5501 EG |
321 | if (ret >= 0) |
322 | return 0; | |
392f8b78 | 323 | |
289e5501 EG |
324 | usleep_range(200, 1000); |
325 | t += 200; | |
326 | } while (t < 150000); | |
392f8b78 | 327 | |
392f8b78 EG |
328 | return ret; |
329 | } | |
330 | ||
cf614297 EG |
331 | /* |
332 | * ucode | |
333 | */ | |
7afe3705 | 334 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 335 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 336 | { |
13df1aab | 337 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
338 | int ret; |
339 | ||
13df1aab | 340 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
341 | |
342 | iwl_write_direct32(trans, | |
20d3b647 JB |
343 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
344 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
345 | |
346 | iwl_write_direct32(trans, | |
20d3b647 JB |
347 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
348 | dst_addr); | |
cf614297 EG |
349 | |
350 | iwl_write_direct32(trans, | |
83f84d7b JB |
351 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
352 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
353 | |
354 | iwl_write_direct32(trans, | |
20d3b647 JB |
355 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
356 | (iwl_get_dma_hi_addr(phy_addr) | |
357 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
358 | |
359 | iwl_write_direct32(trans, | |
20d3b647 JB |
360 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
361 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
362 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
363 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
364 | |
365 | iwl_write_direct32(trans, | |
20d3b647 JB |
366 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
367 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
368 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
369 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 370 | |
13df1aab JB |
371 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
372 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 373 | if (!ret) { |
83f84d7b | 374 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
375 | return -ETIMEDOUT; |
376 | } | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
7afe3705 | 381 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 382 | const struct fw_desc *section) |
cf614297 | 383 | { |
83f84d7b JB |
384 | u8 *v_addr; |
385 | dma_addr_t p_addr; | |
386 | u32 offset; | |
cf614297 EG |
387 | int ret = 0; |
388 | ||
83f84d7b JB |
389 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
390 | section_num); | |
391 | ||
392 | v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL); | |
393 | if (!v_addr) | |
394 | return -ENOMEM; | |
395 | ||
396 | for (offset = 0; offset < section->len; offset += PAGE_SIZE) { | |
397 | u32 copy_size; | |
398 | ||
399 | copy_size = min_t(u32, PAGE_SIZE, section->len - offset); | |
cf614297 | 400 | |
83f84d7b | 401 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
7afe3705 EG |
402 | ret = iwl_pcie_load_firmware_chunk(trans, |
403 | section->offset + offset, | |
404 | p_addr, copy_size); | |
83f84d7b JB |
405 | if (ret) { |
406 | IWL_ERR(trans, | |
407 | "Could not load the [%d] uCode section\n", | |
408 | section_num); | |
409 | break; | |
6dfa8d01 | 410 | } |
83f84d7b JB |
411 | } |
412 | ||
413 | dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr); | |
414 | return ret; | |
415 | } | |
416 | ||
7afe3705 | 417 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 418 | const struct fw_img *image) |
cf614297 | 419 | { |
2d1c0044 | 420 | int i, ret = 0; |
cf614297 | 421 | |
2d1c0044 | 422 | for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) { |
83f84d7b | 423 | if (!image->sec[i].data) |
2d1c0044 | 424 | break; |
cf614297 | 425 | |
7afe3705 | 426 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
2d1c0044 JB |
427 | if (ret) |
428 | return ret; | |
429 | } | |
cf614297 EG |
430 | |
431 | /* Remove all resets to allow NIC to operate */ | |
432 | iwl_write32(trans, CSR_RESET, 0); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
0692fe41 | 437 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
6ae02f3e | 438 | const struct fw_img *fw, bool run_in_rfkill) |
392f8b78 | 439 | { |
d18aa87f | 440 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 | 441 | int ret; |
c9eec95c | 442 | bool hw_rfkill; |
392f8b78 | 443 | |
496bab39 | 444 | /* This may fail if AMT took ownership of the device */ |
7afe3705 | 445 | if (iwl_pcie_prepare_card_hw(trans)) { |
6d8f6eeb | 446 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
447 | return -EIO; |
448 | } | |
449 | ||
d18aa87f JB |
450 | clear_bit(STATUS_FW_ERROR, &trans_pcie->status); |
451 | ||
8c46bb70 EG |
452 | iwl_enable_rfkill_int(trans); |
453 | ||
392f8b78 | 454 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 455 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 456 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
6ae02f3e | 457 | if (hw_rfkill && !run_in_rfkill) |
392f8b78 | 458 | return -ERFKILL; |
392f8b78 | 459 | |
1042db2a | 460 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 461 | |
7afe3705 | 462 | ret = iwl_pcie_nic_init(trans); |
392f8b78 | 463 | if (ret) { |
6d8f6eeb | 464 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
465 | return ret; |
466 | } | |
467 | ||
468 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
469 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
470 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
471 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
472 | ||
473 | /* clear (again), then enable host interrupts */ | |
1042db2a | 474 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 475 | iwl_enable_interrupts(trans); |
392f8b78 EG |
476 | |
477 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
478 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
479 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 480 | |
cf614297 | 481 | /* Load the given image to the HW */ |
7afe3705 | 482 | return iwl_pcie_load_given_ucode(trans, fw); |
b3c2ce13 EG |
483 | } |
484 | ||
adca1235 | 485 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 486 | { |
990aa6d7 | 487 | iwl_pcie_reset_ict(trans); |
f02831be | 488 | iwl_pcie_tx_start(trans, scd_addr); |
c170b867 EG |
489 | } |
490 | ||
43e58856 | 491 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 492 | { |
43e58856 | 493 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
20d3b647 | 494 | unsigned long flags; |
ae2c30bf | 495 | |
43e58856 | 496 | /* tell the device to stop sending interrupts */ |
7b11488f | 497 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 498 | iwl_disable_interrupts(trans); |
7b11488f | 499 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 500 | |
ab6cf8e8 | 501 | /* device going down, Stop using ICT table */ |
990aa6d7 | 502 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
503 | |
504 | /* | |
505 | * If a HW restart happens during firmware loading, | |
506 | * then the firmware loading might call this function | |
507 | * and later it might be called again due to the | |
508 | * restart. So don't process again if the device is | |
509 | * already dead. | |
510 | */ | |
83626404 | 511 | if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) { |
f02831be | 512 | iwl_pcie_tx_stop(trans); |
9805c446 | 513 | iwl_pcie_rx_stop(trans); |
6379103e | 514 | |
ab6cf8e8 | 515 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 516 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
517 | APMG_CLK_VAL_DMA_CLK_RQT); |
518 | udelay(5); | |
519 | } | |
520 | ||
521 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 522 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 523 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
524 | |
525 | /* Stop the device, and put it in low power state */ | |
7afe3705 | 526 | iwl_pcie_apm_stop(trans); |
43e58856 EG |
527 | |
528 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
529 | * Clean again the interrupt here | |
530 | */ | |
7b11488f | 531 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 532 | iwl_disable_interrupts(trans); |
7b11488f | 533 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 | 534 | |
218733cf EG |
535 | iwl_enable_rfkill_int(trans); |
536 | ||
43e58856 | 537 | /* wait to make sure we flush pending tasklet*/ |
75595536 | 538 | synchronize_irq(trans_pcie->irq); |
43e58856 EG |
539 | tasklet_kill(&trans_pcie->irq_tasklet); |
540 | ||
1ee158d8 JB |
541 | cancel_work_sync(&trans_pcie->rx_replenish); |
542 | ||
43e58856 | 543 | /* stop and reset the on-board processor */ |
1042db2a | 544 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
74fda971 DF |
545 | |
546 | /* clear all status bits */ | |
547 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); | |
548 | clear_bit(STATUS_INT_ENABLED, &trans_pcie->status); | |
549 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); | |
01d651d4 | 550 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
f946b529 | 551 | clear_bit(STATUS_RFKILL, &trans_pcie->status); |
ab6cf8e8 EG |
552 | } |
553 | ||
2dd4f9f7 JB |
554 | static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans) |
555 | { | |
556 | /* let the ucode operate on its own */ | |
557 | iwl_write32(trans, CSR_UCODE_DRV_GP1_SET, | |
558 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
559 | ||
560 | iwl_disable_interrupts(trans); | |
561 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
562 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
563 | } | |
564 | ||
57a1dc89 | 565 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 566 | { |
20d3b647 | 567 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e6bb4c9c | 568 | int err; |
c9eec95c | 569 | bool hw_rfkill; |
e6bb4c9c | 570 | |
0c325769 EG |
571 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
572 | ||
57a1dc89 EG |
573 | if (!trans_pcie->irq_requested) { |
574 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
990aa6d7 | 575 | iwl_pcie_tasklet, (unsigned long)trans); |
e6bb4c9c | 576 | |
990aa6d7 | 577 | iwl_pcie_alloc_ict(trans); |
e6bb4c9c | 578 | |
990aa6d7 EG |
579 | err = request_irq(trans_pcie->irq, iwl_pcie_isr_ict, |
580 | IRQF_SHARED, DRV_NAME, trans); | |
57a1dc89 EG |
581 | if (err) { |
582 | IWL_ERR(trans, "Error allocating IRQ %d\n", | |
75595536 | 583 | trans_pcie->irq); |
ebb7678d | 584 | goto error; |
57a1dc89 EG |
585 | } |
586 | ||
57a1dc89 | 587 | trans_pcie->irq_requested = true; |
e6bb4c9c EG |
588 | } |
589 | ||
7afe3705 | 590 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 591 | if (err) { |
d6f1c316 | 592 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
f057ac4e | 593 | goto err_free_irq; |
ebb7678d | 594 | } |
a6c684ee | 595 | |
7afe3705 | 596 | iwl_pcie_apm_init(trans); |
a6c684ee | 597 | |
226c02ca EG |
598 | /* From now on, the op_mode will be kept updated about RF kill state */ |
599 | iwl_enable_rfkill_int(trans); | |
600 | ||
8d425517 | 601 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 602 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
d48e2074 | 603 | |
ebb7678d EG |
604 | return err; |
605 | ||
f057ac4e | 606 | err_free_irq: |
a7be50b7 | 607 | trans_pcie->irq_requested = false; |
75595536 | 608 | free_irq(trans_pcie->irq, trans); |
ebb7678d | 609 | error: |
990aa6d7 | 610 | iwl_pcie_free_ict(trans); |
ebb7678d EG |
611 | tasklet_kill(&trans_pcie->irq_tasklet); |
612 | return err; | |
e6bb4c9c EG |
613 | } |
614 | ||
218733cf EG |
615 | static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans, |
616 | bool op_mode_leaving) | |
cc56feb2 | 617 | { |
20d3b647 | 618 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 619 | bool hw_rfkill; |
218733cf | 620 | unsigned long flags; |
d23f78e6 | 621 | |
ee7d737c DS |
622 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
623 | iwl_disable_interrupts(trans); | |
624 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
625 | ||
7afe3705 | 626 | iwl_pcie_apm_stop(trans); |
cc56feb2 | 627 | |
218733cf EG |
628 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
629 | iwl_disable_interrupts(trans); | |
630 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1df06bdc | 631 | |
8d96bb61 EG |
632 | iwl_pcie_disable_ict(trans); |
633 | ||
218733cf EG |
634 | if (!op_mode_leaving) { |
635 | /* | |
636 | * Even if we stop the HW, we still want the RF kill | |
637 | * interrupt | |
638 | */ | |
639 | iwl_enable_rfkill_int(trans); | |
640 | ||
641 | /* | |
642 | * Check again since the RF kill state may have changed while | |
643 | * all the interrupts were disabled, in this case we couldn't | |
644 | * receive the RF kill interrupt and update the state in the | |
645 | * op_mode. | |
646 | */ | |
647 | hw_rfkill = iwl_is_rfkill_set(trans); | |
648 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
649 | } | |
cc56feb2 EG |
650 | } |
651 | ||
03905495 EG |
652 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
653 | { | |
05f5b97e | 654 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
655 | } |
656 | ||
657 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
658 | { | |
05f5b97e | 659 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
660 | } |
661 | ||
662 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
663 | { | |
05f5b97e | 664 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
665 | } |
666 | ||
6a06b6c1 EG |
667 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
668 | { | |
669 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); | |
670 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); | |
671 | } | |
672 | ||
673 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
674 | u32 val) | |
675 | { | |
676 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
677 | ((addr & 0x0000FFFF) | (3 << 24))); | |
678 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); | |
679 | } | |
680 | ||
c6f600fc | 681 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 682 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
683 | { |
684 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
685 | ||
686 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 687 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
d663ee73 JB |
688 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
689 | trans_pcie->n_no_reclaim_cmds = 0; | |
690 | else | |
691 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
692 | if (trans_pcie->n_no_reclaim_cmds) | |
693 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
694 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 695 | |
b2cf410c JB |
696 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
697 | if (trans_pcie->rx_buf_size_8k) | |
698 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
699 | else | |
700 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
701 | |
702 | trans_pcie->wd_timeout = | |
703 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
704 | |
705 | trans_pcie->command_names = trans_cfg->command_names; | |
046db346 | 706 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
c6f600fc MV |
707 | } |
708 | ||
d1ff5253 | 709 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 710 | { |
20d3b647 | 711 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 712 | |
f02831be | 713 | iwl_pcie_tx_free(trans); |
9805c446 | 714 | iwl_pcie_rx_free(trans); |
6379103e | 715 | |
57a1dc89 | 716 | if (trans_pcie->irq_requested == true) { |
75595536 | 717 | free_irq(trans_pcie->irq, trans); |
990aa6d7 | 718 | iwl_pcie_free_ict(trans); |
57a1dc89 | 719 | } |
a42a1844 EG |
720 | |
721 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 722 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
723 | pci_release_regions(trans_pcie->pci_dev); |
724 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 725 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 726 | |
6d8f6eeb | 727 | kfree(trans); |
34c1b7ba EG |
728 | } |
729 | ||
47107e84 DF |
730 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
731 | { | |
732 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
733 | ||
734 | if (state) | |
01d651d4 | 735 | set_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 | 736 | else |
01d651d4 | 737 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 DF |
738 | } |
739 | ||
c01a4047 | 740 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
741 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
742 | { | |
57210f7c EG |
743 | return 0; |
744 | } | |
745 | ||
746 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
747 | { | |
c9eec95c | 748 | bool hw_rfkill; |
57210f7c | 749 | |
8c46bb70 EG |
750 | iwl_enable_rfkill_int(trans); |
751 | ||
8d425517 | 752 | hw_rfkill = iwl_is_rfkill_set(trans); |
8c46bb70 | 753 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8722c899 | 754 | |
8c46bb70 | 755 | if (!hw_rfkill) |
8722c899 SG |
756 | iwl_enable_interrupts(trans); |
757 | ||
57210f7c EG |
758 | return 0; |
759 | } | |
c01a4047 | 760 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 761 | |
7a65d170 EG |
762 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent) |
763 | { | |
764 | int ret; | |
765 | ||
766 | lockdep_assert_held(&trans->reg_lock); | |
767 | ||
768 | /* this bit wakes up the NIC */ | |
769 | __iwl_set_bit(trans, CSR_GP_CNTRL, | |
770 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
771 | ||
772 | /* | |
773 | * These bits say the device is running, and should keep running for | |
774 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
775 | * but they do not indicate that embedded SRAM is restored yet; | |
776 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
777 | * to/from host DRAM when sleeping/waking for power-saving. | |
778 | * Each direction takes approximately 1/4 millisecond; with this | |
779 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
780 | * series of register accesses are expected (e.g. reading Event Log), | |
781 | * to keep device from sleeping. | |
782 | * | |
783 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
784 | * SRAM is okay/restored. We don't check that here because this call | |
785 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
786 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
787 | * | |
788 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
789 | * and do not save/restore SRAM when power cycling. | |
790 | */ | |
791 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
792 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
793 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
794 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
795 | if (unlikely(ret < 0)) { | |
796 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
797 | if (!silent) { | |
798 | u32 val = iwl_read32(trans, CSR_GP_CNTRL); | |
799 | WARN_ONCE(1, | |
800 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
801 | val); | |
802 | return false; | |
803 | } | |
804 | } | |
805 | ||
806 | return true; | |
807 | } | |
808 | ||
809 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) | |
810 | { | |
811 | lockdep_assert_held(&trans->reg_lock); | |
812 | __iwl_clear_bit(trans, CSR_GP_CNTRL, | |
813 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
814 | /* | |
815 | * Above we read the CSR_GP_CNTRL register, which will flush | |
816 | * any previous writes, but we need the write that clears the | |
817 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
818 | * scheduled on different CPUs (after we drop reg_lock). | |
819 | */ | |
820 | mmiowb(); | |
821 | } | |
822 | ||
4fd442db EG |
823 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
824 | void *buf, int dwords) | |
825 | { | |
826 | unsigned long flags; | |
827 | int offs, ret = 0; | |
828 | u32 *vals = buf; | |
829 | ||
830 | spin_lock_irqsave(&trans->reg_lock, flags); | |
831 | if (likely(iwl_trans_grab_nic_access(trans, false))) { | |
832 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); | |
833 | for (offs = 0; offs < dwords; offs++) | |
834 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
835 | iwl_trans_release_nic_access(trans); | |
836 | } else { | |
837 | ret = -EBUSY; | |
838 | } | |
839 | spin_unlock_irqrestore(&trans->reg_lock, flags); | |
840 | return ret; | |
841 | } | |
842 | ||
843 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
844 | void *buf, int dwords) | |
845 | { | |
846 | unsigned long flags; | |
847 | int offs, ret = 0; | |
848 | u32 *vals = buf; | |
849 | ||
850 | spin_lock_irqsave(&trans->reg_lock, flags); | |
851 | if (likely(iwl_trans_grab_nic_access(trans, false))) { | |
852 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); | |
853 | for (offs = 0; offs < dwords; offs++) | |
854 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]); | |
855 | iwl_trans_release_nic_access(trans); | |
856 | } else { | |
857 | ret = -EBUSY; | |
858 | } | |
859 | spin_unlock_irqrestore(&trans->reg_lock, flags); | |
860 | return ret; | |
861 | } | |
7a65d170 | 862 | |
5f178cd2 EG |
863 | #define IWL_FLUSH_WAIT_MS 2000 |
864 | ||
990aa6d7 | 865 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans) |
5f178cd2 | 866 | { |
8ad71bef | 867 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 868 | struct iwl_txq *txq; |
5f178cd2 EG |
869 | struct iwl_queue *q; |
870 | int cnt; | |
871 | unsigned long now = jiffies; | |
872 | int ret = 0; | |
873 | ||
874 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 875 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
9ba1947a | 876 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 877 | continue; |
8ad71bef | 878 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
879 | q = &txq->q; |
880 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
881 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
882 | msleep(1); | |
883 | ||
884 | if (q->read_ptr != q->write_ptr) { | |
885 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); | |
886 | ret = -ETIMEDOUT; | |
887 | break; | |
888 | } | |
889 | } | |
890 | return ret; | |
891 | } | |
892 | ||
ff620849 EG |
893 | static const char *get_fh_string(int cmd) |
894 | { | |
d9fb6465 | 895 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
896 | switch (cmd) { |
897 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
898 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
899 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
900 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
901 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
902 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
903 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
904 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
905 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
906 | default: | |
907 | return "UNKNOWN"; | |
908 | } | |
d9fb6465 | 909 | #undef IWL_CMD |
ff620849 EG |
910 | } |
911 | ||
990aa6d7 | 912 | int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf) |
ff620849 EG |
913 | { |
914 | int i; | |
ff620849 EG |
915 | static const u32 fh_tbl[] = { |
916 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
917 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
918 | FH_RSCSR_CHNL0_WPTR, | |
919 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
920 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
921 | FH_MEM_RSSR_RX_STATUS_REG, | |
922 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
923 | FH_TSSR_TX_STATUS_REG, | |
924 | FH_TSSR_TX_ERROR_REG | |
925 | }; | |
94543a8d JB |
926 | |
927 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
928 | if (buf) { | |
929 | int pos = 0; | |
930 | size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
931 | ||
ff620849 EG |
932 | *buf = kmalloc(bufsz, GFP_KERNEL); |
933 | if (!*buf) | |
934 | return -ENOMEM; | |
94543a8d | 935 | |
ff620849 EG |
936 | pos += scnprintf(*buf + pos, bufsz - pos, |
937 | "FH register values:\n"); | |
94543a8d JB |
938 | |
939 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) | |
ff620849 EG |
940 | pos += scnprintf(*buf + pos, bufsz - pos, |
941 | " %34s: 0X%08x\n", | |
942 | get_fh_string(fh_tbl[i]), | |
1042db2a | 943 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 944 | |
ff620849 EG |
945 | return pos; |
946 | } | |
947 | #endif | |
94543a8d | 948 | |
ff620849 | 949 | IWL_ERR(trans, "FH register values:\n"); |
94543a8d | 950 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) |
ff620849 EG |
951 | IWL_ERR(trans, " %34s: 0X%08x\n", |
952 | get_fh_string(fh_tbl[i]), | |
1042db2a | 953 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 954 | |
ff620849 EG |
955 | return 0; |
956 | } | |
957 | ||
958 | static const char *get_csr_string(int cmd) | |
959 | { | |
d9fb6465 | 960 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
961 | switch (cmd) { |
962 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
963 | IWL_CMD(CSR_INT_COALESCING); | |
964 | IWL_CMD(CSR_INT); | |
965 | IWL_CMD(CSR_INT_MASK); | |
966 | IWL_CMD(CSR_FH_INT_STATUS); | |
967 | IWL_CMD(CSR_GPIO_IN); | |
968 | IWL_CMD(CSR_RESET); | |
969 | IWL_CMD(CSR_GP_CNTRL); | |
970 | IWL_CMD(CSR_HW_REV); | |
971 | IWL_CMD(CSR_EEPROM_REG); | |
972 | IWL_CMD(CSR_EEPROM_GP); | |
973 | IWL_CMD(CSR_OTP_GP_REG); | |
974 | IWL_CMD(CSR_GIO_REG); | |
975 | IWL_CMD(CSR_GP_UCODE_REG); | |
976 | IWL_CMD(CSR_GP_DRIVER_REG); | |
977 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
978 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
979 | IWL_CMD(CSR_LED_REG); | |
980 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
981 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
982 | IWL_CMD(CSR_ANA_PLL_CFG); | |
983 | IWL_CMD(CSR_HW_REV_WA_REG); | |
984 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
985 | default: | |
986 | return "UNKNOWN"; | |
987 | } | |
d9fb6465 | 988 | #undef IWL_CMD |
ff620849 EG |
989 | } |
990 | ||
990aa6d7 | 991 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
992 | { |
993 | int i; | |
994 | static const u32 csr_tbl[] = { | |
995 | CSR_HW_IF_CONFIG_REG, | |
996 | CSR_INT_COALESCING, | |
997 | CSR_INT, | |
998 | CSR_INT_MASK, | |
999 | CSR_FH_INT_STATUS, | |
1000 | CSR_GPIO_IN, | |
1001 | CSR_RESET, | |
1002 | CSR_GP_CNTRL, | |
1003 | CSR_HW_REV, | |
1004 | CSR_EEPROM_REG, | |
1005 | CSR_EEPROM_GP, | |
1006 | CSR_OTP_GP_REG, | |
1007 | CSR_GIO_REG, | |
1008 | CSR_GP_UCODE_REG, | |
1009 | CSR_GP_DRIVER_REG, | |
1010 | CSR_UCODE_DRV_GP1, | |
1011 | CSR_UCODE_DRV_GP2, | |
1012 | CSR_LED_REG, | |
1013 | CSR_DRAM_INT_TBL_REG, | |
1014 | CSR_GIO_CHICKEN_BITS, | |
1015 | CSR_ANA_PLL_CFG, | |
1016 | CSR_HW_REV_WA_REG, | |
1017 | CSR_DBG_HPET_MEM_REG | |
1018 | }; | |
1019 | IWL_ERR(trans, "CSR values:\n"); | |
1020 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1021 | "CSR_INT_PERIODIC_REG)\n"); | |
1022 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1023 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1024 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1025 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1026 | } |
1027 | } | |
1028 | ||
87e5666c EG |
1029 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1030 | /* create and remove of files */ | |
1031 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1032 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 1033 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 1034 | goto err; \ |
87e5666c EG |
1035 | } while (0) |
1036 | ||
1037 | /* file operation */ | |
1038 | #define DEBUGFS_READ_FUNC(name) \ | |
1039 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1040 | char __user *user_buf, \ | |
1041 | size_t count, loff_t *ppos); | |
1042 | ||
1043 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1044 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1045 | const char __user *user_buf, \ | |
1046 | size_t count, loff_t *ppos); | |
1047 | ||
87e5666c EG |
1048 | #define DEBUGFS_READ_FILE_OPS(name) \ |
1049 | DEBUGFS_READ_FUNC(name); \ | |
1050 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1051 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1052 | .open = simple_open, \ |
87e5666c EG |
1053 | .llseek = generic_file_llseek, \ |
1054 | }; | |
1055 | ||
16db88ba EG |
1056 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1057 | DEBUGFS_WRITE_FUNC(name); \ | |
1058 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1059 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1060 | .open = simple_open, \ |
16db88ba EG |
1061 | .llseek = generic_file_llseek, \ |
1062 | }; | |
1063 | ||
87e5666c EG |
1064 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1065 | DEBUGFS_READ_FUNC(name); \ | |
1066 | DEBUGFS_WRITE_FUNC(name); \ | |
1067 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1068 | .write = iwl_dbgfs_##name##_write, \ | |
1069 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1070 | .open = simple_open, \ |
87e5666c EG |
1071 | .llseek = generic_file_llseek, \ |
1072 | }; | |
1073 | ||
87e5666c | 1074 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1075 | char __user *user_buf, |
1076 | size_t count, loff_t *ppos) | |
8ad71bef | 1077 | { |
5a878bf6 | 1078 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1079 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1080 | struct iwl_txq *txq; |
87e5666c EG |
1081 | struct iwl_queue *q; |
1082 | char *buf; | |
1083 | int pos = 0; | |
1084 | int cnt; | |
1085 | int ret; | |
1745e440 WYG |
1086 | size_t bufsz; |
1087 | ||
035f7ff2 | 1088 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1089 | |
f9e75447 | 1090 | if (!trans_pcie->txq) |
87e5666c | 1091 | return -EAGAIN; |
f9e75447 | 1092 | |
87e5666c EG |
1093 | buf = kzalloc(bufsz, GFP_KERNEL); |
1094 | if (!buf) | |
1095 | return -ENOMEM; | |
1096 | ||
035f7ff2 | 1097 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1098 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1099 | q = &txq->q; |
1100 | pos += scnprintf(buf + pos, bufsz - pos, | |
9eae88fa | 1101 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", |
87e5666c | 1102 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa JB |
1103 | !!test_bit(cnt, trans_pcie->queue_used), |
1104 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
87e5666c EG |
1105 | } |
1106 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1107 | kfree(buf); | |
1108 | return ret; | |
1109 | } | |
1110 | ||
1111 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1112 | char __user *user_buf, |
1113 | size_t count, loff_t *ppos) | |
1114 | { | |
5a878bf6 | 1115 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1116 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1117 | struct iwl_rxq *rxq = &trans_pcie->rxq; |
87e5666c EG |
1118 | char buf[256]; |
1119 | int pos = 0; | |
1120 | const size_t bufsz = sizeof(buf); | |
1121 | ||
1122 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1123 | rxq->read); | |
1124 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1125 | rxq->write); | |
1126 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1127 | rxq->free_count); | |
1128 | if (rxq->rb_stts) { | |
1129 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1130 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1131 | } else { | |
1132 | pos += scnprintf(buf + pos, bufsz - pos, | |
1133 | "closed_rb_num: Not Allocated\n"); | |
1134 | } | |
1135 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1136 | } | |
1137 | ||
1f7b6172 EG |
1138 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1139 | char __user *user_buf, | |
20d3b647 JB |
1140 | size_t count, loff_t *ppos) |
1141 | { | |
1f7b6172 | 1142 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1143 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1144 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1145 | ||
1146 | int pos = 0; | |
1147 | char *buf; | |
1148 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1149 | ssize_t ret; | |
1150 | ||
1151 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1152 | if (!buf) |
1f7b6172 | 1153 | return -ENOMEM; |
1f7b6172 EG |
1154 | |
1155 | pos += scnprintf(buf + pos, bufsz - pos, | |
1156 | "Interrupt Statistics Report:\n"); | |
1157 | ||
1158 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1159 | isr_stats->hw); | |
1160 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1161 | isr_stats->sw); | |
1162 | if (isr_stats->sw || isr_stats->hw) { | |
1163 | pos += scnprintf(buf + pos, bufsz - pos, | |
1164 | "\tLast Restarting Code: 0x%X\n", | |
1165 | isr_stats->err_code); | |
1166 | } | |
1167 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1168 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1169 | isr_stats->sch); | |
1170 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1171 | isr_stats->alive); | |
1172 | #endif | |
1173 | pos += scnprintf(buf + pos, bufsz - pos, | |
1174 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1175 | ||
1176 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1177 | isr_stats->ctkill); | |
1178 | ||
1179 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1180 | isr_stats->wakeup); | |
1181 | ||
1182 | pos += scnprintf(buf + pos, bufsz - pos, | |
1183 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1184 | ||
1185 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1186 | isr_stats->tx); | |
1187 | ||
1188 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1189 | isr_stats->unhandled); | |
1190 | ||
1191 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1192 | kfree(buf); | |
1193 | return ret; | |
1194 | } | |
1195 | ||
1196 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1197 | const char __user *user_buf, | |
1198 | size_t count, loff_t *ppos) | |
1199 | { | |
1200 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1201 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1202 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1203 | ||
1204 | char buf[8]; | |
1205 | int buf_size; | |
1206 | u32 reset_flag; | |
1207 | ||
1208 | memset(buf, 0, sizeof(buf)); | |
1209 | buf_size = min(count, sizeof(buf) - 1); | |
1210 | if (copy_from_user(buf, user_buf, buf_size)) | |
1211 | return -EFAULT; | |
1212 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1213 | return -EFAULT; | |
1214 | if (reset_flag == 0) | |
1215 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1216 | ||
1217 | return count; | |
1218 | } | |
1219 | ||
16db88ba | 1220 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1221 | const char __user *user_buf, |
1222 | size_t count, loff_t *ppos) | |
16db88ba EG |
1223 | { |
1224 | struct iwl_trans *trans = file->private_data; | |
1225 | char buf[8]; | |
1226 | int buf_size; | |
1227 | int csr; | |
1228 | ||
1229 | memset(buf, 0, sizeof(buf)); | |
1230 | buf_size = min(count, sizeof(buf) - 1); | |
1231 | if (copy_from_user(buf, user_buf, buf_size)) | |
1232 | return -EFAULT; | |
1233 | if (sscanf(buf, "%d", &csr) != 1) | |
1234 | return -EFAULT; | |
1235 | ||
990aa6d7 | 1236 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
1237 | |
1238 | return count; | |
1239 | } | |
1240 | ||
16db88ba | 1241 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1242 | char __user *user_buf, |
1243 | size_t count, loff_t *ppos) | |
16db88ba EG |
1244 | { |
1245 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 1246 | char *buf = NULL; |
16db88ba EG |
1247 | int pos = 0; |
1248 | ssize_t ret = -EFAULT; | |
1249 | ||
990aa6d7 | 1250 | ret = pos = iwl_pcie_dump_fh(trans, &buf); |
16db88ba EG |
1251 | if (buf) { |
1252 | ret = simple_read_from_buffer(user_buf, | |
1253 | count, ppos, buf, pos); | |
1254 | kfree(buf); | |
1255 | } | |
1256 | ||
1257 | return ret; | |
1258 | } | |
1259 | ||
48dffd39 JB |
1260 | static ssize_t iwl_dbgfs_fw_restart_write(struct file *file, |
1261 | const char __user *user_buf, | |
1262 | size_t count, loff_t *ppos) | |
1263 | { | |
1264 | struct iwl_trans *trans = file->private_data; | |
1265 | ||
1266 | if (!trans->op_mode) | |
1267 | return -EAGAIN; | |
1268 | ||
24172f39 | 1269 | local_bh_disable(); |
48dffd39 | 1270 | iwl_op_mode_nic_error(trans->op_mode); |
24172f39 | 1271 | local_bh_enable(); |
48dffd39 JB |
1272 | |
1273 | return count; | |
1274 | } | |
1275 | ||
1f7b6172 | 1276 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1277 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1278 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1279 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1280 | DEBUGFS_WRITE_FILE_OPS(csr); |
48dffd39 | 1281 | DEBUGFS_WRITE_FILE_OPS(fw_restart); |
87e5666c EG |
1282 | |
1283 | /* | |
1284 | * Create the debugfs files and directories | |
1285 | * | |
1286 | */ | |
1287 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 1288 | struct dentry *dir) |
87e5666c | 1289 | { |
87e5666c EG |
1290 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1291 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 1292 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1293 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1294 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
48dffd39 | 1295 | DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR); |
87e5666c | 1296 | return 0; |
9da987ac MV |
1297 | |
1298 | err: | |
1299 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1300 | return -ENOMEM; | |
87e5666c EG |
1301 | } |
1302 | #else | |
1303 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 JB |
1304 | struct dentry *dir) |
1305 | { | |
1306 | return 0; | |
1307 | } | |
87e5666c EG |
1308 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
1309 | ||
d1ff5253 | 1310 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 1311 | .start_hw = iwl_trans_pcie_start_hw, |
cc56feb2 | 1312 | .stop_hw = iwl_trans_pcie_stop_hw, |
ed6a3803 | 1313 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 1314 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 1315 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 1316 | |
2dd4f9f7 JB |
1317 | .wowlan_suspend = iwl_trans_pcie_wowlan_suspend, |
1318 | ||
f02831be | 1319 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 1320 | |
e6bb4c9c | 1321 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 1322 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1323 | |
d0624be6 | 1324 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 1325 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 1326 | |
87e5666c | 1327 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 | 1328 | |
990aa6d7 | 1329 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
5f178cd2 | 1330 | |
c01a4047 | 1331 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1332 | .suspend = iwl_trans_pcie_suspend, |
1333 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 1334 | #endif |
03905495 EG |
1335 | .write8 = iwl_trans_pcie_write8, |
1336 | .write32 = iwl_trans_pcie_write32, | |
1337 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
1338 | .read_prph = iwl_trans_pcie_read_prph, |
1339 | .write_prph = iwl_trans_pcie_write_prph, | |
4fd442db EG |
1340 | .read_mem = iwl_trans_pcie_read_mem, |
1341 | .write_mem = iwl_trans_pcie_write_mem, | |
c6f600fc | 1342 | .configure = iwl_trans_pcie_configure, |
47107e84 | 1343 | .set_pmi = iwl_trans_pcie_set_pmi, |
7a65d170 EG |
1344 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
1345 | .release_nic_access = iwl_trans_pcie_release_nic_access | |
e6bb4c9c | 1346 | }; |
a42a1844 | 1347 | |
87ce05a2 | 1348 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
1349 | const struct pci_device_id *ent, |
1350 | const struct iwl_cfg *cfg) | |
a42a1844 | 1351 | { |
a42a1844 EG |
1352 | struct iwl_trans_pcie *trans_pcie; |
1353 | struct iwl_trans *trans; | |
1354 | u16 pci_cmd; | |
1355 | int err; | |
1356 | ||
1357 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 1358 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
a42a1844 | 1359 | |
dbeca583 | 1360 | if (!trans) |
a42a1844 EG |
1361 | return NULL; |
1362 | ||
1363 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1364 | ||
1365 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 1366 | trans->cfg = cfg; |
a42a1844 | 1367 | trans_pcie->trans = trans; |
7b11488f | 1368 | spin_lock_init(&trans_pcie->irq_lock); |
13df1aab | 1369 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 EG |
1370 | |
1371 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
1372 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
1373 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
20d3b647 | 1374 | PCIE_LINK_STATE_CLKPM); |
a42a1844 EG |
1375 | |
1376 | if (pci_enable_device(pdev)) { | |
1377 | err = -ENODEV; | |
1378 | goto out_no_pci; | |
1379 | } | |
1380 | ||
1381 | pci_set_master(pdev); | |
1382 | ||
1383 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1384 | if (!err) | |
1385 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1386 | if (err) { | |
1387 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1388 | if (!err) | |
1389 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 1390 | DMA_BIT_MASK(32)); |
a42a1844 EG |
1391 | /* both attempts failed: */ |
1392 | if (err) { | |
6a4b09f8 | 1393 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
a42a1844 EG |
1394 | goto out_pci_disable_device; |
1395 | } | |
1396 | } | |
1397 | ||
1398 | err = pci_request_regions(pdev, DRV_NAME); | |
1399 | if (err) { | |
6a4b09f8 | 1400 | dev_err(&pdev->dev, "pci_request_regions failed\n"); |
a42a1844 EG |
1401 | goto out_pci_disable_device; |
1402 | } | |
1403 | ||
05f5b97e | 1404 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 1405 | if (!trans_pcie->hw_base) { |
6a4b09f8 | 1406 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
1407 | err = -ENODEV; |
1408 | goto out_pci_release_regions; | |
1409 | } | |
1410 | ||
a42a1844 EG |
1411 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
1412 | * PCI Tx retries from interfering with C3 CPU state */ | |
1413 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
1414 | ||
1415 | err = pci_enable_msi(pdev); | |
9f904b38 | 1416 | if (err) { |
6a4b09f8 | 1417 | dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err); |
9f904b38 EG |
1418 | /* enable rfkill interrupt: hw bug w/a */ |
1419 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1420 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1421 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1422 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1423 | } | |
1424 | } | |
a42a1844 EG |
1425 | |
1426 | trans->dev = &pdev->dev; | |
75595536 | 1427 | trans_pcie->irq = pdev->irq; |
a42a1844 | 1428 | trans_pcie->pci_dev = pdev; |
08079a49 | 1429 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 1430 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
1431 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
1432 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 1433 | |
69a10b29 | 1434 | /* Initialize the wait queue for commands */ |
f946b529 | 1435 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
8b5bed90 | 1436 | spin_lock_init(&trans->reg_lock); |
69a10b29 | 1437 | |
3ec45882 JB |
1438 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
1439 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
1440 | |
1441 | trans->dev_cmd_headroom = 0; | |
1442 | trans->dev_cmd_pool = | |
3ec45882 | 1443 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
1444 | sizeof(struct iwl_device_cmd) |
1445 | + trans->dev_cmd_headroom, | |
1446 | sizeof(void *), | |
1447 | SLAB_HWCACHE_ALIGN, | |
1448 | NULL); | |
1449 | ||
1450 | if (!trans->dev_cmd_pool) | |
1451 | goto out_pci_disable_msi; | |
1452 | ||
a42a1844 EG |
1453 | return trans; |
1454 | ||
59c647b6 EG |
1455 | out_pci_disable_msi: |
1456 | pci_disable_msi(pdev); | |
a42a1844 EG |
1457 | out_pci_release_regions: |
1458 | pci_release_regions(pdev); | |
1459 | out_pci_disable_device: | |
1460 | pci_disable_device(pdev); | |
1461 | out_no_pci: | |
1462 | kfree(trans); | |
1463 | return NULL; | |
1464 | } |