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iwlwifi: mvm: print secboot status registers on alive timeout
[linux-block.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
553452e5
LK		 34 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
cb6bb128 78#include "iwl-scd.h"
7a10e3e4 79#include "iwl-agn-hw.h"
4d075007 80#include "iwl-fw-error-dump.h"
6468a01a 81#include "internal.h"
06d51e0d 82#include "iwl-fh.h"
0439bb62 83
fe45773b
AN		 84/* extended range in FW SRAM */
85#define IWL_FW_MEM_EXTENDED_START 0x40000
86#define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
c2d20201
EG		 88static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89{
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102}
103
96c285da 104static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 105{
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 107 struct page *page = NULL;
c2d20201 108 dma_addr_t phys;
96c285da 109 u32 size = 0;
c2d20201
EG		 110 u8 power;
111
96c285da
EG		 112 if (!max_power) {
113 /* default max_power is maximum */
114 max_power = 26;
115 } else {
116 max_power += 11;
117 }
118
119 if (WARN(max_power > 26,
120 "External buffer size for monitor is too big %d, check the FW TLV\n",
121 max_power))
122 return;
123
c2d20201
EG		 124 if (trans_pcie->fw_mon_page) {
125 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
126 trans_pcie->fw_mon_size,
127 DMA_FROM_DEVICE);
128 return;
129 }
130
131 phys = 0;
96c285da 132 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 133 int order;
134
135 size = BIT(power);
136 order = get_order(size);
137 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
138 order);
139 if (!page)
140 continue;
141
142 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
143 DMA_FROM_DEVICE);
144 if (dma_mapping_error(trans->dev, phys)) {
145 __free_pages(page, order);
553452e5 146 page = NULL;
c2d20201
EG		 147 continue;
148 }
149 IWL_INFO(trans,
150 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
151 size, order);
152 break;
153 }
154
40a76905 155 if (WARN_ON_ONCE(!page))
c2d20201
EG		 156 return;
157
96c285da
EG		 158 if (power != max_power)
159 IWL_ERR(trans,
160 "Sorry - debug buffer is only %luK while you requested %luK\n",
161 (unsigned long)BIT(power - 10),
162 (unsigned long)BIT(max_power - 10));
163
c2d20201
EG		 164 trans_pcie->fw_mon_page = page;
165 trans_pcie->fw_mon_phys = phys;
166 trans_pcie->fw_mon_size = size;
167}
168
a812cba9
AB		 169static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
170{
171 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
172 ((reg & 0x0000ffff) | (2 << 28)));
173 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
174}
175
176static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
177{
178 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
179 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
180 ((reg & 0x0000ffff) | (3 << 28)));
181}
182
ddaf5a5b 183static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 184{
95411d04
AA		 185 if (!trans->cfg->apmg_not_supported)
186 return;
187
ddaf5a5b
JB		 188 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
189 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
190 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
191 ~APMG_PS_CTRL_MSK_PWR_SRC);
192 else
193 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
194 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
195 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 196}
197
af634bee
EG		 198/* PCI registers */
199#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 200
7afe3705 201static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 202{
20d3b647 203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 204 u16 lctl;
9180ac50 205 u16 cap;
af634bee 206
af634bee
EG		 207 /*
208 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
209 * Check if BIOS (or OS) enabled L1-ASPM on this device.
210 * If so (likely), disable L0S, so device moves directly L0->L1;
211 * costs negligible amount of power savings.
212 * If not (unlikely), enable L0S, so there is at least some
213 * power savings, even without L1.
214 */
7afe3705 215 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 216 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 217 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 218 else
af634bee 219 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 220 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 221
222 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
223 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
224 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
225 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
226 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 227}
228
a6c684ee
EG		 229/*
230 * Start up NIC's basic functionality after it has been reset
7afe3705 231 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 232 * NOTE: This does not load uCode nor start the embedded processor
233 */
7afe3705 234static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 235{
236 int ret = 0;
237 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
238
239 /*
240 * Use "set_bit" below rather than "write", to preserve any hardware
241 * bits already set by default after reset.
242 */
243
244 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 245 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
246 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
247 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 248
249 /*
250 * Disable L0s without affecting L1;
251 * don't wait for ICH L0s (ICH bug W/A)
252 */
253 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 254 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 255
256 /* Set FH wait threshold to maximum (HW error during stress W/A) */
257 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
258
259 /*
260 * Enable HAP INTA (interrupt from management bus) to
261 * wake device's PCI Express link L1a -> L0s
262 */
263 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 264 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 265
7afe3705 266 iwl_pcie_apm_config(trans);
a6c684ee
EG		 267
268 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 269 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 270 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 271 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 272
273 /*
274 * Set "initialization complete" bit to move adapter from
275 * D0U* --> D0A* (powered-up active) state.
276 */
277 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
278
279 /*
280 * Wait for clock stabilization; once stabilized, access to
281 * device-internal resources is supported, e.g. iwl_write_prph()
282 * and accesses to uCode SRAM.
283 */
284 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 285 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
286 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 287 if (ret < 0) {
288 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
289 goto out;
290 }
291
2d93aee1
EG		 292 if (trans->cfg->host_interrupt_operation_mode) {
293 /*
294 * This is a bit of an abuse - This is needed for 7260 / 3160
295 * only check host_interrupt_operation_mode even if this is
296 * not related to host_interrupt_operation_mode.
297 *
298 * Enable the oscillator to count wake up time for L1 exit. This
299 * consumes slightly more power (100uA) - but allows to be sure
300 * that we wake up from L1 on time.
301 *
302 * This looks weird: read twice the same register, discard the
303 * value, set a bit, and yet again, read that same register
304 * just to discard the value. But that's the way the hardware
305 * seems to like it.
306 */
307 iwl_read_prph(trans, OSC_CLK);
308 iwl_read_prph(trans, OSC_CLK);
309 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 }
313
a6c684ee
EG		 314 /*
315 * Enable DMA clock and wait for it to stabilize.
316 *
3073d8c0
EH		 317 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
318 * bits do not disable clocks. This preserves any hardware
319 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 320 */
95411d04 321 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 322 iwl_write_prph(trans, APMG_CLK_EN_REG,
323 APMG_CLK_VAL_DMA_CLK_RQT);
324 udelay(20);
325
326 /* Disable L1-Active */
327 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
328 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
329
330 /* Clear the interrupt in APMG if the NIC is in RFKILL */
331 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
332 APMG_RTC_INT_STT_RFKILL);
333 }
889b1696 334
eb7ff77e 335 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 336
337out:
338 return ret;
339}
340
a812cba9
AB		 341/*
342 * Enable LP XTAL to avoid HW bug where device may consume much power if
343 * FW is not loaded after device reset. LP XTAL is disabled by default
344 * after device HW reset. Do it only if XTAL is fed by internal source.
345 * Configure device's "persistence" mode to avoid resetting XTAL again when
346 * SHRD_HW_RST occurs in S3.
347 */
348static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
349{
350 int ret;
351 u32 apmg_gp1_reg;
352 u32 apmg_xtal_cfg_reg;
353 u32 dl_cfg_reg;
354
355 /* Force XTAL ON */
356 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
357 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
358
359 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
360 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
361
362 udelay(10);
363
364 /*
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
367 */
368 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
369
370 /*
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is possible.
373 */
374 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 25000);
378 if (WARN_ON(ret < 0)) {
379 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
380 /* Release XTAL ON request */
381 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383 return;
384 }
385
386 /*
387 * Clear "disable persistence" to avoid LP XTAL resetting when
388 * SHRD_HW_RST is applied in S3.
389 */
390 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
391 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
392
393 /*
394 * Force APMG XTAL to be active to prevent its disabling by HW
395 * caused by APMG idle state.
396 */
397 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
398 SHR_APMG_XTAL_CFG_REG);
399 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
400 apmg_xtal_cfg_reg |
401 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
402
403 /*
404 * Reset entire device again - do controller reset (results in
405 * SHRD_HW_RST). Turn MAC off before proceeding.
406 */
407 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
408
409 udelay(10);
410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
7afe3705 451static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
b7aaeae4 469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
b7aaeae4
EG		 473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
482 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
483 CSR_HW_IF_CONFIG_REG_PREPARE |
484 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
485 mdelay(5);
486 }
487
eb7ff77e 488 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 489
490 /* Stop device's DMA activity */
7afe3705 491 iwl_pcie_apm_stop_master(trans);
cc56feb2 492
a812cba9
AB		 493 if (trans->cfg->lp_xtal_workaround) {
494 iwl_pcie_apm_lp_xtal_enable(trans);
495 return;
496 }
497
cc56feb2
EG		 498 /* Reset the entire device */
499 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
500
501 udelay(10);
502
503 /*
504 * Clear "initialization complete" bit to move adapter from
505 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
506 */
507 iwl_clear_bit(trans, CSR_GP_CNTRL,
508 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
509}
510
7afe3705 511static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 512{
7b11488f 513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 514
515 /* nic_init */
7b70bd63 516 spin_lock(&trans_pcie->irq_lock);
7afe3705 517 iwl_pcie_apm_init(trans);
392f8b78 518
7b70bd63 519 spin_unlock(&trans_pcie->irq_lock);
392f8b78 520
95411d04 521 iwl_pcie_set_pwr(trans, false);
392f8b78 522
ecdb975c 523 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 524
525 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 526 iwl_pcie_rx_init(trans);
392f8b78
EG		 527
528 /* Allocate or reset and init all Tx and Command queues */
f02831be 529 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 530 return -ENOMEM;
531
035f7ff2 532 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 533 /* enable shadow regs in HW */
20d3b647 534 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 535 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 536 }
537
392f8b78
EG		 538 return 0;
539}
540
541#define HW_READY_TIMEOUT (50)
542
543/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 544static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 545{
546 int ret;
547
1042db2a 548 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 549 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 550
551 /* See if we got it */
1042db2a 552 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 553 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
555 HW_READY_TIMEOUT);
392f8b78 556
6a08f514
EG		 557 if (ret >= 0)
558 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
559
6d8f6eeb 560 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 561 return ret;
562}
563
564/* Note: returns standard 0/-ERROR code */
7afe3705 565static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 566{
567 int ret;
289e5501 568 int t = 0;
501fd989 569 int iter;
392f8b78 570
6d8f6eeb 571 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 572
7afe3705 573 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 574 /* If the card is ready, exit 0 */
392f8b78
EG		 575 if (ret >= 0)
576 return 0;
577
501fd989
EG		 578 for (iter = 0; iter < 10; iter++) {
579 /* If HW is not ready, prepare the conditions to check again */
580 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
581 CSR_HW_IF_CONFIG_REG_PREPARE);
582
583 do {
584 ret = iwl_pcie_set_hw_ready(trans);
585 if (ret >= 0)
586 return 0;
392f8b78 587
501fd989
EG		 588 usleep_range(200, 1000);
589 t += 200;
590 } while (t < 150000);
591 msleep(25);
592 }
392f8b78 593
7f2ac8fb 594 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 595
392f8b78
EG		 596 return ret;
597}
598
cf614297
EG		 599/*
600 * ucode
601 */
7afe3705 602static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 603 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 604{
13df1aab 605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 606 int ret;
607
13df1aab 608 trans_pcie->ucode_write_complete = false;
cf614297
EG		 609
610 iwl_write_direct32(trans,
20d3b647
JB		 611 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
612 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 613
614 iwl_write_direct32(trans,
20d3b647
JB		 615 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
616 dst_addr);
cf614297
EG		 617
618 iwl_write_direct32(trans,
83f84d7b
JB		 619 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
620 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 621
622 iwl_write_direct32(trans,
20d3b647
JB		 623 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
624 (iwl_get_dma_hi_addr(phy_addr)
625 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 626
627 iwl_write_direct32(trans,
20d3b647
JB		 628 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
630 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 632
633 iwl_write_direct32(trans,
20d3b647
JB		 634 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
637 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 638
13df1aab
JB		 639 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
640 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 641 if (!ret) {
83f84d7b 642 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 643 return -ETIMEDOUT;
644 }
645
646 return 0;
647}
648
7afe3705 649static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 650 const struct fw_desc *section)
cf614297 651{
83f84d7b
JB		 652 u8 *v_addr;
653 dma_addr_t p_addr;
baa21e83 654 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 655 int ret = 0;
656
83f84d7b
JB		 657 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
658 section_num);
659
c571573a
EG		 660 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
661 GFP_KERNEL | __GFP_NOWARN);
662 if (!v_addr) {
663 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
664 chunk_sz = PAGE_SIZE;
665 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
666 &p_addr, GFP_KERNEL);
667 if (!v_addr)
668 return -ENOMEM;
669 }
83f84d7b 670
c571573a 671 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 672 u32 copy_size, dst_addr;
673 bool extended_addr = false;
83f84d7b 674
c571573a 675 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 676 dst_addr = section->offset + offset;
677
678 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
679 dst_addr <= IWL_FW_MEM_EXTENDED_END)
680 extended_addr = true;
681
682 if (extended_addr)
683 iwl_set_bits_prph(trans, LMPM_CHICK,
684 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 685
83f84d7b 686 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 687 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
688 copy_size);
689
690 if (extended_addr)
691 iwl_clear_bits_prph(trans, LMPM_CHICK,
692 LMPM_CHICK_EXTENDED_ADDR_SPACE);
693
83f84d7b
JB		 694 if (ret) {
695 IWL_ERR(trans,
696 "Could not load the [%d] uCode section\n",
697 section_num);
698 break;
6dfa8d01 699 }
83f84d7b
JB		 700 }
701
c571573a 702 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 703 return ret;
704}
705
16bc119b
EH		 706/*
707 * Driver Takes the ownership on secure machine before FW load
708 * and prevent race with the BT load.
709 * W/A for ROM bug. (should be remove in the next Si step)
710 */
711static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
712{
713 u32 val, loop = 1000;
714
1e167071
EH		 715 /*
716 * Check the RSA semaphore is accessible.
717 * If the HW isn't locked and the rsa semaphore isn't accessible,
718 * we are in trouble.
719 */
16bc119b
EH		 720 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
721 if (val & (BIT(1) | BIT(17))) {
1e167071
EH		 722 IWL_INFO(trans,
723 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 724 return 0;
725 }
726
727 /* take ownership on the AUX IF */
728 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
729 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
730
731 do {
732 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
733 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
734 if (val == 0x1) {
735 iwl_write_prph(trans, RSA_ENABLE, 0);
736 return 0;
737 }
738
739 udelay(10);
740 loop--;
741 } while (loop > 0);
742
743 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
744 return -EIO;
745}
746
5dd9c68a
EG		 747static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
748 const struct fw_img *image,
749 int cpu,
750 int *first_ucode_section)
e2d6f4e7
EH		 751{
752 int shift_param;
dcab8ecd
EH		 753 int i, ret = 0, sec_num = 0x1;
754 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 755
756 if (cpu == 1) {
757 shift_param = 0;
034846cf 758 *first_ucode_section = 0;
e2d6f4e7
EH		 759 } else {
760 shift_param = 16;
034846cf 761 (*first_ucode_section)++;
e2d6f4e7
EH		 762 }
763
034846cf
EH		 764 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
765 last_read_idx = i;
766
a6c4fb44
MG		 767 /*
768 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
769 * CPU1 to CPU2.
770 * PAGING_SEPARATOR_SECTION delimiter - separate between
771 * CPU2 non paged to CPU2 paging sec.
772 */
034846cf 773 if (!image->sec[i].data ||
a6c4fb44
MG		 774 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
775 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 776 IWL_DEBUG_FW(trans,
777 "Break since Data not valid or Empty section, sec = %d\n",
778 i);
189fa2fa 779 break;
034846cf
EH		 780 }
781
189fa2fa
EH		 782 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
783 if (ret)
784 return ret;
dcab8ecd
EH		 785
786 /* Notify the ucode of the loaded section number and status */
787 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
788 val = val | (sec_num << shift_param);
789 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
790 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 791 }
792
034846cf
EH		 793 *first_ucode_section = last_read_idx;
794
afb88917
EH		 795 if (cpu == 1)
796 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
797 else
798 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
799
189fa2fa
EH		 800 return 0;
801}
e2d6f4e7 802
189fa2fa
EH		 803static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
804 const struct fw_img *image,
034846cf
EH		 805 int cpu,
806 int *first_ucode_section)
189fa2fa
EH		 807{
808 int shift_param;
189fa2fa 809 int i, ret = 0;
034846cf 810 u32 last_read_idx = 0;
189fa2fa
EH		 811
812 if (cpu == 1) {
813 shift_param = 0;
034846cf 814 *first_ucode_section = 0;
189fa2fa
EH		 815 } else {
816 shift_param = 16;
034846cf 817 (*first_ucode_section)++;
189fa2fa
EH		 818 }
819
034846cf
EH		 820 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
821 last_read_idx = i;
822
a6c4fb44
MG		 823 /*
824 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
825 * CPU1 to CPU2.
826 * PAGING_SEPARATOR_SECTION delimiter - separate between
827 * CPU2 non paged to CPU2 paging sec.
828 */
034846cf 829 if (!image->sec[i].data ||
a6c4fb44
MG		 830 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
831 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 832 IWL_DEBUG_FW(trans,
833 "Break since Data not valid or Empty section, sec = %d\n",
834 i);
189fa2fa 835 break;
034846cf
EH		 836 }
837
189fa2fa
EH		 838 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
839 if (ret)
840 return ret;
e2d6f4e7
EH		 841 }
842
189fa2fa
EH		 843 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
844 iwl_set_bits_prph(trans,
845 CSR_UCODE_LOAD_STATUS_ADDR,
846 (LMPM_CPU_UCODE_LOADING_COMPLETED |
847 LMPM_CPU_HDRS_LOADING_COMPLETED |
848 LMPM_CPU_UCODE_LOADING_STARTED) <<
849 shift_param);
850
034846cf
EH		 851 *first_ucode_section = last_read_idx;
852
e2d6f4e7
EH		 853 return 0;
854}
855
09e350f7
LK		 856static void iwl_pcie_apply_destination(struct iwl_trans *trans)
857{
858 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
859 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
860 int i;
861
862 if (dest->version)
863 IWL_ERR(trans,
864 "DBG DEST version is %d - expect issues\n",
865 dest->version);
866
867 IWL_INFO(trans, "Applying debug destination %s\n",
868 get_fw_dbg_mode_string(dest->monitor_mode));
869
870 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 871 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 872 else
873 IWL_WARN(trans, "PCI should have external buffer debug\n");
874
875 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
876 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
877 u32 val = le32_to_cpu(dest->reg_ops[i].val);
878
879 switch (dest->reg_ops[i].op) {
880 case CSR_ASSIGN:
881 iwl_write32(trans, addr, val);
882 break;
883 case CSR_SETBIT:
884 iwl_set_bit(trans, addr, BIT(val));
885 break;
886 case CSR_CLEARBIT:
887 iwl_clear_bit(trans, addr, BIT(val));
888 break;
889 case PRPH_ASSIGN:
890 iwl_write_prph(trans, addr, val);
891 break;
892 case PRPH_SETBIT:
893 iwl_set_bits_prph(trans, addr, BIT(val));
894 break;
895 case PRPH_CLEARBIT:
896 iwl_clear_bits_prph(trans, addr, BIT(val));
897 break;
869f3b15
HD		 898 case PRPH_BLOCKBIT:
899 if (iwl_read_prph(trans, addr) & BIT(val)) {
900 IWL_ERR(trans,
901 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
902 val, addr);
903 goto monitor;
904 }
905 break;
09e350f7
LK		 906 default:
907 IWL_ERR(trans, "FW debug - unknown OP %d\n",
908 dest->reg_ops[i].op);
909 break;
910 }
911 }
912
869f3b15 913monitor:
09e350f7
LK		 914 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
915 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
916 trans_pcie->fw_mon_phys >> dest->base_shift);
917 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
918 (trans_pcie->fw_mon_phys +
919 trans_pcie->fw_mon_size) >> dest->end_shift);
920 }
921}
922
7afe3705 923static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 924 const struct fw_img *image)
cf614297 925{
c2d20201 926 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 927 int ret = 0;
034846cf 928 int first_ucode_section;
cf614297 929
dcab8ecd 930 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 931 image->is_dual_cpus ? "Dual" : "Single");
932
dcab8ecd
EH		 933 /* load to FW the binary non secured sections of CPU1 */
934 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
935 if (ret)
936 return ret;
e2d6f4e7
EH		 937
938 if (image->is_dual_cpus) {
189fa2fa
EH		 939 /* set CPU2 header address */
940 iwl_write_prph(trans,
941 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
942 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 943
189fa2fa 944 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 945 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
946 &first_ucode_section);
189fa2fa
EH		 947 if (ret)
948 return ret;
e2d6f4e7 949 }
cf614297 950
c2d20201
EG		 951 /* supported for 7000 only for the moment */
952 if (iwlwifi_mod_params.fw_monitor &&
953 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 954 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 955
956 if (trans_pcie->fw_mon_size) {
957 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
958 trans_pcie->fw_mon_phys >> 4);
959 iwl_write_prph(trans, MON_BUFF_END_ADDR,
960 (trans_pcie->fw_mon_phys +
961 trans_pcie->fw_mon_size) >> 4);
962 }
09e350f7
LK		 963 } else if (trans->dbg_dest_tlv) {
964 iwl_pcie_apply_destination(trans);
c2d20201
EG		 965 }
966
e12ba844 967 /* release CPU reset */
5dd9c68a 968 iwl_write32(trans, CSR_RESET, 0);
e12ba844 969
dcab8ecd
EH		 970 return 0;
971}
189fa2fa 972
5dd9c68a
EG		 973static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
974 const struct fw_img *image)
dcab8ecd
EH		 975{
976 int ret = 0;
977 int first_ucode_section;
dcab8ecd
EH		 978
979 IWL_DEBUG_FW(trans, "working with %s CPU\n",
980 image->is_dual_cpus ? "Dual" : "Single");
981
a2227ce2
EG		 982 if (trans->dbg_dest_tlv)
983 iwl_pcie_apply_destination(trans);
984
16bc119b
EH		 985 /* TODO: remove in the next Si step */
986 ret = iwl_pcie_rsa_race_bug_wa(trans);
987 if (ret)
988 return ret;
989
dcab8ecd
EH		 990 /* configure the ucode to be ready to get the secured image */
991 /* release CPU reset */
992 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
993
994 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 995 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
996 &first_ucode_section);
dcab8ecd
EH		 997 if (ret)
998 return ret;
999
1000 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1001 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1002 &first_ucode_section);
cf614297
EG		 1003}
1004
0692fe41 1005static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 1006 const struct fw_img *fw, bool run_in_rfkill)
392f8b78 1007{
fa9f3281 1008 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1009 bool hw_rfkill;
fa9f3281
EG		 1010 int ret;
1011
1012 mutex_lock(&trans_pcie->mutex);
1013
1014 /* Someone called stop_device, don't try to start_fw */
1015 if (trans_pcie->is_down) {
1016 IWL_WARN(trans,
1017 "Can't start_fw since the HW hasn't been started\n");
1018 ret = EIO;
1019 goto out;
1020 }
392f8b78 1021
496bab39 1022 /* This may fail if AMT took ownership of the device */
7afe3705 1023 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 1024 IWL_WARN(trans, "Exit HW not ready\n");
fa9f3281
EG		 1025 ret = -EIO;
1026 goto out;
392f8b78
EG		 1027 }
1028
8c46bb70
EG		 1029 iwl_enable_rfkill_int(trans);
1030
392f8b78 1031 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 1032 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1033 if (hw_rfkill)
eb7ff77e 1034 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1035 else
eb7ff77e 1036 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1037 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
fa9f3281
EG		 1038 if (hw_rfkill && !run_in_rfkill) {
1039 ret = -ERFKILL;
1040 goto out;
1041 }
392f8b78 1042
1042db2a 1043 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 1044
7afe3705 1045 ret = iwl_pcie_nic_init(trans);
392f8b78 1046 if (ret) {
6d8f6eeb 1047 IWL_ERR(trans, "Unable to init nic\n");
fa9f3281 1048 goto out;
392f8b78
EG		 1049 }
1050
1051 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 1052 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1053 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 1054 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1055
1056 /* clear (again), then enable host interrupts */
1042db2a 1057 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 1058 iwl_enable_interrupts(trans);
392f8b78
EG		 1059
1060 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 1061 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1062 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 1063
cf614297 1064 /* Load the given image to the HW */
5dd9c68a 1065 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
fa9f3281 1066 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
dcab8ecd 1067 else
fa9f3281
EG		 1068 ret = iwl_pcie_load_given_ucode(trans, fw);
1069
1070out:
1071 mutex_unlock(&trans_pcie->mutex);
1072 return ret;
b3c2ce13
EG		 1073}
1074
adca1235 1075static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 1076{
990aa6d7 1077 iwl_pcie_reset_ict(trans);
f02831be 1078 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 1079}
1080
fa9f3281 1081static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1082{
43e58856 1083 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1084 bool hw_rfkill, was_hw_rfkill;
1085
fa9f3281
EG		 1086 lockdep_assert_held(&trans_pcie->mutex);
1087
1088 if (trans_pcie->is_down)
1089 return;
1090
1091 trans_pcie->is_down = true;
1092
3dc3374f 1093 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1094
43e58856 1095 /* tell the device to stop sending interrupts */
7b70bd63 1096 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1097 iwl_disable_interrupts(trans);
7b70bd63 1098 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1099
ab6cf8e8 1100 /* device going down, Stop using ICT table */
990aa6d7 1101 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1102
1103 /*
1104 * If a HW restart happens during firmware loading,
1105 * then the firmware loading might call this function
1106 * and later it might be called again due to the
1107 * restart. So don't process again if the device is
1108 * already dead.
1109 */
31b8b343
EG		 1110 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1111 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1112 iwl_pcie_tx_stop(trans);
9805c446 1113 iwl_pcie_rx_stop(trans);
6379103e 1114
ab6cf8e8 1115 /* Power-down device's busmaster DMA clocks */
95411d04 1116 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1117 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1118 APMG_CLK_VAL_DMA_CLK_RQT);
1119 udelay(5);
1120 }
ab6cf8e8
EG		 1121 }
1122
1123 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1124 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1125 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1126
1127 /* Stop the device, and put it in low power state */
b7aaeae4 1128 iwl_pcie_apm_stop(trans, false);
43e58856 1129
03d6c3b0
EG		 1130 /* stop and reset the on-board processor */
1131 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1132 udelay(20);
1133
1134 /*
1135 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1136 * This is a bug in certain verions of the hardware.
1137 * Certain devices also keep sending HW RF kill interrupt all
1138 * the time, unless the interrupt is ACKed even if the interrupt
1139 * should be masked. Re-ACK all the interrupts here.
43e58856 1140 */
7b70bd63 1141 spin_lock(&trans_pcie->irq_lock);
43e58856 1142 iwl_disable_interrupts(trans);
7b70bd63 1143 spin_unlock(&trans_pcie->irq_lock);
43e58856 1144
74fda971
DF		 1145
1146 /* clear all status bits */
eb7ff77e
AN		 1147 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1148 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1149 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1150 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1151
1152 /*
1153 * Even if we stop the HW, we still want the RF kill
1154 * interrupt
1155 */
1156 iwl_enable_rfkill_int(trans);
1157
1158 /*
1159 * Check again since the RF kill state may have changed while
1160 * all the interrupts were disabled, in this case we couldn't
1161 * receive the RF kill interrupt and update the state in the
1162 * op_mode.
3dc3374f
EG		 1163 * Don't call the op_mode if the rkfill state hasn't changed.
1164 * This allows the op_mode to call stop_device from the rfkill
1165 * notification without endless recursion. Under very rare
1166 * circumstances, we might have a small recursion if the rfkill
1167 * state changed exactly now while we were called from stop_device.
1168 * This is very unlikely but can happen and is supported.
a4082843
AN		 1169 */
1170 hw_rfkill = iwl_is_rfkill_set(trans);
1171 if (hw_rfkill)
eb7ff77e 1172 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1173 else
eb7ff77e 1174 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1175 if (hw_rfkill != was_hw_rfkill)
14cfca71 1176 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1177
1178 /* re-take ownership to prevent other users from stealing the deivce */
1179 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1180}
1181
fa9f3281
EG		 1182static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1183{
1184 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1185
1186 mutex_lock(&trans_pcie->mutex);
1187 _iwl_trans_pcie_stop_device(trans, low_power);
1188 mutex_unlock(&trans_pcie->mutex);
1189}
1190
14cfca71
JB		 1191void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1192{
fa9f3281
EG		 1193 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1194 IWL_TRANS_GET_PCIE_TRANS(trans);
1195
1196 lockdep_assert_held(&trans_pcie->mutex);
1197
14cfca71 1198 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1199 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1200}
1201
debff618 1202static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1203{
33b56af1
EG		 1204 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1205
6dfb36c8
EP		 1206 if (trans->wowlan_d0i3) {
1207 /* Enable persistence mode to avoid reset */
1208 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1209 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1210 }
1211
2dd4f9f7 1212 iwl_disable_interrupts(trans);
debff618
JB		 1213
1214 /*
1215 * in testing mode, the host stays awake and the
1216 * hardware won't be reset (not even partially)
1217 */
1218 if (test)
1219 return;
1220
ddaf5a5b
JB		 1221 iwl_pcie_disable_ict(trans);
1222
33b56af1
EG		 1223 synchronize_irq(trans_pcie->pci_dev->irq);
1224
2dd4f9f7
JB		 1225 iwl_clear_bit(trans, CSR_GP_CNTRL,
1226 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1227 iwl_clear_bit(trans, CSR_GP_CNTRL,
1228 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1229
6dfb36c8
EP		 1230 if (!trans->wowlan_d0i3) {
1231 /*
1232 * reset TX queues -- some of their registers reset during S3
1233 * so if we don't reset everything here the D3 image would try
1234 * to execute some invalid memory upon resume
1235 */
1236 iwl_trans_pcie_tx_reset(trans);
1237 }
ddaf5a5b
JB		 1238
1239 iwl_pcie_set_pwr(trans, true);
1240}
1241
1242static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1243 enum iwl_d3_status *status,
1244 bool test)
ddaf5a5b
JB		 1245{
1246 u32 val;
1247 int ret;
1248
debff618
JB		 1249 if (test) {
1250 iwl_enable_interrupts(trans);
1251 *status = IWL_D3_STATUS_ALIVE;
1252 return 0;
1253 }
1254
ddaf5a5b
JB		 1255 /*
1256 * Also enables interrupts - none will happen as the device doesn't
1257 * know we're waking it up, only when the opmode actually tells it
1258 * after this call.
1259 */
1260 iwl_pcie_reset_ict(trans);
1261
1262 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1263 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1264
01e58a28
EG		 1265 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1266 udelay(2);
1267
ddaf5a5b
JB		 1268 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1269 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1270 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1271 25000);
7f2ac8fb 1272 if (ret < 0) {
ddaf5a5b
JB		 1273 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1274 return ret;
1275 }
1276
a3ead656
EG		 1277 iwl_pcie_set_pwr(trans, false);
1278
6dfb36c8
EP		 1279 if (trans->wowlan_d0i3) {
1280 iwl_clear_bit(trans, CSR_GP_CNTRL,
1281 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1282 } else {
1283 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1284
6dfb36c8
EP		 1285 ret = iwl_pcie_rx_init(trans);
1286 if (ret) {
1287 IWL_ERR(trans,
1288 "Failed to resume the device (RX reset)\n");
1289 return ret;
1290 }
ddaf5a5b
JB		 1291 }
1292
a3ead656
EG		 1293 val = iwl_read32(trans, CSR_RESET);
1294 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1295 *status = IWL_D3_STATUS_RESET;
1296 else
1297 *status = IWL_D3_STATUS_ALIVE;
1298
ddaf5a5b 1299 return 0;
2dd4f9f7
JB		 1300}
1301
fa9f3281 1302static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1303{
fa9f3281 1304 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1305 bool hw_rfkill;
a8b691e6 1306 int err;
e6bb4c9c 1307
fa9f3281
EG		 1308 lockdep_assert_held(&trans_pcie->mutex);
1309
7afe3705 1310 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1311 if (err) {
d6f1c316 1312 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1313 return err;
ebb7678d 1314 }
a6c684ee 1315
2997494f 1316 /* Reset the entire device */
ce836c76 1317 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1318
1319 usleep_range(10, 15);
1320
7afe3705 1321 iwl_pcie_apm_init(trans);
a6c684ee 1322
226c02ca
EG		 1323 /* From now on, the op_mode will be kept updated about RF kill state */
1324 iwl_enable_rfkill_int(trans);
1325
fa9f3281
EG		 1326 /* Set is_down to false here so that...*/
1327 trans_pcie->is_down = false;
1328
8d425517 1329 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1330 if (hw_rfkill)
eb7ff77e 1331 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1332 else
eb7ff77e 1333 clear_bit(STATUS_RFKILL, &trans->status);
fa9f3281 1334 /* ... rfkill can call stop_device and set it false if needed */
14cfca71 1335 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1336
a8b691e6 1337 return 0;
e6bb4c9c
EG		 1338}
1339
fa9f3281
EG		 1340static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1341{
1342 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1343 int ret;
1344
1345 mutex_lock(&trans_pcie->mutex);
1346 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1347 mutex_unlock(&trans_pcie->mutex);
1348
1349 return ret;
1350}
1351
a4082843 1352static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1353{
20d3b647 1354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1355
fa9f3281
EG		 1356 mutex_lock(&trans_pcie->mutex);
1357
a4082843 1358 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1359 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1360 iwl_disable_interrupts(trans);
7b70bd63 1361 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1362
b7aaeae4 1363 iwl_pcie_apm_stop(trans, true);
cc56feb2 1364
7b70bd63 1365 spin_lock(&trans_pcie->irq_lock);
218733cf 1366 iwl_disable_interrupts(trans);
7b70bd63 1367 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1368
8d96bb61 1369 iwl_pcie_disable_ict(trans);
33b56af1 1370
fa9f3281 1371 mutex_unlock(&trans_pcie->mutex);
33b56af1
EG		 1372
1373 synchronize_irq(trans_pcie->pci_dev->irq);
cc56feb2
EG		 1374}
1375
03905495
EG		 1376static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1377{
05f5b97e 1378 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1379}
1380
1381static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1382{
05f5b97e 1383 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1384}
1385
1386static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1387{
05f5b97e 1388 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1389}
1390
6a06b6c1
EG		 1391static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1392{
f9477c17
AP		 1393 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1394 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1395 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1396}
1397
1398static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1399 u32 val)
1400{
1401 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1402 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1403 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1404}
1405
f14d6b39
JB		 1406static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1407{
1408 WARN_ON(1);
1409 return 0;
1410}
1411
c6f600fc 1412static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1413 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1414{
1415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1416
1417 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1418 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1419 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1420 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1421 trans_pcie->n_no_reclaim_cmds = 0;
1422 else
1423 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1424 if (trans_pcie->n_no_reclaim_cmds)
1425 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1426 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1427
b2cf410c
JB		 1428 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1429 if (trans_pcie->rx_buf_size_8k)
1430 trans_pcie->rx_page_order = get_order(8 * 1024);
1431 else
1432 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8 1433
ab02165c 1434 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
d9fb6465 1435 trans_pcie->command_names = trans_cfg->command_names;
046db346 1436 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1437 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39 1438
483f3ab1
EP		 1439 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1440 trans_pcie->ref_count = 1;
1441
f14d6b39
JB		 1442 /* Initialize NAPI here - it should be before registering to mac80211
1443 * in the opmode but after the HW struct is allocated.
1444 * As this function may be called again in some corner cases don't
1445 * do anything if NAPI was already initialized.
1446 */
1447 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1448 init_dummy_netdev(&trans_pcie->napi_dev);
1449 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1450 &trans_pcie->napi_dev,
1451 iwl_pcie_dummy_napi_poll, 64);
1452 }
c6f600fc
MV		 1453}
1454
d1ff5253 1455void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1456{
20d3b647 1457 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1458
0aa86df6 1459 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1460
f02831be 1461 iwl_pcie_tx_free(trans);
9805c446 1462 iwl_pcie_rx_free(trans);
6379103e 1463
a8b691e6
JB		 1464 free_irq(trans_pcie->pci_dev->irq, trans);
1465 iwl_pcie_free_ict(trans);
a42a1844
EG		 1466
1467 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1468 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1469 pci_release_regions(trans_pcie->pci_dev);
1470 pci_disable_device(trans_pcie->pci_dev);
1471
f14d6b39
JB		 1472 if (trans_pcie->napi.poll)
1473 netif_napi_del(&trans_pcie->napi);
1474
c2d20201
EG		 1475 iwl_pcie_free_fw_monitor(trans);
1476
7b501d10 1477 iwl_trans_free(trans);
34c1b7ba
EG		 1478}
1479
47107e84
DF		 1480static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1481{
47107e84 1482 if (state)
eb7ff77e 1483 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1484 else
eb7ff77e 1485 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1486}
1487
e56b04ef
LE		 1488static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1489 unsigned long *flags)
7a65d170
EG		 1490{
1491 int ret;
cfb4e624
JB		 1492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1493
1494 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1495
fc8a350d 1496 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1497 goto out;
1498
7a65d170 1499 /* this bit wakes up the NIC */
e139dc4a
LE		 1500 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1501 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1502 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1503 udelay(2);
7a65d170
EG		 1504
1505 /*
1506 * These bits say the device is running, and should keep running for
1507 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1508 * but they do not indicate that embedded SRAM is restored yet;
1509 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1510 * to/from host DRAM when sleeping/waking for power-saving.
1511 * Each direction takes approximately 1/4 millisecond; with this
1512 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1513 * series of register accesses are expected (e.g. reading Event Log),
1514 * to keep device from sleeping.
1515 *
1516 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1517 * SRAM is okay/restored. We don't check that here because this call
1518 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1519 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1520 *
1521 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1522 * and do not save/restore SRAM when power cycling.
1523 */
1524 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1525 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1526 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1527 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1528 if (unlikely(ret < 0)) {
1529 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1530 if (!silent) {
1531 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1532 WARN_ONCE(1,
1533 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1534 val);
cfb4e624 1535 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1536 return false;
1537 }
1538 }
1539
b9439491 1540out:
e56b04ef
LE		 1541 /*
1542 * Fool sparse by faking we release the lock - sparse will
1543 * track nic_access anyway.
1544 */
cfb4e624 1545 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1546 return true;
1547}
1548
e56b04ef
LE		 1549static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1550 unsigned long *flags)
7a65d170 1551{
cfb4e624 1552 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1553
cfb4e624 1554 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1555
1556 /*
1557 * Fool sparse by faking we acquiring the lock - sparse will
1558 * track nic_access anyway.
1559 */
cfb4e624 1560 __acquire(&trans_pcie->reg_lock);
e56b04ef 1561
fc8a350d 1562 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1563 goto out;
1564
e139dc4a
LE		 1565 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1566 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1567 /*
1568 * Above we read the CSR_GP_CNTRL register, which will flush
1569 * any previous writes, but we need the write that clears the
1570 * MAC_ACCESS_REQ bit to be performed before any other writes
1571 * scheduled on different CPUs (after we drop reg_lock).
1572 */
1573 mmiowb();
b9439491 1574out:
cfb4e624 1575 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1576}
1577
4fd442db
EG		 1578static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1579 void *buf, int dwords)
1580{
1581 unsigned long flags;
1582 int offs, ret = 0;
1583 u32 *vals = buf;
1584
e56b04ef 1585 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1586 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1587 for (offs = 0; offs < dwords; offs++)
1588 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1589 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1590 } else {
1591 ret = -EBUSY;
1592 }
4fd442db
EG		 1593 return ret;
1594}
1595
1596static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1597 const void *buf, int dwords)
4fd442db
EG		 1598{
1599 unsigned long flags;
1600 int offs, ret = 0;
bf0fd5da 1601 const u32 *vals = buf;
4fd442db 1602
e56b04ef 1603 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1604 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1605 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1606 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1607 vals ? vals[offs] : 0);
e56b04ef 1608 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1609 } else {
1610 ret = -EBUSY;
1611 }
4fd442db
EG		 1612 return ret;
1613}
7a65d170 1614
e0b8d405
EG		 1615static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1616 unsigned long txqs,
1617 bool freeze)
1618{
1619 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1620 int queue;
1621
1622 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1623 struct iwl_txq *txq = &trans_pcie->txq[queue];
1624 unsigned long now;
1625
1626 spin_lock_bh(&txq->lock);
1627
1628 now = jiffies;
1629
1630 if (txq->frozen == freeze)
1631 goto next_queue;
1632
1633 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1634 freeze ? "Freezing" : "Waking", queue);
1635
1636 txq->frozen = freeze;
1637
1638 if (txq->q.read_ptr == txq->q.write_ptr)
1639 goto next_queue;
1640
1641 if (freeze) {
1642 if (unlikely(time_after(now,
1643 txq->stuck_timer.expires))) {
1644 /*
1645 * The timer should have fired, maybe it is
1646 * spinning right now on the lock.
1647 */
1648 goto next_queue;
1649 }
1650 /* remember how long until the timer fires */
1651 txq->frozen_expiry_remainder =
1652 txq->stuck_timer.expires - now;
1653 del_timer(&txq->stuck_timer);
1654 goto next_queue;
1655 }
1656
1657 /*
1658 * Wake a non-empty queue -> arm timer with the
1659 * remainder before it froze
1660 */
1661 mod_timer(&txq->stuck_timer,
1662 now + txq->frozen_expiry_remainder);
1663
1664next_queue:
1665 spin_unlock_bh(&txq->lock);
1666 }
1667}
1668
5f178cd2
EG		 1669#define IWL_FLUSH_WAIT_MS 2000
1670
3cafdbe6 1671static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1672{
8ad71bef 1673 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1674 struct iwl_txq *txq;
5f178cd2
EG		 1675 struct iwl_queue *q;
1676 int cnt;
1677 unsigned long now = jiffies;
1c3fea82
EG		 1678 u32 scd_sram_addr;
1679 u8 buf[16];
5f178cd2
EG		 1680 int ret = 0;
1681
1682 /* waiting for all the tx frames complete might take a while */
035f7ff2 1683 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1684 u8 wr_ptr;
1685
9ba1947a 1686 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1687 continue;
3cafdbe6
EG		 1688 if (!test_bit(cnt, trans_pcie->queue_used))
1689 continue;
1690 if (!(BIT(cnt) & txq_bm))
1691 continue;
748fa67c
EG		 1692
1693 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1694 txq = &trans_pcie->txq[cnt];
5f178cd2 1695 q = &txq->q;
fa1a91fd
EG		 1696 wr_ptr = ACCESS_ONCE(q->write_ptr);
1697
1698 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1699 !time_after(jiffies,
1700 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1701 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1702
1703 if (WARN_ONCE(wr_ptr != write_ptr,
1704 "WR pointer moved while flushing %d -> %d\n",
1705 wr_ptr, write_ptr))
1706 return -ETIMEDOUT;
5f178cd2 1707 msleep(1);
fa1a91fd 1708 }
5f178cd2
EG		 1709
1710 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1711 IWL_ERR(trans,
1712 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1713 ret = -ETIMEDOUT;
1714 break;
1715 }
748fa67c 1716 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1717 }
1c3fea82
EG		 1718
1719 if (!ret)
1720 return 0;
1721
1722 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1723 txq->q.read_ptr, txq->q.write_ptr);
1724
1725 scd_sram_addr = trans_pcie->scd_base_addr +
1726 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1727 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1728
1729 iwl_print_hex_error(trans, buf, sizeof(buf));
1730
1731 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1732 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1733 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1734
1735 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1736 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1737 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1738 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1739 u32 tbl_dw =
1740 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1741 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1742
1743 if (cnt & 0x1)
1744 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1745 else
1746 tbl_dw = tbl_dw & 0x0000FFFF;
1747
1748 IWL_ERR(trans,
1749 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1750 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1751 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1752 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1753 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1754 }
1755
5f178cd2
EG		 1756 return ret;
1757}
1758
e139dc4a
LE		 1759static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1760 u32 mask, u32 value)
1761{
e56b04ef 1762 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1763 unsigned long flags;
1764
e56b04ef 1765 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1766 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1767 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1768}
1769
7616f334
EP		 1770void iwl_trans_pcie_ref(struct iwl_trans *trans)
1771{
1772 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1773 unsigned long flags;
1774
1775 if (iwlwifi_mod_params.d0i3_disable)
1776 return;
1777
1778 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1779 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1780 trans_pcie->ref_count++;
1781 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1782}
1783
1784void iwl_trans_pcie_unref(struct iwl_trans *trans)
1785{
1786 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1787 unsigned long flags;
1788
1789 if (iwlwifi_mod_params.d0i3_disable)
1790 return;
1791
1792 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1793 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1794 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1795 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1796 return;
1797 }
1798 trans_pcie->ref_count--;
1799 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1800}
1801
ff620849
EG		 1802static const char *get_csr_string(int cmd)
1803{
d9fb6465 1804#define IWL_CMD(x) case x: return #x
ff620849
EG		 1805 switch (cmd) {
1806 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1807 IWL_CMD(CSR_INT_COALESCING);
1808 IWL_CMD(CSR_INT);
1809 IWL_CMD(CSR_INT_MASK);
1810 IWL_CMD(CSR_FH_INT_STATUS);
1811 IWL_CMD(CSR_GPIO_IN);
1812 IWL_CMD(CSR_RESET);
1813 IWL_CMD(CSR_GP_CNTRL);
1814 IWL_CMD(CSR_HW_REV);
1815 IWL_CMD(CSR_EEPROM_REG);
1816 IWL_CMD(CSR_EEPROM_GP);
1817 IWL_CMD(CSR_OTP_GP_REG);
1818 IWL_CMD(CSR_GIO_REG);
1819 IWL_CMD(CSR_GP_UCODE_REG);
1820 IWL_CMD(CSR_GP_DRIVER_REG);
1821 IWL_CMD(CSR_UCODE_DRV_GP1);
1822 IWL_CMD(CSR_UCODE_DRV_GP2);
1823 IWL_CMD(CSR_LED_REG);
1824 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1825 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1826 IWL_CMD(CSR_ANA_PLL_CFG);
1827 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1828 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1829 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1830 default:
1831 return "UNKNOWN";
1832 }
d9fb6465 1833#undef IWL_CMD
ff620849
EG		 1834}
1835
990aa6d7 1836void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1837{
1838 int i;
1839 static const u32 csr_tbl[] = {
1840 CSR_HW_IF_CONFIG_REG,
1841 CSR_INT_COALESCING,
1842 CSR_INT,
1843 CSR_INT_MASK,
1844 CSR_FH_INT_STATUS,
1845 CSR_GPIO_IN,
1846 CSR_RESET,
1847 CSR_GP_CNTRL,
1848 CSR_HW_REV,
1849 CSR_EEPROM_REG,
1850 CSR_EEPROM_GP,
1851 CSR_OTP_GP_REG,
1852 CSR_GIO_REG,
1853 CSR_GP_UCODE_REG,
1854 CSR_GP_DRIVER_REG,
1855 CSR_UCODE_DRV_GP1,
1856 CSR_UCODE_DRV_GP2,
1857 CSR_LED_REG,
1858 CSR_DRAM_INT_TBL_REG,
1859 CSR_GIO_CHICKEN_BITS,
1860 CSR_ANA_PLL_CFG,
a812cba9 1861 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1862 CSR_HW_REV_WA_REG,
1863 CSR_DBG_HPET_MEM_REG
1864 };
1865 IWL_ERR(trans, "CSR values:\n");
1866 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1867 "CSR_INT_PERIODIC_REG)\n");
1868 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1869 IWL_ERR(trans, " %25s: 0X%08x\n",
1870 get_csr_string(csr_tbl[i]),
1042db2a 1871 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1872 }
1873}
1874
87e5666c
EG		 1875#ifdef CONFIG_IWLWIFI_DEBUGFS
1876/* create and remove of files */
1877#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1878 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1879 &iwl_dbgfs_##name##_ops)) \
9da987ac 1880 goto err; \
87e5666c
EG		 1881} while (0)
1882
1883/* file operation */
87e5666c 1884#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1885static const struct file_operations iwl_dbgfs_##name##_ops = { \
1886 .read = iwl_dbgfs_##name##_read, \
234e3405 1887 .open = simple_open, \
87e5666c
EG		 1888 .llseek = generic_file_llseek, \
1889};
1890
16db88ba 1891#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1892static const struct file_operations iwl_dbgfs_##name##_ops = { \
1893 .write = iwl_dbgfs_##name##_write, \
234e3405 1894 .open = simple_open, \
16db88ba
EG		 1895 .llseek = generic_file_llseek, \
1896};
1897
87e5666c 1898#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1899static const struct file_operations iwl_dbgfs_##name##_ops = { \
1900 .write = iwl_dbgfs_##name##_write, \
1901 .read = iwl_dbgfs_##name##_read, \
234e3405 1902 .open = simple_open, \
87e5666c
EG		 1903 .llseek = generic_file_llseek, \
1904};
1905
87e5666c 1906static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1907 char __user *user_buf,
1908 size_t count, loff_t *ppos)
8ad71bef 1909{
5a878bf6 1910 struct iwl_trans *trans = file->private_data;
8ad71bef 1911 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1912 struct iwl_txq *txq;
87e5666c
EG		 1913 struct iwl_queue *q;
1914 char *buf;
1915 int pos = 0;
1916 int cnt;
1917 int ret;
1745e440
WYG		 1918 size_t bufsz;
1919
e0b8d405 1920 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 1921
f9e75447 1922 if (!trans_pcie->txq)
87e5666c 1923 return -EAGAIN;
f9e75447 1924
87e5666c
EG		 1925 buf = kzalloc(bufsz, GFP_KERNEL);
1926 if (!buf)
1927 return -ENOMEM;
1928
035f7ff2 1929 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1930 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1931 q = &txq->q;
1932 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 1933 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 1934 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1935 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 1936 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 1937 txq->need_update, txq->frozen,
f40faf62 1938 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1939 }
1940 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1941 kfree(buf);
1942 return ret;
1943}
1944
1945static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1946 char __user *user_buf,
1947 size_t count, loff_t *ppos)
1948{
5a878bf6 1949 struct iwl_trans *trans = file->private_data;
20d3b647 1950 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1951 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1952 char buf[256];
1953 int pos = 0;
1954 const size_t bufsz = sizeof(buf);
1955
1956 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1957 rxq->read);
1958 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1959 rxq->write);
f40faf62
AL		 1960 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1961 rxq->write_actual);
1962 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1963 rxq->need_update);
87e5666c
EG		 1964 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1965 rxq->free_count);
1966 if (rxq->rb_stts) {
1967 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1968 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1969 } else {
1970 pos += scnprintf(buf + pos, bufsz - pos,
1971 "closed_rb_num: Not Allocated\n");
1972 }
1973 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1974}
1975
1f7b6172
EG		 1976static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1977 char __user *user_buf,
20d3b647
JB		 1978 size_t count, loff_t *ppos)
1979{
1f7b6172 1980 struct iwl_trans *trans = file->private_data;
20d3b647 1981 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1982 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1983
1984 int pos = 0;
1985 char *buf;
1986 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1987 ssize_t ret;
1988
1989 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1990 if (!buf)
1f7b6172 1991 return -ENOMEM;
1f7b6172
EG		 1992
1993 pos += scnprintf(buf + pos, bufsz - pos,
1994 "Interrupt Statistics Report:\n");
1995
1996 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1997 isr_stats->hw);
1998 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1999 isr_stats->sw);
2000 if (isr_stats->sw || isr_stats->hw) {
2001 pos += scnprintf(buf + pos, bufsz - pos,
2002 "\tLast Restarting Code: 0x%X\n",
2003 isr_stats->err_code);
2004 }
2005#ifdef CONFIG_IWLWIFI_DEBUG
2006 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2007 isr_stats->sch);
2008 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2009 isr_stats->alive);
2010#endif
2011 pos += scnprintf(buf + pos, bufsz - pos,
2012 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2013
2014 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2015 isr_stats->ctkill);
2016
2017 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2018 isr_stats->wakeup);
2019
2020 pos += scnprintf(buf + pos, bufsz - pos,
2021 "Rx command responses:\t\t %u\n", isr_stats->rx);
2022
2023 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2024 isr_stats->tx);
2025
2026 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2027 isr_stats->unhandled);
2028
2029 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2030 kfree(buf);
2031 return ret;
2032}
2033
2034static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2035 const char __user *user_buf,
2036 size_t count, loff_t *ppos)
2037{
2038 struct iwl_trans *trans = file->private_data;
20d3b647 2039 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2040 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2041
2042 char buf[8];
2043 int buf_size;
2044 u32 reset_flag;
2045
2046 memset(buf, 0, sizeof(buf));
2047 buf_size = min(count, sizeof(buf) - 1);
2048 if (copy_from_user(buf, user_buf, buf_size))
2049 return -EFAULT;
2050 if (sscanf(buf, "%x", &reset_flag) != 1)
2051 return -EFAULT;
2052 if (reset_flag == 0)
2053 memset(isr_stats, 0, sizeof(*isr_stats));
2054
2055 return count;
2056}
2057
16db88ba 2058static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2059 const char __user *user_buf,
2060 size_t count, loff_t *ppos)
16db88ba
EG		 2061{
2062 struct iwl_trans *trans = file->private_data;
2063 char buf[8];
2064 int buf_size;
2065 int csr;
2066
2067 memset(buf, 0, sizeof(buf));
2068 buf_size = min(count, sizeof(buf) - 1);
2069 if (copy_from_user(buf, user_buf, buf_size))
2070 return -EFAULT;
2071 if (sscanf(buf, "%d", &csr) != 1)
2072 return -EFAULT;
2073
990aa6d7 2074 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2075
2076 return count;
2077}
2078
16db88ba 2079static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2080 char __user *user_buf,
2081 size_t count, loff_t *ppos)
16db88ba
EG		 2082{
2083 struct iwl_trans *trans = file->private_data;
94543a8d 2084 char *buf = NULL;
56c2477f 2085 ssize_t ret;
16db88ba 2086
56c2477f
JB		 2087 ret = iwl_dump_fh(trans, &buf);
2088 if (ret < 0)
2089 return ret;
2090 if (!buf)
2091 return -EINVAL;
2092 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2093 kfree(buf);
16db88ba
EG		 2094 return ret;
2095}
2096
1f7b6172 2097DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2098DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2099DEBUGFS_READ_FILE_OPS(rx_queue);
2100DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2101DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 2102
2103/*
2104 * Create the debugfs files and directories
2105 *
2106 */
2107static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 2108 struct dentry *dir)
87e5666c 2109{
87e5666c
EG		 2110 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2111 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2112 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2113 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2114 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2115 return 0;
9da987ac
MV		 2116
2117err:
2118 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2119 return -ENOMEM;
87e5666c 2120}
aadede6e
JB		 2121#else
2122static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2123 struct dentry *dir)
2124{
2125 return 0;
2126}
2127#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2128
2129static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2130{
2131 u32 cmdlen = 0;
2132 int i;
2133
2134 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2135 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2136
2137 return cmdlen;
2138}
2139
67c65f2c
EG		 2140static const struct {
2141 u32 start, end;
2142} iwl_prph_dump_addr[] = {
2143 { .start = 0x00a00000, .end = 0x00a00000 },
2144 { .start = 0x00a0000c, .end = 0x00a00024 },
2145 { .start = 0x00a0002c, .end = 0x00a0003c },
2146 { .start = 0x00a00410, .end = 0x00a00418 },
2147 { .start = 0x00a00420, .end = 0x00a00420 },
2148 { .start = 0x00a00428, .end = 0x00a00428 },
2149 { .start = 0x00a00430, .end = 0x00a0043c },
2150 { .start = 0x00a00444, .end = 0x00a00444 },
2151 { .start = 0x00a004c0, .end = 0x00a004cc },
2152 { .start = 0x00a004d8, .end = 0x00a004d8 },
2153 { .start = 0x00a004e0, .end = 0x00a004f0 },
2154 { .start = 0x00a00840, .end = 0x00a00840 },
2155 { .start = 0x00a00850, .end = 0x00a00858 },
2156 { .start = 0x00a01004, .end = 0x00a01008 },
2157 { .start = 0x00a01010, .end = 0x00a01010 },
2158 { .start = 0x00a01018, .end = 0x00a01018 },
2159 { .start = 0x00a01024, .end = 0x00a01024 },
2160 { .start = 0x00a0102c, .end = 0x00a01034 },
2161 { .start = 0x00a0103c, .end = 0x00a01040 },
2162 { .start = 0x00a01048, .end = 0x00a01094 },
2163 { .start = 0x00a01c00, .end = 0x00a01c20 },
2164 { .start = 0x00a01c58, .end = 0x00a01c58 },
2165 { .start = 0x00a01c7c, .end = 0x00a01c7c },
2166 { .start = 0x00a01c28, .end = 0x00a01c54 },
2167 { .start = 0x00a01c5c, .end = 0x00a01c5c },
6a65bd53 2168 { .start = 0x00a01c60, .end = 0x00a01cdc },
67c65f2c
EG		 2169 { .start = 0x00a01ce0, .end = 0x00a01d0c },
2170 { .start = 0x00a01d18, .end = 0x00a01d20 },
2171 { .start = 0x00a01d2c, .end = 0x00a01d30 },
2172 { .start = 0x00a01d40, .end = 0x00a01d5c },
2173 { .start = 0x00a01d80, .end = 0x00a01d80 },
6a65bd53
EG		 2174 { .start = 0x00a01d98, .end = 0x00a01d9c },
2175 { .start = 0x00a01da8, .end = 0x00a01da8 },
2176 { .start = 0x00a01db8, .end = 0x00a01df4 },
67c65f2c
EG		 2177 { .start = 0x00a01dc0, .end = 0x00a01dfc },
2178 { .start = 0x00a01e00, .end = 0x00a01e2c },
2179 { .start = 0x00a01e40, .end = 0x00a01e60 },
6a65bd53
EG		 2180 { .start = 0x00a01e68, .end = 0x00a01e6c },
2181 { .start = 0x00a01e74, .end = 0x00a01e74 },
67c65f2c
EG		 2182 { .start = 0x00a01e84, .end = 0x00a01e90 },
2183 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
6a65bd53
EG		 2184 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2185 { .start = 0x00a01f00, .end = 0x00a01f1c },
2186 { .start = 0x00a01f44, .end = 0x00a01ffc },
67c65f2c
EG		 2187 { .start = 0x00a02000, .end = 0x00a02048 },
2188 { .start = 0x00a02068, .end = 0x00a020f0 },
2189 { .start = 0x00a02100, .end = 0x00a02118 },
2190 { .start = 0x00a02140, .end = 0x00a0214c },
2191 { .start = 0x00a02168, .end = 0x00a0218c },
2192 { .start = 0x00a021c0, .end = 0x00a021c0 },
2193 { .start = 0x00a02400, .end = 0x00a02410 },
2194 { .start = 0x00a02418, .end = 0x00a02420 },
2195 { .start = 0x00a02428, .end = 0x00a0242c },
2196 { .start = 0x00a02434, .end = 0x00a02434 },
2197 { .start = 0x00a02440, .end = 0x00a02460 },
2198 { .start = 0x00a02468, .end = 0x00a024b0 },
2199 { .start = 0x00a024c8, .end = 0x00a024cc },
2200 { .start = 0x00a02500, .end = 0x00a02504 },
2201 { .start = 0x00a0250c, .end = 0x00a02510 },
2202 { .start = 0x00a02540, .end = 0x00a02554 },
2203 { .start = 0x00a02580, .end = 0x00a025f4 },
2204 { .start = 0x00a02600, .end = 0x00a0260c },
2205 { .start = 0x00a02648, .end = 0x00a02650 },
2206 { .start = 0x00a02680, .end = 0x00a02680 },
2207 { .start = 0x00a026c0, .end = 0x00a026d0 },
2208 { .start = 0x00a02700, .end = 0x00a0270c },
2209 { .start = 0x00a02804, .end = 0x00a02804 },
2210 { .start = 0x00a02818, .end = 0x00a0281c },
2211 { .start = 0x00a02c00, .end = 0x00a02db4 },
2212 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2213 { .start = 0x00a03000, .end = 0x00a03014 },
2214 { .start = 0x00a0301c, .end = 0x00a0302c },
2215 { .start = 0x00a03034, .end = 0x00a03038 },
2216 { .start = 0x00a03040, .end = 0x00a03048 },
2217 { .start = 0x00a03060, .end = 0x00a03068 },
2218 { .start = 0x00a03070, .end = 0x00a03074 },
2219 { .start = 0x00a0307c, .end = 0x00a0307c },
2220 { .start = 0x00a03080, .end = 0x00a03084 },
2221 { .start = 0x00a0308c, .end = 0x00a03090 },
2222 { .start = 0x00a03098, .end = 0x00a03098 },
2223 { .start = 0x00a030a0, .end = 0x00a030a0 },
2224 { .start = 0x00a030a8, .end = 0x00a030b4 },
2225 { .start = 0x00a030bc, .end = 0x00a030bc },
2226 { .start = 0x00a030c0, .end = 0x00a0312c },
2227 { .start = 0x00a03c00, .end = 0x00a03c5c },
2228 { .start = 0x00a04400, .end = 0x00a04454 },
2229 { .start = 0x00a04460, .end = 0x00a04474 },
2230 { .start = 0x00a044c0, .end = 0x00a044ec },
2231 { .start = 0x00a04500, .end = 0x00a04504 },
2232 { .start = 0x00a04510, .end = 0x00a04538 },
2233 { .start = 0x00a04540, .end = 0x00a04548 },
2234 { .start = 0x00a04560, .end = 0x00a0457c },
2235 { .start = 0x00a04590, .end = 0x00a04598 },
2236 { .start = 0x00a045c0, .end = 0x00a045f4 },
2237};
2238
2239static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2240 struct iwl_fw_error_dump_data **data)
2241{
2242 struct iwl_fw_error_dump_prph *prph;
2243 unsigned long flags;
2244 u32 prph_len = 0, i;
2245
2246 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2247 return 0;
2248
2249 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2250 /* The range includes both boundaries */
2251 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2252 iwl_prph_dump_addr[i].start + 4;
2253 int reg;
2254 __le32 *val;
2255
87dd634a 2256 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 2257
2258 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2259 (*data)->len = cpu_to_le32(sizeof(*prph) +
2260 num_bytes_in_chunk);
2261 prph = (void *)(*data)->data;
2262 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2263 val = (void *)prph->data;
2264
2265 for (reg = iwl_prph_dump_addr[i].start;
2266 reg <= iwl_prph_dump_addr[i].end;
2267 reg += 4)
2268 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2269 reg));
2270 *data = iwl_fw_error_next_data(*data);
2271 }
2272
2273 iwl_trans_release_nic_access(trans, &flags);
2274
2275 return prph_len;
2276}
2277
473ad712
EG		 2278#define IWL_CSR_TO_DUMP (0x250)
2279
2280static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2281 struct iwl_fw_error_dump_data **data)
2282{
2283 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2284 __le32 *val;
2285 int i;
2286
2287 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2288 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2289 val = (void *)(*data)->data;
2290
2291 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2292 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2293
2294 *data = iwl_fw_error_next_data(*data);
2295
2296 return csr_len;
2297}
2298
06d51e0d
LK		 2299static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2300 struct iwl_fw_error_dump_data **data)
2301{
2302 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2303 unsigned long flags;
2304 __le32 *val;
2305 int i;
2306
2307 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2308 return 0;
2309
2310 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2311 (*data)->len = cpu_to_le32(fh_regs_len);
2312 val = (void *)(*data)->data;
2313
2314 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2315 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2316
2317 iwl_trans_release_nic_access(trans, &flags);
2318
2319 *data = iwl_fw_error_next_data(*data);
2320
2321 return sizeof(**data) + fh_regs_len;
2322}
2323
cc79ef66
LK		 2324static u32
2325iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2326 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2327 u32 monitor_len)
2328{
2329 u32 buf_size_in_dwords = (monitor_len >> 2);
2330 u32 *buffer = (u32 *)fw_mon_data->data;
2331 unsigned long flags;
2332 u32 i;
2333
2334 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2335 return 0;
2336
2337 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2338 for (i = 0; i < buf_size_in_dwords; i++)
2339 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2340 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2341
2342 iwl_trans_release_nic_access(trans, &flags);
2343
2344 return monitor_len;
2345}
2346
48eb7b34
EG		 2347static
2348struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
4d075007
JB		 2349{
2350 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2351 struct iwl_fw_error_dump_data *data;
2352 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2353 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2354 struct iwl_trans_dump_data *dump_data;
4d075007 2355 u32 len;
99684ae3 2356 u32 monitor_len;
4d075007
JB		 2357 int i, ptr;
2358
473ad712
EG		 2359 /* transport dump header */
2360 len = sizeof(*dump_data);
2361
2362 /* host commands */
2363 len += sizeof(*data) +
c2d20201
EG		 2364 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2365
473ad712
EG		 2366 /* CSR registers */
2367 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2368
2369 /* PRPH registers */
67c65f2c
EG		 2370 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2371 /* The range includes both boundaries */
2372 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2373 iwl_prph_dump_addr[i].start + 4;
2374
2375 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2376 num_bytes_in_chunk;
2377 }
2378
06d51e0d
LK		 2379 /* FH registers */
2380 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2381
473ad712 2382 /* FW monitor */
99684ae3 2383 if (trans_pcie->fw_mon_page) {
c544e9c4 2384 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2385 trans_pcie->fw_mon_size;
2386 monitor_len = trans_pcie->fw_mon_size;
2387 } else if (trans->dbg_dest_tlv) {
2388 u32 base, end;
2389
2390 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2391 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2392
2393 base = iwl_read_prph(trans, base) <<
2394 trans->dbg_dest_tlv->base_shift;
2395 end = iwl_read_prph(trans, end) <<
2396 trans->dbg_dest_tlv->end_shift;
2397
2398 /* Make "end" point to the actual end */
cc79ef66
LK		 2399 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2400 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2401 end += (1 << trans->dbg_dest_tlv->end_shift);
2402 monitor_len = end - base;
2403 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2404 monitor_len;
2405 } else {
2406 monitor_len = 0;
2407 }
c2d20201 2408
48eb7b34
EG		 2409 dump_data = vzalloc(len);
2410 if (!dump_data)
2411 return NULL;
4d075007
JB		 2412
2413 len = 0;
48eb7b34 2414 data = (void *)dump_data->data;
4d075007
JB		 2415 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2416 txcmd = (void *)data->data;
2417 spin_lock_bh(&cmdq->lock);
2418 ptr = cmdq->q.write_ptr;
2419 for (i = 0; i < cmdq->q.n_window; i++) {
2420 u8 idx = get_cmd_index(&cmdq->q, ptr);
2421 u32 caplen, cmdlen;
2422
2423 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2424 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2425
2426 if (cmdlen) {
2427 len += sizeof(*txcmd) + caplen;
2428 txcmd->cmdlen = cpu_to_le32(cmdlen);
2429 txcmd->caplen = cpu_to_le32(caplen);
2430 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2431 txcmd = (void *)((u8 *)txcmd->data + caplen);
2432 }
2433
2434 ptr = iwl_queue_dec_wrap(ptr);
2435 }
2436 spin_unlock_bh(&cmdq->lock);
2437
2438 data->len = cpu_to_le32(len);
c2d20201 2439 len += sizeof(*data);
67c65f2c
EG		 2440 data = iwl_fw_error_next_data(data);
2441
2442 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2443 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2444 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
67c65f2c 2445 /* data is already pointing to the next section */
c2d20201 2446
99684ae3
LK		 2447 if ((trans_pcie->fw_mon_page &&
2448 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2449 trans->dbg_dest_tlv) {
c544e9c4 2450 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
99684ae3
LK		 2451 u32 base, write_ptr, wrap_cnt;
2452
2453 /* If there was a dest TLV - use the values from there */
2454 if (trans->dbg_dest_tlv) {
2455 write_ptr =
2456 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2457 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2458 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2459 } else {
2460 base = MON_BUFF_BASE_ADDR;
2461 write_ptr = MON_BUFF_WRPTR;
2462 wrap_cnt = MON_BUFF_CYCLE_CNT;
2463 }
c2d20201 2464
c2d20201 2465 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
c2d20201
EG		 2466 fw_mon_data = (void *)data->data;
2467 fw_mon_data->fw_mon_wr_ptr =
99684ae3 2468 cpu_to_le32(iwl_read_prph(trans, write_ptr));
c2d20201 2469 fw_mon_data->fw_mon_cycle_cnt =
99684ae3 2470 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
c2d20201 2471 fw_mon_data->fw_mon_base_ptr =
99684ae3
LK		 2472 cpu_to_le32(iwl_read_prph(trans, base));
2473
2474 len += sizeof(*data) + sizeof(*fw_mon_data);
2475 if (trans_pcie->fw_mon_page) {
99684ae3
LK		 2476 /*
2477 * The firmware is now asserted, it won't write anything
2478 * to the buffer. CPU can take ownership to fetch the
2479 * data. The buffer will be handed back to the device
2480 * before the firmware will be restarted.
2481 */
2482 dma_sync_single_for_cpu(trans->dev,
2483 trans_pcie->fw_mon_phys,
2484 trans_pcie->fw_mon_size,
2485 DMA_FROM_DEVICE);
2486 memcpy(fw_mon_data->data,
2487 page_address(trans_pcie->fw_mon_page),
2488 trans_pcie->fw_mon_size);
2489
cc79ef66
LK		 2490 monitor_len = trans_pcie->fw_mon_size;
2491 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
99684ae3
LK		 2492 /*
2493 * Update pointers to reflect actual values after
2494 * shifting
2495 */
2496 base = iwl_read_prph(trans, base) <<
2497 trans->dbg_dest_tlv->base_shift;
2498 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2499 monitor_len / sizeof(u32));
cc79ef66
LK		 2500 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2501 monitor_len =
2502 iwl_trans_pci_dump_marbh_monitor(trans,
2503 fw_mon_data,
2504 monitor_len);
2505 } else {
2506 /* Didn't match anything - output no monitor data */
2507 monitor_len = 0;
99684ae3 2508 }
cc79ef66
LK		 2509
2510 len += monitor_len;
2511 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
c2d20201
EG		 2512 }
2513
48eb7b34
EG		 2514 dump_data->len = len;
2515
2516 return dump_data;
4d075007 2517}
87e5666c 2518
d1ff5253 2519static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2520 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2521 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2522 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2523 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2524 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2525
ddaf5a5b
JB		 2526 .d3_suspend = iwl_trans_pcie_d3_suspend,
2527 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2528
f02831be 2529 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2530
e6bb4c9c 2531 .tx = iwl_trans_pcie_tx,
a0eaad71 2532 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2533
d0624be6 2534 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2535 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2536
87e5666c 2537 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2538
990aa6d7 2539 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2540 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
5f178cd2 2541
03905495
EG		 2542 .write8 = iwl_trans_pcie_write8,
2543 .write32 = iwl_trans_pcie_write32,
2544 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2545 .read_prph = iwl_trans_pcie_read_prph,
2546 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2547 .read_mem = iwl_trans_pcie_read_mem,
2548 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2549 .configure = iwl_trans_pcie_configure,
47107e84 2550 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2551 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2552 .release_nic_access = iwl_trans_pcie_release_nic_access,
2553 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2554
7616f334
EP		 2555 .ref = iwl_trans_pcie_ref,
2556 .unref = iwl_trans_pcie_unref,
2557
4d075007 2558 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2559};
a42a1844 2560
87ce05a2 2561struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2562 const struct pci_device_id *ent,
2563 const struct iwl_cfg *cfg)
a42a1844 2564{
a42a1844
EG		 2565 struct iwl_trans_pcie *trans_pcie;
2566 struct iwl_trans *trans;
2567 u16 pci_cmd;
2568 int err;
2569
7b501d10
JB		 2570 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2571 &pdev->dev, cfg, &trans_ops_pcie, 0);
2572 if (!trans)
2573 return ERR_PTR(-ENOMEM);
a42a1844
EG		 2574
2575 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2576
a42a1844 2577 trans_pcie->trans = trans;
7b11488f 2578 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2579 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2580 spin_lock_init(&trans_pcie->ref_lock);
fa9f3281 2581 mutex_init(&trans_pcie->mutex);
13df1aab 2582 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2583
d819c6cf
JB		 2584 err = pci_enable_device(pdev);
2585 if (err)
2586 goto out_no_pci;
2587
f2532b04
EG		 2588 if (!cfg->base_params->pcie_l1_allowed) {
2589 /*
2590 * W/A - seems to solve weird behavior. We need to remove this
2591 * if we don't want to stay in L1 all the time. This wastes a
2592 * lot of power.
2593 */
2594 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2595 PCIE_LINK_STATE_L1 |
2596 PCIE_LINK_STATE_CLKPM);
2597 }
a42a1844 2598
a42a1844
EG		 2599 pci_set_master(pdev);
2600
2601 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2602 if (!err)
2603 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2604 if (err) {
2605 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2606 if (!err)
2607 err = pci_set_consistent_dma_mask(pdev,
20d3b647 2608 DMA_BIT_MASK(32));
a42a1844
EG		 2609 /* both attempts failed: */
2610 if (err) {
6a4b09f8 2611 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2612 goto out_pci_disable_device;
2613 }
2614 }
2615
2616 err = pci_request_regions(pdev, DRV_NAME);
2617 if (err) {
6a4b09f8 2618 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2619 goto out_pci_disable_device;
2620 }
2621
05f5b97e 2622 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2623 if (!trans_pcie->hw_base) {
6a4b09f8 2624 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
a42a1844
EG		 2625 err = -ENODEV;
2626 goto out_pci_release_regions;
2627 }
2628
a42a1844
EG		 2629 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2630 * PCI Tx retries from interfering with C3 CPU state */
2631 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2632
83f7a85f
EG		 2633 trans->dev = &pdev->dev;
2634 trans_pcie->pci_dev = pdev;
2635 iwl_disable_interrupts(trans);
2636
a42a1844 2637 err = pci_enable_msi(pdev);
9f904b38 2638 if (err) {
6a4b09f8 2639 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
9f904b38
EG		 2640 /* enable rfkill interrupt: hw bug w/a */
2641 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2642 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2643 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2644 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2645 }
2646 }
a42a1844 2647
08079a49 2648 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2649 /*
2650 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2651 * changed, and now the revision step also includes bit 0-1 (no more
2652 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2653 * in the old format.
2654 */
7a42baa6
EH		 2655 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2656 unsigned long flags;
2657 int ret;
2658
b513ee7f 2659 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2660 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2661
7a42baa6
EH		 2662 /*
2663 * in-order to recognize C step driver should read chip version
2664 * id located at the AUX bus MISC address space.
2665 */
2666 iwl_set_bit(trans, CSR_GP_CNTRL,
2667 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2668 udelay(2);
2669
2670 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2671 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2672 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2673 25000);
2674 if (ret < 0) {
2675 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2676 goto out_pci_disable_msi;
2677 }
2678
2679 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2680 u32 hw_step;
2681
2682 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2683 hw_step |= ENABLE_WFPM;
2684 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2685 hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2686 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2687 if (hw_step == 0x3)
2688 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2689 (SILICON_C_STEP << 2);
2690 iwl_trans_release_nic_access(trans, &flags);
2691 }
2692 }
2693
99673ee5 2694 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2695 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2696 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2697
69a10b29 2698 /* Initialize the wait queue for commands */
f946b529 2699 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2700
a8b691e6 2701 if (iwl_pcie_alloc_ict(trans))
7b501d10 2702 goto out_pci_disable_msi;
a8b691e6 2703
85bf9da1 2704 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2705 iwl_pcie_irq_handler,
2706 IRQF_SHARED, DRV_NAME, trans);
2707 if (err) {
a8b691e6
JB		 2708 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2709 goto out_free_ict;
2710 }
2711
83f7a85f 2712 trans_pcie->inta_mask = CSR_INI_SET_MASK;
6735943f 2713 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
83f7a85f 2714
a42a1844
EG		 2715 return trans;
2716
a8b691e6
JB		 2717out_free_ict:
2718 iwl_pcie_free_ict(trans);
59c647b6
EG		 2719out_pci_disable_msi:
2720 pci_disable_msi(pdev);
a42a1844
EG		 2721out_pci_release_regions:
2722 pci_release_regions(pdev);
2723out_pci_disable_device:
2724 pci_disable_device(pdev);
2725out_no_pci:
7b501d10 2726 iwl_trans_free(trans);
6965a354 2727 return ERR_PTR(err);
a42a1844 2728}
Linux 6.x block layer and io_uring tree(s)