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iwlwifi: bump API to 14
[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
553452e5
LK		 34 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
cb6bb128 78#include "iwl-scd.h"
7a10e3e4 79#include "iwl-agn-hw.h"
4d075007 80#include "iwl-fw-error-dump.h"
6468a01a 81#include "internal.h"
06d51e0d 82#include "iwl-fh.h"
0439bb62 83
fe45773b
AN		 84/* extended range in FW SRAM */
85#define IWL_FW_MEM_EXTENDED_START 0x40000
86#define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
c2d20201
EG		 88static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89{
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102}
103
96c285da 104static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 105{
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 107 struct page *page = NULL;
c2d20201 108 dma_addr_t phys;
96c285da 109 u32 size = 0;
c2d20201
EG		 110 u8 power;
111
96c285da
EG		 112 if (!max_power) {
113 /* default max_power is maximum */
114 max_power = 26;
115 } else {
116 max_power += 11;
117 }
118
119 if (WARN(max_power > 26,
120 "External buffer size for monitor is too big %d, check the FW TLV\n",
121 max_power))
122 return;
123
c2d20201
EG		 124 if (trans_pcie->fw_mon_page) {
125 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
126 trans_pcie->fw_mon_size,
127 DMA_FROM_DEVICE);
128 return;
129 }
130
131 phys = 0;
96c285da 132 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 133 int order;
134
135 size = BIT(power);
136 order = get_order(size);
137 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
138 order);
139 if (!page)
140 continue;
141
142 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
143 DMA_FROM_DEVICE);
144 if (dma_mapping_error(trans->dev, phys)) {
145 __free_pages(page, order);
553452e5 146 page = NULL;
c2d20201
EG		 147 continue;
148 }
149 IWL_INFO(trans,
150 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
151 size, order);
152 break;
153 }
154
40a76905 155 if (WARN_ON_ONCE(!page))
c2d20201
EG		 156 return;
157
96c285da
EG		 158 if (power != max_power)
159 IWL_ERR(trans,
160 "Sorry - debug buffer is only %luK while you requested %luK\n",
161 (unsigned long)BIT(power - 10),
162 (unsigned long)BIT(max_power - 10));
163
c2d20201
EG		 164 trans_pcie->fw_mon_page = page;
165 trans_pcie->fw_mon_phys = phys;
166 trans_pcie->fw_mon_size = size;
167}
168
a812cba9
AB		 169static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
170{
171 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
172 ((reg & 0x0000ffff) | (2 << 28)));
173 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
174}
175
176static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
177{
178 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
179 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
180 ((reg & 0x0000ffff) | (3 << 28)));
181}
182
ddaf5a5b 183static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 184{
ddaf5a5b
JB		 185 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
186 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
187 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
188 ~APMG_PS_CTRL_MSK_PWR_SRC);
189 else
190 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 193}
194
af634bee
EG		 195/* PCI registers */
196#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 197
7afe3705 198static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 199{
20d3b647 200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 201 u16 lctl;
9180ac50 202 u16 cap;
af634bee 203
af634bee
EG		 204 /*
205 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
206 * Check if BIOS (or OS) enabled L1-ASPM on this device.
207 * If so (likely), disable L0S, so device moves directly L0->L1;
208 * costs negligible amount of power savings.
209 * If not (unlikely), enable L0S, so there is at least some
210 * power savings, even without L1.
211 */
7afe3705 212 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 213 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 214 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 215 else
af634bee 216 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 217 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 218
219 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
220 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
221 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
222 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
223 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 224}
225
a6c684ee
EG		 226/*
227 * Start up NIC's basic functionality after it has been reset
7afe3705 228 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 229 * NOTE: This does not load uCode nor start the embedded processor
230 */
7afe3705 231static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 232{
233 int ret = 0;
234 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
235
236 /*
237 * Use "set_bit" below rather than "write", to preserve any hardware
238 * bits already set by default after reset.
239 */
240
241 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 242 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
243 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
244 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 245
246 /*
247 * Disable L0s without affecting L1;
248 * don't wait for ICH L0s (ICH bug W/A)
249 */
250 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 251 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 252
253 /* Set FH wait threshold to maximum (HW error during stress W/A) */
254 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
255
256 /*
257 * Enable HAP INTA (interrupt from management bus) to
258 * wake device's PCI Express link L1a -> L0s
259 */
260 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 261 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 262
7afe3705 263 iwl_pcie_apm_config(trans);
a6c684ee
EG		 264
265 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 266 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 267 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 268 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 269
270 /*
271 * Set "initialization complete" bit to move adapter from
272 * D0U* --> D0A* (powered-up active) state.
273 */
274 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
275
276 /*
277 * Wait for clock stabilization; once stabilized, access to
278 * device-internal resources is supported, e.g. iwl_write_prph()
279 * and accesses to uCode SRAM.
280 */
281 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 282 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
283 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 284 if (ret < 0) {
285 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
286 goto out;
287 }
288
2d93aee1
EG		 289 if (trans->cfg->host_interrupt_operation_mode) {
290 /*
291 * This is a bit of an abuse - This is needed for 7260 / 3160
292 * only check host_interrupt_operation_mode even if this is
293 * not related to host_interrupt_operation_mode.
294 *
295 * Enable the oscillator to count wake up time for L1 exit. This
296 * consumes slightly more power (100uA) - but allows to be sure
297 * that we wake up from L1 on time.
298 *
299 * This looks weird: read twice the same register, discard the
300 * value, set a bit, and yet again, read that same register
301 * just to discard the value. But that's the way the hardware
302 * seems to like it.
303 */
304 iwl_read_prph(trans, OSC_CLK);
305 iwl_read_prph(trans, OSC_CLK);
306 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
307 iwl_read_prph(trans, OSC_CLK);
308 iwl_read_prph(trans, OSC_CLK);
309 }
310
a6c684ee
EG		 311 /*
312 * Enable DMA clock and wait for it to stabilize.
313 *
3073d8c0
EH		 314 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
315 * bits do not disable clocks. This preserves any hardware
316 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 317 */
3073d8c0
EH		 318 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
319 iwl_write_prph(trans, APMG_CLK_EN_REG,
320 APMG_CLK_VAL_DMA_CLK_RQT);
321 udelay(20);
322
323 /* Disable L1-Active */
324 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
325 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
326
327 /* Clear the interrupt in APMG if the NIC is in RFKILL */
328 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
329 APMG_RTC_INT_STT_RFKILL);
330 }
889b1696 331
eb7ff77e 332 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 333
334out:
335 return ret;
336}
337
a812cba9
AB		 338/*
339 * Enable LP XTAL to avoid HW bug where device may consume much power if
340 * FW is not loaded after device reset. LP XTAL is disabled by default
341 * after device HW reset. Do it only if XTAL is fed by internal source.
342 * Configure device's "persistence" mode to avoid resetting XTAL again when
343 * SHRD_HW_RST occurs in S3.
344 */
345static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
346{
347 int ret;
348 u32 apmg_gp1_reg;
349 u32 apmg_xtal_cfg_reg;
350 u32 dl_cfg_reg;
351
352 /* Force XTAL ON */
353 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
354 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
355
356 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
357 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
358
359 udelay(10);
360
361 /*
362 * Set "initialization complete" bit to move adapter from
363 * D0U* --> D0A* (powered-up active) state.
364 */
365 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
366
367 /*
368 * Wait for clock stabilization; once stabilized, access to
369 * device-internal resources is possible.
370 */
371 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
372 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
373 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
374 25000);
375 if (WARN_ON(ret < 0)) {
376 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
377 /* Release XTAL ON request */
378 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
379 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
380 return;
381 }
382
383 /*
384 * Clear "disable persistence" to avoid LP XTAL resetting when
385 * SHRD_HW_RST is applied in S3.
386 */
387 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
388 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
389
390 /*
391 * Force APMG XTAL to be active to prevent its disabling by HW
392 * caused by APMG idle state.
393 */
394 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
395 SHR_APMG_XTAL_CFG_REG);
396 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
397 apmg_xtal_cfg_reg |
398 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
399
400 /*
401 * Reset entire device again - do controller reset (results in
402 * SHRD_HW_RST). Turn MAC off before proceeding.
403 */
404 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
405
406 udelay(10);
407
408 /* Enable LP XTAL by indirect access through CSR */
409 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
410 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
411 SHR_APMG_GP1_WF_XTAL_LP_EN |
412 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
413
414 /* Clear delay line clock power up */
415 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
416 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
417 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
418
419 /*
420 * Enable persistence mode to avoid LP XTAL resetting when
421 * SHRD_HW_RST is applied in S3.
422 */
423 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
424 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
425
426 /*
427 * Clear "initialization complete" bit to move adapter from
428 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
429 */
430 iwl_clear_bit(trans, CSR_GP_CNTRL,
431 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
432
433 /* Activates XTAL resources monitor */
434 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
435 CSR_MONITOR_XTAL_RESOURCES);
436
437 /* Release XTAL ON request */
438 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
439 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
440 udelay(10);
441
442 /* Release APMG XTAL */
443 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
444 apmg_xtal_cfg_reg &
445 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
446}
447
7afe3705 448static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 449{
450 int ret = 0;
451
452 /* stop device's busmaster DMA activity */
453 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
454
455 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 456 CSR_RESET_REG_FLAG_MASTER_DISABLED,
457 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 458 if (ret < 0)
cc56feb2
EG		 459 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
460
461 IWL_DEBUG_INFO(trans, "stop master\n");
462
463 return ret;
464}
465
b7aaeae4 466static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 467{
468 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
469
b7aaeae4
EG		 470 if (op_mode_leave) {
471 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
472 iwl_pcie_apm_init(trans);
473
474 /* inform ME that we are leaving */
475 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
476 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
477 APMG_PCIDEV_STT_VAL_WAKE_ME);
478 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
479 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
480 CSR_HW_IF_CONFIG_REG_PREPARE |
481 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
482 mdelay(5);
483 }
484
eb7ff77e 485 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 486
487 /* Stop device's DMA activity */
7afe3705 488 iwl_pcie_apm_stop_master(trans);
cc56feb2 489
a812cba9
AB		 490 if (trans->cfg->lp_xtal_workaround) {
491 iwl_pcie_apm_lp_xtal_enable(trans);
492 return;
493 }
494
cc56feb2
EG		 495 /* Reset the entire device */
496 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
497
498 udelay(10);
499
500 /*
501 * Clear "initialization complete" bit to move adapter from
502 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
503 */
504 iwl_clear_bit(trans, CSR_GP_CNTRL,
505 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
506}
507
7afe3705 508static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 509{
7b11488f 510 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 511
512 /* nic_init */
7b70bd63 513 spin_lock(&trans_pcie->irq_lock);
7afe3705 514 iwl_pcie_apm_init(trans);
392f8b78 515
7b70bd63 516 spin_unlock(&trans_pcie->irq_lock);
392f8b78 517
3073d8c0
EH		 518 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
519 iwl_pcie_set_pwr(trans, false);
392f8b78 520
ecdb975c 521 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 522
523 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 524 iwl_pcie_rx_init(trans);
392f8b78
EG		 525
526 /* Allocate or reset and init all Tx and Command queues */
f02831be 527 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 528 return -ENOMEM;
529
035f7ff2 530 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 531 /* enable shadow regs in HW */
20d3b647 532 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 533 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 534 }
535
392f8b78
EG		 536 return 0;
537}
538
539#define HW_READY_TIMEOUT (50)
540
541/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 542static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 543{
544 int ret;
545
1042db2a 546 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 547 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 548
549 /* See if we got it */
1042db2a 550 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 551 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
552 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
553 HW_READY_TIMEOUT);
392f8b78 554
6a08f514
EG		 555 if (ret >= 0)
556 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
557
6d8f6eeb 558 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 559 return ret;
560}
561
562/* Note: returns standard 0/-ERROR code */
7afe3705 563static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 564{
565 int ret;
289e5501 566 int t = 0;
501fd989 567 int iter;
392f8b78 568
6d8f6eeb 569 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 570
7afe3705 571 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 572 /* If the card is ready, exit 0 */
392f8b78
EG		 573 if (ret >= 0)
574 return 0;
575
501fd989
EG		 576 for (iter = 0; iter < 10; iter++) {
577 /* If HW is not ready, prepare the conditions to check again */
578 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
579 CSR_HW_IF_CONFIG_REG_PREPARE);
580
581 do {
582 ret = iwl_pcie_set_hw_ready(trans);
583 if (ret >= 0)
584 return 0;
392f8b78 585
501fd989
EG		 586 usleep_range(200, 1000);
587 t += 200;
588 } while (t < 150000);
589 msleep(25);
590 }
392f8b78 591
7f2ac8fb 592 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 593
392f8b78
EG		 594 return ret;
595}
596
cf614297
EG		 597/*
598 * ucode
599 */
7afe3705 600static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 601 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 602{
13df1aab 603 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 604 int ret;
605
13df1aab 606 trans_pcie->ucode_write_complete = false;
cf614297
EG		 607
608 iwl_write_direct32(trans,
20d3b647
JB		 609 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
610 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 611
612 iwl_write_direct32(trans,
20d3b647
JB		 613 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
614 dst_addr);
cf614297
EG		 615
616 iwl_write_direct32(trans,
83f84d7b
JB		 617 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
618 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 619
620 iwl_write_direct32(trans,
20d3b647
JB		 621 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
622 (iwl_get_dma_hi_addr(phy_addr)
623 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 624
625 iwl_write_direct32(trans,
20d3b647
JB		 626 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
627 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
628 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
629 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 630
631 iwl_write_direct32(trans,
20d3b647
JB		 632 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
633 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
635 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 636
13df1aab
JB		 637 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
638 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 639 if (!ret) {
83f84d7b 640 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 641 return -ETIMEDOUT;
642 }
643
644 return 0;
645}
646
7afe3705 647static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 648 const struct fw_desc *section)
cf614297 649{
83f84d7b
JB		 650 u8 *v_addr;
651 dma_addr_t p_addr;
baa21e83 652 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 653 int ret = 0;
654
83f84d7b
JB		 655 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
656 section_num);
657
c571573a
EG		 658 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
659 GFP_KERNEL | __GFP_NOWARN);
660 if (!v_addr) {
661 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
662 chunk_sz = PAGE_SIZE;
663 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
664 &p_addr, GFP_KERNEL);
665 if (!v_addr)
666 return -ENOMEM;
667 }
83f84d7b 668
c571573a 669 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 670 u32 copy_size, dst_addr;
671 bool extended_addr = false;
83f84d7b 672
c571573a 673 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 674 dst_addr = section->offset + offset;
675
676 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
677 dst_addr <= IWL_FW_MEM_EXTENDED_END)
678 extended_addr = true;
679
680 if (extended_addr)
681 iwl_set_bits_prph(trans, LMPM_CHICK,
682 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 683
83f84d7b 684 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 685 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
686 copy_size);
687
688 if (extended_addr)
689 iwl_clear_bits_prph(trans, LMPM_CHICK,
690 LMPM_CHICK_EXTENDED_ADDR_SPACE);
691
83f84d7b
JB		 692 if (ret) {
693 IWL_ERR(trans,
694 "Could not load the [%d] uCode section\n",
695 section_num);
696 break;
6dfa8d01 697 }
83f84d7b
JB		 698 }
699
c571573a 700 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 701 return ret;
702}
703
16bc119b
EH		 704/*
705 * Driver Takes the ownership on secure machine before FW load
706 * and prevent race with the BT load.
707 * W/A for ROM bug. (should be remove in the next Si step)
708 */
709static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
710{
711 u32 val, loop = 1000;
712
1e167071
EH		 713 /*
714 * Check the RSA semaphore is accessible.
715 * If the HW isn't locked and the rsa semaphore isn't accessible,
716 * we are in trouble.
717 */
16bc119b
EH		 718 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
719 if (val & (BIT(1) | BIT(17))) {
1e167071
EH		 720 IWL_INFO(trans,
721 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 722 return 0;
723 }
724
725 /* take ownership on the AUX IF */
726 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
727 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
728
729 do {
730 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
731 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
732 if (val == 0x1) {
733 iwl_write_prph(trans, RSA_ENABLE, 0);
734 return 0;
735 }
736
737 udelay(10);
738 loop--;
739 } while (loop > 0);
740
741 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
742 return -EIO;
743}
744
5dd9c68a
EG		 745static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
746 const struct fw_img *image,
747 int cpu,
748 int *first_ucode_section)
e2d6f4e7
EH		 749{
750 int shift_param;
dcab8ecd
EH		 751 int i, ret = 0, sec_num = 0x1;
752 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 753
754 if (cpu == 1) {
755 shift_param = 0;
034846cf 756 *first_ucode_section = 0;
e2d6f4e7
EH		 757 } else {
758 shift_param = 16;
034846cf 759 (*first_ucode_section)++;
e2d6f4e7
EH		 760 }
761
034846cf
EH		 762 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
763 last_read_idx = i;
764
765 if (!image->sec[i].data ||
766 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
767 IWL_DEBUG_FW(trans,
768 "Break since Data not valid or Empty section, sec = %d\n",
769 i);
189fa2fa 770 break;
034846cf
EH		 771 }
772
189fa2fa
EH		 773 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
774 if (ret)
775 return ret;
dcab8ecd
EH		 776
777 /* Notify the ucode of the loaded section number and status */
778 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
779 val = val | (sec_num << shift_param);
780 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
781 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 782 }
783
034846cf
EH		 784 *first_ucode_section = last_read_idx;
785
afb88917
EH		 786 if (cpu == 1)
787 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
788 else
789 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
790
189fa2fa
EH		 791 return 0;
792}
e2d6f4e7 793
189fa2fa
EH		 794static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
795 const struct fw_img *image,
034846cf
EH		 796 int cpu,
797 int *first_ucode_section)
189fa2fa
EH		 798{
799 int shift_param;
189fa2fa 800 int i, ret = 0;
034846cf 801 u32 last_read_idx = 0;
189fa2fa
EH		 802
803 if (cpu == 1) {
804 shift_param = 0;
034846cf 805 *first_ucode_section = 0;
189fa2fa
EH		 806 } else {
807 shift_param = 16;
034846cf 808 (*first_ucode_section)++;
189fa2fa
EH		 809 }
810
034846cf
EH		 811 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
812 last_read_idx = i;
813
814 if (!image->sec[i].data ||
815 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
816 IWL_DEBUG_FW(trans,
817 "Break since Data not valid or Empty section, sec = %d\n",
818 i);
189fa2fa 819 break;
034846cf
EH		 820 }
821
189fa2fa
EH		 822 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
823 if (ret)
824 return ret;
e2d6f4e7
EH		 825 }
826
189fa2fa
EH		 827 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
828 iwl_set_bits_prph(trans,
829 CSR_UCODE_LOAD_STATUS_ADDR,
830 (LMPM_CPU_UCODE_LOADING_COMPLETED |
831 LMPM_CPU_HDRS_LOADING_COMPLETED |
832 LMPM_CPU_UCODE_LOADING_STARTED) <<
833 shift_param);
834
034846cf
EH		 835 *first_ucode_section = last_read_idx;
836
e2d6f4e7
EH		 837 return 0;
838}
839
09e350f7
LK		 840static void iwl_pcie_apply_destination(struct iwl_trans *trans)
841{
842 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
843 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
844 int i;
845
846 if (dest->version)
847 IWL_ERR(trans,
848 "DBG DEST version is %d - expect issues\n",
849 dest->version);
850
851 IWL_INFO(trans, "Applying debug destination %s\n",
852 get_fw_dbg_mode_string(dest->monitor_mode));
853
854 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 855 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 856 else
857 IWL_WARN(trans, "PCI should have external buffer debug\n");
858
859 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
860 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
861 u32 val = le32_to_cpu(dest->reg_ops[i].val);
862
863 switch (dest->reg_ops[i].op) {
864 case CSR_ASSIGN:
865 iwl_write32(trans, addr, val);
866 break;
867 case CSR_SETBIT:
868 iwl_set_bit(trans, addr, BIT(val));
869 break;
870 case CSR_CLEARBIT:
871 iwl_clear_bit(trans, addr, BIT(val));
872 break;
873 case PRPH_ASSIGN:
874 iwl_write_prph(trans, addr, val);
875 break;
876 case PRPH_SETBIT:
877 iwl_set_bits_prph(trans, addr, BIT(val));
878 break;
879 case PRPH_CLEARBIT:
880 iwl_clear_bits_prph(trans, addr, BIT(val));
881 break;
882 default:
883 IWL_ERR(trans, "FW debug - unknown OP %d\n",
884 dest->reg_ops[i].op);
885 break;
886 }
887 }
888
889 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
890 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
891 trans_pcie->fw_mon_phys >> dest->base_shift);
892 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
893 (trans_pcie->fw_mon_phys +
894 trans_pcie->fw_mon_size) >> dest->end_shift);
895 }
896}
897
7afe3705 898static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 899 const struct fw_img *image)
cf614297 900{
c2d20201 901 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 902 int ret = 0;
034846cf 903 int first_ucode_section;
cf614297 904
dcab8ecd 905 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 906 image->is_dual_cpus ? "Dual" : "Single");
907
dcab8ecd
EH		 908 /* load to FW the binary non secured sections of CPU1 */
909 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
910 if (ret)
911 return ret;
e2d6f4e7
EH		 912
913 if (image->is_dual_cpus) {
189fa2fa
EH		 914 /* set CPU2 header address */
915 iwl_write_prph(trans,
916 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
917 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 918
189fa2fa 919 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 920 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
921 &first_ucode_section);
189fa2fa
EH		 922 if (ret)
923 return ret;
e2d6f4e7 924 }
cf614297 925
c2d20201
EG		 926 /* supported for 7000 only for the moment */
927 if (iwlwifi_mod_params.fw_monitor &&
928 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 929 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 930
931 if (trans_pcie->fw_mon_size) {
932 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
933 trans_pcie->fw_mon_phys >> 4);
934 iwl_write_prph(trans, MON_BUFF_END_ADDR,
935 (trans_pcie->fw_mon_phys +
936 trans_pcie->fw_mon_size) >> 4);
937 }
09e350f7
LK		 938 } else if (trans->dbg_dest_tlv) {
939 iwl_pcie_apply_destination(trans);
c2d20201
EG		 940 }
941
e12ba844 942 /* release CPU reset */
5dd9c68a 943 iwl_write32(trans, CSR_RESET, 0);
e12ba844 944
dcab8ecd
EH		 945 return 0;
946}
189fa2fa 947
5dd9c68a
EG		 948static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
949 const struct fw_img *image)
dcab8ecd
EH		 950{
951 int ret = 0;
952 int first_ucode_section;
dcab8ecd
EH		 953
954 IWL_DEBUG_FW(trans, "working with %s CPU\n",
955 image->is_dual_cpus ? "Dual" : "Single");
956
a2227ce2
EG		 957 if (trans->dbg_dest_tlv)
958 iwl_pcie_apply_destination(trans);
959
16bc119b
EH		 960 /* TODO: remove in the next Si step */
961 ret = iwl_pcie_rsa_race_bug_wa(trans);
962 if (ret)
963 return ret;
964
dcab8ecd
EH		 965 /* configure the ucode to be ready to get the secured image */
966 /* release CPU reset */
967 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
968
969 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 970 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
971 &first_ucode_section);
dcab8ecd
EH		 972 if (ret)
973 return ret;
974
975 /* load to FW the binary sections of CPU2 */
5dd9c68a
EG		 976 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 2,
977 &first_ucode_section);
dcab8ecd
EH		 978 if (ret)
979 return ret;
980
cf614297
EG		 981 return 0;
982}
983
0692fe41 984static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 985 const struct fw_img *fw, bool run_in_rfkill)
392f8b78
EG		 986{
987 int ret;
c9eec95c 988 bool hw_rfkill;
392f8b78 989
496bab39 990 /* This may fail if AMT took ownership of the device */
7afe3705 991 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 992 IWL_WARN(trans, "Exit HW not ready\n");
392f8b78
EG		 993 return -EIO;
994 }
995
8c46bb70
EG		 996 iwl_enable_rfkill_int(trans);
997
392f8b78 998 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 999 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1000 if (hw_rfkill)
eb7ff77e 1001 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1002 else
eb7ff77e 1003 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1004 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
6ae02f3e 1005 if (hw_rfkill && !run_in_rfkill)
392f8b78 1006 return -ERFKILL;
392f8b78 1007
1042db2a 1008 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 1009
7afe3705 1010 ret = iwl_pcie_nic_init(trans);
392f8b78 1011 if (ret) {
6d8f6eeb 1012 IWL_ERR(trans, "Unable to init nic\n");
392f8b78
EG		 1013 return ret;
1014 }
1015
1016 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 1017 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1018 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 1019 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1020
1021 /* clear (again), then enable host interrupts */
1042db2a 1022 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 1023 iwl_enable_interrupts(trans);
392f8b78
EG		 1024
1025 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 1026 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1027 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 1028
cf614297 1029 /* Load the given image to the HW */
5dd9c68a
EG		 1030 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1031 return iwl_pcie_load_given_ucode_8000(trans, fw);
dcab8ecd
EH		 1032 else
1033 return iwl_pcie_load_given_ucode(trans, fw);
b3c2ce13
EG		 1034}
1035
adca1235 1036static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 1037{
990aa6d7 1038 iwl_pcie_reset_ict(trans);
f02831be 1039 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 1040}
1041
8d193ca2 1042static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1043{
43e58856 1044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1045 bool hw_rfkill, was_hw_rfkill;
1046
1047 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1048
43e58856 1049 /* tell the device to stop sending interrupts */
7b70bd63 1050 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1051 iwl_disable_interrupts(trans);
7b70bd63 1052 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1053
ab6cf8e8 1054 /* device going down, Stop using ICT table */
990aa6d7 1055 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1056
1057 /*
1058 * If a HW restart happens during firmware loading,
1059 * then the firmware loading might call this function
1060 * and later it might be called again due to the
1061 * restart. So don't process again if the device is
1062 * already dead.
1063 */
31b8b343
EG		 1064 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1065 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1066 iwl_pcie_tx_stop(trans);
9805c446 1067 iwl_pcie_rx_stop(trans);
6379103e 1068
ab6cf8e8 1069 /* Power-down device's busmaster DMA clocks */
1aa02b5a
AA		 1070 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
1071 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1072 APMG_CLK_VAL_DMA_CLK_RQT);
1073 udelay(5);
1074 }
ab6cf8e8
EG		 1075 }
1076
1077 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1078 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1079 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1080
1081 /* Stop the device, and put it in low power state */
b7aaeae4 1082 iwl_pcie_apm_stop(trans, false);
43e58856 1083
03d6c3b0
EG		 1084 /* stop and reset the on-board processor */
1085 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1086 udelay(20);
1087
1088 /*
1089 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1090 * This is a bug in certain verions of the hardware.
1091 * Certain devices also keep sending HW RF kill interrupt all
1092 * the time, unless the interrupt is ACKed even if the interrupt
1093 * should be masked. Re-ACK all the interrupts here.
43e58856 1094 */
7b70bd63 1095 spin_lock(&trans_pcie->irq_lock);
43e58856 1096 iwl_disable_interrupts(trans);
7b70bd63 1097 spin_unlock(&trans_pcie->irq_lock);
43e58856 1098
74fda971
DF		 1099
1100 /* clear all status bits */
eb7ff77e
AN		 1101 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1102 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1103 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1104 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1105
1106 /*
1107 * Even if we stop the HW, we still want the RF kill
1108 * interrupt
1109 */
1110 iwl_enable_rfkill_int(trans);
1111
1112 /*
1113 * Check again since the RF kill state may have changed while
1114 * all the interrupts were disabled, in this case we couldn't
1115 * receive the RF kill interrupt and update the state in the
1116 * op_mode.
3dc3374f
EG		 1117 * Don't call the op_mode if the rkfill state hasn't changed.
1118 * This allows the op_mode to call stop_device from the rfkill
1119 * notification without endless recursion. Under very rare
1120 * circumstances, we might have a small recursion if the rfkill
1121 * state changed exactly now while we were called from stop_device.
1122 * This is very unlikely but can happen and is supported.
a4082843
AN		 1123 */
1124 hw_rfkill = iwl_is_rfkill_set(trans);
1125 if (hw_rfkill)
eb7ff77e 1126 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1127 else
eb7ff77e 1128 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1129 if (hw_rfkill != was_hw_rfkill)
14cfca71 1130 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1131
1132 /* re-take ownership to prevent other users from stealing the deivce */
1133 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1134}
1135
1136void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1137{
1138 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
8d193ca2 1139 iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1140}
1141
debff618 1142static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1143{
2dd4f9f7 1144 iwl_disable_interrupts(trans);
debff618
JB		 1145
1146 /*
1147 * in testing mode, the host stays awake and the
1148 * hardware won't be reset (not even partially)
1149 */
1150 if (test)
1151 return;
1152
ddaf5a5b
JB		 1153 iwl_pcie_disable_ict(trans);
1154
2dd4f9f7
JB		 1155 iwl_clear_bit(trans, CSR_GP_CNTRL,
1156 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1157 iwl_clear_bit(trans, CSR_GP_CNTRL,
1158 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1159
1160 /*
1161 * reset TX queues -- some of their registers reset during S3
1162 * so if we don't reset everything here the D3 image would try
1163 * to execute some invalid memory upon resume
1164 */
1165 iwl_trans_pcie_tx_reset(trans);
1166
a61408e9
LC		 1167 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
1168 iwl_pcie_set_pwr(trans, true);
ddaf5a5b
JB		 1169}
1170
1171static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1172 enum iwl_d3_status *status,
1173 bool test)
ddaf5a5b
JB		 1174{
1175 u32 val;
1176 int ret;
1177
debff618
JB		 1178 if (test) {
1179 iwl_enable_interrupts(trans);
1180 *status = IWL_D3_STATUS_ALIVE;
1181 return 0;
1182 }
1183
ddaf5a5b
JB		 1184 /*
1185 * Also enables interrupts - none will happen as the device doesn't
1186 * know we're waking it up, only when the opmode actually tells it
1187 * after this call.
1188 */
1189 iwl_pcie_reset_ict(trans);
1190
1191 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1192 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1193
01e58a28
EG		 1194 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1195 udelay(2);
1196
ddaf5a5b
JB		 1197 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1198 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1199 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1200 25000);
7f2ac8fb 1201 if (ret < 0) {
ddaf5a5b
JB		 1202 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1203 return ret;
1204 }
1205
a61408e9
LC		 1206 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
1207 iwl_pcie_set_pwr(trans, false);
a3ead656 1208
ddaf5a5b
JB		 1209 iwl_trans_pcie_tx_reset(trans);
1210
1211 ret = iwl_pcie_rx_init(trans);
1212 if (ret) {
1213 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1214 return ret;
1215 }
1216
a3ead656
EG		 1217 val = iwl_read32(trans, CSR_RESET);
1218 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1219 *status = IWL_D3_STATUS_RESET;
1220 else
1221 *status = IWL_D3_STATUS_ALIVE;
1222
ddaf5a5b 1223 return 0;
2dd4f9f7
JB		 1224}
1225
8d193ca2 1226static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1227{
c9eec95c 1228 bool hw_rfkill;
a8b691e6 1229 int err;
e6bb4c9c 1230
7afe3705 1231 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1232 if (err) {
d6f1c316 1233 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1234 return err;
ebb7678d 1235 }
a6c684ee 1236
2997494f 1237 /* Reset the entire device */
ce836c76 1238 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1239
1240 usleep_range(10, 15);
1241
7afe3705 1242 iwl_pcie_apm_init(trans);
a6c684ee 1243
226c02ca
EG		 1244 /* From now on, the op_mode will be kept updated about RF kill state */
1245 iwl_enable_rfkill_int(trans);
1246
8d425517 1247 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1248 if (hw_rfkill)
eb7ff77e 1249 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1250 else
eb7ff77e 1251 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1252 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1253
a8b691e6 1254 return 0;
e6bb4c9c
EG		 1255}
1256
a4082843 1257static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1258{
20d3b647 1259 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1260
a4082843 1261 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1262 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1263 iwl_disable_interrupts(trans);
7b70bd63 1264 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1265
b7aaeae4 1266 iwl_pcie_apm_stop(trans, true);
cc56feb2 1267
7b70bd63 1268 spin_lock(&trans_pcie->irq_lock);
218733cf 1269 iwl_disable_interrupts(trans);
7b70bd63 1270 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1271
8d96bb61 1272 iwl_pcie_disable_ict(trans);
cc56feb2
EG		 1273}
1274
03905495
EG		 1275static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1276{
05f5b97e 1277 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1278}
1279
1280static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1281{
05f5b97e 1282 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1283}
1284
1285static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1286{
05f5b97e 1287 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1288}
1289
6a06b6c1
EG		 1290static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1291{
f9477c17
AP		 1292 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1293 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1294 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1295}
1296
1297static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1298 u32 val)
1299{
1300 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1301 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1302 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1303}
1304
f14d6b39
JB		 1305static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1306{
1307 WARN_ON(1);
1308 return 0;
1309}
1310
c6f600fc 1311static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1312 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1313{
1314 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1315
1316 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1317 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1318 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1319 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1320 trans_pcie->n_no_reclaim_cmds = 0;
1321 else
1322 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1323 if (trans_pcie->n_no_reclaim_cmds)
1324 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1325 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1326
b2cf410c
JB		 1327 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1328 if (trans_pcie->rx_buf_size_8k)
1329 trans_pcie->rx_page_order = get_order(8 * 1024);
1330 else
1331 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8 1332
d9fb6465 1333 trans_pcie->command_names = trans_cfg->command_names;
046db346 1334 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1335 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39 1336
483f3ab1
EP		 1337 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1338 trans_pcie->ref_count = 1;
1339
f14d6b39
JB		 1340 /* Initialize NAPI here - it should be before registering to mac80211
1341 * in the opmode but after the HW struct is allocated.
1342 * As this function may be called again in some corner cases don't
1343 * do anything if NAPI was already initialized.
1344 */
1345 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1346 init_dummy_netdev(&trans_pcie->napi_dev);
1347 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1348 &trans_pcie->napi_dev,
1349 iwl_pcie_dummy_napi_poll, 64);
1350 }
c6f600fc
MV		 1351}
1352
d1ff5253 1353void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1354{
20d3b647 1355 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1356
0aa86df6 1357 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1358
f02831be 1359 iwl_pcie_tx_free(trans);
9805c446 1360 iwl_pcie_rx_free(trans);
6379103e 1361
a8b691e6
JB		 1362 free_irq(trans_pcie->pci_dev->irq, trans);
1363 iwl_pcie_free_ict(trans);
a42a1844
EG		 1364
1365 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1366 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1367 pci_release_regions(trans_pcie->pci_dev);
1368 pci_disable_device(trans_pcie->pci_dev);
1369
f14d6b39
JB		 1370 if (trans_pcie->napi.poll)
1371 netif_napi_del(&trans_pcie->napi);
1372
c2d20201
EG		 1373 iwl_pcie_free_fw_monitor(trans);
1374
7b501d10 1375 iwl_trans_free(trans);
34c1b7ba
EG		 1376}
1377
47107e84
DF		 1378static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1379{
47107e84 1380 if (state)
eb7ff77e 1381 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1382 else
eb7ff77e 1383 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1384}
1385
e56b04ef
LE		 1386static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1387 unsigned long *flags)
7a65d170
EG		 1388{
1389 int ret;
cfb4e624
JB		 1390 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1391
1392 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1393
b9439491
EG		 1394 if (trans_pcie->cmd_in_flight)
1395 goto out;
1396
7a65d170 1397 /* this bit wakes up the NIC */
e139dc4a
LE		 1398 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1399 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1400 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1401 udelay(2);
7a65d170
EG		 1402
1403 /*
1404 * These bits say the device is running, and should keep running for
1405 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1406 * but they do not indicate that embedded SRAM is restored yet;
1407 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1408 * to/from host DRAM when sleeping/waking for power-saving.
1409 * Each direction takes approximately 1/4 millisecond; with this
1410 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1411 * series of register accesses are expected (e.g. reading Event Log),
1412 * to keep device from sleeping.
1413 *
1414 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1415 * SRAM is okay/restored. We don't check that here because this call
1416 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1417 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1418 *
1419 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1420 * and do not save/restore SRAM when power cycling.
1421 */
1422 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1423 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1424 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1425 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1426 if (unlikely(ret < 0)) {
1427 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1428 if (!silent) {
1429 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1430 WARN_ONCE(1,
1431 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1432 val);
cfb4e624 1433 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1434 return false;
1435 }
1436 }
1437
b9439491 1438out:
e56b04ef
LE		 1439 /*
1440 * Fool sparse by faking we release the lock - sparse will
1441 * track nic_access anyway.
1442 */
cfb4e624 1443 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1444 return true;
1445}
1446
e56b04ef
LE		 1447static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1448 unsigned long *flags)
7a65d170 1449{
cfb4e624 1450 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1451
cfb4e624 1452 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1453
1454 /*
1455 * Fool sparse by faking we acquiring the lock - sparse will
1456 * track nic_access anyway.
1457 */
cfb4e624 1458 __acquire(&trans_pcie->reg_lock);
e56b04ef 1459
b9439491
EG		 1460 if (trans_pcie->cmd_in_flight)
1461 goto out;
1462
e139dc4a
LE		 1463 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1464 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1465 /*
1466 * Above we read the CSR_GP_CNTRL register, which will flush
1467 * any previous writes, but we need the write that clears the
1468 * MAC_ACCESS_REQ bit to be performed before any other writes
1469 * scheduled on different CPUs (after we drop reg_lock).
1470 */
1471 mmiowb();
b9439491 1472out:
cfb4e624 1473 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1474}
1475
4fd442db
EG		 1476static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1477 void *buf, int dwords)
1478{
1479 unsigned long flags;
1480 int offs, ret = 0;
1481 u32 *vals = buf;
1482
e56b04ef 1483 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1484 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1485 for (offs = 0; offs < dwords; offs++)
1486 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1487 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1488 } else {
1489 ret = -EBUSY;
1490 }
4fd442db
EG		 1491 return ret;
1492}
1493
1494static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1495 const void *buf, int dwords)
4fd442db
EG		 1496{
1497 unsigned long flags;
1498 int offs, ret = 0;
bf0fd5da 1499 const u32 *vals = buf;
4fd442db 1500
e56b04ef 1501 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1502 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1503 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1504 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1505 vals ? vals[offs] : 0);
e56b04ef 1506 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1507 } else {
1508 ret = -EBUSY;
1509 }
4fd442db
EG		 1510 return ret;
1511}
7a65d170 1512
e0b8d405
EG		 1513static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1514 unsigned long txqs,
1515 bool freeze)
1516{
1517 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1518 int queue;
1519
1520 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1521 struct iwl_txq *txq = &trans_pcie->txq[queue];
1522 unsigned long now;
1523
1524 spin_lock_bh(&txq->lock);
1525
1526 now = jiffies;
1527
1528 if (txq->frozen == freeze)
1529 goto next_queue;
1530
1531 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1532 freeze ? "Freezing" : "Waking", queue);
1533
1534 txq->frozen = freeze;
1535
1536 if (txq->q.read_ptr == txq->q.write_ptr)
1537 goto next_queue;
1538
1539 if (freeze) {
1540 if (unlikely(time_after(now,
1541 txq->stuck_timer.expires))) {
1542 /*
1543 * The timer should have fired, maybe it is
1544 * spinning right now on the lock.
1545 */
1546 goto next_queue;
1547 }
1548 /* remember how long until the timer fires */
1549 txq->frozen_expiry_remainder =
1550 txq->stuck_timer.expires - now;
1551 del_timer(&txq->stuck_timer);
1552 goto next_queue;
1553 }
1554
1555 /*
1556 * Wake a non-empty queue -> arm timer with the
1557 * remainder before it froze
1558 */
1559 mod_timer(&txq->stuck_timer,
1560 now + txq->frozen_expiry_remainder);
1561
1562next_queue:
1563 spin_unlock_bh(&txq->lock);
1564 }
1565}
1566
5f178cd2
EG		 1567#define IWL_FLUSH_WAIT_MS 2000
1568
3cafdbe6 1569static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1570{
8ad71bef 1571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1572 struct iwl_txq *txq;
5f178cd2
EG		 1573 struct iwl_queue *q;
1574 int cnt;
1575 unsigned long now = jiffies;
1c3fea82
EG		 1576 u32 scd_sram_addr;
1577 u8 buf[16];
5f178cd2
EG		 1578 int ret = 0;
1579
1580 /* waiting for all the tx frames complete might take a while */
035f7ff2 1581 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1582 u8 wr_ptr;
1583
9ba1947a 1584 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1585 continue;
3cafdbe6
EG		 1586 if (!test_bit(cnt, trans_pcie->queue_used))
1587 continue;
1588 if (!(BIT(cnt) & txq_bm))
1589 continue;
748fa67c
EG		 1590
1591 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1592 txq = &trans_pcie->txq[cnt];
5f178cd2 1593 q = &txq->q;
fa1a91fd
EG		 1594 wr_ptr = ACCESS_ONCE(q->write_ptr);
1595
1596 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1597 !time_after(jiffies,
1598 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1599 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1600
1601 if (WARN_ONCE(wr_ptr != write_ptr,
1602 "WR pointer moved while flushing %d -> %d\n",
1603 wr_ptr, write_ptr))
1604 return -ETIMEDOUT;
5f178cd2 1605 msleep(1);
fa1a91fd 1606 }
5f178cd2
EG		 1607
1608 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1609 IWL_ERR(trans,
1610 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1611 ret = -ETIMEDOUT;
1612 break;
1613 }
748fa67c 1614 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1615 }
1c3fea82
EG		 1616
1617 if (!ret)
1618 return 0;
1619
1620 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1621 txq->q.read_ptr, txq->q.write_ptr);
1622
1623 scd_sram_addr = trans_pcie->scd_base_addr +
1624 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1625 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1626
1627 iwl_print_hex_error(trans, buf, sizeof(buf));
1628
1629 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1630 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1631 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1632
1633 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1634 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1635 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1636 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1637 u32 tbl_dw =
1638 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1639 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1640
1641 if (cnt & 0x1)
1642 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1643 else
1644 tbl_dw = tbl_dw & 0x0000FFFF;
1645
1646 IWL_ERR(trans,
1647 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1648 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1649 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1650 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1651 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1652 }
1653
5f178cd2
EG		 1654 return ret;
1655}
1656
e139dc4a
LE		 1657static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1658 u32 mask, u32 value)
1659{
e56b04ef 1660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1661 unsigned long flags;
1662
e56b04ef 1663 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1664 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1665 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1666}
1667
7616f334
EP		 1668void iwl_trans_pcie_ref(struct iwl_trans *trans)
1669{
1670 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1671 unsigned long flags;
1672
1673 if (iwlwifi_mod_params.d0i3_disable)
1674 return;
1675
1676 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1677 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1678 trans_pcie->ref_count++;
1679 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1680}
1681
1682void iwl_trans_pcie_unref(struct iwl_trans *trans)
1683{
1684 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1685 unsigned long flags;
1686
1687 if (iwlwifi_mod_params.d0i3_disable)
1688 return;
1689
1690 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1691 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1692 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1693 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1694 return;
1695 }
1696 trans_pcie->ref_count--;
1697 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1698}
1699
ff620849
EG		 1700static const char *get_csr_string(int cmd)
1701{
d9fb6465 1702#define IWL_CMD(x) case x: return #x
ff620849
EG		 1703 switch (cmd) {
1704 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1705 IWL_CMD(CSR_INT_COALESCING);
1706 IWL_CMD(CSR_INT);
1707 IWL_CMD(CSR_INT_MASK);
1708 IWL_CMD(CSR_FH_INT_STATUS);
1709 IWL_CMD(CSR_GPIO_IN);
1710 IWL_CMD(CSR_RESET);
1711 IWL_CMD(CSR_GP_CNTRL);
1712 IWL_CMD(CSR_HW_REV);
1713 IWL_CMD(CSR_EEPROM_REG);
1714 IWL_CMD(CSR_EEPROM_GP);
1715 IWL_CMD(CSR_OTP_GP_REG);
1716 IWL_CMD(CSR_GIO_REG);
1717 IWL_CMD(CSR_GP_UCODE_REG);
1718 IWL_CMD(CSR_GP_DRIVER_REG);
1719 IWL_CMD(CSR_UCODE_DRV_GP1);
1720 IWL_CMD(CSR_UCODE_DRV_GP2);
1721 IWL_CMD(CSR_LED_REG);
1722 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1723 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1724 IWL_CMD(CSR_ANA_PLL_CFG);
1725 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1726 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1727 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1728 default:
1729 return "UNKNOWN";
1730 }
d9fb6465 1731#undef IWL_CMD
ff620849
EG		 1732}
1733
990aa6d7 1734void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1735{
1736 int i;
1737 static const u32 csr_tbl[] = {
1738 CSR_HW_IF_CONFIG_REG,
1739 CSR_INT_COALESCING,
1740 CSR_INT,
1741 CSR_INT_MASK,
1742 CSR_FH_INT_STATUS,
1743 CSR_GPIO_IN,
1744 CSR_RESET,
1745 CSR_GP_CNTRL,
1746 CSR_HW_REV,
1747 CSR_EEPROM_REG,
1748 CSR_EEPROM_GP,
1749 CSR_OTP_GP_REG,
1750 CSR_GIO_REG,
1751 CSR_GP_UCODE_REG,
1752 CSR_GP_DRIVER_REG,
1753 CSR_UCODE_DRV_GP1,
1754 CSR_UCODE_DRV_GP2,
1755 CSR_LED_REG,
1756 CSR_DRAM_INT_TBL_REG,
1757 CSR_GIO_CHICKEN_BITS,
1758 CSR_ANA_PLL_CFG,
a812cba9 1759 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1760 CSR_HW_REV_WA_REG,
1761 CSR_DBG_HPET_MEM_REG
1762 };
1763 IWL_ERR(trans, "CSR values:\n");
1764 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1765 "CSR_INT_PERIODIC_REG)\n");
1766 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1767 IWL_ERR(trans, " %25s: 0X%08x\n",
1768 get_csr_string(csr_tbl[i]),
1042db2a 1769 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1770 }
1771}
1772
87e5666c
EG		 1773#ifdef CONFIG_IWLWIFI_DEBUGFS
1774/* create and remove of files */
1775#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1776 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1777 &iwl_dbgfs_##name##_ops)) \
9da987ac 1778 goto err; \
87e5666c
EG		 1779} while (0)
1780
1781/* file operation */
87e5666c 1782#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1783static const struct file_operations iwl_dbgfs_##name##_ops = { \
1784 .read = iwl_dbgfs_##name##_read, \
234e3405 1785 .open = simple_open, \
87e5666c
EG		 1786 .llseek = generic_file_llseek, \
1787};
1788
16db88ba 1789#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1790static const struct file_operations iwl_dbgfs_##name##_ops = { \
1791 .write = iwl_dbgfs_##name##_write, \
234e3405 1792 .open = simple_open, \
16db88ba
EG		 1793 .llseek = generic_file_llseek, \
1794};
1795
87e5666c 1796#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1797static const struct file_operations iwl_dbgfs_##name##_ops = { \
1798 .write = iwl_dbgfs_##name##_write, \
1799 .read = iwl_dbgfs_##name##_read, \
234e3405 1800 .open = simple_open, \
87e5666c
EG		 1801 .llseek = generic_file_llseek, \
1802};
1803
87e5666c 1804static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1805 char __user *user_buf,
1806 size_t count, loff_t *ppos)
8ad71bef 1807{
5a878bf6 1808 struct iwl_trans *trans = file->private_data;
8ad71bef 1809 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1810 struct iwl_txq *txq;
87e5666c
EG		 1811 struct iwl_queue *q;
1812 char *buf;
1813 int pos = 0;
1814 int cnt;
1815 int ret;
1745e440
WYG		 1816 size_t bufsz;
1817
e0b8d405 1818 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 1819
f9e75447 1820 if (!trans_pcie->txq)
87e5666c 1821 return -EAGAIN;
f9e75447 1822
87e5666c
EG		 1823 buf = kzalloc(bufsz, GFP_KERNEL);
1824 if (!buf)
1825 return -ENOMEM;
1826
035f7ff2 1827 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1828 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1829 q = &txq->q;
1830 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 1831 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 1832 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1833 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 1834 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 1835 txq->need_update, txq->frozen,
f40faf62 1836 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1837 }
1838 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1839 kfree(buf);
1840 return ret;
1841}
1842
1843static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1844 char __user *user_buf,
1845 size_t count, loff_t *ppos)
1846{
5a878bf6 1847 struct iwl_trans *trans = file->private_data;
20d3b647 1848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1849 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1850 char buf[256];
1851 int pos = 0;
1852 const size_t bufsz = sizeof(buf);
1853
1854 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1855 rxq->read);
1856 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1857 rxq->write);
f40faf62
AL		 1858 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1859 rxq->write_actual);
1860 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1861 rxq->need_update);
87e5666c
EG		 1862 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1863 rxq->free_count);
1864 if (rxq->rb_stts) {
1865 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1866 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1867 } else {
1868 pos += scnprintf(buf + pos, bufsz - pos,
1869 "closed_rb_num: Not Allocated\n");
1870 }
1871 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1872}
1873
1f7b6172
EG		 1874static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1875 char __user *user_buf,
20d3b647
JB		 1876 size_t count, loff_t *ppos)
1877{
1f7b6172 1878 struct iwl_trans *trans = file->private_data;
20d3b647 1879 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1880 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1881
1882 int pos = 0;
1883 char *buf;
1884 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1885 ssize_t ret;
1886
1887 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1888 if (!buf)
1f7b6172 1889 return -ENOMEM;
1f7b6172
EG		 1890
1891 pos += scnprintf(buf + pos, bufsz - pos,
1892 "Interrupt Statistics Report:\n");
1893
1894 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1895 isr_stats->hw);
1896 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1897 isr_stats->sw);
1898 if (isr_stats->sw || isr_stats->hw) {
1899 pos += scnprintf(buf + pos, bufsz - pos,
1900 "\tLast Restarting Code: 0x%X\n",
1901 isr_stats->err_code);
1902 }
1903#ifdef CONFIG_IWLWIFI_DEBUG
1904 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1905 isr_stats->sch);
1906 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1907 isr_stats->alive);
1908#endif
1909 pos += scnprintf(buf + pos, bufsz - pos,
1910 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1911
1912 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1913 isr_stats->ctkill);
1914
1915 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1916 isr_stats->wakeup);
1917
1918 pos += scnprintf(buf + pos, bufsz - pos,
1919 "Rx command responses:\t\t %u\n", isr_stats->rx);
1920
1921 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1922 isr_stats->tx);
1923
1924 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1925 isr_stats->unhandled);
1926
1927 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1928 kfree(buf);
1929 return ret;
1930}
1931
1932static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1933 const char __user *user_buf,
1934 size_t count, loff_t *ppos)
1935{
1936 struct iwl_trans *trans = file->private_data;
20d3b647 1937 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1938 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1939
1940 char buf[8];
1941 int buf_size;
1942 u32 reset_flag;
1943
1944 memset(buf, 0, sizeof(buf));
1945 buf_size = min(count, sizeof(buf) - 1);
1946 if (copy_from_user(buf, user_buf, buf_size))
1947 return -EFAULT;
1948 if (sscanf(buf, "%x", &reset_flag) != 1)
1949 return -EFAULT;
1950 if (reset_flag == 0)
1951 memset(isr_stats, 0, sizeof(*isr_stats));
1952
1953 return count;
1954}
1955
16db88ba 1956static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 1957 const char __user *user_buf,
1958 size_t count, loff_t *ppos)
16db88ba
EG		 1959{
1960 struct iwl_trans *trans = file->private_data;
1961 char buf[8];
1962 int buf_size;
1963 int csr;
1964
1965 memset(buf, 0, sizeof(buf));
1966 buf_size = min(count, sizeof(buf) - 1);
1967 if (copy_from_user(buf, user_buf, buf_size))
1968 return -EFAULT;
1969 if (sscanf(buf, "%d", &csr) != 1)
1970 return -EFAULT;
1971
990aa6d7 1972 iwl_pcie_dump_csr(trans);
16db88ba
EG		 1973
1974 return count;
1975}
1976
16db88ba 1977static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 1978 char __user *user_buf,
1979 size_t count, loff_t *ppos)
16db88ba
EG		 1980{
1981 struct iwl_trans *trans = file->private_data;
94543a8d 1982 char *buf = NULL;
56c2477f 1983 ssize_t ret;
16db88ba 1984
56c2477f
JB		 1985 ret = iwl_dump_fh(trans, &buf);
1986 if (ret < 0)
1987 return ret;
1988 if (!buf)
1989 return -EINVAL;
1990 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1991 kfree(buf);
16db88ba
EG		 1992 return ret;
1993}
1994
1f7b6172 1995DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 1996DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 1997DEBUGFS_READ_FILE_OPS(rx_queue);
1998DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 1999DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 2000
2001/*
2002 * Create the debugfs files and directories
2003 *
2004 */
2005static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 2006 struct dentry *dir)
87e5666c 2007{
87e5666c
EG		 2008 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2009 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2010 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2011 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2012 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2013 return 0;
9da987ac
MV		 2014
2015err:
2016 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2017 return -ENOMEM;
87e5666c 2018}
aadede6e
JB		 2019#else
2020static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2021 struct dentry *dir)
2022{
2023 return 0;
2024}
2025#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2026
2027static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2028{
2029 u32 cmdlen = 0;
2030 int i;
2031
2032 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2033 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2034
2035 return cmdlen;
2036}
2037
67c65f2c
EG		 2038static const struct {
2039 u32 start, end;
2040} iwl_prph_dump_addr[] = {
2041 { .start = 0x00a00000, .end = 0x00a00000 },
2042 { .start = 0x00a0000c, .end = 0x00a00024 },
2043 { .start = 0x00a0002c, .end = 0x00a0003c },
2044 { .start = 0x00a00410, .end = 0x00a00418 },
2045 { .start = 0x00a00420, .end = 0x00a00420 },
2046 { .start = 0x00a00428, .end = 0x00a00428 },
2047 { .start = 0x00a00430, .end = 0x00a0043c },
2048 { .start = 0x00a00444, .end = 0x00a00444 },
2049 { .start = 0x00a004c0, .end = 0x00a004cc },
2050 { .start = 0x00a004d8, .end = 0x00a004d8 },
2051 { .start = 0x00a004e0, .end = 0x00a004f0 },
2052 { .start = 0x00a00840, .end = 0x00a00840 },
2053 { .start = 0x00a00850, .end = 0x00a00858 },
2054 { .start = 0x00a01004, .end = 0x00a01008 },
2055 { .start = 0x00a01010, .end = 0x00a01010 },
2056 { .start = 0x00a01018, .end = 0x00a01018 },
2057 { .start = 0x00a01024, .end = 0x00a01024 },
2058 { .start = 0x00a0102c, .end = 0x00a01034 },
2059 { .start = 0x00a0103c, .end = 0x00a01040 },
2060 { .start = 0x00a01048, .end = 0x00a01094 },
2061 { .start = 0x00a01c00, .end = 0x00a01c20 },
2062 { .start = 0x00a01c58, .end = 0x00a01c58 },
2063 { .start = 0x00a01c7c, .end = 0x00a01c7c },
2064 { .start = 0x00a01c28, .end = 0x00a01c54 },
2065 { .start = 0x00a01c5c, .end = 0x00a01c5c },
6a65bd53 2066 { .start = 0x00a01c60, .end = 0x00a01cdc },
67c65f2c
EG		 2067 { .start = 0x00a01ce0, .end = 0x00a01d0c },
2068 { .start = 0x00a01d18, .end = 0x00a01d20 },
2069 { .start = 0x00a01d2c, .end = 0x00a01d30 },
2070 { .start = 0x00a01d40, .end = 0x00a01d5c },
2071 { .start = 0x00a01d80, .end = 0x00a01d80 },
6a65bd53
EG		 2072 { .start = 0x00a01d98, .end = 0x00a01d9c },
2073 { .start = 0x00a01da8, .end = 0x00a01da8 },
2074 { .start = 0x00a01db8, .end = 0x00a01df4 },
67c65f2c
EG		 2075 { .start = 0x00a01dc0, .end = 0x00a01dfc },
2076 { .start = 0x00a01e00, .end = 0x00a01e2c },
2077 { .start = 0x00a01e40, .end = 0x00a01e60 },
6a65bd53
EG		 2078 { .start = 0x00a01e68, .end = 0x00a01e6c },
2079 { .start = 0x00a01e74, .end = 0x00a01e74 },
67c65f2c
EG		 2080 { .start = 0x00a01e84, .end = 0x00a01e90 },
2081 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
6a65bd53
EG		 2082 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2083 { .start = 0x00a01f00, .end = 0x00a01f1c },
2084 { .start = 0x00a01f44, .end = 0x00a01ffc },
67c65f2c
EG		 2085 { .start = 0x00a02000, .end = 0x00a02048 },
2086 { .start = 0x00a02068, .end = 0x00a020f0 },
2087 { .start = 0x00a02100, .end = 0x00a02118 },
2088 { .start = 0x00a02140, .end = 0x00a0214c },
2089 { .start = 0x00a02168, .end = 0x00a0218c },
2090 { .start = 0x00a021c0, .end = 0x00a021c0 },
2091 { .start = 0x00a02400, .end = 0x00a02410 },
2092 { .start = 0x00a02418, .end = 0x00a02420 },
2093 { .start = 0x00a02428, .end = 0x00a0242c },
2094 { .start = 0x00a02434, .end = 0x00a02434 },
2095 { .start = 0x00a02440, .end = 0x00a02460 },
2096 { .start = 0x00a02468, .end = 0x00a024b0 },
2097 { .start = 0x00a024c8, .end = 0x00a024cc },
2098 { .start = 0x00a02500, .end = 0x00a02504 },
2099 { .start = 0x00a0250c, .end = 0x00a02510 },
2100 { .start = 0x00a02540, .end = 0x00a02554 },
2101 { .start = 0x00a02580, .end = 0x00a025f4 },
2102 { .start = 0x00a02600, .end = 0x00a0260c },
2103 { .start = 0x00a02648, .end = 0x00a02650 },
2104 { .start = 0x00a02680, .end = 0x00a02680 },
2105 { .start = 0x00a026c0, .end = 0x00a026d0 },
2106 { .start = 0x00a02700, .end = 0x00a0270c },
2107 { .start = 0x00a02804, .end = 0x00a02804 },
2108 { .start = 0x00a02818, .end = 0x00a0281c },
2109 { .start = 0x00a02c00, .end = 0x00a02db4 },
2110 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2111 { .start = 0x00a03000, .end = 0x00a03014 },
2112 { .start = 0x00a0301c, .end = 0x00a0302c },
2113 { .start = 0x00a03034, .end = 0x00a03038 },
2114 { .start = 0x00a03040, .end = 0x00a03048 },
2115 { .start = 0x00a03060, .end = 0x00a03068 },
2116 { .start = 0x00a03070, .end = 0x00a03074 },
2117 { .start = 0x00a0307c, .end = 0x00a0307c },
2118 { .start = 0x00a03080, .end = 0x00a03084 },
2119 { .start = 0x00a0308c, .end = 0x00a03090 },
2120 { .start = 0x00a03098, .end = 0x00a03098 },
2121 { .start = 0x00a030a0, .end = 0x00a030a0 },
2122 { .start = 0x00a030a8, .end = 0x00a030b4 },
2123 { .start = 0x00a030bc, .end = 0x00a030bc },
2124 { .start = 0x00a030c0, .end = 0x00a0312c },
2125 { .start = 0x00a03c00, .end = 0x00a03c5c },
2126 { .start = 0x00a04400, .end = 0x00a04454 },
2127 { .start = 0x00a04460, .end = 0x00a04474 },
2128 { .start = 0x00a044c0, .end = 0x00a044ec },
2129 { .start = 0x00a04500, .end = 0x00a04504 },
2130 { .start = 0x00a04510, .end = 0x00a04538 },
2131 { .start = 0x00a04540, .end = 0x00a04548 },
2132 { .start = 0x00a04560, .end = 0x00a0457c },
2133 { .start = 0x00a04590, .end = 0x00a04598 },
2134 { .start = 0x00a045c0, .end = 0x00a045f4 },
2135};
2136
2137static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2138 struct iwl_fw_error_dump_data **data)
2139{
2140 struct iwl_fw_error_dump_prph *prph;
2141 unsigned long flags;
2142 u32 prph_len = 0, i;
2143
2144 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2145 return 0;
2146
2147 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2148 /* The range includes both boundaries */
2149 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2150 iwl_prph_dump_addr[i].start + 4;
2151 int reg;
2152 __le32 *val;
2153
87dd634a 2154 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 2155
2156 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2157 (*data)->len = cpu_to_le32(sizeof(*prph) +
2158 num_bytes_in_chunk);
2159 prph = (void *)(*data)->data;
2160 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2161 val = (void *)prph->data;
2162
2163 for (reg = iwl_prph_dump_addr[i].start;
2164 reg <= iwl_prph_dump_addr[i].end;
2165 reg += 4)
2166 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2167 reg));
2168 *data = iwl_fw_error_next_data(*data);
2169 }
2170
2171 iwl_trans_release_nic_access(trans, &flags);
2172
2173 return prph_len;
2174}
2175
473ad712
EG		 2176#define IWL_CSR_TO_DUMP (0x250)
2177
2178static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2179 struct iwl_fw_error_dump_data **data)
2180{
2181 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2182 __le32 *val;
2183 int i;
2184
2185 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2186 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2187 val = (void *)(*data)->data;
2188
2189 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2190 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2191
2192 *data = iwl_fw_error_next_data(*data);
2193
2194 return csr_len;
2195}
2196
06d51e0d
LK		 2197static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2198 struct iwl_fw_error_dump_data **data)
2199{
2200 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2201 unsigned long flags;
2202 __le32 *val;
2203 int i;
2204
2205 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2206 return 0;
2207
2208 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2209 (*data)->len = cpu_to_le32(fh_regs_len);
2210 val = (void *)(*data)->data;
2211
2212 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2213 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2214
2215 iwl_trans_release_nic_access(trans, &flags);
2216
2217 *data = iwl_fw_error_next_data(*data);
2218
2219 return sizeof(**data) + fh_regs_len;
2220}
2221
cc79ef66
LK		 2222static u32
2223iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2224 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2225 u32 monitor_len)
2226{
2227 u32 buf_size_in_dwords = (monitor_len >> 2);
2228 u32 *buffer = (u32 *)fw_mon_data->data;
2229 unsigned long flags;
2230 u32 i;
2231
2232 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2233 return 0;
2234
2235 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2236 for (i = 0; i < buf_size_in_dwords; i++)
2237 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2238 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2239
2240 iwl_trans_release_nic_access(trans, &flags);
2241
2242 return monitor_len;
2243}
2244
48eb7b34
EG		 2245static
2246struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
4d075007
JB		 2247{
2248 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2249 struct iwl_fw_error_dump_data *data;
2250 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2251 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2252 struct iwl_trans_dump_data *dump_data;
4d075007 2253 u32 len;
99684ae3 2254 u32 monitor_len;
4d075007
JB		 2255 int i, ptr;
2256
473ad712
EG		 2257 /* transport dump header */
2258 len = sizeof(*dump_data);
2259
2260 /* host commands */
2261 len += sizeof(*data) +
c2d20201
EG		 2262 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2263
473ad712
EG		 2264 /* CSR registers */
2265 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2266
2267 /* PRPH registers */
67c65f2c
EG		 2268 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2269 /* The range includes both boundaries */
2270 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2271 iwl_prph_dump_addr[i].start + 4;
2272
2273 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2274 num_bytes_in_chunk;
2275 }
2276
06d51e0d
LK		 2277 /* FH registers */
2278 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2279
473ad712 2280 /* FW monitor */
99684ae3 2281 if (trans_pcie->fw_mon_page) {
c544e9c4 2282 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2283 trans_pcie->fw_mon_size;
2284 monitor_len = trans_pcie->fw_mon_size;
2285 } else if (trans->dbg_dest_tlv) {
2286 u32 base, end;
2287
2288 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2289 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2290
2291 base = iwl_read_prph(trans, base) <<
2292 trans->dbg_dest_tlv->base_shift;
2293 end = iwl_read_prph(trans, end) <<
2294 trans->dbg_dest_tlv->end_shift;
2295
2296 /* Make "end" point to the actual end */
cc79ef66
LK		 2297 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2298 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2299 end += (1 << trans->dbg_dest_tlv->end_shift);
2300 monitor_len = end - base;
2301 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2302 monitor_len;
2303 } else {
2304 monitor_len = 0;
2305 }
c2d20201 2306
48eb7b34
EG		 2307 dump_data = vzalloc(len);
2308 if (!dump_data)
2309 return NULL;
4d075007
JB		 2310
2311 len = 0;
48eb7b34 2312 data = (void *)dump_data->data;
4d075007
JB		 2313 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2314 txcmd = (void *)data->data;
2315 spin_lock_bh(&cmdq->lock);
2316 ptr = cmdq->q.write_ptr;
2317 for (i = 0; i < cmdq->q.n_window; i++) {
2318 u8 idx = get_cmd_index(&cmdq->q, ptr);
2319 u32 caplen, cmdlen;
2320
2321 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2322 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2323
2324 if (cmdlen) {
2325 len += sizeof(*txcmd) + caplen;
2326 txcmd->cmdlen = cpu_to_le32(cmdlen);
2327 txcmd->caplen = cpu_to_le32(caplen);
2328 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2329 txcmd = (void *)((u8 *)txcmd->data + caplen);
2330 }
2331
2332 ptr = iwl_queue_dec_wrap(ptr);
2333 }
2334 spin_unlock_bh(&cmdq->lock);
2335
2336 data->len = cpu_to_le32(len);
c2d20201 2337 len += sizeof(*data);
67c65f2c
EG		 2338 data = iwl_fw_error_next_data(data);
2339
2340 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2341 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2342 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
67c65f2c 2343 /* data is already pointing to the next section */
c2d20201 2344
99684ae3
LK		 2345 if ((trans_pcie->fw_mon_page &&
2346 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2347 trans->dbg_dest_tlv) {
c544e9c4 2348 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
99684ae3
LK		 2349 u32 base, write_ptr, wrap_cnt;
2350
2351 /* If there was a dest TLV - use the values from there */
2352 if (trans->dbg_dest_tlv) {
2353 write_ptr =
2354 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2355 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2356 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2357 } else {
2358 base = MON_BUFF_BASE_ADDR;
2359 write_ptr = MON_BUFF_WRPTR;
2360 wrap_cnt = MON_BUFF_CYCLE_CNT;
2361 }
c2d20201 2362
c2d20201 2363 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
c2d20201
EG		 2364 fw_mon_data = (void *)data->data;
2365 fw_mon_data->fw_mon_wr_ptr =
99684ae3 2366 cpu_to_le32(iwl_read_prph(trans, write_ptr));
c2d20201 2367 fw_mon_data->fw_mon_cycle_cnt =
99684ae3 2368 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
c2d20201 2369 fw_mon_data->fw_mon_base_ptr =
99684ae3
LK		 2370 cpu_to_le32(iwl_read_prph(trans, base));
2371
2372 len += sizeof(*data) + sizeof(*fw_mon_data);
2373 if (trans_pcie->fw_mon_page) {
99684ae3
LK		 2374 /*
2375 * The firmware is now asserted, it won't write anything
2376 * to the buffer. CPU can take ownership to fetch the
2377 * data. The buffer will be handed back to the device
2378 * before the firmware will be restarted.
2379 */
2380 dma_sync_single_for_cpu(trans->dev,
2381 trans_pcie->fw_mon_phys,
2382 trans_pcie->fw_mon_size,
2383 DMA_FROM_DEVICE);
2384 memcpy(fw_mon_data->data,
2385 page_address(trans_pcie->fw_mon_page),
2386 trans_pcie->fw_mon_size);
2387
cc79ef66
LK		 2388 monitor_len = trans_pcie->fw_mon_size;
2389 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
99684ae3
LK		 2390 /*
2391 * Update pointers to reflect actual values after
2392 * shifting
2393 */
2394 base = iwl_read_prph(trans, base) <<
2395 trans->dbg_dest_tlv->base_shift;
2396 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2397 monitor_len / sizeof(u32));
cc79ef66
LK		 2398 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2399 monitor_len =
2400 iwl_trans_pci_dump_marbh_monitor(trans,
2401 fw_mon_data,
2402 monitor_len);
2403 } else {
2404 /* Didn't match anything - output no monitor data */
2405 monitor_len = 0;
99684ae3 2406 }
cc79ef66
LK		 2407
2408 len += monitor_len;
2409 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
c2d20201
EG		 2410 }
2411
48eb7b34
EG		 2412 dump_data->len = len;
2413
2414 return dump_data;
4d075007 2415}
87e5666c 2416
d1ff5253 2417static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2418 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2419 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2420 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2421 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2422 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2423
ddaf5a5b
JB		 2424 .d3_suspend = iwl_trans_pcie_d3_suspend,
2425 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2426
f02831be 2427 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2428
e6bb4c9c 2429 .tx = iwl_trans_pcie_tx,
a0eaad71 2430 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2431
d0624be6 2432 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2433 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2434
87e5666c 2435 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2436
990aa6d7 2437 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2438 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
5f178cd2 2439
03905495
EG		 2440 .write8 = iwl_trans_pcie_write8,
2441 .write32 = iwl_trans_pcie_write32,
2442 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2443 .read_prph = iwl_trans_pcie_read_prph,
2444 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2445 .read_mem = iwl_trans_pcie_read_mem,
2446 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2447 .configure = iwl_trans_pcie_configure,
47107e84 2448 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2449 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2450 .release_nic_access = iwl_trans_pcie_release_nic_access,
2451 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2452
7616f334
EP		 2453 .ref = iwl_trans_pcie_ref,
2454 .unref = iwl_trans_pcie_unref,
2455
4d075007 2456 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2457};
a42a1844 2458
87ce05a2 2459struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2460 const struct pci_device_id *ent,
2461 const struct iwl_cfg *cfg)
a42a1844 2462{
a42a1844
EG		 2463 struct iwl_trans_pcie *trans_pcie;
2464 struct iwl_trans *trans;
2465 u16 pci_cmd;
2466 int err;
2467
7b501d10
JB		 2468 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2469 &pdev->dev, cfg, &trans_ops_pcie, 0);
2470 if (!trans)
2471 return ERR_PTR(-ENOMEM);
a42a1844
EG		 2472
2473 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2474
a42a1844 2475 trans_pcie->trans = trans;
7b11488f 2476 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2477 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2478 spin_lock_init(&trans_pcie->ref_lock);
13df1aab 2479 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2480
d819c6cf
JB		 2481 err = pci_enable_device(pdev);
2482 if (err)
2483 goto out_no_pci;
2484
f2532b04
EG		 2485 if (!cfg->base_params->pcie_l1_allowed) {
2486 /*
2487 * W/A - seems to solve weird behavior. We need to remove this
2488 * if we don't want to stay in L1 all the time. This wastes a
2489 * lot of power.
2490 */
2491 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2492 PCIE_LINK_STATE_L1 |
2493 PCIE_LINK_STATE_CLKPM);
2494 }
a42a1844 2495
a42a1844
EG		 2496 pci_set_master(pdev);
2497
2498 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2499 if (!err)
2500 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2501 if (err) {
2502 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2503 if (!err)
2504 err = pci_set_consistent_dma_mask(pdev,
20d3b647 2505 DMA_BIT_MASK(32));
a42a1844
EG		 2506 /* both attempts failed: */
2507 if (err) {
6a4b09f8 2508 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2509 goto out_pci_disable_device;
2510 }
2511 }
2512
2513 err = pci_request_regions(pdev, DRV_NAME);
2514 if (err) {
6a4b09f8 2515 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2516 goto out_pci_disable_device;
2517 }
2518
05f5b97e 2519 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2520 if (!trans_pcie->hw_base) {
6a4b09f8 2521 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
a42a1844
EG		 2522 err = -ENODEV;
2523 goto out_pci_release_regions;
2524 }
2525
a42a1844
EG		 2526 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2527 * PCI Tx retries from interfering with C3 CPU state */
2528 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2529
83f7a85f
EG		 2530 trans->dev = &pdev->dev;
2531 trans_pcie->pci_dev = pdev;
2532 iwl_disable_interrupts(trans);
2533
a42a1844 2534 err = pci_enable_msi(pdev);
9f904b38 2535 if (err) {
6a4b09f8 2536 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
9f904b38
EG		 2537 /* enable rfkill interrupt: hw bug w/a */
2538 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2539 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2540 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2541 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2542 }
2543 }
a42a1844 2544
08079a49 2545 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2546 /*
2547 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2548 * changed, and now the revision step also includes bit 0-1 (no more
2549 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2550 * in the old format.
2551 */
7a42baa6
EH		 2552 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2553 unsigned long flags;
2554 int ret;
2555
b513ee7f 2556 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2557 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2558
7a42baa6
EH		 2559 /*
2560 * in-order to recognize C step driver should read chip version
2561 * id located at the AUX bus MISC address space.
2562 */
2563 iwl_set_bit(trans, CSR_GP_CNTRL,
2564 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2565 udelay(2);
2566
2567 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2568 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2569 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2570 25000);
2571 if (ret < 0) {
2572 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2573 goto out_pci_disable_msi;
2574 }
2575
2576 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2577 u32 hw_step;
2578
2579 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2580 hw_step |= ENABLE_WFPM;
2581 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2582 hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2583 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2584 if (hw_step == 0x3)
2585 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2586 (SILICON_C_STEP << 2);
2587 iwl_trans_release_nic_access(trans, &flags);
2588 }
2589 }
2590
99673ee5 2591 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2592 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2593 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2594
69a10b29 2595 /* Initialize the wait queue for commands */
f946b529 2596 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2597
a8b691e6 2598 if (iwl_pcie_alloc_ict(trans))
7b501d10 2599 goto out_pci_disable_msi;
a8b691e6 2600
85bf9da1 2601 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2602 iwl_pcie_irq_handler,
2603 IRQF_SHARED, DRV_NAME, trans);
2604 if (err) {
a8b691e6
JB		 2605 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2606 goto out_free_ict;
2607 }
2608
83f7a85f 2609 trans_pcie->inta_mask = CSR_INI_SET_MASK;
6735943f 2610 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
83f7a85f 2611
a42a1844
EG		 2612 return trans;
2613
a8b691e6
JB		 2614out_free_ict:
2615 iwl_pcie_free_ict(trans);
59c647b6
EG		 2616out_pci_disable_msi:
2617 pci_disable_msi(pdev);
a42a1844
EG		 2618out_pci_release_regions:
2619 pci_release_regions(pdev);
2620out_pci_disable_device:
2621 pci_disable_device(pdev);
2622out_no_pci:
7b501d10 2623 iwl_trans_free(trans);
6965a354 2624 return ERR_PTR(err);
a42a1844 2625}
Linux 6.x block layer and io_uring tree(s)