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ab697a9f EG |
1 | /****************************************************************************** |
2 | * | |
51368bf7 | 3 | * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. |
ab697a9f EG |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | #ifndef __iwl_trans_int_pcie_h__ | |
30 | #define __iwl_trans_int_pcie_h__ | |
31 | ||
a72b8b08 EG |
32 | #include <linux/spinlock.h> |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/skbuff.h> | |
13df1aab | 35 | #include <linux/wait.h> |
522376d2 | 36 | #include <linux/pci.h> |
7c5ba4a8 | 37 | #include <linux/timer.h> |
a72b8b08 | 38 | |
dda61a44 | 39 | #include "iwl-fh.h" |
a72b8b08 | 40 | #include "iwl-csr.h" |
a72b8b08 EG |
41 | #include "iwl-trans.h" |
42 | #include "iwl-debug.h" | |
43 | #include "iwl-io.h" | |
02e38358 | 44 | #include "iwl-op-mode.h" |
a72b8b08 | 45 | |
a72b8b08 | 46 | struct iwl_host_cmd; |
dda61a44 | 47 | |
ab697a9f EG |
48 | /*This file includes the declaration that are internal to the |
49 | * trans_pcie layer */ | |
50 | ||
48a2d66f JB |
51 | struct iwl_rx_mem_buffer { |
52 | dma_addr_t page_dma; | |
53 | struct page *page; | |
54 | struct list_head list; | |
55 | }; | |
56 | ||
1f7b6172 EG |
57 | /** |
58 | * struct isr_statistics - interrupt statistics | |
59 | * | |
60 | */ | |
61 | struct isr_statistics { | |
62 | u32 hw; | |
63 | u32 sw; | |
64 | u32 err_code; | |
65 | u32 sch; | |
66 | u32 alive; | |
67 | u32 rfkill; | |
68 | u32 ctkill; | |
69 | u32 wakeup; | |
70 | u32 rx; | |
71 | u32 tx; | |
72 | u32 unhandled; | |
73 | }; | |
74 | ||
5a878bf6 | 75 | /** |
990aa6d7 | 76 | * struct iwl_rxq - Rx queue |
5a878bf6 EG |
77 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) |
78 | * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) | |
79 | * @pool: | |
80 | * @queue: | |
81 | * @read: Shared index to newest available Rx buffer | |
82 | * @write: Shared index to oldest written Rx packet | |
83 | * @free_count: Number of pre-allocated buffers in rx_free | |
84 | * @write_actual: | |
85 | * @rx_free: list of free SKBs for use | |
86 | * @rx_used: List of Rx buffers with no SKB | |
87 | * @need_update: flag to indicate we need to update read/write index | |
88 | * @rb_stts: driver's pointer to receive buffer status | |
89 | * @rb_stts_dma: bus address of receive buffer status | |
90 | * @lock: | |
91 | * | |
92 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers | |
93 | */ | |
990aa6d7 | 94 | struct iwl_rxq { |
5a878bf6 EG |
95 | __le32 *bd; |
96 | dma_addr_t bd_dma; | |
97 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; | |
98 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
99 | u32 read; | |
100 | u32 write; | |
101 | u32 free_count; | |
102 | u32 write_actual; | |
103 | struct list_head rx_free; | |
104 | struct list_head rx_used; | |
105 | int need_update; | |
106 | struct iwl_rb_status *rb_stts; | |
107 | dma_addr_t rb_stts_dma; | |
108 | spinlock_t lock; | |
109 | }; | |
110 | ||
a72b8b08 EG |
111 | struct iwl_dma_ptr { |
112 | dma_addr_t dma; | |
113 | void *addr; | |
114 | size_t size; | |
115 | }; | |
116 | ||
bffc66ce JB |
117 | /** |
118 | * iwl_queue_inc_wrap - increment queue index, wrap back to beginning | |
119 | * @index -- current index | |
120 | * @n_bd -- total number of entries in queue (must be power of 2) | |
121 | */ | |
122 | static inline int iwl_queue_inc_wrap(int index, int n_bd) | |
123 | { | |
124 | return ++index & (n_bd - 1); | |
125 | } | |
126 | ||
127 | /** | |
128 | * iwl_queue_dec_wrap - decrement queue index, wrap back to end | |
129 | * @index -- current index | |
130 | * @n_bd -- total number of entries in queue (must be power of 2) | |
131 | */ | |
132 | static inline int iwl_queue_dec_wrap(int index, int n_bd) | |
133 | { | |
134 | return --index & (n_bd - 1); | |
135 | } | |
136 | ||
522376d2 EG |
137 | struct iwl_cmd_meta { |
138 | /* only for SYNC commands, iff the reply skb is wanted */ | |
139 | struct iwl_host_cmd *source; | |
c14c7372 | 140 | u32 flags; |
522376d2 EG |
141 | }; |
142 | ||
143 | /* | |
144 | * Generic queue structure | |
145 | * | |
146 | * Contains common data for Rx and Tx queues. | |
147 | * | |
148 | * Note the difference between n_bd and n_window: the hardware | |
149 | * always assumes 256 descriptors, so n_bd is always 256 (unless | |
150 | * there might be HW changes in the future). For the normal TX | |
151 | * queues, n_window, which is the size of the software queue data | |
152 | * is also 256; however, for the command queue, n_window is only | |
153 | * 32 since we don't need so many commands pending. Since the HW | |
154 | * still uses 256 BDs for DMA though, n_bd stays 256. As a result, | |
155 | * the software buffers (in the variables @meta, @txb in struct | |
990aa6d7 EG |
156 | * iwl_txq) only have 32 entries, while the HW buffers (@tfds in |
157 | * the same struct) have 256. | |
522376d2 EG |
158 | * This means that we end up with the following: |
159 | * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | | |
160 | * SW entries: | 0 | ... | 31 | | |
161 | * where N is a number between 0 and 7. This means that the SW | |
162 | * data is a window overlayed over the HW queue. | |
163 | */ | |
164 | struct iwl_queue { | |
165 | int n_bd; /* number of BDs in this queue */ | |
166 | int write_ptr; /* 1-st empty entry (index) host_w*/ | |
167 | int read_ptr; /* last used entry (index) host_r*/ | |
168 | /* use for monitoring and recovering the stuck queue */ | |
169 | dma_addr_t dma_addr; /* physical addr for BD's */ | |
170 | int n_window; /* safe queue window */ | |
171 | u32 id; | |
172 | int low_mark; /* low watermark, resume queue if free | |
173 | * space more than this */ | |
174 | int high_mark; /* high watermark, stop queue if free | |
175 | * space less than this */ | |
176 | }; | |
177 | ||
bf8440e6 JB |
178 | #define TFD_TX_CMD_SLOTS 256 |
179 | #define TFD_CMD_SLOTS 32 | |
180 | ||
8a964f44 JB |
181 | /* |
182 | * The FH will write back to the first TB only, so we need | |
183 | * to copy some data into the buffer regardless of whether | |
38c0f334 JB |
184 | * it should be mapped or not. This indicates how big the |
185 | * first TB must be to include the scratch buffer. Since | |
186 | * the scratch is 4 bytes at offset 12, it's 16 now. If we | |
187 | * make it bigger then allocations will be bigger and copy | |
188 | * slower, so that's probably not useful. | |
8a964f44 | 189 | */ |
38c0f334 | 190 | #define IWL_HCMD_SCRATCHBUF_SIZE 16 |
8a964f44 | 191 | |
990aa6d7 | 192 | struct iwl_pcie_txq_entry { |
bf8440e6 JB |
193 | struct iwl_device_cmd *cmd; |
194 | struct sk_buff *skb; | |
f4feb8ac JB |
195 | /* buffer to free after command completes */ |
196 | const void *free_buf; | |
bf8440e6 JB |
197 | struct iwl_cmd_meta meta; |
198 | }; | |
199 | ||
38c0f334 JB |
200 | struct iwl_pcie_txq_scratch_buf { |
201 | struct iwl_cmd_header hdr; | |
202 | u8 buf[8]; | |
203 | __le32 scratch; | |
204 | }; | |
205 | ||
522376d2 | 206 | /** |
990aa6d7 | 207 | * struct iwl_txq - Tx Queue for DMA |
522376d2 | 208 | * @q: generic Rx/Tx queue descriptor |
bf8440e6 | 209 | * @tfds: transmit frame descriptors (DMA memory) |
38c0f334 JB |
210 | * @scratchbufs: start of command headers, including scratch buffers, for |
211 | * the writeback -- this is DMA memory and an array holding one buffer | |
212 | * for each command on the queue | |
213 | * @scratchbufs_dma: DMA address for the scratchbufs start | |
bf8440e6 JB |
214 | * @entries: transmit entries (driver state) |
215 | * @lock: queue lock | |
216 | * @stuck_timer: timer that fires if queue gets stuck | |
217 | * @trans_pcie: pointer back to transport (for timer) | |
522376d2 | 218 | * @need_update: indicates need to update read/write index |
bf8440e6 | 219 | * @active: stores if queue is active |
68972c46 | 220 | * @ampdu: true if this queue is an ampdu queue for an specific RA/TID |
522376d2 EG |
221 | * |
222 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame | |
223 | * descriptors) and required locking structures. | |
224 | */ | |
990aa6d7 | 225 | struct iwl_txq { |
522376d2 EG |
226 | struct iwl_queue q; |
227 | struct iwl_tfd *tfds; | |
38c0f334 JB |
228 | struct iwl_pcie_txq_scratch_buf *scratchbufs; |
229 | dma_addr_t scratchbufs_dma; | |
990aa6d7 | 230 | struct iwl_pcie_txq_entry *entries; |
015c15e1 | 231 | spinlock_t lock; |
7c5ba4a8 JB |
232 | struct timer_list stuck_timer; |
233 | struct iwl_trans_pcie *trans_pcie; | |
522376d2 | 234 | u8 need_update; |
522376d2 | 235 | u8 active; |
68972c46 | 236 | bool ampdu; |
522376d2 EG |
237 | }; |
238 | ||
38c0f334 JB |
239 | static inline dma_addr_t |
240 | iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx) | |
241 | { | |
242 | return txq->scratchbufs_dma + | |
243 | sizeof(struct iwl_pcie_txq_scratch_buf) * idx; | |
244 | } | |
245 | ||
e6bb4c9c EG |
246 | /** |
247 | * struct iwl_trans_pcie - PCIe transport specific data | |
5a878bf6 EG |
248 | * @rxq: all the RX queue data |
249 | * @rx_replenish: work that will be called when buffers need to be allocated | |
9130bab1 | 250 | * @drv - pointer to iwl_drv |
5a878bf6 | 251 | * @trans: pointer to the generic transport area |
105183b1 EG |
252 | * @scd_base_addr: scheduler sram base address in SRAM |
253 | * @scd_bc_tbls: pointer to the byte count table of the scheduler | |
9d6b2cb1 | 254 | * @kw: keep warm address |
a42a1844 EG |
255 | * @pci_dev: basic pci-network driver stuff |
256 | * @hw_base: pci hardware address support | |
13df1aab JB |
257 | * @ucode_write_complete: indicates that the ucode has been copied. |
258 | * @ucode_write_waitq: wait queue for uCode load | |
c6f600fc | 259 | * @cmd_queue - command queue number |
b2cf410c | 260 | * @rx_buf_size_8k: 8 kB RX buffer size |
046db346 | 261 | * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) |
b2cf410c | 262 | * @rx_page_order: page order for receive buffer size |
7c5ba4a8 | 263 | * @wd_timeout: queue watchdog timeout (jiffies) |
e56b04ef | 264 | * @reg_lock: protect hw register access |
b9439491 | 265 | * @cmd_in_flight: true when we have a host command in flight |
e6bb4c9c EG |
266 | */ |
267 | struct iwl_trans_pcie { | |
990aa6d7 | 268 | struct iwl_rxq rxq; |
5a878bf6 EG |
269 | struct work_struct rx_replenish; |
270 | struct iwl_trans *trans; | |
9130bab1 | 271 | struct iwl_drv *drv; |
0c325769 EG |
272 | |
273 | /* INT ICT Table */ | |
274 | __le32 *ict_tbl; | |
0c325769 | 275 | dma_addr_t ict_tbl_dma; |
0c325769 | 276 | int ict_index; |
0c325769 | 277 | bool use_ict; |
1f7b6172 | 278 | struct isr_statistics isr_stats; |
0c325769 | 279 | |
7b11488f | 280 | spinlock_t irq_lock; |
0c325769 | 281 | u32 inta_mask; |
105183b1 EG |
282 | u32 scd_base_addr; |
283 | struct iwl_dma_ptr scd_bc_tbls; | |
9d6b2cb1 | 284 | struct iwl_dma_ptr kw; |
e13c0c59 | 285 | |
990aa6d7 | 286 | struct iwl_txq *txq; |
9eae88fa | 287 | unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; |
8ad71bef | 288 | unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; |
a42a1844 EG |
289 | |
290 | /* PCI bus related data */ | |
291 | struct pci_dev *pci_dev; | |
292 | void __iomem *hw_base; | |
13df1aab JB |
293 | |
294 | bool ucode_write_complete; | |
295 | wait_queue_head_t ucode_write_waitq; | |
f946b529 EG |
296 | wait_queue_head_t wait_command_queue; |
297 | ||
c6f600fc | 298 | u8 cmd_queue; |
b04db9ac | 299 | u8 cmd_fifo; |
d663ee73 JB |
300 | u8 n_no_reclaim_cmds; |
301 | u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; | |
b2cf410c JB |
302 | |
303 | bool rx_buf_size_8k; | |
046db346 | 304 | bool bc_table_dword; |
b2cf410c | 305 | u32 rx_page_order; |
7c5ba4a8 | 306 | |
d9fb6465 | 307 | const char **command_names; |
7c5ba4a8 JB |
308 | |
309 | /* queue watchdog */ | |
310 | unsigned long wd_timeout; | |
e56b04ef LE |
311 | |
312 | /*protect hw register */ | |
313 | spinlock_t reg_lock; | |
b9439491 | 314 | bool cmd_in_flight; |
e6bb4c9c EG |
315 | }; |
316 | ||
5a878bf6 EG |
317 | #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \ |
318 | ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific)) | |
319 | ||
7c5ba4a8 JB |
320 | static inline struct iwl_trans * |
321 | iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) | |
322 | { | |
323 | return container_of((void *)trans_pcie, struct iwl_trans, | |
324 | trans_specific); | |
325 | } | |
326 | ||
f02831be EG |
327 | /* |
328 | * Convention: trans API functions: iwl_trans_pcie_XXX | |
329 | * Other functions: iwl_pcie_XXX | |
330 | */ | |
d1ff5253 JB |
331 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
332 | const struct pci_device_id *ent, | |
333 | const struct iwl_cfg *cfg); | |
334 | void iwl_trans_pcie_free(struct iwl_trans *trans); | |
335 | ||
253a634c EG |
336 | /***************************************************** |
337 | * RX | |
338 | ******************************************************/ | |
9805c446 | 339 | int iwl_pcie_rx_init(struct iwl_trans *trans); |
2bfb5092 | 340 | irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); |
9805c446 EG |
341 | int iwl_pcie_rx_stop(struct iwl_trans *trans); |
342 | void iwl_pcie_rx_free(struct iwl_trans *trans); | |
ab697a9f | 343 | |
1a361cd8 | 344 | /***************************************************** |
990aa6d7 | 345 | * ICT - interrupt handling |
1a361cd8 | 346 | ******************************************************/ |
85bf9da1 | 347 | irqreturn_t iwl_pcie_isr(int irq, void *data); |
990aa6d7 EG |
348 | int iwl_pcie_alloc_ict(struct iwl_trans *trans); |
349 | void iwl_pcie_free_ict(struct iwl_trans *trans); | |
350 | void iwl_pcie_reset_ict(struct iwl_trans *trans); | |
351 | void iwl_pcie_disable_ict(struct iwl_trans *trans); | |
1a361cd8 | 352 | |
253a634c EG |
353 | /***************************************************** |
354 | * TX / HCMD | |
355 | ******************************************************/ | |
f02831be EG |
356 | int iwl_pcie_tx_init(struct iwl_trans *trans); |
357 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); | |
358 | int iwl_pcie_tx_stop(struct iwl_trans *trans); | |
359 | void iwl_pcie_tx_free(struct iwl_trans *trans); | |
360 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, | |
361 | int sta_id, int tid, int frame_limit, u16 ssn); | |
362 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue); | |
363 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, | |
364 | struct iwl_device_cmd *dev_cmd, int txq_id); | |
990aa6d7 | 365 | void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq); |
f02831be | 366 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); |
990aa6d7 EG |
367 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
368 | struct iwl_rx_cmd_buffer *rxb, int handler_status); | |
f02831be EG |
369 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
370 | struct sk_buff_head *skbs); | |
ddaf5a5b JB |
371 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); |
372 | ||
7ff94706 EG |
373 | /***************************************************** |
374 | * Error handling | |
375 | ******************************************************/ | |
990aa6d7 | 376 | void iwl_pcie_dump_csr(struct iwl_trans *trans); |
16db88ba | 377 | |
8ad71bef EG |
378 | /***************************************************** |
379 | * Helpers | |
380 | ******************************************************/ | |
0c325769 EG |
381 | static inline void iwl_disable_interrupts(struct iwl_trans *trans) |
382 | { | |
eb7ff77e | 383 | clear_bit(STATUS_INT_ENABLED, &trans->status); |
0c325769 EG |
384 | |
385 | /* disable interrupts from uCode/NIC to host */ | |
1042db2a | 386 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); |
0c325769 EG |
387 | |
388 | /* acknowledge/clear/reset any interrupts still pending | |
389 | * from uCode or flow handler (Rx/Tx DMA) */ | |
1042db2a EG |
390 | iwl_write32(trans, CSR_INT, 0xffffffff); |
391 | iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); | |
0c325769 EG |
392 | IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); |
393 | } | |
394 | ||
395 | static inline void iwl_enable_interrupts(struct iwl_trans *trans) | |
396 | { | |
83626404 | 397 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
0c325769 EG |
398 | |
399 | IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); | |
eb7ff77e | 400 | set_bit(STATUS_INT_ENABLED, &trans->status); |
2dbc368d | 401 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1042db2a | 402 | iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); |
0c325769 EG |
403 | } |
404 | ||
8722c899 SG |
405 | static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) |
406 | { | |
2dbc368d EG |
407 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
408 | ||
8722c899 | 409 | IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); |
2dbc368d EG |
410 | trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; |
411 | iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); | |
8722c899 SG |
412 | } |
413 | ||
e20d4341 | 414 | static inline void iwl_wake_queue(struct iwl_trans *trans, |
990aa6d7 | 415 | struct iwl_txq *txq) |
e20d4341 | 416 | { |
9eae88fa JB |
417 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
418 | ||
419 | if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) { | |
420 | IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id); | |
421 | iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id); | |
81a3de1c | 422 | } |
e20d4341 EG |
423 | } |
424 | ||
425 | static inline void iwl_stop_queue(struct iwl_trans *trans, | |
990aa6d7 | 426 | struct iwl_txq *txq) |
e20d4341 | 427 | { |
9eae88fa | 428 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 429 | |
9eae88fa JB |
430 | if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) { |
431 | iwl_op_mode_queue_full(trans->op_mode, txq->q.id); | |
432 | IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id); | |
433 | } else | |
434 | IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", | |
435 | txq->q.id); | |
8ad71bef EG |
436 | } |
437 | ||
6ca6ebc1 | 438 | static inline bool iwl_queue_used(const struct iwl_queue *q, int i) |
8ad71bef EG |
439 | { |
440 | return q->write_ptr >= q->read_ptr ? | |
441 | (i >= q->read_ptr && i < q->write_ptr) : | |
442 | !(i < q->read_ptr && i >= q->write_ptr); | |
443 | } | |
444 | ||
445 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index) | |
446 | { | |
447 | return index & (q->n_window - 1); | |
448 | } | |
449 | ||
990aa6d7 EG |
450 | static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie, |
451 | u8 cmd) | |
d9fb6465 JB |
452 | { |
453 | if (!trans_pcie->command_names || !trans_pcie->command_names[cmd]) | |
454 | return "UNKNOWN"; | |
455 | return trans_pcie->command_names[cmd]; | |
456 | } | |
457 | ||
8d425517 EG |
458 | static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) |
459 | { | |
460 | return !(iwl_read32(trans, CSR_GP_CNTRL) & | |
461 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
462 | } | |
463 | ||
b9439491 EG |
464 | static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, |
465 | u32 reg, u32 mask, u32 value) | |
466 | { | |
467 | u32 v; | |
468 | ||
469 | #ifdef CONFIG_IWLWIFI_DEBUG | |
470 | WARN_ON_ONCE(value & ~mask); | |
471 | #endif | |
472 | ||
473 | v = iwl_read32(trans, reg); | |
474 | v &= ~mask; | |
475 | v |= value; | |
476 | iwl_write32(trans, reg, v); | |
477 | } | |
478 | ||
479 | static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, | |
480 | u32 reg, u32 mask) | |
481 | { | |
482 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); | |
483 | } | |
484 | ||
485 | static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, | |
486 | u32 reg, u32 mask) | |
487 | { | |
488 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); | |
489 | } | |
490 | ||
ab697a9f | 491 | #endif /* __iwl_trans_int_pcie_h__ */ |