[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / pcie / internal.h

/******************************************************************************
 *
 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/
#ifndef __iwl_trans_int_pcie_h__
#define __iwl_trans_int_pcie_h__

#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/skbuff.h>
#include <linux/wait.h>
#include <linux/pci.h>
#include <linux/timer.h>

#include "iwl-fh.h"
#include "iwl-csr.h"
#include "iwl-trans.h"
#include "iwl-debug.h"
#include "iwl-io.h"
#include "iwl-op-mode.h"

struct iwl_host_cmd;

/*This file includes the declaration that are internal to the
 * trans_pcie layer */

struct iwl_rx_mem_buffer {
	dma_addr_t page_dma;
	struct page *page;
	struct list_head list;
};

/**
 * struct isr_statistics - interrupt statistics
 *
 */
struct isr_statistics {
	u32 hw;
	u32 sw;
	u32 err_code;
	u32 sch;
	u32 alive;
	u32 rfkill;
	u32 ctkill;
	u32 wakeup;
	u32 rx;
	u32 tx;
	u32 unhandled;
};

/**
 * struct iwl_rxq - Rx queue
 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
 * @pool:
 * @queue:
 * @read: Shared index to newest available Rx buffer
 * @write: Shared index to oldest written Rx packet
 * @free_count: Number of pre-allocated buffers in rx_free
 * @write_actual:
 * @rx_free: list of free SKBs for use
 * @rx_used: List of Rx buffers with no SKB
 * @need_update: flag to indicate we need to update read/write index
 * @rb_stts: driver's pointer to receive buffer status
 * @rb_stts_dma: bus address of receive buffer status
 * @lock:
 *
 * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
 */
struct iwl_rxq {
	__le32 *bd;
	dma_addr_t bd_dma;
	struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
	u32 read;
	u32 write;
	u32 free_count;
	u32 write_actual;
	struct list_head rx_free;
	struct list_head rx_used;
	int need_update;
	struct iwl_rb_status *rb_stts;
	dma_addr_t rb_stts_dma;
	spinlock_t lock;
};

struct iwl_dma_ptr {
	dma_addr_t dma;
	void *addr;
	size_t size;
};

/**
 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
 * @index -- current index
 * @n_bd -- total number of entries in queue (must be power of 2)
 */
static inline int iwl_queue_inc_wrap(int index, int n_bd)
{
	return ++index & (n_bd - 1);
}

/**
 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
 * @index -- current index
 * @n_bd -- total number of entries in queue (must be power of 2)
 */
static inline int iwl_queue_dec_wrap(int index, int n_bd)
{
	return --index & (n_bd - 1);
}

struct iwl_cmd_meta {
	/* only for SYNC commands, iff the reply skb is wanted */
	struct iwl_host_cmd *source;
	u32 flags;
};

/*
 * Generic queue structure
 *
 * Contains common data for Rx and Tx queues.
 *
 * Note the difference between n_bd and n_window: the hardware
 * always assumes 256 descriptors, so n_bd is always 256 (unless
 * there might be HW changes in the future). For the normal TX
 * queues, n_window, which is the size of the software queue data
 * is also 256; however, for the command queue, n_window is only
 * 32 since we don't need so many commands pending. Since the HW
 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
 * the software buffers (in the variables @meta, @txb in struct
 * iwl_txq) only have 32 entries, while the HW buffers (@tfds in
 * the same struct) have 256.
 * This means that we end up with the following:
 *  HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
 *  SW entries:           | 0      | ... | 31          |
 * where N is a number between 0 and 7. This means that the SW
 * data is a window overlayed over the HW queue.
 */
struct iwl_queue {
	int n_bd;              /* number of BDs in this queue */
	int write_ptr;       /* 1-st empty entry (index) host_w*/
	int read_ptr;         /* last used entry (index) host_r*/
	/* use for monitoring and recovering the stuck queue */
	dma_addr_t dma_addr;   /* physical addr for BD's */
	int n_window;	       /* safe queue window */
	u32 id;
	int low_mark;	       /* low watermark, resume queue if free
				* space more than this */
	int high_mark;         /* high watermark, stop queue if free
				* space less than this */
};

#define TFD_TX_CMD_SLOTS 256
#define TFD_CMD_SLOTS 32

/*
 * The FH will write back to the first TB only, so we need
 * to copy some data into the buffer regardless of whether
 * it should be mapped or not. This indicates how big the
 * first TB must be to include the scratch buffer. Since
 * the scratch is 4 bytes at offset 12, it's 16 now. If we
 * make it bigger then allocations will be bigger and copy
 * slower, so that's probably not useful.
 */
#define IWL_HCMD_SCRATCHBUF_SIZE	16

struct iwl_pcie_txq_entry {
	struct iwl_device_cmd *cmd;
	struct sk_buff *skb;
	/* buffer to free after command completes */
	const void *free_buf;
	struct iwl_cmd_meta meta;
};

struct iwl_pcie_txq_scratch_buf {
	struct iwl_cmd_header hdr;
	u8 buf[8];
	__le32 scratch;
};

/**
 * struct iwl_txq - Tx Queue for DMA
 * @q: generic Rx/Tx queue descriptor
 * @tfds: transmit frame descriptors (DMA memory)
 * @scratchbufs: start of command headers, including scratch buffers, for
 *	the writeback -- this is DMA memory and an array holding one buffer
 *	for each command on the queue
 * @scratchbufs_dma: DMA address for the scratchbufs start
 * @entries: transmit entries (driver state)
 * @lock: queue lock
 * @stuck_timer: timer that fires if queue gets stuck
 * @trans_pcie: pointer back to transport (for timer)
 * @need_update: indicates need to update read/write index
 * @active: stores if queue is active
 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
 *
 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
 * descriptors) and required locking structures.
 */
struct iwl_txq {
	struct iwl_queue q;
	struct iwl_tfd *tfds;
	struct iwl_pcie_txq_scratch_buf *scratchbufs;
	dma_addr_t scratchbufs_dma;
	struct iwl_pcie_txq_entry *entries;
	spinlock_t lock;
	struct timer_list stuck_timer;
	struct iwl_trans_pcie *trans_pcie;
	u8 need_update;
	u8 active;
	bool ampdu;
};

static inline dma_addr_t
iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
{
	return txq->scratchbufs_dma +
	       sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
}

/**
 * struct iwl_trans_pcie - PCIe transport specific data
 * @rxq: all the RX queue data
 * @rx_replenish: work that will be called when buffers need to be allocated
 * @drv - pointer to iwl_drv
 * @trans: pointer to the generic transport area
 * @scd_base_addr: scheduler sram base address in SRAM
 * @scd_bc_tbls: pointer to the byte count table of the scheduler
 * @kw: keep warm address
 * @pci_dev: basic pci-network driver stuff
 * @hw_base: pci hardware address support
 * @ucode_write_complete: indicates that the ucode has been copied.
 * @ucode_write_waitq: wait queue for uCode load
 * @status - transport specific status flags
 * @cmd_queue - command queue number
 * @rx_buf_size_8k: 8 kB RX buffer size
 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
 * @rx_page_order: page order for receive buffer size
 * @wd_timeout: queue watchdog timeout (jiffies)
 * @reg_lock: protect hw register access
 */
struct iwl_trans_pcie {
	struct iwl_rxq rxq;
	struct work_struct rx_replenish;
	struct iwl_trans *trans;
	struct iwl_drv *drv;

	/* INT ICT Table */
	__le32 *ict_tbl;
	dma_addr_t ict_tbl_dma;
	int ict_index;
	u32 inta;
	bool use_ict;
	struct isr_statistics isr_stats;

	spinlock_t irq_lock;
	u32 inta_mask;
	u32 scd_base_addr;
	struct iwl_dma_ptr scd_bc_tbls;
	struct iwl_dma_ptr kw;

	struct iwl_txq *txq;
	unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
	unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];

	/* PCI bus related data */
	struct pci_dev *pci_dev;
	void __iomem *hw_base;

	bool ucode_write_complete;
	wait_queue_head_t ucode_write_waitq;
	wait_queue_head_t wait_command_queue;

	unsigned long status;
	u8 cmd_queue;
	u8 cmd_fifo;
	u8 n_no_reclaim_cmds;
	u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];

	bool rx_buf_size_8k;
	bool bc_table_dword;
	u32 rx_page_order;

	const char **command_names;

	/* queue watchdog */
	unsigned long wd_timeout;

	/*protect hw register */
	spinlock_t reg_lock;
};

/**
 * enum iwl_pcie_status: status of the PCIe transport
 * @STATUS_HCMD_ACTIVE: a SYNC command is being processed
 * @STATUS_DEVICE_ENABLED: APM is enabled
 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
 * @STATUS_INT_ENABLED: interrupts are enabled
 * @STATUS_RFKILL: the HW RFkill switch is in KILL position
 * @STATUS_FW_ERROR: the fw is in error state
 */
enum iwl_pcie_status {
	STATUS_HCMD_ACTIVE,
	STATUS_DEVICE_ENABLED,
	STATUS_TPOWER_PMI,
	STATUS_INT_ENABLED,
	STATUS_RFKILL,
	STATUS_FW_ERROR,
};

#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
	((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))

static inline struct iwl_trans *
iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
{
	return container_of((void *)trans_pcie, struct iwl_trans,
			    trans_specific);
}

/*
 * Convention: trans API functions: iwl_trans_pcie_XXX
 *	Other functions: iwl_pcie_XXX
 */
struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
				       const struct pci_device_id *ent,
				       const struct iwl_cfg *cfg);
void iwl_trans_pcie_free(struct iwl_trans *trans);

/*****************************************************
* RX
******************************************************/
int iwl_pcie_rx_init(struct iwl_trans *trans);
irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
int iwl_pcie_rx_stop(struct iwl_trans *trans);
void iwl_pcie_rx_free(struct iwl_trans *trans);

/*****************************************************
* ICT - interrupt handling
******************************************************/
irqreturn_t iwl_pcie_isr_ict(int irq, void *data);
int iwl_pcie_alloc_ict(struct iwl_trans *trans);
void iwl_pcie_free_ict(struct iwl_trans *trans);
void iwl_pcie_reset_ict(struct iwl_trans *trans);
void iwl_pcie_disable_ict(struct iwl_trans *trans);

/*****************************************************
* TX / HCMD
******************************************************/
int iwl_pcie_tx_init(struct iwl_trans *trans);
void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
int iwl_pcie_tx_stop(struct iwl_trans *trans);
void iwl_pcie_tx_free(struct iwl_trans *trans);
void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
			       int sta_id, int tid, int frame_limit, u16 ssn);
void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
		      struct iwl_device_cmd *dev_cmd, int txq_id);
void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq);
int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
			    struct iwl_rx_cmd_buffer *rxb, int handler_status);
void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
			    struct sk_buff_head *skbs);
void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);

/*****************************************************
* Error handling
******************************************************/
void iwl_pcie_dump_csr(struct iwl_trans *trans);

/*****************************************************
* Helpers
******************************************************/
static inline void iwl_disable_interrupts(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);

	/* disable interrupts from uCode/NIC to host */
	iwl_write32(trans, CSR_INT_MASK, 0x00000000);

	/* acknowledge/clear/reset any interrupts still pending
	 * from uCode or flow handler (Rx/Tx DMA) */
	iwl_write32(trans, CSR_INT, 0xffffffff);
	iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
	IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
}

static inline void iwl_enable_interrupts(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
	set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
	iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
}

static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
{
	IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
	iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
}

static inline void iwl_wake_queue(struct iwl_trans *trans,
				  struct iwl_txq *txq)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
		IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
		iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
	}
}

static inline void iwl_stop_queue(struct iwl_trans *trans,
				  struct iwl_txq *txq)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
		iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
		IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
	} else
		IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
				    txq->q.id);
}

static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
{
	return q->write_ptr >= q->read_ptr ?
		(i >= q->read_ptr && i < q->write_ptr) :
		!(i < q->read_ptr && i >= q->write_ptr);
}

static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
{
	return index & (q->n_window - 1);
}

static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie,
					 u8 cmd)
{
	if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
		return "UNKNOWN";
	return trans_pcie->command_names[cmd];
}

static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
{
	return !(iwl_read32(trans, CSR_GP_CNTRL) &
		CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
}

static inline void iwl_nic_error(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	set_bit(STATUS_FW_ERROR, &trans_pcie->status);
	iwl_op_mode_nic_error(trans->op_mode);
}

#endif /* __iwl_trans_int_pcie_h__ */
Commit	Line	Data
ab697a9f EG	1	/******************************************************************************
ab697a9f EG	2	*
128e63ef	3	* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
ab697a9f EG	4	*
	5	* Portions of this file are derived from the ipw3945 project, as well
	6	* as portions of the ieee80211 subsystem header files.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of version 2 of the GNU General Public License as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	20	*
	21	* The full GNU General Public License is included in this distribution in the
	22	* file called LICENSE.
	23	*
	24	* Contact Information:
	25	* Intel Linux Wireless <ilw@linux.intel.com>
	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*
	28	*****************************************************************************/
	29	#ifndef __iwl_trans_int_pcie_h__
	30	#define __iwl_trans_int_pcie_h__
	31
a72b8b08 EG	32	#include <linux/spinlock.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/skbuff.h>
13df1aab	35	#include <linux/wait.h>
522376d2	36	#include <linux/pci.h>
7c5ba4a8	37	#include <linux/timer.h>
a72b8b08	38
dda61a44	39	#include "iwl-fh.h"
a72b8b08	40	#include "iwl-csr.h"
a72b8b08 EG	41	#include "iwl-trans.h"
	42	#include "iwl-debug.h"
	43	#include "iwl-io.h"
02e38358	44	#include "iwl-op-mode.h"
a72b8b08	45
a72b8b08	46	struct iwl_host_cmd;
dda61a44	47
ab697a9f EG	48	/*This file includes the declaration that are internal to the
	49	* trans_pcie layer */
	50
48a2d66f JB	51	struct iwl_rx_mem_buffer {
	52	dma_addr_t page_dma;
	53	struct page *page;
	54	struct list_head list;
	55	};
	56
1f7b6172 EG	57	/**
	58	* struct isr_statistics - interrupt statistics
	59	*
	60	*/
	61	struct isr_statistics {
	62	u32 hw;
	63	u32 sw;
	64	u32 err_code;
	65	u32 sch;
	66	u32 alive;
	67	u32 rfkill;
	68	u32 ctkill;
	69	u32 wakeup;
	70	u32 rx;
	71	u32 tx;
	72	u32 unhandled;
	73	};
	74
5a878bf6	75	/**
990aa6d7	76	* struct iwl_rxq - Rx queue
5a878bf6 EG	77	* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
	78	* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
	79	* @pool:
	80	* @queue:
	81	* @read: Shared index to newest available Rx buffer
	82	* @write: Shared index to oldest written Rx packet
	83	* @free_count: Number of pre-allocated buffers in rx_free
	84	* @write_actual:
	85	* @rx_free: list of free SKBs for use
	86	* @rx_used: List of Rx buffers with no SKB
	87	* @need_update: flag to indicate we need to update read/write index
	88	* @rb_stts: driver's pointer to receive buffer status
	89	* @rb_stts_dma: bus address of receive buffer status
	90	* @lock:
	91	*
	92	* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
	93	*/
990aa6d7	94	struct iwl_rxq {
5a878bf6 EG	95	__le32 *bd;
	96	dma_addr_t bd_dma;
	97	struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
	98	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
	99	u32 read;
	100	u32 write;
	101	u32 free_count;
	102	u32 write_actual;
	103	struct list_head rx_free;
	104	struct list_head rx_used;
	105	int need_update;
	106	struct iwl_rb_status *rb_stts;
	107	dma_addr_t rb_stts_dma;
	108	spinlock_t lock;
	109	};
	110
a72b8b08 EG	111	struct iwl_dma_ptr {
	112	dma_addr_t dma;
	113	void *addr;
	114	size_t size;
	115	};
	116
bffc66ce JB	117	/**
	118	* iwl_queue_inc_wrap - increment queue index, wrap back to beginning
	119	* @index -- current index
	120	* @n_bd -- total number of entries in queue (must be power of 2)
	121	*/
	122	static inline int iwl_queue_inc_wrap(int index, int n_bd)
	123	{
	124	return ++index & (n_bd - 1);
	125	}
	126
	127	/**
	128	* iwl_queue_dec_wrap - decrement queue index, wrap back to end
	129	* @index -- current index
	130	* @n_bd -- total number of entries in queue (must be power of 2)
	131	*/
	132	static inline int iwl_queue_dec_wrap(int index, int n_bd)
	133	{
	134	return --index & (n_bd - 1);
	135	}
	136
522376d2 EG	137	struct iwl_cmd_meta {
	138	/* only for SYNC commands, iff the reply skb is wanted */
	139	struct iwl_host_cmd *source;
c14c7372	140	u32 flags;
522376d2 EG	141	};
	142
	143	/*
	144	* Generic queue structure
	145	*
	146	* Contains common data for Rx and Tx queues.
	147	*
	148	* Note the difference between n_bd and n_window: the hardware
	149	* always assumes 256 descriptors, so n_bd is always 256 (unless
	150	* there might be HW changes in the future). For the normal TX
	151	* queues, n_window, which is the size of the software queue data
	152	* is also 256; however, for the command queue, n_window is only
	153	* 32 since we don't need so many commands pending. Since the HW
	154	* still uses 256 BDs for DMA though, n_bd stays 256. As a result,
	155	* the software buffers (in the variables @meta, @txb in struct
990aa6d7 EG	156	* iwl_txq) only have 32 entries, while the HW buffers (@tfds in
990aa6d7 EG	157	* the same struct) have 256.
522376d2 EG	158	* This means that we end up with the following:
	159	* HW entries: \| 0 \| ... \| N * 32 \| ... \| N * 32 + 31 \| ... \| 255 \|
	160	* SW entries: \| 0 \| ... \| 31 \|
	161	* where N is a number between 0 and 7. This means that the SW
	162	* data is a window overlayed over the HW queue.
	163	*/
	164	struct iwl_queue {
	165	int n_bd; /* number of BDs in this queue */
	166	int write_ptr; /* 1-st empty entry (index) host_w*/
	167	int read_ptr; /* last used entry (index) host_r*/
	168	/* use for monitoring and recovering the stuck queue */
	169	dma_addr_t dma_addr; /* physical addr for BD's */
	170	int n_window; /* safe queue window */
	171	u32 id;
	172	int low_mark; /* low watermark, resume queue if free
	173	* space more than this */
	174	int high_mark; /* high watermark, stop queue if free
	175	* space less than this */
	176	};
	177
bf8440e6 JB	178	#define TFD_TX_CMD_SLOTS 256
	179	#define TFD_CMD_SLOTS 32
	180
8a964f44 JB	181	/*
	182	* The FH will write back to the first TB only, so we need
	183	* to copy some data into the buffer regardless of whether
38c0f334 JB	184	* it should be mapped or not. This indicates how big the
	185	* first TB must be to include the scratch buffer. Since
	186	* the scratch is 4 bytes at offset 12, it's 16 now. If we
	187	* make it bigger then allocations will be bigger and copy
	188	* slower, so that's probably not useful.
8a964f44	189	*/
38c0f334	190	#define IWL_HCMD_SCRATCHBUF_SIZE 16
8a964f44	191
990aa6d7	192	struct iwl_pcie_txq_entry {
bf8440e6 JB	193	struct iwl_device_cmd *cmd;
bf8440e6 JB	194	struct sk_buff *skb;
f4feb8ac JB	195	/* buffer to free after command completes */
f4feb8ac JB	196	const void *free_buf;
bf8440e6 JB	197	struct iwl_cmd_meta meta;
	198	};
	199
38c0f334 JB	200	struct iwl_pcie_txq_scratch_buf {
	201	struct iwl_cmd_header hdr;
	202	u8 buf[8];
	203	__le32 scratch;
	204	};
	205
522376d2	206	/**
990aa6d7	207	* struct iwl_txq - Tx Queue for DMA
522376d2	208	* @q: generic Rx/Tx queue descriptor
bf8440e6	209	* @tfds: transmit frame descriptors (DMA memory)
38c0f334 JB	210	* @scratchbufs: start of command headers, including scratch buffers, for
	211	* the writeback -- this is DMA memory and an array holding one buffer
	212	* for each command on the queue
	213	* @scratchbufs_dma: DMA address for the scratchbufs start
bf8440e6 JB	214	* @entries: transmit entries (driver state)
	215	* @lock: queue lock
	216	* @stuck_timer: timer that fires if queue gets stuck
	217	* @trans_pcie: pointer back to transport (for timer)
522376d2	218	* @need_update: indicates need to update read/write index
bf8440e6	219	* @active: stores if queue is active
68972c46	220	* @ampdu: true if this queue is an ampdu queue for an specific RA/TID
522376d2 EG	221	*
	222	* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
	223	* descriptors) and required locking structures.
	224	*/
990aa6d7	225	struct iwl_txq {
522376d2 EG	226	struct iwl_queue q;
522376d2 EG	227	struct iwl_tfd *tfds;
38c0f334 JB	228	struct iwl_pcie_txq_scratch_buf *scratchbufs;
38c0f334 JB	229	dma_addr_t scratchbufs_dma;
990aa6d7	230	struct iwl_pcie_txq_entry *entries;
015c15e1	231	spinlock_t lock;
7c5ba4a8 JB	232	struct timer_list stuck_timer;
7c5ba4a8 JB	233	struct iwl_trans_pcie *trans_pcie;
522376d2	234	u8 need_update;
522376d2	235	u8 active;
68972c46	236	bool ampdu;
522376d2 EG	237	};
522376d2 EG	238
38c0f334 JB	239	static inline dma_addr_t
	240	iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
	241	{
	242	return txq->scratchbufs_dma +
	243	sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
	244	}
	245
e6bb4c9c EG	246	/**
e6bb4c9c EG	247	* struct iwl_trans_pcie - PCIe transport specific data
5a878bf6 EG	248	* @rxq: all the RX queue data
5a878bf6 EG	249	* @rx_replenish: work that will be called when buffers need to be allocated
9130bab1	250	* @drv - pointer to iwl_drv
5a878bf6	251	* @trans: pointer to the generic transport area
105183b1 EG	252	* @scd_base_addr: scheduler sram base address in SRAM
105183b1 EG	253	* @scd_bc_tbls: pointer to the byte count table of the scheduler
9d6b2cb1	254	* @kw: keep warm address
a42a1844 EG	255	* @pci_dev: basic pci-network driver stuff
a42a1844 EG	256	* @hw_base: pci hardware address support
13df1aab JB	257	* @ucode_write_complete: indicates that the ucode has been copied.
13df1aab JB	258	* @ucode_write_waitq: wait queue for uCode load
9a716863	259	* @status - transport specific status flags
c6f600fc	260	* @cmd_queue - command queue number
b2cf410c	261	* @rx_buf_size_8k: 8 kB RX buffer size
046db346	262	* @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
b2cf410c	263	* @rx_page_order: page order for receive buffer size
7c5ba4a8	264	* @wd_timeout: queue watchdog timeout (jiffies)
e56b04ef	265	* @reg_lock: protect hw register access
e6bb4c9c EG	266	*/
e6bb4c9c EG	267	struct iwl_trans_pcie {
990aa6d7	268	struct iwl_rxq rxq;
5a878bf6 EG	269	struct work_struct rx_replenish;
5a878bf6 EG	270	struct iwl_trans *trans;
9130bab1	271	struct iwl_drv *drv;
0c325769 EG	272
	273	/* INT ICT Table */
	274	__le32 *ict_tbl;
0c325769	275	dma_addr_t ict_tbl_dma;
0c325769 EG	276	int ict_index;
	277	u32 inta;
	278	bool use_ict;
1f7b6172	279	struct isr_statistics isr_stats;
0c325769	280
7b11488f	281	spinlock_t irq_lock;
0c325769	282	u32 inta_mask;
105183b1 EG	283	u32 scd_base_addr;
105183b1 EG	284	struct iwl_dma_ptr scd_bc_tbls;
9d6b2cb1	285	struct iwl_dma_ptr kw;
e13c0c59	286
990aa6d7	287	struct iwl_txq *txq;
9eae88fa	288	unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
8ad71bef	289	unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
a42a1844 EG	290
	291	/* PCI bus related data */
	292	struct pci_dev *pci_dev;
	293	void __iomem *hw_base;
13df1aab JB	294
	295	bool ucode_write_complete;
	296	wait_queue_head_t ucode_write_waitq;
f946b529 EG	297	wait_queue_head_t wait_command_queue;
f946b529 EG	298
9a716863	299	unsigned long status;
c6f600fc	300	u8 cmd_queue;
b04db9ac	301	u8 cmd_fifo;
d663ee73 JB	302	u8 n_no_reclaim_cmds;
d663ee73 JB	303	u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
b2cf410c JB	304
b2cf410c JB	305	bool rx_buf_size_8k;
046db346	306	bool bc_table_dword;
b2cf410c	307	u32 rx_page_order;
7c5ba4a8	308
d9fb6465	309	const char **command_names;
7c5ba4a8 JB	310
	311	/* queue watchdog */
	312	unsigned long wd_timeout;
e56b04ef LE	313
	314	/protect hw register /
	315	spinlock_t reg_lock;
e6bb4c9c EG	316	};
e6bb4c9c EG	317
b55e57f5 EG	318	/**
	319	* enum iwl_pcie_status: status of the PCIe transport
	320	* @STATUS_HCMD_ACTIVE: a SYNC command is being processed
	321	* @STATUS_DEVICE_ENABLED: APM is enabled
	322	* @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
	323	* @STATUS_INT_ENABLED: interrupts are enabled
	324	* @STATUS_RFKILL: the HW RFkill switch is in KILL position
	325	* @STATUS_FW_ERROR: the fw is in error state
	326	*/
	327	enum iwl_pcie_status {
f946b529 EG	328	STATUS_HCMD_ACTIVE,
	329	STATUS_DEVICE_ENABLED,
	330	STATUS_TPOWER_PMI,
	331	STATUS_INT_ENABLED,
	332	STATUS_RFKILL,
d18aa87f	333	STATUS_FW_ERROR,
f946b529	334	};
01d651d4	335
5a878bf6 EG	336	#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
	337	((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
	338
7c5ba4a8 JB	339	static inline struct iwl_trans *
	340	iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
	341	{
	342	return container_of((void *)trans_pcie, struct iwl_trans,
	343	trans_specific);
	344	}
	345
f02831be EG	346	/*
	347	* Convention: trans API functions: iwl_trans_pcie_XXX
	348	* Other functions: iwl_pcie_XXX
	349	*/
d1ff5253 JB	350	struct iwl_trans iwl_trans_pcie_alloc(struct pci_dev pdev,
	351	const struct pci_device_id *ent,
	352	const struct iwl_cfg *cfg);
	353	void iwl_trans_pcie_free(struct iwl_trans *trans);
	354
253a634c EG	355	/*****************************************************
	356	* RX
	357	******************************************************/
9805c446	358	int iwl_pcie_rx_init(struct iwl_trans *trans);
2bfb5092	359	irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
9805c446 EG	360	int iwl_pcie_rx_stop(struct iwl_trans *trans);
9805c446 EG	361	void iwl_pcie_rx_free(struct iwl_trans *trans);
ab697a9f	362
1a361cd8	363	/*****************************************************
990aa6d7	364	* ICT - interrupt handling
1a361cd8	365	******************************************************/
990aa6d7 EG	366	irqreturn_t iwl_pcie_isr_ict(int irq, void *data);
	367	int iwl_pcie_alloc_ict(struct iwl_trans *trans);
	368	void iwl_pcie_free_ict(struct iwl_trans *trans);
	369	void iwl_pcie_reset_ict(struct iwl_trans *trans);
	370	void iwl_pcie_disable_ict(struct iwl_trans *trans);
1a361cd8	371
253a634c EG	372	/*****************************************************
	373	* TX / HCMD
	374	******************************************************/
f02831be EG	375	int iwl_pcie_tx_init(struct iwl_trans *trans);
	376	void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
	377	int iwl_pcie_tx_stop(struct iwl_trans *trans);
	378	void iwl_pcie_tx_free(struct iwl_trans *trans);
	379	void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
	380	int sta_id, int tid, int frame_limit, u16 ssn);
	381	void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
	382	int iwl_trans_pcie_tx(struct iwl_trans trans, struct sk_buff skb,
	383	struct iwl_device_cmd *dev_cmd, int txq_id);
990aa6d7	384	void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans trans, struct iwl_txq txq);
f02831be	385	int iwl_trans_pcie_send_hcmd(struct iwl_trans trans, struct iwl_host_cmd cmd);
990aa6d7 EG	386	void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
990aa6d7 EG	387	struct iwl_rx_cmd_buffer *rxb, int handler_status);
f02831be EG	388	void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
f02831be EG	389	struct sk_buff_head *skbs);
ddaf5a5b JB	390	void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
ddaf5a5b JB	391
7ff94706 EG	392	/*****************************************************
	393	* Error handling
	394	******************************************************/
990aa6d7	395	void iwl_pcie_dump_csr(struct iwl_trans *trans);
16db88ba	396
8ad71bef EG	397	/*****************************************************
	398	* Helpers
	399	******************************************************/
0c325769 EG	400	static inline void iwl_disable_interrupts(struct iwl_trans *trans)
0c325769 EG	401	{
83626404 DF	402	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
83626404 DF	403	clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
0c325769 EG	404
0c325769 EG	405	/* disable interrupts from uCode/NIC to host */
1042db2a	406	iwl_write32(trans, CSR_INT_MASK, 0x00000000);
0c325769 EG	407
	408	/* acknowledge/clear/reset any interrupts still pending
	409	* from uCode or flow handler (Rx/Tx DMA) */
1042db2a EG	410	iwl_write32(trans, CSR_INT, 0xffffffff);
1042db2a EG	411	iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
0c325769 EG	412	IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
	413	}
	414
	415	static inline void iwl_enable_interrupts(struct iwl_trans *trans)
	416	{
83626404	417	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
0c325769 EG	418
0c325769 EG	419	IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
83626404	420	set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1042db2a	421	iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
0c325769 EG	422	}
0c325769 EG	423
8722c899 SG	424	static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
	425	{
	426	IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
	427	iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
	428	}
	429
e20d4341	430	static inline void iwl_wake_queue(struct iwl_trans *trans,
990aa6d7	431	struct iwl_txq *txq)
e20d4341	432	{
9eae88fa JB	433	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	434
	435	if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
	436	IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
	437	iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
81a3de1c	438	}
e20d4341 EG	439	}
	440
	441	static inline void iwl_stop_queue(struct iwl_trans *trans,
990aa6d7	442	struct iwl_txq *txq)
e20d4341	443	{
9eae88fa	444	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
8ad71bef	445
9eae88fa JB	446	if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
	447	iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
	448	IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
	449	} else
	450	IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
	451	txq->q.id);
8ad71bef EG	452	}
8ad71bef EG	453
6ca6ebc1	454	static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
8ad71bef EG	455	{
	456	return q->write_ptr >= q->read_ptr ?
	457	(i >= q->read_ptr && i < q->write_ptr) :
	458	!(i < q->read_ptr && i >= q->write_ptr);
	459	}
	460
	461	static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
	462	{
	463	return index & (q->n_window - 1);
	464	}
	465
990aa6d7 EG	466	static inline const char get_cmd_string(struct iwl_trans_pcie trans_pcie,
990aa6d7 EG	467	u8 cmd)
d9fb6465 JB	468	{
	469	if (!trans_pcie->command_names \|\| !trans_pcie->command_names[cmd])
	470	return "UNKNOWN";
	471	return trans_pcie->command_names[cmd];
	472	}
	473
8d425517 EG	474	static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
	475	{
	476	return !(iwl_read32(trans, CSR_GP_CNTRL) &
	477	CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
	478	}
	479
6860bd15 AB	480	static inline void iwl_nic_error(struct iwl_trans *trans)
	481	{
	482	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	483
	484	set_bit(STATUS_FW_ERROR, &trans_pcie->status);
	485	iwl_op_mode_nic_error(trans->op_mode);
	486	}
	487
ab697a9f	488	#endif /* __iwl_trans_int_pcie_h__ */