Commit | Line | Data |
---|---|---|
8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
8ca151b5 JB |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
8ca151b5 JB |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 35 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
8ca151b5 JB |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
1214755c | 65 | #include <linux/firmware.h> |
90d4f7db | 66 | #include <linux/rtnetlink.h> |
8ca151b5 | 67 | #include "iwl-trans.h" |
c2a2b28b | 68 | #include "iwl-csr.h" |
8ca151b5 JB |
69 | #include "mvm.h" |
70 | #include "iwl-eeprom-parse.h" | |
71 | #include "iwl-eeprom-read.h" | |
72 | #include "iwl-nvm-parse.h" | |
73 | ||
1fd4afe2 | 74 | /* Default NVM size to read */ |
1214755c | 75 | #define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024) |
f251c07c LK |
76 | #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 |
77 | #define IWL_MAX_NVM_8000A_SECTION_SIZE 0xffc | |
78 | #define IWL_MAX_NVM_8000B_SECTION_SIZE 0x1ffc | |
1fd4afe2 | 79 | |
1214755c EH |
80 | #define NVM_WRITE_OPCODE 1 |
81 | #define NVM_READ_OPCODE 0 | |
82 | ||
d6aeb354 EH |
83 | /* load nvm chunk response */ |
84 | enum { | |
85 | READ_NVM_CHUNK_SUCCEED = 0, | |
86 | READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 | |
87 | }; | |
88 | ||
1214755c EH |
89 | /* |
90 | * prepare the NVM host command w/ the pointers to the nvm buffer | |
91 | * and send it to fw | |
92 | */ | |
93 | static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section, | |
94 | u16 offset, u16 length, const u8 *data) | |
8ca151b5 | 95 | { |
1214755c EH |
96 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
97 | .offset = cpu_to_le16(offset), | |
98 | .length = cpu_to_le16(length), | |
99 | .type = cpu_to_le16(section), | |
100 | .op_code = NVM_WRITE_OPCODE, | |
101 | }; | |
102 | struct iwl_host_cmd cmd = { | |
103 | .id = NVM_ACCESS_CMD, | |
104 | .len = { sizeof(struct iwl_nvm_access_cmd), length }, | |
a1022927 | 105 | .flags = CMD_SEND_IN_RFKILL, |
1214755c EH |
106 | .data = { &nvm_access_cmd, data }, |
107 | /* data may come from vmalloc, so use _DUP */ | |
108 | .dataflags = { 0, IWL_HCMD_DFL_DUP }, | |
109 | }; | |
110 | ||
111 | return iwl_mvm_send_cmd(mvm, &cmd); | |
8ca151b5 JB |
112 | } |
113 | ||
114 | static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section, | |
115 | u16 offset, u16 length, u8 *data) | |
116 | { | |
1214755c EH |
117 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
118 | .offset = cpu_to_le16(offset), | |
119 | .length = cpu_to_le16(length), | |
120 | .type = cpu_to_le16(section), | |
121 | .op_code = NVM_READ_OPCODE, | |
122 | }; | |
b9545b48 | 123 | struct iwl_nvm_access_resp *nvm_resp; |
8ca151b5 JB |
124 | struct iwl_rx_packet *pkt; |
125 | struct iwl_host_cmd cmd = { | |
126 | .id = NVM_ACCESS_CMD, | |
a1022927 | 127 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
8ca151b5 JB |
128 | .data = { &nvm_access_cmd, }, |
129 | }; | |
130 | int ret, bytes_read, offset_read; | |
131 | u8 *resp_data; | |
132 | ||
b9545b48 | 133 | cmd.len[0] = sizeof(struct iwl_nvm_access_cmd); |
8ca151b5 JB |
134 | |
135 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
136 | if (ret) | |
137 | return ret; | |
138 | ||
139 | pkt = cmd.resp_pkt; | |
140 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
141 | IWL_ERR(mvm, "Bad return from NVM_ACCES_COMMAND (0x%08X)\n", | |
142 | pkt->hdr.flags); | |
143 | ret = -EIO; | |
144 | goto exit; | |
145 | } | |
146 | ||
147 | /* Extract NVM response */ | |
148 | nvm_resp = (void *)pkt->data; | |
b9545b48 EG |
149 | ret = le16_to_cpu(nvm_resp->status); |
150 | bytes_read = le16_to_cpu(nvm_resp->length); | |
151 | offset_read = le16_to_cpu(nvm_resp->offset); | |
152 | resp_data = nvm_resp->data; | |
8ca151b5 | 153 | if (ret) { |
d6aeb354 EH |
154 | if ((offset != 0) && |
155 | (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { | |
156 | /* | |
157 | * meaning of NOT_VALID_ADDRESS: | |
158 | * driver try to read chunk from address that is | |
159 | * multiple of 2K and got an error since addr is empty. | |
160 | * meaning of (offset != 0): driver already | |
161 | * read valid data from another chunk so this case | |
162 | * is not an error. | |
163 | */ | |
164 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
165 | "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", | |
166 | offset); | |
167 | ret = 0; | |
168 | } else { | |
169 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
170 | "NVM access command failed with status %d (device: %s)\n", | |
171 | ret, mvm->cfg->name); | |
172 | ret = -EIO; | |
173 | } | |
8ca151b5 JB |
174 | goto exit; |
175 | } | |
176 | ||
177 | if (offset_read != offset) { | |
178 | IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n", | |
179 | offset_read); | |
180 | ret = -EINVAL; | |
181 | goto exit; | |
182 | } | |
183 | ||
184 | /* Write data to NVM */ | |
185 | memcpy(data + offset, resp_data, bytes_read); | |
186 | ret = bytes_read; | |
187 | ||
188 | exit: | |
189 | iwl_free_resp(&cmd); | |
190 | return ret; | |
191 | } | |
192 | ||
1214755c EH |
193 | static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section, |
194 | const u8 *data, u16 length) | |
195 | { | |
196 | int offset = 0; | |
197 | ||
198 | /* copy data in chunks of 2k (and remainder if any) */ | |
199 | ||
200 | while (offset < length) { | |
201 | int chunk_size, ret; | |
202 | ||
203 | chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE, | |
204 | length - offset); | |
205 | ||
206 | ret = iwl_nvm_write_chunk(mvm, section, offset, | |
207 | chunk_size, data + offset); | |
208 | if (ret < 0) | |
209 | return ret; | |
210 | ||
211 | offset += chunk_size; | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
8ca151b5 JB |
217 | /* |
218 | * Reads an NVM section completely. | |
219 | * NICs prior to 7000 family doesn't have a real NVM, but just read | |
220 | * section 0 which is the EEPROM. Because the EEPROM reading is unlimited | |
221 | * by uCode, we need to manually check in this case that we don't | |
222 | * overflow and try to read more than the EEPROM size. | |
223 | * For 7000 family NICs, we supply the maximal size we can read, and | |
224 | * the uCode fills the response with as much data as we can, | |
225 | * without overflowing, so no check is needed. | |
226 | */ | |
227 | static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section, | |
5daddc99 | 228 | u8 *data, u32 size_read) |
8ca151b5 JB |
229 | { |
230 | u16 length, offset = 0; | |
231 | int ret; | |
8ca151b5 | 232 | |
1fd4afe2 DS |
233 | /* Set nvm section read length */ |
234 | length = IWL_NVM_DEFAULT_CHUNK_SIZE; | |
235 | ||
8ca151b5 JB |
236 | ret = length; |
237 | ||
238 | /* Read the NVM until exhausted (reading less than requested) */ | |
239 | while (ret == length) { | |
5daddc99 LK |
240 | /* Check no memory assumptions fail and cause an overflow */ |
241 | if ((size_read + offset + length) > | |
242 | mvm->cfg->base_params->eeprom_size) { | |
243 | IWL_ERR(mvm, "EEPROM size is too small for NVM\n"); | |
244 | return -ENOBUFS; | |
245 | } | |
246 | ||
8ca151b5 JB |
247 | ret = iwl_nvm_read_chunk(mvm, section, offset, length, data); |
248 | if (ret < 0) { | |
d6aeb354 EH |
249 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
250 | "Cannot read NVM from section %d offset %d, length %d\n", | |
251 | section, offset, length); | |
8ca151b5 JB |
252 | return ret; |
253 | } | |
254 | offset += ret; | |
8ca151b5 JB |
255 | } |
256 | ||
07fd7d28 JB |
257 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
258 | "NVM section %d read completed\n", section); | |
8ca151b5 JB |
259 | return offset; |
260 | } | |
261 | ||
262 | static struct iwl_nvm_data * | |
263 | iwl_parse_nvm_sections(struct iwl_mvm *mvm) | |
264 | { | |
265 | struct iwl_nvm_section *sections = mvm->nvm_sections; | |
77db0a3c | 266 | const __le16 *hw, *sw, *calib, *regulatory, *mac_override; |
8ca151b5 JB |
267 | |
268 | /* Checking for required sections */ | |
77db0a3c EH |
269 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
270 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || | |
271 | !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) { | |
abf09c56 | 272 | IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n"); |
77db0a3c EH |
273 | return NULL; |
274 | } | |
275 | } else { | |
9f32e017 | 276 | /* SW and REGULATORY sections are mandatory */ |
77db0a3c | 277 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || |
77db0a3c EH |
278 | !mvm->nvm_sections[NVM_SECTION_TYPE_REGULATORY].data) { |
279 | IWL_ERR(mvm, | |
abf09c56 | 280 | "Can't parse empty family 8000 OTP/NVM sections\n"); |
77db0a3c EH |
281 | return NULL; |
282 | } | |
9f32e017 | 283 | /* MAC_OVERRIDE or at least HW section must exist */ |
bb926924 | 284 | if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data && |
9f32e017 EH |
285 | !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) { |
286 | IWL_ERR(mvm, | |
287 | "Can't parse mac_address, empty sections\n"); | |
288 | return NULL; | |
289 | } | |
8ca151b5 JB |
290 | } |
291 | ||
292 | if (WARN_ON(!mvm->cfg)) | |
293 | return NULL; | |
294 | ||
ae2b21b0 | 295 | hw = (const __le16 *)sections[mvm->cfg->nvm_hw_section_num].data; |
8ca151b5 JB |
296 | sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data; |
297 | calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data; | |
77db0a3c EH |
298 | regulatory = (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data; |
299 | mac_override = | |
300 | (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data; | |
301 | ||
9ce4fa72 | 302 | return iwl_parse_nvm_data(mvm->trans->dev, mvm->cfg, hw, sw, calib, |
77db0a3c | 303 | regulatory, mac_override, |
4ed735e7 | 304 | mvm->fw->valid_tx_ant, |
770ceda6 AN |
305 | mvm->fw->valid_rx_ant, |
306 | iwl_mvm_is_lar_supported(mvm)); | |
8ca151b5 JB |
307 | } |
308 | ||
1214755c EH |
309 | #define MAX_NVM_FILE_LEN 16384 |
310 | ||
311 | /* | |
81a67e32 EL |
312 | * Reads external NVM from a file into mvm->nvm_sections |
313 | * | |
1214755c EH |
314 | * HOW TO CREATE THE NVM FILE FORMAT: |
315 | * ------------------------------ | |
316 | * 1. create hex file, format: | |
317 | * 3800 -> header | |
318 | * 0000 -> header | |
319 | * 5a40 -> data | |
320 | * | |
321 | * rev - 6 bit (word1) | |
322 | * len - 10 bit (word1) | |
323 | * id - 4 bit (word2) | |
324 | * rsv - 12 bit (word2) | |
325 | * | |
326 | * 2. flip 8bits with 8 bits per line to get the right NVM file format | |
327 | * | |
328 | * 3. create binary file from the hex file | |
329 | * | |
330 | * 4. save as "iNVM_xxx.bin" under /lib/firmware | |
331 | */ | |
81a67e32 | 332 | static int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm) |
1214755c | 333 | { |
81a67e32 EL |
334 | int ret, section_size; |
335 | u16 section_id; | |
1214755c EH |
336 | const struct firmware *fw_entry; |
337 | const struct { | |
338 | __le16 word1; | |
339 | __le16 word2; | |
340 | u8 data[]; | |
341 | } *file_sec; | |
81a67e32 | 342 | const u8 *eof, *temp; |
f251c07c | 343 | int max_section_size; |
a4e5df28 | 344 | const __le32 *dword_buff; |
1214755c EH |
345 | |
346 | #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) | |
347 | #define NVM_WORD2_ID(x) (x >> 12) | |
77db0a3c EH |
348 | #define NVM_WORD2_LEN_FAMILY_8000(x) (2 * ((x & 0xFF) << 8 | x >> 8)) |
349 | #define NVM_WORD1_ID_FAMILY_8000(x) (x >> 4) | |
a4e5df28 IK |
350 | #define NVM_HEADER_0 (0x2A504C54) |
351 | #define NVM_HEADER_1 (0x4E564D2A) | |
352 | #define NVM_HEADER_SIZE (4 * sizeof(u32)) | |
1214755c | 353 | |
81a67e32 EL |
354 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n"); |
355 | ||
f251c07c LK |
356 | /* Maximal size depends on HW family and step */ |
357 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
358 | max_section_size = IWL_MAX_NVM_SECTION_SIZE; | |
c2a2b28b | 359 | else if (CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_A_STEP) |
f251c07c | 360 | max_section_size = IWL_MAX_NVM_8000A_SECTION_SIZE; |
716e48a6 | 361 | else /* Family 8000 B-step or C-step */ |
f251c07c LK |
362 | max_section_size = IWL_MAX_NVM_8000B_SECTION_SIZE; |
363 | ||
1214755c EH |
364 | /* |
365 | * Obtain NVM image via request_firmware. Since we already used | |
366 | * request_firmware_nowait() for the firmware binary load and only | |
367 | * get here after that we assume the NVM request can be satisfied | |
368 | * synchronously. | |
369 | */ | |
e02a9d60 | 370 | ret = request_firmware(&fw_entry, mvm->nvm_file_name, |
1214755c EH |
371 | mvm->trans->dev); |
372 | if (ret) { | |
373 | IWL_ERR(mvm, "ERROR: %s isn't available %d\n", | |
e02a9d60 | 374 | mvm->nvm_file_name, ret); |
1214755c EH |
375 | return ret; |
376 | } | |
377 | ||
378 | IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n", | |
e02a9d60 | 379 | mvm->nvm_file_name, fw_entry->size); |
1214755c | 380 | |
1214755c EH |
381 | if (fw_entry->size > MAX_NVM_FILE_LEN) { |
382 | IWL_ERR(mvm, "NVM file too large\n"); | |
383 | ret = -EINVAL; | |
384 | goto out; | |
385 | } | |
386 | ||
387 | eof = fw_entry->data + fw_entry->size; | |
a4e5df28 IK |
388 | dword_buff = (__le32 *)fw_entry->data; |
389 | ||
390 | /* some NVM file will contain a header. | |
391 | * The header is identified by 2 dwords header as follow: | |
392 | * dword[0] = 0x2A504C54 | |
393 | * dword[1] = 0x4E564D2A | |
394 | * | |
395 | * This header must be skipped when providing the NVM data to the FW. | |
396 | */ | |
397 | if (fw_entry->size > NVM_HEADER_SIZE && | |
398 | dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && | |
399 | dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { | |
400 | file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); | |
401 | IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); | |
402 | IWL_INFO(mvm, "NVM Manufacturing date %08X\n", | |
403 | le32_to_cpu(dword_buff[3])); | |
404 | } else { | |
405 | file_sec = (void *)fw_entry->data; | |
406 | } | |
1214755c EH |
407 | |
408 | while (true) { | |
409 | if (file_sec->data > eof) { | |
410 | IWL_ERR(mvm, | |
411 | "ERROR - NVM file too short for section header\n"); | |
412 | ret = -EINVAL; | |
413 | break; | |
414 | } | |
415 | ||
416 | /* check for EOF marker */ | |
417 | if (!file_sec->word1 && !file_sec->word2) { | |
418 | ret = 0; | |
419 | break; | |
420 | } | |
421 | ||
77db0a3c EH |
422 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
423 | section_size = | |
424 | 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); | |
425 | section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); | |
426 | } else { | |
427 | section_size = 2 * NVM_WORD2_LEN_FAMILY_8000( | |
428 | le16_to_cpu(file_sec->word2)); | |
429 | section_id = NVM_WORD1_ID_FAMILY_8000( | |
430 | le16_to_cpu(file_sec->word1)); | |
431 | } | |
1214755c | 432 | |
f251c07c | 433 | if (section_size > max_section_size) { |
1214755c EH |
434 | IWL_ERR(mvm, "ERROR - section too large (%d)\n", |
435 | section_size); | |
436 | ret = -EINVAL; | |
437 | break; | |
438 | } | |
439 | ||
440 | if (!section_size) { | |
441 | IWL_ERR(mvm, "ERROR - section empty\n"); | |
442 | ret = -EINVAL; | |
443 | break; | |
444 | } | |
445 | ||
446 | if (file_sec->data + section_size > eof) { | |
447 | IWL_ERR(mvm, | |
448 | "ERROR - NVM file too short for section (%d bytes)\n", | |
449 | section_size); | |
450 | ret = -EINVAL; | |
451 | break; | |
452 | } | |
453 | ||
ae2b21b0 | 454 | if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, |
a4a12478 EL |
455 | "Invalid NVM section ID %d\n", section_id)) { |
456 | ret = -EINVAL; | |
457 | break; | |
458 | } | |
459 | ||
81a67e32 EL |
460 | temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); |
461 | if (!temp) { | |
462 | ret = -ENOMEM; | |
463 | break; | |
464 | } | |
81a67e32 EL |
465 | mvm->nvm_sections[section_id].data = temp; |
466 | mvm->nvm_sections[section_id].length = section_size; | |
1214755c EH |
467 | |
468 | /* advance to the next section */ | |
469 | file_sec = (void *)(file_sec->data + section_size); | |
470 | } | |
471 | out: | |
472 | release_firmware(fw_entry); | |
473 | return ret; | |
474 | } | |
475 | ||
81a67e32 EL |
476 | /* Loads the NVM data stored in mvm->nvm_sections into the NIC */ |
477 | int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm) | |
478 | { | |
05159fcc | 479 | int i, ret = 0; |
81a67e32 EL |
480 | struct iwl_nvm_section *sections = mvm->nvm_sections; |
481 | ||
482 | IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n"); | |
483 | ||
099d8f20 EG |
484 | for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) { |
485 | if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length) | |
486 | continue; | |
487 | ret = iwl_nvm_write_section(mvm, i, sections[i].data, | |
488 | sections[i].length); | |
81a67e32 EL |
489 | if (ret < 0) { |
490 | IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret); | |
491 | break; | |
492 | } | |
493 | } | |
494 | return ret; | |
495 | } | |
496 | ||
14b485f0 | 497 | int iwl_nvm_init(struct iwl_mvm *mvm, bool read_nvm_from_nic) |
8ca151b5 | 498 | { |
d6aeb354 | 499 | int ret, section; |
5daddc99 | 500 | u32 size_read = 0; |
8ca151b5 JB |
501 | u8 *nvm_buffer, *temp; |
502 | ||
ae2b21b0 EH |
503 | if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS)) |
504 | return -EINVAL; | |
505 | ||
26481bf4 | 506 | /* load NVM values from nic */ |
14b485f0 | 507 | if (read_nvm_from_nic) { |
81a67e32 EL |
508 | /* Read From FW NVM */ |
509 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n"); | |
510 | ||
81a67e32 EL |
511 | nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size, |
512 | GFP_KERNEL); | |
513 | if (!nvm_buffer) | |
514 | return -ENOMEM; | |
d6aeb354 | 515 | for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) { |
81a67e32 | 516 | /* we override the constness for initial read */ |
5daddc99 LK |
517 | ret = iwl_nvm_read_section(mvm, section, nvm_buffer, |
518 | size_read); | |
81a67e32 | 519 | if (ret < 0) |
d6aeb354 | 520 | continue; |
5daddc99 | 521 | size_read += ret; |
81a67e32 EL |
522 | temp = kmemdup(nvm_buffer, ret, GFP_KERNEL); |
523 | if (!temp) { | |
524 | ret = -ENOMEM; | |
525 | break; | |
526 | } | |
527 | mvm->nvm_sections[section].data = temp; | |
528 | mvm->nvm_sections[section].length = ret; | |
086f7368 EG |
529 | |
530 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
531 | switch (section) { | |
086f7368 EG |
532 | case NVM_SECTION_TYPE_SW: |
533 | mvm->nvm_sw_blob.data = temp; | |
534 | mvm->nvm_sw_blob.size = ret; | |
535 | break; | |
536 | case NVM_SECTION_TYPE_CALIBRATION: | |
537 | mvm->nvm_calib_blob.data = temp; | |
538 | mvm->nvm_calib_blob.size = ret; | |
539 | break; | |
540 | case NVM_SECTION_TYPE_PRODUCTION: | |
541 | mvm->nvm_prod_blob.data = temp; | |
542 | mvm->nvm_prod_blob.size = ret; | |
543 | break; | |
544 | default: | |
ae2b21b0 EH |
545 | if (section == mvm->cfg->nvm_hw_section_num) { |
546 | mvm->nvm_hw_blob.data = temp; | |
547 | mvm->nvm_hw_blob.size = ret; | |
548 | break; | |
549 | } | |
086f7368 EG |
550 | } |
551 | #endif | |
8ca151b5 | 552 | } |
bdce40f0 EH |
553 | if (!size_read) |
554 | IWL_ERR(mvm, "OTP is blank\n"); | |
81a67e32 | 555 | kfree(nvm_buffer); |
8ca151b5 JB |
556 | } |
557 | ||
26481bf4 | 558 | /* load external NVM if configured */ |
e02a9d60 | 559 | if (mvm->nvm_file_name) { |
26481bf4 EH |
560 | /* move to External NVM flow */ |
561 | ret = iwl_mvm_read_external_nvm(mvm); | |
562 | if (ret) | |
563 | return ret; | |
564 | } | |
565 | ||
566 | /* parse the relevant nvm sections */ | |
b9545b48 | 567 | mvm->nvm_data = iwl_parse_nvm_sections(mvm); |
82598b4f JB |
568 | if (!mvm->nvm_data) |
569 | return -ENODATA; | |
2a831e08 EH |
570 | IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n", |
571 | mvm->nvm_data->nvm_version); | |
8ca151b5 | 572 | |
82598b4f | 573 | return 0; |
8ca151b5 | 574 | } |
dcaf9f5e AN |
575 | |
576 | struct iwl_mcc_update_resp * | |
577 | iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2) | |
578 | { | |
579 | struct iwl_mcc_update_cmd mcc_update_cmd = { | |
580 | .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]), | |
581 | }; | |
582 | struct iwl_mcc_update_resp *mcc_resp, *resp_cp = NULL; | |
583 | struct iwl_rx_packet *pkt; | |
584 | struct iwl_host_cmd cmd = { | |
585 | .id = MCC_UPDATE_CMD, | |
586 | .flags = CMD_WANT_SKB, | |
587 | .data = { &mcc_update_cmd }, | |
588 | }; | |
589 | ||
590 | int ret; | |
591 | u32 status; | |
592 | int resp_len, n_channels; | |
593 | u16 mcc; | |
594 | ||
595 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
596 | return ERR_PTR(-EOPNOTSUPP); | |
597 | ||
598 | cmd.len[0] = sizeof(struct iwl_mcc_update_cmd); | |
599 | ||
600 | IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c'\n", | |
601 | alpha2[0], alpha2[1]); | |
602 | ||
603 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
604 | if (ret) | |
605 | return ERR_PTR(ret); | |
606 | ||
607 | pkt = cmd.resp_pkt; | |
608 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
609 | IWL_ERR(mvm, "Bad return from MCC_UPDATE_COMMAND (0x%08X)\n", | |
610 | pkt->hdr.flags); | |
611 | ret = -EIO; | |
612 | goto exit; | |
613 | } | |
614 | ||
615 | /* Extract MCC response */ | |
616 | mcc_resp = (void *)pkt->data; | |
617 | status = le32_to_cpu(mcc_resp->status); | |
618 | ||
619 | if (status == MCC_RESP_INVALID) { | |
620 | IWL_ERR(mvm, | |
621 | "FW ERROR: MCC update with invalid parameter '%c%c'\n", | |
622 | alpha2[0], alpha2[1]); | |
623 | ret = -EINVAL; | |
624 | goto exit; | |
625 | } else if (status == MCC_RESP_NVM_DISABLED) { | |
626 | ret = 0; | |
627 | /* resp_cp will be NULL */ | |
628 | goto exit; | |
629 | } | |
630 | ||
631 | mcc = le16_to_cpu(mcc_resp->mcc); | |
632 | ||
633 | /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ | |
634 | if (mcc == 0) { | |
635 | mcc = 0x3030; /* "00" - world */ | |
636 | mcc_resp->mcc = cpu_to_le16(mcc); | |
637 | } | |
638 | ||
639 | n_channels = __le32_to_cpu(mcc_resp->n_channels); | |
640 | IWL_DEBUG_LAR(mvm, | |
641 | "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n", | |
642 | status, mcc, mcc >> 8, mcc & 0xff, | |
643 | !!(status == MCC_RESP_SAME_CHAN_PROFILE), n_channels); | |
644 | ||
645 | resp_len = sizeof(*mcc_resp) + n_channels * sizeof(__le32); | |
646 | resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL); | |
647 | if (!resp_cp) { | |
648 | ret = -ENOMEM; | |
649 | goto exit; | |
650 | } | |
651 | ||
652 | ret = 0; | |
653 | exit: | |
654 | iwl_free_resp(&cmd); | |
655 | if (ret) | |
656 | return ERR_PTR(ret); | |
657 | return resp_cp; | |
658 | } | |
90d4f7db AN |
659 | |
660 | int iwl_mvm_init_mcc(struct iwl_mvm *mvm) | |
661 | { | |
662 | if (!iwl_mvm_is_lar_supported(mvm)) | |
663 | return 0; | |
664 | ||
665 | /* | |
666 | * During HW restart, only replay the last set MCC to FW. Otherwise, | |
667 | * queue an update to cfg80211 to retrieve the default alpha2 from FW. | |
668 | */ | |
669 | if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) { | |
670 | /* This should only be called during vif up and hold RTNL */ | |
671 | const struct ieee80211_regdomain *r = | |
672 | rtnl_dereference(mvm->hw->wiphy->regd); | |
673 | ||
674 | if (r) { | |
675 | struct iwl_mcc_update_resp *resp; | |
676 | ||
677 | resp = iwl_mvm_update_mcc(mvm, r->alpha2); | |
678 | if (IS_ERR_OR_NULL(resp)) | |
679 | return -EIO; | |
680 | ||
681 | kfree(resp); | |
682 | } | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | /* | |
688 | * Driver regulatory hint for initial update - use the special | |
689 | * unknown-country "99" code. This will also clear the "custom reg" | |
690 | * flag and allow regdomain changes. It will happen after init since | |
691 | * RTNL is required. | |
88931cc9 AN |
692 | * Disallow scans that might crash the FW while the LAR regdomain |
693 | * is not set. | |
90d4f7db | 694 | */ |
88931cc9 AN |
695 | mvm->lar_regdom_set = false; |
696 | return 0; | |
697 | } | |
698 | ||
699 | int iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm, | |
700 | struct iwl_rx_cmd_buffer *rxb, | |
701 | struct iwl_device_cmd *cmd) | |
702 | { | |
703 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
704 | struct iwl_mcc_chub_notif *notif = (void *)pkt->data; | |
705 | char mcc[3]; | |
706 | ||
707 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
708 | return -EOPNOTSUPP; | |
709 | ||
710 | mcc[0] = notif->mcc >> 8; | |
711 | mcc[1] = notif->mcc & 0xff; | |
712 | mcc[2] = '\0'; | |
713 | ||
714 | IWL_DEBUG_LAR(mvm, | |
715 | "RX: received chub update mcc command (mcc 0x%x '%s')\n", | |
716 | notif->mcc, mcc); | |
717 | return 0; | |
90d4f7db | 718 | } |