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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
8ca151b5 JB |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
8ca151b5 JB |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 35 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
8ca151b5 JB |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
1214755c | 65 | #include <linux/firmware.h> |
90d4f7db | 66 | #include <linux/rtnetlink.h> |
8ca151b5 | 67 | #include "iwl-trans.h" |
c2a2b28b | 68 | #include "iwl-csr.h" |
8ca151b5 JB |
69 | #include "mvm.h" |
70 | #include "iwl-eeprom-parse.h" | |
71 | #include "iwl-eeprom-read.h" | |
72 | #include "iwl-nvm-parse.h" | |
73 | ||
1fd4afe2 | 74 | /* Default NVM size to read */ |
1214755c | 75 | #define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024) |
f251c07c LK |
76 | #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 |
77 | #define IWL_MAX_NVM_8000A_SECTION_SIZE 0xffc | |
78 | #define IWL_MAX_NVM_8000B_SECTION_SIZE 0x1ffc | |
1fd4afe2 | 79 | |
1214755c EH |
80 | #define NVM_WRITE_OPCODE 1 |
81 | #define NVM_READ_OPCODE 0 | |
82 | ||
d6aeb354 EH |
83 | /* load nvm chunk response */ |
84 | enum { | |
85 | READ_NVM_CHUNK_SUCCEED = 0, | |
86 | READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 | |
87 | }; | |
88 | ||
1214755c EH |
89 | /* |
90 | * prepare the NVM host command w/ the pointers to the nvm buffer | |
91 | * and send it to fw | |
92 | */ | |
93 | static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section, | |
94 | u16 offset, u16 length, const u8 *data) | |
8ca151b5 | 95 | { |
1214755c EH |
96 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
97 | .offset = cpu_to_le16(offset), | |
98 | .length = cpu_to_le16(length), | |
99 | .type = cpu_to_le16(section), | |
100 | .op_code = NVM_WRITE_OPCODE, | |
101 | }; | |
102 | struct iwl_host_cmd cmd = { | |
103 | .id = NVM_ACCESS_CMD, | |
104 | .len = { sizeof(struct iwl_nvm_access_cmd), length }, | |
a1022927 | 105 | .flags = CMD_SEND_IN_RFKILL, |
1214755c EH |
106 | .data = { &nvm_access_cmd, data }, |
107 | /* data may come from vmalloc, so use _DUP */ | |
108 | .dataflags = { 0, IWL_HCMD_DFL_DUP }, | |
109 | }; | |
110 | ||
111 | return iwl_mvm_send_cmd(mvm, &cmd); | |
8ca151b5 JB |
112 | } |
113 | ||
114 | static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section, | |
115 | u16 offset, u16 length, u8 *data) | |
116 | { | |
1214755c EH |
117 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
118 | .offset = cpu_to_le16(offset), | |
119 | .length = cpu_to_le16(length), | |
120 | .type = cpu_to_le16(section), | |
121 | .op_code = NVM_READ_OPCODE, | |
122 | }; | |
b9545b48 | 123 | struct iwl_nvm_access_resp *nvm_resp; |
8ca151b5 JB |
124 | struct iwl_rx_packet *pkt; |
125 | struct iwl_host_cmd cmd = { | |
126 | .id = NVM_ACCESS_CMD, | |
a1022927 | 127 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
8ca151b5 JB |
128 | .data = { &nvm_access_cmd, }, |
129 | }; | |
130 | int ret, bytes_read, offset_read; | |
131 | u8 *resp_data; | |
132 | ||
b9545b48 | 133 | cmd.len[0] = sizeof(struct iwl_nvm_access_cmd); |
8ca151b5 JB |
134 | |
135 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
136 | if (ret) | |
137 | return ret; | |
138 | ||
139 | pkt = cmd.resp_pkt; | |
140 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
141 | IWL_ERR(mvm, "Bad return from NVM_ACCES_COMMAND (0x%08X)\n", | |
142 | pkt->hdr.flags); | |
143 | ret = -EIO; | |
144 | goto exit; | |
145 | } | |
146 | ||
147 | /* Extract NVM response */ | |
148 | nvm_resp = (void *)pkt->data; | |
b9545b48 EG |
149 | ret = le16_to_cpu(nvm_resp->status); |
150 | bytes_read = le16_to_cpu(nvm_resp->length); | |
151 | offset_read = le16_to_cpu(nvm_resp->offset); | |
152 | resp_data = nvm_resp->data; | |
8ca151b5 | 153 | if (ret) { |
d6aeb354 EH |
154 | if ((offset != 0) && |
155 | (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { | |
156 | /* | |
157 | * meaning of NOT_VALID_ADDRESS: | |
158 | * driver try to read chunk from address that is | |
159 | * multiple of 2K and got an error since addr is empty. | |
160 | * meaning of (offset != 0): driver already | |
161 | * read valid data from another chunk so this case | |
162 | * is not an error. | |
163 | */ | |
164 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
165 | "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", | |
166 | offset); | |
167 | ret = 0; | |
168 | } else { | |
169 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
170 | "NVM access command failed with status %d (device: %s)\n", | |
171 | ret, mvm->cfg->name); | |
172 | ret = -EIO; | |
173 | } | |
8ca151b5 JB |
174 | goto exit; |
175 | } | |
176 | ||
177 | if (offset_read != offset) { | |
178 | IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n", | |
179 | offset_read); | |
180 | ret = -EINVAL; | |
181 | goto exit; | |
182 | } | |
183 | ||
184 | /* Write data to NVM */ | |
185 | memcpy(data + offset, resp_data, bytes_read); | |
186 | ret = bytes_read; | |
187 | ||
188 | exit: | |
189 | iwl_free_resp(&cmd); | |
190 | return ret; | |
191 | } | |
192 | ||
1214755c EH |
193 | static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section, |
194 | const u8 *data, u16 length) | |
195 | { | |
196 | int offset = 0; | |
197 | ||
198 | /* copy data in chunks of 2k (and remainder if any) */ | |
199 | ||
200 | while (offset < length) { | |
201 | int chunk_size, ret; | |
202 | ||
203 | chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE, | |
204 | length - offset); | |
205 | ||
206 | ret = iwl_nvm_write_chunk(mvm, section, offset, | |
207 | chunk_size, data + offset); | |
208 | if (ret < 0) | |
209 | return ret; | |
210 | ||
211 | offset += chunk_size; | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
8ca151b5 JB |
217 | /* |
218 | * Reads an NVM section completely. | |
219 | * NICs prior to 7000 family doesn't have a real NVM, but just read | |
220 | * section 0 which is the EEPROM. Because the EEPROM reading is unlimited | |
221 | * by uCode, we need to manually check in this case that we don't | |
222 | * overflow and try to read more than the EEPROM size. | |
223 | * For 7000 family NICs, we supply the maximal size we can read, and | |
224 | * the uCode fills the response with as much data as we can, | |
225 | * without overflowing, so no check is needed. | |
226 | */ | |
227 | static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section, | |
5daddc99 | 228 | u8 *data, u32 size_read) |
8ca151b5 JB |
229 | { |
230 | u16 length, offset = 0; | |
231 | int ret; | |
8ca151b5 | 232 | |
1fd4afe2 DS |
233 | /* Set nvm section read length */ |
234 | length = IWL_NVM_DEFAULT_CHUNK_SIZE; | |
235 | ||
8ca151b5 JB |
236 | ret = length; |
237 | ||
238 | /* Read the NVM until exhausted (reading less than requested) */ | |
239 | while (ret == length) { | |
5daddc99 LK |
240 | /* Check no memory assumptions fail and cause an overflow */ |
241 | if ((size_read + offset + length) > | |
242 | mvm->cfg->base_params->eeprom_size) { | |
243 | IWL_ERR(mvm, "EEPROM size is too small for NVM\n"); | |
244 | return -ENOBUFS; | |
245 | } | |
246 | ||
8ca151b5 JB |
247 | ret = iwl_nvm_read_chunk(mvm, section, offset, length, data); |
248 | if (ret < 0) { | |
d6aeb354 EH |
249 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
250 | "Cannot read NVM from section %d offset %d, length %d\n", | |
251 | section, offset, length); | |
8ca151b5 JB |
252 | return ret; |
253 | } | |
254 | offset += ret; | |
8ca151b5 JB |
255 | } |
256 | ||
07fd7d28 JB |
257 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
258 | "NVM section %d read completed\n", section); | |
8ca151b5 JB |
259 | return offset; |
260 | } | |
261 | ||
262 | static struct iwl_nvm_data * | |
263 | iwl_parse_nvm_sections(struct iwl_mvm *mvm) | |
264 | { | |
265 | struct iwl_nvm_section *sections = mvm->nvm_sections; | |
ce500071 | 266 | const __le16 *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku; |
5711cac4 | 267 | bool is_family_8000_a_step = false, lar_enabled; |
8ca151b5 JB |
268 | |
269 | /* Checking for required sections */ | |
77db0a3c EH |
270 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
271 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || | |
272 | !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) { | |
abf09c56 | 273 | IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n"); |
77db0a3c EH |
274 | return NULL; |
275 | } | |
276 | } else { | |
9f32e017 | 277 | /* SW and REGULATORY sections are mandatory */ |
77db0a3c | 278 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || |
77db0a3c EH |
279 | !mvm->nvm_sections[NVM_SECTION_TYPE_REGULATORY].data) { |
280 | IWL_ERR(mvm, | |
abf09c56 | 281 | "Can't parse empty family 8000 OTP/NVM sections\n"); |
77db0a3c EH |
282 | return NULL; |
283 | } | |
9f32e017 | 284 | /* MAC_OVERRIDE or at least HW section must exist */ |
bb926924 | 285 | if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data && |
9f32e017 EH |
286 | !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) { |
287 | IWL_ERR(mvm, | |
288 | "Can't parse mac_address, empty sections\n"); | |
289 | return NULL; | |
290 | } | |
ce500071 EH |
291 | |
292 | if (CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_A_STEP) | |
293 | is_family_8000_a_step = true; | |
294 | ||
295 | /* PHY_SKU section is mandatory in B0 */ | |
296 | if (!is_family_8000_a_step && | |
297 | !mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) { | |
298 | IWL_ERR(mvm, | |
299 | "Can't parse phy_sku in B0, empty sections\n"); | |
300 | return NULL; | |
301 | } | |
8ca151b5 JB |
302 | } |
303 | ||
304 | if (WARN_ON(!mvm->cfg)) | |
305 | return NULL; | |
306 | ||
ae2b21b0 | 307 | hw = (const __le16 *)sections[mvm->cfg->nvm_hw_section_num].data; |
8ca151b5 JB |
308 | sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data; |
309 | calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data; | |
77db0a3c EH |
310 | regulatory = (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data; |
311 | mac_override = | |
312 | (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data; | |
ce500071 | 313 | phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data; |
77db0a3c | 314 | |
5711cac4 AN |
315 | lar_enabled = !iwlwifi_mod_params.lar_disable && |
316 | (mvm->fw->ucode_capa.capa[0] & | |
317 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT); | |
318 | ||
9ce4fa72 | 319 | return iwl_parse_nvm_data(mvm->trans->dev, mvm->cfg, hw, sw, calib, |
ce500071 | 320 | regulatory, mac_override, phy_sku, |
5711cac4 AN |
321 | mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant, |
322 | lar_enabled, is_family_8000_a_step); | |
8ca151b5 JB |
323 | } |
324 | ||
1214755c EH |
325 | #define MAX_NVM_FILE_LEN 16384 |
326 | ||
327 | /* | |
81a67e32 EL |
328 | * Reads external NVM from a file into mvm->nvm_sections |
329 | * | |
1214755c EH |
330 | * HOW TO CREATE THE NVM FILE FORMAT: |
331 | * ------------------------------ | |
332 | * 1. create hex file, format: | |
333 | * 3800 -> header | |
334 | * 0000 -> header | |
335 | * 5a40 -> data | |
336 | * | |
337 | * rev - 6 bit (word1) | |
338 | * len - 10 bit (word1) | |
339 | * id - 4 bit (word2) | |
340 | * rsv - 12 bit (word2) | |
341 | * | |
342 | * 2. flip 8bits with 8 bits per line to get the right NVM file format | |
343 | * | |
344 | * 3. create binary file from the hex file | |
345 | * | |
346 | * 4. save as "iNVM_xxx.bin" under /lib/firmware | |
347 | */ | |
81a67e32 | 348 | static int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm) |
1214755c | 349 | { |
81a67e32 EL |
350 | int ret, section_size; |
351 | u16 section_id; | |
1214755c EH |
352 | const struct firmware *fw_entry; |
353 | const struct { | |
354 | __le16 word1; | |
355 | __le16 word2; | |
356 | u8 data[]; | |
357 | } *file_sec; | |
81a67e32 | 358 | const u8 *eof, *temp; |
f251c07c | 359 | int max_section_size; |
a4e5df28 | 360 | const __le32 *dword_buff; |
1214755c EH |
361 | |
362 | #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) | |
363 | #define NVM_WORD2_ID(x) (x >> 12) | |
77db0a3c EH |
364 | #define NVM_WORD2_LEN_FAMILY_8000(x) (2 * ((x & 0xFF) << 8 | x >> 8)) |
365 | #define NVM_WORD1_ID_FAMILY_8000(x) (x >> 4) | |
a4e5df28 IK |
366 | #define NVM_HEADER_0 (0x2A504C54) |
367 | #define NVM_HEADER_1 (0x4E564D2A) | |
368 | #define NVM_HEADER_SIZE (4 * sizeof(u32)) | |
1214755c | 369 | |
81a67e32 EL |
370 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n"); |
371 | ||
f251c07c LK |
372 | /* Maximal size depends on HW family and step */ |
373 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
374 | max_section_size = IWL_MAX_NVM_SECTION_SIZE; | |
c2a2b28b | 375 | else if (CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_A_STEP) |
f251c07c | 376 | max_section_size = IWL_MAX_NVM_8000A_SECTION_SIZE; |
716e48a6 | 377 | else /* Family 8000 B-step or C-step */ |
f251c07c LK |
378 | max_section_size = IWL_MAX_NVM_8000B_SECTION_SIZE; |
379 | ||
1214755c EH |
380 | /* |
381 | * Obtain NVM image via request_firmware. Since we already used | |
382 | * request_firmware_nowait() for the firmware binary load and only | |
383 | * get here after that we assume the NVM request can be satisfied | |
384 | * synchronously. | |
385 | */ | |
e02a9d60 | 386 | ret = request_firmware(&fw_entry, mvm->nvm_file_name, |
1214755c EH |
387 | mvm->trans->dev); |
388 | if (ret) { | |
389 | IWL_ERR(mvm, "ERROR: %s isn't available %d\n", | |
e02a9d60 | 390 | mvm->nvm_file_name, ret); |
1214755c EH |
391 | return ret; |
392 | } | |
393 | ||
394 | IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n", | |
e02a9d60 | 395 | mvm->nvm_file_name, fw_entry->size); |
1214755c | 396 | |
1214755c EH |
397 | if (fw_entry->size > MAX_NVM_FILE_LEN) { |
398 | IWL_ERR(mvm, "NVM file too large\n"); | |
399 | ret = -EINVAL; | |
400 | goto out; | |
401 | } | |
402 | ||
403 | eof = fw_entry->data + fw_entry->size; | |
a4e5df28 IK |
404 | dword_buff = (__le32 *)fw_entry->data; |
405 | ||
406 | /* some NVM file will contain a header. | |
407 | * The header is identified by 2 dwords header as follow: | |
408 | * dword[0] = 0x2A504C54 | |
409 | * dword[1] = 0x4E564D2A | |
410 | * | |
411 | * This header must be skipped when providing the NVM data to the FW. | |
412 | */ | |
413 | if (fw_entry->size > NVM_HEADER_SIZE && | |
414 | dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && | |
415 | dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { | |
416 | file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); | |
417 | IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); | |
418 | IWL_INFO(mvm, "NVM Manufacturing date %08X\n", | |
419 | le32_to_cpu(dword_buff[3])); | |
420 | } else { | |
421 | file_sec = (void *)fw_entry->data; | |
422 | } | |
1214755c EH |
423 | |
424 | while (true) { | |
425 | if (file_sec->data > eof) { | |
426 | IWL_ERR(mvm, | |
427 | "ERROR - NVM file too short for section header\n"); | |
428 | ret = -EINVAL; | |
429 | break; | |
430 | } | |
431 | ||
432 | /* check for EOF marker */ | |
433 | if (!file_sec->word1 && !file_sec->word2) { | |
434 | ret = 0; | |
435 | break; | |
436 | } | |
437 | ||
77db0a3c EH |
438 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
439 | section_size = | |
440 | 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); | |
441 | section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); | |
442 | } else { | |
443 | section_size = 2 * NVM_WORD2_LEN_FAMILY_8000( | |
444 | le16_to_cpu(file_sec->word2)); | |
445 | section_id = NVM_WORD1_ID_FAMILY_8000( | |
446 | le16_to_cpu(file_sec->word1)); | |
447 | } | |
1214755c | 448 | |
f251c07c | 449 | if (section_size > max_section_size) { |
1214755c EH |
450 | IWL_ERR(mvm, "ERROR - section too large (%d)\n", |
451 | section_size); | |
452 | ret = -EINVAL; | |
453 | break; | |
454 | } | |
455 | ||
456 | if (!section_size) { | |
457 | IWL_ERR(mvm, "ERROR - section empty\n"); | |
458 | ret = -EINVAL; | |
459 | break; | |
460 | } | |
461 | ||
462 | if (file_sec->data + section_size > eof) { | |
463 | IWL_ERR(mvm, | |
464 | "ERROR - NVM file too short for section (%d bytes)\n", | |
465 | section_size); | |
466 | ret = -EINVAL; | |
467 | break; | |
468 | } | |
469 | ||
ae2b21b0 | 470 | if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, |
a4a12478 EL |
471 | "Invalid NVM section ID %d\n", section_id)) { |
472 | ret = -EINVAL; | |
473 | break; | |
474 | } | |
475 | ||
81a67e32 EL |
476 | temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); |
477 | if (!temp) { | |
478 | ret = -ENOMEM; | |
479 | break; | |
480 | } | |
81a67e32 EL |
481 | mvm->nvm_sections[section_id].data = temp; |
482 | mvm->nvm_sections[section_id].length = section_size; | |
1214755c EH |
483 | |
484 | /* advance to the next section */ | |
485 | file_sec = (void *)(file_sec->data + section_size); | |
486 | } | |
487 | out: | |
488 | release_firmware(fw_entry); | |
489 | return ret; | |
490 | } | |
491 | ||
81a67e32 EL |
492 | /* Loads the NVM data stored in mvm->nvm_sections into the NIC */ |
493 | int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm) | |
494 | { | |
05159fcc | 495 | int i, ret = 0; |
81a67e32 EL |
496 | struct iwl_nvm_section *sections = mvm->nvm_sections; |
497 | ||
498 | IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n"); | |
499 | ||
099d8f20 EG |
500 | for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) { |
501 | if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length) | |
502 | continue; | |
503 | ret = iwl_nvm_write_section(mvm, i, sections[i].data, | |
504 | sections[i].length); | |
81a67e32 EL |
505 | if (ret < 0) { |
506 | IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret); | |
507 | break; | |
508 | } | |
509 | } | |
510 | return ret; | |
511 | } | |
512 | ||
14b485f0 | 513 | int iwl_nvm_init(struct iwl_mvm *mvm, bool read_nvm_from_nic) |
8ca151b5 | 514 | { |
d6aeb354 | 515 | int ret, section; |
5daddc99 | 516 | u32 size_read = 0; |
8ca151b5 JB |
517 | u8 *nvm_buffer, *temp; |
518 | ||
ae2b21b0 EH |
519 | if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS)) |
520 | return -EINVAL; | |
521 | ||
26481bf4 | 522 | /* load NVM values from nic */ |
14b485f0 | 523 | if (read_nvm_from_nic) { |
81a67e32 EL |
524 | /* Read From FW NVM */ |
525 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n"); | |
526 | ||
81a67e32 EL |
527 | nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size, |
528 | GFP_KERNEL); | |
529 | if (!nvm_buffer) | |
530 | return -ENOMEM; | |
d6aeb354 | 531 | for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) { |
81a67e32 | 532 | /* we override the constness for initial read */ |
5daddc99 LK |
533 | ret = iwl_nvm_read_section(mvm, section, nvm_buffer, |
534 | size_read); | |
81a67e32 | 535 | if (ret < 0) |
d6aeb354 | 536 | continue; |
5daddc99 | 537 | size_read += ret; |
81a67e32 EL |
538 | temp = kmemdup(nvm_buffer, ret, GFP_KERNEL); |
539 | if (!temp) { | |
540 | ret = -ENOMEM; | |
541 | break; | |
542 | } | |
543 | mvm->nvm_sections[section].data = temp; | |
544 | mvm->nvm_sections[section].length = ret; | |
086f7368 EG |
545 | |
546 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
547 | switch (section) { | |
086f7368 EG |
548 | case NVM_SECTION_TYPE_SW: |
549 | mvm->nvm_sw_blob.data = temp; | |
550 | mvm->nvm_sw_blob.size = ret; | |
551 | break; | |
552 | case NVM_SECTION_TYPE_CALIBRATION: | |
553 | mvm->nvm_calib_blob.data = temp; | |
554 | mvm->nvm_calib_blob.size = ret; | |
555 | break; | |
556 | case NVM_SECTION_TYPE_PRODUCTION: | |
557 | mvm->nvm_prod_blob.data = temp; | |
558 | mvm->nvm_prod_blob.size = ret; | |
559 | break; | |
560 | default: | |
ae2b21b0 EH |
561 | if (section == mvm->cfg->nvm_hw_section_num) { |
562 | mvm->nvm_hw_blob.data = temp; | |
563 | mvm->nvm_hw_blob.size = ret; | |
564 | break; | |
565 | } | |
086f7368 EG |
566 | } |
567 | #endif | |
8ca151b5 | 568 | } |
bdce40f0 EH |
569 | if (!size_read) |
570 | IWL_ERR(mvm, "OTP is blank\n"); | |
81a67e32 | 571 | kfree(nvm_buffer); |
8ca151b5 JB |
572 | } |
573 | ||
26481bf4 | 574 | /* load external NVM if configured */ |
e02a9d60 | 575 | if (mvm->nvm_file_name) { |
26481bf4 EH |
576 | /* move to External NVM flow */ |
577 | ret = iwl_mvm_read_external_nvm(mvm); | |
578 | if (ret) | |
579 | return ret; | |
580 | } | |
581 | ||
582 | /* parse the relevant nvm sections */ | |
b9545b48 | 583 | mvm->nvm_data = iwl_parse_nvm_sections(mvm); |
82598b4f JB |
584 | if (!mvm->nvm_data) |
585 | return -ENODATA; | |
2a831e08 EH |
586 | IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n", |
587 | mvm->nvm_data->nvm_version); | |
8ca151b5 | 588 | |
82598b4f | 589 | return 0; |
8ca151b5 | 590 | } |
dcaf9f5e AN |
591 | |
592 | struct iwl_mcc_update_resp * | |
593 | iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2) | |
594 | { | |
595 | struct iwl_mcc_update_cmd mcc_update_cmd = { | |
596 | .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]), | |
597 | }; | |
598 | struct iwl_mcc_update_resp *mcc_resp, *resp_cp = NULL; | |
599 | struct iwl_rx_packet *pkt; | |
600 | struct iwl_host_cmd cmd = { | |
601 | .id = MCC_UPDATE_CMD, | |
602 | .flags = CMD_WANT_SKB, | |
603 | .data = { &mcc_update_cmd }, | |
604 | }; | |
605 | ||
606 | int ret; | |
607 | u32 status; | |
608 | int resp_len, n_channels; | |
609 | u16 mcc; | |
610 | ||
611 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
612 | return ERR_PTR(-EOPNOTSUPP); | |
613 | ||
614 | cmd.len[0] = sizeof(struct iwl_mcc_update_cmd); | |
615 | ||
616 | IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c'\n", | |
617 | alpha2[0], alpha2[1]); | |
618 | ||
619 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
620 | if (ret) | |
621 | return ERR_PTR(ret); | |
622 | ||
623 | pkt = cmd.resp_pkt; | |
624 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
625 | IWL_ERR(mvm, "Bad return from MCC_UPDATE_COMMAND (0x%08X)\n", | |
626 | pkt->hdr.flags); | |
627 | ret = -EIO; | |
628 | goto exit; | |
629 | } | |
630 | ||
631 | /* Extract MCC response */ | |
632 | mcc_resp = (void *)pkt->data; | |
633 | status = le32_to_cpu(mcc_resp->status); | |
634 | ||
635 | if (status == MCC_RESP_INVALID) { | |
636 | IWL_ERR(mvm, | |
637 | "FW ERROR: MCC update with invalid parameter '%c%c'\n", | |
638 | alpha2[0], alpha2[1]); | |
639 | ret = -EINVAL; | |
640 | goto exit; | |
641 | } else if (status == MCC_RESP_NVM_DISABLED) { | |
642 | ret = 0; | |
643 | /* resp_cp will be NULL */ | |
644 | goto exit; | |
645 | } | |
646 | ||
647 | mcc = le16_to_cpu(mcc_resp->mcc); | |
648 | ||
649 | /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ | |
650 | if (mcc == 0) { | |
651 | mcc = 0x3030; /* "00" - world */ | |
652 | mcc_resp->mcc = cpu_to_le16(mcc); | |
653 | } | |
654 | ||
655 | n_channels = __le32_to_cpu(mcc_resp->n_channels); | |
656 | IWL_DEBUG_LAR(mvm, | |
657 | "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n", | |
658 | status, mcc, mcc >> 8, mcc & 0xff, | |
659 | !!(status == MCC_RESP_SAME_CHAN_PROFILE), n_channels); | |
660 | ||
661 | resp_len = sizeof(*mcc_resp) + n_channels * sizeof(__le32); | |
662 | resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL); | |
663 | if (!resp_cp) { | |
664 | ret = -ENOMEM; | |
665 | goto exit; | |
666 | } | |
667 | ||
668 | ret = 0; | |
669 | exit: | |
670 | iwl_free_resp(&cmd); | |
671 | if (ret) | |
672 | return ERR_PTR(ret); | |
673 | return resp_cp; | |
674 | } | |
90d4f7db AN |
675 | |
676 | int iwl_mvm_init_mcc(struct iwl_mvm *mvm) | |
677 | { | |
d0d15197 MG |
678 | bool tlv_lar; |
679 | bool nvm_lar; | |
680 | ||
681 | if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000) { | |
682 | tlv_lar = mvm->fw->ucode_capa.capa[0] & | |
683 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT; | |
684 | nvm_lar = mvm->nvm_data->lar_enabled; | |
685 | if (tlv_lar != nvm_lar) | |
686 | IWL_INFO(mvm, | |
687 | "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n", | |
688 | tlv_lar ? "enabled" : "disabled", | |
689 | nvm_lar ? "enabled" : "disabled"); | |
690 | } | |
691 | ||
90d4f7db AN |
692 | if (!iwl_mvm_is_lar_supported(mvm)) |
693 | return 0; | |
694 | ||
695 | /* | |
696 | * During HW restart, only replay the last set MCC to FW. Otherwise, | |
697 | * queue an update to cfg80211 to retrieve the default alpha2 from FW. | |
698 | */ | |
699 | if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) { | |
700 | /* This should only be called during vif up and hold RTNL */ | |
701 | const struct ieee80211_regdomain *r = | |
702 | rtnl_dereference(mvm->hw->wiphy->regd); | |
703 | ||
704 | if (r) { | |
705 | struct iwl_mcc_update_resp *resp; | |
706 | ||
707 | resp = iwl_mvm_update_mcc(mvm, r->alpha2); | |
708 | if (IS_ERR_OR_NULL(resp)) | |
709 | return -EIO; | |
710 | ||
711 | kfree(resp); | |
712 | } | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | /* | |
718 | * Driver regulatory hint for initial update - use the special | |
719 | * unknown-country "99" code. This will also clear the "custom reg" | |
720 | * flag and allow regdomain changes. It will happen after init since | |
721 | * RTNL is required. | |
88931cc9 AN |
722 | * Disallow scans that might crash the FW while the LAR regdomain |
723 | * is not set. | |
90d4f7db | 724 | */ |
88931cc9 AN |
725 | mvm->lar_regdom_set = false; |
726 | return 0; | |
727 | } | |
728 | ||
729 | int iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm, | |
730 | struct iwl_rx_cmd_buffer *rxb, | |
731 | struct iwl_device_cmd *cmd) | |
732 | { | |
733 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
734 | struct iwl_mcc_chub_notif *notif = (void *)pkt->data; | |
735 | char mcc[3]; | |
736 | ||
737 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
738 | return -EOPNOTSUPP; | |
739 | ||
740 | mcc[0] = notif->mcc >> 8; | |
741 | mcc[1] = notif->mcc & 0xff; | |
742 | mcc[2] = '\0'; | |
743 | ||
744 | IWL_DEBUG_LAR(mvm, | |
745 | "RX: received chub update mcc command (mcc 0x%x '%s')\n", | |
746 | notif->mcc, mcc); | |
747 | return 0; | |
90d4f7db | 748 | } |