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1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2012 - 2013 Intel Corporation. All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 25 | * in the file called COPYING. |
8ca151b5 JB |
26 | * |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
33 | * Copyright(c) 2012 - 2013 Intel Corporation. All rights reserved. | |
34 | * All rights reserved. | |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
63 | ||
64 | #ifndef __fw_api_h__ | |
65 | #define __fw_api_h__ | |
66 | ||
67 | #include "fw-api-rs.h" | |
68 | #include "fw-api-tx.h" | |
69 | #include "fw-api-sta.h" | |
70 | #include "fw-api-mac.h" | |
71 | #include "fw-api-power.h" | |
72 | #include "fw-api-d3.h" | |
fb3ceb81 | 73 | #include "fw-api-bt-coex.h" |
8ca151b5 JB |
74 | |
75 | /* queue and FIFO numbers by usage */ | |
76 | enum { | |
77 | IWL_MVM_OFFCHANNEL_QUEUE = 8, | |
78 | IWL_MVM_CMD_QUEUE = 9, | |
79 | IWL_MVM_AUX_QUEUE = 15, | |
80 | IWL_MVM_FIRST_AGG_QUEUE = 16, | |
81 | IWL_MVM_NUM_QUEUES = 20, | |
82 | IWL_MVM_LAST_AGG_QUEUE = IWL_MVM_NUM_QUEUES - 1, | |
83 | IWL_MVM_CMD_FIFO = 7 | |
84 | }; | |
85 | ||
86 | #define IWL_MVM_STATION_COUNT 16 | |
87 | ||
88 | /* commands */ | |
89 | enum { | |
90 | MVM_ALIVE = 0x1, | |
91 | REPLY_ERROR = 0x2, | |
92 | ||
93 | INIT_COMPLETE_NOTIF = 0x4, | |
94 | ||
95 | /* PHY context commands */ | |
96 | PHY_CONTEXT_CMD = 0x8, | |
97 | DBG_CFG = 0x9, | |
98 | ||
99 | /* station table */ | |
100 | ADD_STA = 0x18, | |
101 | REMOVE_STA = 0x19, | |
102 | ||
103 | /* TX */ | |
104 | TX_CMD = 0x1c, | |
105 | TXPATH_FLUSH = 0x1e, | |
106 | MGMT_MCAST_KEY = 0x1f, | |
107 | ||
108 | /* global key */ | |
109 | WEP_KEY = 0x20, | |
110 | ||
111 | /* MAC and Binding commands */ | |
112 | MAC_CONTEXT_CMD = 0x28, | |
113 | TIME_EVENT_CMD = 0x29, /* both CMD and response */ | |
114 | TIME_EVENT_NOTIFICATION = 0x2a, | |
115 | BINDING_CONTEXT_CMD = 0x2b, | |
116 | TIME_QUOTA_CMD = 0x2c, | |
117 | ||
118 | LQ_CMD = 0x4e, | |
119 | ||
120 | /* Calibration */ | |
121 | TEMPERATURE_NOTIFICATION = 0x62, | |
122 | CALIBRATION_CFG_CMD = 0x65, | |
123 | CALIBRATION_RES_NOTIFICATION = 0x66, | |
124 | CALIBRATION_COMPLETE_NOTIFICATION = 0x67, | |
125 | RADIO_VERSION_NOTIFICATION = 0x68, | |
126 | ||
127 | /* Scan offload */ | |
128 | SCAN_OFFLOAD_REQUEST_CMD = 0x51, | |
129 | SCAN_OFFLOAD_ABORT_CMD = 0x52, | |
130 | SCAN_OFFLOAD_COMPLETE = 0x6D, | |
131 | SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E, | |
132 | SCAN_OFFLOAD_CONFIG_CMD = 0x6f, | |
133 | ||
134 | /* Phy */ | |
135 | PHY_CONFIGURATION_CMD = 0x6a, | |
136 | CALIB_RES_NOTIF_PHY_DB = 0x6b, | |
137 | /* PHY_DB_CMD = 0x6c, */ | |
138 | ||
139 | /* Power */ | |
140 | POWER_TABLE_CMD = 0x77, | |
141 | ||
142 | /* Scanning */ | |
143 | SCAN_REQUEST_CMD = 0x80, | |
144 | SCAN_ABORT_CMD = 0x81, | |
145 | SCAN_START_NOTIFICATION = 0x82, | |
146 | SCAN_RESULTS_NOTIFICATION = 0x83, | |
147 | SCAN_COMPLETE_NOTIFICATION = 0x84, | |
148 | ||
149 | /* NVM */ | |
150 | NVM_ACCESS_CMD = 0x88, | |
151 | ||
152 | SET_CALIB_DEFAULT_CMD = 0x8e, | |
153 | ||
571765c8 | 154 | BEACON_NOTIFICATION = 0x90, |
8ca151b5 JB |
155 | BEACON_TEMPLATE_CMD = 0x91, |
156 | TX_ANT_CONFIGURATION_CMD = 0x98, | |
fb3ceb81 | 157 | BT_CONFIG = 0x9b, |
8ca151b5 JB |
158 | STATISTICS_NOTIFICATION = 0x9d, |
159 | ||
160 | /* RF-KILL commands and notifications */ | |
161 | CARD_STATE_CMD = 0xa0, | |
162 | CARD_STATE_NOTIFICATION = 0xa1, | |
163 | ||
164 | REPLY_RX_PHY_CMD = 0xc0, | |
165 | REPLY_RX_MPDU_CMD = 0xc1, | |
166 | BA_NOTIF = 0xc5, | |
167 | ||
fb3ceb81 EG |
168 | /* BT Coex */ |
169 | BT_COEX_PRIO_TABLE = 0xcc, | |
170 | BT_COEX_PROT_ENV = 0xcd, | |
171 | BT_PROFILE_NOTIFICATION = 0xce, | |
172 | ||
8ca151b5 JB |
173 | REPLY_DEBUG_CMD = 0xf0, |
174 | DEBUG_LOG_MSG = 0xf7, | |
175 | ||
176 | /* D3 commands/notifications */ | |
177 | D3_CONFIG_CMD = 0xd3, | |
178 | PROT_OFFLOAD_CONFIG_CMD = 0xd4, | |
179 | OFFLOADS_QUERY_CMD = 0xd5, | |
180 | REMOTE_WAKE_CONFIG_CMD = 0xd6, | |
181 | ||
182 | /* for WoWLAN in particular */ | |
183 | WOWLAN_PATTERNS = 0xe0, | |
184 | WOWLAN_CONFIGURATION = 0xe1, | |
185 | WOWLAN_TSC_RSC_PARAM = 0xe2, | |
186 | WOWLAN_TKIP_PARAM = 0xe3, | |
187 | WOWLAN_KEK_KCK_MATERIAL = 0xe4, | |
188 | WOWLAN_GET_STATUSES = 0xe5, | |
189 | WOWLAN_TX_POWER_PER_DB = 0xe6, | |
190 | ||
191 | /* and for NetDetect */ | |
192 | NET_DETECT_CONFIG_CMD = 0x54, | |
193 | NET_DETECT_PROFILES_QUERY_CMD = 0x56, | |
194 | NET_DETECT_PROFILES_CMD = 0x57, | |
195 | NET_DETECT_HOTSPOTS_CMD = 0x58, | |
196 | NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, | |
197 | ||
198 | REPLY_MAX = 0xff, | |
199 | }; | |
200 | ||
201 | /** | |
202 | * struct iwl_cmd_response - generic response struct for most commands | |
203 | * @status: status of the command asked, changes for each one | |
204 | */ | |
205 | struct iwl_cmd_response { | |
206 | __le32 status; | |
207 | }; | |
208 | ||
209 | /* | |
210 | * struct iwl_tx_ant_cfg_cmd | |
211 | * @valid: valid antenna configuration | |
212 | */ | |
213 | struct iwl_tx_ant_cfg_cmd { | |
214 | __le32 valid; | |
215 | } __packed; | |
216 | ||
217 | /* | |
218 | * Calibration control struct. | |
219 | * Sent as part of the phy configuration command. | |
220 | * @flow_trigger: bitmap for which calibrations to perform according to | |
221 | * flow triggers. | |
222 | * @event_trigger: bitmap for which calibrations to perform according to | |
223 | * event triggers. | |
224 | */ | |
225 | struct iwl_calib_ctrl { | |
226 | __le32 flow_trigger; | |
227 | __le32 event_trigger; | |
228 | } __packed; | |
229 | ||
230 | /* This enum defines the bitmap of various calibrations to enable in both | |
231 | * init ucode and runtime ucode through CALIBRATION_CFG_CMD. | |
232 | */ | |
233 | enum iwl_calib_cfg { | |
234 | IWL_CALIB_CFG_XTAL_IDX = BIT(0), | |
235 | IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1), | |
236 | IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2), | |
237 | IWL_CALIB_CFG_PAPD_IDX = BIT(3), | |
238 | IWL_CALIB_CFG_TX_PWR_IDX = BIT(4), | |
239 | IWL_CALIB_CFG_DC_IDX = BIT(5), | |
240 | IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6), | |
241 | IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7), | |
242 | IWL_CALIB_CFG_TX_IQ_IDX = BIT(8), | |
243 | IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9), | |
244 | IWL_CALIB_CFG_RX_IQ_IDX = BIT(10), | |
245 | IWL_CALIB_CFG_RX_IQ_SKEW_IDX = BIT(11), | |
246 | IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(12), | |
247 | IWL_CALIB_CFG_CHAIN_NOISE_IDX = BIT(13), | |
248 | IWL_CALIB_CFG_DISCONNECTED_ANT_IDX = BIT(14), | |
249 | IWL_CALIB_CFG_ANT_COUPLING_IDX = BIT(15), | |
250 | IWL_CALIB_CFG_DAC_IDX = BIT(16), | |
251 | IWL_CALIB_CFG_ABS_IDX = BIT(17), | |
252 | IWL_CALIB_CFG_AGC_IDX = BIT(18), | |
253 | }; | |
254 | ||
255 | /* | |
256 | * Phy configuration command. | |
257 | */ | |
258 | struct iwl_phy_cfg_cmd { | |
259 | __le32 phy_cfg; | |
260 | struct iwl_calib_ctrl calib_control; | |
261 | } __packed; | |
262 | ||
263 | #define PHY_CFG_RADIO_TYPE (BIT(0) | BIT(1)) | |
264 | #define PHY_CFG_RADIO_STEP (BIT(2) | BIT(3)) | |
265 | #define PHY_CFG_RADIO_DASH (BIT(4) | BIT(5)) | |
266 | #define PHY_CFG_PRODUCT_NUMBER (BIT(6) | BIT(7)) | |
267 | #define PHY_CFG_TX_CHAIN_A BIT(8) | |
268 | #define PHY_CFG_TX_CHAIN_B BIT(9) | |
269 | #define PHY_CFG_TX_CHAIN_C BIT(10) | |
270 | #define PHY_CFG_RX_CHAIN_A BIT(12) | |
271 | #define PHY_CFG_RX_CHAIN_B BIT(13) | |
272 | #define PHY_CFG_RX_CHAIN_C BIT(14) | |
273 | ||
274 | ||
275 | /* Target of the NVM_ACCESS_CMD */ | |
276 | enum { | |
277 | NVM_ACCESS_TARGET_CACHE = 0, | |
278 | NVM_ACCESS_TARGET_OTP = 1, | |
279 | NVM_ACCESS_TARGET_EEPROM = 2, | |
280 | }; | |
281 | ||
b9545b48 | 282 | /* Section types for NVM_ACCESS_CMD */ |
8ca151b5 JB |
283 | enum { |
284 | NVM_SECTION_TYPE_HW = 0, | |
285 | NVM_SECTION_TYPE_SW, | |
286 | NVM_SECTION_TYPE_PAPD, | |
287 | NVM_SECTION_TYPE_BT, | |
288 | NVM_SECTION_TYPE_CALIBRATION, | |
289 | NVM_SECTION_TYPE_PRODUCTION, | |
290 | NVM_SECTION_TYPE_POST_FCS_CALIB, | |
291 | NVM_NUM_OF_SECTIONS, | |
292 | }; | |
293 | ||
294 | /** | |
295 | * struct iwl_nvm_access_cmd_ver2 - Request the device to send an NVM section | |
296 | * @op_code: 0 - read, 1 - write | |
297 | * @target: NVM_ACCESS_TARGET_* | |
298 | * @type: NVM_SECTION_TYPE_* | |
299 | * @offset: offset in bytes into the section | |
300 | * @length: in bytes, to read/write | |
301 | * @data: if write operation, the data to write. On read its empty | |
302 | */ | |
b9545b48 | 303 | struct iwl_nvm_access_cmd { |
8ca151b5 JB |
304 | u8 op_code; |
305 | u8 target; | |
306 | __le16 type; | |
307 | __le16 offset; | |
308 | __le16 length; | |
309 | u8 data[]; | |
310 | } __packed; /* NVM_ACCESS_CMD_API_S_VER_2 */ | |
311 | ||
312 | /** | |
313 | * struct iwl_nvm_access_resp_ver2 - response to NVM_ACCESS_CMD | |
314 | * @offset: offset in bytes into the section | |
315 | * @length: in bytes, either how much was written or read | |
316 | * @type: NVM_SECTION_TYPE_* | |
317 | * @status: 0 for success, fail otherwise | |
318 | * @data: if read operation, the data returned. Empty on write. | |
319 | */ | |
b9545b48 | 320 | struct iwl_nvm_access_resp { |
8ca151b5 JB |
321 | __le16 offset; |
322 | __le16 length; | |
323 | __le16 type; | |
324 | __le16 status; | |
325 | u8 data[]; | |
326 | } __packed; /* NVM_ACCESS_CMD_RESP_API_S_VER_2 */ | |
327 | ||
328 | /* MVM_ALIVE 0x1 */ | |
329 | ||
330 | /* alive response is_valid values */ | |
331 | #define ALIVE_RESP_UCODE_OK BIT(0) | |
332 | #define ALIVE_RESP_RFKILL BIT(1) | |
333 | ||
334 | /* alive response ver_type values */ | |
335 | enum { | |
336 | FW_TYPE_HW = 0, | |
337 | FW_TYPE_PROT = 1, | |
338 | FW_TYPE_AP = 2, | |
339 | FW_TYPE_WOWLAN = 3, | |
340 | FW_TYPE_TIMING = 4, | |
341 | FW_TYPE_WIPAN = 5 | |
342 | }; | |
343 | ||
344 | /* alive response ver_subtype values */ | |
345 | enum { | |
346 | FW_SUBTYPE_FULL_FEATURE = 0, | |
347 | FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ | |
348 | FW_SUBTYPE_REDUCED = 2, | |
349 | FW_SUBTYPE_ALIVE_ONLY = 3, | |
350 | FW_SUBTYPE_WOWLAN = 4, | |
351 | FW_SUBTYPE_AP_SUBTYPE = 5, | |
352 | FW_SUBTYPE_WIPAN = 6, | |
353 | FW_SUBTYPE_INITIALIZE = 9 | |
354 | }; | |
355 | ||
356 | #define IWL_ALIVE_STATUS_ERR 0xDEAD | |
357 | #define IWL_ALIVE_STATUS_OK 0xCAFE | |
358 | ||
359 | #define IWL_ALIVE_FLG_RFKILL BIT(0) | |
360 | ||
361 | struct mvm_alive_resp { | |
362 | __le16 status; | |
363 | __le16 flags; | |
364 | u8 ucode_minor; | |
365 | u8 ucode_major; | |
366 | __le16 id; | |
367 | u8 api_minor; | |
368 | u8 api_major; | |
369 | u8 ver_subtype; | |
370 | u8 ver_type; | |
371 | u8 mac; | |
372 | u8 opt; | |
373 | __le16 reserved2; | |
374 | __le32 timestamp; | |
375 | __le32 error_event_table_ptr; /* SRAM address for error log */ | |
376 | __le32 log_event_table_ptr; /* SRAM address for event log */ | |
377 | __le32 cpu_register_ptr; | |
378 | __le32 dbgm_config_ptr; | |
379 | __le32 alive_counter_ptr; | |
380 | __le32 scd_base_ptr; /* SRAM address for SCD */ | |
381 | } __packed; /* ALIVE_RES_API_S_VER_1 */ | |
382 | ||
383 | /* Error response/notification */ | |
384 | enum { | |
385 | FW_ERR_UNKNOWN_CMD = 0x0, | |
386 | FW_ERR_INVALID_CMD_PARAM = 0x1, | |
387 | FW_ERR_SERVICE = 0x2, | |
388 | FW_ERR_ARC_MEMORY = 0x3, | |
389 | FW_ERR_ARC_CODE = 0x4, | |
390 | FW_ERR_WATCH_DOG = 0x5, | |
391 | FW_ERR_WEP_GRP_KEY_INDX = 0x10, | |
392 | FW_ERR_WEP_KEY_SIZE = 0x11, | |
393 | FW_ERR_OBSOLETE_FUNC = 0x12, | |
394 | FW_ERR_UNEXPECTED = 0xFE, | |
395 | FW_ERR_FATAL = 0xFF | |
396 | }; | |
397 | ||
398 | /** | |
399 | * struct iwl_error_resp - FW error indication | |
400 | * ( REPLY_ERROR = 0x2 ) | |
401 | * @error_type: one of FW_ERR_* | |
402 | * @cmd_id: the command ID for which the error occured | |
403 | * @bad_cmd_seq_num: sequence number of the erroneous command | |
404 | * @error_service: which service created the error, applicable only if | |
405 | * error_type = 2, otherwise 0 | |
406 | * @timestamp: TSF in usecs. | |
407 | */ | |
408 | struct iwl_error_resp { | |
409 | __le32 error_type; | |
410 | u8 cmd_id; | |
411 | u8 reserved1; | |
412 | __le16 bad_cmd_seq_num; | |
413 | __le32 error_service; | |
414 | __le64 timestamp; | |
415 | } __packed; | |
416 | ||
417 | ||
418 | /* Common PHY, MAC and Bindings definitions */ | |
419 | ||
420 | #define MAX_MACS_IN_BINDING (3) | |
421 | #define MAX_BINDINGS (4) | |
422 | #define AUX_BINDING_INDEX (3) | |
423 | #define MAX_PHYS (4) | |
424 | ||
425 | /* Used to extract ID and color from the context dword */ | |
426 | #define FW_CTXT_ID_POS (0) | |
427 | #define FW_CTXT_ID_MSK (0xff << FW_CTXT_ID_POS) | |
428 | #define FW_CTXT_COLOR_POS (8) | |
429 | #define FW_CTXT_COLOR_MSK (0xff << FW_CTXT_COLOR_POS) | |
430 | #define FW_CTXT_INVALID (0xffffffff) | |
431 | ||
432 | #define FW_CMD_ID_AND_COLOR(_id, _color) ((_id << FW_CTXT_ID_POS) |\ | |
433 | (_color << FW_CTXT_COLOR_POS)) | |
434 | ||
435 | /* Possible actions on PHYs, MACs and Bindings */ | |
436 | enum { | |
437 | FW_CTXT_ACTION_STUB = 0, | |
438 | FW_CTXT_ACTION_ADD, | |
439 | FW_CTXT_ACTION_MODIFY, | |
440 | FW_CTXT_ACTION_REMOVE, | |
441 | FW_CTXT_ACTION_NUM | |
442 | }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ | |
443 | ||
444 | /* Time Events */ | |
445 | ||
446 | /* Time Event types, according to MAC type */ | |
447 | enum iwl_time_event_type { | |
448 | /* BSS Station Events */ | |
449 | TE_BSS_STA_AGGRESSIVE_ASSOC, | |
450 | TE_BSS_STA_ASSOC, | |
451 | TE_BSS_EAP_DHCP_PROT, | |
452 | TE_BSS_QUIET_PERIOD, | |
453 | ||
454 | /* P2P Device Events */ | |
455 | TE_P2P_DEVICE_DISCOVERABLE, | |
456 | TE_P2P_DEVICE_LISTEN, | |
457 | TE_P2P_DEVICE_ACTION_SCAN, | |
458 | TE_P2P_DEVICE_FULL_SCAN, | |
459 | ||
460 | /* P2P Client Events */ | |
461 | TE_P2P_CLIENT_AGGRESSIVE_ASSOC, | |
462 | TE_P2P_CLIENT_ASSOC, | |
463 | TE_P2P_CLIENT_QUIET_PERIOD, | |
464 | ||
465 | /* P2P GO Events */ | |
466 | TE_P2P_GO_ASSOC_PROT, | |
467 | TE_P2P_GO_REPETITIVE_NOA, | |
468 | TE_P2P_GO_CT_WINDOW, | |
469 | ||
470 | /* WiDi Sync Events */ | |
471 | TE_WIDI_TX_SYNC, | |
472 | ||
473 | TE_MAX | |
474 | }; /* MAC_EVENT_TYPE_API_E_VER_1 */ | |
475 | ||
476 | /* Time Event dependencies: none, on another TE, or in a specific time */ | |
477 | enum { | |
478 | TE_INDEPENDENT = 0, | |
479 | TE_DEP_OTHER = 1, | |
480 | TE_DEP_TSF = 2, | |
481 | TE_EVENT_SOCIOPATHIC = 4, | |
482 | }; /* MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ | |
483 | ||
484 | /* When to send Time Event notifications and to whom (internal = FW) */ | |
485 | enum { | |
486 | TE_NOTIF_NONE = 0, | |
487 | TE_NOTIF_HOST_START = 0x1, | |
488 | TE_NOTIF_HOST_END = 0x2, | |
489 | TE_NOTIF_INTERNAL_START = 0x4, | |
490 | TE_NOTIF_INTERNAL_END = 0x8 | |
491 | }; /* MAC_EVENT_ACTION_API_E_VER_1 */ | |
492 | ||
493 | /* | |
494 | * @TE_FRAG_NONE: fragmentation of the time event is NOT allowed. | |
495 | * @TE_FRAG_SINGLE: fragmentation of the time event is allowed, but only | |
496 | * the first fragment is scheduled. | |
497 | * @TE_FRAG_DUAL: fragmentation of the time event is allowed, but only | |
498 | * the first 2 fragments are scheduled. | |
499 | * @TE_FRAG_ENDLESS: fragmentation of the time event is allowed, and any number | |
500 | * of fragments are valid. | |
501 | * | |
502 | * Other than the constant defined above, specifying a fragmentation value 'x' | |
503 | * means that the event can be fragmented but only the first 'x' will be | |
504 | * scheduled. | |
505 | */ | |
506 | enum { | |
507 | TE_FRAG_NONE = 0, | |
508 | TE_FRAG_SINGLE = 1, | |
509 | TE_FRAG_DUAL = 2, | |
510 | TE_FRAG_ENDLESS = 0xffffffff | |
511 | }; | |
512 | ||
513 | /* Repeat the time event endlessly (until removed) */ | |
514 | #define TE_REPEAT_ENDLESS (0xffffffff) | |
515 | /* If a Time Event has bounded repetitions, this is the maximal value */ | |
516 | #define TE_REPEAT_MAX_MSK (0x0fffffff) | |
517 | /* If a Time Event can be fragmented, this is the max number of fragments */ | |
518 | #define TE_FRAG_MAX_MSK (0x0fffffff) | |
519 | ||
520 | /** | |
521 | * struct iwl_time_event_cmd - configuring Time Events | |
522 | * ( TIME_EVENT_CMD = 0x29 ) | |
523 | * @id_and_color: ID and color of the relevant MAC | |
524 | * @action: action to perform, one of FW_CTXT_ACTION_* | |
525 | * @id: this field has two meanings, depending on the action: | |
526 | * If the action is ADD, then it means the type of event to add. | |
527 | * For all other actions it is the unique event ID assigned when the | |
528 | * event was added by the FW. | |
529 | * @apply_time: When to start the Time Event (in GP2) | |
530 | * @max_delay: maximum delay to event's start (apply time), in TU | |
531 | * @depends_on: the unique ID of the event we depend on (if any) | |
532 | * @interval: interval between repetitions, in TU | |
533 | * @interval_reciprocal: 2^32 / interval | |
534 | * @duration: duration of event in TU | |
535 | * @repeat: how many repetitions to do, can be TE_REPEAT_ENDLESS | |
536 | * @dep_policy: one of TE_INDEPENDENT, TE_DEP_OTHER, TE_DEP_TSF | |
537 | * @is_present: 0 or 1, are we present or absent during the Time Event | |
538 | * @max_frags: maximal number of fragments the Time Event can be divided to | |
539 | * @notify: notifications using TE_NOTIF_* (whom to notify when) | |
540 | */ | |
541 | struct iwl_time_event_cmd { | |
542 | /* COMMON_INDEX_HDR_API_S_VER_1 */ | |
543 | __le32 id_and_color; | |
544 | __le32 action; | |
545 | __le32 id; | |
546 | /* MAC_TIME_EVENT_DATA_API_S_VER_1 */ | |
547 | __le32 apply_time; | |
548 | __le32 max_delay; | |
549 | __le32 dep_policy; | |
550 | __le32 depends_on; | |
551 | __le32 is_present; | |
552 | __le32 max_frags; | |
553 | __le32 interval; | |
554 | __le32 interval_reciprocal; | |
555 | __le32 duration; | |
556 | __le32 repeat; | |
557 | __le32 notify; | |
558 | } __packed; /* MAC_TIME_EVENT_CMD_API_S_VER_1 */ | |
559 | ||
560 | /** | |
561 | * struct iwl_time_event_resp - response structure to iwl_time_event_cmd | |
562 | * @status: bit 0 indicates success, all others specify errors | |
563 | * @id: the Time Event type | |
564 | * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE | |
565 | * @id_and_color: ID and color of the relevant MAC | |
566 | */ | |
567 | struct iwl_time_event_resp { | |
568 | __le32 status; | |
569 | __le32 id; | |
570 | __le32 unique_id; | |
571 | __le32 id_and_color; | |
572 | } __packed; /* MAC_TIME_EVENT_RSP_API_S_VER_1 */ | |
573 | ||
574 | /** | |
575 | * struct iwl_time_event_notif - notifications of time event start/stop | |
576 | * ( TIME_EVENT_NOTIFICATION = 0x2a ) | |
577 | * @timestamp: action timestamp in GP2 | |
578 | * @session_id: session's unique id | |
579 | * @unique_id: unique id of the Time Event itself | |
580 | * @id_and_color: ID and color of the relevant MAC | |
581 | * @action: one of TE_NOTIF_START or TE_NOTIF_END | |
582 | * @status: true if scheduled, false otherwise (not executed) | |
583 | */ | |
584 | struct iwl_time_event_notif { | |
585 | __le32 timestamp; | |
586 | __le32 session_id; | |
587 | __le32 unique_id; | |
588 | __le32 id_and_color; | |
589 | __le32 action; | |
590 | __le32 status; | |
591 | } __packed; /* MAC_TIME_EVENT_NTFY_API_S_VER_1 */ | |
592 | ||
593 | ||
594 | /* Bindings and Time Quota */ | |
595 | ||
596 | /** | |
597 | * struct iwl_binding_cmd - configuring bindings | |
598 | * ( BINDING_CONTEXT_CMD = 0x2b ) | |
599 | * @id_and_color: ID and color of the relevant Binding | |
600 | * @action: action to perform, one of FW_CTXT_ACTION_* | |
601 | * @macs: array of MAC id and colors which belong to the binding | |
602 | * @phy: PHY id and color which belongs to the binding | |
603 | */ | |
604 | struct iwl_binding_cmd { | |
605 | /* COMMON_INDEX_HDR_API_S_VER_1 */ | |
606 | __le32 id_and_color; | |
607 | __le32 action; | |
608 | /* BINDING_DATA_API_S_VER_1 */ | |
609 | __le32 macs[MAX_MACS_IN_BINDING]; | |
610 | __le32 phy; | |
611 | } __packed; /* BINDING_CMD_API_S_VER_1 */ | |
612 | ||
35adfd6e IP |
613 | /* The maximal number of fragments in the FW's schedule session */ |
614 | #define IWL_MVM_MAX_QUOTA 128 | |
615 | ||
8ca151b5 JB |
616 | /** |
617 | * struct iwl_time_quota_data - configuration of time quota per binding | |
618 | * @id_and_color: ID and color of the relevant Binding | |
619 | * @quota: absolute time quota in TU. The scheduler will try to divide the | |
620 | * remainig quota (after Time Events) according to this quota. | |
621 | * @max_duration: max uninterrupted context duration in TU | |
622 | */ | |
623 | struct iwl_time_quota_data { | |
624 | __le32 id_and_color; | |
625 | __le32 quota; | |
626 | __le32 max_duration; | |
627 | } __packed; /* TIME_QUOTA_DATA_API_S_VER_1 */ | |
628 | ||
629 | /** | |
630 | * struct iwl_time_quota_cmd - configuration of time quota between bindings | |
631 | * ( TIME_QUOTA_CMD = 0x2c ) | |
632 | * @quotas: allocations per binding | |
633 | */ | |
634 | struct iwl_time_quota_cmd { | |
635 | struct iwl_time_quota_data quotas[MAX_BINDINGS]; | |
636 | } __packed; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ | |
637 | ||
638 | ||
639 | /* PHY context */ | |
640 | ||
641 | /* Supported bands */ | |
642 | #define PHY_BAND_5 (0) | |
643 | #define PHY_BAND_24 (1) | |
644 | ||
645 | /* Supported channel width, vary if there is VHT support */ | |
646 | #define PHY_VHT_CHANNEL_MODE20 (0x0) | |
647 | #define PHY_VHT_CHANNEL_MODE40 (0x1) | |
648 | #define PHY_VHT_CHANNEL_MODE80 (0x2) | |
649 | #define PHY_VHT_CHANNEL_MODE160 (0x3) | |
650 | ||
651 | /* | |
652 | * Control channel position: | |
653 | * For legacy set bit means upper channel, otherwise lower. | |
654 | * For VHT - bit-2 marks if the control is lower/upper relative to center-freq | |
655 | * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. | |
656 | * center_freq | |
657 | * | | |
658 | * 40Mhz |_______|_______| | |
659 | * 80Mhz |_______|_______|_______|_______| | |
660 | * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| | |
661 | * code 011 010 001 000 | 100 101 110 111 | |
662 | */ | |
663 | #define PHY_VHT_CTRL_POS_1_BELOW (0x0) | |
664 | #define PHY_VHT_CTRL_POS_2_BELOW (0x1) | |
665 | #define PHY_VHT_CTRL_POS_3_BELOW (0x2) | |
666 | #define PHY_VHT_CTRL_POS_4_BELOW (0x3) | |
667 | #define PHY_VHT_CTRL_POS_1_ABOVE (0x4) | |
668 | #define PHY_VHT_CTRL_POS_2_ABOVE (0x5) | |
669 | #define PHY_VHT_CTRL_POS_3_ABOVE (0x6) | |
670 | #define PHY_VHT_CTRL_POS_4_ABOVE (0x7) | |
671 | ||
672 | /* | |
673 | * @band: PHY_BAND_* | |
674 | * @channel: channel number | |
675 | * @width: PHY_[VHT|LEGACY]_CHANNEL_* | |
676 | * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* | |
677 | */ | |
678 | struct iwl_fw_channel_info { | |
679 | u8 band; | |
680 | u8 channel; | |
681 | u8 width; | |
682 | u8 ctrl_pos; | |
683 | } __packed; | |
684 | ||
685 | #define PHY_RX_CHAIN_DRIVER_FORCE_POS (0) | |
686 | #define PHY_RX_CHAIN_DRIVER_FORCE_MSK \ | |
687 | (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS) | |
688 | #define PHY_RX_CHAIN_VALID_POS (1) | |
689 | #define PHY_RX_CHAIN_VALID_MSK \ | |
690 | (0x7 << PHY_RX_CHAIN_VALID_POS) | |
691 | #define PHY_RX_CHAIN_FORCE_SEL_POS (4) | |
692 | #define PHY_RX_CHAIN_FORCE_SEL_MSK \ | |
693 | (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS) | |
694 | #define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) | |
695 | #define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ | |
696 | (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) | |
697 | #define PHY_RX_CHAIN_CNT_POS (10) | |
698 | #define PHY_RX_CHAIN_CNT_MSK \ | |
699 | (0x3 << PHY_RX_CHAIN_CNT_POS) | |
700 | #define PHY_RX_CHAIN_MIMO_CNT_POS (12) | |
701 | #define PHY_RX_CHAIN_MIMO_CNT_MSK \ | |
702 | (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS) | |
703 | #define PHY_RX_CHAIN_MIMO_FORCE_POS (14) | |
704 | #define PHY_RX_CHAIN_MIMO_FORCE_MSK \ | |
705 | (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS) | |
706 | ||
707 | /* TODO: fix the value, make it depend on firmware at runtime? */ | |
708 | #define NUM_PHY_CTX 3 | |
709 | ||
710 | /* TODO: complete missing documentation */ | |
711 | /** | |
712 | * struct iwl_phy_context_cmd - config of the PHY context | |
713 | * ( PHY_CONTEXT_CMD = 0x8 ) | |
714 | * @id_and_color: ID and color of the relevant Binding | |
715 | * @action: action to perform, one of FW_CTXT_ACTION_* | |
716 | * @apply_time: 0 means immediate apply and context switch. | |
717 | * other value means apply new params after X usecs | |
718 | * @tx_param_color: ??? | |
719 | * @channel_info: | |
720 | * @txchain_info: ??? | |
721 | * @rxchain_info: ??? | |
722 | * @acquisition_data: ??? | |
723 | * @dsp_cfg_flags: set to 0 | |
724 | */ | |
725 | struct iwl_phy_context_cmd { | |
726 | /* COMMON_INDEX_HDR_API_S_VER_1 */ | |
727 | __le32 id_and_color; | |
728 | __le32 action; | |
729 | /* PHY_CONTEXT_DATA_API_S_VER_1 */ | |
730 | __le32 apply_time; | |
731 | __le32 tx_param_color; | |
732 | struct iwl_fw_channel_info ci; | |
733 | __le32 txchain_info; | |
734 | __le32 rxchain_info; | |
735 | __le32 acquisition_data; | |
736 | __le32 dsp_cfg_flags; | |
737 | } __packed; /* PHY_CONTEXT_CMD_API_VER_1 */ | |
738 | ||
739 | #define IWL_RX_INFO_PHY_CNT 8 | |
740 | #define IWL_RX_INFO_AGC_IDX 1 | |
741 | #define IWL_RX_INFO_RSSI_AB_IDX 2 | |
8101a7f0 EG |
742 | #define IWL_OFDM_AGC_A_MSK 0x0000007f |
743 | #define IWL_OFDM_AGC_A_POS 0 | |
744 | #define IWL_OFDM_AGC_B_MSK 0x00003f80 | |
745 | #define IWL_OFDM_AGC_B_POS 7 | |
746 | #define IWL_OFDM_AGC_CODE_MSK 0x3fe00000 | |
747 | #define IWL_OFDM_AGC_CODE_POS 20 | |
8ca151b5 | 748 | #define IWL_OFDM_RSSI_INBAND_A_MSK 0x00ff |
8ca151b5 | 749 | #define IWL_OFDM_RSSI_A_POS 0 |
8101a7f0 EG |
750 | #define IWL_OFDM_RSSI_ALLBAND_A_MSK 0xff00 |
751 | #define IWL_OFDM_RSSI_ALLBAND_A_POS 8 | |
8ca151b5 | 752 | #define IWL_OFDM_RSSI_INBAND_B_MSK 0xff0000 |
8ca151b5 | 753 | #define IWL_OFDM_RSSI_B_POS 16 |
8101a7f0 EG |
754 | #define IWL_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 |
755 | #define IWL_OFDM_RSSI_ALLBAND_B_POS 24 | |
8ca151b5 JB |
756 | |
757 | /** | |
758 | * struct iwl_rx_phy_info - phy info | |
759 | * (REPLY_RX_PHY_CMD = 0xc0) | |
760 | * @non_cfg_phy_cnt: non configurable DSP phy data byte count | |
761 | * @cfg_phy_cnt: configurable DSP phy data byte count | |
762 | * @stat_id: configurable DSP phy data set ID | |
763 | * @reserved1: | |
764 | * @system_timestamp: GP2 at on air rise | |
765 | * @timestamp: TSF at on air rise | |
766 | * @beacon_time_stamp: beacon at on-air rise | |
767 | * @phy_flags: general phy flags: band, modulation, ... | |
768 | * @channel: channel number | |
769 | * @non_cfg_phy_buf: for various implementations of non_cfg_phy | |
770 | * @rate_n_flags: RATE_MCS_* | |
771 | * @byte_count: frame's byte-count | |
772 | * @frame_time: frame's time on the air, based on byte count and frame rate | |
773 | * calculation | |
6bfcb7e8 | 774 | * @mac_active_msk: what MACs were active when the frame was received |
8ca151b5 JB |
775 | * |
776 | * Before each Rx, the device sends this data. It contains PHY information | |
777 | * about the reception of the packet. | |
778 | */ | |
779 | struct iwl_rx_phy_info { | |
780 | u8 non_cfg_phy_cnt; | |
781 | u8 cfg_phy_cnt; | |
782 | u8 stat_id; | |
783 | u8 reserved1; | |
784 | __le32 system_timestamp; | |
785 | __le64 timestamp; | |
786 | __le32 beacon_time_stamp; | |
787 | __le16 phy_flags; | |
788 | __le16 channel; | |
789 | __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; | |
790 | __le32 rate_n_flags; | |
791 | __le32 byte_count; | |
6bfcb7e8 | 792 | __le16 mac_active_msk; |
8ca151b5 JB |
793 | __le16 frame_time; |
794 | } __packed; | |
795 | ||
796 | struct iwl_rx_mpdu_res_start { | |
797 | __le16 byte_count; | |
798 | __le16 reserved; | |
799 | } __packed; | |
800 | ||
801 | /** | |
802 | * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags | |
803 | * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band | |
804 | * @RX_RES_PHY_FLAGS_MOD_CCK: | |
805 | * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short | |
806 | * @RX_RES_PHY_FLAGS_NARROW_BAND: | |
807 | * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received | |
808 | * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU | |
809 | * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame | |
810 | * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble | |
811 | * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame | |
812 | */ | |
813 | enum iwl_rx_phy_flags { | |
814 | RX_RES_PHY_FLAGS_BAND_24 = BIT(0), | |
815 | RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), | |
816 | RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), | |
817 | RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), | |
818 | RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), | |
819 | RX_RES_PHY_FLAGS_ANTENNA_POS = 4, | |
820 | RX_RES_PHY_FLAGS_AGG = BIT(7), | |
821 | RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), | |
822 | RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), | |
823 | RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), | |
824 | }; | |
825 | ||
826 | /** | |
827 | * enum iwl_mvm_rx_status - written by fw for each Rx packet | |
828 | * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine | |
829 | * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow | |
830 | * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: | |
831 | * @RX_MPDU_RES_STATUS_KEY_VALID: | |
832 | * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: | |
833 | * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed | |
834 | * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked | |
835 | * in the driver. | |
836 | * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine | |
837 | * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or | |
838 | * alg = CCM only. Checks replay attack for 11w frames. Relevant only if | |
839 | * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. | |
840 | * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted | |
841 | * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP | |
842 | * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM | |
843 | * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP | |
844 | * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC | |
845 | * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted | |
846 | * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm | |
847 | * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted | |
848 | * @RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: | |
849 | * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: | |
850 | * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: | |
851 | * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame | |
852 | * @RX_MPDU_RES_STATUS_HASH_INDEX_MSK: | |
853 | * @RX_MPDU_RES_STATUS_STA_ID_MSK: | |
854 | * @RX_MPDU_RES_STATUS_RRF_KILL: | |
855 | * @RX_MPDU_RES_STATUS_FILTERING_MSK: | |
856 | * @RX_MPDU_RES_STATUS2_FILTERING_MSK: | |
857 | */ | |
858 | enum iwl_mvm_rx_status { | |
859 | RX_MPDU_RES_STATUS_CRC_OK = BIT(0), | |
860 | RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), | |
861 | RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), | |
862 | RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), | |
863 | RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4), | |
864 | RX_MPDU_RES_STATUS_ICV_OK = BIT(5), | |
865 | RX_MPDU_RES_STATUS_MIC_OK = BIT(6), | |
866 | RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), | |
867 | RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), | |
868 | RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), | |
869 | RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), | |
870 | RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), | |
871 | RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), | |
872 | RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), | |
873 | RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), | |
874 | RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), | |
875 | RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), | |
876 | RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = BIT(12), | |
877 | RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13), | |
878 | RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14), | |
879 | RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15), | |
880 | RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), | |
881 | RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), | |
882 | RX_MPDU_RES_STATUS_RRF_KILL = BIT(29), | |
883 | RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), | |
884 | RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), | |
885 | }; | |
886 | ||
887 | /** | |
888 | * struct iwl_radio_version_notif - information on the radio version | |
889 | * ( RADIO_VERSION_NOTIFICATION = 0x68 ) | |
890 | * @radio_flavor: | |
891 | * @radio_step: | |
892 | * @radio_dash: | |
893 | */ | |
894 | struct iwl_radio_version_notif { | |
895 | __le32 radio_flavor; | |
896 | __le32 radio_step; | |
897 | __le32 radio_dash; | |
898 | } __packed; /* RADIO_VERSION_NOTOFICATION_S_VER_1 */ | |
899 | ||
900 | enum iwl_card_state_flags { | |
901 | CARD_ENABLED = 0x00, | |
902 | HW_CARD_DISABLED = 0x01, | |
903 | SW_CARD_DISABLED = 0x02, | |
904 | CT_KILL_CARD_DISABLED = 0x04, | |
905 | HALT_CARD_DISABLED = 0x08, | |
906 | CARD_DISABLED_MSK = 0x0f, | |
907 | CARD_IS_RX_ON = 0x10, | |
908 | }; | |
909 | ||
910 | /** | |
911 | * struct iwl_radio_version_notif - information on the radio version | |
912 | * ( CARD_STATE_NOTIFICATION = 0xa1 ) | |
913 | * @flags: %iwl_card_state_flags | |
914 | */ | |
915 | struct iwl_card_state_notif { | |
916 | __le32 flags; | |
917 | } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ | |
918 | ||
919 | /** | |
920 | * struct iwl_set_calib_default_cmd - set default value for calibration. | |
921 | * ( SET_CALIB_DEFAULT_CMD = 0x8e ) | |
922 | * @calib_index: the calibration to set value for | |
923 | * @length: of data | |
924 | * @data: the value to set for the calibration result | |
925 | */ | |
926 | struct iwl_set_calib_default_cmd { | |
927 | __le16 calib_index; | |
928 | __le16 length; | |
929 | u8 data[0]; | |
930 | } __packed; /* PHY_CALIB_OVERRIDE_VALUES_S */ | |
931 | ||
932 | #endif /* __fw_api_h__ */ |