projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mac80211: adjustable number of bits for qdisc pool
[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
b481de9c
ZY		 49#include "iwl-3945.h"
50#include "iwl-helpers.h"
51
c8b0e6e1 52#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 53u32 iwl3945_debug_level;
b481de9c
ZY		 54#endif
55
bb8c093b
CH		 56static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
57 struct iwl3945_tx_queue *txq);
416e1438 58
b481de9c
ZY		 59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
65/* module parameters */
6440adb5
CB		 66static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
67static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
68static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 69static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 70int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
71static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
72int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
c8b0e6e1 82#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 83#define VD "d"
84#else
85#define VD
86#endif
87
c8b0e6e1 88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 89#define VS "s"
90#else
91#define VS
92#endif
93
71972664 94#define IWLWIFI_VERSION "1.2.23k" VD VS
b481de9c
ZY		 95#define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
96#define DRV_VERSION IWLWIFI_VERSION
97
98/* Change firmware file name, using "-" and incrementing number,
99 * *only* when uCode interface or architecture changes so that it
100 * is not compatible with earlier drivers.
101 * This number will also appear in << 8 position of 1st dword of uCode file */
102#define IWL3945_UCODE_API "-1"
103
104MODULE_DESCRIPTION(DRV_DESCRIPTION);
105MODULE_VERSION(DRV_VERSION);
106MODULE_AUTHOR(DRV_COPYRIGHT);
107MODULE_LICENSE("GPL");
108
416e1438 109static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
b481de9c
ZY		 110{
111 u16 fc = le16_to_cpu(hdr->frame_control);
112 int hdr_len = ieee80211_get_hdrlen(fc);
113
114 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
115 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
116 return NULL;
117}
118
8318d78a
JB		 119static const struct ieee80211_supported_band *iwl3945_get_band(
120 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 121{
8318d78a 122 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 123}
124
bb8c093b 125static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 126{
127 /* Single white space is for Linksys APs */
128 if (essid_len == 1 && essid[0] == ' ')
129 return 1;
130
131 /* Otherwise, if the entire essid is 0, we assume it is hidden */
132 while (essid_len) {
133 essid_len--;
134 if (essid[essid_len] != '\0')
135 return 0;
136 }
137
138 return 1;
139}
140
bb8c093b 141static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 142{
143 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
144 const char *s = essid;
145 char *d = escaped;
146
bb8c093b 147 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 148 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
149 return escaped;
150 }
151
152 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
153 while (essid_len--) {
154 if (*s == '\0') {
155 *d++ = '\\';
156 *d++ = '0';
157 s++;
158 } else
159 *d++ = *s++;
160 }
161 *d = '\0';
162 return escaped;
163}
164
bb8c093b 165static void iwl3945_print_hex_dump(int level, void *p, u32 len)
b481de9c 166{
c8b0e6e1 167#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 168 if (!(iwl3945_debug_level & level))
b481de9c
ZY		 169 return;
170
171 print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
172 p, len, 1);
173#endif
174}
175
176/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
177 * DMA services
178 *
179 * Theory of operation
180 *
6440adb5
CB		 181 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
182 * of buffer descriptors, each of which points to one or more data buffers for
183 * the device to read from or fill. Driver and device exchange status of each
184 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
185 * entries in each circular buffer, to protect against confusing empty and full
186 * queue states.
187 *
188 * The device reads or writes the data in the queues via the device's several
189 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 190 *
191 * For Tx queue, there are low mark and high mark limits. If, after queuing
192 * the packet for Tx, free space become < low mark, Tx queue stopped. When
193 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
194 * Tx queue resumed.
195 *
6440adb5
CB		 196 * The 3945 operates with six queues: One receive queue, one transmit queue
197 * (#4) for sending commands to the device firmware, and four transmit queues
198 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 199 ***************************************************/
200
bb8c093b 201static int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 202{
fc4b6853 203 int s = q->read_ptr - q->write_ptr;
b481de9c 204
fc4b6853 205 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 206 s -= q->n_bd;
207
208 if (s <= 0)
209 s += q->n_window;
210 /* keep some reserve to not confuse empty and full situations */
211 s -= 2;
212 if (s < 0)
213 s = 0;
214 return s;
215}
216
6440adb5
CB		 217/**
218 * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning
219 * @index -- current index
220 * @n_bd -- total number of entries in queue (must be power of 2)
221 */
bb8c093b 222static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
b481de9c
ZY		 223{
224 return ++index & (n_bd - 1);
225}
226
6440adb5
CB		 227/**
228 * iwl3945_queue_dec_wrap - increment queue index, wrap back to end
229 * @index -- current index
230 * @n_bd -- total number of entries in queue (must be power of 2)
231 */
bb8c093b 232static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 233{
234 return --index & (n_bd - 1);
235}
236
bb8c093b 237static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 238{
fc4b6853
TW		 239 return q->write_ptr > q->read_ptr ?
240 (i >= q->read_ptr && i < q->write_ptr) :
241 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 242}
243
bb8c093b 244static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 245{
6440adb5 246 /* This is for scan command, the big buffer at end of command array */
b481de9c 247 if (is_huge)
6440adb5 248 return q->n_window; /* must be power of 2 */
b481de9c 249
6440adb5 250 /* Otherwise, use normal size buffers */
b481de9c
ZY		 251 return index & (q->n_window - 1);
252}
253
6440adb5
CB		 254/**
255 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
256 */
bb8c093b 257static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 258 int count, int slots_num, u32 id)
259{
260 q->n_bd = count;
261 q->n_window = slots_num;
262 q->id = id;
263
bb8c093b
CH		 264 /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
265 * and iwl3945_queue_dec_wrap are broken. */
b481de9c
ZY		 266 BUG_ON(!is_power_of_2(count));
267
268 /* slots_num must be power-of-two size, otherwise
269 * get_cmd_index is broken. */
270 BUG_ON(!is_power_of_2(slots_num));
271
272 q->low_mark = q->n_window / 4;
273 if (q->low_mark < 4)
274 q->low_mark = 4;
275
276 q->high_mark = q->n_window / 8;
277 if (q->high_mark < 2)
278 q->high_mark = 2;
279
fc4b6853 280 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 281
282 return 0;
283}
284
6440adb5
CB		 285/**
286 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
287 */
bb8c093b
CH		 288static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
289 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 290{
291 struct pci_dev *dev = priv->pci_dev;
292
6440adb5
CB		 293 /* Driver private data, only for Tx (not command) queues,
294 * not shared with device. */
b481de9c
ZY		 295 if (id != IWL_CMD_QUEUE_NUM) {
296 txq->txb = kmalloc(sizeof(txq->txb[0]) *
297 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
298 if (!txq->txb) {
01ebd063 299 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 300 "structures failed\n");
301 goto error;
302 }
303 } else
304 txq->txb = NULL;
305
6440adb5
CB		 306 /* Circular buffer of transmit frame descriptors (TFDs),
307 * shared with device */
b481de9c
ZY		 308 txq->bd = pci_alloc_consistent(dev,
309 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
310 &txq->q.dma_addr);
311
312 if (!txq->bd) {
313 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
314 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
315 goto error;
316 }
317 txq->q.id = id;
318
319 return 0;
320
321 error:
322 if (txq->txb) {
323 kfree(txq->txb);
324 txq->txb = NULL;
325 }
326
327 return -ENOMEM;
328}
329
6440adb5
CB		 330/**
331 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
332 */
bb8c093b
CH		 333int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
334 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 335{
336 struct pci_dev *dev = priv->pci_dev;
337 int len;
338 int rc = 0;
339
6440adb5
CB		 340 /*
341 * Alloc buffer array for commands (Tx or other types of commands).
342 * For the command queue (#4), allocate command space + one big
343 * command for scan, since scan command is very huge; the system will
344 * not have two scans at the same time, so only one is needed.
345 * For data Tx queues (all other queues), no super-size command
346 * space is needed.
347 */
bb8c093b 348 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 349 if (txq_id == IWL_CMD_QUEUE_NUM)
350 len += IWL_MAX_SCAN_SIZE;
351 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
352 if (!txq->cmd)
353 return -ENOMEM;
354
6440adb5 355 /* Alloc driver data array and TFD circular buffer */
bb8c093b 356 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 357 if (rc) {
358 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
359
360 return -ENOMEM;
361 }
362 txq->need_update = 0;
363
364 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
bb8c093b 365 * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
b481de9c 366 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 367
368 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 369 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 370
6440adb5 371 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 372 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 373
374 return 0;
375}
376
377/**
bb8c093b 378 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 379 * @txq: Transmit queue to deallocate.
380 *
381 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 382 * Free all buffers.
383 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 384 */
bb8c093b 385void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 386{
bb8c093b 387 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 388 struct pci_dev *dev = priv->pci_dev;
389 int len;
390
391 if (q->n_bd == 0)
392 return;
393
394 /* first, empty all BD's */
fc4b6853 395 for (; q->write_ptr != q->read_ptr;
bb8c093b
CH		 396 q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
397 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 398
bb8c093b 399 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 400 if (q->id == IWL_CMD_QUEUE_NUM)
401 len += IWL_MAX_SCAN_SIZE;
402
6440adb5 403 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 404 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
405
6440adb5 406 /* De-alloc circular buffer of TFDs */
b481de9c 407 if (txq->q.n_bd)
bb8c093b 408 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 409 txq->q.n_bd, txq->bd, txq->q.dma_addr);
410
6440adb5 411 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 412 if (txq->txb) {
413 kfree(txq->txb);
414 txq->txb = NULL;
415 }
416
6440adb5 417 /* 0-fill queue descriptor structure */
b481de9c
ZY		 418 memset(txq, 0, sizeof(*txq));
419}
420
bb8c093b 421const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 422
423/*************** STATION TABLE MANAGEMENT ****
9fbab516 424 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 425 * the functionality provided here
426 */
427
428/**************************************************************/
01ebd063 429#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 430/**
431 * iwl3945_remove_station - Remove driver's knowledge of station.
432 *
433 * NOTE: This does not remove station from device's station table.
434 */
bb8c093b 435static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 436{
437 int index = IWL_INVALID_STATION;
438 int i;
439 unsigned long flags;
440
441 spin_lock_irqsave(&priv->sta_lock, flags);
442
443 if (is_ap)
444 index = IWL_AP_ID;
445 else if (is_broadcast_ether_addr(addr))
446 index = priv->hw_setting.bcast_sta_id;
447 else
448 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
449 if (priv->stations[i].used &&
450 !compare_ether_addr(priv->stations[i].sta.sta.addr,
451 addr)) {
452 index = i;
453 break;
454 }
455
456 if (unlikely(index == IWL_INVALID_STATION))
457 goto out;
458
459 if (priv->stations[index].used) {
460 priv->stations[index].used = 0;
461 priv->num_stations--;
462 }
463
464 BUG_ON(priv->num_stations < 0);
465
466out:
467 spin_unlock_irqrestore(&priv->sta_lock, flags);
468 return 0;
469}
556f8db7 470#endif
6440adb5
CB		 471
472/**
473 * iwl3945_clear_stations_table - Clear the driver's station table
474 *
475 * NOTE: This does not clear or otherwise alter the device's station table.
476 */
bb8c093b 477static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 478{
479 unsigned long flags;
480
481 spin_lock_irqsave(&priv->sta_lock, flags);
482
483 priv->num_stations = 0;
484 memset(priv->stations, 0, sizeof(priv->stations));
485
486 spin_unlock_irqrestore(&priv->sta_lock, flags);
487}
488
6440adb5
CB		 489/**
490 * iwl3945_add_station - Add station to station tables in driver and device
491 */
bb8c093b 492u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 493{
494 int i;
495 int index = IWL_INVALID_STATION;
bb8c093b 496 struct iwl3945_station_entry *station;
b481de9c 497 unsigned long flags_spin;
0795af57 498 DECLARE_MAC_BUF(mac);
c14c521e 499 u8 rate;
b481de9c
ZY		 500
501 spin_lock_irqsave(&priv->sta_lock, flags_spin);
502 if (is_ap)
503 index = IWL_AP_ID;
504 else if (is_broadcast_ether_addr(addr))
505 index = priv->hw_setting.bcast_sta_id;
506 else
507 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
508 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
509 addr)) {
510 index = i;
511 break;
512 }
513
514 if (!priv->stations[i].used &&
515 index == IWL_INVALID_STATION)
516 index = i;
517 }
518
01ebd063 519 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 520 since they have different meaning */
521 if (unlikely(index == IWL_INVALID_STATION)) {
522 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
523 return index;
524 }
525
526 if (priv->stations[index].used &&
527 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
528 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
529 return index;
530 }
531
0795af57 532 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 533 station = &priv->stations[index];
534 station->used = 1;
535 priv->num_stations++;
536
6440adb5 537 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 538 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 539 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
540 station->sta.mode = 0;
541 station->sta.sta.sta_id = index;
542 station->sta.station_flags = 0;
543
8318d78a 544 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 545 rate = IWL_RATE_6M_PLCP;
546 else
547 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 548
549 /* Turn on both antennas for the station... */
550 station->sta.rate_n_flags =
bb8c093b 551 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 552 station->current_rate.rate_n_flags =
553 le16_to_cpu(station->sta.rate_n_flags);
554
b481de9c 555 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 556
557 /* Add station to device's station table */
bb8c093b 558 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 559 return index;
560
561}
562
563/*************** DRIVER STATUS FUNCTIONS *****/
564
bb8c093b 565static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 566{
567 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
568 * set but EXIT_PENDING is not */
569 return test_bit(STATUS_READY, &priv->status) &&
570 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
571 !test_bit(STATUS_EXIT_PENDING, &priv->status);
572}
573
bb8c093b 574static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 575{
576 return test_bit(STATUS_ALIVE, &priv->status);
577}
578
bb8c093b 579static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 580{
581 return test_bit(STATUS_INIT, &priv->status);
582}
583
bb8c093b 584static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c
ZY		 585{
586 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
587 test_bit(STATUS_RF_KILL_SW, &priv->status);
588}
589
bb8c093b 590static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 591{
592
bb8c093b 593 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 594 return 0;
595
bb8c093b 596 return iwl3945_is_ready(priv);
b481de9c
ZY		 597}
598
599/*************** HOST COMMAND QUEUE FUNCTIONS *****/
600
601#define IWL_CMD(x) case x : return #x
602
603static const char *get_cmd_string(u8 cmd)
604{
605 switch (cmd) {
606 IWL_CMD(REPLY_ALIVE);
607 IWL_CMD(REPLY_ERROR);
608 IWL_CMD(REPLY_RXON);
609 IWL_CMD(REPLY_RXON_ASSOC);
610 IWL_CMD(REPLY_QOS_PARAM);
611 IWL_CMD(REPLY_RXON_TIMING);
612 IWL_CMD(REPLY_ADD_STA);
613 IWL_CMD(REPLY_REMOVE_STA);
614 IWL_CMD(REPLY_REMOVE_ALL_STA);
615 IWL_CMD(REPLY_3945_RX);
616 IWL_CMD(REPLY_TX);
617 IWL_CMD(REPLY_RATE_SCALE);
618 IWL_CMD(REPLY_LEDS_CMD);
619 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
620 IWL_CMD(RADAR_NOTIFICATION);
621 IWL_CMD(REPLY_QUIET_CMD);
622 IWL_CMD(REPLY_CHANNEL_SWITCH);
623 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
624 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
625 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
626 IWL_CMD(POWER_TABLE_CMD);
627 IWL_CMD(PM_SLEEP_NOTIFICATION);
628 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
629 IWL_CMD(REPLY_SCAN_CMD);
630 IWL_CMD(REPLY_SCAN_ABORT_CMD);
631 IWL_CMD(SCAN_START_NOTIFICATION);
632 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
633 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
634 IWL_CMD(BEACON_NOTIFICATION);
635 IWL_CMD(REPLY_TX_BEACON);
636 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
637 IWL_CMD(QUIET_NOTIFICATION);
638 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
639 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
640 IWL_CMD(REPLY_BT_CONFIG);
641 IWL_CMD(REPLY_STATISTICS_CMD);
642 IWL_CMD(STATISTICS_NOTIFICATION);
643 IWL_CMD(REPLY_CARD_STATE_CMD);
644 IWL_CMD(CARD_STATE_NOTIFICATION);
645 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
646 default:
647 return "UNKNOWN";
648
649 }
650}
651
652#define HOST_COMPLETE_TIMEOUT (HZ / 2)
653
654/**
bb8c093b 655 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 656 * @priv: device private data point
657 * @cmd: a point to the ucode command structure
658 *
659 * The function returns < 0 values to indicate the operation is
660 * failed. On success, it turns the index (> 0) of command in the
661 * command queue.
662 */
bb8c093b 663static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 664{
bb8c093b
CH		 665 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
666 struct iwl3945_queue *q = &txq->q;
667 struct iwl3945_tfd_frame *tfd;
b481de9c 668 u32 *control_flags;
bb8c093b 669 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 670 u32 idx;
671 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
672 dma_addr_t phys_addr;
673 int pad;
674 u16 count;
675 int ret;
676 unsigned long flags;
677
678 /* If any of the command structures end up being larger than
679 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
680 * we will need to increase the size of the TFD entries */
681 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
682 !(cmd->meta.flags & CMD_SIZE_HUGE));
683
c342a1b9
GG		 684
685 if (iwl3945_is_rfkill(priv)) {
686 IWL_DEBUG_INFO("Not sending command - RF KILL");
687 return -EIO;
688 }
689
bb8c093b 690 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 691 IWL_ERROR("No space for Tx\n");
692 return -ENOSPC;
693 }
694
695 spin_lock_irqsave(&priv->hcmd_lock, flags);
696
fc4b6853 697 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 698 memset(tfd, 0, sizeof(*tfd));
699
700 control_flags = (u32 *) tfd;
701
fc4b6853 702 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 703 out_cmd = &txq->cmd[idx];
704
705 out_cmd->hdr.cmd = cmd->id;
706 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
707 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
708
709 /* At this point, the out_cmd now has all of the incoming cmd
710 * information */
711
712 out_cmd->hdr.flags = 0;
713 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 714 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 715 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
716 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
717
718 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 719 offsetof(struct iwl3945_cmd, hdr);
720 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 721
722 pad = U32_PAD(cmd->len);
723 count = TFD_CTL_COUNT_GET(*control_flags);
724 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
725
726 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
727 "%d bytes at %d[%d]:%d\n",
728 get_cmd_string(out_cmd->hdr.cmd),
729 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 730 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 731
732 txq->need_update = 1;
6440adb5
CB		 733
734 /* Increment and update queue's write index */
bb8c093b
CH		 735 q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
736 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 737
738 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
739 return ret ? ret : idx;
740}
741
bb8c093b 742static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 743{
744 int ret;
745
746 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
747
748 /* An asynchronous command can not expect an SKB to be set. */
749 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
750
751 /* An asynchronous command MUST have a callback. */
752 BUG_ON(!cmd->meta.u.callback);
753
754 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
755 return -EBUSY;
756
bb8c093b 757 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 758 if (ret < 0) {
bb8c093b 759 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 760 get_cmd_string(cmd->id), ret);
761 return ret;
762 }
763 return 0;
764}
765
bb8c093b 766static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 767{
768 int cmd_idx;
769 int ret;
770 static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
771
772 BUG_ON(cmd->meta.flags & CMD_ASYNC);
773
774 /* A synchronous command can not have a callback set. */
775 BUG_ON(cmd->meta.u.callback != NULL);
776
777 if (atomic_xchg(&entry, 1)) {
778 IWL_ERROR("Error sending %s: Already sending a host command\n",
779 get_cmd_string(cmd->id));
780 return -EBUSY;
781 }
782
783 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
784
785 if (cmd->meta.flags & CMD_WANT_SKB)
786 cmd->meta.source = &cmd->meta;
787
bb8c093b 788 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 789 if (cmd_idx < 0) {
790 ret = cmd_idx;
bb8c093b 791 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 792 get_cmd_string(cmd->id), ret);
793 goto out;
794 }
795
796 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
797 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
798 HOST_COMPLETE_TIMEOUT);
799 if (!ret) {
800 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
801 IWL_ERROR("Error sending %s: time out after %dms.\n",
802 get_cmd_string(cmd->id),
803 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
804
805 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
806 ret = -ETIMEDOUT;
807 goto cancel;
808 }
809 }
810
811 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
812 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
813 get_cmd_string(cmd->id));
814 ret = -ECANCELED;
815 goto fail;
816 }
817 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
818 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
819 get_cmd_string(cmd->id));
820 ret = -EIO;
821 goto fail;
822 }
823 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
824 IWL_ERROR("Error: Response NULL in '%s'\n",
825 get_cmd_string(cmd->id));
826 ret = -EIO;
827 goto out;
828 }
829
830 ret = 0;
831 goto out;
832
833cancel:
834 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 835 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 836
837 /* Cancel the CMD_WANT_SKB flag for the cmd in the
838 * TX cmd queue. Otherwise in case the cmd comes
839 * in later, it will possibly set an invalid
840 * address (cmd->meta.source). */
841 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
842 qcmd->meta.flags &= ~CMD_WANT_SKB;
843 }
844fail:
845 if (cmd->meta.u.skb) {
846 dev_kfree_skb_any(cmd->meta.u.skb);
847 cmd->meta.u.skb = NULL;
848 }
849out:
850 atomic_set(&entry, 0);
851 return ret;
852}
853
bb8c093b 854int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 855{
b481de9c 856 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 857 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 858
bb8c093b 859 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 860}
861
bb8c093b 862int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 863{
bb8c093b 864 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 865 .id = id,
866 .len = len,
867 .data = data,
868 };
869
bb8c093b 870 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 871}
872
bb8c093b 873static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 874{
bb8c093b 875 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 876 .id = id,
877 .len = sizeof(val),
878 .data = &val,
879 };
880
bb8c093b 881 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 882}
883
bb8c093b 884int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 885{
bb8c093b 886 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 887}
888
b481de9c 889/**
bb8c093b 890 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 891 * @band: 2.4 or 5 GHz band
892 * @channel: Any channel valid for the requested band
b481de9c 893
8318d78a 894 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 895 *
896 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 897 * in the staging RXON flag structure based on the band
b481de9c 898 */
8318d78a
JB		 899static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
900 enum ieee80211_band band,
901 u16 channel)
b481de9c 902{
8318d78a 903 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 904 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 905 channel, band);
b481de9c
ZY		 906 return -EINVAL;
907 }
908
909 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 910 (priv->band == band))
b481de9c
ZY		 911 return 0;
912
913 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 914 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 915 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
916 else
917 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
918
8318d78a 919 priv->band = band;
b481de9c 920
8318d78a 921 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 922
923 return 0;
924}
925
926/**
bb8c093b 927 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 928 *
929 * NOTE: This is really only useful during development and can eventually
930 * be #ifdef'd out once the driver is stable and folks aren't actively
931 * making changes
932 */
bb8c093b 933static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 934{
935 int error = 0;
936 int counter = 1;
937
938 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
939 error |= le32_to_cpu(rxon->flags &
940 (RXON_FLG_TGJ_NARROW_BAND_MSK |
941 RXON_FLG_RADAR_DETECT_MSK));
942 if (error)
943 IWL_WARNING("check 24G fields %d | %d\n",
944 counter++, error);
945 } else {
946 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
947 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
948 if (error)
949 IWL_WARNING("check 52 fields %d | %d\n",
950 counter++, error);
951 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
952 if (error)
953 IWL_WARNING("check 52 CCK %d | %d\n",
954 counter++, error);
955 }
956 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
957 if (error)
958 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
959
960 /* make sure basic rates 6Mbps and 1Mbps are supported */
961 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
962 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
963 if (error)
964 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
965
966 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
967 if (error)
968 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
969
970 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
971 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
972 if (error)
973 IWL_WARNING("check CCK and short slot %d | %d\n",
974 counter++, error);
975
976 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
977 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
978 if (error)
979 IWL_WARNING("check CCK & auto detect %d | %d\n",
980 counter++, error);
981
982 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
983 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
984 if (error)
985 IWL_WARNING("check TGG and auto detect %d | %d\n",
986 counter++, error);
987
988 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
989 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
990 RXON_FLG_ANT_A_MSK)) == 0);
991 if (error)
992 IWL_WARNING("check antenna %d %d\n", counter++, error);
993
994 if (error)
995 IWL_WARNING("Tuning to channel %d\n",
996 le16_to_cpu(rxon->channel));
997
998 if (error) {
bb8c093b 999 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 1000 return -1;
1001 }
1002 return 0;
1003}
1004
1005/**
9fbab516 1006 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 1007 * @priv: staging_rxon is compared to active_rxon
b481de9c 1008 *
9fbab516
BC		 1009 * If the RXON structure is changing enough to require a new tune,
1010 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
1011 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 1012 */
bb8c093b 1013static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 1014{
1015
1016 /* These items are only settable from the full RXON command */
1017 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
1018 compare_ether_addr(priv->staging_rxon.bssid_addr,
1019 priv->active_rxon.bssid_addr) ||
1020 compare_ether_addr(priv->staging_rxon.node_addr,
1021 priv->active_rxon.node_addr) ||
1022 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
1023 priv->active_rxon.wlap_bssid_addr) ||
1024 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
1025 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
1026 (priv->staging_rxon.air_propagation !=
1027 priv->active_rxon.air_propagation) ||
1028 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
1029 return 1;
1030
1031 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
1032 * be updated with the RXON_ASSOC command -- however only some
1033 * flag transitions are allowed using RXON_ASSOC */
1034
1035 /* Check if we are not switching bands */
1036 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
1037 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
1038 return 1;
1039
1040 /* Check if we are switching association toggle */
1041 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1042 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1043 return 1;
1044
1045 return 0;
1046}
1047
bb8c093b 1048static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1049{
1050 int rc = 0;
bb8c093b
CH		 1051 struct iwl3945_rx_packet *res = NULL;
1052 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1053 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1054 .id = REPLY_RXON_ASSOC,
1055 .len = sizeof(rxon_assoc),
1056 .meta.flags = CMD_WANT_SKB,
1057 .data = &rxon_assoc,
1058 };
bb8c093b
CH		 1059 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1060 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1061
1062 if ((rxon1->flags == rxon2->flags) &&
1063 (rxon1->filter_flags == rxon2->filter_flags) &&
1064 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1065 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1066 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1067 return 0;
1068 }
1069
1070 rxon_assoc.flags = priv->staging_rxon.flags;
1071 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1072 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1073 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1074 rxon_assoc.reserved = 0;
1075
bb8c093b 1076 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1077 if (rc)
1078 return rc;
1079
bb8c093b 1080 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1081 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1082 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1083 rc = -EIO;
1084 }
1085
1086 priv->alloc_rxb_skb--;
1087 dev_kfree_skb_any(cmd.meta.u.skb);
1088
1089 return rc;
1090}
1091
1092/**
bb8c093b 1093 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1094 *
01ebd063 1095 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1096 * the active_rxon structure is updated with the new data. This
1097 * function correctly transitions out of the RXON_ASSOC_MSK state if
1098 * a HW tune is required based on the RXON structure changes.
1099 */
bb8c093b 1100static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1101{
1102 /* cast away the const for active_rxon in this function */
bb8c093b 1103 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1104 int rc = 0;
0795af57 1105 DECLARE_MAC_BUF(mac);
b481de9c 1106
bb8c093b 1107 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1108 return -1;
1109
1110 /* always get timestamp with Rx frame */
1111 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1112
1113 /* select antenna */
1114 priv->staging_rxon.flags &=
1115 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1116 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1117
bb8c093b 1118 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1119 if (rc) {
1120 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1121 return -EINVAL;
1122 }
1123
1124 /* If we don't need to send a full RXON, we can use
bb8c093b 1125 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1126 * and other flags for the current radio configuration. */
bb8c093b
CH		 1127 if (!iwl3945_full_rxon_required(priv)) {
1128 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1129 if (rc) {
1130 IWL_ERROR("Error setting RXON_ASSOC "
1131 "configuration (%d).\n", rc);
1132 return rc;
1133 }
1134
1135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1136
1137 return 0;
1138 }
1139
1140 /* If we are currently associated and the new config requires
1141 * an RXON_ASSOC and the new config wants the associated mask enabled,
1142 * we must clear the associated from the active configuration
1143 * before we apply the new config */
bb8c093b 1144 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1145 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1146 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1147 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1148
bb8c093b
CH		 1149 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1150 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1151 &priv->active_rxon);
1152
1153 /* If the mask clearing failed then we set
1154 * active_rxon back to what it was previously */
1155 if (rc) {
1156 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1157 IWL_ERROR("Error clearing ASSOC_MSK on current "
1158 "configuration (%d).\n", rc);
1159 return rc;
1160 }
b481de9c
ZY		 1161 }
1162
1163 IWL_DEBUG_INFO("Sending RXON\n"
1164 "* with%s RXON_FILTER_ASSOC_MSK\n"
1165 "* channel = %d\n"
0795af57 1166 "* bssid = %s\n",
b481de9c
ZY		 1167 ((priv->staging_rxon.filter_flags &
1168 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1169 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1170 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY		 1171
1172 /* Apply the new configuration */
bb8c093b
CH		 1173 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1174 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1175 if (rc) {
1176 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1177 return rc;
1178 }
1179
1180 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1181
bb8c093b 1182 iwl3945_clear_stations_table(priv);
556f8db7 1183
b481de9c
ZY		 1184 /* If we issue a new RXON command which required a tune then we must
1185 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1186 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1187 if (rc) {
1188 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1189 return rc;
1190 }
1191
1192 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1193 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1194 IWL_INVALID_STATION) {
1195 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1196 return -EIO;
1197 }
1198
1199 /* If we have set the ASSOC_MSK and we are in BSS mode then
1200 * add the IWL_AP_ID to the station rate table */
bb8c093b 1201 if (iwl3945_is_associated(priv) &&
b481de9c 1202 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1203 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1204 == IWL_INVALID_STATION) {
1205 IWL_ERROR("Error adding AP address for transmit.\n");
1206 return -EIO;
1207 }
1208
8318d78a 1209 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1210 rc = iwl3945_init_hw_rate_table(priv);
1211 if (rc) {
1212 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1213 return -EIO;
1214 }
1215
1216 return 0;
1217}
1218
bb8c093b 1219static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1220{
bb8c093b 1221 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1222 .flags = 3,
1223 .lead_time = 0xAA,
1224 .max_kill = 1,
1225 .kill_ack_mask = 0,
1226 .kill_cts_mask = 0,
1227 };
1228
bb8c093b
CH		 1229 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1230 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1231}
1232
bb8c093b 1233static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1234{
1235 int rc = 0;
bb8c093b
CH		 1236 struct iwl3945_rx_packet *res;
1237 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1238 .id = REPLY_SCAN_ABORT_CMD,
1239 .meta.flags = CMD_WANT_SKB,
1240 };
1241
1242 /* If there isn't a scan actively going on in the hardware
1243 * then we are in between scan bands and not actually
1244 * actively scanning, so don't send the abort command */
1245 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1246 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1247 return 0;
1248 }
1249
bb8c093b 1250 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1251 if (rc) {
1252 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1253 return rc;
1254 }
1255
bb8c093b 1256 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1257 if (res->u.status != CAN_ABORT_STATUS) {
1258 /* The scan abort will return 1 for success or
1259 * 2 for "failure". A failure condition can be
1260 * due to simply not being in an active scan which
1261 * can occur if we send the scan abort before we
1262 * the microcode has notified us that a scan is
1263 * completed. */
1264 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1265 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1266 clear_bit(STATUS_SCAN_HW, &priv->status);
1267 }
1268
1269 dev_kfree_skb_any(cmd.meta.u.skb);
1270
1271 return rc;
1272}
1273
bb8c093b
CH		 1274static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1275 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1276 struct sk_buff *skb)
1277{
1278 return 1;
1279}
1280
1281/*
1282 * CARD_STATE_CMD
1283 *
9fbab516 1284 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1285 *
1286 * When in the 'enable' state the card operates as normal.
1287 * When in the 'disable' state, the card enters into a low power mode.
1288 * When in the 'halt' state, the card is shut down and must be fully
1289 * restarted to come back on.
1290 */
bb8c093b 1291static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1292{
bb8c093b 1293 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1294 .id = REPLY_CARD_STATE_CMD,
1295 .len = sizeof(u32),
1296 .data = &flags,
1297 .meta.flags = meta_flag,
1298 };
1299
1300 if (meta_flag & CMD_ASYNC)
bb8c093b 1301 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1302
bb8c093b 1303 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1304}
1305
bb8c093b
CH		 1306static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1307 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1308{
bb8c093b 1309 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1310
1311 if (!skb) {
1312 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1313 return 1;
1314 }
1315
bb8c093b 1316 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1317 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1318 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1319 res->hdr.flags);
1320 return 1;
1321 }
1322
1323 switch (res->u.add_sta.status) {
1324 case ADD_STA_SUCCESS_MSK:
1325 break;
1326 default:
1327 break;
1328 }
1329
1330 /* We didn't cache the SKB; let the caller free it */
1331 return 1;
1332}
1333
bb8c093b
CH		 1334int iwl3945_send_add_station(struct iwl3945_priv *priv,
1335 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1336{
bb8c093b 1337 struct iwl3945_rx_packet *res = NULL;
b481de9c 1338 int rc = 0;
bb8c093b 1339 struct iwl3945_host_cmd cmd = {
b481de9c 1340 .id = REPLY_ADD_STA,
bb8c093b 1341 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1342 .meta.flags = flags,
1343 .data = sta,
1344 };
1345
1346 if (flags & CMD_ASYNC)
bb8c093b 1347 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1348 else
1349 cmd.meta.flags |= CMD_WANT_SKB;
1350
bb8c093b 1351 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1352
1353 if (rc || (flags & CMD_ASYNC))
1354 return rc;
1355
bb8c093b 1356 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1357 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1358 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1359 res->hdr.flags);
1360 rc = -EIO;
1361 }
1362
1363 if (rc == 0) {
1364 switch (res->u.add_sta.status) {
1365 case ADD_STA_SUCCESS_MSK:
1366 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1367 break;
1368 default:
1369 rc = -EIO;
1370 IWL_WARNING("REPLY_ADD_STA failed\n");
1371 break;
1372 }
1373 }
1374
1375 priv->alloc_rxb_skb--;
1376 dev_kfree_skb_any(cmd.meta.u.skb);
1377
1378 return rc;
1379}
1380
bb8c093b 1381static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1382 struct ieee80211_key_conf *keyconf,
1383 u8 sta_id)
1384{
1385 unsigned long flags;
1386 __le16 key_flags = 0;
1387
1388 switch (keyconf->alg) {
1389 case ALG_CCMP:
1390 key_flags |= STA_KEY_FLG_CCMP;
1391 key_flags |= cpu_to_le16(
1392 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1393 key_flags &= ~STA_KEY_FLG_INVALID;
1394 break;
1395 case ALG_TKIP:
1396 case ALG_WEP:
b481de9c
ZY		 1397 default:
1398 return -EINVAL;
1399 }
1400 spin_lock_irqsave(&priv->sta_lock, flags);
1401 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1402 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1403 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1404 keyconf->keylen);
1405
1406 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1407 keyconf->keylen);
1408 priv->stations[sta_id].sta.key.key_flags = key_flags;
1409 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1410 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1411
1412 spin_unlock_irqrestore(&priv->sta_lock, flags);
1413
1414 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1415 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1416 return 0;
1417}
1418
bb8c093b 1419static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1420{
1421 unsigned long flags;
1422
1423 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1424 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1425 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1426 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1427 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1428 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1429 spin_unlock_irqrestore(&priv->sta_lock, flags);
1430
1431 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1432 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1433 return 0;
1434}
1435
bb8c093b 1436static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1437{
1438 struct list_head *element;
1439
1440 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1441 priv->frames_count);
1442
1443 while (!list_empty(&priv->free_frames)) {
1444 element = priv->free_frames.next;
1445 list_del(element);
bb8c093b 1446 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1447 priv->frames_count--;
1448 }
1449
1450 if (priv->frames_count) {
1451 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1452 priv->frames_count);
1453 priv->frames_count = 0;
1454 }
1455}
1456
bb8c093b 1457static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1458{
bb8c093b 1459 struct iwl3945_frame *frame;
b481de9c
ZY		 1460 struct list_head *element;
1461 if (list_empty(&priv->free_frames)) {
1462 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1463 if (!frame) {
1464 IWL_ERROR("Could not allocate frame!\n");
1465 return NULL;
1466 }
1467
1468 priv->frames_count++;
1469 return frame;
1470 }
1471
1472 element = priv->free_frames.next;
1473 list_del(element);
bb8c093b 1474 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1475}
1476
bb8c093b 1477static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1478{
1479 memset(frame, 0, sizeof(*frame));
1480 list_add(&frame->list, &priv->free_frames);
1481}
1482
bb8c093b 1483unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1484 struct ieee80211_hdr *hdr,
1485 const u8 *dest, int left)
1486{
1487
bb8c093b 1488 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1489 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1490 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1491 return 0;
1492
1493 if (priv->ibss_beacon->len > left)
1494 return 0;
1495
1496 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1497
1498 return priv->ibss_beacon->len;
1499}
1500
bb8c093b 1501static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1502{
1503 u8 i;
1504
1505 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1506 i = iwl3945_rates[i].next_ieee) {
b481de9c 1507 if (rate_mask & (1 << i))
bb8c093b 1508 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1509 }
1510
1511 return IWL_RATE_INVALID;
1512}
1513
bb8c093b 1514static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1515{
bb8c093b 1516 struct iwl3945_frame *frame;
b481de9c
ZY		 1517 unsigned int frame_size;
1518 int rc;
1519 u8 rate;
1520
bb8c093b 1521 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1522
1523 if (!frame) {
1524 IWL_ERROR("Could not obtain free frame buffer for beacon "
1525 "command.\n");
1526 return -ENOMEM;
1527 }
1528
1529 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1530 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1531 0xFF0);
1532 if (rate == IWL_INVALID_RATE)
1533 rate = IWL_RATE_6M_PLCP;
1534 } else {
bb8c093b 1535 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1536 if (rate == IWL_INVALID_RATE)
1537 rate = IWL_RATE_1M_PLCP;
1538 }
1539
bb8c093b 1540 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1541
bb8c093b 1542 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1543 &frame->u.cmd[0]);
1544
bb8c093b 1545 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1546
1547 return rc;
1548}
1549
1550/******************************************************************************
1551 *
1552 * EEPROM related functions
1553 *
1554 ******************************************************************************/
1555
bb8c093b 1556static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1557{
1558 memcpy(mac, priv->eeprom.mac_address, 6);
1559}
1560
74a3a250
RC		 1561/*
1562 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1563 * embedded controller) as EEPROM reader; each read is a series of pulses
1564 * to/from the EEPROM chip, not a single event, so even reads could conflict
1565 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1566 * simply claims ownership, which should be safe when this function is called
1567 * (i.e. before loading uCode!).
1568 */
1569static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1570{
1571 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1572 return 0;
1573}
1574
b481de9c 1575/**
bb8c093b 1576 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1577 *
6440adb5 1578 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1579 *
1580 * NOTE: This routine uses the non-debug IO access functions.
1581 */
bb8c093b 1582int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1583{
58ff6d4d 1584 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1585 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1586 u32 r;
1587 int sz = sizeof(priv->eeprom);
1588 int rc;
1589 int i;
1590 u16 addr;
1591
1592 /* The EEPROM structure has several padding buffers within it
1593 * and when adding new EEPROM maps is subject to programmer errors
1594 * which may be very difficult to identify without explicitly
1595 * checking the resulting size of the eeprom map. */
1596 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1597
1598 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1599 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1600 return -ENOENT;
1601 }
1602
6440adb5 1603 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1604 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1605 if (rc < 0) {
91e17473 1606 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1607 return -ENOENT;
1608 }
1609
1610 /* eeprom is an array of 16bit values */
1611 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1612 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1613 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1614
1615 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1616 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1617 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1618 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1619 break;
1620 udelay(IWL_EEPROM_ACCESS_DELAY);
1621 }
1622
1623 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1624 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1625 return -ETIMEDOUT;
1626 }
58ff6d4d 1627 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1628 }
1629
1630 return 0;
1631}
1632
1633/******************************************************************************
1634 *
1635 * Misc. internal state and helper functions
1636 *
1637 ******************************************************************************/
c8b0e6e1 1638#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 1639
1640/**
bb8c093b 1641 * iwl3945_report_frame - dump frame to syslog during debug sessions
b481de9c 1642 *
9fbab516 1643 * You may hack this function to show different aspects of received frames,
b481de9c
ZY		 1644 * including selective frame dumps.
1645 * group100 parameter selects whether to show 1 out of 100 good frames.
b481de9c 1646 */
bb8c093b
CH		 1647void iwl3945_report_frame(struct iwl3945_priv *priv,
1648 struct iwl3945_rx_packet *pkt,
b481de9c
ZY		 1649 struct ieee80211_hdr *header, int group100)
1650{
1651 u32 to_us;
1652 u32 print_summary = 0;
1653 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
1654 u32 hundred = 0;
1655 u32 dataframe = 0;
1656 u16 fc;
1657 u16 seq_ctl;
1658 u16 channel;
1659 u16 phy_flags;
1660 int rate_sym;
1661 u16 length;
1662 u16 status;
1663 u16 bcn_tmr;
1664 u32 tsf_low;
1665 u64 tsf;
1666 u8 rssi;
1667 u8 agc;
1668 u16 sig_avg;
1669 u16 noise_diff;
bb8c093b
CH		 1670 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
1671 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
1672 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 1673 u8 *data = IWL_RX_DATA(pkt);
1674
1675 /* MAC header */
1676 fc = le16_to_cpu(header->frame_control);
1677 seq_ctl = le16_to_cpu(header->seq_ctrl);
1678
1679 /* metadata */
1680 channel = le16_to_cpu(rx_hdr->channel);
1681 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
1682 rate_sym = rx_hdr->rate;
1683 length = le16_to_cpu(rx_hdr->len);
1684
1685 /* end-of-frame status and timestamp */
1686 status = le32_to_cpu(rx_end->status);
1687 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
1688 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
1689 tsf = le64_to_cpu(rx_end->timestamp);
1690
1691 /* signal statistics */
1692 rssi = rx_stats->rssi;
1693 agc = rx_stats->agc;
1694 sig_avg = le16_to_cpu(rx_stats->sig_avg);
1695 noise_diff = le16_to_cpu(rx_stats->noise_diff);
1696
1697 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
1698
1699 /* if data frame is to us and all is good,
1700 * (optionally) print summary for only 1 out of every 100 */
1701 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
1702 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
1703 dataframe = 1;
1704 if (!group100)
1705 print_summary = 1; /* print each frame */
1706 else if (priv->framecnt_to_us < 100) {
1707 priv->framecnt_to_us++;
1708 print_summary = 0;
1709 } else {
1710 priv->framecnt_to_us = 0;
1711 print_summary = 1;
1712 hundred = 1;
1713 }
1714 } else {
1715 /* print summary for all other frames */
1716 print_summary = 1;
1717 }
1718
1719 if (print_summary) {
1720 char *title;
1721 u32 rate;
1722
1723 if (hundred)
1724 title = "100Frames";
1725 else if (fc & IEEE80211_FCTL_RETRY)
1726 title = "Retry";
1727 else if (ieee80211_is_assoc_response(fc))
1728 title = "AscRsp";
1729 else if (ieee80211_is_reassoc_response(fc))
1730 title = "RasRsp";
1731 else if (ieee80211_is_probe_response(fc)) {
1732 title = "PrbRsp";
1733 print_dump = 1; /* dump frame contents */
1734 } else if (ieee80211_is_beacon(fc)) {
1735 title = "Beacon";
1736 print_dump = 1; /* dump frame contents */
1737 } else if (ieee80211_is_atim(fc))
1738 title = "ATIM";
1739 else if (ieee80211_is_auth(fc))
1740 title = "Auth";
1741 else if (ieee80211_is_deauth(fc))
1742 title = "DeAuth";
1743 else if (ieee80211_is_disassoc(fc))
1744 title = "DisAssoc";
1745 else
1746 title = "Frame";
1747
bb8c093b 1748 rate = iwl3945_rate_index_from_plcp(rate_sym);
b481de9c
ZY		 1749 if (rate == -1)
1750 rate = 0;
1751 else
bb8c093b 1752 rate = iwl3945_rates[rate].ieee / 2;
b481de9c
ZY		 1753
1754 /* print frame summary.
1755 * MAC addresses show just the last byte (for brevity),
1756 * but you can hack it to show more, if you'd like to. */
1757 if (dataframe)
1758 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
1759 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
1760 title, fc, header->addr1[5],
1761 length, rssi, channel, rate);
1762 else {
1763 /* src/dst addresses assume managed mode */
1764 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
1765 "src=0x%02x, rssi=%u, tim=%lu usec, "
1766 "phy=0x%02x, chnl=%d\n",
1767 title, fc, header->addr1[5],
1768 header->addr3[5], rssi,
1769 tsf_low - priv->scan_start_tsf,
1770 phy_flags, channel);
1771 }
1772 }
1773 if (print_dump)
bb8c093b 1774 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
b481de9c
ZY		 1775}
1776#endif
1777
bb8c093b 1778static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1779{
1780 if (priv->hw_setting.shared_virt)
1781 pci_free_consistent(priv->pci_dev,
bb8c093b 1782 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1783 priv->hw_setting.shared_virt,
1784 priv->hw_setting.shared_phys);
1785}
1786
1787/**
bb8c093b 1788 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1789 *
1790 * return : set the bit for each supported rate insert in ie
1791 */
bb8c093b 1792static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1793 u16 basic_rate, int *left)
b481de9c
ZY		 1794{
1795 u16 ret_rates = 0, bit;
1796 int i;
c7c46676
TW		 1797 u8 *cnt = ie;
1798 u8 *rates = ie + 1;
b481de9c
ZY		 1799
1800 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1801 if (bit & supported_rate) {
1802 ret_rates |= bit;
bb8c093b 1803 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1804 ((bit & basic_rate) ? 0x80 : 0x00);
1805 (*cnt)++;
1806 (*left)--;
1807 if ((*left <= 0) ||
1808 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1809 break;
1810 }
1811 }
1812
1813 return ret_rates;
1814}
1815
1816/**
bb8c093b 1817 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1818 */
bb8c093b 1819static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1820 struct ieee80211_mgmt *frame,
1821 int left, int is_direct)
1822{
1823 int len = 0;
1824 u8 *pos = NULL;
c7c46676 1825 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1826
1827 /* Make sure there is enough space for the probe request,
1828 * two mandatory IEs and the data */
1829 left -= 24;
1830 if (left < 0)
1831 return 0;
1832 len += 24;
1833
1834 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1835 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1836 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1837 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1838 frame->seq_ctrl = 0;
1839
1840 /* fill in our indirect SSID IE */
1841 /* ...next IE... */
1842
1843 left -= 2;
1844 if (left < 0)
1845 return 0;
1846 len += 2;
1847 pos = &(frame->u.probe_req.variable[0]);
1848 *pos++ = WLAN_EID_SSID;
1849 *pos++ = 0;
1850
1851 /* fill in our direct SSID IE... */
1852 if (is_direct) {
1853 /* ...next IE... */
1854 left -= 2 + priv->essid_len;
1855 if (left < 0)
1856 return 0;
1857 /* ... fill it in... */
1858 *pos++ = WLAN_EID_SSID;
1859 *pos++ = priv->essid_len;
1860 memcpy(pos, priv->essid, priv->essid_len);
1861 pos += priv->essid_len;
1862 len += 2 + priv->essid_len;
1863 }
1864
1865 /* fill in supported rate */
1866 /* ...next IE... */
1867 left -= 2;
1868 if (left < 0)
1869 return 0;
c7c46676 1870
b481de9c
ZY		 1871 /* ... fill it in... */
1872 *pos++ = WLAN_EID_SUPP_RATES;
1873 *pos = 0;
c7c46676
TW		 1874
1875 priv->active_rate = priv->rates_mask;
1876 active_rates = priv->active_rate;
b481de9c
ZY		 1877 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1878
c7c46676 1879 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1880 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1881 priv->active_rate_basic, &left);
1882 active_rates &= ~ret_rates;
1883
bb8c093b 1884 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1885 priv->active_rate_basic, &left);
1886 active_rates &= ~ret_rates;
1887
b481de9c
ZY		 1888 len += 2 + *pos;
1889 pos += (*pos) + 1;
c7c46676 1890 if (active_rates == 0)
b481de9c
ZY		 1891 goto fill_end;
1892
1893 /* fill in supported extended rate */
1894 /* ...next IE... */
1895 left -= 2;
1896 if (left < 0)
1897 return 0;
1898 /* ... fill it in... */
1899 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1900 *pos = 0;
bb8c093b 1901 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1902 priv->active_rate_basic, &left);
b481de9c
ZY		 1903 if (*pos > 0)
1904 len += 2 + *pos;
1905
1906 fill_end:
1907 return (u16)len;
1908}
1909
1910/*
1911 * QoS support
1912*/
c8b0e6e1 1913#ifdef CONFIG_IWL3945_QOS
bb8c093b
CH		 1914static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1915 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1916{
1917
bb8c093b
CH		 1918 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1919 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1920}
1921
bb8c093b 1922static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1923{
1924 u16 cw_min = 15;
1925 u16 cw_max = 1023;
1926 u8 aifs = 2;
1927 u8 is_legacy = 0;
1928 unsigned long flags;
1929 int i;
1930
1931 spin_lock_irqsave(&priv->lock, flags);
1932 priv->qos_data.qos_active = 0;
1933
1934 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1935 if (priv->qos_data.qos_enable)
1936 priv->qos_data.qos_active = 1;
1937 if (!(priv->active_rate & 0xfff0)) {
1938 cw_min = 31;
1939 is_legacy = 1;
1940 }
1941 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1942 if (priv->qos_data.qos_enable)
1943 priv->qos_data.qos_active = 1;
1944 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1945 cw_min = 31;
1946 is_legacy = 1;
1947 }
1948
1949 if (priv->qos_data.qos_active)
1950 aifs = 3;
1951
1952 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1953 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1954 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1955 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1956 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1957
1958 if (priv->qos_data.qos_active) {
1959 i = 1;
1960 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1961 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1962 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1963 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1964 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1965
1966 i = 2;
1967 priv->qos_data.def_qos_parm.ac[i].cw_min =
1968 cpu_to_le16((cw_min + 1) / 2 - 1);
1969 priv->qos_data.def_qos_parm.ac[i].cw_max =
1970 cpu_to_le16(cw_max);
1971 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1972 if (is_legacy)
1973 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1974 cpu_to_le16(6016);
1975 else
1976 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1977 cpu_to_le16(3008);
1978 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1979
1980 i = 3;
1981 priv->qos_data.def_qos_parm.ac[i].cw_min =
1982 cpu_to_le16((cw_min + 1) / 4 - 1);
1983 priv->qos_data.def_qos_parm.ac[i].cw_max =
1984 cpu_to_le16((cw_max + 1) / 2 - 1);
1985 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1986 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1987 if (is_legacy)
1988 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1989 cpu_to_le16(3264);
1990 else
1991 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1992 cpu_to_le16(1504);
1993 } else {
1994 for (i = 1; i < 4; i++) {
1995 priv->qos_data.def_qos_parm.ac[i].cw_min =
1996 cpu_to_le16(cw_min);
1997 priv->qos_data.def_qos_parm.ac[i].cw_max =
1998 cpu_to_le16(cw_max);
1999 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
2000 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
2001 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
2002 }
2003 }
2004 IWL_DEBUG_QOS("set QoS to default \n");
2005
2006 spin_unlock_irqrestore(&priv->lock, flags);
2007}
2008
bb8c093b 2009static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 2010{
2011 unsigned long flags;
2012
b481de9c
ZY		 2013 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2014 return;
2015
2016 if (!priv->qos_data.qos_enable)
2017 return;
2018
2019 spin_lock_irqsave(&priv->lock, flags);
2020 priv->qos_data.def_qos_parm.qos_flags = 0;
2021
2022 if (priv->qos_data.qos_cap.q_AP.queue_request &&
2023 !priv->qos_data.qos_cap.q_AP.txop_request)
2024 priv->qos_data.def_qos_parm.qos_flags |=
2025 QOS_PARAM_FLG_TXOP_TYPE_MSK;
2026
2027 if (priv->qos_data.qos_active)
2028 priv->qos_data.def_qos_parm.qos_flags |=
2029 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
2030
2031 spin_unlock_irqrestore(&priv->lock, flags);
2032
bb8c093b 2033 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 2034 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
2035 priv->qos_data.qos_active);
2036
bb8c093b 2037 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 2038 &(priv->qos_data.def_qos_parm));
2039 }
2040}
2041
c8b0e6e1 2042#endif /* CONFIG_IWL3945_QOS */
b481de9c
ZY		 2043/*
2044 * Power management (not Tx power!) functions
2045 */
2046#define MSEC_TO_USEC 1024
2047
2048#define NOSLP __constant_cpu_to_le32(0)
2049#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
2050#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
2051#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
2052 __constant_cpu_to_le32(X1), \
2053 __constant_cpu_to_le32(X2), \
2054 __constant_cpu_to_le32(X3), \
2055 __constant_cpu_to_le32(X4)}
2056
2057
2058/* default power management (not Tx power) table values */
2059/* for tim 0-10 */
bb8c093b 2060static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 2061 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2062 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
2063 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
2064 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
2065 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
2066 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
2067};
2068
2069/* for tim > 10 */
bb8c093b 2070static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 2071 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2072 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
2073 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
2074 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
2075 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
2076 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
2077 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
2078 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
2079 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
2080 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
2081};
2082
bb8c093b 2083int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 2084{
2085 int rc = 0, i;
bb8c093b
CH		 2086 struct iwl3945_power_mgr *pow_data;
2087 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 2088 u16 pci_pm;
2089
2090 IWL_DEBUG_POWER("Initialize power \n");
2091
2092 pow_data = &(priv->power_data);
2093
2094 memset(pow_data, 0, sizeof(*pow_data));
2095
2096 pow_data->active_index = IWL_POWER_RANGE_0;
2097 pow_data->dtim_val = 0xffff;
2098
2099 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
2100 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
2101
2102 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
2103 if (rc != 0)
2104 return 0;
2105 else {
bb8c093b 2106 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 2107
2108 IWL_DEBUG_POWER("adjust power command flags\n");
2109
2110 for (i = 0; i < IWL_POWER_AC; i++) {
2111 cmd = &pow_data->pwr_range_0[i].cmd;
2112
2113 if (pci_pm & 0x1)
2114 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
2115 else
2116 cmd->flags |= IWL_POWER_PCI_PM_MSK;
2117 }
2118 }
2119 return rc;
2120}
2121
bb8c093b
CH		 2122static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
2123 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 2124{
2125 int rc = 0, i;
2126 u8 skip;
2127 u32 max_sleep = 0;
bb8c093b 2128 struct iwl3945_power_vec_entry *range;
b481de9c 2129 u8 period = 0;
bb8c093b 2130 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 2131
2132 if (mode > IWL_POWER_INDEX_5) {
2133 IWL_DEBUG_POWER("Error invalid power mode \n");
2134 return -1;
2135 }
2136 pow_data = &(priv->power_data);
2137
2138 if (pow_data->active_index == IWL_POWER_RANGE_0)
2139 range = &pow_data->pwr_range_0[0];
2140 else
2141 range = &pow_data->pwr_range_1[1];
2142
bb8c093b 2143 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 2144
2145#ifdef IWL_MAC80211_DISABLE
2146 if (priv->assoc_network != NULL) {
2147 unsigned long flags;
2148
2149 period = priv->assoc_network->tim.tim_period;
2150 }
2151#endif /*IWL_MAC80211_DISABLE */
2152 skip = range[mode].no_dtim;
2153
2154 if (period == 0) {
2155 period = 1;
2156 skip = 0;
2157 }
2158
2159 if (skip == 0) {
2160 max_sleep = period;
2161 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
2162 } else {
2163 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
2164 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
2165 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
2166 }
2167
2168 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
2169 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
2170 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
2171 }
2172
2173 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
2174 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
2175 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
2176 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
2177 le32_to_cpu(cmd->sleep_interval[0]),
2178 le32_to_cpu(cmd->sleep_interval[1]),
2179 le32_to_cpu(cmd->sleep_interval[2]),
2180 le32_to_cpu(cmd->sleep_interval[3]),
2181 le32_to_cpu(cmd->sleep_interval[4]));
2182
2183 return rc;
2184}
2185
bb8c093b 2186static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 2187{
9a62f73b 2188 u32 uninitialized_var(final_mode);
b481de9c 2189 int rc;
bb8c093b 2190 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2191
2192 /* If on battery, set to 3,
01ebd063 2193 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2194 * else user level */
2195 switch (mode) {
2196 case IWL_POWER_BATTERY:
2197 final_mode = IWL_POWER_INDEX_3;
2198 break;
2199 case IWL_POWER_AC:
2200 final_mode = IWL_POWER_MODE_CAM;
2201 break;
2202 default:
2203 final_mode = mode;
2204 break;
2205 }
2206
bb8c093b 2207 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2208
bb8c093b 2209 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2210
2211 if (final_mode == IWL_POWER_MODE_CAM)
2212 clear_bit(STATUS_POWER_PMI, &priv->status);
2213 else
2214 set_bit(STATUS_POWER_PMI, &priv->status);
2215
2216 return rc;
2217}
2218
bb8c093b 2219int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2220{
2221 /* Filter incoming packets to determine if they are targeted toward
2222 * this network, discarding packets coming from ourselves */
2223 switch (priv->iw_mode) {
2224 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2225 /* packets from our adapter are dropped (echo) */
2226 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2227 return 0;
2228 /* {broad,multi}cast packets to our IBSS go through */
2229 if (is_multicast_ether_addr(header->addr1))
2230 return !compare_ether_addr(header->addr3, priv->bssid);
2231 /* packets to our adapter go through */
2232 return !compare_ether_addr(header->addr1, priv->mac_addr);
2233 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2234 /* packets from our adapter are dropped (echo) */
2235 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2236 return 0;
2237 /* {broad,multi}cast packets to our BSS go through */
2238 if (is_multicast_ether_addr(header->addr1))
2239 return !compare_ether_addr(header->addr2, priv->bssid);
2240 /* packets to our adapter go through */
2241 return !compare_ether_addr(header->addr1, priv->mac_addr);
2242 }
2243
2244 return 1;
2245}
2246
2247#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2248
bb8c093b 2249static const char *iwl3945_get_tx_fail_reason(u32 status)
b481de9c
ZY		 2250{
2251 switch (status & TX_STATUS_MSK) {
2252 case TX_STATUS_SUCCESS:
2253 return "SUCCESS";
2254 TX_STATUS_ENTRY(SHORT_LIMIT);
2255 TX_STATUS_ENTRY(LONG_LIMIT);
2256 TX_STATUS_ENTRY(FIFO_UNDERRUN);
2257 TX_STATUS_ENTRY(MGMNT_ABORT);
2258 TX_STATUS_ENTRY(NEXT_FRAG);
2259 TX_STATUS_ENTRY(LIFE_EXPIRE);
2260 TX_STATUS_ENTRY(DEST_PS);
2261 TX_STATUS_ENTRY(ABORTED);
2262 TX_STATUS_ENTRY(BT_RETRY);
2263 TX_STATUS_ENTRY(STA_INVALID);
2264 TX_STATUS_ENTRY(FRAG_DROPPED);
2265 TX_STATUS_ENTRY(TID_DISABLE);
2266 TX_STATUS_ENTRY(FRAME_FLUSHED);
2267 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
2268 TX_STATUS_ENTRY(TX_LOCKED);
2269 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
2270 }
2271
2272 return "UNKNOWN";
2273}
2274
2275/**
bb8c093b 2276 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2277 *
2278 * NOTE: priv->mutex is not required before calling this function
2279 */
bb8c093b 2280static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2281{
2282 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2283 clear_bit(STATUS_SCANNING, &priv->status);
2284 return 0;
2285 }
2286
2287 if (test_bit(STATUS_SCANNING, &priv->status)) {
2288 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2289 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2290 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2291 queue_work(priv->workqueue, &priv->abort_scan);
2292
2293 } else
2294 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2295
2296 return test_bit(STATUS_SCANNING, &priv->status);
2297 }
2298
2299 return 0;
2300}
2301
2302/**
bb8c093b 2303 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2304 * @ms: amount of time to wait (in milliseconds) for scan to abort
2305 *
2306 * NOTE: priv->mutex must be held before calling this function
2307 */
bb8c093b 2308static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2309{
2310 unsigned long now = jiffies;
2311 int ret;
2312
bb8c093b 2313 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2314 if (ret && ms) {
2315 mutex_unlock(&priv->mutex);
2316 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2317 test_bit(STATUS_SCANNING, &priv->status))
2318 msleep(1);
2319 mutex_lock(&priv->mutex);
2320
2321 return test_bit(STATUS_SCANNING, &priv->status);
2322 }
2323
2324 return ret;
2325}
2326
bb8c093b 2327static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 2328{
2329 /* Reset ieee stats */
2330
2331 /* We don't reset the net_device_stats (ieee->stats) on
2332 * re-association */
2333
2334 priv->last_seq_num = -1;
2335 priv->last_frag_num = -1;
2336 priv->last_packet_time = 0;
2337
bb8c093b 2338 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2339}
2340
2341#define MAX_UCODE_BEACON_INTERVAL 1024
2342#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2343
bb8c093b 2344static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2345{
2346 u16 new_val = 0;
2347 u16 beacon_factor = 0;
2348
2349 beacon_factor =
2350 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2351 / MAX_UCODE_BEACON_INTERVAL;
2352 new_val = beacon_val / beacon_factor;
2353
2354 return cpu_to_le16(new_val);
2355}
2356
bb8c093b 2357static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2358{
2359 u64 interval_tm_unit;
2360 u64 tsf, result;
2361 unsigned long flags;
2362 struct ieee80211_conf *conf = NULL;
2363 u16 beacon_int = 0;
2364
2365 conf = ieee80211_get_hw_conf(priv->hw);
2366
2367 spin_lock_irqsave(&priv->lock, flags);
2368 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2369 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2370
2371 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2372
2373 tsf = priv->timestamp1;
2374 tsf = ((tsf << 32) | priv->timestamp0);
2375
2376 beacon_int = priv->beacon_int;
2377 spin_unlock_irqrestore(&priv->lock, flags);
2378
2379 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2380 if (beacon_int == 0) {
2381 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2382 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2383 } else {
2384 priv->rxon_timing.beacon_interval =
2385 cpu_to_le16(beacon_int);
2386 priv->rxon_timing.beacon_interval =
bb8c093b 2387 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2388 le16_to_cpu(priv->rxon_timing.beacon_interval));
2389 }
2390
2391 priv->rxon_timing.atim_window = 0;
2392 } else {
2393 priv->rxon_timing.beacon_interval =
bb8c093b 2394 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2395 /* TODO: we need to get atim_window from upper stack
2396 * for now we set to 0 */
2397 priv->rxon_timing.atim_window = 0;
2398 }
2399
2400 interval_tm_unit =
2401 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2402 result = do_div(tsf, interval_tm_unit);
2403 priv->rxon_timing.beacon_init_val =
2404 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2405
2406 IWL_DEBUG_ASSOC
2407 ("beacon interval %d beacon timer %d beacon tim %d\n",
2408 le16_to_cpu(priv->rxon_timing.beacon_interval),
2409 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2410 le16_to_cpu(priv->rxon_timing.atim_window));
2411}
2412
bb8c093b 2413static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY		 2414{
2415 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2416 IWL_ERROR("APs don't scan.\n");
2417 return 0;
2418 }
2419
bb8c093b 2420 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2421 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2422 return -EIO;
2423 }
2424
2425 if (test_bit(STATUS_SCANNING, &priv->status)) {
2426 IWL_DEBUG_SCAN("Scan already in progress.\n");
2427 return -EAGAIN;
2428 }
2429
2430 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2431 IWL_DEBUG_SCAN("Scan request while abort pending. "
2432 "Queuing.\n");
2433 return -EAGAIN;
2434 }
2435
2436 IWL_DEBUG_INFO("Starting scan...\n");
2437 priv->scan_bands = 2;
2438 set_bit(STATUS_SCANNING, &priv->status);
2439 priv->scan_start = jiffies;
2440 priv->scan_pass_start = priv->scan_start;
2441
2442 queue_work(priv->workqueue, &priv->request_scan);
2443
2444 return 0;
2445}
2446
bb8c093b 2447static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2448{
bb8c093b 2449 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2450
2451 if (hw_decrypt)
2452 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2453 else
2454 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2455
2456 return 0;
2457}
2458
8318d78a
JB		 2459static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2460 enum ieee80211_band band)
b481de9c 2461{
8318d78a 2462 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2463 priv->staging_rxon.flags &=
2464 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2465 | RXON_FLG_CCK_MSK);
2466 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2467 } else {
bb8c093b 2468 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2469 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2470 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2471 else
2472 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2473
2474 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2475 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2476
2477 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2478 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2479 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2480 }
2481}
2482
2483/*
01ebd063 2484 * initialize rxon structure with default values from eeprom
b481de9c 2485 */
bb8c093b 2486static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2487{
bb8c093b 2488 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2489
2490 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2491
2492 switch (priv->iw_mode) {
2493 case IEEE80211_IF_TYPE_AP:
2494 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2495 break;
2496
2497 case IEEE80211_IF_TYPE_STA:
2498 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2499 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2500 break;
2501
2502 case IEEE80211_IF_TYPE_IBSS:
2503 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2504 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2505 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2506 RXON_FILTER_ACCEPT_GRP_MSK;
2507 break;
2508
2509 case IEEE80211_IF_TYPE_MNTR:
2510 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2511 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2512 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2513 break;
2514 }
2515
2516#if 0
2517 /* TODO: Figure out when short_preamble would be set and cache from
2518 * that */
2519 if (!hw_to_local(priv->hw)->short_preamble)
2520 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2521 else
2522 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2523#endif
2524
8318d78a 2525 ch_info = iwl3945_get_channel_info(priv, priv->band,
b481de9c
ZY		 2526 le16_to_cpu(priv->staging_rxon.channel));
2527
2528 if (!ch_info)
2529 ch_info = &priv->channel_info[0];
2530
2531 /*
2532 * in some case A channels are all non IBSS
2533 * in this case force B/G channel
2534 */
2535 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2536 !(is_channel_ibss(ch_info)))
2537 ch_info = &priv->channel_info[0];
2538
2539 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2540 if (is_channel_a_band(ch_info))
8318d78a 2541 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2542 else
8318d78a 2543 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2544
8318d78a 2545 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2546
2547 priv->staging_rxon.ofdm_basic_rates =
2548 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2549 priv->staging_rxon.cck_basic_rates =
2550 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2551}
2552
bb8c093b 2553static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2554{
b481de9c 2555 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2556 const struct iwl3945_channel_info *ch_info;
b481de9c 2557
bb8c093b 2558 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2559 priv->band,
b481de9c
ZY		 2560 le16_to_cpu(priv->staging_rxon.channel));
2561
2562 if (!ch_info || !is_channel_ibss(ch_info)) {
2563 IWL_ERROR("channel %d not IBSS channel\n",
2564 le16_to_cpu(priv->staging_rxon.channel));
2565 return -EINVAL;
2566 }
2567 }
2568
b481de9c
ZY		 2569 priv->iw_mode = mode;
2570
bb8c093b 2571 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2572 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2573
bb8c093b 2574 iwl3945_clear_stations_table(priv);
b481de9c 2575
fde3571f
MA		 2576 /* dont commit rxon if rf-kill is on*/
2577 if (!iwl3945_is_ready_rf(priv))
2578 return -EAGAIN;
2579
2580 cancel_delayed_work(&priv->scan_check);
2581 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2582 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2583 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2584 return -EAGAIN;
2585 }
2586
bb8c093b 2587 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2588
2589 return 0;
2590}
2591
bb8c093b 2592static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
b481de9c 2593 struct ieee80211_tx_control *ctl,
bb8c093b 2594 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2595 struct sk_buff *skb_frag,
2596 int last_frag)
2597{
bb8c093b 2598 struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
b481de9c
ZY		 2599
2600 switch (keyinfo->alg) {
2601 case ALG_CCMP:
2602 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2603 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2604 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2605 break;
2606
2607 case ALG_TKIP:
2608#if 0
2609 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2610
2611 if (last_frag)
2612 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2613 8);
2614 else
2615 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2616#endif
2617 break;
2618
2619 case ALG_WEP:
2620 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2621 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2622
2623 if (keyinfo->keylen == 13)
2624 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2625
2626 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2627
2628 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2629 "with key %d\n", ctl->key_idx);
2630 break;
2631
b481de9c
ZY		 2632 default:
2633 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2634 break;
2635 }
2636}
2637
2638/*
2639 * handle build REPLY_TX command notification.
2640 */
bb8c093b
CH		 2641static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2642 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2643 struct ieee80211_tx_control *ctrl,
2644 struct ieee80211_hdr *hdr,
2645 int is_unicast, u8 std_id)
2646{
2647 __le16 *qc;
2648 u16 fc = le16_to_cpu(hdr->frame_control);
2649 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2650
2651 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2652 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2653 tx_flags |= TX_CMD_FLG_ACK_MSK;
2654 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2655 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2656 if (ieee80211_is_probe_response(fc) &&
2657 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2658 tx_flags |= TX_CMD_FLG_TSF_MSK;
2659 } else {
2660 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2661 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2662 }
2663
2664 cmd->cmd.tx.sta_id = std_id;
2665 if (ieee80211_get_morefrag(hdr))
2666 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2667
2668 qc = ieee80211_get_qos_ctrl(hdr);
2669 if (qc) {
2670 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2671 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2672 } else
2673 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2674
2675 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2676 tx_flags |= TX_CMD_FLG_RTS_MSK;
2677 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2678 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2679 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2680 tx_flags |= TX_CMD_FLG_CTS_MSK;
2681 }
2682
2683 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2684 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2685
2686 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2687 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2688 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2689 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2690 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2691 else
bc434dd2 2692 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
b481de9c
ZY		 2693 } else
2694 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2695
2696 cmd->cmd.tx.driver_txop = 0;
2697 cmd->cmd.tx.tx_flags = tx_flags;
2698 cmd->cmd.tx.next_frame_len = 0;
2699}
2700
6440adb5
CB		 2701/**
2702 * iwl3945_get_sta_id - Find station's index within station table
2703 */
bb8c093b 2704static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2705{
2706 int sta_id;
2707 u16 fc = le16_to_cpu(hdr->frame_control);
2708
6440adb5 2709 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2710 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2711 is_multicast_ether_addr(hdr->addr1))
2712 return priv->hw_setting.bcast_sta_id;
2713
2714 switch (priv->iw_mode) {
2715
6440adb5
CB		 2716 /* If we are a client station in a BSS network, use the special
2717 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2718 case IEEE80211_IF_TYPE_STA:
2719 return IWL_AP_ID;
2720
2721 /* If we are an AP, then find the station, or use BCAST */
2722 case IEEE80211_IF_TYPE_AP:
bb8c093b 2723 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2724 if (sta_id != IWL_INVALID_STATION)
2725 return sta_id;
2726 return priv->hw_setting.bcast_sta_id;
2727
6440adb5
CB		 2728 /* If this frame is going out to an IBSS network, find the station,
2729 * or create a new station table entry */
0795af57
JP		 2730 case IEEE80211_IF_TYPE_IBSS: {
2731 DECLARE_MAC_BUF(mac);
2732
6440adb5 2733 /* Create new station table entry */
bb8c093b 2734 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2735 if (sta_id != IWL_INVALID_STATION)
2736 return sta_id;
2737
bb8c093b 2738 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2739
2740 if (sta_id != IWL_INVALID_STATION)
2741 return sta_id;
2742
0795af57 2743 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2744 "Defaulting to broadcast...\n",
0795af57 2745 print_mac(mac, hdr->addr1));
bb8c093b 2746 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2747 return priv->hw_setting.bcast_sta_id;
0795af57 2748 }
b481de9c 2749 default:
01ebd063 2750 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2751 return priv->hw_setting.bcast_sta_id;
2752 }
2753}
2754
2755/*
2756 * start REPLY_TX command process
2757 */
bb8c093b 2758static int iwl3945_tx_skb(struct iwl3945_priv *priv,
b481de9c
ZY		 2759 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2760{
2761 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2762 struct iwl3945_tfd_frame *tfd;
b481de9c
ZY		 2763 u32 *control_flags;
2764 int txq_id = ctl->queue;
bb8c093b
CH		 2765 struct iwl3945_tx_queue *txq = NULL;
2766 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2767 dma_addr_t phys_addr;
2768 dma_addr_t txcmd_phys;
bb8c093b 2769 struct iwl3945_cmd *out_cmd = NULL;
b481de9c
ZY		 2770 u16 len, idx, len_org;
2771 u8 id, hdr_len, unicast;
2772 u8 sta_id;
2773 u16 seq_number = 0;
2774 u16 fc;
2775 __le16 *qc;
2776 u8 wait_write_ptr = 0;
2777 unsigned long flags;
2778 int rc;
2779
2780 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2781 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2782 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2783 goto drop_unlock;
2784 }
2785
32bfd35d
JB		 2786 if (!priv->vif) {
2787 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY		 2788 goto drop_unlock;
2789 }
2790
8318d78a 2791 if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2792 IWL_ERROR("ERROR: No TX rate available.\n");
2793 goto drop_unlock;
2794 }
2795
2796 unicast = !is_multicast_ether_addr(hdr->addr1);
2797 id = 0;
2798
2799 fc = le16_to_cpu(hdr->frame_control);
2800
c8b0e6e1 2801#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2802 if (ieee80211_is_auth(fc))
2803 IWL_DEBUG_TX("Sending AUTH frame\n");
2804 else if (ieee80211_is_assoc_request(fc))
2805 IWL_DEBUG_TX("Sending ASSOC frame\n");
2806 else if (ieee80211_is_reassoc_request(fc))
2807 IWL_DEBUG_TX("Sending REASSOC frame\n");
2808#endif
2809
7878a5a4 2810 /* drop all data frame if we are not associated */
a6477249
RC		 2811 if ((!iwl3945_is_associated(priv) ||
2812 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
b481de9c 2813 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
bb8c093b 2814 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2815 goto drop_unlock;
2816 }
2817
2818 spin_unlock_irqrestore(&priv->lock, flags);
2819
2820 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
CB		 2821
2822 /* Find (or create) index into station table for destination station */
bb8c093b 2823 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2824 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2825 DECLARE_MAC_BUF(mac);
2826
2827 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2828 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2829 goto drop;
2830 }
2831
2832 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2833
2834 qc = ieee80211_get_qos_ctrl(hdr);
2835 if (qc) {
2836 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2837 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2838 IEEE80211_SCTL_SEQ;
2839 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2840 (hdr->seq_ctrl &
2841 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2842 seq_number += 0x10;
2843 }
6440adb5
CB		 2844
2845 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2846 txq = &priv->txq[txq_id];
2847 q = &txq->q;
2848
2849 spin_lock_irqsave(&priv->lock, flags);
2850
6440adb5 2851 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2852 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2853 memset(tfd, 0, sizeof(*tfd));
2854 control_flags = (u32 *) tfd;
fc4b6853 2855 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2856
6440adb5 2857 /* Set up driver data for this TFD */
bb8c093b 2858 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853
TW		 2859 txq->txb[q->write_ptr].skb[0] = skb;
2860 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2861 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
CB		 2862
2863 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2864 out_cmd = &txq->cmd[idx];
2865 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2866 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2867
2868 /*
2869 * Set up the Tx-command (not MAC!) header.
2870 * Store the chosen Tx queue and TFD index within the sequence field;
2871 * after Tx, uCode's Tx response will return this value so driver can
2872 * locate the frame within the tx queue and do post-tx processing.
2873 */
b481de9c
ZY		 2874 out_cmd->hdr.cmd = REPLY_TX;
2875 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2876 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2877
2878 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2879 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2880
6440adb5
CB		 2881 /*
2882 * Use the first empty entry in this queue's command buffer array
2883 * to contain the Tx command and MAC header concatenated together
2884 * (payload data will be in another buffer).
2885 * Size of this varies, due to varying MAC header length.
2886 * If end is not dword aligned, we'll have 2 extra bytes at the end
2887 * of the MAC header (device reads on dword boundaries).
2888 * We'll tell device about this padding later.
2889 */
b481de9c 2890 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2891 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2892
2893 len_org = len;
2894 len = (len + 3) & ~3;
2895
2896 if (len_org != len)
2897 len_org = 1;
2898 else
2899 len_org = 0;
2900
6440adb5
CB		 2901 /* Physical address of this Tx command's header (not MAC header!),
2902 * within command buffer array. */
bb8c093b
CH		 2903 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2904 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2905
6440adb5
CB		 2906 /* Add buffer containing Tx command and MAC(!) header to TFD's
2907 * first entry */
bb8c093b 2908 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY		 2909
2910 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
bb8c093b 2911 iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
b481de9c 2912
6440adb5
CB		 2913 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2914 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2915 len = skb->len - hdr_len;
2916 if (len) {
2917 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2918 len, PCI_DMA_TODEVICE);
bb8c093b 2919 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2920 }
2921
b481de9c 2922 if (!len)
6440adb5 2923 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2924 *control_flags = TFD_CTL_COUNT_SET(1);
2925 else
6440adb5
CB		 2926 /* Else use 2 buffers.
2927 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2928 *control_flags = TFD_CTL_COUNT_SET(2) |
2929 TFD_CTL_PAD_SET(U32_PAD(len));
2930
6440adb5 2931 /* Total # bytes to be transmitted */
b481de9c
ZY		 2932 len = (u16)skb->len;
2933 out_cmd->cmd.tx.len = cpu_to_le16(len);
2934
2935 /* TODO need this for burst mode later on */
bb8c093b 2936 iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY		 2937
2938 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 2939 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c
ZY		 2940
2941 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2942 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2943
2944 if (!ieee80211_get_morefrag(hdr)) {
2945 txq->need_update = 1;
2946 if (qc) {
2947 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2948 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2949 }
2950 } else {
2951 wait_write_ptr = 1;
2952 txq->need_update = 0;
2953 }
2954
bb8c093b 2955 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2956 sizeof(out_cmd->cmd.tx));
2957
bb8c093b 2958 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY		 2959 ieee80211_get_hdrlen(fc));
2960
6440adb5 2961 /* Tell device the write index *just past* this latest filled TFD */
bb8c093b
CH		 2962 q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
2963 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2964 spin_unlock_irqrestore(&priv->lock, flags);
2965
2966 if (rc)
2967 return rc;
2968
bb8c093b 2969 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2970 && priv->mac80211_registered) {
2971 if (wait_write_ptr) {
2972 spin_lock_irqsave(&priv->lock, flags);
2973 txq->need_update = 1;
bb8c093b 2974 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2975 spin_unlock_irqrestore(&priv->lock, flags);
2976 }
2977
2978 ieee80211_stop_queue(priv->hw, ctl->queue);
2979 }
2980
2981 return 0;
2982
2983drop_unlock:
2984 spin_unlock_irqrestore(&priv->lock, flags);
2985drop:
2986 return -1;
2987}
2988
bb8c093b 2989static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2990{
8318d78a 2991 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2992 struct ieee80211_rate *rate;
2993 int i;
2994
8318d78a
JB		 2995 sband = iwl3945_get_band(priv, priv->band);
2996 if (!sband) {
c4ba9621
SA		 2997 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2998 return;
2999 }
b481de9c
ZY		 3000
3001 priv->active_rate = 0;
3002 priv->active_rate_basic = 0;
3003
8318d78a
JB		 3004 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
3005 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
3006
3007 for (i = 0; i < sband->n_bitrates; i++) {
3008 rate = &sband->bitrates[i];
3009 if ((rate->hw_value < IWL_RATE_COUNT) &&
3010 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
3011 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
3012 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
3013 priv->active_rate |= (1 << rate->hw_value);
3014 }
b481de9c
ZY		 3015 }
3016
3017 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
3018 priv->active_rate, priv->active_rate_basic);
3019
3020 /*
3021 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
3022 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
3023 * OFDM
3024 */
3025 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
3026 priv->staging_rxon.cck_basic_rates =
3027 ((priv->active_rate_basic &
3028 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
3029 else
3030 priv->staging_rxon.cck_basic_rates =
3031 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
3032
3033 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
3034 priv->staging_rxon.ofdm_basic_rates =
3035 ((priv->active_rate_basic &
3036 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
3037 IWL_FIRST_OFDM_RATE) & 0xFF;
3038 else
3039 priv->staging_rxon.ofdm_basic_rates =
3040 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
3041}
3042
bb8c093b 3043static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 3044{
3045 unsigned long flags;
3046
3047 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
3048 return;
3049
3050 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
3051 disable_radio ? "OFF" : "ON");
3052
3053 if (disable_radio) {
bb8c093b 3054 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3055 /* FIXME: This is a workaround for AP */
3056 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
3057 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3058 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3059 CSR_UCODE_SW_BIT_RFKILL);
3060 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 3061 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 3062 set_bit(STATUS_RF_KILL_SW, &priv->status);
3063 }
3064 return;
3065 }
3066
3067 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3068 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3069
3070 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3071 spin_unlock_irqrestore(&priv->lock, flags);
3072
3073 /* wake up ucode */
3074 msleep(10);
3075
3076 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 3077 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
3078 if (!iwl3945_grab_nic_access(priv))
3079 iwl3945_release_nic_access(priv);
b481de9c
ZY		 3080 spin_unlock_irqrestore(&priv->lock, flags);
3081
3082 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
3083 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
3084 "disabled by HW switch\n");
3085 return;
3086 }
3087
3088 queue_work(priv->workqueue, &priv->restart);
3089 return;
3090}
3091
bb8c093b 3092void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 3093 u32 decrypt_res, struct ieee80211_rx_status *stats)
3094{
3095 u16 fc =
3096 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
3097
3098 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
3099 return;
3100
3101 if (!(fc & IEEE80211_FCTL_PROTECTED))
3102 return;
3103
3104 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
3105 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
3106 case RX_RES_STATUS_SEC_TYPE_TKIP:
3107 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3108 RX_RES_STATUS_BAD_ICV_MIC)
3109 stats->flag |= RX_FLAG_MMIC_ERROR;
3110 case RX_RES_STATUS_SEC_TYPE_WEP:
3111 case RX_RES_STATUS_SEC_TYPE_CCMP:
3112 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3113 RX_RES_STATUS_DECRYPT_OK) {
3114 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
3115 stats->flag |= RX_FLAG_DECRYPTED;
3116 }
3117 break;
3118
3119 default:
3120 break;
3121 }
3122}
3123
b481de9c
ZY		 3124#define IWL_PACKET_RETRY_TIME HZ
3125
bb8c093b 3126int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 3127{
3128 u16 sc = le16_to_cpu(header->seq_ctrl);
3129 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
3130 u16 frag = sc & IEEE80211_SCTL_FRAG;
3131 u16 *last_seq, *last_frag;
3132 unsigned long *last_time;
3133
3134 switch (priv->iw_mode) {
3135 case IEEE80211_IF_TYPE_IBSS:{
3136 struct list_head *p;
bb8c093b 3137 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY		 3138 u8 *mac = header->addr2;
3139 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
3140
3141 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 3142 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY		 3143 if (!compare_ether_addr(entry->mac, mac))
3144 break;
3145 }
3146 if (p == &priv->ibss_mac_hash[index]) {
3147 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
3148 if (!entry) {
bc434dd2 3149 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 3150 return 0;
3151 }
3152 memcpy(entry->mac, mac, ETH_ALEN);
3153 entry->seq_num = seq;
3154 entry->frag_num = frag;
3155 entry->packet_time = jiffies;
bc434dd2 3156 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 3157 return 0;
3158 }
3159 last_seq = &entry->seq_num;
3160 last_frag = &entry->frag_num;
3161 last_time = &entry->packet_time;
3162 break;
3163 }
3164 case IEEE80211_IF_TYPE_STA:
3165 last_seq = &priv->last_seq_num;
3166 last_frag = &priv->last_frag_num;
3167 last_time = &priv->last_packet_time;
3168 break;
3169 default:
3170 return 0;
3171 }
3172 if ((*last_seq == seq) &&
3173 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
3174 if (*last_frag == frag)
3175 goto drop;
3176 if (*last_frag + 1 != frag)
3177 /* out-of-order fragment */
3178 goto drop;
3179 } else
3180 *last_seq = seq;
3181
3182 *last_frag = frag;
3183 *last_time = jiffies;
3184 return 0;
3185
3186 drop:
3187 return 1;
3188}
3189
c8b0e6e1 3190#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 3191
3192#include "iwl-spectrum.h"
3193
3194#define BEACON_TIME_MASK_LOW 0x00FFFFFF
3195#define BEACON_TIME_MASK_HIGH 0xFF000000
3196#define TIME_UNIT 1024
3197
3198/*
3199 * extended beacon time format
3200 * time in usec will be changed into a 32-bit value in 8:24 format
3201 * the high 1 byte is the beacon counts
3202 * the lower 3 bytes is the time in usec within one beacon interval
3203 */
3204
bb8c093b 3205static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 3206{
3207 u32 quot;
3208 u32 rem;
3209 u32 interval = beacon_interval * 1024;
3210
3211 if (!interval || !usec)
3212 return 0;
3213
3214 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3215 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3216
3217 return (quot << 24) + rem;
3218}
3219
3220/* base is usually what we get from ucode with each received frame,
3221 * the same as HW timer counter counting down
3222 */
3223
bb8c093b 3224static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 3225{
3226 u32 base_low = base & BEACON_TIME_MASK_LOW;
3227 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3228 u32 interval = beacon_interval * TIME_UNIT;
3229 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3230 (addon & BEACON_TIME_MASK_HIGH);
3231
3232 if (base_low > addon_low)
3233 res += base_low - addon_low;
3234 else if (base_low < addon_low) {
3235 res += interval + base_low - addon_low;
3236 res += (1 << 24);
3237 } else
3238 res += (1 << 24);
3239
3240 return cpu_to_le32(res);
3241}
3242
bb8c093b 3243static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 3244 struct ieee80211_measurement_params *params,
3245 u8 type)
3246{
bb8c093b
CH		 3247 struct iwl3945_spectrum_cmd spectrum;
3248 struct iwl3945_rx_packet *res;
3249 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 3250 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3251 .data = (void *)&spectrum,
3252 .meta.flags = CMD_WANT_SKB,
3253 };
3254 u32 add_time = le64_to_cpu(params->start_time);
3255 int rc;
3256 int spectrum_resp_status;
3257 int duration = le16_to_cpu(params->duration);
3258
bb8c093b 3259 if (iwl3945_is_associated(priv))
b481de9c 3260 add_time =
bb8c093b 3261 iwl3945_usecs_to_beacons(
b481de9c
ZY		 3262 le64_to_cpu(params->start_time) - priv->last_tsf,
3263 le16_to_cpu(priv->rxon_timing.beacon_interval));
3264
3265 memset(&spectrum, 0, sizeof(spectrum));
3266
3267 spectrum.channel_count = cpu_to_le16(1);
3268 spectrum.flags =
3269 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3270 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3271 cmd.len = sizeof(spectrum);
3272 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3273
bb8c093b 3274 if (iwl3945_is_associated(priv))
b481de9c 3275 spectrum.start_time =
bb8c093b 3276 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 3277 add_time,
3278 le16_to_cpu(priv->rxon_timing.beacon_interval));
3279 else
3280 spectrum.start_time = 0;
3281
3282 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3283 spectrum.channels[0].channel = params->channel;
3284 spectrum.channels[0].type = type;
3285 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3286 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3287 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3288
bb8c093b 3289 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 3290 if (rc)
3291 return rc;
3292
bb8c093b 3293 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 3294 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3295 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3296 rc = -EIO;
3297 }
3298
3299 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3300 switch (spectrum_resp_status) {
3301 case 0: /* Command will be handled */
3302 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 3303 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3304 res->u.spectrum.id);
b481de9c
ZY		 3305 priv->measurement_status &= ~MEASUREMENT_READY;
3306 }
3307 priv->measurement_status |= MEASUREMENT_ACTIVE;
3308 rc = 0;
3309 break;
3310
3311 case 1: /* Command will not be handled */
3312 rc = -EAGAIN;
3313 break;
3314 }
3315
3316 dev_kfree_skb_any(cmd.meta.u.skb);
3317
3318 return rc;
3319}
3320#endif
3321
bb8c093b
CH		 3322static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
3323 struct iwl3945_tx_info *tx_sta)
b481de9c
ZY		 3324{
3325
3326 tx_sta->status.ack_signal = 0;
3327 tx_sta->status.excessive_retries = 0;
3328 tx_sta->status.queue_length = 0;
3329 tx_sta->status.queue_number = 0;
3330
3331 if (in_interrupt())
3332 ieee80211_tx_status_irqsafe(priv->hw,
3333 tx_sta->skb[0], &(tx_sta->status));
3334 else
3335 ieee80211_tx_status(priv->hw,
3336 tx_sta->skb[0], &(tx_sta->status));
3337
3338 tx_sta->skb[0] = NULL;
3339}
3340
3341/**
6440adb5 3342 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
b481de9c 3343 *
6440adb5
CB		 3344 * When FW advances 'R' index, all entries between old and new 'R' index
3345 * need to be reclaimed. As result, some free space forms. If there is
3346 * enough free space (> low mark), wake the stack that feeds us.
b481de9c 3347 */
bb8c093b 3348static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
b481de9c 3349{
bb8c093b
CH		 3350 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3351 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 3352 int nfreed = 0;
3353
3354 if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
3355 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3356 "is out of range [0-%d] %d %d.\n", txq_id,
fc4b6853 3357 index, q->n_bd, q->write_ptr, q->read_ptr);
b481de9c
ZY		 3358 return 0;
3359 }
3360
bb8c093b 3361 for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
fc4b6853 3362 q->read_ptr != index;
bb8c093b 3363 q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
b481de9c 3364 if (txq_id != IWL_CMD_QUEUE_NUM) {
bb8c093b 3365 iwl3945_txstatus_to_ieee(priv,
fc4b6853 3366 &(txq->txb[txq->q.read_ptr]));
bb8c093b 3367 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c
ZY		 3368 } else if (nfreed > 1) {
3369 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
fc4b6853 3370 q->write_ptr, q->read_ptr);
b481de9c
ZY		 3371 queue_work(priv->workqueue, &priv->restart);
3372 }
3373 nfreed++;
3374 }
3375
bb8c093b 3376 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
b481de9c
ZY		 3377 (txq_id != IWL_CMD_QUEUE_NUM) &&
3378 priv->mac80211_registered)
3379 ieee80211_wake_queue(priv->hw, txq_id);
3380
3381
3382 return nfreed;
3383}
3384
bb8c093b 3385static int iwl3945_is_tx_success(u32 status)
b481de9c
ZY		 3386{
3387 return (status & 0xFF) == 0x1;
3388}
3389
3390/******************************************************************************
3391 *
3392 * Generic RX handler implementations
3393 *
3394 ******************************************************************************/
6440adb5
CB		 3395/**
3396 * iwl3945_rx_reply_tx - Handle Tx response
3397 */
bb8c093b
CH		 3398static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
3399 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3400{
bb8c093b 3401 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3402 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3403 int txq_id = SEQ_TO_QUEUE(sequence);
3404 int index = SEQ_TO_INDEX(sequence);
bb8c093b 3405 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
b481de9c 3406 struct ieee80211_tx_status *tx_status;
bb8c093b 3407 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
b481de9c
ZY		 3408 u32 status = le32_to_cpu(tx_resp->status);
3409
3410 if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
3411 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3412 "is out of range [0-%d] %d %d\n", txq_id,
fc4b6853
TW		 3413 index, txq->q.n_bd, txq->q.write_ptr,
3414 txq->q.read_ptr);
b481de9c
ZY		 3415 return;
3416 }
3417
fc4b6853 3418 tx_status = &(txq->txb[txq->q.read_ptr].status);
b481de9c
ZY		 3419
3420 tx_status->retry_count = tx_resp->failure_frame;
3421 tx_status->queue_number = status;
3422 tx_status->queue_length = tx_resp->bt_kill_count;
3423 tx_status->queue_length |= tx_resp->failure_rts;
3424
3425 tx_status->flags =
bb8c093b 3426 iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
b481de9c 3427
b481de9c 3428 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
bb8c093b 3429 txq_id, iwl3945_get_tx_fail_reason(status), status,
b481de9c
ZY		 3430 tx_resp->rate, tx_resp->failure_frame);
3431
3432 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
3433 if (index != -1)
bb8c093b 3434 iwl3945_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3435
3436 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3437 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3438}
3439
3440
bb8c093b
CH		 3441static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3442 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3443{
bb8c093b
CH		 3444 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3445 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3446 struct delayed_work *pwork;
3447
3448 palive = &pkt->u.alive_frame;
3449
3450 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3451 "0x%01X 0x%01X\n",
3452 palive->is_valid, palive->ver_type,
3453 palive->ver_subtype);
3454
3455 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3456 IWL_DEBUG_INFO("Initialization Alive received.\n");
3457 memcpy(&priv->card_alive_init,
3458 &pkt->u.alive_frame,
bb8c093b 3459 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3460 pwork = &priv->init_alive_start;
3461 } else {
3462 IWL_DEBUG_INFO("Runtime Alive received.\n");
3463 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3464 sizeof(struct iwl3945_alive_resp));
b481de9c 3465 pwork = &priv->alive_start;
bb8c093b 3466 iwl3945_disable_events(priv);
b481de9c
ZY		 3467 }
3468
3469 /* We delay the ALIVE response by 5ms to
3470 * give the HW RF Kill time to activate... */
3471 if (palive->is_valid == UCODE_VALID_OK)
3472 queue_delayed_work(priv->workqueue, pwork,
3473 msecs_to_jiffies(5));
3474 else
3475 IWL_WARNING("uCode did not respond OK.\n");
3476}
3477
bb8c093b
CH		 3478static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3479 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3480{
bb8c093b 3481 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3482
3483 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3484 return;
3485}
3486
bb8c093b
CH		 3487static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3488 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3489{
bb8c093b 3490 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3491
3492 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3493 "seq 0x%04X ser 0x%08X\n",
3494 le32_to_cpu(pkt->u.err_resp.error_type),
3495 get_cmd_string(pkt->u.err_resp.cmd_id),
3496 pkt->u.err_resp.cmd_id,
3497 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3498 le32_to_cpu(pkt->u.err_resp.error_info));
3499}
3500
3501#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3502
bb8c093b 3503static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3504{
bb8c093b
CH		 3505 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3506 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3507 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3508 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3509 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3510 rxon->channel = csa->channel;
3511 priv->staging_rxon.channel = csa->channel;
3512}
3513
bb8c093b
CH		 3514static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3515 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3516{
c8b0e6e1 3517#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3518 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3519 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3520
3521 if (!report->state) {
3522 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3523 "Spectrum Measure Notification: Start\n");
3524 return;
3525 }
3526
3527 memcpy(&priv->measure_report, report, sizeof(*report));
3528 priv->measurement_status |= MEASUREMENT_READY;
3529#endif
3530}
3531
bb8c093b
CH		 3532static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3533 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3534{
c8b0e6e1 3535#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3536 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3537 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3538 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3539 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3540#endif
3541}
3542
bb8c093b
CH		 3543static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3544 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3545{
bb8c093b 3546 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3547 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3548 "notification for %s:\n",
3549 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3550 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3551}
3552
bb8c093b 3553static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3554{
bb8c093b
CH		 3555 struct iwl3945_priv *priv =
3556 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3557 struct sk_buff *beacon;
3558
3559 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
32bfd35d 3560 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
b481de9c
ZY		 3561
3562 if (!beacon) {
3563 IWL_ERROR("update beacon failed\n");
3564 return;
3565 }
3566
3567 mutex_lock(&priv->mutex);
3568 /* new beacon skb is allocated every time; dispose previous.*/
3569 if (priv->ibss_beacon)
3570 dev_kfree_skb(priv->ibss_beacon);
3571
3572 priv->ibss_beacon = beacon;
3573 mutex_unlock(&priv->mutex);
3574
bb8c093b 3575 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3576}
3577
bb8c093b
CH		 3578static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3579 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3580{
c8b0e6e1 3581#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3582 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3583 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3584 u8 rate = beacon->beacon_notify_hdr.rate;
3585
3586 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3587 "tsf %d %d rate %d\n",
3588 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3589 beacon->beacon_notify_hdr.failure_frame,
3590 le32_to_cpu(beacon->ibss_mgr_status),
3591 le32_to_cpu(beacon->high_tsf),
3592 le32_to_cpu(beacon->low_tsf), rate);
3593#endif
3594
3595 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3596 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3597 queue_work(priv->workqueue, &priv->beacon_update);
3598}
3599
3600/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3601static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3602 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3603{
c8b0e6e1 3604#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3605 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3606 struct iwl3945_scanreq_notification *notif =
3607 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3608
3609 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3610#endif
3611}
3612
3613/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3614static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3615 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3616{
bb8c093b
CH		 3617 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3618 struct iwl3945_scanstart_notification *notif =
3619 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3620 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3621 IWL_DEBUG_SCAN("Scan start: "
3622 "%d [802.11%s] "
3623 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3624 notif->channel,
3625 notif->band ? "bg" : "a",
3626 notif->tsf_high,
3627 notif->tsf_low, notif->status, notif->beacon_timer);
3628}
3629
3630/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3631static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3632 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3633{
bb8c093b
CH		 3634 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3635 struct iwl3945_scanresults_notification *notif =
3636 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3637
3638 IWL_DEBUG_SCAN("Scan ch.res: "
3639 "%d [802.11%s] "
3640 "(TSF: 0x%08X:%08X) - %d "
3641 "elapsed=%lu usec (%dms since last)\n",
3642 notif->channel,
3643 notif->band ? "bg" : "a",
3644 le32_to_cpu(notif->tsf_high),
3645 le32_to_cpu(notif->tsf_low),
3646 le32_to_cpu(notif->statistics[0]),
3647 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3648 jiffies_to_msecs(elapsed_jiffies
3649 (priv->last_scan_jiffies, jiffies)));
3650
3651 priv->last_scan_jiffies = jiffies;
7878a5a4 3652 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3653}
3654
3655/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3656static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3657 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3658{
bb8c093b
CH		 3659 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3660 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3661
3662 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3663 scan_notif->scanned_channels,
3664 scan_notif->tsf_low,
3665 scan_notif->tsf_high, scan_notif->status);
3666
3667 /* The HW is no longer scanning */
3668 clear_bit(STATUS_SCAN_HW, &priv->status);
3669
3670 /* The scan completion notification came in, so kill that timer... */
3671 cancel_delayed_work(&priv->scan_check);
3672
3673 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3674 (priv->scan_bands == 2) ? "2.4" : "5.2",
3675 jiffies_to_msecs(elapsed_jiffies
3676 (priv->scan_pass_start, jiffies)));
3677
3678 /* Remove this scanned band from the list
3679 * of pending bands to scan */
3680 priv->scan_bands--;
3681
3682 /* If a request to abort was given, or the scan did not succeed
3683 * then we reset the scan state machine and terminate,
3684 * re-queuing another scan if one has been requested */
3685 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3686 IWL_DEBUG_INFO("Aborted scan completed.\n");
3687 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3688 } else {
3689 /* If there are more bands on this scan pass reschedule */
3690 if (priv->scan_bands > 0)
3691 goto reschedule;
3692 }
3693
3694 priv->last_scan_jiffies = jiffies;
7878a5a4 3695 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3696 IWL_DEBUG_INFO("Setting scan to off\n");
3697
3698 clear_bit(STATUS_SCANNING, &priv->status);
3699
3700 IWL_DEBUG_INFO("Scan took %dms\n",
3701 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3702
3703 queue_work(priv->workqueue, &priv->scan_completed);
3704
3705 return;
3706
3707reschedule:
3708 priv->scan_pass_start = jiffies;
3709 queue_work(priv->workqueue, &priv->request_scan);
3710}
3711
3712/* Handle notification from uCode that card's power state is changing
3713 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3714static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3715 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3716{
bb8c093b 3717 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3718 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3719 unsigned long status = priv->status;
3720
3721 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3722 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3723 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3724
bb8c093b 3725 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3726 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3727
3728 if (flags & HW_CARD_DISABLED)
3729 set_bit(STATUS_RF_KILL_HW, &priv->status);
3730 else
3731 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3732
3733
3734 if (flags & SW_CARD_DISABLED)
3735 set_bit(STATUS_RF_KILL_SW, &priv->status);
3736 else
3737 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3738
bb8c093b 3739 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3740
3741 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3742 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3743 (test_bit(STATUS_RF_KILL_SW, &status) !=
3744 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3745 queue_work(priv->workqueue, &priv->rf_kill);
3746 else
3747 wake_up_interruptible(&priv->wait_command_queue);
3748}
3749
3750/**
bb8c093b 3751 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3752 *
3753 * Setup the RX handlers for each of the reply types sent from the uCode
3754 * to the host.
3755 *
3756 * This function chains into the hardware specific files for them to setup
3757 * any hardware specific handlers as well.
3758 */
bb8c093b 3759static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3760{
bb8c093b
CH		 3761 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3762 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3763 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3764 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3765 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3766 iwl3945_rx_spectrum_measure_notif;
3767 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3768 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3769 iwl3945_rx_pm_debug_statistics_notif;
3770 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3771
9fbab516
BC		 3772 /*
3773 * The same handler is used for both the REPLY to a discrete
3774 * statistics request from the host as well as for the periodic
3775 * statistics notifications (after received beacons) from the uCode.
b481de9c 3776 */
bb8c093b
CH		 3777 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3778 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3779
bb8c093b
CH		 3780 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3781 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3782 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3783 iwl3945_rx_scan_results_notif;
b481de9c 3784 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3785 iwl3945_rx_scan_complete_notif;
3786 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
3787 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c 3788
9fbab516 3789 /* Set up hardware specific Rx handlers */
bb8c093b 3790 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3791}
3792
3793/**
bb8c093b 3794 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3795 * @rxb: Rx buffer to reclaim
3796 *
3797 * If an Rx buffer has an async callback associated with it the callback
3798 * will be executed. The attached skb (if present) will only be freed
3799 * if the callback returns 1
3800 */
bb8c093b
CH		 3801static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3802 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3803{
bb8c093b 3804 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3805 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3806 int txq_id = SEQ_TO_QUEUE(sequence);
3807 int index = SEQ_TO_INDEX(sequence);
3808 int huge = sequence & SEQ_HUGE_FRAME;
3809 int cmd_index;
bb8c093b 3810 struct iwl3945_cmd *cmd;
b481de9c
ZY		 3811
3812 /* If a Tx command is being handled and it isn't in the actual
3813 * command queue then there a command routing bug has been introduced
3814 * in the queue management code. */
3815 if (txq_id != IWL_CMD_QUEUE_NUM)
3816 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
3817 txq_id, pkt->hdr.cmd);
3818 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3819
3820 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3821 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3822
3823 /* Input error checking is done when commands are added to queue. */
3824 if (cmd->meta.flags & CMD_WANT_SKB) {
3825 cmd->meta.source->u.skb = rxb->skb;
3826 rxb->skb = NULL;
3827 } else if (cmd->meta.u.callback &&
3828 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3829 rxb->skb = NULL;
3830
bb8c093b 3831 iwl3945_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3832
3833 if (!(cmd->meta.flags & CMD_ASYNC)) {
3834 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3835 wake_up_interruptible(&priv->wait_command_queue);
3836 }
3837}
3838
3839/************************** RX-FUNCTIONS ****************************/
3840/*
3841 * Rx theory of operation
3842 *
3843 * The host allocates 32 DMA target addresses and passes the host address
3844 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3845 * 0 to 31
3846 *
3847 * Rx Queue Indexes
3848 * The host/firmware share two index registers for managing the Rx buffers.
3849 *
3850 * The READ index maps to the first position that the firmware may be writing
3851 * to -- the driver can read up to (but not including) this position and get
3852 * good data.
3853 * The READ index is managed by the firmware once the card is enabled.
3854 *
3855 * The WRITE index maps to the last position the driver has read from -- the
3856 * position preceding WRITE is the last slot the firmware can place a packet.
3857 *
3858 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3859 * WRITE = READ.
3860 *
9fbab516 3861 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3862 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3863 *
9fbab516 3864 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3865 * and fire the RX interrupt. The driver can then query the READ index and
3866 * process as many packets as possible, moving the WRITE index forward as it
3867 * resets the Rx queue buffers with new memory.
3868 *
3869 * The management in the driver is as follows:
3870 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3871 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3872 * to replenish the iwl->rxq->rx_free.
bb8c093b 3873 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3874 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3875 * 'processed' and 'read' driver indexes as well)
3876 * + A received packet is processed and handed to the kernel network stack,
3877 * detached from the iwl->rxq. The driver 'processed' index is updated.
3878 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3879 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3880 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3881 * were enough free buffers and RX_STALLED is set it is cleared.
3882 *
3883 *
3884 * Driver sequence:
3885 *
9fbab516
BC		 3886 * iwl3945_rx_queue_alloc() Allocates rx_free
3887 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3888 * iwl3945_rx_queue_restock
9fbab516 3889 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3890 * queue, updates firmware pointers, and updates
3891 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3892 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3893 *
3894 * -- enable interrupts --
9fbab516 3895 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3896 * READ INDEX, detaching the SKB from the pool.
3897 * Moves the packet buffer from queue to rx_used.
bb8c093b 3898 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3899 * slots.
3900 * ...
3901 *
3902 */
3903
3904/**
bb8c093b 3905 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3906 */
bb8c093b 3907static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3908{
3909 int s = q->read - q->write;
3910 if (s <= 0)
3911 s += RX_QUEUE_SIZE;
3912 /* keep some buffer to not confuse full and empty queue */
3913 s -= 2;
3914 if (s < 0)
3915 s = 0;
3916 return s;
3917}
3918
3919/**
bb8c093b 3920 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3921 */
bb8c093b 3922int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3923{
3924 u32 reg = 0;
3925 int rc = 0;
3926 unsigned long flags;
3927
3928 spin_lock_irqsave(&q->lock, flags);
3929
3930 if (q->need_update == 0)
3931 goto exit_unlock;
3932
6440adb5 3933 /* If power-saving is in use, make sure device is awake */
b481de9c 3934 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3935 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3936
3937 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3938 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3939 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3940 goto exit_unlock;
3941 }
3942
bb8c093b 3943 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3944 if (rc)
3945 goto exit_unlock;
3946
6440adb5 3947 /* Device expects a multiple of 8 */
bb8c093b 3948 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3949 q->write & ~0x7);
bb8c093b 3950 iwl3945_release_nic_access(priv);
6440adb5
CB		 3951
3952 /* Else device is assumed to be awake */
b481de9c 3953 } else
6440adb5 3954 /* Device expects a multiple of 8 */
bb8c093b 3955 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3956
3957
3958 q->need_update = 0;
3959
3960 exit_unlock:
3961 spin_unlock_irqrestore(&q->lock, flags);
3962 return rc;
3963}
3964
3965/**
9fbab516 3966 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3967 */
bb8c093b 3968static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3969 dma_addr_t dma_addr)
3970{
3971 return cpu_to_le32((u32)dma_addr);
3972}
3973
3974/**
bb8c093b 3975 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3976 *
9fbab516 3977 * If there are slots in the RX queue that need to be restocked,
b481de9c 3978 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3979 * as we can, pulling from rx_free.
b481de9c
ZY		 3980 *
3981 * This moves the 'write' index forward to catch up with 'processed', and
3982 * also updates the memory address in the firmware to reference the new
3983 * target buffer.
3984 */
bb8c093b 3985static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3986{
bb8c093b 3987 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3988 struct list_head *element;
bb8c093b 3989 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3990 unsigned long flags;
3991 int write, rc;
3992
3993 spin_lock_irqsave(&rxq->lock, flags);
3994 write = rxq->write & ~0x7;
bb8c093b 3995 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3996 /* Get next free Rx buffer, remove from free list */
b481de9c 3997 element = rxq->rx_free.next;
bb8c093b 3998 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3999 list_del(element);
6440adb5
CB		 4000
4001 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 4002 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 4003 rxq->queue[rxq->write] = rxb;
4004 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
4005 rxq->free_count--;
4006 }
4007 spin_unlock_irqrestore(&rxq->lock, flags);
4008 /* If the pre-allocated buffer pool is dropping low, schedule to
4009 * refill it */
4010 if (rxq->free_count <= RX_LOW_WATERMARK)
4011 queue_work(priv->workqueue, &priv->rx_replenish);
4012
4013
6440adb5
CB		 4014 /* If we've added more space for the firmware to place data, tell it.
4015 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 4016 if ((write != (rxq->write & ~0x7))
4017 || (abs(rxq->write - rxq->read) > 7)) {
4018 spin_lock_irqsave(&rxq->lock, flags);
4019 rxq->need_update = 1;
4020 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 4021 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 4022 if (rc)
4023 return rc;
4024 }
4025
4026 return 0;
4027}
4028
4029/**
bb8c093b 4030 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 4031 *
4032 * When moving to rx_free an SKB is allocated for the slot.
4033 *
bb8c093b 4034 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 4035 * This is called as a scheduled work item (except for during initialization)
b481de9c 4036 */
5c0eef96 4037static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 4038{
bb8c093b 4039 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 4040 struct list_head *element;
bb8c093b 4041 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 4042 unsigned long flags;
4043 spin_lock_irqsave(&rxq->lock, flags);
4044 while (!list_empty(&rxq->rx_used)) {
4045 element = rxq->rx_used.next;
bb8c093b 4046 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 4047
4048 /* Alloc a new receive buffer */
b481de9c
ZY		 4049 rxb->skb =
4050 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
4051 if (!rxb->skb) {
4052 if (net_ratelimit())
4053 printk(KERN_CRIT DRV_NAME
4054 ": Can not allocate SKB buffers\n");
4055 /* We don't reschedule replenish work here -- we will
4056 * call the restock method and if it still needs
4057 * more buffers it will schedule replenish */
4058 break;
4059 }
12342c47
ZY		 4060
4061 /* If radiotap head is required, reserve some headroom here.
4062 * The physical head count is a variable rx_stats->phy_count.
4063 * We reserve 4 bytes here. Plus these extra bytes, the
4064 * headroom of the physical head should be enough for the
4065 * radiotap head that iwl3945 supported. See iwl3945_rt.
4066 */
4067 skb_reserve(rxb->skb, 4);
4068
b481de9c
ZY		 4069 priv->alloc_rxb_skb++;
4070 list_del(element);
6440adb5
CB		 4071
4072 /* Get physical address of RB/SKB */
b481de9c
ZY		 4073 rxb->dma_addr =
4074 pci_map_single(priv->pci_dev, rxb->skb->data,
4075 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4076 list_add_tail(&rxb->list, &rxq->rx_free);
4077 rxq->free_count++;
4078 }
4079 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 4080}
4081
4082/*
4083 * this should be called while priv->lock is locked
4084 */
4fd1f841 4085static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 4086{
4087 struct iwl3945_priv *priv = data;
4088
4089 iwl3945_rx_allocate(priv);
4090 iwl3945_rx_queue_restock(priv);
4091}
4092
4093
4094void iwl3945_rx_replenish(void *data)
4095{
4096 struct iwl3945_priv *priv = data;
4097 unsigned long flags;
4098
4099 iwl3945_rx_allocate(priv);
b481de9c
ZY		 4100
4101 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 4102 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4103 spin_unlock_irqrestore(&priv->lock, flags);
4104}
4105
4106/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 4107 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 4108 * This free routine walks the list of POOL entries and if SKB is set to
4109 * non NULL it is unmapped and freed
4110 */
bb8c093b 4111static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 4112{
4113 int i;
4114 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
4115 if (rxq->pool[i].skb != NULL) {
4116 pci_unmap_single(priv->pci_dev,
4117 rxq->pool[i].dma_addr,
4118 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4119 dev_kfree_skb(rxq->pool[i].skb);
4120 }
4121 }
4122
4123 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4124 rxq->dma_addr);
4125 rxq->bd = NULL;
4126}
4127
bb8c093b 4128int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 4129{
bb8c093b 4130 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 4131 struct pci_dev *dev = priv->pci_dev;
4132 int i;
4133
4134 spin_lock_init(&rxq->lock);
4135 INIT_LIST_HEAD(&rxq->rx_free);
4136 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 4137
4138 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 4139 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
4140 if (!rxq->bd)
4141 return -ENOMEM;
6440adb5 4142
b481de9c
ZY		 4143 /* Fill the rx_used queue with _all_ of the Rx buffers */
4144 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
4145 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 4146
b481de9c
ZY		 4147 /* Set us so that we have processed and used all buffers, but have
4148 * not restocked the Rx queue with fresh buffers */
4149 rxq->read = rxq->write = 0;
4150 rxq->free_count = 0;
4151 rxq->need_update = 0;
4152 return 0;
4153}
4154
bb8c093b 4155void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 4156{
4157 unsigned long flags;
4158 int i;
4159 spin_lock_irqsave(&rxq->lock, flags);
4160 INIT_LIST_HEAD(&rxq->rx_free);
4161 INIT_LIST_HEAD(&rxq->rx_used);
4162 /* Fill the rx_used queue with _all_ of the Rx buffers */
4163 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
4164 /* In the reset function, these buffers may have been allocated
4165 * to an SKB, so we need to unmap and free potential storage */
4166 if (rxq->pool[i].skb != NULL) {
4167 pci_unmap_single(priv->pci_dev,
4168 rxq->pool[i].dma_addr,
4169 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4170 priv->alloc_rxb_skb--;
4171 dev_kfree_skb(rxq->pool[i].skb);
4172 rxq->pool[i].skb = NULL;
4173 }
4174 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
4175 }
4176
4177 /* Set us so that we have processed and used all buffers, but have
4178 * not restocked the Rx queue with fresh buffers */
4179 rxq->read = rxq->write = 0;
4180 rxq->free_count = 0;
4181 spin_unlock_irqrestore(&rxq->lock, flags);
4182}
4183
4184/* Convert linear signal-to-noise ratio into dB */
4185static u8 ratio2dB[100] = {
4186/* 0 1 2 3 4 5 6 7 8 9 */
4187 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
4188 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
4189 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
4190 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
4191 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
4192 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
4193 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
4194 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
4195 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
4196 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4197};
4198
4199/* Calculates a relative dB value from a ratio of linear
4200 * (i.e. not dB) signal levels.
4201 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 4202int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 4203{
221c80cf
AB		 4204 /* 1000:1 or higher just report as 60 dB */
4205 if (sig_ratio >= 1000)
b481de9c
ZY		 4206 return 60;
4207
221c80cf 4208 /* 100:1 or higher, divide by 10 and use table,
b481de9c 4209 * add 20 dB to make up for divide by 10 */
221c80cf 4210 if (sig_ratio >= 100)
b481de9c
ZY		 4211 return (20 + (int)ratio2dB[sig_ratio/10]);
4212
4213 /* We shouldn't see this */
4214 if (sig_ratio < 1)
4215 return 0;
4216
4217 /* Use table for ratios 1:1 - 99:1 */
4218 return (int)ratio2dB[sig_ratio];
4219}
4220
4221#define PERFECT_RSSI (-20) /* dBm */
4222#define WORST_RSSI (-95) /* dBm */
4223#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
4224
4225/* Calculate an indication of rx signal quality (a percentage, not dBm!).
4226 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
4227 * about formulas used below. */
bb8c093b 4228int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 4229{
4230 int sig_qual;
4231 int degradation = PERFECT_RSSI - rssi_dbm;
4232
4233 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
4234 * as indicator; formula is (signal dbm - noise dbm).
4235 * SNR at or above 40 is a great signal (100%).
4236 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
4237 * Weakest usable signal is usually 10 - 15 dB SNR. */
4238 if (noise_dbm) {
4239 if (rssi_dbm - noise_dbm >= 40)
4240 return 100;
4241 else if (rssi_dbm < noise_dbm)
4242 return 0;
4243 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
4244
4245 /* Else use just the signal level.
4246 * This formula is a least squares fit of data points collected and
4247 * compared with a reference system that had a percentage (%) display
4248 * for signal quality. */
4249 } else
4250 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
4251 (15 * RSSI_RANGE + 62 * degradation)) /
4252 (RSSI_RANGE * RSSI_RANGE);
4253
4254 if (sig_qual > 100)
4255 sig_qual = 100;
4256 else if (sig_qual < 1)
4257 sig_qual = 0;
4258
4259 return sig_qual;
4260}
4261
4262/**
9fbab516 4263 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 4264 *
4265 * Uses the priv->rx_handlers callback function array to invoke
4266 * the appropriate handlers, including command responses,
4267 * frame-received notifications, and other notifications.
4268 */
bb8c093b 4269static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 4270{
bb8c093b
CH		 4271 struct iwl3945_rx_mem_buffer *rxb;
4272 struct iwl3945_rx_packet *pkt;
4273 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 4274 u32 r, i;
4275 int reclaim;
4276 unsigned long flags;
5c0eef96 4277 u8 fill_rx = 0;
d68ab680 4278 u32 count = 8;
b481de9c 4279
6440adb5
CB		 4280 /* uCode's read index (stored in shared DRAM) indicates the last Rx
4281 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 4282 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 4283 i = rxq->read;
4284
5c0eef96
MA		 4285 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
4286 fill_rx = 1;
b481de9c
ZY		 4287 /* Rx interrupt, but nothing sent from uCode */
4288 if (i == r)
4289 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
4290
4291 while (i != r) {
4292 rxb = rxq->queue[i];
4293
9fbab516 4294 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 4295 * then a bug has been introduced in the queue refilling
4296 * routines -- catch it here */
4297 BUG_ON(rxb == NULL);
4298
4299 rxq->queue[i] = NULL;
4300
4301 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
4302 IWL_RX_BUF_SIZE,
4303 PCI_DMA_FROMDEVICE);
bb8c093b 4304 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4305
4306 /* Reclaim a command buffer only if this packet is a response
4307 * to a (driver-originated) command.
4308 * If the packet (e.g. Rx frame) originated from uCode,
4309 * there is no command buffer to reclaim.
4310 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4311 * but apparently a few don't get set; catch them here. */
4312 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4313 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4314 (pkt->hdr.cmd != REPLY_TX);
4315
4316 /* Based on type of command response or notification,
4317 * handle those that need handling via function in
bb8c093b 4318 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 4319 if (priv->rx_handlers[pkt->hdr.cmd]) {
4320 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4321 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4322 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4323 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4324 } else {
4325 /* No handling needed */
4326 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4327 "r %d i %d No handler needed for %s, 0x%02x\n",
4328 r, i, get_cmd_string(pkt->hdr.cmd),
4329 pkt->hdr.cmd);
4330 }
4331
4332 if (reclaim) {
9fbab516
BC		 4333 /* Invoke any callbacks, transfer the skb to caller, and
4334 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 4335 * as we reclaim the driver command queue */
4336 if (rxb && rxb->skb)
bb8c093b 4337 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4338 else
4339 IWL_WARNING("Claim null rxb?\n");
4340 }
4341
4342 /* For now we just don't re-use anything. We can tweak this
4343 * later to try and re-use notification packets and SKBs that
4344 * fail to Rx correctly */
4345 if (rxb->skb != NULL) {
4346 priv->alloc_rxb_skb--;
4347 dev_kfree_skb_any(rxb->skb);
4348 rxb->skb = NULL;
4349 }
4350
4351 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4352 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4353 spin_lock_irqsave(&rxq->lock, flags);
4354 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4355 spin_unlock_irqrestore(&rxq->lock, flags);
4356 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 4357 /* If there are a lot of unused frames,
4358 * restock the Rx queue so ucode won't assert. */
4359 if (fill_rx) {
4360 count++;
4361 if (count >= 8) {
4362 priv->rxq.read = i;
4363 __iwl3945_rx_replenish(priv);
4364 count = 0;
4365 }
4366 }
b481de9c
ZY		 4367 }
4368
4369 /* Backtrack one entry */
4370 priv->rxq.read = i;
bb8c093b 4371 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4372}
4373
6440adb5
CB		 4374/**
4375 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4376 */
bb8c093b
CH		 4377static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4378 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 4379{
4380 u32 reg = 0;
4381 int rc = 0;
4382 int txq_id = txq->q.id;
4383
4384 if (txq->need_update == 0)
4385 return rc;
4386
4387 /* if we're trying to save power */
4388 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4389 /* wake up nic if it's powered down ...
4390 * uCode will wake up, and interrupt us again, so next
4391 * time we'll skip this part. */
bb8c093b 4392 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4393
4394 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4395 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4396 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4397 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4398 return rc;
4399 }
4400
4401 /* restore this queue's parameters in nic hardware. */
bb8c093b 4402 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4403 if (rc)
4404 return rc;
bb8c093b 4405 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4406 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4407 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4408
4409 /* else not in power-save mode, uCode will never sleep when we're
4410 * trying to tx (during RFKILL, we're not trying to tx). */
4411 } else
bb8c093b 4412 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4413 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4414
4415 txq->need_update = 0;
4416
4417 return rc;
4418}
4419
c8b0e6e1 4420#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4421static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4422{
0795af57
JP		 4423 DECLARE_MAC_BUF(mac);
4424
b481de9c 4425 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4426 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4427 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4428 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4429 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4430 le32_to_cpu(rxon->filter_flags));
4431 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4432 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4433 rxon->ofdm_basic_rates);
4434 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4435 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4436 print_mac(mac, rxon->node_addr));
4437 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4438 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4439 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4440}
4441#endif
4442
bb8c093b 4443static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4444{
4445 IWL_DEBUG_ISR("Enabling interrupts\n");
4446 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4447 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4448}
4449
bb8c093b 4450static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4451{
4452 clear_bit(STATUS_INT_ENABLED, &priv->status);
4453
4454 /* disable interrupts from uCode/NIC to host */
bb8c093b 4455 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4456
4457 /* acknowledge/clear/reset any interrupts still pending
4458 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4459 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4460 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4461 IWL_DEBUG_ISR("Disabled interrupts\n");
4462}
4463
4464static const char *desc_lookup(int i)
4465{
4466 switch (i) {
4467 case 1:
4468 return "FAIL";
4469 case 2:
4470 return "BAD_PARAM";
4471 case 3:
4472 return "BAD_CHECKSUM";
4473 case 4:
4474 return "NMI_INTERRUPT";
4475 case 5:
4476 return "SYSASSERT";
4477 case 6:
4478 return "FATAL_ERROR";
4479 }
4480
4481 return "UNKNOWN";
4482}
4483
4484#define ERROR_START_OFFSET (1 * sizeof(u32))
4485#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4486
bb8c093b 4487static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4488{
4489 u32 i;
4490 u32 desc, time, count, base, data1;
4491 u32 blink1, blink2, ilink1, ilink2;
4492 int rc;
4493
4494 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4495
bb8c093b 4496 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4497 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4498 return;
4499 }
4500
bb8c093b 4501 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4502 if (rc) {
4503 IWL_WARNING("Can not read from adapter at this time.\n");
4504 return;
4505 }
4506
bb8c093b 4507 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4508
4509 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4510 IWL_ERROR("Start IWL Error Log Dump:\n");
4511 IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
4512 priv->status, priv->config, count);
4513 }
4514
4515 IWL_ERROR("Desc Time asrtPC blink2 "
4516 "ilink1 nmiPC Line\n");
4517 for (i = ERROR_START_OFFSET;
4518 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4519 i += ERROR_ELEM_SIZE) {
bb8c093b 4520 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4521 time =
bb8c093b 4522 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4523 blink1 =
bb8c093b 4524 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4525 blink2 =
bb8c093b 4526 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4527 ilink1 =
bb8c093b 4528 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4529 ilink2 =
bb8c093b 4530 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4531 data1 =
bb8c093b 4532 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4533
4534 IWL_ERROR
4535 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4536 desc_lookup(desc), desc, time, blink1, blink2,
4537 ilink1, ilink2, data1);
4538 }
4539
bb8c093b 4540 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4541
4542}
4543
f58177b9 4544#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4545
4546/**
bb8c093b 4547 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4548 *
bb8c093b 4549 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4550 */
bb8c093b 4551static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4552 u32 num_events, u32 mode)
4553{
4554 u32 i;
4555 u32 base; /* SRAM byte address of event log header */
4556 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4557 u32 ptr; /* SRAM byte address of log data */
4558 u32 ev, time, data; /* event log data */
4559
4560 if (num_events == 0)
4561 return;
4562
4563 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4564
4565 if (mode == 0)
4566 event_size = 2 * sizeof(u32);
4567 else
4568 event_size = 3 * sizeof(u32);
4569
4570 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4571
4572 /* "time" is actually "data" for mode 0 (no timestamp).
4573 * place event id # at far right for easier visual parsing. */
4574 for (i = 0; i < num_events; i++) {
bb8c093b 4575 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4576 ptr += sizeof(u32);
bb8c093b 4577 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4578 ptr += sizeof(u32);
4579 if (mode == 0)
4580 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4581 else {
bb8c093b 4582 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4583 ptr += sizeof(u32);
4584 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4585 }
4586 }
4587}
4588
bb8c093b 4589static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4590{
4591 int rc;
4592 u32 base; /* SRAM byte address of event log header */
4593 u32 capacity; /* event log capacity in # entries */
4594 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4595 u32 num_wraps; /* # times uCode wrapped to top of log */
4596 u32 next_entry; /* index of next entry to be written by uCode */
4597 u32 size; /* # entries that we'll print */
4598
4599 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4600 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4601 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4602 return;
4603 }
4604
bb8c093b 4605 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4606 if (rc) {
4607 IWL_WARNING("Can not read from adapter at this time.\n");
4608 return;
4609 }
4610
4611 /* event log header */
bb8c093b
CH		 4612 capacity = iwl3945_read_targ_mem(priv, base);
4613 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4614 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4615 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4616
4617 size = num_wraps ? capacity : next_entry;
4618
4619 /* bail out if nothing in log */
4620 if (size == 0) {
583fab37 4621 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4622 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4623 return;
4624 }
4625
583fab37 4626 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4627 size, num_wraps);
4628
4629 /* if uCode has wrapped back to top of log, start at the oldest entry,
4630 * i.e the next one that uCode would fill. */
4631 if (num_wraps)
bb8c093b 4632 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4633 capacity - next_entry, mode);
4634
4635 /* (then/else) start at top of log */
bb8c093b 4636 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4637
bb8c093b 4638 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4639}
4640
4641/**
bb8c093b 4642 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4643 */
bb8c093b 4644static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4645{
bb8c093b 4646 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4647 set_bit(STATUS_FW_ERROR, &priv->status);
4648
4649 /* Cancel currently queued command. */
4650 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4651
c8b0e6e1 4652#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4653 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4654 iwl3945_dump_nic_error_log(priv);
4655 iwl3945_dump_nic_event_log(priv);
4656 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4657 }
4658#endif
4659
4660 wake_up_interruptible(&priv->wait_command_queue);
4661
4662 /* Keep the restart process from trying to send host
4663 * commands by clearing the INIT status bit */
4664 clear_bit(STATUS_READY, &priv->status);
4665
4666 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4667 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4668 "Restarting adapter due to uCode error.\n");
4669
bb8c093b 4670 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4671 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4672 sizeof(priv->recovery_rxon));
4673 priv->error_recovering = 1;
4674 }
4675 queue_work(priv->workqueue, &priv->restart);
4676 }
4677}
4678
bb8c093b 4679static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4680{
4681 unsigned long flags;
4682
4683 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4684 sizeof(priv->staging_rxon));
4685 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4686 iwl3945_commit_rxon(priv);
b481de9c 4687
bb8c093b 4688 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4689
4690 spin_lock_irqsave(&priv->lock, flags);
4691 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4692 priv->error_recovering = 0;
4693 spin_unlock_irqrestore(&priv->lock, flags);
4694}
4695
bb8c093b 4696static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4697{
4698 u32 inta, handled = 0;
4699 u32 inta_fh;
4700 unsigned long flags;
c8b0e6e1 4701#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4702 u32 inta_mask;
4703#endif
4704
4705 spin_lock_irqsave(&priv->lock, flags);
4706
4707 /* Ack/clear/reset pending uCode interrupts.
4708 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4709 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4710 inta = iwl3945_read32(priv, CSR_INT);
4711 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4712
4713 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4714 * Any new interrupts that happen after this, either while we're
4715 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4716 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4717 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4718
c8b0e6e1 4719#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4720 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4721 /* just for debug */
4722 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4723 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4724 inta, inta_mask, inta_fh);
4725 }
4726#endif
4727
4728 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4729 * atomic, make sure that inta covers all the interrupts that
4730 * we've discovered, even if FH interrupt came in just after
4731 * reading CSR_INT. */
4732 if (inta_fh & CSR_FH_INT_RX_MASK)
4733 inta |= CSR_INT_BIT_FH_RX;
4734 if (inta_fh & CSR_FH_INT_TX_MASK)
4735 inta |= CSR_INT_BIT_FH_TX;
4736
4737 /* Now service all interrupt bits discovered above. */
4738 if (inta & CSR_INT_BIT_HW_ERR) {
4739 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4740
4741 /* Tell the device to stop sending interrupts */
bb8c093b 4742 iwl3945_disable_interrupts(priv);
b481de9c 4743
bb8c093b 4744 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4745
4746 handled |= CSR_INT_BIT_HW_ERR;
4747
4748 spin_unlock_irqrestore(&priv->lock, flags);
4749
4750 return;
4751 }
4752
c8b0e6e1 4753#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4754 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4755 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4756 if (inta & CSR_INT_BIT_SCD)
4757 IWL_DEBUG_ISR("Scheduler finished to transmit "
4758 "the frame/frames.\n");
b481de9c
ZY		 4759
4760 /* Alive notification via Rx interrupt will do the real work */
4761 if (inta & CSR_INT_BIT_ALIVE)
4762 IWL_DEBUG_ISR("Alive interrupt\n");
4763 }
4764#endif
4765 /* Safely ignore these bits for debug checks below */
25c03d8e 4766 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4767
4768 /* HW RF KILL switch toggled (4965 only) */
4769 if (inta & CSR_INT_BIT_RF_KILL) {
4770 int hw_rf_kill = 0;
bb8c093b 4771 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4772 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4773 hw_rf_kill = 1;
4774
4775 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4776 "RF_KILL bit toggled to %s.\n",
4777 hw_rf_kill ? "disable radio":"enable radio");
4778
4779 /* Queue restart only if RF_KILL switch was set to "kill"
4780 * when we loaded driver, and is now set to "enable".
4781 * After we're Alive, RF_KILL gets handled by
4782 * iwl_rx_card_state_notif() */
53e49093
ZY		 4783 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4784 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4785 queue_work(priv->workqueue, &priv->restart);
53e49093 4786 }
b481de9c
ZY		 4787
4788 handled |= CSR_INT_BIT_RF_KILL;
4789 }
4790
4791 /* Chip got too hot and stopped itself (4965 only) */
4792 if (inta & CSR_INT_BIT_CT_KILL) {
4793 IWL_ERROR("Microcode CT kill error detected.\n");
4794 handled |= CSR_INT_BIT_CT_KILL;
4795 }
4796
4797 /* Error detected by uCode */
4798 if (inta & CSR_INT_BIT_SW_ERR) {
4799 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4800 inta);
bb8c093b 4801 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4802 handled |= CSR_INT_BIT_SW_ERR;
4803 }
4804
4805 /* uCode wakes up after power-down sleep */
4806 if (inta & CSR_INT_BIT_WAKEUP) {
4807 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4808 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4809 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4810 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4811 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4812 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4813 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4814 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4815
4816 handled |= CSR_INT_BIT_WAKEUP;
4817 }
4818
4819 /* All uCode command responses, including Tx command responses,
4820 * Rx "responses" (frame-received notification), and other
4821 * notifications from uCode come through here*/
4822 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4823 iwl3945_rx_handle(priv);
b481de9c
ZY		 4824 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4825 }
4826
4827 if (inta & CSR_INT_BIT_FH_TX) {
4828 IWL_DEBUG_ISR("Tx interrupt\n");
4829
bb8c093b
CH		 4830 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4831 if (!iwl3945_grab_nic_access(priv)) {
4832 iwl3945_write_direct32(priv,
b481de9c
ZY		 4833 FH_TCSR_CREDIT
4834 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4835 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4836 }
4837 handled |= CSR_INT_BIT_FH_TX;
4838 }
4839
4840 if (inta & ~handled)
4841 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4842
4843 if (inta & ~CSR_INI_SET_MASK) {
4844 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4845 inta & ~CSR_INI_SET_MASK);
4846 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4847 }
4848
4849 /* Re-enable all interrupts */
bb8c093b 4850 iwl3945_enable_interrupts(priv);
b481de9c 4851
c8b0e6e1 4852#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4853 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4854 inta = iwl3945_read32(priv, CSR_INT);
4855 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4856 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4857 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4858 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4859 }
4860#endif
4861 spin_unlock_irqrestore(&priv->lock, flags);
4862}
4863
bb8c093b 4864static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4865{
bb8c093b 4866 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4867 u32 inta, inta_mask;
4868 u32 inta_fh;
4869 if (!priv)
4870 return IRQ_NONE;
4871
4872 spin_lock(&priv->lock);
4873
4874 /* Disable (but don't clear!) interrupts here to avoid
4875 * back-to-back ISRs and sporadic interrupts from our NIC.
4876 * If we have something to service, the tasklet will re-enable ints.
4877 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4878 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4879 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4880
4881 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4882 inta = iwl3945_read32(priv, CSR_INT);
4883 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4884
4885 /* Ignore interrupt if there's nothing in NIC to service.
4886 * This may be due to IRQ shared with another device,
4887 * or due to sporadic interrupts thrown from our NIC. */
4888 if (!inta && !inta_fh) {
4889 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4890 goto none;
4891 }
4892
4893 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4894 /* Hardware disappeared */
4895 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4896 goto unplugged;
b481de9c
ZY		 4897 }
4898
4899 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4900 inta, inta_mask, inta_fh);
4901
25c03d8e
JP		 4902 inta &= ~CSR_INT_BIT_SCD;
4903
bb8c093b 4904 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4905 if (likely(inta || inta_fh))
4906 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4907unplugged:
b481de9c
ZY		 4908 spin_unlock(&priv->lock);
4909
4910 return IRQ_HANDLED;
4911
4912 none:
4913 /* re-enable interrupts here since we don't have anything to service. */
bb8c093b 4914 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4915 spin_unlock(&priv->lock);
4916 return IRQ_NONE;
4917}
4918
4919/************************** EEPROM BANDS ****************************
4920 *
bb8c093b 4921 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4922 * EEPROM contents to the specific channel number supported for each
4923 * band.
4924 *
bb8c093b 4925 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4926 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4927 * The specific geography and calibration information for that channel
4928 * is contained in the eeprom map itself.
4929 *
4930 * During init, we copy the eeprom information and channel map
4931 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4932 *
4933 * channel_map_24/52 provides the index in the channel_info array for a
4934 * given channel. We have to have two separate maps as there is channel
4935 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4936 * band_2
4937 *
4938 * A value of 0xff stored in the channel_map indicates that the channel
4939 * is not supported by the hardware at all.
4940 *
4941 * A value of 0xfe in the channel_map indicates that the channel is not
4942 * valid for Tx with the current hardware. This means that
4943 * while the system can tune and receive on a given channel, it may not
4944 * be able to associate or transmit any frames on that
4945 * channel. There is no corresponding channel information for that
4946 * entry.
4947 *
4948 *********************************************************************/
4949
4950/* 2.4 GHz */
bb8c093b 4951static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4952 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4953};
4954
4955/* 5.2 GHz bands */
9fbab516 4956static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4957 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4958};
4959
9fbab516 4960static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4961 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4962};
4963
bb8c093b 4964static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4965 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4966};
4967
bb8c093b 4968static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4969 145, 149, 153, 157, 161, 165
4970};
4971
bb8c093b 4972static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4973 int *eeprom_ch_count,
bb8c093b 4974 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4975 **eeprom_ch_info,
4976 const u8 **eeprom_ch_index)
4977{
4978 switch (band) {
4979 case 1: /* 2.4GHz band */
bb8c093b 4980 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4981 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4982 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4983 break;
9fbab516 4984 case 2: /* 4.9GHz band */
bb8c093b 4985 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4986 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4987 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4988 break;
4989 case 3: /* 5.2GHz band */
bb8c093b 4990 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4991 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4992 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4993 break;
9fbab516 4994 case 4: /* 5.5GHz band */
bb8c093b 4995 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4996 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4997 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4998 break;
9fbab516 4999 case 5: /* 5.7GHz band */
bb8c093b 5000 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 5001 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 5002 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 5003 break;
5004 default:
5005 BUG();
5006 return;
5007 }
5008}
5009
6440adb5
CB		 5010/**
5011 * iwl3945_get_channel_info - Find driver's private channel info
5012 *
5013 * Based on band and channel number.
5014 */
bb8c093b 5015const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 5016 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 5017{
5018 int i;
5019
8318d78a
JB		 5020 switch (band) {
5021 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 5022 for (i = 14; i < priv->channel_count; i++) {
5023 if (priv->channel_info[i].channel == channel)
5024 return &priv->channel_info[i];
5025 }
5026 break;
5027
8318d78a 5028 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 5029 if (channel >= 1 && channel <= 14)
5030 return &priv->channel_info[channel - 1];
5031 break;
8318d78a
JB		 5032 case IEEE80211_NUM_BANDS:
5033 WARN_ON(1);
b481de9c
ZY		 5034 }
5035
5036 return NULL;
5037}
5038
5039#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
5040 ? # x " " : "")
5041
6440adb5
CB		 5042/**
5043 * iwl3945_init_channel_map - Set up driver's info for all possible channels
5044 */
bb8c093b 5045static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 5046{
5047 int eeprom_ch_count = 0;
5048 const u8 *eeprom_ch_index = NULL;
bb8c093b 5049 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 5050 int band, ch;
bb8c093b 5051 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 5052
5053 if (priv->channel_count) {
5054 IWL_DEBUG_INFO("Channel map already initialized.\n");
5055 return 0;
5056 }
5057
5058 if (priv->eeprom.version < 0x2f) {
5059 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
5060 priv->eeprom.version);
5061 return -EINVAL;
5062 }
5063
5064 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
5065
5066 priv->channel_count =
bb8c093b
CH		 5067 ARRAY_SIZE(iwl3945_eeprom_band_1) +
5068 ARRAY_SIZE(iwl3945_eeprom_band_2) +
5069 ARRAY_SIZE(iwl3945_eeprom_band_3) +
5070 ARRAY_SIZE(iwl3945_eeprom_band_4) +
5071 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 5072
5073 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
5074
bb8c093b 5075 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 5076 priv->channel_count, GFP_KERNEL);
5077 if (!priv->channel_info) {
5078 IWL_ERROR("Could not allocate channel_info\n");
5079 priv->channel_count = 0;
5080 return -ENOMEM;
5081 }
5082
5083 ch_info = priv->channel_info;
5084
5085 /* Loop through the 5 EEPROM bands adding them in order to the
5086 * channel map we maintain (that contains additional information than
5087 * what just in the EEPROM) */
5088 for (band = 1; band <= 5; band++) {
5089
bb8c093b 5090 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 5091 &eeprom_ch_info, &eeprom_ch_index);
5092
5093 /* Loop through each band adding each of the channels */
5094 for (ch = 0; ch < eeprom_ch_count; ch++) {
5095 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 5096 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
5097 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 5098
5099 /* permanently store EEPROM's channel regulatory flags
5100 * and max power in channel info database. */
5101 ch_info->eeprom = eeprom_ch_info[ch];
5102
5103 /* Copy the run-time flags so they are there even on
5104 * invalid channels */
5105 ch_info->flags = eeprom_ch_info[ch].flags;
5106
5107 if (!(is_channel_valid(ch_info))) {
5108 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
5109 "No traffic\n",
5110 ch_info->channel,
5111 ch_info->flags,
5112 is_channel_a_band(ch_info) ?
5113 "5.2" : "2.4");
5114 ch_info++;
5115 continue;
5116 }
5117
5118 /* Initialize regulatory-based run-time data */
5119 ch_info->max_power_avg = ch_info->curr_txpow =
5120 eeprom_ch_info[ch].max_power_avg;
5121 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
5122 ch_info->min_power = 0;
5123
5124 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
5125 " %ddBm): Ad-Hoc %ssupported\n",
5126 ch_info->channel,
5127 is_channel_a_band(ch_info) ?
5128 "5.2" : "2.4",
5129 CHECK_AND_PRINT(IBSS),
5130 CHECK_AND_PRINT(ACTIVE),
5131 CHECK_AND_PRINT(RADAR),
5132 CHECK_AND_PRINT(WIDE),
5133 CHECK_AND_PRINT(NARROW),
5134 CHECK_AND_PRINT(DFS),
5135 eeprom_ch_info[ch].flags,
5136 eeprom_ch_info[ch].max_power_avg,
5137 ((eeprom_ch_info[ch].
5138 flags & EEPROM_CHANNEL_IBSS)
5139 && !(eeprom_ch_info[ch].
5140 flags & EEPROM_CHANNEL_RADAR))
5141 ? "" : "not ");
5142
5143 /* Set the user_txpower_limit to the highest power
5144 * supported by any channel */
5145 if (eeprom_ch_info[ch].max_power_avg >
5146 priv->user_txpower_limit)
5147 priv->user_txpower_limit =
5148 eeprom_ch_info[ch].max_power_avg;
5149
5150 ch_info++;
5151 }
5152 }
5153
6440adb5 5154 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 5155 if (iwl3945_txpower_set_from_eeprom(priv))
5156 return -EIO;
5157
5158 return 0;
5159}
5160
849e0dce
RC		 5161/*
5162 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
5163 */
5164static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
5165{
5166 kfree(priv->channel_info);
5167 priv->channel_count = 0;
5168}
5169
b481de9c
ZY		 5170/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
5171 * sending probe req. This should be set long enough to hear probe responses
5172 * from more than one AP. */
5173#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
5174#define IWL_ACTIVE_DWELL_TIME_52 (10)
5175
5176/* For faster active scanning, scan will move to the next channel if fewer than
5177 * PLCP_QUIET_THRESH packets are heard on this channel within
5178 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
5179 * time if it's a quiet channel (nothing responded to our probe, and there's
5180 * no other traffic).
5181 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
5182#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
5183#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
5184
5185/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
5186 * Must be set longer than active dwell time.
5187 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
5188#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
5189#define IWL_PASSIVE_DWELL_TIME_52 (10)
5190#define IWL_PASSIVE_DWELL_BASE (100)
5191#define IWL_CHANNEL_TUNE_TIME 5
5192
8318d78a
JB		 5193static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
5194 enum ieee80211_band band)
b481de9c 5195{
8318d78a 5196 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 5197 return IWL_ACTIVE_DWELL_TIME_52;
5198 else
5199 return IWL_ACTIVE_DWELL_TIME_24;
5200}
5201
8318d78a
JB		 5202static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
5203 enum ieee80211_band band)
b481de9c 5204{
8318d78a
JB		 5205 u16 active = iwl3945_get_active_dwell_time(priv, band);
5206 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 5207 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
5208 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
5209
bb8c093b 5210 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 5211 /* If we're associated, we clamp the maximum passive
5212 * dwell time to be 98% of the beacon interval (minus
5213 * 2 * channel tune time) */
5214 passive = priv->beacon_int;
5215 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
5216 passive = IWL_PASSIVE_DWELL_BASE;
5217 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
5218 }
5219
5220 if (passive <= active)
5221 passive = active + 1;
5222
5223 return passive;
5224}
5225
8318d78a
JB		 5226static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
5227 enum ieee80211_band band,
b481de9c 5228 u8 is_active, u8 direct_mask,
bb8c093b 5229 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 5230{
5231 const struct ieee80211_channel *channels = NULL;
8318d78a 5232 const struct ieee80211_supported_band *sband;
bb8c093b 5233 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 5234 u16 passive_dwell = 0;
5235 u16 active_dwell = 0;
5236 int added, i;
5237
8318d78a
JB		 5238 sband = iwl3945_get_band(priv, band);
5239 if (!sband)
b481de9c
ZY		 5240 return 0;
5241
8318d78a 5242 channels = sband->channels;
b481de9c 5243
8318d78a
JB		 5244 active_dwell = iwl3945_get_active_dwell_time(priv, band);
5245 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 5246
8318d78a
JB		 5247 for (i = 0, added = 0; i < sband->n_channels; i++) {
5248 if (channels[i].hw_value ==
b481de9c 5249 le16_to_cpu(priv->active_rxon.channel)) {
bb8c093b 5250 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 5251 IWL_DEBUG_SCAN
5252 ("Skipping current channel %d\n",
5253 le16_to_cpu(priv->active_rxon.channel));
5254 continue;
5255 }
5256 } else if (priv->only_active_channel)
5257 continue;
5258
8318d78a 5259 scan_ch->channel = channels[i].hw_value;
b481de9c 5260
8318d78a 5261 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c
ZY		 5262 if (!is_channel_valid(ch_info)) {
5263 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
5264 scan_ch->channel);
5265 continue;
5266 }
5267
5268 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 5269 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 5270 scan_ch->type = 0; /* passive */
5271 else
5272 scan_ch->type = 1; /* active */
5273
5274 if (scan_ch->type & 1)
5275 scan_ch->type |= (direct_mask << 1);
5276
5277 if (is_channel_narrow(ch_info))
5278 scan_ch->type |= (1 << 7);
5279
5280 scan_ch->active_dwell = cpu_to_le16(active_dwell);
5281 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
5282
9fbab516 5283 /* Set txpower levels to defaults */
b481de9c
ZY		 5284 scan_ch->tpc.dsp_atten = 110;
5285 /* scan_pwr_info->tpc.dsp_atten; */
5286
5287 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 5288 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 5289 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
5290 else {
5291 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
5292 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 5293 * power level:
8a1b0245 5294 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 5295 */
5296 }
5297
5298 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5299 scan_ch->channel,
5300 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5301 (scan_ch->type & 1) ?
5302 active_dwell : passive_dwell);
5303
5304 scan_ch++;
5305 added++;
5306 }
5307
5308 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5309 return added;
5310}
5311
bb8c093b 5312static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 5313 struct ieee80211_rate *rates)
5314{
5315 int i;
5316
5317 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 5318 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
5319 rates[i].hw_value = i; /* Rate scaling will work on indexes */
5320 rates[i].hw_value_short = i;
5321 rates[i].flags = 0;
5322 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 5323 /*
8318d78a 5324 * If CCK != 1M then set short preamble rate flag.
b481de9c 5325 */
bb8c093b 5326 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 5327 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 5328 }
b481de9c
ZY		 5329 }
5330}
5331
5332/**
bb8c093b 5333 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5334 */
bb8c093b 5335static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5336{
bb8c093b 5337 struct iwl3945_channel_info *ch;
8318d78a 5338 struct ieee80211_supported_band *band;
b481de9c
ZY		 5339 struct ieee80211_channel *channels;
5340 struct ieee80211_channel *geo_ch;
5341 struct ieee80211_rate *rates;
5342 int i = 0;
b481de9c 5343
8318d78a
JB		 5344 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
5345 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 5346 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5347 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5348 return 0;
5349 }
5350
b481de9c
ZY		 5351 channels = kzalloc(sizeof(struct ieee80211_channel) *
5352 priv->channel_count, GFP_KERNEL);
8318d78a 5353 if (!channels)
b481de9c 5354 return -ENOMEM;
b481de9c
ZY		 5355
5356 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
5357 GFP_KERNEL);
5358 if (!rates) {
b481de9c
ZY		 5359 kfree(channels);
5360 return -ENOMEM;
5361 }
5362
b481de9c 5363 /* 5.2GHz channels start after the 2.4GHz channels */
8318d78a
JB		 5364 band = &priv->bands[IEEE80211_BAND_5GHZ];
5365 band->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
5366 band->bitrates = &rates[4];
5367 band->n_bitrates = 8; /* just OFDM */
5368
5369 band = &priv->bands[IEEE80211_BAND_2GHZ];
5370 band->channels = channels;
5371 band->bitrates = rates;
5372 band->n_bitrates = 12; /* OFDM & CCK */
b481de9c
ZY		 5373
5374 priv->ieee_channels = channels;
5375 priv->ieee_rates = rates;
5376
bb8c093b 5377 iwl3945_init_hw_rates(priv, rates);
b481de9c
ZY		 5378
5379 for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
5380 ch = &priv->channel_info[i];
5381
5382 if (!is_channel_valid(ch)) {
5383 IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
5384 "skipping.\n",
5385 ch->channel, is_channel_a_band(ch) ?
5386 "5.2" : "2.4");
5387 continue;
5388 }
5389
5390 if (is_channel_a_band(ch))
8318d78a
JB		 5391 geo_ch = &priv->bands[IEEE80211_BAND_5GHZ].channels[priv->bands[IEEE80211_BAND_5GHZ].n_channels++];
5392 else
5393 geo_ch = &priv->bands[IEEE80211_BAND_2GHZ].channels[priv->bands[IEEE80211_BAND_2GHZ].n_channels++];
b481de9c 5394
8318d78a
JB		 5395 geo_ch->center_freq = ieee80211chan2mhz(ch->channel);
5396 geo_ch->max_power = ch->max_power_avg;
5397 geo_ch->max_antenna_gain = 0xff;
7b72304d 5398 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 5399
5400 if (is_channel_valid(ch)) {
8318d78a
JB		 5401 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5402 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5403
8318d78a
JB		 5404 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5405 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 5406
5407 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5408 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 5409
5410 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5411 priv->max_channel_txpower_limit =
5412 ch->max_power_avg;
8318d78a
JB		 5413 } else
5414 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
b481de9c
ZY		 5415 }
5416
8318d78a 5417 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && priv->is_abg) {
b481de9c
ZY		 5418 printk(KERN_INFO DRV_NAME
5419 ": Incorrectly detected BG card as ABG. Please send "
5420 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5421 priv->pci_dev->device, priv->pci_dev->subsystem_device);
5422 priv->is_abg = 0;
5423 }
5424
5425 printk(KERN_INFO DRV_NAME
5426 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5427 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5428 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5429
8318d78a
JB		 5430 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->bands[IEEE80211_BAND_2GHZ];
5431 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5432
b481de9c
ZY		 5433 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5434
5435 return 0;
5436}
5437
849e0dce
RC		 5438/*
5439 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5440 */
5441static void iwl3945_free_geos(struct iwl3945_priv *priv)
5442{
849e0dce
RC		 5443 kfree(priv->ieee_channels);
5444 kfree(priv->ieee_rates);
5445 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5446}
5447
b481de9c
ZY		 5448/******************************************************************************
5449 *
5450 * uCode download functions
5451 *
5452 ******************************************************************************/
5453
bb8c093b 5454static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5455{
98c92211
TW		 5456 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5457 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5458 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5459 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5460 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5461 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5462}
5463
5464/**
bb8c093b 5465 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5466 * looking at all data.
5467 */
bb8c093b 5468static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY		 5469{
5470 u32 val;
5471 u32 save_len = len;
5472 int rc = 0;
5473 u32 errcnt;
5474
5475 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5476
bb8c093b 5477 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5478 if (rc)
5479 return rc;
5480
bb8c093b 5481 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5482
5483 errcnt = 0;
5484 for (; len > 0; len -= sizeof(u32), image++) {
5485 /* read data comes through single port, auto-incr addr */
5486 /* NOTE: Use the debugless read so we don't flood kernel log
5487 * if IWL_DL_IO is set */
bb8c093b 5488 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5489 if (val != le32_to_cpu(*image)) {
5490 IWL_ERROR("uCode INST section is invalid at "
5491 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5492 save_len - len, val, le32_to_cpu(*image));
5493 rc = -EIO;
5494 errcnt++;
5495 if (errcnt >= 20)
5496 break;
5497 }
5498 }
5499
bb8c093b 5500 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5501
5502 if (!errcnt)
bc434dd2 5503 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5504
5505 return rc;
5506}
5507
5508
5509/**
bb8c093b 5510 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5511 * using sample data 100 bytes apart. If these sample points are good,
5512 * it's a pretty good bet that everything between them is good, too.
5513 */
bb8c093b 5514static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5515{
5516 u32 val;
5517 int rc = 0;
5518 u32 errcnt = 0;
5519 u32 i;
5520
5521 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5522
bb8c093b 5523 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5524 if (rc)
5525 return rc;
5526
5527 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5528 /* read data comes through single port, auto-incr addr */
5529 /* NOTE: Use the debugless read so we don't flood kernel log
5530 * if IWL_DL_IO is set */
bb8c093b 5531 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5532 i + RTC_INST_LOWER_BOUND);
bb8c093b 5533 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5534 if (val != le32_to_cpu(*image)) {
5535#if 0 /* Enable this if you want to see details */
5536 IWL_ERROR("uCode INST section is invalid at "
5537 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5538 i, val, *image);
5539#endif
5540 rc = -EIO;
5541 errcnt++;
5542 if (errcnt >= 3)
5543 break;
5544 }
5545 }
5546
bb8c093b 5547 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5548
5549 return rc;
5550}
5551
5552
5553/**
bb8c093b 5554 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5555 * and verify its contents
5556 */
bb8c093b 5557static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5558{
5559 __le32 *image;
5560 u32 len;
5561 int rc = 0;
5562
5563 /* Try bootstrap */
5564 image = (__le32 *)priv->ucode_boot.v_addr;
5565 len = priv->ucode_boot.len;
bb8c093b 5566 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5567 if (rc == 0) {
5568 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5569 return 0;
5570 }
5571
5572 /* Try initialize */
5573 image = (__le32 *)priv->ucode_init.v_addr;
5574 len = priv->ucode_init.len;
bb8c093b 5575 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5576 if (rc == 0) {
5577 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5578 return 0;
5579 }
5580
5581 /* Try runtime/protocol */
5582 image = (__le32 *)priv->ucode_code.v_addr;
5583 len = priv->ucode_code.len;
bb8c093b 5584 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5585 if (rc == 0) {
5586 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5587 return 0;
5588 }
5589
5590 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5591
9fbab516
BC		 5592 /* Since nothing seems to match, show first several data entries in
5593 * instruction SRAM, so maybe visual inspection will give a clue.
5594 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5595 image = (__le32 *)priv->ucode_boot.v_addr;
5596 len = priv->ucode_boot.len;
bb8c093b 5597 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5598
5599 return rc;
5600}
5601
5602
5603/* check contents of special bootstrap uCode SRAM */
bb8c093b 5604static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5605{
5606 __le32 *image = priv->ucode_boot.v_addr;
5607 u32 len = priv->ucode_boot.len;
5608 u32 reg;
5609 u32 val;
5610
5611 IWL_DEBUG_INFO("Begin verify bsm\n");
5612
5613 /* verify BSM SRAM contents */
bb8c093b 5614 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5615 for (reg = BSM_SRAM_LOWER_BOUND;
5616 reg < BSM_SRAM_LOWER_BOUND + len;
5617 reg += sizeof(u32), image ++) {
bb8c093b 5618 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5619 if (val != le32_to_cpu(*image)) {
5620 IWL_ERROR("BSM uCode verification failed at "
5621 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5622 BSM_SRAM_LOWER_BOUND,
5623 reg - BSM_SRAM_LOWER_BOUND, len,
5624 val, le32_to_cpu(*image));
5625 return -EIO;
5626 }
5627 }
5628
5629 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5630
5631 return 0;
5632}
5633
5634/**
bb8c093b 5635 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5636 *
5637 * BSM operation:
5638 *
5639 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5640 * in special SRAM that does not power down during RFKILL. When powering back
5641 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5642 * the bootstrap program into the on-board processor, and starts it.
5643 *
5644 * The bootstrap program loads (via DMA) instructions and data for a new
5645 * program from host DRAM locations indicated by the host driver in the
5646 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5647 * automatically.
5648 *
5649 * When initializing the NIC, the host driver points the BSM to the
5650 * "initialize" uCode image. This uCode sets up some internal data, then
5651 * notifies host via "initialize alive" that it is complete.
5652 *
5653 * The host then replaces the BSM_DRAM_* pointer values to point to the
5654 * normal runtime uCode instructions and a backup uCode data cache buffer
5655 * (filled initially with starting data values for the on-board processor),
5656 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5657 * which begins normal operation.
5658 *
5659 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5660 * the backup data cache in DRAM before SRAM is powered down.
5661 *
5662 * When powering back up, the BSM loads the bootstrap program. This reloads
5663 * the runtime uCode instructions and the backup data cache into SRAM,
5664 * and re-launches the runtime uCode from where it left off.
5665 */
bb8c093b 5666static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5667{
5668 __le32 *image = priv->ucode_boot.v_addr;
5669 u32 len = priv->ucode_boot.len;
5670 dma_addr_t pinst;
5671 dma_addr_t pdata;
5672 u32 inst_len;
5673 u32 data_len;
5674 int rc;
5675 int i;
5676 u32 done;
5677 u32 reg_offset;
5678
5679 IWL_DEBUG_INFO("Begin load bsm\n");
5680
5681 /* make sure bootstrap program is no larger than BSM's SRAM size */
5682 if (len > IWL_MAX_BSM_SIZE)
5683 return -EINVAL;
5684
5685 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5686 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5687 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5688 * after the "initialize" uCode has run, to point to
5689 * runtime/protocol instructions and backup data cache. */
5690 pinst = priv->ucode_init.p_addr;
5691 pdata = priv->ucode_init_data.p_addr;
5692 inst_len = priv->ucode_init.len;
5693 data_len = priv->ucode_init_data.len;
5694
bb8c093b 5695 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5696 if (rc)
5697 return rc;
5698
bb8c093b
CH		 5699 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5700 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5701 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5702 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5703
5704 /* Fill BSM memory with bootstrap instructions */
5705 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5706 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5707 reg_offset += sizeof(u32), image++)
bb8c093b 5708 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5709 le32_to_cpu(*image));
5710
bb8c093b 5711 rc = iwl3945_verify_bsm(priv);
b481de9c 5712 if (rc) {
bb8c093b 5713 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5714 return rc;
5715 }
5716
5717 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5718 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5719 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5720 RTC_INST_LOWER_BOUND);
bb8c093b 5721 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5722
5723 /* Load bootstrap code into instruction SRAM now,
5724 * to prepare to load "initialize" uCode */
bb8c093b 5725 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5726 BSM_WR_CTRL_REG_BIT_START);
5727
5728 /* Wait for load of bootstrap uCode to finish */
5729 for (i = 0; i < 100; i++) {
bb8c093b 5730 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5731 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5732 break;
5733 udelay(10);
5734 }
5735 if (i < 100)
5736 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5737 else {
5738 IWL_ERROR("BSM write did not complete!\n");
5739 return -EIO;
5740 }
5741
5742 /* Enable future boot loads whenever power management unit triggers it
5743 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5744 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5745 BSM_WR_CTRL_REG_BIT_START_EN);
5746
bb8c093b 5747 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5748
5749 return 0;
5750}
5751
bb8c093b 5752static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5753{
5754 /* Remove all resets to allow NIC to operate */
bb8c093b 5755 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5756}
5757
5758/**
bb8c093b 5759 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5760 *
5761 * Copy into buffers for card to fetch via bus-mastering
5762 */
bb8c093b 5763static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5764{
bb8c093b 5765 struct iwl3945_ucode *ucode;
90e759d1 5766 int ret = 0;
b481de9c
ZY		 5767 const struct firmware *ucode_raw;
5768 /* firmware file name contains uCode/driver compatibility version */
5769 const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
5770 u8 *src;
5771 size_t len;
5772 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5773
5774 /* Ask kernel firmware_class module to get the boot firmware off disk.
5775 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5776 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5777 if (ret < 0) {
5778 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5779 name, ret);
b481de9c
ZY		 5780 goto error;
5781 }
5782
5783 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5784 name, ucode_raw->size);
5785
5786 /* Make sure that we got at least our header! */
5787 if (ucode_raw->size < sizeof(*ucode)) {
5788 IWL_ERROR("File size way too small!\n");
90e759d1 5789 ret = -EINVAL;
b481de9c
ZY		 5790 goto err_release;
5791 }
5792
5793 /* Data from ucode file: header followed by uCode images */
5794 ucode = (void *)ucode_raw->data;
5795
5796 ver = le32_to_cpu(ucode->ver);
5797 inst_size = le32_to_cpu(ucode->inst_size);
5798 data_size = le32_to_cpu(ucode->data_size);
5799 init_size = le32_to_cpu(ucode->init_size);
5800 init_data_size = le32_to_cpu(ucode->init_data_size);
5801 boot_size = le32_to_cpu(ucode->boot_size);
5802
5803 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5804 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5805 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5806 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5807 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5808 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5809
5810 /* Verify size of file vs. image size info in file's header */
5811 if (ucode_raw->size < sizeof(*ucode) +
5812 inst_size + data_size + init_size +
5813 init_data_size + boot_size) {
5814
5815 IWL_DEBUG_INFO("uCode file size %d too small\n",
5816 (int)ucode_raw->size);
90e759d1 5817 ret = -EINVAL;
b481de9c
ZY		 5818 goto err_release;
5819 }
5820
5821 /* Verify that uCode images will fit in card's SRAM */
5822 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5823 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5824 inst_size);
5825 ret = -EINVAL;
b481de9c
ZY		 5826 goto err_release;
5827 }
5828
5829 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5830 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5831 data_size);
5832 ret = -EINVAL;
b481de9c
ZY		 5833 goto err_release;
5834 }
5835 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5836 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5837 init_size);
5838 ret = -EINVAL;
b481de9c
ZY		 5839 goto err_release;
5840 }
5841 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5842 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5843 init_data_size);
5844 ret = -EINVAL;
b481de9c
ZY		 5845 goto err_release;
5846 }
5847 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5848 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5849 boot_size);
5850 ret = -EINVAL;
b481de9c
ZY		 5851 goto err_release;
5852 }
5853
5854 /* Allocate ucode buffers for card's bus-master loading ... */
5855
5856 /* Runtime instructions and 2 copies of data:
5857 * 1) unmodified from disk
5858 * 2) backup cache for save/restore during power-downs */
5859 priv->ucode_code.len = inst_size;
98c92211 5860 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5861
5862 priv->ucode_data.len = data_size;
98c92211 5863 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5864
5865 priv->ucode_data_backup.len = data_size;
98c92211 5866 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5867
90e759d1
TW		 5868 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5869 !priv->ucode_data_backup.v_addr)
5870 goto err_pci_alloc;
b481de9c
ZY		 5871
5872 /* Initialization instructions and data */
90e759d1
TW		 5873 if (init_size && init_data_size) {
5874 priv->ucode_init.len = init_size;
98c92211 5875 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5876
5877 priv->ucode_init_data.len = init_data_size;
98c92211 5878 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5879
5880 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5881 goto err_pci_alloc;
5882 }
b481de9c
ZY		 5883
5884 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5885 if (boot_size) {
5886 priv->ucode_boot.len = boot_size;
98c92211 5887 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5888
90e759d1
TW		 5889 if (!priv->ucode_boot.v_addr)
5890 goto err_pci_alloc;
5891 }
b481de9c
ZY		 5892
5893 /* Copy images into buffers for card's bus-master reads ... */
5894
5895 /* Runtime instructions (first block of data in file) */
5896 src = &ucode->data[0];
5897 len = priv->ucode_code.len;
90e759d1 5898 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5899 memcpy(priv->ucode_code.v_addr, src, len);
5900 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5901 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5902
5903 /* Runtime data (2nd block)
bb8c093b 5904 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5905 src = &ucode->data[inst_size];
5906 len = priv->ucode_data.len;
90e759d1 5907 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5908 memcpy(priv->ucode_data.v_addr, src, len);
5909 memcpy(priv->ucode_data_backup.v_addr, src, len);
5910
5911 /* Initialization instructions (3rd block) */
5912 if (init_size) {
5913 src = &ucode->data[inst_size + data_size];
5914 len = priv->ucode_init.len;
90e759d1
TW		 5915 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5916 len);
b481de9c
ZY		 5917 memcpy(priv->ucode_init.v_addr, src, len);
5918 }
5919
5920 /* Initialization data (4th block) */
5921 if (init_data_size) {
5922 src = &ucode->data[inst_size + data_size + init_size];
5923 len = priv->ucode_init_data.len;
5924 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5925 (int)len);
5926 memcpy(priv->ucode_init_data.v_addr, src, len);
5927 }
5928
5929 /* Bootstrap instructions (5th block) */
5930 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5931 len = priv->ucode_boot.len;
5932 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5933 (int)len);
5934 memcpy(priv->ucode_boot.v_addr, src, len);
5935
5936 /* We have our copies now, allow OS release its copies */
5937 release_firmware(ucode_raw);
5938 return 0;
5939
5940 err_pci_alloc:
5941 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5942 ret = -ENOMEM;
bb8c093b 5943 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5944
5945 err_release:
5946 release_firmware(ucode_raw);
5947
5948 error:
90e759d1 5949 return ret;
b481de9c
ZY		 5950}
5951
5952
5953/**
bb8c093b 5954 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5955 *
5956 * Tell initialization uCode where to find runtime uCode.
5957 *
5958 * BSM registers initially contain pointers to initialization uCode.
5959 * We need to replace them to load runtime uCode inst and data,
5960 * and to save runtime data when powering down.
5961 */
bb8c093b 5962static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5963{
5964 dma_addr_t pinst;
5965 dma_addr_t pdata;
5966 int rc = 0;
5967 unsigned long flags;
5968
5969 /* bits 31:0 for 3945 */
5970 pinst = priv->ucode_code.p_addr;
5971 pdata = priv->ucode_data_backup.p_addr;
5972
5973 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5974 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5975 if (rc) {
5976 spin_unlock_irqrestore(&priv->lock, flags);
5977 return rc;
5978 }
5979
5980 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5981 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5982 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5983 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5984 priv->ucode_data.len);
5985
5986 /* Inst bytecount must be last to set up, bit 31 signals uCode
5987 * that all new ptr/size info is in place */
bb8c093b 5988 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5989 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5990
bb8c093b 5991 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5992
5993 spin_unlock_irqrestore(&priv->lock, flags);
5994
5995 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5996
5997 return rc;
5998}
5999
6000/**
bb8c093b 6001 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 6002 *
6003 * Called after REPLY_ALIVE notification received from "initialize" uCode.
6004 *
b481de9c 6005 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 6006 */
bb8c093b 6007static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 6008{
6009 /* Check alive response for "valid" sign from uCode */
6010 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
6011 /* We had an error bringing up the hardware, so take it
6012 * all the way back down so we can try again */
6013 IWL_DEBUG_INFO("Initialize Alive failed.\n");
6014 goto restart;
6015 }
6016
6017 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
6018 * This is a paranoid check, because we would not have gotten the
6019 * "initialize" alive if code weren't properly loaded. */
bb8c093b 6020 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 6021 /* Runtime instruction load was bad;
6022 * take it all the way back down so we can try again */
6023 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
6024 goto restart;
6025 }
6026
6027 /* Send pointers to protocol/runtime uCode image ... init code will
6028 * load and launch runtime uCode, which will send us another "Alive"
6029 * notification. */
6030 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 6031 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 6032 /* Runtime instruction load won't happen;
6033 * take it all the way back down so we can try again */
6034 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
6035 goto restart;
6036 }
6037 return;
6038
6039 restart:
6040 queue_work(priv->workqueue, &priv->restart);
6041}
6042
6043
6044/**
bb8c093b 6045 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 6046 * from protocol/runtime uCode (initialization uCode's
bb8c093b 6047 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 6048 */
bb8c093b 6049static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 6050{
6051 int rc = 0;
6052 int thermal_spin = 0;
6053 u32 rfkill;
6054
6055 IWL_DEBUG_INFO("Runtime Alive received.\n");
6056
6057 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
6058 /* We had an error bringing up the hardware, so take it
6059 * all the way back down so we can try again */
6060 IWL_DEBUG_INFO("Alive failed.\n");
6061 goto restart;
6062 }
6063
6064 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
6065 * This is a paranoid check, because we would not have gotten the
6066 * "runtime" alive if code weren't properly loaded. */
bb8c093b 6067 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 6068 /* Runtime instruction load was bad;
6069 * take it all the way back down so we can try again */
6070 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
6071 goto restart;
6072 }
6073
bb8c093b 6074 iwl3945_clear_stations_table(priv);
b481de9c 6075
bb8c093b 6076 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 6077 if (rc) {
6078 IWL_WARNING("Can not read rfkill status from adapter\n");
6079 return;
6080 }
6081
bb8c093b 6082 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 6083 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 6084 iwl3945_release_nic_access(priv);
b481de9c
ZY		 6085
6086 if (rfkill & 0x1) {
6087 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6088 /* if rfkill is not on, then wait for thermal
6089 * sensor in adapter to kick in */
bb8c093b 6090 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 6091 thermal_spin++;
6092 udelay(10);
6093 }
6094
6095 if (thermal_spin)
6096 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
6097 thermal_spin * 10);
6098 } else
6099 set_bit(STATUS_RF_KILL_HW, &priv->status);
6100
9fbab516 6101 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 6102 set_bit(STATUS_ALIVE, &priv->status);
6103
6104 /* Clear out the uCode error bit if it is set */
6105 clear_bit(STATUS_FW_ERROR, &priv->status);
6106
bb8c093b 6107 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 6108 return;
6109
5a66926a 6110 ieee80211_start_queues(priv->hw);
b481de9c
ZY		 6111
6112 priv->active_rate = priv->rates_mask;
6113 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
6114
bb8c093b 6115 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 6116
bb8c093b
CH		 6117 if (iwl3945_is_associated(priv)) {
6118 struct iwl3945_rxon_cmd *active_rxon =
6119 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 6120
6121 memcpy(&priv->staging_rxon, &priv->active_rxon,
6122 sizeof(priv->staging_rxon));
6123 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6124 } else {
6125 /* Initialize our rx_config data */
bb8c093b 6126 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 6127 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
6128 }
6129
9fbab516 6130 /* Configure Bluetooth device coexistence support */
bb8c093b 6131 iwl3945_send_bt_config(priv);
b481de9c
ZY		 6132
6133 /* Configure the adapter for unassociated operation */
bb8c093b 6134 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6135
6136 /* At this point, the NIC is initialized and operational */
6137 priv->notif_missed_beacons = 0;
6138 set_bit(STATUS_READY, &priv->status);
6139
6140 iwl3945_reg_txpower_periodic(priv);
6141
6142 IWL_DEBUG_INFO("ALIVE processing complete.\n");
5a66926a 6143 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 6144
6145 if (priv->error_recovering)
bb8c093b 6146 iwl3945_error_recovery(priv);
b481de9c
ZY		 6147
6148 return;
6149
6150 restart:
6151 queue_work(priv->workqueue, &priv->restart);
6152}
6153
bb8c093b 6154static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 6155
bb8c093b 6156static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 6157{
6158 unsigned long flags;
6159 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
6160 struct ieee80211_conf *conf = NULL;
6161
6162 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
6163
6164 conf = ieee80211_get_hw_conf(priv->hw);
6165
6166 if (!exit_pending)
6167 set_bit(STATUS_EXIT_PENDING, &priv->status);
6168
bb8c093b 6169 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6170
6171 /* Unblock any waiting calls */
6172 wake_up_interruptible_all(&priv->wait_command_queue);
6173
b481de9c
ZY		 6174 /* Wipe out the EXIT_PENDING status bit if we are not actually
6175 * exiting the module */
6176 if (!exit_pending)
6177 clear_bit(STATUS_EXIT_PENDING, &priv->status);
6178
6179 /* stop and reset the on-board processor */
bb8c093b 6180 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 6181
6182 /* tell the device to stop sending interrupts */
bb8c093b 6183 iwl3945_disable_interrupts(priv);
b481de9c
ZY		 6184
6185 if (priv->mac80211_registered)
6186 ieee80211_stop_queues(priv->hw);
6187
bb8c093b 6188 /* If we have not previously called iwl3945_init() then
b481de9c 6189 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 6190 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 6191 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6192 STATUS_RF_KILL_HW |
6193 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6194 STATUS_RF_KILL_SW |
9788864e
RC		 6195 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
6196 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 6197 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6198 STATUS_IN_SUSPEND;
6199 goto exit;
6200 }
6201
6202 /* ...otherwise clear out all the status bits but the RF Kill and
6203 * SUSPEND bits and continue taking the NIC down. */
6204 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6205 STATUS_RF_KILL_HW |
6206 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6207 STATUS_RF_KILL_SW |
9788864e
RC		 6208 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
6209 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 6210 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6211 STATUS_IN_SUSPEND |
6212 test_bit(STATUS_FW_ERROR, &priv->status) <<
6213 STATUS_FW_ERROR;
6214
6215 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 6216 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 6217 spin_unlock_irqrestore(&priv->lock, flags);
6218
bb8c093b
CH		 6219 iwl3945_hw_txq_ctx_stop(priv);
6220 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 6221
6222 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 6223 if (!iwl3945_grab_nic_access(priv)) {
6224 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 6225 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 6226 iwl3945_release_nic_access(priv);
b481de9c
ZY		 6227 }
6228 spin_unlock_irqrestore(&priv->lock, flags);
6229
6230 udelay(5);
6231
bb8c093b
CH		 6232 iwl3945_hw_nic_stop_master(priv);
6233 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
6234 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 6235
6236 exit:
bb8c093b 6237 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 6238
6239 if (priv->ibss_beacon)
6240 dev_kfree_skb(priv->ibss_beacon);
6241 priv->ibss_beacon = NULL;
6242
6243 /* clear out any free frames */
bb8c093b 6244 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 6245}
6246
bb8c093b 6247static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 6248{
6249 mutex_lock(&priv->mutex);
bb8c093b 6250 __iwl3945_down(priv);
b481de9c 6251 mutex_unlock(&priv->mutex);
b24d22b1 6252
bb8c093b 6253 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 6254}
6255
6256#define MAX_HW_RESTARTS 5
6257
bb8c093b 6258static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 6259{
6260 int rc, i;
6261
6262 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6263 IWL_WARNING("Exit pending; will not bring the NIC up\n");
6264 return -EIO;
6265 }
6266
6267 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
6268 IWL_WARNING("Radio disabled by SW RF kill (module "
6269 "parameter)\n");
e655b9f0
ZY		 6270 return -ENODEV;
6271 }
6272
e903fbd4
RC		 6273 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6274 IWL_ERROR("ucode not available for device bringup\n");
6275 return -EIO;
6276 }
6277
e655b9f0
ZY		 6278 /* If platform's RF_KILL switch is NOT set to KILL */
6279 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
6280 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6281 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6282 else {
6283 set_bit(STATUS_RF_KILL_HW, &priv->status);
6284 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6285 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6286 return -ENODEV;
6287 }
b481de9c
ZY		 6288 }
6289
bb8c093b 6290 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6291
bb8c093b 6292 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 6293 if (rc) {
6294 IWL_ERROR("Unable to int nic\n");
6295 return rc;
6296 }
6297
6298 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6299 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6300 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 6301 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6302
6303 /* clear (again), then enable host interrupts */
bb8c093b
CH		 6304 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6305 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 6306
6307 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6308 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6309 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 6310
6311 /* Copy original ucode data image from disk into backup cache.
6312 * This will be used to initialize the on-board processor's
6313 * data SRAM for a clean start when the runtime program first loads. */
6314 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6315 priv->ucode_data.len);
b481de9c 6316
e655b9f0
ZY		 6317 /* We return success when we resume from suspend and rf_kill is on. */
6318 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
6319 return 0;
6320
b481de9c
ZY		 6321 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6322
bb8c093b 6323 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6324
6325 /* load bootstrap state machine,
6326 * load bootstrap program into processor's memory,
6327 * prepare to load the "initialize" uCode */
bb8c093b 6328 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 6329
6330 if (rc) {
6331 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6332 continue;
6333 }
6334
6335 /* start card; "initialize" will load runtime ucode */
bb8c093b 6336 iwl3945_nic_start(priv);
b481de9c 6337
b481de9c
ZY		 6338 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6339
6340 return 0;
6341 }
6342
6343 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6344 __iwl3945_down(priv);
b481de9c
ZY		 6345
6346 /* tried to restart and config the device for as long as our
6347 * patience could withstand */
6348 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6349 return -EIO;
6350}
6351
6352
6353/*****************************************************************************
6354 *
6355 * Workqueue callbacks
6356 *
6357 *****************************************************************************/
6358
bb8c093b 6359static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6360{
bb8c093b
CH		 6361 struct iwl3945_priv *priv =
6362 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 6363
6364 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6365 return;
6366
6367 mutex_lock(&priv->mutex);
bb8c093b 6368 iwl3945_init_alive_start(priv);
b481de9c
ZY		 6369 mutex_unlock(&priv->mutex);
6370}
6371
bb8c093b 6372static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6373{
bb8c093b
CH		 6374 struct iwl3945_priv *priv =
6375 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 6376
6377 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6378 return;
6379
6380 mutex_lock(&priv->mutex);
bb8c093b 6381 iwl3945_alive_start(priv);
b481de9c
ZY		 6382 mutex_unlock(&priv->mutex);
6383}
6384
bb8c093b 6385static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6386{
bb8c093b 6387 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6388
6389 wake_up_interruptible(&priv->wait_command_queue);
6390
6391 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6392 return;
6393
6394 mutex_lock(&priv->mutex);
6395
bb8c093b 6396 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6397 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6398 "HW and/or SW RF Kill no longer active, restarting "
6399 "device\n");
6400 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6401 queue_work(priv->workqueue, &priv->restart);
6402 } else {
6403
6404 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6405 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6406 "disabled by SW switch\n");
6407 else
6408 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6409 "Kill switch must be turned off for "
6410 "wireless networking to work.\n");
6411 }
6412 mutex_unlock(&priv->mutex);
6413}
6414
6415#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6416
bb8c093b 6417static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6418{
bb8c093b
CH		 6419 struct iwl3945_priv *priv =
6420 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6421
6422 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6423 return;
6424
6425 mutex_lock(&priv->mutex);
6426 if (test_bit(STATUS_SCANNING, &priv->status) ||
6427 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6428 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6429 "Scan completion watchdog resetting adapter (%dms)\n",
6430 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6431
b481de9c 6432 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6433 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6434 }
6435 mutex_unlock(&priv->mutex);
6436}
6437
bb8c093b 6438static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6439{
bb8c093b
CH		 6440 struct iwl3945_priv *priv =
6441 container_of(data, struct iwl3945_priv, request_scan);
6442 struct iwl3945_host_cmd cmd = {
b481de9c 6443 .id = REPLY_SCAN_CMD,
bb8c093b 6444 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6445 .meta.flags = CMD_SIZE_HUGE,
6446 };
6447 int rc = 0;
bb8c093b 6448 struct iwl3945_scan_cmd *scan;
b481de9c
ZY		 6449 struct ieee80211_conf *conf = NULL;
6450 u8 direct_mask;
8318d78a 6451 enum ieee80211_band band;
b481de9c
ZY		 6452
6453 conf = ieee80211_get_hw_conf(priv->hw);
6454
6455 mutex_lock(&priv->mutex);
6456
bb8c093b 6457 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6458 IWL_WARNING("request scan called when driver not ready.\n");
6459 goto done;
6460 }
6461
6462 /* Make sure the scan wasn't cancelled before this queued work
6463 * was given the chance to run... */
6464 if (!test_bit(STATUS_SCANNING, &priv->status))
6465 goto done;
6466
6467 /* This should never be called or scheduled if there is currently
6468 * a scan active in the hardware. */
6469 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6470 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6471 "Ignoring second request.\n");
6472 rc = -EIO;
6473 goto done;
6474 }
6475
6476 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6477 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6478 goto done;
6479 }
6480
6481 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6482 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6483 goto done;
6484 }
6485
bb8c093b 6486 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6487 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6488 goto done;
6489 }
6490
6491 if (!test_bit(STATUS_READY, &priv->status)) {
6492 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6493 goto done;
6494 }
6495
6496 if (!priv->scan_bands) {
6497 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6498 goto done;
6499 }
6500
6501 if (!priv->scan) {
bb8c093b 6502 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6503 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6504 if (!priv->scan) {
6505 rc = -ENOMEM;
6506 goto done;
6507 }
6508 }
6509 scan = priv->scan;
bb8c093b 6510 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6511
6512 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6513 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6514
bb8c093b 6515 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6516 u16 interval = 0;
6517 u32 extra;
6518 u32 suspend_time = 100;
6519 u32 scan_suspend_time = 100;
6520 unsigned long flags;
6521
6522 IWL_DEBUG_INFO("Scanning while associated...\n");
6523
6524 spin_lock_irqsave(&priv->lock, flags);
6525 interval = priv->beacon_int;
6526 spin_unlock_irqrestore(&priv->lock, flags);
6527
6528 scan->suspend_time = 0;
15e869d8 6529 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6530 if (!interval)
6531 interval = suspend_time;
6532 /*
6533 * suspend time format:
6534 * 0-19: beacon interval in usec (time before exec.)
6535 * 20-23: 0
6536 * 24-31: number of beacons (suspend between channels)
6537 */
6538
6539 extra = (suspend_time / interval) << 24;
6540 scan_suspend_time = 0xFF0FFFFF &
6541 (extra | ((suspend_time % interval) * 1024));
6542
6543 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6544 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6545 scan_suspend_time, interval);
6546 }
6547
6548 /* We should add the ability for user to lock to PASSIVE ONLY */
6549 if (priv->one_direct_scan) {
6550 IWL_DEBUG_SCAN
6551 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6552 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6553 priv->direct_ssid_len));
6554 scan->direct_scan[0].id = WLAN_EID_SSID;
6555 scan->direct_scan[0].len = priv->direct_ssid_len;
6556 memcpy(scan->direct_scan[0].ssid,
6557 priv->direct_ssid, priv->direct_ssid_len);
6558 direct_mask = 1;
bb8c093b 6559 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
b481de9c
ZY		 6560 scan->direct_scan[0].id = WLAN_EID_SSID;
6561 scan->direct_scan[0].len = priv->essid_len;
6562 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6563 direct_mask = 1;
6564 } else
6565 direct_mask = 0;
6566
6567 /* We don't build a direct scan probe request; the uCode will do
6568 * that based on the direct_mask added to each channel entry */
6569 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6570 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6571 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6572 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6573 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6574 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6575
6576 /* flags + rate selection */
6577
6578 switch (priv->scan_bands) {
6579 case 2:
6580 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6581 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6582 scan->good_CRC_th = 0;
8318d78a 6583 band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 6584 break;
6585
6586 case 1:
6587 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6588 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6589 band = IEEE80211_BAND_5GHZ;
b481de9c
ZY		 6590 break;
6591
6592 default:
6593 IWL_WARNING("Invalid scan band count\n");
6594 goto done;
6595 }
6596
6597 /* select Rx antennas */
6598 scan->flags |= iwl3945_get_antenna_flags(priv);
6599
6600 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6601 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6602
6603 if (direct_mask)
6604 IWL_DEBUG_SCAN
6605 ("Initiating direct scan for %s.\n",
bb8c093b 6606 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 6607 else
6608 IWL_DEBUG_SCAN("Initiating indirect scan.\n");
6609
6610 scan->channel_count =
bb8c093b 6611 iwl3945_get_channels_for_scan(
8318d78a 6612 priv, band, 1, /* active */
b481de9c
ZY		 6613 direct_mask,
6614 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6615
6616 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6617 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6618 cmd.data = scan;
6619 scan->len = cpu_to_le16(cmd.len);
6620
6621 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6622 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6623 if (rc)
6624 goto done;
6625
6626 queue_delayed_work(priv->workqueue, &priv->scan_check,
6627 IWL_SCAN_CHECK_WATCHDOG);
6628
6629 mutex_unlock(&priv->mutex);
6630 return;
6631
6632 done:
01ebd063 6633 /* inform mac80211 scan aborted */
b481de9c
ZY		 6634 queue_work(priv->workqueue, &priv->scan_completed);
6635 mutex_unlock(&priv->mutex);
6636}
6637
bb8c093b 6638static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6639{
bb8c093b 6640 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6641
6642 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6643 return;
6644
6645 mutex_lock(&priv->mutex);
bb8c093b 6646 __iwl3945_up(priv);
b481de9c
ZY		 6647 mutex_unlock(&priv->mutex);
6648}
6649
bb8c093b 6650static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6651{
bb8c093b 6652 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6653
6654 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6655 return;
6656
bb8c093b 6657 iwl3945_down(priv);
b481de9c
ZY		 6658 queue_work(priv->workqueue, &priv->up);
6659}
6660
bb8c093b 6661static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6662{
bb8c093b
CH		 6663 struct iwl3945_priv *priv =
6664 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6665
6666 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6667 return;
6668
6669 mutex_lock(&priv->mutex);
bb8c093b 6670 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6671 mutex_unlock(&priv->mutex);
6672}
6673
7878a5a4
MA		 6674#define IWL_DELAY_NEXT_SCAN (HZ*2)
6675
bb8c093b 6676static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6677{
bb8c093b 6678 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY		 6679 post_associate.work);
6680
6681 int rc = 0;
6682 struct ieee80211_conf *conf = NULL;
0795af57 6683 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6684
6685 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6686 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6687 return;
6688 }
6689
6690
0795af57
JP		 6691 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6692 priv->assoc_id,
6693 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 6694
6695 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6696 return;
6697
6698 mutex_lock(&priv->mutex);
6699
32bfd35d 6700 if (!priv->vif || !priv->is_open) {
6ef89d0a
MA		 6701 mutex_unlock(&priv->mutex);
6702 return;
6703 }
bb8c093b 6704 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6705
b481de9c
ZY		 6706 conf = ieee80211_get_hw_conf(priv->hw);
6707
6708 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6709 iwl3945_commit_rxon(priv);
b481de9c 6710
bb8c093b
CH		 6711 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6712 iwl3945_setup_rxon_timing(priv);
6713 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6714 sizeof(priv->rxon_timing), &priv->rxon_timing);
6715 if (rc)
6716 IWL_WARNING("REPLY_RXON_TIMING failed - "
6717 "Attempting to continue.\n");
6718
6719 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6720
6721 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6722
6723 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6724 priv->assoc_id, priv->beacon_int);
6725
6726 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6727 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6728 else
6729 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6730
6731 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6732 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6733 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6734 else
6735 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6736
6737 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6738 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6739
6740 }
6741
bb8c093b 6742 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6743
6744 switch (priv->iw_mode) {
6745 case IEEE80211_IF_TYPE_STA:
bb8c093b 6746 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6747 break;
6748
6749 case IEEE80211_IF_TYPE_IBSS:
6750
6751 /* clear out the station table */
bb8c093b 6752 iwl3945_clear_stations_table(priv);
b481de9c 6753
bb8c093b
CH		 6754 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6755 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6756 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6757 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6758 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6759 CMD_ASYNC);
bb8c093b
CH		 6760 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6761 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6762
6763 break;
6764
6765 default:
6766 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6767 __FUNCTION__, priv->iw_mode);
b481de9c
ZY		 6768 break;
6769 }
6770
bb8c093b 6771 iwl3945_sequence_reset(priv);
b481de9c 6772
c8b0e6e1 6773#ifdef CONFIG_IWL3945_QOS
bb8c093b 6774 iwl3945_activate_qos(priv, 0);
c8b0e6e1 6775#endif /* CONFIG_IWL3945_QOS */
7878a5a4
MA		 6776 /* we have just associated, don't start scan too early */
6777 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 6778 mutex_unlock(&priv->mutex);
6779}
6780
bb8c093b 6781static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6782{
bb8c093b 6783 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6784
bb8c093b 6785 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6786 return;
6787
6788 mutex_lock(&priv->mutex);
6789
6790 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6791 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6792
6793 mutex_unlock(&priv->mutex);
6794}
6795
76bb77e0
ZY		 6796static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6797
bb8c093b 6798static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6799{
bb8c093b
CH		 6800 struct iwl3945_priv *priv =
6801 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6802
6803 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6804
6805 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6806 return;
6807
a0646470
ZY		 6808 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6809 iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6810
b481de9c
ZY		 6811 ieee80211_scan_completed(priv->hw);
6812
6813 /* Since setting the TXPOWER may have been deferred while
6814 * performing the scan, fire one off */
6815 mutex_lock(&priv->mutex);
bb8c093b 6816 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6817 mutex_unlock(&priv->mutex);
6818}
6819
6820/*****************************************************************************
6821 *
6822 * mac80211 entry point functions
6823 *
6824 *****************************************************************************/
6825
5a66926a
ZY		 6826#define UCODE_READY_TIMEOUT (2 * HZ)
6827
bb8c093b 6828static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6829{
bb8c093b 6830 struct iwl3945_priv *priv = hw->priv;
5a66926a 6831 int ret;
b481de9c
ZY		 6832
6833 IWL_DEBUG_MAC80211("enter\n");
6834
5a66926a
ZY		 6835 if (pci_enable_device(priv->pci_dev)) {
6836 IWL_ERROR("Fail to pci_enable_device\n");
6837 return -ENODEV;
6838 }
6839 pci_restore_state(priv->pci_dev);
6840 pci_enable_msi(priv->pci_dev);
6841
6842 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6843 DRV_NAME, priv);
6844 if (ret) {
6845 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6846 goto out_disable_msi;
6847 }
6848
b481de9c
ZY		 6849 /* we should be verifying the device is ready to be opened */
6850 mutex_lock(&priv->mutex);
6851
5a66926a
ZY		 6852 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6853 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6854 * ucode filename and max sizes are card-specific. */
6855
6856 if (!priv->ucode_code.len) {
6857 ret = iwl3945_read_ucode(priv);
6858 if (ret) {
6859 IWL_ERROR("Could not read microcode: %d\n", ret);
6860 mutex_unlock(&priv->mutex);
6861 goto out_release_irq;
6862 }
6863 }
b481de9c 6864
e655b9f0 6865 ret = __iwl3945_up(priv);
b481de9c
ZY		 6866
6867 mutex_unlock(&priv->mutex);
5a66926a 6868
e655b9f0
ZY		 6869 if (ret)
6870 goto out_release_irq;
6871
6872 IWL_DEBUG_INFO("Start UP work.\n");
6873
6874 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6875 return 0;
6876
5a66926a
ZY		 6877 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6878 * mac80211 will not be run successfully. */
6879 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6880 test_bit(STATUS_READY, &priv->status),
6881 UCODE_READY_TIMEOUT);
6882 if (!ret) {
6883 if (!test_bit(STATUS_READY, &priv->status)) {
6884 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6885 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6886 ret = -ETIMEDOUT;
6887 goto out_release_irq;
6888 }
6889 }
6890
e655b9f0 6891 priv->is_open = 1;
b481de9c
ZY		 6892 IWL_DEBUG_MAC80211("leave\n");
6893 return 0;
5a66926a
ZY		 6894
6895out_release_irq:
6896 free_irq(priv->pci_dev->irq, priv);
6897out_disable_msi:
6898 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6899 pci_disable_device(priv->pci_dev);
6900 priv->is_open = 0;
6901 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6902 return ret;
b481de9c
ZY		 6903}
6904
bb8c093b 6905static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6906{
bb8c093b 6907 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6908
6909 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6910
e655b9f0
ZY		 6911 if (!priv->is_open) {
6912 IWL_DEBUG_MAC80211("leave - skip\n");
6913 return;
6914 }
6915
b481de9c 6916 priv->is_open = 0;
5a66926a
ZY		 6917
6918 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6919 /* stop mac, cancel any scan request and clear
6920 * RXON_FILTER_ASSOC_MSK BIT
6921 */
5a66926a
ZY		 6922 mutex_lock(&priv->mutex);
6923 iwl3945_scan_cancel_timeout(priv, 100);
6924 cancel_delayed_work(&priv->post_associate);
fde3571f 6925 mutex_unlock(&priv->mutex);
fde3571f
MA		 6926 }
6927
5a66926a
ZY		 6928 iwl3945_down(priv);
6929
6930 flush_workqueue(priv->workqueue);
6931 free_irq(priv->pci_dev->irq, priv);
6932 pci_disable_msi(priv->pci_dev);
6933 pci_save_state(priv->pci_dev);
6934 pci_disable_device(priv->pci_dev);
6ef89d0a 6935
b481de9c 6936 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6937}
6938
bb8c093b 6939static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 6940 struct ieee80211_tx_control *ctl)
6941{
bb8c093b 6942 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6943
6944 IWL_DEBUG_MAC80211("enter\n");
6945
6946 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
6947 IWL_DEBUG_MAC80211("leave - monitor\n");
6948 return -1;
6949 }
6950
6951 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
8318d78a 6952 ctl->tx_rate->bitrate);
b481de9c 6953
bb8c093b 6954 if (iwl3945_tx_skb(priv, skb, ctl))
b481de9c
ZY		 6955 dev_kfree_skb_any(skb);
6956
6957 IWL_DEBUG_MAC80211("leave\n");
6958 return 0;
6959}
6960
bb8c093b 6961static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6962 struct ieee80211_if_init_conf *conf)
6963{
bb8c093b 6964 struct iwl3945_priv *priv = hw->priv;
b481de9c 6965 unsigned long flags;
0795af57 6966 DECLARE_MAC_BUF(mac);
b481de9c 6967
32bfd35d 6968 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6969
32bfd35d
JB		 6970 if (priv->vif) {
6971 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6972 return -EOPNOTSUPP;
b481de9c
ZY		 6973 }
6974
6975 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6976 priv->vif = conf->vif;
b481de9c
ZY		 6977
6978 spin_unlock_irqrestore(&priv->lock, flags);
6979
6980 mutex_lock(&priv->mutex);
864792e3
TW		 6981
6982 if (conf->mac_addr) {
6983 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
6984 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6985 }
6986
5a66926a
ZY		 6987 if (iwl3945_is_ready(priv))
6988 iwl3945_set_mode(priv, conf->type);
b481de9c 6989
b481de9c
ZY		 6990 mutex_unlock(&priv->mutex);
6991
5a66926a 6992 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6993 return 0;
6994}
6995
6996/**
bb8c093b 6997 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6998 *
6999 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
7000 * be set inappropriately and the driver currently sets the hardware up to
7001 * use it whenever needed.
7002 */
bb8c093b 7003static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 7004{
bb8c093b
CH		 7005 struct iwl3945_priv *priv = hw->priv;
7006 const struct iwl3945_channel_info *ch_info;
b481de9c 7007 unsigned long flags;
76bb77e0 7008 int ret = 0;
b481de9c
ZY		 7009
7010 mutex_lock(&priv->mutex);
8318d78a 7011 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 7012
12342c47
ZY		 7013 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
7014
bb8c093b 7015 if (!iwl3945_is_ready(priv)) {
b481de9c 7016 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 7017 ret = -EIO;
7018 goto out;
b481de9c
ZY		 7019 }
7020
bb8c093b 7021 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 7022 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 7023 IWL_DEBUG_MAC80211("leave - scanning\n");
7024 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 7025 mutex_unlock(&priv->mutex);
a0646470 7026 return 0;
b481de9c
ZY		 7027 }
7028
7029 spin_lock_irqsave(&priv->lock, flags);
7030
8318d78a
JB		 7031 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
7032 conf->channel->hw_value);
b481de9c
ZY		 7033 if (!is_channel_valid(ch_info)) {
7034 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
8318d78a 7035 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 7036 IWL_DEBUG_MAC80211("leave - invalid channel\n");
7037 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 7038 ret = -EINVAL;
7039 goto out;
b481de9c
ZY		 7040 }
7041
8318d78a 7042 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 7043
8318d78a 7044 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 7045
7046 /* The list of supported rates and rate mask can be different
7047 * for each phymode; since the phymode may have changed, reset
7048 * the rate mask to what mac80211 lists */
bb8c093b 7049 iwl3945_set_rate(priv);
b481de9c
ZY		 7050
7051 spin_unlock_irqrestore(&priv->lock, flags);
7052
7053#ifdef IEEE80211_CONF_CHANNEL_SWITCH
7054 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 7055 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 7056 goto out;
b481de9c
ZY		 7057 }
7058#endif
7059
bb8c093b 7060 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 7061
7062 if (!conf->radio_enabled) {
7063 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 7064 goto out;
b481de9c
ZY		 7065 }
7066
bb8c093b 7067 if (iwl3945_is_rfkill(priv)) {
b481de9c 7068 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 7069 ret = -EIO;
7070 goto out;
b481de9c
ZY		 7071 }
7072
bb8c093b 7073 iwl3945_set_rate(priv);
b481de9c
ZY		 7074
7075 if (memcmp(&priv->active_rxon,
7076 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 7077 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7078 else
7079 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
7080
7081 IWL_DEBUG_MAC80211("leave\n");
7082
76bb77e0 7083out:
a0646470 7084 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 7085 mutex_unlock(&priv->mutex);
76bb77e0 7086 return ret;
b481de9c
ZY		 7087}
7088
bb8c093b 7089static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 7090{
7091 int rc = 0;
7092
d986bcd1 7093 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 7094 return;
7095
7096 /* The following should be done only at AP bring up */
7097 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
7098
7099 /* RXON - unassoc (to set timing command) */
7100 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7101 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7102
7103 /* RXON Timing */
bb8c093b
CH		 7104 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
7105 iwl3945_setup_rxon_timing(priv);
7106 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 7107 sizeof(priv->rxon_timing), &priv->rxon_timing);
7108 if (rc)
7109 IWL_WARNING("REPLY_RXON_TIMING failed - "
7110 "Attempting to continue.\n");
7111
7112 /* FIXME: what should be the assoc_id for AP? */
7113 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
7114 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
7115 priv->staging_rxon.flags |=
7116 RXON_FLG_SHORT_PREAMBLE_MSK;
7117 else
7118 priv->staging_rxon.flags &=
7119 ~RXON_FLG_SHORT_PREAMBLE_MSK;
7120
7121 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
7122 if (priv->assoc_capability &
7123 WLAN_CAPABILITY_SHORT_SLOT_TIME)
7124 priv->staging_rxon.flags |=
7125 RXON_FLG_SHORT_SLOT_MSK;
7126 else
7127 priv->staging_rxon.flags &=
7128 ~RXON_FLG_SHORT_SLOT_MSK;
7129
7130 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7131 priv->staging_rxon.flags &=
7132 ~RXON_FLG_SHORT_SLOT_MSK;
7133 }
7134 /* restore RXON assoc */
7135 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 7136 iwl3945_commit_rxon(priv);
7137 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 7138 }
bb8c093b 7139 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 7140
7141 /* FIXME - we need to add code here to detect a totally new
7142 * configuration, reset the AP, unassoc, rxon timing, assoc,
7143 * clear sta table, add BCAST sta... */
7144}
7145
32bfd35d
JB		 7146static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
7147 struct ieee80211_vif *vif,
b481de9c
ZY		 7148 struct ieee80211_if_conf *conf)
7149{
bb8c093b 7150 struct iwl3945_priv *priv = hw->priv;
0795af57 7151 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 7152 unsigned long flags;
7153 int rc;
7154
7155 if (conf == NULL)
7156 return -EIO;
7157
4150c572
JB		 7158 /* XXX: this MUST use conf->mac_addr */
7159
b481de9c
ZY		 7160 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
7161 (!conf->beacon || !conf->ssid_len)) {
7162 IWL_DEBUG_MAC80211
7163 ("Leaving in AP mode because HostAPD is not ready.\n");
7164 return 0;
7165 }
7166
5a66926a
ZY		 7167 if (!iwl3945_is_alive(priv))
7168 return -EAGAIN;
7169
b481de9c
ZY		 7170 mutex_lock(&priv->mutex);
7171
b481de9c 7172 if (conf->bssid)
0795af57
JP		 7173 IWL_DEBUG_MAC80211("bssid: %s\n",
7174 print_mac(mac, conf->bssid));
b481de9c 7175
4150c572
JB		 7176/*
7177 * very dubious code was here; the probe filtering flag is never set:
7178 *
b481de9c
ZY		 7179 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
7180 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572
JB		 7181 */
7182 if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
b481de9c
ZY		 7183 IWL_DEBUG_MAC80211("leave - scanning\n");
7184 mutex_unlock(&priv->mutex);
7185 return 0;
7186 }
7187
32bfd35d
JB		 7188 if (priv->vif != vif) {
7189 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b481de9c
ZY		 7190 mutex_unlock(&priv->mutex);
7191 return 0;
7192 }
7193
7194 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
7195 if (!conf->bssid) {
7196 conf->bssid = priv->mac_addr;
7197 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 7198 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
7199 print_mac(mac, conf->bssid));
b481de9c
ZY		 7200 }
7201 if (priv->ibss_beacon)
7202 dev_kfree_skb(priv->ibss_beacon);
7203
7204 priv->ibss_beacon = conf->beacon;
7205 }
7206
fde3571f
MA		 7207 if (iwl3945_is_rfkill(priv))
7208 goto done;
7209
b481de9c
ZY		 7210 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
7211 !is_multicast_ether_addr(conf->bssid)) {
7212 /* If there is currently a HW scan going on in the background
7213 * then we need to cancel it else the RXON below will fail. */
bb8c093b 7214 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 7215 IWL_WARNING("Aborted scan still in progress "
7216 "after 100ms\n");
7217 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
7218 mutex_unlock(&priv->mutex);
7219 return -EAGAIN;
7220 }
7221 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
7222
7223 /* TODO: Audit driver for usage of these members and see
7224 * if mac80211 deprecates them (priv->bssid looks like it
7225 * shouldn't be there, but I haven't scanned the IBSS code
7226 * to verify) - jpk */
7227 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
7228
7229 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 7230 iwl3945_config_ap(priv);
b481de9c 7231 else {
bb8c093b 7232 rc = iwl3945_commit_rxon(priv);
b481de9c 7233 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 7234 iwl3945_add_station(priv,
556f8db7 7235 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 7236 }
7237
7238 } else {
bb8c093b 7239 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 7240 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7241 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7242 }
7243
fde3571f 7244 done:
b481de9c
ZY		 7245 spin_lock_irqsave(&priv->lock, flags);
7246 if (!conf->ssid_len)
7247 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7248 else
7249 memcpy(priv->essid, conf->ssid, conf->ssid_len);
7250
7251 priv->essid_len = conf->ssid_len;
7252 spin_unlock_irqrestore(&priv->lock, flags);
7253
7254 IWL_DEBUG_MAC80211("leave\n");
7255 mutex_unlock(&priv->mutex);
7256
7257 return 0;
7258}
7259
bb8c093b 7260static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 7261 unsigned int changed_flags,
7262 unsigned int *total_flags,
7263 int mc_count, struct dev_addr_list *mc_list)
7264{
7265 /*
7266 * XXX: dummy
bb8c093b 7267 * see also iwl3945_connection_init_rx_config
4150c572
JB		 7268 */
7269 *total_flags = 0;
7270}
7271
bb8c093b 7272static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7273 struct ieee80211_if_init_conf *conf)
7274{
bb8c093b 7275 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7276
7277 IWL_DEBUG_MAC80211("enter\n");
7278
7279 mutex_lock(&priv->mutex);
6ef89d0a 7280
fde3571f
MA		 7281 if (iwl3945_is_ready_rf(priv)) {
7282 iwl3945_scan_cancel_timeout(priv, 100);
7283 cancel_delayed_work(&priv->post_associate);
7284 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7285 iwl3945_commit_rxon(priv);
7286 }
32bfd35d
JB		 7287 if (priv->vif == conf->vif) {
7288 priv->vif = NULL;
b481de9c
ZY		 7289 memset(priv->bssid, 0, ETH_ALEN);
7290 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7291 priv->essid_len = 0;
7292 }
7293 mutex_unlock(&priv->mutex);
7294
7295 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7296}
7297
bb8c093b 7298static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7299{
7300 int rc = 0;
7301 unsigned long flags;
bb8c093b 7302 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7303
7304 IWL_DEBUG_MAC80211("enter\n");
7305
15e869d8 7306 mutex_lock(&priv->mutex);
b481de9c
ZY		 7307 spin_lock_irqsave(&priv->lock, flags);
7308
bb8c093b 7309 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7310 rc = -EIO;
7311 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7312 goto out_unlock;
7313 }
7314
7315 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7316 rc = -EIO;
7317 IWL_ERROR("ERROR: APs don't scan\n");
7318 goto out_unlock;
7319 }
7320
7878a5a4
MA		 7321 /* we don't schedule scan within next_scan_jiffies period */
7322 if (priv->next_scan_jiffies &&
7323 time_after(priv->next_scan_jiffies, jiffies)) {
7324 rc = -EAGAIN;
7325 goto out_unlock;
7326 }
b481de9c 7327 /* if we just finished scan ask for delay */
7878a5a4
MA		 7328 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
7329 IWL_DELAY_NEXT_SCAN, jiffies)) {
b481de9c
ZY		 7330 rc = -EAGAIN;
7331 goto out_unlock;
7332 }
7333 if (len) {
7878a5a4 7334 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7335 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7336
7337 priv->one_direct_scan = 1;
7338 priv->direct_ssid_len = (u8)
7339 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7340 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7341 } else
7342 priv->one_direct_scan = 0;
b481de9c 7343
bb8c093b 7344 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7345
7346 IWL_DEBUG_MAC80211("leave\n");
7347
7348out_unlock:
7349 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7350 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7351
7352 return rc;
7353}
7354
bb8c093b 7355static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7356 const u8 *local_addr, const u8 *addr,
7357 struct ieee80211_key_conf *key)
7358{
bb8c093b 7359 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7360 int rc = 0;
7361 u8 sta_id;
7362
7363 IWL_DEBUG_MAC80211("enter\n");
7364
bb8c093b 7365 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7366 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7367 return -EOPNOTSUPP;
7368 }
7369
7370 if (is_zero_ether_addr(addr))
7371 /* only support pairwise keys */
7372 return -EOPNOTSUPP;
7373
bb8c093b 7374 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7375 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 7376 DECLARE_MAC_BUF(mac);
7377
7378 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7379 print_mac(mac, addr));
b481de9c
ZY		 7380 return -EINVAL;
7381 }
7382
7383 mutex_lock(&priv->mutex);
7384
bb8c093b 7385 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7386
b481de9c
ZY		 7387 switch (cmd) {
7388 case SET_KEY:
bb8c093b 7389 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7390 if (!rc) {
bb8c093b
CH		 7391 iwl3945_set_rxon_hwcrypto(priv, 1);
7392 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7393 key->hw_key_idx = sta_id;
7394 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7396 }
7397 break;
7398 case DISABLE_KEY:
bb8c093b 7399 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7400 if (!rc) {
bb8c093b
CH		 7401 iwl3945_set_rxon_hwcrypto(priv, 0);
7402 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7403 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7404 }
7405 break;
7406 default:
7407 rc = -EINVAL;
7408 }
7409
7410 IWL_DEBUG_MAC80211("leave\n");
7411 mutex_unlock(&priv->mutex);
7412
7413 return rc;
7414}
7415
bb8c093b 7416static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
b481de9c
ZY		 7417 const struct ieee80211_tx_queue_params *params)
7418{
bb8c093b 7419 struct iwl3945_priv *priv = hw->priv;
c8b0e6e1 7420#ifdef CONFIG_IWL3945_QOS
b481de9c
ZY		 7421 unsigned long flags;
7422 int q;
0054b34d 7423#endif /* CONFIG_IWL3945_QOS */
b481de9c
ZY		 7424
7425 IWL_DEBUG_MAC80211("enter\n");
7426
bb8c093b 7427 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7428 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7429 return -EIO;
7430 }
7431
7432 if (queue >= AC_NUM) {
7433 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7434 return 0;
7435 }
7436
c8b0e6e1 7437#ifdef CONFIG_IWL3945_QOS
b481de9c
ZY		 7438 if (!priv->qos_data.qos_enable) {
7439 priv->qos_data.qos_active = 0;
7440 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7441 return 0;
7442 }
7443 q = AC_NUM - 1 - queue;
7444
7445 spin_lock_irqsave(&priv->lock, flags);
7446
7447 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7448 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7449 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7450 priv->qos_data.def_qos_parm.ac[q].edca_txop =
7451 cpu_to_le16((params->burst_time * 100));
7452
7453 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7454 priv->qos_data.qos_active = 1;
7455
7456 spin_unlock_irqrestore(&priv->lock, flags);
7457
7458 mutex_lock(&priv->mutex);
7459 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH		 7460 iwl3945_activate_qos(priv, 1);
7461 else if (priv->assoc_id && iwl3945_is_associated(priv))
7462 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7463
7464 mutex_unlock(&priv->mutex);
7465
c8b0e6e1 7466#endif /*CONFIG_IWL3945_QOS */
b481de9c
ZY		 7467
7468 IWL_DEBUG_MAC80211("leave\n");
7469 return 0;
7470}
7471
bb8c093b 7472static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7473 struct ieee80211_tx_queue_stats *stats)
7474{
bb8c093b 7475 struct iwl3945_priv *priv = hw->priv;
b481de9c 7476 int i, avail;
bb8c093b
CH		 7477 struct iwl3945_tx_queue *txq;
7478 struct iwl3945_queue *q;
b481de9c
ZY		 7479 unsigned long flags;
7480
7481 IWL_DEBUG_MAC80211("enter\n");
7482
bb8c093b 7483 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7484 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7485 return -EIO;
7486 }
7487
7488 spin_lock_irqsave(&priv->lock, flags);
7489
7490 for (i = 0; i < AC_NUM; i++) {
7491 txq = &priv->txq[i];
7492 q = &txq->q;
bb8c093b 7493 avail = iwl3945_queue_space(q);
b481de9c
ZY		 7494
7495 stats->data[i].len = q->n_window - avail;
7496 stats->data[i].limit = q->n_window - q->high_mark;
7497 stats->data[i].count = q->n_window;
7498
7499 }
7500 spin_unlock_irqrestore(&priv->lock, flags);
7501
7502 IWL_DEBUG_MAC80211("leave\n");
7503
7504 return 0;
7505}
7506
bb8c093b 7507static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7508 struct ieee80211_low_level_stats *stats)
7509{
7510 IWL_DEBUG_MAC80211("enter\n");
7511 IWL_DEBUG_MAC80211("leave\n");
7512
7513 return 0;
7514}
7515
bb8c093b 7516static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7517{
7518 IWL_DEBUG_MAC80211("enter\n");
7519 IWL_DEBUG_MAC80211("leave\n");
7520
7521 return 0;
7522}
7523
bb8c093b 7524static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7525{
bb8c093b 7526 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7527 unsigned long flags;
7528
7529 mutex_lock(&priv->mutex);
7530 IWL_DEBUG_MAC80211("enter\n");
7531
c8b0e6e1 7532#ifdef CONFIG_IWL3945_QOS
bb8c093b 7533 iwl3945_reset_qos(priv);
b481de9c
ZY		 7534#endif
7535 cancel_delayed_work(&priv->post_associate);
7536
7537 spin_lock_irqsave(&priv->lock, flags);
7538 priv->assoc_id = 0;
7539 priv->assoc_capability = 0;
7540 priv->call_post_assoc_from_beacon = 0;
7541
7542 /* new association get rid of ibss beacon skb */
7543 if (priv->ibss_beacon)
7544 dev_kfree_skb(priv->ibss_beacon);
7545
7546 priv->ibss_beacon = NULL;
7547
7548 priv->beacon_int = priv->hw->conf.beacon_int;
7549 priv->timestamp1 = 0;
7550 priv->timestamp0 = 0;
7551 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7552 priv->beacon_int = 0;
7553
7554 spin_unlock_irqrestore(&priv->lock, flags);
7555
fde3571f
MA		 7556 if (!iwl3945_is_ready_rf(priv)) {
7557 IWL_DEBUG_MAC80211("leave - not ready\n");
7558 mutex_unlock(&priv->mutex);
7559 return;
7560 }
7561
15e869d8
MA		 7562 /* we are restarting association process
7563 * clear RXON_FILTER_ASSOC_MSK bit
7564 */
7565 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7566 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7567 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7568 iwl3945_commit_rxon(priv);
15e869d8
MA		 7569 }
7570
b481de9c
ZY		 7571 /* Per mac80211.h: This is only used in IBSS mode... */
7572 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7573
b481de9c
ZY		 7574 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7575 mutex_unlock(&priv->mutex);
7576 return;
b481de9c
ZY		 7577 }
7578
7579 priv->only_active_channel = 0;
7580
bb8c093b 7581 iwl3945_set_rate(priv);
b481de9c
ZY		 7582
7583 mutex_unlock(&priv->mutex);
7584
7585 IWL_DEBUG_MAC80211("leave\n");
7586
7587}
7588
bb8c093b 7589static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 7590 struct ieee80211_tx_control *control)
7591{
bb8c093b 7592 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7593 unsigned long flags;
7594
7595 mutex_lock(&priv->mutex);
7596 IWL_DEBUG_MAC80211("enter\n");
7597
bb8c093b 7598 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7599 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7600 mutex_unlock(&priv->mutex);
7601 return -EIO;
7602 }
7603
7604 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7605 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7606 mutex_unlock(&priv->mutex);
7607 return -EIO;
7608 }
7609
7610 spin_lock_irqsave(&priv->lock, flags);
7611
7612 if (priv->ibss_beacon)
7613 dev_kfree_skb(priv->ibss_beacon);
7614
7615 priv->ibss_beacon = skb;
7616
7617 priv->assoc_id = 0;
7618
7619 IWL_DEBUG_MAC80211("leave\n");
7620 spin_unlock_irqrestore(&priv->lock, flags);
7621
c8b0e6e1 7622#ifdef CONFIG_IWL3945_QOS
bb8c093b 7623 iwl3945_reset_qos(priv);
b481de9c
ZY		 7624#endif
7625
7626 queue_work(priv->workqueue, &priv->post_associate.work);
7627
7628 mutex_unlock(&priv->mutex);
7629
7630 return 0;
7631}
7632
7633/*****************************************************************************
7634 *
7635 * sysfs attributes
7636 *
7637 *****************************************************************************/
7638
c8b0e6e1 7639#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7640
7641/*
7642 * The following adds a new attribute to the sysfs representation
7643 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7644 * used for controlling the debug level.
7645 *
7646 * See the level definitions in iwl for details.
7647 */
7648
7649static ssize_t show_debug_level(struct device_driver *d, char *buf)
7650{
bb8c093b 7651 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7652}
7653static ssize_t store_debug_level(struct device_driver *d,
7654 const char *buf, size_t count)
7655{
7656 char *p = (char *)buf;
7657 u32 val;
7658
7659 val = simple_strtoul(p, &p, 0);
7660 if (p == buf)
7661 printk(KERN_INFO DRV_NAME
7662 ": %s is not in hex or decimal form.\n", buf);
7663 else
bb8c093b 7664 iwl3945_debug_level = val;
b481de9c
ZY		 7665
7666 return strnlen(buf, count);
7667}
7668
7669static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7670 show_debug_level, store_debug_level);
7671
c8b0e6e1 7672#endif /* CONFIG_IWL3945_DEBUG */
b481de9c
ZY		 7673
7674static ssize_t show_rf_kill(struct device *d,
7675 struct device_attribute *attr, char *buf)
7676{
7677 /*
7678 * 0 - RF kill not enabled
7679 * 1 - SW based RF kill active (sysfs)
7680 * 2 - HW based RF kill active
7681 * 3 - Both HW and SW based RF kill active
7682 */
bb8c093b 7683 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7684 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
7685 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
7686
7687 return sprintf(buf, "%i\n", val);
7688}
7689
7690static ssize_t store_rf_kill(struct device *d,
7691 struct device_attribute *attr,
7692 const char *buf, size_t count)
7693{
bb8c093b 7694 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7695
7696 mutex_lock(&priv->mutex);
bb8c093b 7697 iwl3945_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY		 7698 mutex_unlock(&priv->mutex);
7699
7700 return count;
7701}
7702
7703static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
7704
7705static ssize_t show_temperature(struct device *d,
7706 struct device_attribute *attr, char *buf)
7707{
bb8c093b 7708 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7709
bb8c093b 7710 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7711 return -EAGAIN;
7712
bb8c093b 7713 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7714}
7715
7716static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7717
7718static ssize_t show_rs_window(struct device *d,
7719 struct device_attribute *attr,
7720 char *buf)
7721{
bb8c093b
CH		 7722 struct iwl3945_priv *priv = d->driver_data;
7723 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 7724}
7725static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7726
7727static ssize_t show_tx_power(struct device *d,
7728 struct device_attribute *attr, char *buf)
7729{
bb8c093b 7730 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7731 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7732}
7733
7734static ssize_t store_tx_power(struct device *d,
7735 struct device_attribute *attr,
7736 const char *buf, size_t count)
7737{
bb8c093b 7738 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7739 char *p = (char *)buf;
7740 u32 val;
7741
7742 val = simple_strtoul(p, &p, 10);
7743 if (p == buf)
7744 printk(KERN_INFO DRV_NAME
7745 ": %s is not in decimal form.\n", buf);
7746 else
bb8c093b 7747 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7748
7749 return count;
7750}
7751
7752static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7753
7754static ssize_t show_flags(struct device *d,
7755 struct device_attribute *attr, char *buf)
7756{
bb8c093b 7757 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7758
7759 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7760}
7761
7762static ssize_t store_flags(struct device *d,
7763 struct device_attribute *attr,
7764 const char *buf, size_t count)
7765{
bb8c093b 7766 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7767 u32 flags = simple_strtoul(buf, NULL, 0);
7768
7769 mutex_lock(&priv->mutex);
7770 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7771 /* Cancel any currently running scans... */
bb8c093b 7772 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7773 IWL_WARNING("Could not cancel scan.\n");
7774 else {
7775 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7776 flags);
7777 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7778 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7779 }
7780 }
7781 mutex_unlock(&priv->mutex);
7782
7783 return count;
7784}
7785
7786static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7787
7788static ssize_t show_filter_flags(struct device *d,
7789 struct device_attribute *attr, char *buf)
7790{
bb8c093b 7791 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7792
7793 return sprintf(buf, "0x%04X\n",
7794 le32_to_cpu(priv->active_rxon.filter_flags));
7795}
7796
7797static ssize_t store_filter_flags(struct device *d,
7798 struct device_attribute *attr,
7799 const char *buf, size_t count)
7800{
bb8c093b 7801 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7802 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7803
7804 mutex_lock(&priv->mutex);
7805 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7806 /* Cancel any currently running scans... */
bb8c093b 7807 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7808 IWL_WARNING("Could not cancel scan.\n");
7809 else {
7810 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7811 "0x%04X\n", filter_flags);
7812 priv->staging_rxon.filter_flags =
7813 cpu_to_le32(filter_flags);
bb8c093b 7814 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7815 }
7816 }
7817 mutex_unlock(&priv->mutex);
7818
7819 return count;
7820}
7821
7822static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7823 store_filter_flags);
7824
c8b0e6e1 7825#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7826
7827static ssize_t show_measurement(struct device *d,
7828 struct device_attribute *attr, char *buf)
7829{
bb8c093b
CH		 7830 struct iwl3945_priv *priv = dev_get_drvdata(d);
7831 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY		 7832 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7833 u8 *data = (u8 *) & measure_report;
7834 unsigned long flags;
7835
7836 spin_lock_irqsave(&priv->lock, flags);
7837 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7838 spin_unlock_irqrestore(&priv->lock, flags);
7839 return 0;
7840 }
7841 memcpy(&measure_report, &priv->measure_report, size);
7842 priv->measurement_status = 0;
7843 spin_unlock_irqrestore(&priv->lock, flags);
7844
7845 while (size && (PAGE_SIZE - len)) {
7846 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7847 PAGE_SIZE - len, 1);
7848 len = strlen(buf);
7849 if (PAGE_SIZE - len)
7850 buf[len++] = '\n';
7851
7852 ofs += 16;
7853 size -= min(size, 16U);
7854 }
7855
7856 return len;
7857}
7858
7859static ssize_t store_measurement(struct device *d,
7860 struct device_attribute *attr,
7861 const char *buf, size_t count)
7862{
bb8c093b 7863 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7864 struct ieee80211_measurement_params params = {
7865 .channel = le16_to_cpu(priv->active_rxon.channel),
7866 .start_time = cpu_to_le64(priv->last_tsf),
7867 .duration = cpu_to_le16(1),
7868 };
7869 u8 type = IWL_MEASURE_BASIC;
7870 u8 buffer[32];
7871 u8 channel;
7872
7873 if (count) {
7874 char *p = buffer;
7875 strncpy(buffer, buf, min(sizeof(buffer), count));
7876 channel = simple_strtoul(p, NULL, 0);
7877 if (channel)
7878 params.channel = channel;
7879
7880 p = buffer;
7881 while (*p && *p != ' ')
7882 p++;
7883 if (*p)
7884 type = simple_strtoul(p + 1, NULL, 0);
7885 }
7886
7887 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7888 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7889 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7890
7891 return count;
7892}
7893
7894static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7895 show_measurement, store_measurement);
c8b0e6e1 7896#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c
ZY		 7897
7898static ssize_t show_rate(struct device *d,
7899 struct device_attribute *attr, char *buf)
7900{
bb8c093b 7901 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7902 unsigned long flags;
7903 int i;
7904
7905 spin_lock_irqsave(&priv->sta_lock, flags);
7906 if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
7907 i = priv->stations[IWL_AP_ID].current_rate.s.rate;
7908 else
7909 i = priv->stations[IWL_STA_ID].current_rate.s.rate;
7910 spin_unlock_irqrestore(&priv->sta_lock, flags);
7911
bb8c093b 7912 i = iwl3945_rate_index_from_plcp(i);
b481de9c
ZY		 7913 if (i == -1)
7914 return sprintf(buf, "0\n");
7915
7916 return sprintf(buf, "%d%s\n",
bb8c093b
CH		 7917 (iwl3945_rates[i].ieee >> 1),
7918 (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
b481de9c
ZY		 7919}
7920
7921static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
7922
7923static ssize_t store_retry_rate(struct device *d,
7924 struct device_attribute *attr,
7925 const char *buf, size_t count)
7926{
bb8c093b 7927 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7928
7929 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7930 if (priv->retry_rate <= 0)
7931 priv->retry_rate = 1;
7932
7933 return count;
7934}
7935
7936static ssize_t show_retry_rate(struct device *d,
7937 struct device_attribute *attr, char *buf)
7938{
bb8c093b 7939 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7940 return sprintf(buf, "%d", priv->retry_rate);
7941}
7942
7943static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7944 store_retry_rate);
7945
7946static ssize_t store_power_level(struct device *d,
7947 struct device_attribute *attr,
7948 const char *buf, size_t count)
7949{
bb8c093b 7950 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7951 int rc;
7952 int mode;
7953
7954 mode = simple_strtoul(buf, NULL, 0);
7955 mutex_lock(&priv->mutex);
7956
bb8c093b 7957 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7958 rc = -EAGAIN;
7959 goto out;
7960 }
7961
7962 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7963 mode = IWL_POWER_AC;
7964 else
7965 mode |= IWL_POWER_ENABLED;
7966
7967 if (mode != priv->power_mode) {
bb8c093b 7968 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7969 if (rc) {
7970 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7971 goto out;
7972 }
7973 priv->power_mode = mode;
7974 }
7975
7976 rc = count;
7977
7978 out:
7979 mutex_unlock(&priv->mutex);
7980 return rc;
7981}
7982
7983#define MAX_WX_STRING 80
7984
7985/* Values are in microsecond */
7986static const s32 timeout_duration[] = {
7987 350000,
7988 250000,
7989 75000,
7990 37000,
7991 25000,
7992};
7993static const s32 period_duration[] = {
7994 400000,
7995 700000,
7996 1000000,
7997 1000000,
7998 1000000
7999};
8000
8001static ssize_t show_power_level(struct device *d,
8002 struct device_attribute *attr, char *buf)
8003{
bb8c093b 8004 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8005 int level = IWL_POWER_LEVEL(priv->power_mode);
8006 char *p = buf;
8007
8008 p += sprintf(p, "%d ", level);
8009 switch (level) {
8010 case IWL_POWER_MODE_CAM:
8011 case IWL_POWER_AC:
8012 p += sprintf(p, "(AC)");
8013 break;
8014 case IWL_POWER_BATTERY:
8015 p += sprintf(p, "(BATTERY)");
8016 break;
8017 default:
8018 p += sprintf(p,
8019 "(Timeout %dms, Period %dms)",
8020 timeout_duration[level - 1] / 1000,
8021 period_duration[level - 1] / 1000);
8022 }
8023
8024 if (!(priv->power_mode & IWL_POWER_ENABLED))
8025 p += sprintf(p, " OFF\n");
8026 else
8027 p += sprintf(p, " \n");
8028
8029 return (p - buf + 1);
8030
8031}
8032
8033static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
8034 store_power_level);
8035
8036static ssize_t show_channels(struct device *d,
8037 struct device_attribute *attr, char *buf)
8038{
8318d78a
JB		 8039 /* all this shit doesn't belong into sysfs anyway */
8040 return 0;
b481de9c
ZY		 8041}
8042
8043static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
8044
8045static ssize_t show_statistics(struct device *d,
8046 struct device_attribute *attr, char *buf)
8047{
bb8c093b
CH		 8048 struct iwl3945_priv *priv = dev_get_drvdata(d);
8049 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY		 8050 u32 len = 0, ofs = 0;
8051 u8 *data = (u8 *) & priv->statistics;
8052 int rc = 0;
8053
bb8c093b 8054 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 8055 return -EAGAIN;
8056
8057 mutex_lock(&priv->mutex);
bb8c093b 8058 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 8059 mutex_unlock(&priv->mutex);
8060
8061 if (rc) {
8062 len = sprintf(buf,
8063 "Error sending statistics request: 0x%08X\n", rc);
8064 return len;
8065 }
8066
8067 while (size && (PAGE_SIZE - len)) {
8068 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
8069 PAGE_SIZE - len, 1);
8070 len = strlen(buf);
8071 if (PAGE_SIZE - len)
8072 buf[len++] = '\n';
8073
8074 ofs += 16;
8075 size -= min(size, 16U);
8076 }
8077
8078 return len;
8079}
8080
8081static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
8082
8083static ssize_t show_antenna(struct device *d,
8084 struct device_attribute *attr, char *buf)
8085{
bb8c093b 8086 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 8087
bb8c093b 8088 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 8089 return -EAGAIN;
8090
8091 return sprintf(buf, "%d\n", priv->antenna);
8092}
8093
8094static ssize_t store_antenna(struct device *d,
8095 struct device_attribute *attr,
8096 const char *buf, size_t count)
8097{
8098 int ant;
bb8c093b 8099 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8100
8101 if (count == 0)
8102 return 0;
8103
8104 if (sscanf(buf, "%1i", &ant) != 1) {
8105 IWL_DEBUG_INFO("not in hex or decimal form.\n");
8106 return count;
8107 }
8108
8109 if ((ant >= 0) && (ant <= 2)) {
8110 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 8111 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 8112 } else
8113 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
8114
8115
8116 return count;
8117}
8118
8119static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
8120
8121static ssize_t show_status(struct device *d,
8122 struct device_attribute *attr, char *buf)
8123{
bb8c093b
CH		 8124 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
8125 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 8126 return -EAGAIN;
8127 return sprintf(buf, "0x%08x\n", (int)priv->status);
8128}
8129
8130static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
8131
8132static ssize_t dump_error_log(struct device *d,
8133 struct device_attribute *attr,
8134 const char *buf, size_t count)
8135{
8136 char *p = (char *)buf;
8137
8138 if (p[0] == '1')
bb8c093b 8139 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 8140
8141 return strnlen(buf, count);
8142}
8143
8144static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
8145
8146static ssize_t dump_event_log(struct device *d,
8147 struct device_attribute *attr,
8148 const char *buf, size_t count)
8149{
8150 char *p = (char *)buf;
8151
8152 if (p[0] == '1')
bb8c093b 8153 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 8154
8155 return strnlen(buf, count);
8156}
8157
8158static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
8159
8160/*****************************************************************************
8161 *
8162 * driver setup and teardown
8163 *
8164 *****************************************************************************/
8165
bb8c093b 8166static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 8167{
8168 priv->workqueue = create_workqueue(DRV_NAME);
8169
8170 init_waitqueue_head(&priv->wait_command_queue);
8171
bb8c093b
CH		 8172 INIT_WORK(&priv->up, iwl3945_bg_up);
8173 INIT_WORK(&priv->restart, iwl3945_bg_restart);
8174 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
8175 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
8176 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
8177 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
8178 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
8179 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
8180 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
8181 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
8182 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
8183 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
8184
8185 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 8186
8187 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 8188 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 8189}
8190
bb8c093b 8191static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 8192{
bb8c093b 8193 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 8194
e47eb6ad 8195 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 8196 cancel_delayed_work(&priv->scan_check);
8197 cancel_delayed_work(&priv->alive_start);
8198 cancel_delayed_work(&priv->post_associate);
8199 cancel_work_sync(&priv->beacon_update);
8200}
8201
bb8c093b 8202static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 8203 &dev_attr_antenna.attr,
8204 &dev_attr_channels.attr,
8205 &dev_attr_dump_errors.attr,
8206 &dev_attr_dump_events.attr,
8207 &dev_attr_flags.attr,
8208 &dev_attr_filter_flags.attr,
c8b0e6e1 8209#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 8210 &dev_attr_measurement.attr,
8211#endif
8212 &dev_attr_power_level.attr,
8213 &dev_attr_rate.attr,
8214 &dev_attr_retry_rate.attr,
8215 &dev_attr_rf_kill.attr,
8216 &dev_attr_rs_window.attr,
8217 &dev_attr_statistics.attr,
8218 &dev_attr_status.attr,
8219 &dev_attr_temperature.attr,
b481de9c
ZY		 8220 &dev_attr_tx_power.attr,
8221
8222 NULL
8223};
8224
bb8c093b 8225static struct attribute_group iwl3945_attribute_group = {
b481de9c 8226 .name = NULL, /* put in device directory */
bb8c093b 8227 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 8228};
8229
bb8c093b
CH		 8230static struct ieee80211_ops iwl3945_hw_ops = {
8231 .tx = iwl3945_mac_tx,
8232 .start = iwl3945_mac_start,
8233 .stop = iwl3945_mac_stop,
8234 .add_interface = iwl3945_mac_add_interface,
8235 .remove_interface = iwl3945_mac_remove_interface,
8236 .config = iwl3945_mac_config,
8237 .config_interface = iwl3945_mac_config_interface,
8238 .configure_filter = iwl3945_configure_filter,
8239 .set_key = iwl3945_mac_set_key,
8240 .get_stats = iwl3945_mac_get_stats,
8241 .get_tx_stats = iwl3945_mac_get_tx_stats,
8242 .conf_tx = iwl3945_mac_conf_tx,
8243 .get_tsf = iwl3945_mac_get_tsf,
8244 .reset_tsf = iwl3945_mac_reset_tsf,
8245 .beacon_update = iwl3945_mac_beacon_update,
8246 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 8247};
8248
bb8c093b 8249static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 8250{
8251 int err = 0;
8252 u32 pci_id;
bb8c093b 8253 struct iwl3945_priv *priv;
b481de9c
ZY		 8254 struct ieee80211_hw *hw;
8255 int i;
5a66926a 8256 DECLARE_MAC_BUF(mac);
b481de9c 8257
6440adb5
CB		 8258 /* Disabling hardware scan means that mac80211 will perform scans
8259 * "the hard way", rather than using device's scan. */
bb8c093b 8260 if (iwl3945_param_disable_hw_scan) {
b481de9c 8261 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 8262 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 8263 }
8264
bb8c093b
CH		 8265 if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
8266 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c
ZY		 8267 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
8268 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
8269 err = -EINVAL;
8270 goto out;
8271 }
8272
8273 /* mac80211 allocates memory for this device instance, including
8274 * space for this driver's private structure */
bb8c093b 8275 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 8276 if (hw == NULL) {
8277 IWL_ERROR("Can not allocate network device\n");
8278 err = -ENOMEM;
8279 goto out;
8280 }
8281 SET_IEEE80211_DEV(hw, &pdev->dev);
8282
f51359a8
JB		 8283 hw->rate_control_algorithm = "iwl-3945-rs";
8284
b481de9c
ZY		 8285 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
8286 priv = hw->priv;
8287 priv->hw = hw;
8288
8289 priv->pci_dev = pdev;
6440adb5
CB		 8290
8291 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 8292 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 8293#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8294 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 8295 atomic_set(&priv->restrict_refcnt, 0);
8296#endif
8297 priv->retry_rate = 1;
8298
8299 priv->ibss_beacon = NULL;
8300
8301 /* Tell mac80211 and its clients (e.g. Wireless Extensions)
8302 * the range of signal quality values that we'll provide.
8303 * Negative values for level/noise indicate that we'll provide dBm.
8304 * For WE, at least, non-0 values here *enable* display of values
8305 * in app (iwconfig). */
8306 hw->max_rssi = -20; /* signal level, negative indicates dBm */
8307 hw->max_noise = -20; /* noise level, negative indicates dBm */
8308 hw->max_signal = 100; /* link quality indication (%) */
8309
8310 /* Tell mac80211 our Tx characteristics */
8311 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
8312
6440adb5 8313 /* 4 EDCA QOS priorities */
b481de9c
ZY		 8314 hw->queues = 4;
8315
8316 spin_lock_init(&priv->lock);
8317 spin_lock_init(&priv->power_data.lock);
8318 spin_lock_init(&priv->sta_lock);
8319 spin_lock_init(&priv->hcmd_lock);
8320
8321 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8322 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8323
8324 INIT_LIST_HEAD(&priv->free_frames);
8325
8326 mutex_init(&priv->mutex);
8327 if (pci_enable_device(pdev)) {
8328 err = -ENODEV;
8329 goto out_ieee80211_free_hw;
8330 }
8331
8332 pci_set_master(pdev);
8333
6440adb5 8334 /* Clear the driver's (not device's) station table */
bb8c093b 8335 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8336
8337 priv->data_retry_limit = -1;
8338 priv->ieee_channels = NULL;
8339 priv->ieee_rates = NULL;
8318d78a 8340 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 8341
8342 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8343 if (!err)
8344 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8345 if (err) {
8346 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8347 goto out_pci_disable_device;
8348 }
8349
8350 pci_set_drvdata(pdev, priv);
8351 err = pci_request_regions(pdev, DRV_NAME);
8352 if (err)
8353 goto out_pci_disable_device;
6440adb5 8354
b481de9c
ZY		 8355 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8356 * PCI Tx retries from interfering with C3 CPU state */
8357 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8358
b481de9c
ZY		 8359 priv->hw_base = pci_iomap(pdev, 0, 0);
8360 if (!priv->hw_base) {
8361 err = -ENODEV;
8362 goto out_pci_release_regions;
8363 }
8364
8365 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8366 (unsigned long long) pci_resource_len(pdev, 0));
8367 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8368
8369 /* Initialize module parameter values here */
8370
6440adb5 8371 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8372 if (iwl3945_param_disable) {
b481de9c
ZY		 8373 set_bit(STATUS_RF_KILL_SW, &priv->status);
8374 IWL_DEBUG_INFO("Radio disabled.\n");
8375 }
8376
8377 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8378
8379 pci_id =
8380 (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
8381
8382 switch (pci_id) {
8383 case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
8384 case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
8385 case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
8386 case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
8387 priv->is_abg = 0;
8388 break;
8389
8390 /*
8391 * Rest are assumed ABG SKU -- if this is not the
8392 * case then the card will get the wrong 'Detected'
8393 * line in the kernel log however the code that
8394 * initializes the GEO table will detect no A-band
8395 * channels and remove the is_abg mask.
8396 */
8397 default:
8398 priv->is_abg = 1;
8399 break;
8400 }
8401
8402 printk(KERN_INFO DRV_NAME
8403 ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
8404 priv->is_abg ? "A" : "");
8405
8406 /* Device-specific setup */
bb8c093b 8407 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 8408 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 8409 goto out_iounmap;
8410 }
8411
c8b0e6e1 8412#ifdef CONFIG_IWL3945_QOS
bb8c093b 8413 if (iwl3945_param_qos_enable)
b481de9c
ZY		 8414 priv->qos_data.qos_enable = 1;
8415
bb8c093b 8416 iwl3945_reset_qos(priv);
b481de9c
ZY		 8417
8418 priv->qos_data.qos_active = 0;
8419 priv->qos_data.qos_cap.val = 0;
c8b0e6e1 8420#endif /* CONFIG_IWL3945_QOS */
b481de9c 8421
8318d78a 8422 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 8423 iwl3945_setup_deferred_work(priv);
8424 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 8425
8426 priv->rates_mask = IWL_RATES_MASK;
8427 /* If power management is turned on, default to AC mode */
8428 priv->power_mode = IWL_POWER_AC;
8429 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8430
bb8c093b 8431 iwl3945_disable_interrupts(priv);
49df2b33 8432
bb8c093b 8433 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8434 if (err) {
8435 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 8436 goto out_release_irq;
8437 }
8438
5a66926a
ZY		 8439 /* nic init */
8440 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8441 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8442
8443 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8444 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8445 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8446 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8447 if (err < 0) {
8448 IWL_DEBUG_INFO("Failed to init the card\n");
8449 goto out_remove_sysfs;
8450 }
8451 /* Read the EEPROM */
8452 err = iwl3945_eeprom_init(priv);
b481de9c 8453 if (err) {
5a66926a
ZY		 8454 IWL_ERROR("Unable to init EEPROM\n");
8455 goto out_remove_sysfs;
b481de9c 8456 }
5a66926a
ZY		 8457 /* MAC Address location in EEPROM same for 3945/4965 */
8458 get_eeprom_mac(priv, priv->mac_addr);
8459 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8460 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8461
849e0dce
RC		 8462 err = iwl3945_init_channel_map(priv);
8463 if (err) {
8464 IWL_ERROR("initializing regulatory failed: %d\n", err);
8465 goto out_remove_sysfs;
8466 }
8467
8468 err = iwl3945_init_geos(priv);
8469 if (err) {
8470 IWL_ERROR("initializing geos failed: %d\n", err);
8471 goto out_free_channel_map;
8472 }
849e0dce 8473
5a66926a
ZY		 8474 iwl3945_rate_control_register(priv->hw);
8475 err = ieee80211_register_hw(priv->hw);
8476 if (err) {
8477 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8478 goto out_free_geos;
5a66926a 8479 }
b481de9c 8480
5a66926a
ZY		 8481 priv->hw->conf.beacon_int = 100;
8482 priv->mac80211_registered = 1;
8483 pci_save_state(pdev);
8484 pci_disable_device(pdev);
b481de9c
ZY		 8485
8486 return 0;
8487
849e0dce
RC		 8488 out_free_geos:
8489 iwl3945_free_geos(priv);
8490 out_free_channel_map:
8491 iwl3945_free_channel_map(priv);
5a66926a 8492 out_remove_sysfs:
bb8c093b 8493 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8494
8495 out_release_irq:
b481de9c
ZY		 8496 destroy_workqueue(priv->workqueue);
8497 priv->workqueue = NULL;
bb8c093b 8498 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8499
8500 out_iounmap:
8501 pci_iounmap(pdev, priv->hw_base);
8502 out_pci_release_regions:
8503 pci_release_regions(pdev);
8504 out_pci_disable_device:
8505 pci_disable_device(pdev);
8506 pci_set_drvdata(pdev, NULL);
8507 out_ieee80211_free_hw:
8508 ieee80211_free_hw(priv->hw);
8509 out:
8510 return err;
8511}
8512
bb8c093b 8513static void iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8514{
bb8c093b 8515 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8516 struct list_head *p, *q;
8517 int i;
8518
8519 if (!priv)
8520 return;
8521
8522 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8523
b481de9c 8524 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8525
bb8c093b 8526 iwl3945_down(priv);
b481de9c
ZY		 8527
8528 /* Free MAC hash list for ADHOC */
8529 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8530 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8531 list_del(p);
bb8c093b 8532 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY		 8533 }
8534 }
8535
bb8c093b 8536 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8537
bb8c093b 8538 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8539
8540 if (priv->rxq.bd)
bb8c093b
CH		 8541 iwl3945_rx_queue_free(priv, &priv->rxq);
8542 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8543
bb8c093b
CH		 8544 iwl3945_unset_hw_setting(priv);
8545 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8546
8547 if (priv->mac80211_registered) {
8548 ieee80211_unregister_hw(priv->hw);
bb8c093b 8549 iwl3945_rate_control_unregister(priv->hw);
b481de9c
ZY		 8550 }
8551
6ef89d0a
MA		 8552 /*netif_stop_queue(dev); */
8553 flush_workqueue(priv->workqueue);
8554
bb8c093b 8555 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8556 * priv->workqueue... so we can't take down the workqueue
8557 * until now... */
8558 destroy_workqueue(priv->workqueue);
8559 priv->workqueue = NULL;
8560
b481de9c
ZY		 8561 pci_iounmap(pdev, priv->hw_base);
8562 pci_release_regions(pdev);
8563 pci_disable_device(pdev);
8564 pci_set_drvdata(pdev, NULL);
8565
849e0dce
RC		 8566 iwl3945_free_channel_map(priv);
8567 iwl3945_free_geos(priv);
b481de9c
ZY		 8568
8569 if (priv->ibss_beacon)
8570 dev_kfree_skb(priv->ibss_beacon);
8571
8572 ieee80211_free_hw(priv->hw);
8573}
8574
8575#ifdef CONFIG_PM
8576
bb8c093b 8577static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8578{
bb8c093b 8579 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8580
e655b9f0
ZY		 8581 if (priv->is_open) {
8582 set_bit(STATUS_IN_SUSPEND, &priv->status);
8583 iwl3945_mac_stop(priv->hw);
8584 priv->is_open = 1;
8585 }
b481de9c 8586
b481de9c
ZY		 8587 pci_set_power_state(pdev, PCI_D3hot);
8588
b481de9c
ZY		 8589 return 0;
8590}
8591
bb8c093b 8592static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8593{
bb8c093b 8594 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8595
b481de9c 8596 pci_set_power_state(pdev, PCI_D0);
b481de9c 8597
e655b9f0
ZY		 8598 if (priv->is_open)
8599 iwl3945_mac_start(priv->hw);
b481de9c 8600
e655b9f0 8601 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8602 return 0;
8603}
8604
8605#endif /* CONFIG_PM */
8606
8607/*****************************************************************************
8608 *
8609 * driver and module entry point
8610 *
8611 *****************************************************************************/
8612
bb8c093b 8613static struct pci_driver iwl3945_driver = {
b481de9c 8614 .name = DRV_NAME,
bb8c093b
CH		 8615 .id_table = iwl3945_hw_card_ids,
8616 .probe = iwl3945_pci_probe,
8617 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8618#ifdef CONFIG_PM
bb8c093b
CH		 8619 .suspend = iwl3945_pci_suspend,
8620 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8621#endif
8622};
8623
bb8c093b 8624static int __init iwl3945_init(void)
b481de9c
ZY		 8625{
8626
8627 int ret;
8628 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8629 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
bb8c093b 8630 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8631 if (ret) {
8632 IWL_ERROR("Unable to initialize PCI module\n");
8633 return ret;
8634 }
c8b0e6e1 8635#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8636 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8637 if (ret) {
8638 IWL_ERROR("Unable to create driver sysfs file\n");
bb8c093b 8639 pci_unregister_driver(&iwl3945_driver);
b481de9c
ZY		 8640 return ret;
8641 }
8642#endif
8643
8644 return ret;
8645}
8646
bb8c093b 8647static void __exit iwl3945_exit(void)
b481de9c 8648{
c8b0e6e1 8649#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8650 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8651#endif
bb8c093b 8652 pci_unregister_driver(&iwl3945_driver);
b481de9c
ZY		 8653}
8654
bb8c093b 8655module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8656MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8657module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8658MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8659module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8660MODULE_PARM_DESC(hwcrypto,
8661 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8662module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8663MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8664module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8665MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8666
bb8c093b 8667module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8668MODULE_PARM_DESC(queues_num, "number of hw queues.");
8669
8670/* QoS */
bb8c093b 8671module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8672MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8673
bb8c093b
CH		 8674module_exit(iwl3945_exit);
8675module_init(iwl3945_init);
Linux 6.x block layer and io_uring tree(s)