iwlwifi: cleanup usage of inline functions
[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
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49#include "iwl-3945.h"
50#include "iwl-helpers.h"
51
c8b0e6e1 52#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 53u32 iwl3945_debug_level;
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54#endif
55
bb8c093b
CH
56static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
57 struct iwl3945_tx_queue *txq);
416e1438 58
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59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
65/* module parameters */
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66static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
67static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
68static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 69static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
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70int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
71static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
72int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
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73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
c8b0e6e1 82#ifdef CONFIG_IWL3945_DEBUG
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83#define VD "d"
84#else
85#define VD
86#endif
87
c8b0e6e1 88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
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89#define VS "s"
90#else
91#define VS
92#endif
93
71972664 94#define IWLWIFI_VERSION "1.2.23k" VD VS
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95#define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
96#define DRV_VERSION IWLWIFI_VERSION
97
98/* Change firmware file name, using "-" and incrementing number,
99 * *only* when uCode interface or architecture changes so that it
100 * is not compatible with earlier drivers.
101 * This number will also appear in << 8 position of 1st dword of uCode file */
102#define IWL3945_UCODE_API "-1"
103
104MODULE_DESCRIPTION(DRV_DESCRIPTION);
105MODULE_VERSION(DRV_VERSION);
106MODULE_AUTHOR(DRV_COPYRIGHT);
107MODULE_LICENSE("GPL");
108
416e1438 109static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
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110{
111 u16 fc = le16_to_cpu(hdr->frame_control);
112 int hdr_len = ieee80211_get_hdrlen(fc);
113
114 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
115 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
116 return NULL;
117}
118
bb8c093b
CH
119static const struct ieee80211_hw_mode *iwl3945_get_hw_mode(
120 struct iwl3945_priv *priv, int mode)
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121{
122 int i;
123
124 for (i = 0; i < 3; i++)
125 if (priv->modes[i].mode == mode)
126 return &priv->modes[i];
127
128 return NULL;
129}
130
bb8c093b 131static int iwl3945_is_empty_essid(const char *essid, int essid_len)
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132{
133 /* Single white space is for Linksys APs */
134 if (essid_len == 1 && essid[0] == ' ')
135 return 1;
136
137 /* Otherwise, if the entire essid is 0, we assume it is hidden */
138 while (essid_len) {
139 essid_len--;
140 if (essid[essid_len] != '\0')
141 return 0;
142 }
143
144 return 1;
145}
146
bb8c093b 147static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
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148{
149 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
150 const char *s = essid;
151 char *d = escaped;
152
bb8c093b 153 if (iwl3945_is_empty_essid(essid, essid_len)) {
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154 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
155 return escaped;
156 }
157
158 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
159 while (essid_len--) {
160 if (*s == '\0') {
161 *d++ = '\\';
162 *d++ = '0';
163 s++;
164 } else
165 *d++ = *s++;
166 }
167 *d = '\0';
168 return escaped;
169}
170
bb8c093b 171static void iwl3945_print_hex_dump(int level, void *p, u32 len)
b481de9c 172{
c8b0e6e1 173#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 174 if (!(iwl3945_debug_level & level))
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175 return;
176
177 print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
178 p, len, 1);
179#endif
180}
181
182/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
183 * DMA services
184 *
185 * Theory of operation
186 *
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187 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
188 * of buffer descriptors, each of which points to one or more data buffers for
189 * the device to read from or fill. Driver and device exchange status of each
190 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
191 * entries in each circular buffer, to protect against confusing empty and full
192 * queue states.
193 *
194 * The device reads or writes the data in the queues via the device's several
195 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
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196 *
197 * For Tx queue, there are low mark and high mark limits. If, after queuing
198 * the packet for Tx, free space become < low mark, Tx queue stopped. When
199 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
200 * Tx queue resumed.
201 *
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202 * The 3945 operates with six queues: One receive queue, one transmit queue
203 * (#4) for sending commands to the device firmware, and four transmit queues
204 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
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205 ***************************************************/
206
bb8c093b 207static int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 208{
fc4b6853 209 int s = q->read_ptr - q->write_ptr;
b481de9c 210
fc4b6853 211 if (q->read_ptr > q->write_ptr)
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212 s -= q->n_bd;
213
214 if (s <= 0)
215 s += q->n_window;
216 /* keep some reserve to not confuse empty and full situations */
217 s -= 2;
218 if (s < 0)
219 s = 0;
220 return s;
221}
222
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223/**
224 * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning
225 * @index -- current index
226 * @n_bd -- total number of entries in queue (must be power of 2)
227 */
bb8c093b 228static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
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229{
230 return ++index & (n_bd - 1);
231}
232
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233/**
234 * iwl3945_queue_dec_wrap - increment queue index, wrap back to end
235 * @index -- current index
236 * @n_bd -- total number of entries in queue (must be power of 2)
237 */
bb8c093b 238static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
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239{
240 return --index & (n_bd - 1);
241}
242
bb8c093b 243static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 244{
fc4b6853
TW
245 return q->write_ptr > q->read_ptr ?
246 (i >= q->read_ptr && i < q->write_ptr) :
247 !(i < q->read_ptr && i >= q->write_ptr);
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248}
249
bb8c093b 250static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 251{
6440adb5 252 /* This is for scan command, the big buffer at end of command array */
b481de9c 253 if (is_huge)
6440adb5 254 return q->n_window; /* must be power of 2 */
b481de9c 255
6440adb5 256 /* Otherwise, use normal size buffers */
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257 return index & (q->n_window - 1);
258}
259
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260/**
261 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
262 */
bb8c093b 263static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
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264 int count, int slots_num, u32 id)
265{
266 q->n_bd = count;
267 q->n_window = slots_num;
268 q->id = id;
269
bb8c093b
CH
270 /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
271 * and iwl3945_queue_dec_wrap are broken. */
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272 BUG_ON(!is_power_of_2(count));
273
274 /* slots_num must be power-of-two size, otherwise
275 * get_cmd_index is broken. */
276 BUG_ON(!is_power_of_2(slots_num));
277
278 q->low_mark = q->n_window / 4;
279 if (q->low_mark < 4)
280 q->low_mark = 4;
281
282 q->high_mark = q->n_window / 8;
283 if (q->high_mark < 2)
284 q->high_mark = 2;
285
fc4b6853 286 q->write_ptr = q->read_ptr = 0;
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287
288 return 0;
289}
290
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291/**
292 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
293 */
bb8c093b
CH
294static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
295 struct iwl3945_tx_queue *txq, u32 id)
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296{
297 struct pci_dev *dev = priv->pci_dev;
298
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299 /* Driver private data, only for Tx (not command) queues,
300 * not shared with device. */
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301 if (id != IWL_CMD_QUEUE_NUM) {
302 txq->txb = kmalloc(sizeof(txq->txb[0]) *
303 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
304 if (!txq->txb) {
01ebd063 305 IWL_ERROR("kmalloc for auxiliary BD "
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306 "structures failed\n");
307 goto error;
308 }
309 } else
310 txq->txb = NULL;
311
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312 /* Circular buffer of transmit frame descriptors (TFDs),
313 * shared with device */
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314 txq->bd = pci_alloc_consistent(dev,
315 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
316 &txq->q.dma_addr);
317
318 if (!txq->bd) {
319 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
320 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
321 goto error;
322 }
323 txq->q.id = id;
324
325 return 0;
326
327 error:
328 if (txq->txb) {
329 kfree(txq->txb);
330 txq->txb = NULL;
331 }
332
333 return -ENOMEM;
334}
335
6440adb5
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336/**
337 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
338 */
bb8c093b
CH
339int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
340 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
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341{
342 struct pci_dev *dev = priv->pci_dev;
343 int len;
344 int rc = 0;
345
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346 /*
347 * Alloc buffer array for commands (Tx or other types of commands).
348 * For the command queue (#4), allocate command space + one big
349 * command for scan, since scan command is very huge; the system will
350 * not have two scans at the same time, so only one is needed.
351 * For data Tx queues (all other queues), no super-size command
352 * space is needed.
353 */
bb8c093b 354 len = sizeof(struct iwl3945_cmd) * slots_num;
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355 if (txq_id == IWL_CMD_QUEUE_NUM)
356 len += IWL_MAX_SCAN_SIZE;
357 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
358 if (!txq->cmd)
359 return -ENOMEM;
360
6440adb5 361 /* Alloc driver data array and TFD circular buffer */
bb8c093b 362 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
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363 if (rc) {
364 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
365
366 return -ENOMEM;
367 }
368 txq->need_update = 0;
369
370 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
bb8c093b 371 * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
b481de9c 372 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
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373
374 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 375 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 376
6440adb5 377 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 378 iwl3945_hw_tx_queue_init(priv, txq);
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379
380 return 0;
381}
382
383/**
bb8c093b 384 * iwl3945_tx_queue_free - Deallocate DMA queue.
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385 * @txq: Transmit queue to deallocate.
386 *
387 * Empty queue by removing and destroying all BD's.
6440adb5
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388 * Free all buffers.
389 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 390 */
bb8c093b 391void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 392{
bb8c093b 393 struct iwl3945_queue *q = &txq->q;
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394 struct pci_dev *dev = priv->pci_dev;
395 int len;
396
397 if (q->n_bd == 0)
398 return;
399
400 /* first, empty all BD's */
fc4b6853 401 for (; q->write_ptr != q->read_ptr;
bb8c093b
CH
402 q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
403 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 404
bb8c093b 405 len = sizeof(struct iwl3945_cmd) * q->n_window;
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406 if (q->id == IWL_CMD_QUEUE_NUM)
407 len += IWL_MAX_SCAN_SIZE;
408
6440adb5 409 /* De-alloc array of command/tx buffers */
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410 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
411
6440adb5 412 /* De-alloc circular buffer of TFDs */
b481de9c 413 if (txq->q.n_bd)
bb8c093b 414 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
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415 txq->q.n_bd, txq->bd, txq->q.dma_addr);
416
6440adb5 417 /* De-alloc array of per-TFD driver data */
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418 if (txq->txb) {
419 kfree(txq->txb);
420 txq->txb = NULL;
421 }
422
6440adb5 423 /* 0-fill queue descriptor structure */
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424 memset(txq, 0, sizeof(*txq));
425}
426
bb8c093b 427const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
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428
429/*************** STATION TABLE MANAGEMENT ****
9fbab516 430 * mac80211 should be examined to determine if sta_info is duplicating
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431 * the functionality provided here
432 */
433
434/**************************************************************/
01ebd063 435#if 0 /* temporary disable till we add real remove station */
6440adb5
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436/**
437 * iwl3945_remove_station - Remove driver's knowledge of station.
438 *
439 * NOTE: This does not remove station from device's station table.
440 */
bb8c093b 441static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
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442{
443 int index = IWL_INVALID_STATION;
444 int i;
445 unsigned long flags;
446
447 spin_lock_irqsave(&priv->sta_lock, flags);
448
449 if (is_ap)
450 index = IWL_AP_ID;
451 else if (is_broadcast_ether_addr(addr))
452 index = priv->hw_setting.bcast_sta_id;
453 else
454 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
455 if (priv->stations[i].used &&
456 !compare_ether_addr(priv->stations[i].sta.sta.addr,
457 addr)) {
458 index = i;
459 break;
460 }
461
462 if (unlikely(index == IWL_INVALID_STATION))
463 goto out;
464
465 if (priv->stations[index].used) {
466 priv->stations[index].used = 0;
467 priv->num_stations--;
468 }
469
470 BUG_ON(priv->num_stations < 0);
471
472out:
473 spin_unlock_irqrestore(&priv->sta_lock, flags);
474 return 0;
475}
556f8db7 476#endif
6440adb5
CB
477
478/**
479 * iwl3945_clear_stations_table - Clear the driver's station table
480 *
481 * NOTE: This does not clear or otherwise alter the device's station table.
482 */
bb8c093b 483static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
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484{
485 unsigned long flags;
486
487 spin_lock_irqsave(&priv->sta_lock, flags);
488
489 priv->num_stations = 0;
490 memset(priv->stations, 0, sizeof(priv->stations));
491
492 spin_unlock_irqrestore(&priv->sta_lock, flags);
493}
494
6440adb5
CB
495/**
496 * iwl3945_add_station - Add station to station tables in driver and device
497 */
bb8c093b 498u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
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499{
500 int i;
501 int index = IWL_INVALID_STATION;
bb8c093b 502 struct iwl3945_station_entry *station;
b481de9c 503 unsigned long flags_spin;
0795af57 504 DECLARE_MAC_BUF(mac);
c14c521e 505 u8 rate;
b481de9c
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506
507 spin_lock_irqsave(&priv->sta_lock, flags_spin);
508 if (is_ap)
509 index = IWL_AP_ID;
510 else if (is_broadcast_ether_addr(addr))
511 index = priv->hw_setting.bcast_sta_id;
512 else
513 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
514 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
515 addr)) {
516 index = i;
517 break;
518 }
519
520 if (!priv->stations[i].used &&
521 index == IWL_INVALID_STATION)
522 index = i;
523 }
524
01ebd063 525 /* These two conditions has the same outcome but keep them separate
b481de9c
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526 since they have different meaning */
527 if (unlikely(index == IWL_INVALID_STATION)) {
528 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
529 return index;
530 }
531
532 if (priv->stations[index].used &&
533 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
534 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
535 return index;
536 }
537
0795af57 538 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
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539 station = &priv->stations[index];
540 station->used = 1;
541 priv->num_stations++;
542
6440adb5 543 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 544 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
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545 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
546 station->sta.mode = 0;
547 station->sta.sta.sta_id = index;
548 station->sta.station_flags = 0;
549
69946333
TW
550 if (priv->phymode == MODE_IEEE80211A)
551 rate = IWL_RATE_6M_PLCP;
552 else
553 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY
554
555 /* Turn on both antennas for the station... */
556 station->sta.rate_n_flags =
bb8c093b 557 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY
558 station->current_rate.rate_n_flags =
559 le16_to_cpu(station->sta.rate_n_flags);
560
b481de9c 561 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB
562
563 /* Add station to device's station table */
bb8c093b 564 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
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565 return index;
566
567}
568
569/*************** DRIVER STATUS FUNCTIONS *****/
570
bb8c093b 571static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
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572{
573 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
574 * set but EXIT_PENDING is not */
575 return test_bit(STATUS_READY, &priv->status) &&
576 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
577 !test_bit(STATUS_EXIT_PENDING, &priv->status);
578}
579
bb8c093b 580static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY
581{
582 return test_bit(STATUS_ALIVE, &priv->status);
583}
584
bb8c093b 585static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY
586{
587 return test_bit(STATUS_INIT, &priv->status);
588}
589
bb8c093b 590static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c
ZY
591{
592 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
593 test_bit(STATUS_RF_KILL_SW, &priv->status);
594}
595
bb8c093b 596static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY
597{
598
bb8c093b 599 if (iwl3945_is_rfkill(priv))
b481de9c
ZY
600 return 0;
601
bb8c093b 602 return iwl3945_is_ready(priv);
b481de9c
ZY
603}
604
605/*************** HOST COMMAND QUEUE FUNCTIONS *****/
606
607#define IWL_CMD(x) case x : return #x
608
609static const char *get_cmd_string(u8 cmd)
610{
611 switch (cmd) {
612 IWL_CMD(REPLY_ALIVE);
613 IWL_CMD(REPLY_ERROR);
614 IWL_CMD(REPLY_RXON);
615 IWL_CMD(REPLY_RXON_ASSOC);
616 IWL_CMD(REPLY_QOS_PARAM);
617 IWL_CMD(REPLY_RXON_TIMING);
618 IWL_CMD(REPLY_ADD_STA);
619 IWL_CMD(REPLY_REMOVE_STA);
620 IWL_CMD(REPLY_REMOVE_ALL_STA);
621 IWL_CMD(REPLY_3945_RX);
622 IWL_CMD(REPLY_TX);
623 IWL_CMD(REPLY_RATE_SCALE);
624 IWL_CMD(REPLY_LEDS_CMD);
625 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
626 IWL_CMD(RADAR_NOTIFICATION);
627 IWL_CMD(REPLY_QUIET_CMD);
628 IWL_CMD(REPLY_CHANNEL_SWITCH);
629 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
630 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
631 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
632 IWL_CMD(POWER_TABLE_CMD);
633 IWL_CMD(PM_SLEEP_NOTIFICATION);
634 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
635 IWL_CMD(REPLY_SCAN_CMD);
636 IWL_CMD(REPLY_SCAN_ABORT_CMD);
637 IWL_CMD(SCAN_START_NOTIFICATION);
638 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
639 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
640 IWL_CMD(BEACON_NOTIFICATION);
641 IWL_CMD(REPLY_TX_BEACON);
642 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
643 IWL_CMD(QUIET_NOTIFICATION);
644 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
645 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
646 IWL_CMD(REPLY_BT_CONFIG);
647 IWL_CMD(REPLY_STATISTICS_CMD);
648 IWL_CMD(STATISTICS_NOTIFICATION);
649 IWL_CMD(REPLY_CARD_STATE_CMD);
650 IWL_CMD(CARD_STATE_NOTIFICATION);
651 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
652 default:
653 return "UNKNOWN";
654
655 }
656}
657
658#define HOST_COMPLETE_TIMEOUT (HZ / 2)
659
660/**
bb8c093b 661 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY
662 * @priv: device private data point
663 * @cmd: a point to the ucode command structure
664 *
665 * The function returns < 0 values to indicate the operation is
666 * failed. On success, it turns the index (> 0) of command in the
667 * command queue.
668 */
bb8c093b 669static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 670{
bb8c093b
CH
671 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
672 struct iwl3945_queue *q = &txq->q;
673 struct iwl3945_tfd_frame *tfd;
b481de9c 674 u32 *control_flags;
bb8c093b 675 struct iwl3945_cmd *out_cmd;
b481de9c
ZY
676 u32 idx;
677 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
678 dma_addr_t phys_addr;
679 int pad;
680 u16 count;
681 int ret;
682 unsigned long flags;
683
684 /* If any of the command structures end up being larger than
685 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
686 * we will need to increase the size of the TFD entries */
687 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
688 !(cmd->meta.flags & CMD_SIZE_HUGE));
689
bb8c093b 690 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY
691 IWL_ERROR("No space for Tx\n");
692 return -ENOSPC;
693 }
694
695 spin_lock_irqsave(&priv->hcmd_lock, flags);
696
fc4b6853 697 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY
698 memset(tfd, 0, sizeof(*tfd));
699
700 control_flags = (u32 *) tfd;
701
fc4b6853 702 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY
703 out_cmd = &txq->cmd[idx];
704
705 out_cmd->hdr.cmd = cmd->id;
706 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
707 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
708
709 /* At this point, the out_cmd now has all of the incoming cmd
710 * information */
711
712 out_cmd->hdr.flags = 0;
713 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 714 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY
715 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
716 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
717
718 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH
719 offsetof(struct iwl3945_cmd, hdr);
720 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY
721
722 pad = U32_PAD(cmd->len);
723 count = TFD_CTL_COUNT_GET(*control_flags);
724 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
725
726 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
727 "%d bytes at %d[%d]:%d\n",
728 get_cmd_string(out_cmd->hdr.cmd),
729 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 730 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY
731
732 txq->need_update = 1;
6440adb5
CB
733
734 /* Increment and update queue's write index */
bb8c093b
CH
735 q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
736 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
737
738 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
739 return ret ? ret : idx;
740}
741
bb8c093b 742static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY
743{
744 int ret;
745
746 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
747
748 /* An asynchronous command can not expect an SKB to be set. */
749 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
750
751 /* An asynchronous command MUST have a callback. */
752 BUG_ON(!cmd->meta.u.callback);
753
754 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
755 return -EBUSY;
756
bb8c093b 757 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 758 if (ret < 0) {
bb8c093b 759 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY
760 get_cmd_string(cmd->id), ret);
761 return ret;
762 }
763 return 0;
764}
765
bb8c093b 766static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY
767{
768 int cmd_idx;
769 int ret;
770 static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
771
772 BUG_ON(cmd->meta.flags & CMD_ASYNC);
773
774 /* A synchronous command can not have a callback set. */
775 BUG_ON(cmd->meta.u.callback != NULL);
776
777 if (atomic_xchg(&entry, 1)) {
778 IWL_ERROR("Error sending %s: Already sending a host command\n",
779 get_cmd_string(cmd->id));
780 return -EBUSY;
781 }
782
783 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
784
785 if (cmd->meta.flags & CMD_WANT_SKB)
786 cmd->meta.source = &cmd->meta;
787
bb8c093b 788 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY
789 if (cmd_idx < 0) {
790 ret = cmd_idx;
bb8c093b 791 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY
792 get_cmd_string(cmd->id), ret);
793 goto out;
794 }
795
796 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
797 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
798 HOST_COMPLETE_TIMEOUT);
799 if (!ret) {
800 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
801 IWL_ERROR("Error sending %s: time out after %dms.\n",
802 get_cmd_string(cmd->id),
803 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
804
805 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
806 ret = -ETIMEDOUT;
807 goto cancel;
808 }
809 }
810
811 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
812 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
813 get_cmd_string(cmd->id));
814 ret = -ECANCELED;
815 goto fail;
816 }
817 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
818 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
819 get_cmd_string(cmd->id));
820 ret = -EIO;
821 goto fail;
822 }
823 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
824 IWL_ERROR("Error: Response NULL in '%s'\n",
825 get_cmd_string(cmd->id));
826 ret = -EIO;
827 goto out;
828 }
829
830 ret = 0;
831 goto out;
832
833cancel:
834 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 835 struct iwl3945_cmd *qcmd;
b481de9c
ZY
836
837 /* Cancel the CMD_WANT_SKB flag for the cmd in the
838 * TX cmd queue. Otherwise in case the cmd comes
839 * in later, it will possibly set an invalid
840 * address (cmd->meta.source). */
841 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
842 qcmd->meta.flags &= ~CMD_WANT_SKB;
843 }
844fail:
845 if (cmd->meta.u.skb) {
846 dev_kfree_skb_any(cmd->meta.u.skb);
847 cmd->meta.u.skb = NULL;
848 }
849out:
850 atomic_set(&entry, 0);
851 return ret;
852}
853
bb8c093b 854int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 855{
b481de9c 856 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 857 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 858
bb8c093b 859 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY
860}
861
bb8c093b 862int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 863{
bb8c093b 864 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
865 .id = id,
866 .len = len,
867 .data = data,
868 };
869
bb8c093b 870 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
871}
872
bb8c093b 873static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 874{
bb8c093b 875 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
876 .id = id,
877 .len = sizeof(val),
878 .data = &val,
879 };
880
bb8c093b 881 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
882}
883
bb8c093b 884int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 885{
bb8c093b 886 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY
887}
888
b481de9c 889/**
bb8c093b 890 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
b481de9c
ZY
891 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
892 * @channel: Any channel valid for the requested phymode
893
894 * In addition to setting the staging RXON, priv->phymode is also set.
895 *
896 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
897 * in the staging RXON flag structure based on the phymode
898 */
bb8c093b 899static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv, u8 phymode, u16 channel)
b481de9c 900{
bb8c093b 901 if (!iwl3945_get_channel_info(priv, phymode, channel)) {
b481de9c
ZY
902 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
903 channel, phymode);
904 return -EINVAL;
905 }
906
907 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
908 (priv->phymode == phymode))
909 return 0;
910
911 priv->staging_rxon.channel = cpu_to_le16(channel);
912 if (phymode == MODE_IEEE80211A)
913 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
914 else
915 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
916
917 priv->phymode = phymode;
918
919 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, phymode);
920
921 return 0;
922}
923
924/**
bb8c093b 925 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY
926 *
927 * NOTE: This is really only useful during development and can eventually
928 * be #ifdef'd out once the driver is stable and folks aren't actively
929 * making changes
930 */
bb8c093b 931static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY
932{
933 int error = 0;
934 int counter = 1;
935
936 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
937 error |= le32_to_cpu(rxon->flags &
938 (RXON_FLG_TGJ_NARROW_BAND_MSK |
939 RXON_FLG_RADAR_DETECT_MSK));
940 if (error)
941 IWL_WARNING("check 24G fields %d | %d\n",
942 counter++, error);
943 } else {
944 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
945 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
946 if (error)
947 IWL_WARNING("check 52 fields %d | %d\n",
948 counter++, error);
949 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
950 if (error)
951 IWL_WARNING("check 52 CCK %d | %d\n",
952 counter++, error);
953 }
954 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
955 if (error)
956 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
957
958 /* make sure basic rates 6Mbps and 1Mbps are supported */
959 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
960 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
961 if (error)
962 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
963
964 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
965 if (error)
966 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
967
968 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
969 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
970 if (error)
971 IWL_WARNING("check CCK and short slot %d | %d\n",
972 counter++, error);
973
974 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
975 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
976 if (error)
977 IWL_WARNING("check CCK & auto detect %d | %d\n",
978 counter++, error);
979
980 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
981 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
982 if (error)
983 IWL_WARNING("check TGG and auto detect %d | %d\n",
984 counter++, error);
985
986 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
987 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
988 RXON_FLG_ANT_A_MSK)) == 0);
989 if (error)
990 IWL_WARNING("check antenna %d %d\n", counter++, error);
991
992 if (error)
993 IWL_WARNING("Tuning to channel %d\n",
994 le16_to_cpu(rxon->channel));
995
996 if (error) {
bb8c093b 997 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY
998 return -1;
999 }
1000 return 0;
1001}
1002
1003/**
9fbab516 1004 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 1005 * @priv: staging_rxon is compared to active_rxon
b481de9c 1006 *
9fbab516
BC
1007 * If the RXON structure is changing enough to require a new tune,
1008 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
1009 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 1010 */
bb8c093b 1011static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY
1012{
1013
1014 /* These items are only settable from the full RXON command */
1015 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
1016 compare_ether_addr(priv->staging_rxon.bssid_addr,
1017 priv->active_rxon.bssid_addr) ||
1018 compare_ether_addr(priv->staging_rxon.node_addr,
1019 priv->active_rxon.node_addr) ||
1020 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
1021 priv->active_rxon.wlap_bssid_addr) ||
1022 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
1023 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
1024 (priv->staging_rxon.air_propagation !=
1025 priv->active_rxon.air_propagation) ||
1026 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
1027 return 1;
1028
1029 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
1030 * be updated with the RXON_ASSOC command -- however only some
1031 * flag transitions are allowed using RXON_ASSOC */
1032
1033 /* Check if we are not switching bands */
1034 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
1035 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
1036 return 1;
1037
1038 /* Check if we are switching association toggle */
1039 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1040 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1041 return 1;
1042
1043 return 0;
1044}
1045
bb8c093b 1046static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY
1047{
1048 int rc = 0;
bb8c093b
CH
1049 struct iwl3945_rx_packet *res = NULL;
1050 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1051 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
1052 .id = REPLY_RXON_ASSOC,
1053 .len = sizeof(rxon_assoc),
1054 .meta.flags = CMD_WANT_SKB,
1055 .data = &rxon_assoc,
1056 };
bb8c093b
CH
1057 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1058 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY
1059
1060 if ((rxon1->flags == rxon2->flags) &&
1061 (rxon1->filter_flags == rxon2->filter_flags) &&
1062 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1063 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1064 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1065 return 0;
1066 }
1067
1068 rxon_assoc.flags = priv->staging_rxon.flags;
1069 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1070 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1071 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1072 rxon_assoc.reserved = 0;
1073
bb8c093b 1074 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1075 if (rc)
1076 return rc;
1077
bb8c093b 1078 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1079 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1080 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1081 rc = -EIO;
1082 }
1083
1084 priv->alloc_rxb_skb--;
1085 dev_kfree_skb_any(cmd.meta.u.skb);
1086
1087 return rc;
1088}
1089
1090/**
bb8c093b 1091 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1092 *
01ebd063 1093 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY
1094 * the active_rxon structure is updated with the new data. This
1095 * function correctly transitions out of the RXON_ASSOC_MSK state if
1096 * a HW tune is required based on the RXON structure changes.
1097 */
bb8c093b 1098static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY
1099{
1100 /* cast away the const for active_rxon in this function */
bb8c093b 1101 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1102 int rc = 0;
0795af57 1103 DECLARE_MAC_BUF(mac);
b481de9c 1104
bb8c093b 1105 if (!iwl3945_is_alive(priv))
b481de9c
ZY
1106 return -1;
1107
1108 /* always get timestamp with Rx frame */
1109 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1110
1111 /* select antenna */
1112 priv->staging_rxon.flags &=
1113 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1114 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1115
bb8c093b 1116 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY
1117 if (rc) {
1118 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1119 return -EINVAL;
1120 }
1121
1122 /* If we don't need to send a full RXON, we can use
bb8c093b 1123 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1124 * and other flags for the current radio configuration. */
bb8c093b
CH
1125 if (!iwl3945_full_rxon_required(priv)) {
1126 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY
1127 if (rc) {
1128 IWL_ERROR("Error setting RXON_ASSOC "
1129 "configuration (%d).\n", rc);
1130 return rc;
1131 }
1132
1133 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1134
1135 return 0;
1136 }
1137
1138 /* If we are currently associated and the new config requires
1139 * an RXON_ASSOC and the new config wants the associated mask enabled,
1140 * we must clear the associated from the active configuration
1141 * before we apply the new config */
bb8c093b 1142 if (iwl3945_is_associated(priv) &&
b481de9c
ZY
1143 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1144 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1145 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1146
bb8c093b
CH
1147 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1148 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY
1149 &priv->active_rxon);
1150
1151 /* If the mask clearing failed then we set
1152 * active_rxon back to what it was previously */
1153 if (rc) {
1154 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1155 IWL_ERROR("Error clearing ASSOC_MSK on current "
1156 "configuration (%d).\n", rc);
1157 return rc;
1158 }
b481de9c
ZY
1159 }
1160
1161 IWL_DEBUG_INFO("Sending RXON\n"
1162 "* with%s RXON_FILTER_ASSOC_MSK\n"
1163 "* channel = %d\n"
0795af57 1164 "* bssid = %s\n",
b481de9c
ZY
1165 ((priv->staging_rxon.filter_flags &
1166 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1167 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1168 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY
1169
1170 /* Apply the new configuration */
bb8c093b
CH
1171 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1172 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY
1173 if (rc) {
1174 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1175 return rc;
1176 }
1177
1178 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1179
bb8c093b 1180 iwl3945_clear_stations_table(priv);
556f8db7 1181
b481de9c
ZY
1182 /* If we issue a new RXON command which required a tune then we must
1183 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1184 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY
1185 if (rc) {
1186 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1187 return rc;
1188 }
1189
1190 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1191 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY
1192 IWL_INVALID_STATION) {
1193 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1194 return -EIO;
1195 }
1196
1197 /* If we have set the ASSOC_MSK and we are in BSS mode then
1198 * add the IWL_AP_ID to the station rate table */
bb8c093b 1199 if (iwl3945_is_associated(priv) &&
b481de9c 1200 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1201 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY
1202 == IWL_INVALID_STATION) {
1203 IWL_ERROR("Error adding AP address for transmit.\n");
1204 return -EIO;
1205 }
1206
1207 /* Init the hardware's rate fallback order based on the
1208 * phymode */
1209 rc = iwl3945_init_hw_rate_table(priv);
1210 if (rc) {
1211 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1212 return -EIO;
1213 }
1214
1215 return 0;
1216}
1217
bb8c093b 1218static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1219{
bb8c093b 1220 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY
1221 .flags = 3,
1222 .lead_time = 0xAA,
1223 .max_kill = 1,
1224 .kill_ack_mask = 0,
1225 .kill_cts_mask = 0,
1226 };
1227
bb8c093b
CH
1228 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1229 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY
1230}
1231
bb8c093b 1232static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY
1233{
1234 int rc = 0;
bb8c093b
CH
1235 struct iwl3945_rx_packet *res;
1236 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
1237 .id = REPLY_SCAN_ABORT_CMD,
1238 .meta.flags = CMD_WANT_SKB,
1239 };
1240
1241 /* If there isn't a scan actively going on in the hardware
1242 * then we are in between scan bands and not actually
1243 * actively scanning, so don't send the abort command */
1244 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1245 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1246 return 0;
1247 }
1248
bb8c093b 1249 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1250 if (rc) {
1251 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1252 return rc;
1253 }
1254
bb8c093b 1255 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1256 if (res->u.status != CAN_ABORT_STATUS) {
1257 /* The scan abort will return 1 for success or
1258 * 2 for "failure". A failure condition can be
1259 * due to simply not being in an active scan which
1260 * can occur if we send the scan abort before we
1261 * the microcode has notified us that a scan is
1262 * completed. */
1263 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1264 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1265 clear_bit(STATUS_SCAN_HW, &priv->status);
1266 }
1267
1268 dev_kfree_skb_any(cmd.meta.u.skb);
1269
1270 return rc;
1271}
1272
bb8c093b
CH
1273static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1274 struct iwl3945_cmd *cmd,
b481de9c
ZY
1275 struct sk_buff *skb)
1276{
1277 return 1;
1278}
1279
1280/*
1281 * CARD_STATE_CMD
1282 *
9fbab516 1283 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY
1284 *
1285 * When in the 'enable' state the card operates as normal.
1286 * When in the 'disable' state, the card enters into a low power mode.
1287 * When in the 'halt' state, the card is shut down and must be fully
1288 * restarted to come back on.
1289 */
bb8c093b 1290static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1291{
bb8c093b 1292 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
1293 .id = REPLY_CARD_STATE_CMD,
1294 .len = sizeof(u32),
1295 .data = &flags,
1296 .meta.flags = meta_flag,
1297 };
1298
1299 if (meta_flag & CMD_ASYNC)
bb8c093b 1300 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1301
bb8c093b 1302 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY
1303}
1304
bb8c093b
CH
1305static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1306 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1307{
bb8c093b 1308 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY
1309
1310 if (!skb) {
1311 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1312 return 1;
1313 }
1314
bb8c093b 1315 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY
1316 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1317 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1318 res->hdr.flags);
1319 return 1;
1320 }
1321
1322 switch (res->u.add_sta.status) {
1323 case ADD_STA_SUCCESS_MSK:
1324 break;
1325 default:
1326 break;
1327 }
1328
1329 /* We didn't cache the SKB; let the caller free it */
1330 return 1;
1331}
1332
bb8c093b
CH
1333int iwl3945_send_add_station(struct iwl3945_priv *priv,
1334 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1335{
bb8c093b 1336 struct iwl3945_rx_packet *res = NULL;
b481de9c 1337 int rc = 0;
bb8c093b 1338 struct iwl3945_host_cmd cmd = {
b481de9c 1339 .id = REPLY_ADD_STA,
bb8c093b 1340 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY
1341 .meta.flags = flags,
1342 .data = sta,
1343 };
1344
1345 if (flags & CMD_ASYNC)
bb8c093b 1346 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY
1347 else
1348 cmd.meta.flags |= CMD_WANT_SKB;
1349
bb8c093b 1350 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY
1351
1352 if (rc || (flags & CMD_ASYNC))
1353 return rc;
1354
bb8c093b 1355 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1356 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1357 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1358 res->hdr.flags);
1359 rc = -EIO;
1360 }
1361
1362 if (rc == 0) {
1363 switch (res->u.add_sta.status) {
1364 case ADD_STA_SUCCESS_MSK:
1365 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1366 break;
1367 default:
1368 rc = -EIO;
1369 IWL_WARNING("REPLY_ADD_STA failed\n");
1370 break;
1371 }
1372 }
1373
1374 priv->alloc_rxb_skb--;
1375 dev_kfree_skb_any(cmd.meta.u.skb);
1376
1377 return rc;
1378}
1379
bb8c093b 1380static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY
1381 struct ieee80211_key_conf *keyconf,
1382 u8 sta_id)
1383{
1384 unsigned long flags;
1385 __le16 key_flags = 0;
1386
1387 switch (keyconf->alg) {
1388 case ALG_CCMP:
1389 key_flags |= STA_KEY_FLG_CCMP;
1390 key_flags |= cpu_to_le16(
1391 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1392 key_flags &= ~STA_KEY_FLG_INVALID;
1393 break;
1394 case ALG_TKIP:
1395 case ALG_WEP:
b481de9c
ZY
1396 default:
1397 return -EINVAL;
1398 }
1399 spin_lock_irqsave(&priv->sta_lock, flags);
1400 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1401 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1402 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1403 keyconf->keylen);
1404
1405 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1406 keyconf->keylen);
1407 priv->stations[sta_id].sta.key.key_flags = key_flags;
1408 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1409 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1410
1411 spin_unlock_irqrestore(&priv->sta_lock, flags);
1412
1413 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1414 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
1415 return 0;
1416}
1417
bb8c093b 1418static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY
1419{
1420 unsigned long flags;
1421
1422 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH
1423 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1424 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY
1425 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1426 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1427 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1428 spin_unlock_irqrestore(&priv->sta_lock, flags);
1429
1430 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1431 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
1432 return 0;
1433}
1434
bb8c093b 1435static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY
1436{
1437 struct list_head *element;
1438
1439 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1440 priv->frames_count);
1441
1442 while (!list_empty(&priv->free_frames)) {
1443 element = priv->free_frames.next;
1444 list_del(element);
bb8c093b 1445 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY
1446 priv->frames_count--;
1447 }
1448
1449 if (priv->frames_count) {
1450 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1451 priv->frames_count);
1452 priv->frames_count = 0;
1453 }
1454}
1455
bb8c093b 1456static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1457{
bb8c093b 1458 struct iwl3945_frame *frame;
b481de9c
ZY
1459 struct list_head *element;
1460 if (list_empty(&priv->free_frames)) {
1461 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1462 if (!frame) {
1463 IWL_ERROR("Could not allocate frame!\n");
1464 return NULL;
1465 }
1466
1467 priv->frames_count++;
1468 return frame;
1469 }
1470
1471 element = priv->free_frames.next;
1472 list_del(element);
bb8c093b 1473 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY
1474}
1475
bb8c093b 1476static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY
1477{
1478 memset(frame, 0, sizeof(*frame));
1479 list_add(&frame->list, &priv->free_frames);
1480}
1481
bb8c093b 1482unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY
1483 struct ieee80211_hdr *hdr,
1484 const u8 *dest, int left)
1485{
1486
bb8c093b 1487 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY
1488 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1489 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1490 return 0;
1491
1492 if (priv->ibss_beacon->len > left)
1493 return 0;
1494
1495 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1496
1497 return priv->ibss_beacon->len;
1498}
1499
bb8c093b 1500static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY
1501{
1502 u8 i;
1503
1504 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1505 i = iwl3945_rates[i].next_ieee) {
b481de9c 1506 if (rate_mask & (1 << i))
bb8c093b 1507 return iwl3945_rates[i].plcp;
b481de9c
ZY
1508 }
1509
1510 return IWL_RATE_INVALID;
1511}
1512
bb8c093b 1513static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1514{
bb8c093b 1515 struct iwl3945_frame *frame;
b481de9c
ZY
1516 unsigned int frame_size;
1517 int rc;
1518 u8 rate;
1519
bb8c093b 1520 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
1521
1522 if (!frame) {
1523 IWL_ERROR("Could not obtain free frame buffer for beacon "
1524 "command.\n");
1525 return -ENOMEM;
1526 }
1527
1528 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1529 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY
1530 0xFF0);
1531 if (rate == IWL_INVALID_RATE)
1532 rate = IWL_RATE_6M_PLCP;
1533 } else {
bb8c093b 1534 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY
1535 if (rate == IWL_INVALID_RATE)
1536 rate = IWL_RATE_1M_PLCP;
1537 }
1538
bb8c093b 1539 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1540
bb8c093b 1541 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
1542 &frame->u.cmd[0]);
1543
bb8c093b 1544 iwl3945_free_frame(priv, frame);
b481de9c
ZY
1545
1546 return rc;
1547}
1548
1549/******************************************************************************
1550 *
1551 * EEPROM related functions
1552 *
1553 ******************************************************************************/
1554
bb8c093b 1555static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY
1556{
1557 memcpy(mac, priv->eeprom.mac_address, 6);
1558}
1559
74a3a250
RC
1560/*
1561 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1562 * embedded controller) as EEPROM reader; each read is a series of pulses
1563 * to/from the EEPROM chip, not a single event, so even reads could conflict
1564 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1565 * simply claims ownership, which should be safe when this function is called
1566 * (i.e. before loading uCode!).
1567 */
1568static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1569{
1570 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1571 return 0;
1572}
1573
b481de9c 1574/**
bb8c093b 1575 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1576 *
6440adb5 1577 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY
1578 *
1579 * NOTE: This routine uses the non-debug IO access functions.
1580 */
bb8c093b 1581int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1582{
0e5ce1f3 1583 __le16 *e = (__le16 *)&priv->eeprom;
bb8c093b 1584 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY
1585 u32 r;
1586 int sz = sizeof(priv->eeprom);
1587 int rc;
1588 int i;
1589 u16 addr;
1590
1591 /* The EEPROM structure has several padding buffers within it
1592 * and when adding new EEPROM maps is subject to programmer errors
1593 * which may be very difficult to identify without explicitly
1594 * checking the resulting size of the eeprom map. */
1595 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1596
1597 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1598 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1599 return -ENOENT;
1600 }
1601
6440adb5 1602 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1603 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1604 if (rc < 0) {
91e17473 1605 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY
1606 return -ENOENT;
1607 }
1608
1609 /* eeprom is an array of 16bit values */
1610 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH
1611 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1612 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY
1613
1614 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1615 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1616 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY
1617 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1618 break;
1619 udelay(IWL_EEPROM_ACCESS_DELAY);
1620 }
1621
1622 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1623 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1624 return -ETIMEDOUT;
1625 }
0e5ce1f3 1626 e[addr / 2] = cpu_to_le16(r >> 16);
b481de9c
ZY
1627 }
1628
1629 return 0;
1630}
1631
1632/******************************************************************************
1633 *
1634 * Misc. internal state and helper functions
1635 *
1636 ******************************************************************************/
c8b0e6e1 1637#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
1638
1639/**
bb8c093b 1640 * iwl3945_report_frame - dump frame to syslog during debug sessions
b481de9c 1641 *
9fbab516 1642 * You may hack this function to show different aspects of received frames,
b481de9c
ZY
1643 * including selective frame dumps.
1644 * group100 parameter selects whether to show 1 out of 100 good frames.
b481de9c 1645 */
bb8c093b
CH
1646void iwl3945_report_frame(struct iwl3945_priv *priv,
1647 struct iwl3945_rx_packet *pkt,
b481de9c
ZY
1648 struct ieee80211_hdr *header, int group100)
1649{
1650 u32 to_us;
1651 u32 print_summary = 0;
1652 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
1653 u32 hundred = 0;
1654 u32 dataframe = 0;
1655 u16 fc;
1656 u16 seq_ctl;
1657 u16 channel;
1658 u16 phy_flags;
1659 int rate_sym;
1660 u16 length;
1661 u16 status;
1662 u16 bcn_tmr;
1663 u32 tsf_low;
1664 u64 tsf;
1665 u8 rssi;
1666 u8 agc;
1667 u16 sig_avg;
1668 u16 noise_diff;
bb8c093b
CH
1669 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
1670 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
1671 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY
1672 u8 *data = IWL_RX_DATA(pkt);
1673
1674 /* MAC header */
1675 fc = le16_to_cpu(header->frame_control);
1676 seq_ctl = le16_to_cpu(header->seq_ctrl);
1677
1678 /* metadata */
1679 channel = le16_to_cpu(rx_hdr->channel);
1680 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
1681 rate_sym = rx_hdr->rate;
1682 length = le16_to_cpu(rx_hdr->len);
1683
1684 /* end-of-frame status and timestamp */
1685 status = le32_to_cpu(rx_end->status);
1686 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
1687 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
1688 tsf = le64_to_cpu(rx_end->timestamp);
1689
1690 /* signal statistics */
1691 rssi = rx_stats->rssi;
1692 agc = rx_stats->agc;
1693 sig_avg = le16_to_cpu(rx_stats->sig_avg);
1694 noise_diff = le16_to_cpu(rx_stats->noise_diff);
1695
1696 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
1697
1698 /* if data frame is to us and all is good,
1699 * (optionally) print summary for only 1 out of every 100 */
1700 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
1701 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
1702 dataframe = 1;
1703 if (!group100)
1704 print_summary = 1; /* print each frame */
1705 else if (priv->framecnt_to_us < 100) {
1706 priv->framecnt_to_us++;
1707 print_summary = 0;
1708 } else {
1709 priv->framecnt_to_us = 0;
1710 print_summary = 1;
1711 hundred = 1;
1712 }
1713 } else {
1714 /* print summary for all other frames */
1715 print_summary = 1;
1716 }
1717
1718 if (print_summary) {
1719 char *title;
1720 u32 rate;
1721
1722 if (hundred)
1723 title = "100Frames";
1724 else if (fc & IEEE80211_FCTL_RETRY)
1725 title = "Retry";
1726 else if (ieee80211_is_assoc_response(fc))
1727 title = "AscRsp";
1728 else if (ieee80211_is_reassoc_response(fc))
1729 title = "RasRsp";
1730 else if (ieee80211_is_probe_response(fc)) {
1731 title = "PrbRsp";
1732 print_dump = 1; /* dump frame contents */
1733 } else if (ieee80211_is_beacon(fc)) {
1734 title = "Beacon";
1735 print_dump = 1; /* dump frame contents */
1736 } else if (ieee80211_is_atim(fc))
1737 title = "ATIM";
1738 else if (ieee80211_is_auth(fc))
1739 title = "Auth";
1740 else if (ieee80211_is_deauth(fc))
1741 title = "DeAuth";
1742 else if (ieee80211_is_disassoc(fc))
1743 title = "DisAssoc";
1744 else
1745 title = "Frame";
1746
bb8c093b 1747 rate = iwl3945_rate_index_from_plcp(rate_sym);
b481de9c
ZY
1748 if (rate == -1)
1749 rate = 0;
1750 else
bb8c093b 1751 rate = iwl3945_rates[rate].ieee / 2;
b481de9c
ZY
1752
1753 /* print frame summary.
1754 * MAC addresses show just the last byte (for brevity),
1755 * but you can hack it to show more, if you'd like to. */
1756 if (dataframe)
1757 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
1758 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
1759 title, fc, header->addr1[5],
1760 length, rssi, channel, rate);
1761 else {
1762 /* src/dst addresses assume managed mode */
1763 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
1764 "src=0x%02x, rssi=%u, tim=%lu usec, "
1765 "phy=0x%02x, chnl=%d\n",
1766 title, fc, header->addr1[5],
1767 header->addr3[5], rssi,
1768 tsf_low - priv->scan_start_tsf,
1769 phy_flags, channel);
1770 }
1771 }
1772 if (print_dump)
bb8c093b 1773 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
b481de9c
ZY
1774}
1775#endif
1776
bb8c093b 1777static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY
1778{
1779 if (priv->hw_setting.shared_virt)
1780 pci_free_consistent(priv->pci_dev,
bb8c093b 1781 sizeof(struct iwl3945_shared),
b481de9c
ZY
1782 priv->hw_setting.shared_virt,
1783 priv->hw_setting.shared_phys);
1784}
1785
1786/**
bb8c093b 1787 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY
1788 *
1789 * return : set the bit for each supported rate insert in ie
1790 */
bb8c093b 1791static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1792 u16 basic_rate, int *left)
b481de9c
ZY
1793{
1794 u16 ret_rates = 0, bit;
1795 int i;
c7c46676
TW
1796 u8 *cnt = ie;
1797 u8 *rates = ie + 1;
b481de9c
ZY
1798
1799 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1800 if (bit & supported_rate) {
1801 ret_rates |= bit;
bb8c093b 1802 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW
1803 ((bit & basic_rate) ? 0x80 : 0x00);
1804 (*cnt)++;
1805 (*left)--;
1806 if ((*left <= 0) ||
1807 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY
1808 break;
1809 }
1810 }
1811
1812 return ret_rates;
1813}
1814
1815/**
bb8c093b 1816 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1817 */
bb8c093b 1818static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY
1819 struct ieee80211_mgmt *frame,
1820 int left, int is_direct)
1821{
1822 int len = 0;
1823 u8 *pos = NULL;
c7c46676 1824 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY
1825
1826 /* Make sure there is enough space for the probe request,
1827 * two mandatory IEs and the data */
1828 left -= 24;
1829 if (left < 0)
1830 return 0;
1831 len += 24;
1832
1833 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1834 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1835 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1836 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY
1837 frame->seq_ctrl = 0;
1838
1839 /* fill in our indirect SSID IE */
1840 /* ...next IE... */
1841
1842 left -= 2;
1843 if (left < 0)
1844 return 0;
1845 len += 2;
1846 pos = &(frame->u.probe_req.variable[0]);
1847 *pos++ = WLAN_EID_SSID;
1848 *pos++ = 0;
1849
1850 /* fill in our direct SSID IE... */
1851 if (is_direct) {
1852 /* ...next IE... */
1853 left -= 2 + priv->essid_len;
1854 if (left < 0)
1855 return 0;
1856 /* ... fill it in... */
1857 *pos++ = WLAN_EID_SSID;
1858 *pos++ = priv->essid_len;
1859 memcpy(pos, priv->essid, priv->essid_len);
1860 pos += priv->essid_len;
1861 len += 2 + priv->essid_len;
1862 }
1863
1864 /* fill in supported rate */
1865 /* ...next IE... */
1866 left -= 2;
1867 if (left < 0)
1868 return 0;
c7c46676 1869
b481de9c
ZY
1870 /* ... fill it in... */
1871 *pos++ = WLAN_EID_SUPP_RATES;
1872 *pos = 0;
c7c46676
TW
1873
1874 priv->active_rate = priv->rates_mask;
1875 active_rates = priv->active_rate;
b481de9c
ZY
1876 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1877
c7c46676 1878 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1879 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW
1880 priv->active_rate_basic, &left);
1881 active_rates &= ~ret_rates;
1882
bb8c093b 1883 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW
1884 priv->active_rate_basic, &left);
1885 active_rates &= ~ret_rates;
1886
b481de9c
ZY
1887 len += 2 + *pos;
1888 pos += (*pos) + 1;
c7c46676 1889 if (active_rates == 0)
b481de9c
ZY
1890 goto fill_end;
1891
1892 /* fill in supported extended rate */
1893 /* ...next IE... */
1894 left -= 2;
1895 if (left < 0)
1896 return 0;
1897 /* ... fill it in... */
1898 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1899 *pos = 0;
bb8c093b 1900 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1901 priv->active_rate_basic, &left);
b481de9c
ZY
1902 if (*pos > 0)
1903 len += 2 + *pos;
1904
1905 fill_end:
1906 return (u16)len;
1907}
1908
1909/*
1910 * QoS support
1911*/
c8b0e6e1 1912#ifdef CONFIG_IWL3945_QOS
bb8c093b
CH
1913static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1914 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY
1915{
1916
bb8c093b
CH
1917 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1918 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY
1919}
1920
bb8c093b 1921static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY
1922{
1923 u16 cw_min = 15;
1924 u16 cw_max = 1023;
1925 u8 aifs = 2;
1926 u8 is_legacy = 0;
1927 unsigned long flags;
1928 int i;
1929
1930 spin_lock_irqsave(&priv->lock, flags);
1931 priv->qos_data.qos_active = 0;
1932
1933 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1934 if (priv->qos_data.qos_enable)
1935 priv->qos_data.qos_active = 1;
1936 if (!(priv->active_rate & 0xfff0)) {
1937 cw_min = 31;
1938 is_legacy = 1;
1939 }
1940 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1941 if (priv->qos_data.qos_enable)
1942 priv->qos_data.qos_active = 1;
1943 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1944 cw_min = 31;
1945 is_legacy = 1;
1946 }
1947
1948 if (priv->qos_data.qos_active)
1949 aifs = 3;
1950
1951 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1952 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1953 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1954 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1955 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1956
1957 if (priv->qos_data.qos_active) {
1958 i = 1;
1959 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1960 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1961 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1962 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1963 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1964
1965 i = 2;
1966 priv->qos_data.def_qos_parm.ac[i].cw_min =
1967 cpu_to_le16((cw_min + 1) / 2 - 1);
1968 priv->qos_data.def_qos_parm.ac[i].cw_max =
1969 cpu_to_le16(cw_max);
1970 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1971 if (is_legacy)
1972 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1973 cpu_to_le16(6016);
1974 else
1975 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1976 cpu_to_le16(3008);
1977 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1978
1979 i = 3;
1980 priv->qos_data.def_qos_parm.ac[i].cw_min =
1981 cpu_to_le16((cw_min + 1) / 4 - 1);
1982 priv->qos_data.def_qos_parm.ac[i].cw_max =
1983 cpu_to_le16((cw_max + 1) / 2 - 1);
1984 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1985 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1986 if (is_legacy)
1987 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1988 cpu_to_le16(3264);
1989 else
1990 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1991 cpu_to_le16(1504);
1992 } else {
1993 for (i = 1; i < 4; i++) {
1994 priv->qos_data.def_qos_parm.ac[i].cw_min =
1995 cpu_to_le16(cw_min);
1996 priv->qos_data.def_qos_parm.ac[i].cw_max =
1997 cpu_to_le16(cw_max);
1998 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1999 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
2000 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
2001 }
2002 }
2003 IWL_DEBUG_QOS("set QoS to default \n");
2004
2005 spin_unlock_irqrestore(&priv->lock, flags);
2006}
2007
bb8c093b 2008static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY
2009{
2010 unsigned long flags;
2011
b481de9c
ZY
2012 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2013 return;
2014
2015 if (!priv->qos_data.qos_enable)
2016 return;
2017
2018 spin_lock_irqsave(&priv->lock, flags);
2019 priv->qos_data.def_qos_parm.qos_flags = 0;
2020
2021 if (priv->qos_data.qos_cap.q_AP.queue_request &&
2022 !priv->qos_data.qos_cap.q_AP.txop_request)
2023 priv->qos_data.def_qos_parm.qos_flags |=
2024 QOS_PARAM_FLG_TXOP_TYPE_MSK;
2025
2026 if (priv->qos_data.qos_active)
2027 priv->qos_data.def_qos_parm.qos_flags |=
2028 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
2029
2030 spin_unlock_irqrestore(&priv->lock, flags);
2031
bb8c093b 2032 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY
2033 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
2034 priv->qos_data.qos_active);
2035
bb8c093b 2036 iwl3945_send_qos_params_command(priv,
b481de9c
ZY
2037 &(priv->qos_data.def_qos_parm));
2038 }
2039}
2040
c8b0e6e1 2041#endif /* CONFIG_IWL3945_QOS */
b481de9c
ZY
2042/*
2043 * Power management (not Tx power!) functions
2044 */
2045#define MSEC_TO_USEC 1024
2046
2047#define NOSLP __constant_cpu_to_le32(0)
2048#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
2049#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
2050#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
2051 __constant_cpu_to_le32(X1), \
2052 __constant_cpu_to_le32(X2), \
2053 __constant_cpu_to_le32(X3), \
2054 __constant_cpu_to_le32(X4)}
2055
2056
2057/* default power management (not Tx power) table values */
2058/* for tim 0-10 */
bb8c093b 2059static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY
2060 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2061 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
2062 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
2063 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
2064 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
2065 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
2066};
2067
2068/* for tim > 10 */
bb8c093b 2069static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY
2070 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2071 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
2072 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
2073 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
2074 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
2075 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
2076 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
2077 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
2078 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
2079 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
2080};
2081
bb8c093b 2082int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY
2083{
2084 int rc = 0, i;
bb8c093b
CH
2085 struct iwl3945_power_mgr *pow_data;
2086 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY
2087 u16 pci_pm;
2088
2089 IWL_DEBUG_POWER("Initialize power \n");
2090
2091 pow_data = &(priv->power_data);
2092
2093 memset(pow_data, 0, sizeof(*pow_data));
2094
2095 pow_data->active_index = IWL_POWER_RANGE_0;
2096 pow_data->dtim_val = 0xffff;
2097
2098 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
2099 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
2100
2101 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
2102 if (rc != 0)
2103 return 0;
2104 else {
bb8c093b 2105 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY
2106
2107 IWL_DEBUG_POWER("adjust power command flags\n");
2108
2109 for (i = 0; i < IWL_POWER_AC; i++) {
2110 cmd = &pow_data->pwr_range_0[i].cmd;
2111
2112 if (pci_pm & 0x1)
2113 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
2114 else
2115 cmd->flags |= IWL_POWER_PCI_PM_MSK;
2116 }
2117 }
2118 return rc;
2119}
2120
bb8c093b
CH
2121static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
2122 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY
2123{
2124 int rc = 0, i;
2125 u8 skip;
2126 u32 max_sleep = 0;
bb8c093b 2127 struct iwl3945_power_vec_entry *range;
b481de9c 2128 u8 period = 0;
bb8c093b 2129 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY
2130
2131 if (mode > IWL_POWER_INDEX_5) {
2132 IWL_DEBUG_POWER("Error invalid power mode \n");
2133 return -1;
2134 }
2135 pow_data = &(priv->power_data);
2136
2137 if (pow_data->active_index == IWL_POWER_RANGE_0)
2138 range = &pow_data->pwr_range_0[0];
2139 else
2140 range = &pow_data->pwr_range_1[1];
2141
bb8c093b 2142 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY
2143
2144#ifdef IWL_MAC80211_DISABLE
2145 if (priv->assoc_network != NULL) {
2146 unsigned long flags;
2147
2148 period = priv->assoc_network->tim.tim_period;
2149 }
2150#endif /*IWL_MAC80211_DISABLE */
2151 skip = range[mode].no_dtim;
2152
2153 if (period == 0) {
2154 period = 1;
2155 skip = 0;
2156 }
2157
2158 if (skip == 0) {
2159 max_sleep = period;
2160 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
2161 } else {
2162 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
2163 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
2164 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
2165 }
2166
2167 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
2168 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
2169 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
2170 }
2171
2172 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
2173 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
2174 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
2175 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
2176 le32_to_cpu(cmd->sleep_interval[0]),
2177 le32_to_cpu(cmd->sleep_interval[1]),
2178 le32_to_cpu(cmd->sleep_interval[2]),
2179 le32_to_cpu(cmd->sleep_interval[3]),
2180 le32_to_cpu(cmd->sleep_interval[4]));
2181
2182 return rc;
2183}
2184
bb8c093b 2185static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 2186{
9a62f73b 2187 u32 uninitialized_var(final_mode);
b481de9c 2188 int rc;
bb8c093b 2189 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY
2190
2191 /* If on battery, set to 3,
01ebd063 2192 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY
2193 * else user level */
2194 switch (mode) {
2195 case IWL_POWER_BATTERY:
2196 final_mode = IWL_POWER_INDEX_3;
2197 break;
2198 case IWL_POWER_AC:
2199 final_mode = IWL_POWER_MODE_CAM;
2200 break;
2201 default:
2202 final_mode = mode;
2203 break;
2204 }
2205
bb8c093b 2206 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2207
bb8c093b 2208 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY
2209
2210 if (final_mode == IWL_POWER_MODE_CAM)
2211 clear_bit(STATUS_POWER_PMI, &priv->status);
2212 else
2213 set_bit(STATUS_POWER_PMI, &priv->status);
2214
2215 return rc;
2216}
2217
bb8c093b 2218int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY
2219{
2220 /* Filter incoming packets to determine if they are targeted toward
2221 * this network, discarding packets coming from ourselves */
2222 switch (priv->iw_mode) {
2223 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2224 /* packets from our adapter are dropped (echo) */
2225 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2226 return 0;
2227 /* {broad,multi}cast packets to our IBSS go through */
2228 if (is_multicast_ether_addr(header->addr1))
2229 return !compare_ether_addr(header->addr3, priv->bssid);
2230 /* packets to our adapter go through */
2231 return !compare_ether_addr(header->addr1, priv->mac_addr);
2232 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2233 /* packets from our adapter are dropped (echo) */
2234 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2235 return 0;
2236 /* {broad,multi}cast packets to our BSS go through */
2237 if (is_multicast_ether_addr(header->addr1))
2238 return !compare_ether_addr(header->addr2, priv->bssid);
2239 /* packets to our adapter go through */
2240 return !compare_ether_addr(header->addr1, priv->mac_addr);
2241 }
2242
2243 return 1;
2244}
2245
2246#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2247
bb8c093b 2248static const char *iwl3945_get_tx_fail_reason(u32 status)
b481de9c
ZY
2249{
2250 switch (status & TX_STATUS_MSK) {
2251 case TX_STATUS_SUCCESS:
2252 return "SUCCESS";
2253 TX_STATUS_ENTRY(SHORT_LIMIT);
2254 TX_STATUS_ENTRY(LONG_LIMIT);
2255 TX_STATUS_ENTRY(FIFO_UNDERRUN);
2256 TX_STATUS_ENTRY(MGMNT_ABORT);
2257 TX_STATUS_ENTRY(NEXT_FRAG);
2258 TX_STATUS_ENTRY(LIFE_EXPIRE);
2259 TX_STATUS_ENTRY(DEST_PS);
2260 TX_STATUS_ENTRY(ABORTED);
2261 TX_STATUS_ENTRY(BT_RETRY);
2262 TX_STATUS_ENTRY(STA_INVALID);
2263 TX_STATUS_ENTRY(FRAG_DROPPED);
2264 TX_STATUS_ENTRY(TID_DISABLE);
2265 TX_STATUS_ENTRY(FRAME_FLUSHED);
2266 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
2267 TX_STATUS_ENTRY(TX_LOCKED);
2268 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
2269 }
2270
2271 return "UNKNOWN";
2272}
2273
2274/**
bb8c093b 2275 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY
2276 *
2277 * NOTE: priv->mutex is not required before calling this function
2278 */
bb8c093b 2279static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY
2280{
2281 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2282 clear_bit(STATUS_SCANNING, &priv->status);
2283 return 0;
2284 }
2285
2286 if (test_bit(STATUS_SCANNING, &priv->status)) {
2287 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2288 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2289 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2290 queue_work(priv->workqueue, &priv->abort_scan);
2291
2292 } else
2293 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2294
2295 return test_bit(STATUS_SCANNING, &priv->status);
2296 }
2297
2298 return 0;
2299}
2300
2301/**
bb8c093b 2302 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY
2303 * @ms: amount of time to wait (in milliseconds) for scan to abort
2304 *
2305 * NOTE: priv->mutex must be held before calling this function
2306 */
bb8c093b 2307static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY
2308{
2309 unsigned long now = jiffies;
2310 int ret;
2311
bb8c093b 2312 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY
2313 if (ret && ms) {
2314 mutex_unlock(&priv->mutex);
2315 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2316 test_bit(STATUS_SCANNING, &priv->status))
2317 msleep(1);
2318 mutex_lock(&priv->mutex);
2319
2320 return test_bit(STATUS_SCANNING, &priv->status);
2321 }
2322
2323 return ret;
2324}
2325
bb8c093b 2326static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY
2327{
2328 /* Reset ieee stats */
2329
2330 /* We don't reset the net_device_stats (ieee->stats) on
2331 * re-association */
2332
2333 priv->last_seq_num = -1;
2334 priv->last_frag_num = -1;
2335 priv->last_packet_time = 0;
2336
bb8c093b 2337 iwl3945_scan_cancel(priv);
b481de9c
ZY
2338}
2339
2340#define MAX_UCODE_BEACON_INTERVAL 1024
2341#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2342
bb8c093b 2343static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY
2344{
2345 u16 new_val = 0;
2346 u16 beacon_factor = 0;
2347
2348 beacon_factor =
2349 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2350 / MAX_UCODE_BEACON_INTERVAL;
2351 new_val = beacon_val / beacon_factor;
2352
2353 return cpu_to_le16(new_val);
2354}
2355
bb8c093b 2356static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY
2357{
2358 u64 interval_tm_unit;
2359 u64 tsf, result;
2360 unsigned long flags;
2361 struct ieee80211_conf *conf = NULL;
2362 u16 beacon_int = 0;
2363
2364 conf = ieee80211_get_hw_conf(priv->hw);
2365
2366 spin_lock_irqsave(&priv->lock, flags);
2367 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2368 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2369
2370 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2371
2372 tsf = priv->timestamp1;
2373 tsf = ((tsf << 32) | priv->timestamp0);
2374
2375 beacon_int = priv->beacon_int;
2376 spin_unlock_irqrestore(&priv->lock, flags);
2377
2378 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2379 if (beacon_int == 0) {
2380 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2381 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2382 } else {
2383 priv->rxon_timing.beacon_interval =
2384 cpu_to_le16(beacon_int);
2385 priv->rxon_timing.beacon_interval =
bb8c093b 2386 iwl3945_adjust_beacon_interval(
b481de9c
ZY
2387 le16_to_cpu(priv->rxon_timing.beacon_interval));
2388 }
2389
2390 priv->rxon_timing.atim_window = 0;
2391 } else {
2392 priv->rxon_timing.beacon_interval =
bb8c093b 2393 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY
2394 /* TODO: we need to get atim_window from upper stack
2395 * for now we set to 0 */
2396 priv->rxon_timing.atim_window = 0;
2397 }
2398
2399 interval_tm_unit =
2400 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2401 result = do_div(tsf, interval_tm_unit);
2402 priv->rxon_timing.beacon_init_val =
2403 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2404
2405 IWL_DEBUG_ASSOC
2406 ("beacon interval %d beacon timer %d beacon tim %d\n",
2407 le16_to_cpu(priv->rxon_timing.beacon_interval),
2408 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2409 le16_to_cpu(priv->rxon_timing.atim_window));
2410}
2411
bb8c093b 2412static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY
2413{
2414 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2415 IWL_ERROR("APs don't scan.\n");
2416 return 0;
2417 }
2418
bb8c093b 2419 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
2420 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2421 return -EIO;
2422 }
2423
2424 if (test_bit(STATUS_SCANNING, &priv->status)) {
2425 IWL_DEBUG_SCAN("Scan already in progress.\n");
2426 return -EAGAIN;
2427 }
2428
2429 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2430 IWL_DEBUG_SCAN("Scan request while abort pending. "
2431 "Queuing.\n");
2432 return -EAGAIN;
2433 }
2434
2435 IWL_DEBUG_INFO("Starting scan...\n");
2436 priv->scan_bands = 2;
2437 set_bit(STATUS_SCANNING, &priv->status);
2438 priv->scan_start = jiffies;
2439 priv->scan_pass_start = priv->scan_start;
2440
2441 queue_work(priv->workqueue, &priv->request_scan);
2442
2443 return 0;
2444}
2445
bb8c093b 2446static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2447{
bb8c093b 2448 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY
2449
2450 if (hw_decrypt)
2451 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2452 else
2453 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2454
2455 return 0;
2456}
2457
bb8c093b 2458static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode)
b481de9c
ZY
2459{
2460 if (phymode == MODE_IEEE80211A) {
2461 priv->staging_rxon.flags &=
2462 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2463 | RXON_FLG_CCK_MSK);
2464 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2465 } else {
bb8c093b 2466 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY
2467 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2468 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2469 else
2470 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2471
2472 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2473 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2474
2475 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2476 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2477 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2478 }
2479}
2480
2481/*
01ebd063 2482 * initialize rxon structure with default values from eeprom
b481de9c 2483 */
bb8c093b 2484static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2485{
bb8c093b 2486 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY
2487
2488 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2489
2490 switch (priv->iw_mode) {
2491 case IEEE80211_IF_TYPE_AP:
2492 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2493 break;
2494
2495 case IEEE80211_IF_TYPE_STA:
2496 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2497 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2498 break;
2499
2500 case IEEE80211_IF_TYPE_IBSS:
2501 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2502 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2503 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2504 RXON_FILTER_ACCEPT_GRP_MSK;
2505 break;
2506
2507 case IEEE80211_IF_TYPE_MNTR:
2508 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2509 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2510 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2511 break;
2512 }
2513
2514#if 0
2515 /* TODO: Figure out when short_preamble would be set and cache from
2516 * that */
2517 if (!hw_to_local(priv->hw)->short_preamble)
2518 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2519 else
2520 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2521#endif
2522
bb8c093b 2523 ch_info = iwl3945_get_channel_info(priv, priv->phymode,
b481de9c
ZY
2524 le16_to_cpu(priv->staging_rxon.channel));
2525
2526 if (!ch_info)
2527 ch_info = &priv->channel_info[0];
2528
2529 /*
2530 * in some case A channels are all non IBSS
2531 * in this case force B/G channel
2532 */
2533 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2534 !(is_channel_ibss(ch_info)))
2535 ch_info = &priv->channel_info[0];
2536
2537 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2538 if (is_channel_a_band(ch_info))
2539 priv->phymode = MODE_IEEE80211A;
2540 else
2541 priv->phymode = MODE_IEEE80211G;
2542
bb8c093b 2543 iwl3945_set_flags_for_phymode(priv, priv->phymode);
b481de9c
ZY
2544
2545 priv->staging_rxon.ofdm_basic_rates =
2546 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2547 priv->staging_rxon.cck_basic_rates =
2548 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2549}
2550
bb8c093b 2551static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2552{
b481de9c 2553 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2554 const struct iwl3945_channel_info *ch_info;
b481de9c 2555
bb8c093b 2556 ch_info = iwl3945_get_channel_info(priv,
b481de9c
ZY
2557 priv->phymode,
2558 le16_to_cpu(priv->staging_rxon.channel));
2559
2560 if (!ch_info || !is_channel_ibss(ch_info)) {
2561 IWL_ERROR("channel %d not IBSS channel\n",
2562 le16_to_cpu(priv->staging_rxon.channel));
2563 return -EINVAL;
2564 }
2565 }
2566
b481de9c
ZY
2567 priv->iw_mode = mode;
2568
bb8c093b 2569 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY
2570 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2571
bb8c093b 2572 iwl3945_clear_stations_table(priv);
b481de9c 2573
fde3571f
MA
2574 /* dont commit rxon if rf-kill is on*/
2575 if (!iwl3945_is_ready_rf(priv))
2576 return -EAGAIN;
2577
2578 cancel_delayed_work(&priv->scan_check);
2579 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2580 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2581 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2582 return -EAGAIN;
2583 }
2584
bb8c093b 2585 iwl3945_commit_rxon(priv);
b481de9c
ZY
2586
2587 return 0;
2588}
2589
bb8c093b 2590static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
b481de9c 2591 struct ieee80211_tx_control *ctl,
bb8c093b 2592 struct iwl3945_cmd *cmd,
b481de9c
ZY
2593 struct sk_buff *skb_frag,
2594 int last_frag)
2595{
bb8c093b 2596 struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
b481de9c
ZY
2597
2598 switch (keyinfo->alg) {
2599 case ALG_CCMP:
2600 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2601 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2602 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2603 break;
2604
2605 case ALG_TKIP:
2606#if 0
2607 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2608
2609 if (last_frag)
2610 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2611 8);
2612 else
2613 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2614#endif
2615 break;
2616
2617 case ALG_WEP:
2618 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2619 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2620
2621 if (keyinfo->keylen == 13)
2622 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2623
2624 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2625
2626 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2627 "with key %d\n", ctl->key_idx);
2628 break;
2629
b481de9c
ZY
2630 default:
2631 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2632 break;
2633 }
2634}
2635
2636/*
2637 * handle build REPLY_TX command notification.
2638 */
bb8c093b
CH
2639static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2640 struct iwl3945_cmd *cmd,
b481de9c
ZY
2641 struct ieee80211_tx_control *ctrl,
2642 struct ieee80211_hdr *hdr,
2643 int is_unicast, u8 std_id)
2644{
2645 __le16 *qc;
2646 u16 fc = le16_to_cpu(hdr->frame_control);
2647 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2648
2649 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2650 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2651 tx_flags |= TX_CMD_FLG_ACK_MSK;
2652 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2653 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2654 if (ieee80211_is_probe_response(fc) &&
2655 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2656 tx_flags |= TX_CMD_FLG_TSF_MSK;
2657 } else {
2658 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2659 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2660 }
2661
2662 cmd->cmd.tx.sta_id = std_id;
2663 if (ieee80211_get_morefrag(hdr))
2664 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2665
2666 qc = ieee80211_get_qos_ctrl(hdr);
2667 if (qc) {
2668 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2669 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2670 } else
2671 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2672
2673 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2674 tx_flags |= TX_CMD_FLG_RTS_MSK;
2675 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2676 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2677 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2678 tx_flags |= TX_CMD_FLG_CTS_MSK;
2679 }
2680
2681 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2682 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2683
2684 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2685 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2686 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2687 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2688 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2689 else
bc434dd2 2690 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
b481de9c
ZY
2691 } else
2692 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2693
2694 cmd->cmd.tx.driver_txop = 0;
2695 cmd->cmd.tx.tx_flags = tx_flags;
2696 cmd->cmd.tx.next_frame_len = 0;
2697}
2698
6440adb5
CB
2699/**
2700 * iwl3945_get_sta_id - Find station's index within station table
2701 */
bb8c093b 2702static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY
2703{
2704 int sta_id;
2705 u16 fc = le16_to_cpu(hdr->frame_control);
2706
6440adb5 2707 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY
2708 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2709 is_multicast_ether_addr(hdr->addr1))
2710 return priv->hw_setting.bcast_sta_id;
2711
2712 switch (priv->iw_mode) {
2713
6440adb5
CB
2714 /* If we are a client station in a BSS network, use the special
2715 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY
2716 case IEEE80211_IF_TYPE_STA:
2717 return IWL_AP_ID;
2718
2719 /* If we are an AP, then find the station, or use BCAST */
2720 case IEEE80211_IF_TYPE_AP:
bb8c093b 2721 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2722 if (sta_id != IWL_INVALID_STATION)
2723 return sta_id;
2724 return priv->hw_setting.bcast_sta_id;
2725
6440adb5
CB
2726 /* If this frame is going out to an IBSS network, find the station,
2727 * or create a new station table entry */
0795af57
JP
2728 case IEEE80211_IF_TYPE_IBSS: {
2729 DECLARE_MAC_BUF(mac);
2730
6440adb5 2731 /* Create new station table entry */
bb8c093b 2732 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2733 if (sta_id != IWL_INVALID_STATION)
2734 return sta_id;
2735
bb8c093b 2736 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY
2737
2738 if (sta_id != IWL_INVALID_STATION)
2739 return sta_id;
2740
0795af57 2741 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2742 "Defaulting to broadcast...\n",
0795af57 2743 print_mac(mac, hdr->addr1));
bb8c093b 2744 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2745 return priv->hw_setting.bcast_sta_id;
0795af57 2746 }
b481de9c 2747 default:
01ebd063 2748 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY
2749 return priv->hw_setting.bcast_sta_id;
2750 }
2751}
2752
2753/*
2754 * start REPLY_TX command process
2755 */
bb8c093b 2756static int iwl3945_tx_skb(struct iwl3945_priv *priv,
b481de9c
ZY
2757 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2758{
2759 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2760 struct iwl3945_tfd_frame *tfd;
b481de9c
ZY
2761 u32 *control_flags;
2762 int txq_id = ctl->queue;
bb8c093b
CH
2763 struct iwl3945_tx_queue *txq = NULL;
2764 struct iwl3945_queue *q = NULL;
b481de9c
ZY
2765 dma_addr_t phys_addr;
2766 dma_addr_t txcmd_phys;
bb8c093b 2767 struct iwl3945_cmd *out_cmd = NULL;
b481de9c
ZY
2768 u16 len, idx, len_org;
2769 u8 id, hdr_len, unicast;
2770 u8 sta_id;
2771 u16 seq_number = 0;
2772 u16 fc;
2773 __le16 *qc;
2774 u8 wait_write_ptr = 0;
2775 unsigned long flags;
2776 int rc;
2777
2778 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2779 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY
2780 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2781 goto drop_unlock;
2782 }
2783
32bfd35d
JB
2784 if (!priv->vif) {
2785 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY
2786 goto drop_unlock;
2787 }
2788
2789 if ((ctl->tx_rate & 0xFF) == IWL_INVALID_RATE) {
2790 IWL_ERROR("ERROR: No TX rate available.\n");
2791 goto drop_unlock;
2792 }
2793
2794 unicast = !is_multicast_ether_addr(hdr->addr1);
2795 id = 0;
2796
2797 fc = le16_to_cpu(hdr->frame_control);
2798
c8b0e6e1 2799#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
2800 if (ieee80211_is_auth(fc))
2801 IWL_DEBUG_TX("Sending AUTH frame\n");
2802 else if (ieee80211_is_assoc_request(fc))
2803 IWL_DEBUG_TX("Sending ASSOC frame\n");
2804 else if (ieee80211_is_reassoc_request(fc))
2805 IWL_DEBUG_TX("Sending REASSOC frame\n");
2806#endif
2807
7878a5a4
MA
2808 /* drop all data frame if we are not associated */
2809 if (!iwl3945_is_associated(priv) && !priv->assoc_id &&
b481de9c 2810 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
bb8c093b 2811 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY
2812 goto drop_unlock;
2813 }
2814
2815 spin_unlock_irqrestore(&priv->lock, flags);
2816
2817 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
CB
2818
2819 /* Find (or create) index into station table for destination station */
bb8c093b 2820 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2821 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP
2822 DECLARE_MAC_BUF(mac);
2823
2824 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2825 print_mac(mac, hdr->addr1));
b481de9c
ZY
2826 goto drop;
2827 }
2828
2829 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2830
2831 qc = ieee80211_get_qos_ctrl(hdr);
2832 if (qc) {
2833 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2834 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2835 IEEE80211_SCTL_SEQ;
2836 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2837 (hdr->seq_ctrl &
2838 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2839 seq_number += 0x10;
2840 }
6440adb5
CB
2841
2842 /* Descriptor for chosen Tx queue */
b481de9c
ZY
2843 txq = &priv->txq[txq_id];
2844 q = &txq->q;
2845
2846 spin_lock_irqsave(&priv->lock, flags);
2847
6440adb5 2848 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2849 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY
2850 memset(tfd, 0, sizeof(*tfd));
2851 control_flags = (u32 *) tfd;
fc4b6853 2852 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2853
6440adb5 2854 /* Set up driver data for this TFD */
bb8c093b 2855 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853
TW
2856 txq->txb[q->write_ptr].skb[0] = skb;
2857 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2858 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
CB
2859
2860 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY
2861 out_cmd = &txq->cmd[idx];
2862 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2863 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB
2864
2865 /*
2866 * Set up the Tx-command (not MAC!) header.
2867 * Store the chosen Tx queue and TFD index within the sequence field;
2868 * after Tx, uCode's Tx response will return this value so driver can
2869 * locate the frame within the tx queue and do post-tx processing.
2870 */
b481de9c
ZY
2871 out_cmd->hdr.cmd = REPLY_TX;
2872 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2873 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
2874
2875 /* Copy MAC header from skb into command buffer */
b481de9c
ZY
2876 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2877
6440adb5
CB
2878 /*
2879 * Use the first empty entry in this queue's command buffer array
2880 * to contain the Tx command and MAC header concatenated together
2881 * (payload data will be in another buffer).
2882 * Size of this varies, due to varying MAC header length.
2883 * If end is not dword aligned, we'll have 2 extra bytes at the end
2884 * of the MAC header (device reads on dword boundaries).
2885 * We'll tell device about this padding later.
2886 */
b481de9c 2887 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2888 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY
2889
2890 len_org = len;
2891 len = (len + 3) & ~3;
2892
2893 if (len_org != len)
2894 len_org = 1;
2895 else
2896 len_org = 0;
2897
6440adb5
CB
2898 /* Physical address of this Tx command's header (not MAC header!),
2899 * within command buffer array. */
bb8c093b
CH
2900 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2901 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2902
6440adb5
CB
2903 /* Add buffer containing Tx command and MAC(!) header to TFD's
2904 * first entry */
bb8c093b 2905 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY
2906
2907 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
bb8c093b 2908 iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
b481de9c 2909
6440adb5
CB
2910 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2911 * if any (802.11 null frames have no payload). */
b481de9c
ZY
2912 len = skb->len - hdr_len;
2913 if (len) {
2914 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2915 len, PCI_DMA_TODEVICE);
bb8c093b 2916 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY
2917 }
2918
b481de9c 2919 if (!len)
6440adb5 2920 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY
2921 *control_flags = TFD_CTL_COUNT_SET(1);
2922 else
6440adb5
CB
2923 /* Else use 2 buffers.
2924 * Tell 3945 about any padding after MAC header */
b481de9c
ZY
2925 *control_flags = TFD_CTL_COUNT_SET(2) |
2926 TFD_CTL_PAD_SET(U32_PAD(len));
2927
6440adb5 2928 /* Total # bytes to be transmitted */
b481de9c
ZY
2929 len = (u16)skb->len;
2930 out_cmd->cmd.tx.len = cpu_to_le16(len);
2931
2932 /* TODO need this for burst mode later on */
bb8c093b 2933 iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY
2934
2935 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 2936 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c
ZY
2937
2938 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2939 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2940
2941 if (!ieee80211_get_morefrag(hdr)) {
2942 txq->need_update = 1;
2943 if (qc) {
2944 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2945 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2946 }
2947 } else {
2948 wait_write_ptr = 1;
2949 txq->need_update = 0;
2950 }
2951
bb8c093b 2952 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY
2953 sizeof(out_cmd->cmd.tx));
2954
bb8c093b 2955 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY
2956 ieee80211_get_hdrlen(fc));
2957
6440adb5 2958 /* Tell device the write index *just past* this latest filled TFD */
bb8c093b
CH
2959 q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
2960 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2961 spin_unlock_irqrestore(&priv->lock, flags);
2962
2963 if (rc)
2964 return rc;
2965
bb8c093b 2966 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY
2967 && priv->mac80211_registered) {
2968 if (wait_write_ptr) {
2969 spin_lock_irqsave(&priv->lock, flags);
2970 txq->need_update = 1;
bb8c093b 2971 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2972 spin_unlock_irqrestore(&priv->lock, flags);
2973 }
2974
2975 ieee80211_stop_queue(priv->hw, ctl->queue);
2976 }
2977
2978 return 0;
2979
2980drop_unlock:
2981 spin_unlock_irqrestore(&priv->lock, flags);
2982drop:
2983 return -1;
2984}
2985
bb8c093b 2986static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c
ZY
2987{
2988 const struct ieee80211_hw_mode *hw = NULL;
2989 struct ieee80211_rate *rate;
2990 int i;
2991
bb8c093b 2992 hw = iwl3945_get_hw_mode(priv, priv->phymode);
c4ba9621
SA
2993 if (!hw) {
2994 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2995 return;
2996 }
b481de9c
ZY
2997
2998 priv->active_rate = 0;
2999 priv->active_rate_basic = 0;
3000
3001 IWL_DEBUG_RATE("Setting rates for 802.11%c\n",
3002 hw->mode == MODE_IEEE80211A ?
3003 'a' : ((hw->mode == MODE_IEEE80211B) ? 'b' : 'g'));
3004
3005 for (i = 0; i < hw->num_rates; i++) {
3006 rate = &(hw->rates[i]);
3007 if ((rate->val < IWL_RATE_COUNT) &&
3008 (rate->flags & IEEE80211_RATE_SUPPORTED)) {
3009 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)%s\n",
bb8c093b 3010 rate->val, iwl3945_rates[rate->val].plcp,
b481de9c
ZY
3011 (rate->flags & IEEE80211_RATE_BASIC) ?
3012 "*" : "");
3013 priv->active_rate |= (1 << rate->val);
3014 if (rate->flags & IEEE80211_RATE_BASIC)
3015 priv->active_rate_basic |= (1 << rate->val);
3016 } else
3017 IWL_DEBUG_RATE("Not adding rate %d (plcp %d)\n",
bb8c093b 3018 rate->val, iwl3945_rates[rate->val].plcp);
b481de9c
ZY
3019 }
3020
3021 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
3022 priv->active_rate, priv->active_rate_basic);
3023
3024 /*
3025 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
3026 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
3027 * OFDM
3028 */
3029 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
3030 priv->staging_rxon.cck_basic_rates =
3031 ((priv->active_rate_basic &
3032 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
3033 else
3034 priv->staging_rxon.cck_basic_rates =
3035 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
3036
3037 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
3038 priv->staging_rxon.ofdm_basic_rates =
3039 ((priv->active_rate_basic &
3040 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
3041 IWL_FIRST_OFDM_RATE) & 0xFF;
3042 else
3043 priv->staging_rxon.ofdm_basic_rates =
3044 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
3045}
3046
bb8c093b 3047static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY
3048{
3049 unsigned long flags;
3050
3051 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
3052 return;
3053
3054 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
3055 disable_radio ? "OFF" : "ON");
3056
3057 if (disable_radio) {
bb8c093b 3058 iwl3945_scan_cancel(priv);
b481de9c
ZY
3059 /* FIXME: This is a workaround for AP */
3060 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
3061 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3062 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3063 CSR_UCODE_SW_BIT_RFKILL);
3064 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 3065 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY
3066 set_bit(STATUS_RF_KILL_SW, &priv->status);
3067 }
3068 return;
3069 }
3070
3071 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3072 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
3073
3074 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3075 spin_unlock_irqrestore(&priv->lock, flags);
3076
3077 /* wake up ucode */
3078 msleep(10);
3079
3080 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH
3081 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
3082 if (!iwl3945_grab_nic_access(priv))
3083 iwl3945_release_nic_access(priv);
b481de9c
ZY
3084 spin_unlock_irqrestore(&priv->lock, flags);
3085
3086 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
3087 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
3088 "disabled by HW switch\n");
3089 return;
3090 }
3091
3092 queue_work(priv->workqueue, &priv->restart);
3093 return;
3094}
3095
bb8c093b 3096void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY
3097 u32 decrypt_res, struct ieee80211_rx_status *stats)
3098{
3099 u16 fc =
3100 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
3101
3102 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
3103 return;
3104
3105 if (!(fc & IEEE80211_FCTL_PROTECTED))
3106 return;
3107
3108 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
3109 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
3110 case RX_RES_STATUS_SEC_TYPE_TKIP:
3111 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3112 RX_RES_STATUS_BAD_ICV_MIC)
3113 stats->flag |= RX_FLAG_MMIC_ERROR;
3114 case RX_RES_STATUS_SEC_TYPE_WEP:
3115 case RX_RES_STATUS_SEC_TYPE_CCMP:
3116 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3117 RX_RES_STATUS_DECRYPT_OK) {
3118 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
3119 stats->flag |= RX_FLAG_DECRYPTED;
3120 }
3121 break;
3122
3123 default:
3124 break;
3125 }
3126}
3127
b481de9c
ZY
3128#define IWL_PACKET_RETRY_TIME HZ
3129
bb8c093b 3130int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY
3131{
3132 u16 sc = le16_to_cpu(header->seq_ctrl);
3133 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
3134 u16 frag = sc & IEEE80211_SCTL_FRAG;
3135 u16 *last_seq, *last_frag;
3136 unsigned long *last_time;
3137
3138 switch (priv->iw_mode) {
3139 case IEEE80211_IF_TYPE_IBSS:{
3140 struct list_head *p;
bb8c093b 3141 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY
3142 u8 *mac = header->addr2;
3143 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
3144
3145 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 3146 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY
3147 if (!compare_ether_addr(entry->mac, mac))
3148 break;
3149 }
3150 if (p == &priv->ibss_mac_hash[index]) {
3151 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
3152 if (!entry) {
bc434dd2 3153 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY
3154 return 0;
3155 }
3156 memcpy(entry->mac, mac, ETH_ALEN);
3157 entry->seq_num = seq;
3158 entry->frag_num = frag;
3159 entry->packet_time = jiffies;
bc434dd2 3160 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY
3161 return 0;
3162 }
3163 last_seq = &entry->seq_num;
3164 last_frag = &entry->frag_num;
3165 last_time = &entry->packet_time;
3166 break;
3167 }
3168 case IEEE80211_IF_TYPE_STA:
3169 last_seq = &priv->last_seq_num;
3170 last_frag = &priv->last_frag_num;
3171 last_time = &priv->last_packet_time;
3172 break;
3173 default:
3174 return 0;
3175 }
3176 if ((*last_seq == seq) &&
3177 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
3178 if (*last_frag == frag)
3179 goto drop;
3180 if (*last_frag + 1 != frag)
3181 /* out-of-order fragment */
3182 goto drop;
3183 } else
3184 *last_seq = seq;
3185
3186 *last_frag = frag;
3187 *last_time = jiffies;
3188 return 0;
3189
3190 drop:
3191 return 1;
3192}
3193
c8b0e6e1 3194#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3195
3196#include "iwl-spectrum.h"
3197
3198#define BEACON_TIME_MASK_LOW 0x00FFFFFF
3199#define BEACON_TIME_MASK_HIGH 0xFF000000
3200#define TIME_UNIT 1024
3201
3202/*
3203 * extended beacon time format
3204 * time in usec will be changed into a 32-bit value in 8:24 format
3205 * the high 1 byte is the beacon counts
3206 * the lower 3 bytes is the time in usec within one beacon interval
3207 */
3208
bb8c093b 3209static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
3210{
3211 u32 quot;
3212 u32 rem;
3213 u32 interval = beacon_interval * 1024;
3214
3215 if (!interval || !usec)
3216 return 0;
3217
3218 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3219 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3220
3221 return (quot << 24) + rem;
3222}
3223
3224/* base is usually what we get from ucode with each received frame,
3225 * the same as HW timer counter counting down
3226 */
3227
bb8c093b 3228static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
3229{
3230 u32 base_low = base & BEACON_TIME_MASK_LOW;
3231 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3232 u32 interval = beacon_interval * TIME_UNIT;
3233 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3234 (addon & BEACON_TIME_MASK_HIGH);
3235
3236 if (base_low > addon_low)
3237 res += base_low - addon_low;
3238 else if (base_low < addon_low) {
3239 res += interval + base_low - addon_low;
3240 res += (1 << 24);
3241 } else
3242 res += (1 << 24);
3243
3244 return cpu_to_le32(res);
3245}
3246
bb8c093b 3247static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY
3248 struct ieee80211_measurement_params *params,
3249 u8 type)
3250{
bb8c093b
CH
3251 struct iwl3945_spectrum_cmd spectrum;
3252 struct iwl3945_rx_packet *res;
3253 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
3254 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3255 .data = (void *)&spectrum,
3256 .meta.flags = CMD_WANT_SKB,
3257 };
3258 u32 add_time = le64_to_cpu(params->start_time);
3259 int rc;
3260 int spectrum_resp_status;
3261 int duration = le16_to_cpu(params->duration);
3262
bb8c093b 3263 if (iwl3945_is_associated(priv))
b481de9c 3264 add_time =
bb8c093b 3265 iwl3945_usecs_to_beacons(
b481de9c
ZY
3266 le64_to_cpu(params->start_time) - priv->last_tsf,
3267 le16_to_cpu(priv->rxon_timing.beacon_interval));
3268
3269 memset(&spectrum, 0, sizeof(spectrum));
3270
3271 spectrum.channel_count = cpu_to_le16(1);
3272 spectrum.flags =
3273 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3274 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3275 cmd.len = sizeof(spectrum);
3276 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3277
bb8c093b 3278 if (iwl3945_is_associated(priv))
b481de9c 3279 spectrum.start_time =
bb8c093b 3280 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
3281 add_time,
3282 le16_to_cpu(priv->rxon_timing.beacon_interval));
3283 else
3284 spectrum.start_time = 0;
3285
3286 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3287 spectrum.channels[0].channel = params->channel;
3288 spectrum.channels[0].type = type;
3289 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3290 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3291 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3292
bb8c093b 3293 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
3294 if (rc)
3295 return rc;
3296
bb8c093b 3297 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
3298 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3299 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3300 rc = -EIO;
3301 }
3302
3303 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3304 switch (spectrum_resp_status) {
3305 case 0: /* Command will be handled */
3306 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS
3307 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3308 res->u.spectrum.id);
b481de9c
ZY
3309 priv->measurement_status &= ~MEASUREMENT_READY;
3310 }
3311 priv->measurement_status |= MEASUREMENT_ACTIVE;
3312 rc = 0;
3313 break;
3314
3315 case 1: /* Command will not be handled */
3316 rc = -EAGAIN;
3317 break;
3318 }
3319
3320 dev_kfree_skb_any(cmd.meta.u.skb);
3321
3322 return rc;
3323}
3324#endif
3325
bb8c093b
CH
3326static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
3327 struct iwl3945_tx_info *tx_sta)
b481de9c
ZY
3328{
3329
3330 tx_sta->status.ack_signal = 0;
3331 tx_sta->status.excessive_retries = 0;
3332 tx_sta->status.queue_length = 0;
3333 tx_sta->status.queue_number = 0;
3334
3335 if (in_interrupt())
3336 ieee80211_tx_status_irqsafe(priv->hw,
3337 tx_sta->skb[0], &(tx_sta->status));
3338 else
3339 ieee80211_tx_status(priv->hw,
3340 tx_sta->skb[0], &(tx_sta->status));
3341
3342 tx_sta->skb[0] = NULL;
3343}
3344
3345/**
6440adb5 3346 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
b481de9c 3347 *
6440adb5
CB
3348 * When FW advances 'R' index, all entries between old and new 'R' index
3349 * need to be reclaimed. As result, some free space forms. If there is
3350 * enough free space (> low mark), wake the stack that feeds us.
b481de9c 3351 */
bb8c093b 3352static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
b481de9c 3353{
bb8c093b
CH
3354 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3355 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY
3356 int nfreed = 0;
3357
3358 if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
3359 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3360 "is out of range [0-%d] %d %d.\n", txq_id,
fc4b6853 3361 index, q->n_bd, q->write_ptr, q->read_ptr);
b481de9c
ZY
3362 return 0;
3363 }
3364
bb8c093b 3365 for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
fc4b6853 3366 q->read_ptr != index;
bb8c093b 3367 q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
b481de9c 3368 if (txq_id != IWL_CMD_QUEUE_NUM) {
bb8c093b 3369 iwl3945_txstatus_to_ieee(priv,
fc4b6853 3370 &(txq->txb[txq->q.read_ptr]));
bb8c093b 3371 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c
ZY
3372 } else if (nfreed > 1) {
3373 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
fc4b6853 3374 q->write_ptr, q->read_ptr);
b481de9c
ZY
3375 queue_work(priv->workqueue, &priv->restart);
3376 }
3377 nfreed++;
3378 }
3379
bb8c093b 3380 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
b481de9c
ZY
3381 (txq_id != IWL_CMD_QUEUE_NUM) &&
3382 priv->mac80211_registered)
3383 ieee80211_wake_queue(priv->hw, txq_id);
3384
3385
3386 return nfreed;
3387}
3388
bb8c093b 3389static int iwl3945_is_tx_success(u32 status)
b481de9c
ZY
3390{
3391 return (status & 0xFF) == 0x1;
3392}
3393
3394/******************************************************************************
3395 *
3396 * Generic RX handler implementations
3397 *
3398 ******************************************************************************/
6440adb5
CB
3399/**
3400 * iwl3945_rx_reply_tx - Handle Tx response
3401 */
bb8c093b
CH
3402static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
3403 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3404{
bb8c093b 3405 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3406 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3407 int txq_id = SEQ_TO_QUEUE(sequence);
3408 int index = SEQ_TO_INDEX(sequence);
bb8c093b 3409 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
b481de9c 3410 struct ieee80211_tx_status *tx_status;
bb8c093b 3411 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
b481de9c
ZY
3412 u32 status = le32_to_cpu(tx_resp->status);
3413
3414 if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
3415 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3416 "is out of range [0-%d] %d %d\n", txq_id,
fc4b6853
TW
3417 index, txq->q.n_bd, txq->q.write_ptr,
3418 txq->q.read_ptr);
b481de9c
ZY
3419 return;
3420 }
3421
fc4b6853 3422 tx_status = &(txq->txb[txq->q.read_ptr].status);
b481de9c
ZY
3423
3424 tx_status->retry_count = tx_resp->failure_frame;
3425 tx_status->queue_number = status;
3426 tx_status->queue_length = tx_resp->bt_kill_count;
3427 tx_status->queue_length |= tx_resp->failure_rts;
3428
3429 tx_status->flags =
bb8c093b 3430 iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
b481de9c 3431
bb8c093b 3432 tx_status->control.tx_rate = iwl3945_rate_index_from_plcp(tx_resp->rate);
b481de9c
ZY
3433
3434 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
bb8c093b 3435 txq_id, iwl3945_get_tx_fail_reason(status), status,
b481de9c
ZY
3436 tx_resp->rate, tx_resp->failure_frame);
3437
3438 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
3439 if (index != -1)
bb8c093b 3440 iwl3945_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY
3441
3442 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3443 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3444}
3445
3446
bb8c093b
CH
3447static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3448 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3449{
bb8c093b
CH
3450 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3451 struct iwl3945_alive_resp *palive;
b481de9c
ZY
3452 struct delayed_work *pwork;
3453
3454 palive = &pkt->u.alive_frame;
3455
3456 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3457 "0x%01X 0x%01X\n",
3458 palive->is_valid, palive->ver_type,
3459 palive->ver_subtype);
3460
3461 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3462 IWL_DEBUG_INFO("Initialization Alive received.\n");
3463 memcpy(&priv->card_alive_init,
3464 &pkt->u.alive_frame,
bb8c093b 3465 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY
3466 pwork = &priv->init_alive_start;
3467 } else {
3468 IWL_DEBUG_INFO("Runtime Alive received.\n");
3469 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3470 sizeof(struct iwl3945_alive_resp));
b481de9c 3471 pwork = &priv->alive_start;
bb8c093b 3472 iwl3945_disable_events(priv);
b481de9c
ZY
3473 }
3474
3475 /* We delay the ALIVE response by 5ms to
3476 * give the HW RF Kill time to activate... */
3477 if (palive->is_valid == UCODE_VALID_OK)
3478 queue_delayed_work(priv->workqueue, pwork,
3479 msecs_to_jiffies(5));
3480 else
3481 IWL_WARNING("uCode did not respond OK.\n");
3482}
3483
bb8c093b
CH
3484static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3485 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3486{
bb8c093b 3487 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3488
3489 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3490 return;
3491}
3492
bb8c093b
CH
3493static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3494 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3495{
bb8c093b 3496 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3497
3498 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3499 "seq 0x%04X ser 0x%08X\n",
3500 le32_to_cpu(pkt->u.err_resp.error_type),
3501 get_cmd_string(pkt->u.err_resp.cmd_id),
3502 pkt->u.err_resp.cmd_id,
3503 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3504 le32_to_cpu(pkt->u.err_resp.error_info));
3505}
3506
3507#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3508
bb8c093b 3509static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3510{
bb8c093b
CH
3511 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3512 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3513 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY
3514 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3515 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3516 rxon->channel = csa->channel;
3517 priv->staging_rxon.channel = csa->channel;
3518}
3519
bb8c093b
CH
3520static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3521 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3522{
c8b0e6e1 3523#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH
3524 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3525 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY
3526
3527 if (!report->state) {
3528 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3529 "Spectrum Measure Notification: Start\n");
3530 return;
3531 }
3532
3533 memcpy(&priv->measure_report, report, sizeof(*report));
3534 priv->measurement_status |= MEASUREMENT_READY;
3535#endif
3536}
3537
bb8c093b
CH
3538static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3539 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3540{
c8b0e6e1 3541#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
3542 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3543 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY
3544 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3545 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3546#endif
3547}
3548
bb8c093b
CH
3549static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3550 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3551{
bb8c093b 3552 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3553 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3554 "notification for %s:\n",
3555 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3556 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY
3557}
3558
bb8c093b 3559static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3560{
bb8c093b
CH
3561 struct iwl3945_priv *priv =
3562 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY
3563 struct sk_buff *beacon;
3564
3565 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
32bfd35d 3566 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
b481de9c
ZY
3567
3568 if (!beacon) {
3569 IWL_ERROR("update beacon failed\n");
3570 return;
3571 }
3572
3573 mutex_lock(&priv->mutex);
3574 /* new beacon skb is allocated every time; dispose previous.*/
3575 if (priv->ibss_beacon)
3576 dev_kfree_skb(priv->ibss_beacon);
3577
3578 priv->ibss_beacon = beacon;
3579 mutex_unlock(&priv->mutex);
3580
bb8c093b 3581 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3582}
3583
bb8c093b
CH
3584static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3585 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3586{
c8b0e6e1 3587#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
3588 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3589 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
3590 u8 rate = beacon->beacon_notify_hdr.rate;
3591
3592 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3593 "tsf %d %d rate %d\n",
3594 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3595 beacon->beacon_notify_hdr.failure_frame,
3596 le32_to_cpu(beacon->ibss_mgr_status),
3597 le32_to_cpu(beacon->high_tsf),
3598 le32_to_cpu(beacon->low_tsf), rate);
3599#endif
3600
3601 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3602 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3603 queue_work(priv->workqueue, &priv->beacon_update);
3604}
3605
3606/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH
3607static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3608 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3609{
c8b0e6e1 3610#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
3611 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3612 struct iwl3945_scanreq_notification *notif =
3613 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY
3614
3615 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3616#endif
3617}
3618
3619/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH
3620static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3621 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3622{
bb8c093b
CH
3623 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3624 struct iwl3945_scanstart_notification *notif =
3625 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY
3626 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3627 IWL_DEBUG_SCAN("Scan start: "
3628 "%d [802.11%s] "
3629 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3630 notif->channel,
3631 notif->band ? "bg" : "a",
3632 notif->tsf_high,
3633 notif->tsf_low, notif->status, notif->beacon_timer);
3634}
3635
3636/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH
3637static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3638 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3639{
bb8c093b
CH
3640 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3641 struct iwl3945_scanresults_notification *notif =
3642 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY
3643
3644 IWL_DEBUG_SCAN("Scan ch.res: "
3645 "%d [802.11%s] "
3646 "(TSF: 0x%08X:%08X) - %d "
3647 "elapsed=%lu usec (%dms since last)\n",
3648 notif->channel,
3649 notif->band ? "bg" : "a",
3650 le32_to_cpu(notif->tsf_high),
3651 le32_to_cpu(notif->tsf_low),
3652 le32_to_cpu(notif->statistics[0]),
3653 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3654 jiffies_to_msecs(elapsed_jiffies
3655 (priv->last_scan_jiffies, jiffies)));
3656
3657 priv->last_scan_jiffies = jiffies;
7878a5a4 3658 priv->next_scan_jiffies = 0;
b481de9c
ZY
3659}
3660
3661/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH
3662static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3663 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3664{
bb8c093b
CH
3665 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3666 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY
3667
3668 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3669 scan_notif->scanned_channels,
3670 scan_notif->tsf_low,
3671 scan_notif->tsf_high, scan_notif->status);
3672
3673 /* The HW is no longer scanning */
3674 clear_bit(STATUS_SCAN_HW, &priv->status);
3675
3676 /* The scan completion notification came in, so kill that timer... */
3677 cancel_delayed_work(&priv->scan_check);
3678
3679 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3680 (priv->scan_bands == 2) ? "2.4" : "5.2",
3681 jiffies_to_msecs(elapsed_jiffies
3682 (priv->scan_pass_start, jiffies)));
3683
3684 /* Remove this scanned band from the list
3685 * of pending bands to scan */
3686 priv->scan_bands--;
3687
3688 /* If a request to abort was given, or the scan did not succeed
3689 * then we reset the scan state machine and terminate,
3690 * re-queuing another scan if one has been requested */
3691 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3692 IWL_DEBUG_INFO("Aborted scan completed.\n");
3693 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3694 } else {
3695 /* If there are more bands on this scan pass reschedule */
3696 if (priv->scan_bands > 0)
3697 goto reschedule;
3698 }
3699
3700 priv->last_scan_jiffies = jiffies;
7878a5a4 3701 priv->next_scan_jiffies = 0;
b481de9c
ZY
3702 IWL_DEBUG_INFO("Setting scan to off\n");
3703
3704 clear_bit(STATUS_SCANNING, &priv->status);
3705
3706 IWL_DEBUG_INFO("Scan took %dms\n",
3707 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3708
3709 queue_work(priv->workqueue, &priv->scan_completed);
3710
3711 return;
3712
3713reschedule:
3714 priv->scan_pass_start = jiffies;
3715 queue_work(priv->workqueue, &priv->request_scan);
3716}
3717
3718/* Handle notification from uCode that card's power state is changing
3719 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH
3720static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3721 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3722{
bb8c093b 3723 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3724 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3725 unsigned long status = priv->status;
3726
3727 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3728 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3729 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3730
bb8c093b 3731 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3732 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3733
3734 if (flags & HW_CARD_DISABLED)
3735 set_bit(STATUS_RF_KILL_HW, &priv->status);
3736 else
3737 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3738
3739
3740 if (flags & SW_CARD_DISABLED)
3741 set_bit(STATUS_RF_KILL_SW, &priv->status);
3742 else
3743 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3744
bb8c093b 3745 iwl3945_scan_cancel(priv);
b481de9c
ZY
3746
3747 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3748 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3749 (test_bit(STATUS_RF_KILL_SW, &status) !=
3750 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3751 queue_work(priv->workqueue, &priv->rf_kill);
3752 else
3753 wake_up_interruptible(&priv->wait_command_queue);
3754}
3755
3756/**
bb8c093b 3757 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
3758 *
3759 * Setup the RX handlers for each of the reply types sent from the uCode
3760 * to the host.
3761 *
3762 * This function chains into the hardware specific files for them to setup
3763 * any hardware specific handlers as well.
3764 */
bb8c093b 3765static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3766{
bb8c093b
CH
3767 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3768 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3769 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3770 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3771 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH
3772 iwl3945_rx_spectrum_measure_notif;
3773 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3774 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH
3775 iwl3945_rx_pm_debug_statistics_notif;
3776 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3777
9fbab516
BC
3778 /*
3779 * The same handler is used for both the REPLY to a discrete
3780 * statistics request from the host as well as for the periodic
3781 * statistics notifications (after received beacons) from the uCode.
b481de9c 3782 */
bb8c093b
CH
3783 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3784 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3785
bb8c093b
CH
3786 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3787 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3788 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3789 iwl3945_rx_scan_results_notif;
b481de9c 3790 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH
3791 iwl3945_rx_scan_complete_notif;
3792 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
3793 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c 3794
9fbab516 3795 /* Set up hardware specific Rx handlers */
bb8c093b 3796 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
3797}
3798
3799/**
bb8c093b 3800 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY
3801 * @rxb: Rx buffer to reclaim
3802 *
3803 * If an Rx buffer has an async callback associated with it the callback
3804 * will be executed. The attached skb (if present) will only be freed
3805 * if the callback returns 1
3806 */
bb8c093b
CH
3807static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3808 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3809{
bb8c093b 3810 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY
3811 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3812 int txq_id = SEQ_TO_QUEUE(sequence);
3813 int index = SEQ_TO_INDEX(sequence);
3814 int huge = sequence & SEQ_HUGE_FRAME;
3815 int cmd_index;
bb8c093b 3816 struct iwl3945_cmd *cmd;
b481de9c
ZY
3817
3818 /* If a Tx command is being handled and it isn't in the actual
3819 * command queue then there a command routing bug has been introduced
3820 * in the queue management code. */
3821 if (txq_id != IWL_CMD_QUEUE_NUM)
3822 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
3823 txq_id, pkt->hdr.cmd);
3824 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3825
3826 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3827 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3828
3829 /* Input error checking is done when commands are added to queue. */
3830 if (cmd->meta.flags & CMD_WANT_SKB) {
3831 cmd->meta.source->u.skb = rxb->skb;
3832 rxb->skb = NULL;
3833 } else if (cmd->meta.u.callback &&
3834 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3835 rxb->skb = NULL;
3836
bb8c093b 3837 iwl3945_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY
3838
3839 if (!(cmd->meta.flags & CMD_ASYNC)) {
3840 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3841 wake_up_interruptible(&priv->wait_command_queue);
3842 }
3843}
3844
3845/************************** RX-FUNCTIONS ****************************/
3846/*
3847 * Rx theory of operation
3848 *
3849 * The host allocates 32 DMA target addresses and passes the host address
3850 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3851 * 0 to 31
3852 *
3853 * Rx Queue Indexes
3854 * The host/firmware share two index registers for managing the Rx buffers.
3855 *
3856 * The READ index maps to the first position that the firmware may be writing
3857 * to -- the driver can read up to (but not including) this position and get
3858 * good data.
3859 * The READ index is managed by the firmware once the card is enabled.
3860 *
3861 * The WRITE index maps to the last position the driver has read from -- the
3862 * position preceding WRITE is the last slot the firmware can place a packet.
3863 *
3864 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3865 * WRITE = READ.
3866 *
9fbab516 3867 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
3868 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3869 *
9fbab516 3870 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
3871 * and fire the RX interrupt. The driver can then query the READ index and
3872 * process as many packets as possible, moving the WRITE index forward as it
3873 * resets the Rx queue buffers with new memory.
3874 *
3875 * The management in the driver is as follows:
3876 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3877 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3878 * to replenish the iwl->rxq->rx_free.
bb8c093b 3879 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
3880 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3881 * 'processed' and 'read' driver indexes as well)
3882 * + A received packet is processed and handed to the kernel network stack,
3883 * detached from the iwl->rxq. The driver 'processed' index is updated.
3884 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3885 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3886 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3887 * were enough free buffers and RX_STALLED is set it is cleared.
3888 *
3889 *
3890 * Driver sequence:
3891 *
9fbab516
BC
3892 * iwl3945_rx_queue_alloc() Allocates rx_free
3893 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3894 * iwl3945_rx_queue_restock
9fbab516 3895 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
3896 * queue, updates firmware pointers, and updates
3897 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3898 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
3899 *
3900 * -- enable interrupts --
9fbab516 3901 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY
3902 * READ INDEX, detaching the SKB from the pool.
3903 * Moves the packet buffer from queue to rx_used.
bb8c093b 3904 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
3905 * slots.
3906 * ...
3907 *
3908 */
3909
3910/**
bb8c093b 3911 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3912 */
bb8c093b 3913static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY
3914{
3915 int s = q->read - q->write;
3916 if (s <= 0)
3917 s += RX_QUEUE_SIZE;
3918 /* keep some buffer to not confuse full and empty queue */
3919 s -= 2;
3920 if (s < 0)
3921 s = 0;
3922 return s;
3923}
3924
3925/**
bb8c093b 3926 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3927 */
bb8c093b 3928int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY
3929{
3930 u32 reg = 0;
3931 int rc = 0;
3932 unsigned long flags;
3933
3934 spin_lock_irqsave(&q->lock, flags);
3935
3936 if (q->need_update == 0)
3937 goto exit_unlock;
3938
6440adb5 3939 /* If power-saving is in use, make sure device is awake */
b481de9c 3940 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3941 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
3942
3943 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3944 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
3945 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3946 goto exit_unlock;
3947 }
3948
bb8c093b 3949 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
3950 if (rc)
3951 goto exit_unlock;
3952
6440adb5 3953 /* Device expects a multiple of 8 */
bb8c093b 3954 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3955 q->write & ~0x7);
bb8c093b 3956 iwl3945_release_nic_access(priv);
6440adb5
CB
3957
3958 /* Else device is assumed to be awake */
b481de9c 3959 } else
6440adb5 3960 /* Device expects a multiple of 8 */
bb8c093b 3961 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY
3962
3963
3964 q->need_update = 0;
3965
3966 exit_unlock:
3967 spin_unlock_irqrestore(&q->lock, flags);
3968 return rc;
3969}
3970
3971/**
9fbab516 3972 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3973 */
bb8c093b 3974static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY
3975 dma_addr_t dma_addr)
3976{
3977 return cpu_to_le32((u32)dma_addr);
3978}
3979
3980/**
bb8c093b 3981 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3982 *
9fbab516 3983 * If there are slots in the RX queue that need to be restocked,
b481de9c 3984 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3985 * as we can, pulling from rx_free.
b481de9c
ZY
3986 *
3987 * This moves the 'write' index forward to catch up with 'processed', and
3988 * also updates the memory address in the firmware to reference the new
3989 * target buffer.
3990 */
bb8c093b 3991static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3992{
bb8c093b 3993 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3994 struct list_head *element;
bb8c093b 3995 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY
3996 unsigned long flags;
3997 int write, rc;
3998
3999 spin_lock_irqsave(&rxq->lock, flags);
4000 write = rxq->write & ~0x7;
bb8c093b 4001 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 4002 /* Get next free Rx buffer, remove from free list */
b481de9c 4003 element = rxq->rx_free.next;
bb8c093b 4004 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 4005 list_del(element);
6440adb5
CB
4006
4007 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 4008 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY
4009 rxq->queue[rxq->write] = rxb;
4010 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
4011 rxq->free_count--;
4012 }
4013 spin_unlock_irqrestore(&rxq->lock, flags);
4014 /* If the pre-allocated buffer pool is dropping low, schedule to
4015 * refill it */
4016 if (rxq->free_count <= RX_LOW_WATERMARK)
4017 queue_work(priv->workqueue, &priv->rx_replenish);
4018
4019
6440adb5
CB
4020 /* If we've added more space for the firmware to place data, tell it.
4021 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY
4022 if ((write != (rxq->write & ~0x7))
4023 || (abs(rxq->write - rxq->read) > 7)) {
4024 spin_lock_irqsave(&rxq->lock, flags);
4025 rxq->need_update = 1;
4026 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 4027 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
4028 if (rc)
4029 return rc;
4030 }
4031
4032 return 0;
4033}
4034
4035/**
bb8c093b 4036 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
4037 *
4038 * When moving to rx_free an SKB is allocated for the slot.
4039 *
bb8c093b 4040 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 4041 * This is called as a scheduled work item (except for during initialization)
b481de9c 4042 */
5c0eef96 4043static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 4044{
bb8c093b 4045 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 4046 struct list_head *element;
bb8c093b 4047 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY
4048 unsigned long flags;
4049 spin_lock_irqsave(&rxq->lock, flags);
4050 while (!list_empty(&rxq->rx_used)) {
4051 element = rxq->rx_used.next;
bb8c093b 4052 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB
4053
4054 /* Alloc a new receive buffer */
b481de9c
ZY
4055 rxb->skb =
4056 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
4057 if (!rxb->skb) {
4058 if (net_ratelimit())
4059 printk(KERN_CRIT DRV_NAME
4060 ": Can not allocate SKB buffers\n");
4061 /* We don't reschedule replenish work here -- we will
4062 * call the restock method and if it still needs
4063 * more buffers it will schedule replenish */
4064 break;
4065 }
12342c47
ZY
4066
4067 /* If radiotap head is required, reserve some headroom here.
4068 * The physical head count is a variable rx_stats->phy_count.
4069 * We reserve 4 bytes here. Plus these extra bytes, the
4070 * headroom of the physical head should be enough for the
4071 * radiotap head that iwl3945 supported. See iwl3945_rt.
4072 */
4073 skb_reserve(rxb->skb, 4);
4074
b481de9c
ZY
4075 priv->alloc_rxb_skb++;
4076 list_del(element);
6440adb5
CB
4077
4078 /* Get physical address of RB/SKB */
b481de9c
ZY
4079 rxb->dma_addr =
4080 pci_map_single(priv->pci_dev, rxb->skb->data,
4081 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4082 list_add_tail(&rxb->list, &rxq->rx_free);
4083 rxq->free_count++;
4084 }
4085 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA
4086}
4087
4088/*
4089 * this should be called while priv->lock is locked
4090 */
4fd1f841 4091static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA
4092{
4093 struct iwl3945_priv *priv = data;
4094
4095 iwl3945_rx_allocate(priv);
4096 iwl3945_rx_queue_restock(priv);
4097}
4098
4099
4100void iwl3945_rx_replenish(void *data)
4101{
4102 struct iwl3945_priv *priv = data;
4103 unsigned long flags;
4104
4105 iwl3945_rx_allocate(priv);
b481de9c
ZY
4106
4107 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 4108 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
4109 spin_unlock_irqrestore(&priv->lock, flags);
4110}
4111
4112/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 4113 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY
4114 * This free routine walks the list of POOL entries and if SKB is set to
4115 * non NULL it is unmapped and freed
4116 */
bb8c093b 4117static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY
4118{
4119 int i;
4120 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
4121 if (rxq->pool[i].skb != NULL) {
4122 pci_unmap_single(priv->pci_dev,
4123 rxq->pool[i].dma_addr,
4124 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4125 dev_kfree_skb(rxq->pool[i].skb);
4126 }
4127 }
4128
4129 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4130 rxq->dma_addr);
4131 rxq->bd = NULL;
4132}
4133
bb8c093b 4134int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 4135{
bb8c093b 4136 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
4137 struct pci_dev *dev = priv->pci_dev;
4138 int i;
4139
4140 spin_lock_init(&rxq->lock);
4141 INIT_LIST_HEAD(&rxq->rx_free);
4142 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB
4143
4144 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY
4145 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
4146 if (!rxq->bd)
4147 return -ENOMEM;
6440adb5 4148
b481de9c
ZY
4149 /* Fill the rx_used queue with _all_ of the Rx buffers */
4150 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
4151 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 4152
b481de9c
ZY
4153 /* Set us so that we have processed and used all buffers, but have
4154 * not restocked the Rx queue with fresh buffers */
4155 rxq->read = rxq->write = 0;
4156 rxq->free_count = 0;
4157 rxq->need_update = 0;
4158 return 0;
4159}
4160
bb8c093b 4161void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY
4162{
4163 unsigned long flags;
4164 int i;
4165 spin_lock_irqsave(&rxq->lock, flags);
4166 INIT_LIST_HEAD(&rxq->rx_free);
4167 INIT_LIST_HEAD(&rxq->rx_used);
4168 /* Fill the rx_used queue with _all_ of the Rx buffers */
4169 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
4170 /* In the reset function, these buffers may have been allocated
4171 * to an SKB, so we need to unmap and free potential storage */
4172 if (rxq->pool[i].skb != NULL) {
4173 pci_unmap_single(priv->pci_dev,
4174 rxq->pool[i].dma_addr,
4175 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4176 priv->alloc_rxb_skb--;
4177 dev_kfree_skb(rxq->pool[i].skb);
4178 rxq->pool[i].skb = NULL;
4179 }
4180 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
4181 }
4182
4183 /* Set us so that we have processed and used all buffers, but have
4184 * not restocked the Rx queue with fresh buffers */
4185 rxq->read = rxq->write = 0;
4186 rxq->free_count = 0;
4187 spin_unlock_irqrestore(&rxq->lock, flags);
4188}
4189
4190/* Convert linear signal-to-noise ratio into dB */
4191static u8 ratio2dB[100] = {
4192/* 0 1 2 3 4 5 6 7 8 9 */
4193 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
4194 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
4195 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
4196 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
4197 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
4198 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
4199 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
4200 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
4201 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
4202 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4203};
4204
4205/* Calculates a relative dB value from a ratio of linear
4206 * (i.e. not dB) signal levels.
4207 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 4208int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c
ZY
4209{
4210 /* Anything above 1000:1 just report as 60 dB */
4211 if (sig_ratio > 1000)
4212 return 60;
4213
4214 /* Above 100:1, divide by 10 and use table,
4215 * add 20 dB to make up for divide by 10 */
4216 if (sig_ratio > 100)
4217 return (20 + (int)ratio2dB[sig_ratio/10]);
4218
4219 /* We shouldn't see this */
4220 if (sig_ratio < 1)
4221 return 0;
4222
4223 /* Use table for ratios 1:1 - 99:1 */
4224 return (int)ratio2dB[sig_ratio];
4225}
4226
4227#define PERFECT_RSSI (-20) /* dBm */
4228#define WORST_RSSI (-95) /* dBm */
4229#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
4230
4231/* Calculate an indication of rx signal quality (a percentage, not dBm!).
4232 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
4233 * about formulas used below. */
bb8c093b 4234int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
4235{
4236 int sig_qual;
4237 int degradation = PERFECT_RSSI - rssi_dbm;
4238
4239 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
4240 * as indicator; formula is (signal dbm - noise dbm).
4241 * SNR at or above 40 is a great signal (100%).
4242 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
4243 * Weakest usable signal is usually 10 - 15 dB SNR. */
4244 if (noise_dbm) {
4245 if (rssi_dbm - noise_dbm >= 40)
4246 return 100;
4247 else if (rssi_dbm < noise_dbm)
4248 return 0;
4249 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
4250
4251 /* Else use just the signal level.
4252 * This formula is a least squares fit of data points collected and
4253 * compared with a reference system that had a percentage (%) display
4254 * for signal quality. */
4255 } else
4256 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
4257 (15 * RSSI_RANGE + 62 * degradation)) /
4258 (RSSI_RANGE * RSSI_RANGE);
4259
4260 if (sig_qual > 100)
4261 sig_qual = 100;
4262 else if (sig_qual < 1)
4263 sig_qual = 0;
4264
4265 return sig_qual;
4266}
4267
4268/**
9fbab516 4269 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
4270 *
4271 * Uses the priv->rx_handlers callback function array to invoke
4272 * the appropriate handlers, including command responses,
4273 * frame-received notifications, and other notifications.
4274 */
bb8c093b 4275static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 4276{
bb8c093b
CH
4277 struct iwl3945_rx_mem_buffer *rxb;
4278 struct iwl3945_rx_packet *pkt;
4279 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
4280 u32 r, i;
4281 int reclaim;
4282 unsigned long flags;
5c0eef96
MA
4283 u8 fill_rx = 0;
4284 u32 count = 0;
b481de9c 4285
6440adb5
CB
4286 /* uCode's read index (stored in shared DRAM) indicates the last Rx
4287 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 4288 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY
4289 i = rxq->read;
4290
5c0eef96
MA
4291 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
4292 fill_rx = 1;
b481de9c
ZY
4293 /* Rx interrupt, but nothing sent from uCode */
4294 if (i == r)
4295 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
4296
4297 while (i != r) {
4298 rxb = rxq->queue[i];
4299
9fbab516 4300 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
4301 * then a bug has been introduced in the queue refilling
4302 * routines -- catch it here */
4303 BUG_ON(rxb == NULL);
4304
4305 rxq->queue[i] = NULL;
4306
4307 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
4308 IWL_RX_BUF_SIZE,
4309 PCI_DMA_FROMDEVICE);
bb8c093b 4310 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY
4311
4312 /* Reclaim a command buffer only if this packet is a response
4313 * to a (driver-originated) command.
4314 * If the packet (e.g. Rx frame) originated from uCode,
4315 * there is no command buffer to reclaim.
4316 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4317 * but apparently a few don't get set; catch them here. */
4318 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4319 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4320 (pkt->hdr.cmd != REPLY_TX);
4321
4322 /* Based on type of command response or notification,
4323 * handle those that need handling via function in
bb8c093b 4324 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY
4325 if (priv->rx_handlers[pkt->hdr.cmd]) {
4326 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4327 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4328 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4329 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4330 } else {
4331 /* No handling needed */
4332 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4333 "r %d i %d No handler needed for %s, 0x%02x\n",
4334 r, i, get_cmd_string(pkt->hdr.cmd),
4335 pkt->hdr.cmd);
4336 }
4337
4338 if (reclaim) {
9fbab516
BC
4339 /* Invoke any callbacks, transfer the skb to caller, and
4340 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY
4341 * as we reclaim the driver command queue */
4342 if (rxb && rxb->skb)
bb8c093b 4343 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY
4344 else
4345 IWL_WARNING("Claim null rxb?\n");
4346 }
4347
4348 /* For now we just don't re-use anything. We can tweak this
4349 * later to try and re-use notification packets and SKBs that
4350 * fail to Rx correctly */
4351 if (rxb->skb != NULL) {
4352 priv->alloc_rxb_skb--;
4353 dev_kfree_skb_any(rxb->skb);
4354 rxb->skb = NULL;
4355 }
4356
4357 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4358 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4359 spin_lock_irqsave(&rxq->lock, flags);
4360 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4361 spin_unlock_irqrestore(&rxq->lock, flags);
4362 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
4363 /* If there are a lot of unused frames,
4364 * restock the Rx queue so ucode won't assert. */
4365 if (fill_rx) {
4366 count++;
4367 if (count >= 8) {
4368 priv->rxq.read = i;
4369 __iwl3945_rx_replenish(priv);
4370 count = 0;
4371 }
4372 }
b481de9c
ZY
4373 }
4374
4375 /* Backtrack one entry */
4376 priv->rxq.read = i;
bb8c093b 4377 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
4378}
4379
6440adb5
CB
4380/**
4381 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4382 */
bb8c093b
CH
4383static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4384 struct iwl3945_tx_queue *txq)
b481de9c
ZY
4385{
4386 u32 reg = 0;
4387 int rc = 0;
4388 int txq_id = txq->q.id;
4389
4390 if (txq->need_update == 0)
4391 return rc;
4392
4393 /* if we're trying to save power */
4394 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4395 /* wake up nic if it's powered down ...
4396 * uCode will wake up, and interrupt us again, so next
4397 * time we'll skip this part. */
bb8c093b 4398 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
4399
4400 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4401 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4402 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
4403 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4404 return rc;
4405 }
4406
4407 /* restore this queue's parameters in nic hardware. */
bb8c093b 4408 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
4409 if (rc)
4410 return rc;
bb8c093b 4411 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4412 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4413 iwl3945_release_nic_access(priv);
b481de9c
ZY
4414
4415 /* else not in power-save mode, uCode will never sleep when we're
4416 * trying to tx (during RFKILL, we're not trying to tx). */
4417 } else
bb8c093b 4418 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4419 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY
4420
4421 txq->need_update = 0;
4422
4423 return rc;
4424}
4425
c8b0e6e1 4426#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4427static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4428{
0795af57
JP
4429 DECLARE_MAC_BUF(mac);
4430
b481de9c 4431 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4432 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY
4433 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4434 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4435 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4436 le32_to_cpu(rxon->filter_flags));
4437 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4438 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4439 rxon->ofdm_basic_rates);
4440 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP
4441 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4442 print_mac(mac, rxon->node_addr));
4443 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4444 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY
4445 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4446}
4447#endif
4448
bb8c093b 4449static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY
4450{
4451 IWL_DEBUG_ISR("Enabling interrupts\n");
4452 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4453 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY
4454}
4455
bb8c093b 4456static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY
4457{
4458 clear_bit(STATUS_INT_ENABLED, &priv->status);
4459
4460 /* disable interrupts from uCode/NIC to host */
bb8c093b 4461 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
4462
4463 /* acknowledge/clear/reset any interrupts still pending
4464 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH
4465 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4466 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY
4467 IWL_DEBUG_ISR("Disabled interrupts\n");
4468}
4469
4470static const char *desc_lookup(int i)
4471{
4472 switch (i) {
4473 case 1:
4474 return "FAIL";
4475 case 2:
4476 return "BAD_PARAM";
4477 case 3:
4478 return "BAD_CHECKSUM";
4479 case 4:
4480 return "NMI_INTERRUPT";
4481 case 5:
4482 return "SYSASSERT";
4483 case 6:
4484 return "FATAL_ERROR";
4485 }
4486
4487 return "UNKNOWN";
4488}
4489
4490#define ERROR_START_OFFSET (1 * sizeof(u32))
4491#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4492
bb8c093b 4493static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY
4494{
4495 u32 i;
4496 u32 desc, time, count, base, data1;
4497 u32 blink1, blink2, ilink1, ilink2;
4498 int rc;
4499
4500 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4501
bb8c093b 4502 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY
4503 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4504 return;
4505 }
4506
bb8c093b 4507 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
4508 if (rc) {
4509 IWL_WARNING("Can not read from adapter at this time.\n");
4510 return;
4511 }
4512
bb8c093b 4513 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY
4514
4515 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4516 IWL_ERROR("Start IWL Error Log Dump:\n");
4517 IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
4518 priv->status, priv->config, count);
4519 }
4520
4521 IWL_ERROR("Desc Time asrtPC blink2 "
4522 "ilink1 nmiPC Line\n");
4523 for (i = ERROR_START_OFFSET;
4524 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4525 i += ERROR_ELEM_SIZE) {
bb8c093b 4526 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4527 time =
bb8c093b 4528 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4529 blink1 =
bb8c093b 4530 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4531 blink2 =
bb8c093b 4532 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4533 ilink1 =
bb8c093b 4534 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4535 ilink2 =
bb8c093b 4536 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4537 data1 =
bb8c093b 4538 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY
4539
4540 IWL_ERROR
4541 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4542 desc_lookup(desc), desc, time, blink1, blink2,
4543 ilink1, ilink2, data1);
4544 }
4545
bb8c093b 4546 iwl3945_release_nic_access(priv);
b481de9c
ZY
4547
4548}
4549
f58177b9 4550#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
4551
4552/**
bb8c093b 4553 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4554 *
bb8c093b 4555 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4556 */
bb8c093b 4557static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY
4558 u32 num_events, u32 mode)
4559{
4560 u32 i;
4561 u32 base; /* SRAM byte address of event log header */
4562 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4563 u32 ptr; /* SRAM byte address of log data */
4564 u32 ev, time, data; /* event log data */
4565
4566 if (num_events == 0)
4567 return;
4568
4569 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4570
4571 if (mode == 0)
4572 event_size = 2 * sizeof(u32);
4573 else
4574 event_size = 3 * sizeof(u32);
4575
4576 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4577
4578 /* "time" is actually "data" for mode 0 (no timestamp).
4579 * place event id # at far right for easier visual parsing. */
4580 for (i = 0; i < num_events; i++) {
bb8c093b 4581 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4582 ptr += sizeof(u32);
bb8c093b 4583 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY
4584 ptr += sizeof(u32);
4585 if (mode == 0)
4586 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4587 else {
bb8c093b 4588 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY
4589 ptr += sizeof(u32);
4590 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4591 }
4592 }
4593}
4594
bb8c093b 4595static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY
4596{
4597 int rc;
4598 u32 base; /* SRAM byte address of event log header */
4599 u32 capacity; /* event log capacity in # entries */
4600 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4601 u32 num_wraps; /* # times uCode wrapped to top of log */
4602 u32 next_entry; /* index of next entry to be written by uCode */
4603 u32 size; /* # entries that we'll print */
4604
4605 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4606 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY
4607 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4608 return;
4609 }
4610
bb8c093b 4611 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
4612 if (rc) {
4613 IWL_WARNING("Can not read from adapter at this time.\n");
4614 return;
4615 }
4616
4617 /* event log header */
bb8c093b
CH
4618 capacity = iwl3945_read_targ_mem(priv, base);
4619 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4620 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4621 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
4622
4623 size = num_wraps ? capacity : next_entry;
4624
4625 /* bail out if nothing in log */
4626 if (size == 0) {
583fab37 4627 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4628 iwl3945_release_nic_access(priv);
b481de9c
ZY
4629 return;
4630 }
4631
583fab37 4632 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
4633 size, num_wraps);
4634
4635 /* if uCode has wrapped back to top of log, start at the oldest entry,
4636 * i.e the next one that uCode would fill. */
4637 if (num_wraps)
bb8c093b 4638 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
4639 capacity - next_entry, mode);
4640
4641 /* (then/else) start at top of log */
bb8c093b 4642 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4643
bb8c093b 4644 iwl3945_release_nic_access(priv);
b481de9c
ZY
4645}
4646
4647/**
bb8c093b 4648 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4649 */
bb8c093b 4650static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4651{
bb8c093b 4652 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY
4653 set_bit(STATUS_FW_ERROR, &priv->status);
4654
4655 /* Cancel currently queued command. */
4656 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4657
c8b0e6e1 4658#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
4659 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4660 iwl3945_dump_nic_error_log(priv);
4661 iwl3945_dump_nic_event_log(priv);
4662 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY
4663 }
4664#endif
4665
4666 wake_up_interruptible(&priv->wait_command_queue);
4667
4668 /* Keep the restart process from trying to send host
4669 * commands by clearing the INIT status bit */
4670 clear_bit(STATUS_READY, &priv->status);
4671
4672 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4673 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4674 "Restarting adapter due to uCode error.\n");
4675
bb8c093b 4676 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
4677 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4678 sizeof(priv->recovery_rxon));
4679 priv->error_recovering = 1;
4680 }
4681 queue_work(priv->workqueue, &priv->restart);
4682 }
4683}
4684
bb8c093b 4685static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY
4686{
4687 unsigned long flags;
4688
4689 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4690 sizeof(priv->staging_rxon));
4691 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4692 iwl3945_commit_rxon(priv);
b481de9c 4693
bb8c093b 4694 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY
4695
4696 spin_lock_irqsave(&priv->lock, flags);
4697 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4698 priv->error_recovering = 0;
4699 spin_unlock_irqrestore(&priv->lock, flags);
4700}
4701
bb8c093b 4702static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY
4703{
4704 u32 inta, handled = 0;
4705 u32 inta_fh;
4706 unsigned long flags;
c8b0e6e1 4707#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
4708 u32 inta_mask;
4709#endif
4710
4711 spin_lock_irqsave(&priv->lock, flags);
4712
4713 /* Ack/clear/reset pending uCode interrupts.
4714 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4715 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH
4716 inta = iwl3945_read32(priv, CSR_INT);
4717 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY
4718
4719 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4720 * Any new interrupts that happen after this, either while we're
4721 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH
4722 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4723 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4724
c8b0e6e1 4725#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4726 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC
4727 /* just for debug */
4728 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY
4729 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4730 inta, inta_mask, inta_fh);
4731 }
4732#endif
4733
4734 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4735 * atomic, make sure that inta covers all the interrupts that
4736 * we've discovered, even if FH interrupt came in just after
4737 * reading CSR_INT. */
4738 if (inta_fh & CSR_FH_INT_RX_MASK)
4739 inta |= CSR_INT_BIT_FH_RX;
4740 if (inta_fh & CSR_FH_INT_TX_MASK)
4741 inta |= CSR_INT_BIT_FH_TX;
4742
4743 /* Now service all interrupt bits discovered above. */
4744 if (inta & CSR_INT_BIT_HW_ERR) {
4745 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4746
4747 /* Tell the device to stop sending interrupts */
bb8c093b 4748 iwl3945_disable_interrupts(priv);
b481de9c 4749
bb8c093b 4750 iwl3945_irq_handle_error(priv);
b481de9c
ZY
4751
4752 handled |= CSR_INT_BIT_HW_ERR;
4753
4754 spin_unlock_irqrestore(&priv->lock, flags);
4755
4756 return;
4757 }
4758
c8b0e6e1 4759#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4760 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c
ZY
4761 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4762 if (inta & CSR_INT_BIT_MAC_CLK_ACTV)
4763 IWL_DEBUG_ISR("Microcode started or stopped.\n");
4764
4765 /* Alive notification via Rx interrupt will do the real work */
4766 if (inta & CSR_INT_BIT_ALIVE)
4767 IWL_DEBUG_ISR("Alive interrupt\n");
4768 }
4769#endif
4770 /* Safely ignore these bits for debug checks below */
4771 inta &= ~(CSR_INT_BIT_MAC_CLK_ACTV | CSR_INT_BIT_ALIVE);
4772
4773 /* HW RF KILL switch toggled (4965 only) */
4774 if (inta & CSR_INT_BIT_RF_KILL) {
4775 int hw_rf_kill = 0;
bb8c093b 4776 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
4777 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4778 hw_rf_kill = 1;
4779
4780 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4781 "RF_KILL bit toggled to %s.\n",
4782 hw_rf_kill ? "disable radio":"enable radio");
4783
4784 /* Queue restart only if RF_KILL switch was set to "kill"
4785 * when we loaded driver, and is now set to "enable".
4786 * After we're Alive, RF_KILL gets handled by
4787 * iwl_rx_card_state_notif() */
53e49093
ZY
4788 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4789 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4790 queue_work(priv->workqueue, &priv->restart);
53e49093 4791 }
b481de9c
ZY
4792
4793 handled |= CSR_INT_BIT_RF_KILL;
4794 }
4795
4796 /* Chip got too hot and stopped itself (4965 only) */
4797 if (inta & CSR_INT_BIT_CT_KILL) {
4798 IWL_ERROR("Microcode CT kill error detected.\n");
4799 handled |= CSR_INT_BIT_CT_KILL;
4800 }
4801
4802 /* Error detected by uCode */
4803 if (inta & CSR_INT_BIT_SW_ERR) {
4804 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4805 inta);
bb8c093b 4806 iwl3945_irq_handle_error(priv);
b481de9c
ZY
4807 handled |= CSR_INT_BIT_SW_ERR;
4808 }
4809
4810 /* uCode wakes up after power-down sleep */
4811 if (inta & CSR_INT_BIT_WAKEUP) {
4812 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH
4813 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4814 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4815 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4816 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4817 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4818 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4819 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY
4820
4821 handled |= CSR_INT_BIT_WAKEUP;
4822 }
4823
4824 /* All uCode command responses, including Tx command responses,
4825 * Rx "responses" (frame-received notification), and other
4826 * notifications from uCode come through here*/
4827 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4828 iwl3945_rx_handle(priv);
b481de9c
ZY
4829 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4830 }
4831
4832 if (inta & CSR_INT_BIT_FH_TX) {
4833 IWL_DEBUG_ISR("Tx interrupt\n");
4834
bb8c093b
CH
4835 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4836 if (!iwl3945_grab_nic_access(priv)) {
4837 iwl3945_write_direct32(priv,
b481de9c
ZY
4838 FH_TCSR_CREDIT
4839 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4840 iwl3945_release_nic_access(priv);
b481de9c
ZY
4841 }
4842 handled |= CSR_INT_BIT_FH_TX;
4843 }
4844
4845 if (inta & ~handled)
4846 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4847
4848 if (inta & ~CSR_INI_SET_MASK) {
4849 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4850 inta & ~CSR_INI_SET_MASK);
4851 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4852 }
4853
4854 /* Re-enable all interrupts */
bb8c093b 4855 iwl3945_enable_interrupts(priv);
b481de9c 4856
c8b0e6e1 4857#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
4858 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4859 inta = iwl3945_read32(priv, CSR_INT);
4860 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4861 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4862 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4863 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4864 }
4865#endif
4866 spin_unlock_irqrestore(&priv->lock, flags);
4867}
4868
bb8c093b 4869static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4870{
bb8c093b 4871 struct iwl3945_priv *priv = data;
b481de9c
ZY
4872 u32 inta, inta_mask;
4873 u32 inta_fh;
4874 if (!priv)
4875 return IRQ_NONE;
4876
4877 spin_lock(&priv->lock);
4878
4879 /* Disable (but don't clear!) interrupts here to avoid
4880 * back-to-back ISRs and sporadic interrupts from our NIC.
4881 * If we have something to service, the tasklet will re-enable ints.
4882 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH
4883 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4884 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
4885
4886 /* Discover which interrupts are active/pending */
bb8c093b
CH
4887 inta = iwl3945_read32(priv, CSR_INT);
4888 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4889
4890 /* Ignore interrupt if there's nothing in NIC to service.
4891 * This may be due to IRQ shared with another device,
4892 * or due to sporadic interrupts thrown from our NIC. */
4893 if (!inta && !inta_fh) {
4894 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4895 goto none;
4896 }
4897
4898 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4899 /* Hardware disappeared */
4900 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4901 goto unplugged;
b481de9c
ZY
4902 }
4903
4904 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4905 inta, inta_mask, inta_fh);
4906
bb8c093b 4907 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
b481de9c 4908 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4909unplugged:
b481de9c
ZY
4910 spin_unlock(&priv->lock);
4911
4912 return IRQ_HANDLED;
4913
4914 none:
4915 /* re-enable interrupts here since we don't have anything to service. */
bb8c093b 4916 iwl3945_enable_interrupts(priv);
b481de9c
ZY
4917 spin_unlock(&priv->lock);
4918 return IRQ_NONE;
4919}
4920
4921/************************** EEPROM BANDS ****************************
4922 *
bb8c093b 4923 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY
4924 * EEPROM contents to the specific channel number supported for each
4925 * band.
4926 *
bb8c093b 4927 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY
4928 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4929 * The specific geography and calibration information for that channel
4930 * is contained in the eeprom map itself.
4931 *
4932 * During init, we copy the eeprom information and channel map
4933 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4934 *
4935 * channel_map_24/52 provides the index in the channel_info array for a
4936 * given channel. We have to have two separate maps as there is channel
4937 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4938 * band_2
4939 *
4940 * A value of 0xff stored in the channel_map indicates that the channel
4941 * is not supported by the hardware at all.
4942 *
4943 * A value of 0xfe in the channel_map indicates that the channel is not
4944 * valid for Tx with the current hardware. This means that
4945 * while the system can tune and receive on a given channel, it may not
4946 * be able to associate or transmit any frames on that
4947 * channel. There is no corresponding channel information for that
4948 * entry.
4949 *
4950 *********************************************************************/
4951
4952/* 2.4 GHz */
bb8c093b 4953static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY
4954 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4955};
4956
4957/* 5.2 GHz bands */
9fbab516 4958static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY
4959 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4960};
4961
9fbab516 4962static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY
4963 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4964};
4965
bb8c093b 4966static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY
4967 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4968};
4969
bb8c093b 4970static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY
4971 145, 149, 153, 157, 161, 165
4972};
4973
bb8c093b 4974static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4975 int *eeprom_ch_count,
bb8c093b 4976 const struct iwl3945_eeprom_channel
b481de9c
ZY
4977 **eeprom_ch_info,
4978 const u8 **eeprom_ch_index)
4979{
4980 switch (band) {
4981 case 1: /* 2.4GHz band */
bb8c093b 4982 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4983 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4984 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4985 break;
9fbab516 4986 case 2: /* 4.9GHz band */
bb8c093b 4987 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4988 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4989 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY
4990 break;
4991 case 3: /* 5.2GHz band */
bb8c093b 4992 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4993 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4994 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4995 break;
9fbab516 4996 case 4: /* 5.5GHz band */
bb8c093b 4997 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4998 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4999 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 5000 break;
9fbab516 5001 case 5: /* 5.7GHz band */
bb8c093b 5002 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 5003 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 5004 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY
5005 break;
5006 default:
5007 BUG();
5008 return;
5009 }
5010}
5011
6440adb5
CB
5012/**
5013 * iwl3945_get_channel_info - Find driver's private channel info
5014 *
5015 * Based on band and channel number.
5016 */
bb8c093b 5017const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
b481de9c
ZY
5018 int phymode, u16 channel)
5019{
5020 int i;
5021
5022 switch (phymode) {
5023 case MODE_IEEE80211A:
5024 for (i = 14; i < priv->channel_count; i++) {
5025 if (priv->channel_info[i].channel == channel)
5026 return &priv->channel_info[i];
5027 }
5028 break;
5029
5030 case MODE_IEEE80211B:
5031 case MODE_IEEE80211G:
5032 if (channel >= 1 && channel <= 14)
5033 return &priv->channel_info[channel - 1];
5034 break;
5035
5036 }
5037
5038 return NULL;
5039}
5040
5041#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
5042 ? # x " " : "")
5043
6440adb5
CB
5044/**
5045 * iwl3945_init_channel_map - Set up driver's info for all possible channels
5046 */
bb8c093b 5047static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY
5048{
5049 int eeprom_ch_count = 0;
5050 const u8 *eeprom_ch_index = NULL;
bb8c093b 5051 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 5052 int band, ch;
bb8c093b 5053 struct iwl3945_channel_info *ch_info;
b481de9c
ZY
5054
5055 if (priv->channel_count) {
5056 IWL_DEBUG_INFO("Channel map already initialized.\n");
5057 return 0;
5058 }
5059
5060 if (priv->eeprom.version < 0x2f) {
5061 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
5062 priv->eeprom.version);
5063 return -EINVAL;
5064 }
5065
5066 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
5067
5068 priv->channel_count =
bb8c093b
CH
5069 ARRAY_SIZE(iwl3945_eeprom_band_1) +
5070 ARRAY_SIZE(iwl3945_eeprom_band_2) +
5071 ARRAY_SIZE(iwl3945_eeprom_band_3) +
5072 ARRAY_SIZE(iwl3945_eeprom_band_4) +
5073 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY
5074
5075 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
5076
bb8c093b 5077 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY
5078 priv->channel_count, GFP_KERNEL);
5079 if (!priv->channel_info) {
5080 IWL_ERROR("Could not allocate channel_info\n");
5081 priv->channel_count = 0;
5082 return -ENOMEM;
5083 }
5084
5085 ch_info = priv->channel_info;
5086
5087 /* Loop through the 5 EEPROM bands adding them in order to the
5088 * channel map we maintain (that contains additional information than
5089 * what just in the EEPROM) */
5090 for (band = 1; band <= 5; band++) {
5091
bb8c093b 5092 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY
5093 &eeprom_ch_info, &eeprom_ch_index);
5094
5095 /* Loop through each band adding each of the channels */
5096 for (ch = 0; ch < eeprom_ch_count; ch++) {
5097 ch_info->channel = eeprom_ch_index[ch];
5098 ch_info->phymode = (band == 1) ? MODE_IEEE80211B :
5099 MODE_IEEE80211A;
5100
5101 /* permanently store EEPROM's channel regulatory flags
5102 * and max power in channel info database. */
5103 ch_info->eeprom = eeprom_ch_info[ch];
5104
5105 /* Copy the run-time flags so they are there even on
5106 * invalid channels */
5107 ch_info->flags = eeprom_ch_info[ch].flags;
5108
5109 if (!(is_channel_valid(ch_info))) {
5110 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
5111 "No traffic\n",
5112 ch_info->channel,
5113 ch_info->flags,
5114 is_channel_a_band(ch_info) ?
5115 "5.2" : "2.4");
5116 ch_info++;
5117 continue;
5118 }
5119
5120 /* Initialize regulatory-based run-time data */
5121 ch_info->max_power_avg = ch_info->curr_txpow =
5122 eeprom_ch_info[ch].max_power_avg;
5123 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
5124 ch_info->min_power = 0;
5125
5126 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
5127 " %ddBm): Ad-Hoc %ssupported\n",
5128 ch_info->channel,
5129 is_channel_a_band(ch_info) ?
5130 "5.2" : "2.4",
5131 CHECK_AND_PRINT(IBSS),
5132 CHECK_AND_PRINT(ACTIVE),
5133 CHECK_AND_PRINT(RADAR),
5134 CHECK_AND_PRINT(WIDE),
5135 CHECK_AND_PRINT(NARROW),
5136 CHECK_AND_PRINT(DFS),
5137 eeprom_ch_info[ch].flags,
5138 eeprom_ch_info[ch].max_power_avg,
5139 ((eeprom_ch_info[ch].
5140 flags & EEPROM_CHANNEL_IBSS)
5141 && !(eeprom_ch_info[ch].
5142 flags & EEPROM_CHANNEL_RADAR))
5143 ? "" : "not ");
5144
5145 /* Set the user_txpower_limit to the highest power
5146 * supported by any channel */
5147 if (eeprom_ch_info[ch].max_power_avg >
5148 priv->user_txpower_limit)
5149 priv->user_txpower_limit =
5150 eeprom_ch_info[ch].max_power_avg;
5151
5152 ch_info++;
5153 }
5154 }
5155
6440adb5 5156 /* Set up txpower settings in driver for all channels */
b481de9c
ZY
5157 if (iwl3945_txpower_set_from_eeprom(priv))
5158 return -EIO;
5159
5160 return 0;
5161}
5162
849e0dce
RC
5163/*
5164 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
5165 */
5166static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
5167{
5168 kfree(priv->channel_info);
5169 priv->channel_count = 0;
5170}
5171
b481de9c
ZY
5172/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
5173 * sending probe req. This should be set long enough to hear probe responses
5174 * from more than one AP. */
5175#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
5176#define IWL_ACTIVE_DWELL_TIME_52 (10)
5177
5178/* For faster active scanning, scan will move to the next channel if fewer than
5179 * PLCP_QUIET_THRESH packets are heard on this channel within
5180 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
5181 * time if it's a quiet channel (nothing responded to our probe, and there's
5182 * no other traffic).
5183 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
5184#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
5185#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
5186
5187/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
5188 * Must be set longer than active dwell time.
5189 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
5190#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
5191#define IWL_PASSIVE_DWELL_TIME_52 (10)
5192#define IWL_PASSIVE_DWELL_BASE (100)
5193#define IWL_CHANNEL_TUNE_TIME 5
5194
bb8c093b 5195static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv, int phymode)
b481de9c
ZY
5196{
5197 if (phymode == MODE_IEEE80211A)
5198 return IWL_ACTIVE_DWELL_TIME_52;
5199 else
5200 return IWL_ACTIVE_DWELL_TIME_24;
5201}
5202
bb8c093b 5203static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv, int phymode)
b481de9c 5204{
bb8c093b 5205 u16 active = iwl3945_get_active_dwell_time(priv, phymode);
b481de9c
ZY
5206 u16 passive = (phymode != MODE_IEEE80211A) ?
5207 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
5208 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
5209
bb8c093b 5210 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
5211 /* If we're associated, we clamp the maximum passive
5212 * dwell time to be 98% of the beacon interval (minus
5213 * 2 * channel tune time) */
5214 passive = priv->beacon_int;
5215 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
5216 passive = IWL_PASSIVE_DWELL_BASE;
5217 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
5218 }
5219
5220 if (passive <= active)
5221 passive = active + 1;
5222
5223 return passive;
5224}
5225
bb8c093b 5226static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv, int phymode,
b481de9c 5227 u8 is_active, u8 direct_mask,
bb8c093b 5228 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY
5229{
5230 const struct ieee80211_channel *channels = NULL;
5231 const struct ieee80211_hw_mode *hw_mode;
bb8c093b 5232 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY
5233 u16 passive_dwell = 0;
5234 u16 active_dwell = 0;
5235 int added, i;
5236
bb8c093b 5237 hw_mode = iwl3945_get_hw_mode(priv, phymode);
b481de9c
ZY
5238 if (!hw_mode)
5239 return 0;
5240
5241 channels = hw_mode->channels;
5242
bb8c093b
CH
5243 active_dwell = iwl3945_get_active_dwell_time(priv, phymode);
5244 passive_dwell = iwl3945_get_passive_dwell_time(priv, phymode);
b481de9c
ZY
5245
5246 for (i = 0, added = 0; i < hw_mode->num_channels; i++) {
5247 if (channels[i].chan ==
5248 le16_to_cpu(priv->active_rxon.channel)) {
bb8c093b 5249 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
5250 IWL_DEBUG_SCAN
5251 ("Skipping current channel %d\n",
5252 le16_to_cpu(priv->active_rxon.channel));
5253 continue;
5254 }
5255 } else if (priv->only_active_channel)
5256 continue;
5257
5258 scan_ch->channel = channels[i].chan;
5259
bb8c093b 5260 ch_info = iwl3945_get_channel_info(priv, phymode, scan_ch->channel);
b481de9c
ZY
5261 if (!is_channel_valid(ch_info)) {
5262 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
5263 scan_ch->channel);
5264 continue;
5265 }
5266
5267 if (!is_active || is_channel_passive(ch_info) ||
5268 !(channels[i].flag & IEEE80211_CHAN_W_ACTIVE_SCAN))
5269 scan_ch->type = 0; /* passive */
5270 else
5271 scan_ch->type = 1; /* active */
5272
5273 if (scan_ch->type & 1)
5274 scan_ch->type |= (direct_mask << 1);
5275
5276 if (is_channel_narrow(ch_info))
5277 scan_ch->type |= (1 << 7);
5278
5279 scan_ch->active_dwell = cpu_to_le16(active_dwell);
5280 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
5281
9fbab516 5282 /* Set txpower levels to defaults */
b481de9c
ZY
5283 scan_ch->tpc.dsp_atten = 110;
5284 /* scan_pwr_info->tpc.dsp_atten; */
5285
5286 /*scan_pwr_info->tpc.tx_gain; */
5287 if (phymode == MODE_IEEE80211A)
5288 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
5289 else {
5290 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
5291 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 5292 * power level:
8a1b0245 5293 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
5294 */
5295 }
5296
5297 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5298 scan_ch->channel,
5299 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5300 (scan_ch->type & 1) ?
5301 active_dwell : passive_dwell);
5302
5303 scan_ch++;
5304 added++;
5305 }
5306
5307 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5308 return added;
5309}
5310
bb8c093b 5311static void iwl3945_reset_channel_flag(struct iwl3945_priv *priv)
b481de9c
ZY
5312{
5313 int i, j;
5314 for (i = 0; i < 3; i++) {
5315 struct ieee80211_hw_mode *hw_mode = (void *)&priv->modes[i];
5316 for (j = 0; j < hw_mode->num_channels; j++)
5317 hw_mode->channels[j].flag = hw_mode->channels[j].val;
5318 }
5319}
5320
bb8c093b 5321static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY
5322 struct ieee80211_rate *rates)
5323{
5324 int i;
5325
5326 for (i = 0; i < IWL_RATE_COUNT; i++) {
bb8c093b 5327 rates[i].rate = iwl3945_rates[i].ieee * 5;
b481de9c
ZY
5328 rates[i].val = i; /* Rate scaling will work on indexes */
5329 rates[i].val2 = i;
5330 rates[i].flags = IEEE80211_RATE_SUPPORTED;
5331 /* Only OFDM have the bits-per-symbol set */
5332 if ((i <= IWL_LAST_OFDM_RATE) && (i >= IWL_FIRST_OFDM_RATE))
5333 rates[i].flags |= IEEE80211_RATE_OFDM;
5334 else {
5335 /*
5336 * If CCK 1M then set rate flag to CCK else CCK_2
5337 * which is CCK | PREAMBLE2
5338 */
bb8c093b 5339 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
b481de9c
ZY
5340 IEEE80211_RATE_CCK : IEEE80211_RATE_CCK_2;
5341 }
5342
5343 /* Set up which ones are basic rates... */
5344 if (IWL_BASIC_RATES_MASK & (1 << i))
5345 rates[i].flags |= IEEE80211_RATE_BASIC;
5346 }
5347}
5348
5349/**
bb8c093b 5350 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5351 */
bb8c093b 5352static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5353{
bb8c093b 5354 struct iwl3945_channel_info *ch;
b481de9c
ZY
5355 struct ieee80211_hw_mode *modes;
5356 struct ieee80211_channel *channels;
5357 struct ieee80211_channel *geo_ch;
5358 struct ieee80211_rate *rates;
5359 int i = 0;
5360 enum {
5361 A = 0,
5362 B = 1,
5363 G = 2,
5364 };
5365 int mode_count = 3;
5366
5367 if (priv->modes) {
5368 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5369 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5370 return 0;
5371 }
5372
5373 modes = kzalloc(sizeof(struct ieee80211_hw_mode) * mode_count,
5374 GFP_KERNEL);
5375 if (!modes)
5376 return -ENOMEM;
5377
5378 channels = kzalloc(sizeof(struct ieee80211_channel) *
5379 priv->channel_count, GFP_KERNEL);
5380 if (!channels) {
5381 kfree(modes);
5382 return -ENOMEM;
5383 }
5384
5385 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
5386 GFP_KERNEL);
5387 if (!rates) {
5388 kfree(modes);
5389 kfree(channels);
5390 return -ENOMEM;
5391 }
5392
5393 /* 0 = 802.11a
5394 * 1 = 802.11b
5395 * 2 = 802.11g
5396 */
5397
5398 /* 5.2GHz channels start after the 2.4GHz channels */
5399 modes[A].mode = MODE_IEEE80211A;
bb8c093b 5400 modes[A].channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
14577f23 5401 modes[A].rates = &rates[4];
b481de9c
ZY
5402 modes[A].num_rates = 8; /* just OFDM */
5403 modes[A].num_channels = 0;
5404
5405 modes[B].mode = MODE_IEEE80211B;
5406 modes[B].channels = channels;
14577f23 5407 modes[B].rates = rates;
b481de9c
ZY
5408 modes[B].num_rates = 4; /* just CCK */
5409 modes[B].num_channels = 0;
5410
5411 modes[G].mode = MODE_IEEE80211G;
5412 modes[G].channels = channels;
5413 modes[G].rates = rates;
5414 modes[G].num_rates = 12; /* OFDM & CCK */
5415 modes[G].num_channels = 0;
5416
5417 priv->ieee_channels = channels;
5418 priv->ieee_rates = rates;
5419
bb8c093b 5420 iwl3945_init_hw_rates(priv, rates);
b481de9c
ZY
5421
5422 for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
5423 ch = &priv->channel_info[i];
5424
5425 if (!is_channel_valid(ch)) {
5426 IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
5427 "skipping.\n",
5428 ch->channel, is_channel_a_band(ch) ?
5429 "5.2" : "2.4");
5430 continue;
5431 }
5432
5433 if (is_channel_a_band(ch))
5434 geo_ch = &modes[A].channels[modes[A].num_channels++];
5435 else {
5436 geo_ch = &modes[B].channels[modes[B].num_channels++];
5437 modes[G].num_channels++;
5438 }
5439
5440 geo_ch->freq = ieee80211chan2mhz(ch->channel);
5441 geo_ch->chan = ch->channel;
5442 geo_ch->power_level = ch->max_power_avg;
5443 geo_ch->antenna_max = 0xff;
5444
5445 if (is_channel_valid(ch)) {
5446 geo_ch->flag = IEEE80211_CHAN_W_SCAN;
5447 if (ch->flags & EEPROM_CHANNEL_IBSS)
5448 geo_ch->flag |= IEEE80211_CHAN_W_IBSS;
5449
5450 if (ch->flags & EEPROM_CHANNEL_ACTIVE)
5451 geo_ch->flag |= IEEE80211_CHAN_W_ACTIVE_SCAN;
5452
5453 if (ch->flags & EEPROM_CHANNEL_RADAR)
5454 geo_ch->flag |= IEEE80211_CHAN_W_RADAR_DETECT;
5455
5456 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5457 priv->max_channel_txpower_limit =
5458 ch->max_power_avg;
5459 }
5460
5461 geo_ch->val = geo_ch->flag;
5462 }
5463
5464 if ((modes[A].num_channels == 0) && priv->is_abg) {
5465 printk(KERN_INFO DRV_NAME
5466 ": Incorrectly detected BG card as ABG. Please send "
5467 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5468 priv->pci_dev->device, priv->pci_dev->subsystem_device);
5469 priv->is_abg = 0;
5470 }
5471
5472 printk(KERN_INFO DRV_NAME
5473 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
5474 modes[G].num_channels, modes[A].num_channels);
5475
5476 /*
5477 * NOTE: We register these in preference of order -- the
5478 * stack doesn't currently (as of 7.0.6 / Apr 24 '07) pick
5479 * a phymode based on rates or AP capabilities but seems to
5480 * configure it purely on if the channel being configured
5481 * is supported by a mode -- and the first match is taken
5482 */
5483
5484 if (modes[G].num_channels)
5485 ieee80211_register_hwmode(priv->hw, &modes[G]);
5486 if (modes[B].num_channels)
5487 ieee80211_register_hwmode(priv->hw, &modes[B]);
5488 if (modes[A].num_channels)
5489 ieee80211_register_hwmode(priv->hw, &modes[A]);
5490
5491 priv->modes = modes;
5492 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5493
5494 return 0;
5495}
5496
849e0dce
RC
5497/*
5498 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5499 */
5500static void iwl3945_free_geos(struct iwl3945_priv *priv)
5501{
5502 kfree(priv->modes);
5503 kfree(priv->ieee_channels);
5504 kfree(priv->ieee_rates);
5505 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5506}
5507
b481de9c
ZY
5508/******************************************************************************
5509 *
5510 * uCode download functions
5511 *
5512 ******************************************************************************/
5513
bb8c093b 5514static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5515{
98c92211
TW
5516 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5517 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5518 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5519 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5520 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5521 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
5522}
5523
5524/**
bb8c093b 5525 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
5526 * looking at all data.
5527 */
bb8c093b 5528static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY
5529{
5530 u32 val;
5531 u32 save_len = len;
5532 int rc = 0;
5533 u32 errcnt;
5534
5535 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5536
bb8c093b 5537 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5538 if (rc)
5539 return rc;
5540
bb8c093b 5541 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY
5542
5543 errcnt = 0;
5544 for (; len > 0; len -= sizeof(u32), image++) {
5545 /* read data comes through single port, auto-incr addr */
5546 /* NOTE: Use the debugless read so we don't flood kernel log
5547 * if IWL_DL_IO is set */
bb8c093b 5548 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
5549 if (val != le32_to_cpu(*image)) {
5550 IWL_ERROR("uCode INST section is invalid at "
5551 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5552 save_len - len, val, le32_to_cpu(*image));
5553 rc = -EIO;
5554 errcnt++;
5555 if (errcnt >= 20)
5556 break;
5557 }
5558 }
5559
bb8c093b 5560 iwl3945_release_nic_access(priv);
b481de9c
ZY
5561
5562 if (!errcnt)
bc434dd2 5563 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
5564
5565 return rc;
5566}
5567
5568
5569/**
bb8c093b 5570 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
5571 * using sample data 100 bytes apart. If these sample points are good,
5572 * it's a pretty good bet that everything between them is good, too.
5573 */
bb8c093b 5574static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
5575{
5576 u32 val;
5577 int rc = 0;
5578 u32 errcnt = 0;
5579 u32 i;
5580
5581 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5582
bb8c093b 5583 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5584 if (rc)
5585 return rc;
5586
5587 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5588 /* read data comes through single port, auto-incr addr */
5589 /* NOTE: Use the debugless read so we don't flood kernel log
5590 * if IWL_DL_IO is set */
bb8c093b 5591 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5592 i + RTC_INST_LOWER_BOUND);
bb8c093b 5593 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
5594 if (val != le32_to_cpu(*image)) {
5595#if 0 /* Enable this if you want to see details */
5596 IWL_ERROR("uCode INST section is invalid at "
5597 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5598 i, val, *image);
5599#endif
5600 rc = -EIO;
5601 errcnt++;
5602 if (errcnt >= 3)
5603 break;
5604 }
5605 }
5606
bb8c093b 5607 iwl3945_release_nic_access(priv);
b481de9c
ZY
5608
5609 return rc;
5610}
5611
5612
5613/**
bb8c093b 5614 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
5615 * and verify its contents
5616 */
bb8c093b 5617static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY
5618{
5619 __le32 *image;
5620 u32 len;
5621 int rc = 0;
5622
5623 /* Try bootstrap */
5624 image = (__le32 *)priv->ucode_boot.v_addr;
5625 len = priv->ucode_boot.len;
bb8c093b 5626 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5627 if (rc == 0) {
5628 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5629 return 0;
5630 }
5631
5632 /* Try initialize */
5633 image = (__le32 *)priv->ucode_init.v_addr;
5634 len = priv->ucode_init.len;
bb8c093b 5635 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5636 if (rc == 0) {
5637 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5638 return 0;
5639 }
5640
5641 /* Try runtime/protocol */
5642 image = (__le32 *)priv->ucode_code.v_addr;
5643 len = priv->ucode_code.len;
bb8c093b 5644 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5645 if (rc == 0) {
5646 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5647 return 0;
5648 }
5649
5650 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5651
9fbab516
BC
5652 /* Since nothing seems to match, show first several data entries in
5653 * instruction SRAM, so maybe visual inspection will give a clue.
5654 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
5655 image = (__le32 *)priv->ucode_boot.v_addr;
5656 len = priv->ucode_boot.len;
bb8c093b 5657 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
5658
5659 return rc;
5660}
5661
5662
5663/* check contents of special bootstrap uCode SRAM */
bb8c093b 5664static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY
5665{
5666 __le32 *image = priv->ucode_boot.v_addr;
5667 u32 len = priv->ucode_boot.len;
5668 u32 reg;
5669 u32 val;
5670
5671 IWL_DEBUG_INFO("Begin verify bsm\n");
5672
5673 /* verify BSM SRAM contents */
bb8c093b 5674 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY
5675 for (reg = BSM_SRAM_LOWER_BOUND;
5676 reg < BSM_SRAM_LOWER_BOUND + len;
5677 reg += sizeof(u32), image ++) {
bb8c093b 5678 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY
5679 if (val != le32_to_cpu(*image)) {
5680 IWL_ERROR("BSM uCode verification failed at "
5681 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5682 BSM_SRAM_LOWER_BOUND,
5683 reg - BSM_SRAM_LOWER_BOUND, len,
5684 val, le32_to_cpu(*image));
5685 return -EIO;
5686 }
5687 }
5688
5689 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5690
5691 return 0;
5692}
5693
5694/**
bb8c093b 5695 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY
5696 *
5697 * BSM operation:
5698 *
5699 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5700 * in special SRAM that does not power down during RFKILL. When powering back
5701 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5702 * the bootstrap program into the on-board processor, and starts it.
5703 *
5704 * The bootstrap program loads (via DMA) instructions and data for a new
5705 * program from host DRAM locations indicated by the host driver in the
5706 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5707 * automatically.
5708 *
5709 * When initializing the NIC, the host driver points the BSM to the
5710 * "initialize" uCode image. This uCode sets up some internal data, then
5711 * notifies host via "initialize alive" that it is complete.
5712 *
5713 * The host then replaces the BSM_DRAM_* pointer values to point to the
5714 * normal runtime uCode instructions and a backup uCode data cache buffer
5715 * (filled initially with starting data values for the on-board processor),
5716 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5717 * which begins normal operation.
5718 *
5719 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5720 * the backup data cache in DRAM before SRAM is powered down.
5721 *
5722 * When powering back up, the BSM loads the bootstrap program. This reloads
5723 * the runtime uCode instructions and the backup data cache into SRAM,
5724 * and re-launches the runtime uCode from where it left off.
5725 */
bb8c093b 5726static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY
5727{
5728 __le32 *image = priv->ucode_boot.v_addr;
5729 u32 len = priv->ucode_boot.len;
5730 dma_addr_t pinst;
5731 dma_addr_t pdata;
5732 u32 inst_len;
5733 u32 data_len;
5734 int rc;
5735 int i;
5736 u32 done;
5737 u32 reg_offset;
5738
5739 IWL_DEBUG_INFO("Begin load bsm\n");
5740
5741 /* make sure bootstrap program is no larger than BSM's SRAM size */
5742 if (len > IWL_MAX_BSM_SIZE)
5743 return -EINVAL;
5744
5745 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5746 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5747 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY
5748 * after the "initialize" uCode has run, to point to
5749 * runtime/protocol instructions and backup data cache. */
5750 pinst = priv->ucode_init.p_addr;
5751 pdata = priv->ucode_init_data.p_addr;
5752 inst_len = priv->ucode_init.len;
5753 data_len = priv->ucode_init_data.len;
5754
bb8c093b 5755 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5756 if (rc)
5757 return rc;
5758
bb8c093b
CH
5759 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5760 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5761 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5762 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY
5763
5764 /* Fill BSM memory with bootstrap instructions */
5765 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5766 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5767 reg_offset += sizeof(u32), image++)
bb8c093b 5768 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY
5769 le32_to_cpu(*image));
5770
bb8c093b 5771 rc = iwl3945_verify_bsm(priv);
b481de9c 5772 if (rc) {
bb8c093b 5773 iwl3945_release_nic_access(priv);
b481de9c
ZY
5774 return rc;
5775 }
5776
5777 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH
5778 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5779 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5780 RTC_INST_LOWER_BOUND);
bb8c093b 5781 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY
5782
5783 /* Load bootstrap code into instruction SRAM now,
5784 * to prepare to load "initialize" uCode */
bb8c093b 5785 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY
5786 BSM_WR_CTRL_REG_BIT_START);
5787
5788 /* Wait for load of bootstrap uCode to finish */
5789 for (i = 0; i < 100; i++) {
bb8c093b 5790 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY
5791 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5792 break;
5793 udelay(10);
5794 }
5795 if (i < 100)
5796 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5797 else {
5798 IWL_ERROR("BSM write did not complete!\n");
5799 return -EIO;
5800 }
5801
5802 /* Enable future boot loads whenever power management unit triggers it
5803 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5804 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY
5805 BSM_WR_CTRL_REG_BIT_START_EN);
5806
bb8c093b 5807 iwl3945_release_nic_access(priv);
b481de9c
ZY
5808
5809 return 0;
5810}
5811
bb8c093b 5812static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY
5813{
5814 /* Remove all resets to allow NIC to operate */
bb8c093b 5815 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY
5816}
5817
5818/**
bb8c093b 5819 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
5820 *
5821 * Copy into buffers for card to fetch via bus-mastering
5822 */
bb8c093b 5823static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5824{
bb8c093b 5825 struct iwl3945_ucode *ucode;
90e759d1 5826 int ret = 0;
b481de9c
ZY
5827 const struct firmware *ucode_raw;
5828 /* firmware file name contains uCode/driver compatibility version */
5829 const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
5830 u8 *src;
5831 size_t len;
5832 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5833
5834 /* Ask kernel firmware_class module to get the boot firmware off disk.
5835 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW
5836 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5837 if (ret < 0) {
5838 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5839 name, ret);
b481de9c
ZY
5840 goto error;
5841 }
5842
5843 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5844 name, ucode_raw->size);
5845
5846 /* Make sure that we got at least our header! */
5847 if (ucode_raw->size < sizeof(*ucode)) {
5848 IWL_ERROR("File size way too small!\n");
90e759d1 5849 ret = -EINVAL;
b481de9c
ZY
5850 goto err_release;
5851 }
5852
5853 /* Data from ucode file: header followed by uCode images */
5854 ucode = (void *)ucode_raw->data;
5855
5856 ver = le32_to_cpu(ucode->ver);
5857 inst_size = le32_to_cpu(ucode->inst_size);
5858 data_size = le32_to_cpu(ucode->data_size);
5859 init_size = le32_to_cpu(ucode->init_size);
5860 init_data_size = le32_to_cpu(ucode->init_data_size);
5861 boot_size = le32_to_cpu(ucode->boot_size);
5862
5863 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS
5864 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5865 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5866 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5867 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5868 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY
5869
5870 /* Verify size of file vs. image size info in file's header */
5871 if (ucode_raw->size < sizeof(*ucode) +
5872 inst_size + data_size + init_size +
5873 init_data_size + boot_size) {
5874
5875 IWL_DEBUG_INFO("uCode file size %d too small\n",
5876 (int)ucode_raw->size);
90e759d1 5877 ret = -EINVAL;
b481de9c
ZY
5878 goto err_release;
5879 }
5880
5881 /* Verify that uCode images will fit in card's SRAM */
5882 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW
5883 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5884 inst_size);
5885 ret = -EINVAL;
b481de9c
ZY
5886 goto err_release;
5887 }
5888
5889 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW
5890 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5891 data_size);
5892 ret = -EINVAL;
b481de9c
ZY
5893 goto err_release;
5894 }
5895 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW
5896 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5897 init_size);
5898 ret = -EINVAL;
b481de9c
ZY
5899 goto err_release;
5900 }
5901 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW
5902 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5903 init_data_size);
5904 ret = -EINVAL;
b481de9c
ZY
5905 goto err_release;
5906 }
5907 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW
5908 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5909 boot_size);
5910 ret = -EINVAL;
b481de9c
ZY
5911 goto err_release;
5912 }
5913
5914 /* Allocate ucode buffers for card's bus-master loading ... */
5915
5916 /* Runtime instructions and 2 copies of data:
5917 * 1) unmodified from disk
5918 * 2) backup cache for save/restore during power-downs */
5919 priv->ucode_code.len = inst_size;
98c92211 5920 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
5921
5922 priv->ucode_data.len = data_size;
98c92211 5923 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
5924
5925 priv->ucode_data_backup.len = data_size;
98c92211 5926 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5927
90e759d1
TW
5928 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5929 !priv->ucode_data_backup.v_addr)
5930 goto err_pci_alloc;
b481de9c
ZY
5931
5932 /* Initialization instructions and data */
90e759d1
TW
5933 if (init_size && init_data_size) {
5934 priv->ucode_init.len = init_size;
98c92211 5935 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
5936
5937 priv->ucode_init_data.len = init_data_size;
98c92211 5938 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
5939
5940 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5941 goto err_pci_alloc;
5942 }
b481de9c
ZY
5943
5944 /* Bootstrap (instructions only, no data) */
90e759d1
TW
5945 if (boot_size) {
5946 priv->ucode_boot.len = boot_size;
98c92211 5947 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5948
90e759d1
TW
5949 if (!priv->ucode_boot.v_addr)
5950 goto err_pci_alloc;
5951 }
b481de9c
ZY
5952
5953 /* Copy images into buffers for card's bus-master reads ... */
5954
5955 /* Runtime instructions (first block of data in file) */
5956 src = &ucode->data[0];
5957 len = priv->ucode_code.len;
90e759d1 5958 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY
5959 memcpy(priv->ucode_code.v_addr, src, len);
5960 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5961 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5962
5963 /* Runtime data (2nd block)
bb8c093b 5964 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY
5965 src = &ucode->data[inst_size];
5966 len = priv->ucode_data.len;
90e759d1 5967 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
5968 memcpy(priv->ucode_data.v_addr, src, len);
5969 memcpy(priv->ucode_data_backup.v_addr, src, len);
5970
5971 /* Initialization instructions (3rd block) */
5972 if (init_size) {
5973 src = &ucode->data[inst_size + data_size];
5974 len = priv->ucode_init.len;
90e759d1
TW
5975 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5976 len);
b481de9c
ZY
5977 memcpy(priv->ucode_init.v_addr, src, len);
5978 }
5979
5980 /* Initialization data (4th block) */
5981 if (init_data_size) {
5982 src = &ucode->data[inst_size + data_size + init_size];
5983 len = priv->ucode_init_data.len;
5984 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5985 (int)len);
5986 memcpy(priv->ucode_init_data.v_addr, src, len);
5987 }
5988
5989 /* Bootstrap instructions (5th block) */
5990 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5991 len = priv->ucode_boot.len;
5992 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5993 (int)len);
5994 memcpy(priv->ucode_boot.v_addr, src, len);
5995
5996 /* We have our copies now, allow OS release its copies */
5997 release_firmware(ucode_raw);
5998 return 0;
5999
6000 err_pci_alloc:
6001 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 6002 ret = -ENOMEM;
bb8c093b 6003 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
6004
6005 err_release:
6006 release_firmware(ucode_raw);
6007
6008 error:
90e759d1 6009 return ret;
b481de9c
ZY
6010}
6011
6012
6013/**
bb8c093b 6014 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
6015 *
6016 * Tell initialization uCode where to find runtime uCode.
6017 *
6018 * BSM registers initially contain pointers to initialization uCode.
6019 * We need to replace them to load runtime uCode inst and data,
6020 * and to save runtime data when powering down.
6021 */
bb8c093b 6022static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY
6023{
6024 dma_addr_t pinst;
6025 dma_addr_t pdata;
6026 int rc = 0;
6027 unsigned long flags;
6028
6029 /* bits 31:0 for 3945 */
6030 pinst = priv->ucode_code.p_addr;
6031 pdata = priv->ucode_data_backup.p_addr;
6032
6033 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 6034 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
6035 if (rc) {
6036 spin_unlock_irqrestore(&priv->lock, flags);
6037 return rc;
6038 }
6039
6040 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH
6041 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
6042 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
6043 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
6044 priv->ucode_data.len);
6045
6046 /* Inst bytecount must be last to set up, bit 31 signals uCode
6047 * that all new ptr/size info is in place */
bb8c093b 6048 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
6049 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
6050
bb8c093b 6051 iwl3945_release_nic_access(priv);
b481de9c
ZY
6052
6053 spin_unlock_irqrestore(&priv->lock, flags);
6054
6055 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
6056
6057 return rc;
6058}
6059
6060/**
bb8c093b 6061 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
6062 *
6063 * Called after REPLY_ALIVE notification received from "initialize" uCode.
6064 *
b481de9c 6065 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 6066 */
bb8c093b 6067static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY
6068{
6069 /* Check alive response for "valid" sign from uCode */
6070 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
6071 /* We had an error bringing up the hardware, so take it
6072 * all the way back down so we can try again */
6073 IWL_DEBUG_INFO("Initialize Alive failed.\n");
6074 goto restart;
6075 }
6076
6077 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
6078 * This is a paranoid check, because we would not have gotten the
6079 * "initialize" alive if code weren't properly loaded. */
bb8c093b 6080 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
6081 /* Runtime instruction load was bad;
6082 * take it all the way back down so we can try again */
6083 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
6084 goto restart;
6085 }
6086
6087 /* Send pointers to protocol/runtime uCode image ... init code will
6088 * load and launch runtime uCode, which will send us another "Alive"
6089 * notification. */
6090 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 6091 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
6092 /* Runtime instruction load won't happen;
6093 * take it all the way back down so we can try again */
6094 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
6095 goto restart;
6096 }
6097 return;
6098
6099 restart:
6100 queue_work(priv->workqueue, &priv->restart);
6101}
6102
6103
6104/**
bb8c093b 6105 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 6106 * from protocol/runtime uCode (initialization uCode's
bb8c093b 6107 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 6108 */
bb8c093b 6109static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY
6110{
6111 int rc = 0;
6112 int thermal_spin = 0;
6113 u32 rfkill;
6114
6115 IWL_DEBUG_INFO("Runtime Alive received.\n");
6116
6117 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
6118 /* We had an error bringing up the hardware, so take it
6119 * all the way back down so we can try again */
6120 IWL_DEBUG_INFO("Alive failed.\n");
6121 goto restart;
6122 }
6123
6124 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
6125 * This is a paranoid check, because we would not have gotten the
6126 * "runtime" alive if code weren't properly loaded. */
bb8c093b 6127 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
6128 /* Runtime instruction load was bad;
6129 * take it all the way back down so we can try again */
6130 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
6131 goto restart;
6132 }
6133
bb8c093b 6134 iwl3945_clear_stations_table(priv);
b481de9c 6135
bb8c093b 6136 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
6137 if (rc) {
6138 IWL_WARNING("Can not read rfkill status from adapter\n");
6139 return;
6140 }
6141
bb8c093b 6142 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 6143 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 6144 iwl3945_release_nic_access(priv);
b481de9c
ZY
6145
6146 if (rfkill & 0x1) {
6147 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6148 /* if rfkill is not on, then wait for thermal
6149 * sensor in adapter to kick in */
bb8c093b 6150 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
6151 thermal_spin++;
6152 udelay(10);
6153 }
6154
6155 if (thermal_spin)
6156 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
6157 thermal_spin * 10);
6158 } else
6159 set_bit(STATUS_RF_KILL_HW, &priv->status);
6160
9fbab516 6161 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
6162 set_bit(STATUS_ALIVE, &priv->status);
6163
6164 /* Clear out the uCode error bit if it is set */
6165 clear_bit(STATUS_FW_ERROR, &priv->status);
6166
bb8c093b 6167 if (iwl3945_is_rfkill(priv))
b481de9c
ZY
6168 return;
6169
5a66926a 6170 ieee80211_start_queues(priv->hw);
b481de9c
ZY
6171
6172 priv->active_rate = priv->rates_mask;
6173 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
6174
bb8c093b 6175 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 6176
bb8c093b
CH
6177 if (iwl3945_is_associated(priv)) {
6178 struct iwl3945_rxon_cmd *active_rxon =
6179 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY
6180
6181 memcpy(&priv->staging_rxon, &priv->active_rxon,
6182 sizeof(priv->staging_rxon));
6183 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6184 } else {
6185 /* Initialize our rx_config data */
bb8c093b 6186 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY
6187 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
6188 }
6189
9fbab516 6190 /* Configure Bluetooth device coexistence support */
bb8c093b 6191 iwl3945_send_bt_config(priv);
b481de9c
ZY
6192
6193 /* Configure the adapter for unassociated operation */
bb8c093b 6194 iwl3945_commit_rxon(priv);
b481de9c
ZY
6195
6196 /* At this point, the NIC is initialized and operational */
6197 priv->notif_missed_beacons = 0;
6198 set_bit(STATUS_READY, &priv->status);
6199
6200 iwl3945_reg_txpower_periodic(priv);
6201
6202 IWL_DEBUG_INFO("ALIVE processing complete.\n");
5a66926a 6203 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
6204
6205 if (priv->error_recovering)
bb8c093b 6206 iwl3945_error_recovery(priv);
b481de9c
ZY
6207
6208 return;
6209
6210 restart:
6211 queue_work(priv->workqueue, &priv->restart);
6212}
6213
bb8c093b 6214static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 6215
bb8c093b 6216static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY
6217{
6218 unsigned long flags;
6219 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
6220 struct ieee80211_conf *conf = NULL;
6221
6222 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
6223
6224 conf = ieee80211_get_hw_conf(priv->hw);
6225
6226 if (!exit_pending)
6227 set_bit(STATUS_EXIT_PENDING, &priv->status);
6228
bb8c093b 6229 iwl3945_clear_stations_table(priv);
b481de9c
ZY
6230
6231 /* Unblock any waiting calls */
6232 wake_up_interruptible_all(&priv->wait_command_queue);
6233
b481de9c
ZY
6234 /* Wipe out the EXIT_PENDING status bit if we are not actually
6235 * exiting the module */
6236 if (!exit_pending)
6237 clear_bit(STATUS_EXIT_PENDING, &priv->status);
6238
6239 /* stop and reset the on-board processor */
bb8c093b 6240 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
6241
6242 /* tell the device to stop sending interrupts */
bb8c093b 6243 iwl3945_disable_interrupts(priv);
b481de9c
ZY
6244
6245 if (priv->mac80211_registered)
6246 ieee80211_stop_queues(priv->hw);
6247
bb8c093b 6248 /* If we have not previously called iwl3945_init() then
b481de9c 6249 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 6250 if (!iwl3945_is_init(priv)) {
b481de9c
ZY
6251 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6252 STATUS_RF_KILL_HW |
6253 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6254 STATUS_RF_KILL_SW |
6255 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6256 STATUS_IN_SUSPEND;
6257 goto exit;
6258 }
6259
6260 /* ...otherwise clear out all the status bits but the RF Kill and
6261 * SUSPEND bits and continue taking the NIC down. */
6262 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6263 STATUS_RF_KILL_HW |
6264 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6265 STATUS_RF_KILL_SW |
6266 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6267 STATUS_IN_SUSPEND |
6268 test_bit(STATUS_FW_ERROR, &priv->status) <<
6269 STATUS_FW_ERROR;
6270
6271 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 6272 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
6273 spin_unlock_irqrestore(&priv->lock, flags);
6274
bb8c093b
CH
6275 iwl3945_hw_txq_ctx_stop(priv);
6276 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY
6277
6278 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH
6279 if (!iwl3945_grab_nic_access(priv)) {
6280 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 6281 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 6282 iwl3945_release_nic_access(priv);
b481de9c
ZY
6283 }
6284 spin_unlock_irqrestore(&priv->lock, flags);
6285
6286 udelay(5);
6287
bb8c093b
CH
6288 iwl3945_hw_nic_stop_master(priv);
6289 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
6290 iwl3945_hw_nic_reset(priv);
b481de9c
ZY
6291
6292 exit:
bb8c093b 6293 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY
6294
6295 if (priv->ibss_beacon)
6296 dev_kfree_skb(priv->ibss_beacon);
6297 priv->ibss_beacon = NULL;
6298
6299 /* clear out any free frames */
bb8c093b 6300 iwl3945_clear_free_frames(priv);
b481de9c
ZY
6301}
6302
bb8c093b 6303static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY
6304{
6305 mutex_lock(&priv->mutex);
bb8c093b 6306 __iwl3945_down(priv);
b481de9c 6307 mutex_unlock(&priv->mutex);
b24d22b1 6308
bb8c093b 6309 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
6310}
6311
6312#define MAX_HW_RESTARTS 5
6313
bb8c093b 6314static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY
6315{
6316 int rc, i;
6317
6318 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6319 IWL_WARNING("Exit pending; will not bring the NIC up\n");
6320 return -EIO;
6321 }
6322
6323 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
6324 IWL_WARNING("Radio disabled by SW RF kill (module "
6325 "parameter)\n");
e655b9f0
ZY
6326 return -ENODEV;
6327 }
6328
6329 /* If platform's RF_KILL switch is NOT set to KILL */
6330 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
6331 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6332 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6333 else {
6334 set_bit(STATUS_RF_KILL_HW, &priv->status);
6335 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6336 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6337 return -ENODEV;
6338 }
b481de9c
ZY
6339 }
6340
a781cf94
RC
6341 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6342 IWL_ERROR("ucode not available for device bringup\n");
6343 return -EIO;
6344 }
6345
bb8c093b 6346 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6347
bb8c093b 6348 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY
6349 if (rc) {
6350 IWL_ERROR("Unable to int nic\n");
6351 return rc;
6352 }
6353
6354 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH
6355 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6356 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
6357 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6358
6359 /* clear (again), then enable host interrupts */
bb8c093b
CH
6360 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6361 iwl3945_enable_interrupts(priv);
b481de9c
ZY
6362
6363 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH
6364 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6365 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
6366
6367 /* Copy original ucode data image from disk into backup cache.
6368 * This will be used to initialize the on-board processor's
6369 * data SRAM for a clean start when the runtime program first loads. */
6370 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6371 priv->ucode_data.len);
b481de9c 6372
e655b9f0
ZY
6373 /* We return success when we resume from suspend and rf_kill is on. */
6374 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
6375 return 0;
6376
b481de9c
ZY
6377 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6378
bb8c093b 6379 iwl3945_clear_stations_table(priv);
b481de9c
ZY
6380
6381 /* load bootstrap state machine,
6382 * load bootstrap program into processor's memory,
6383 * prepare to load the "initialize" uCode */
bb8c093b 6384 rc = iwl3945_load_bsm(priv);
b481de9c
ZY
6385
6386 if (rc) {
6387 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6388 continue;
6389 }
6390
6391 /* start card; "initialize" will load runtime ucode */
bb8c093b 6392 iwl3945_nic_start(priv);
b481de9c 6393
b481de9c
ZY
6394 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6395
6396 return 0;
6397 }
6398
6399 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6400 __iwl3945_down(priv);
b481de9c
ZY
6401
6402 /* tried to restart and config the device for as long as our
6403 * patience could withstand */
6404 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6405 return -EIO;
6406}
6407
6408
6409/*****************************************************************************
6410 *
6411 * Workqueue callbacks
6412 *
6413 *****************************************************************************/
6414
bb8c093b 6415static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6416{
bb8c093b
CH
6417 struct iwl3945_priv *priv =
6418 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY
6419
6420 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6421 return;
6422
6423 mutex_lock(&priv->mutex);
bb8c093b 6424 iwl3945_init_alive_start(priv);
b481de9c
ZY
6425 mutex_unlock(&priv->mutex);
6426}
6427
bb8c093b 6428static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6429{
bb8c093b
CH
6430 struct iwl3945_priv *priv =
6431 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY
6432
6433 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6434 return;
6435
6436 mutex_lock(&priv->mutex);
bb8c093b 6437 iwl3945_alive_start(priv);
b481de9c
ZY
6438 mutex_unlock(&priv->mutex);
6439}
6440
bb8c093b 6441static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6442{
bb8c093b 6443 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY
6444
6445 wake_up_interruptible(&priv->wait_command_queue);
6446
6447 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6448 return;
6449
6450 mutex_lock(&priv->mutex);
6451
bb8c093b 6452 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY
6453 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6454 "HW and/or SW RF Kill no longer active, restarting "
6455 "device\n");
6456 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6457 queue_work(priv->workqueue, &priv->restart);
6458 } else {
6459
6460 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6461 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6462 "disabled by SW switch\n");
6463 else
6464 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6465 "Kill switch must be turned off for "
6466 "wireless networking to work.\n");
6467 }
6468 mutex_unlock(&priv->mutex);
6469}
6470
6471#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6472
bb8c093b 6473static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6474{
bb8c093b
CH
6475 struct iwl3945_priv *priv =
6476 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY
6477
6478 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6479 return;
6480
6481 mutex_lock(&priv->mutex);
6482 if (test_bit(STATUS_SCANNING, &priv->status) ||
6483 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6484 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6485 "Scan completion watchdog resetting adapter (%dms)\n",
6486 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6487
b481de9c 6488 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6489 iwl3945_send_scan_abort(priv);
b481de9c
ZY
6490 }
6491 mutex_unlock(&priv->mutex);
6492}
6493
bb8c093b 6494static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6495{
bb8c093b
CH
6496 struct iwl3945_priv *priv =
6497 container_of(data, struct iwl3945_priv, request_scan);
6498 struct iwl3945_host_cmd cmd = {
b481de9c 6499 .id = REPLY_SCAN_CMD,
bb8c093b 6500 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY
6501 .meta.flags = CMD_SIZE_HUGE,
6502 };
6503 int rc = 0;
bb8c093b 6504 struct iwl3945_scan_cmd *scan;
b481de9c
ZY
6505 struct ieee80211_conf *conf = NULL;
6506 u8 direct_mask;
6507 int phymode;
6508
6509 conf = ieee80211_get_hw_conf(priv->hw);
6510
6511 mutex_lock(&priv->mutex);
6512
bb8c093b 6513 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY
6514 IWL_WARNING("request scan called when driver not ready.\n");
6515 goto done;
6516 }
6517
6518 /* Make sure the scan wasn't cancelled before this queued work
6519 * was given the chance to run... */
6520 if (!test_bit(STATUS_SCANNING, &priv->status))
6521 goto done;
6522
6523 /* This should never be called or scheduled if there is currently
6524 * a scan active in the hardware. */
6525 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6526 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6527 "Ignoring second request.\n");
6528 rc = -EIO;
6529 goto done;
6530 }
6531
6532 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6533 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6534 goto done;
6535 }
6536
6537 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6538 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6539 goto done;
6540 }
6541
bb8c093b 6542 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY
6543 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6544 goto done;
6545 }
6546
6547 if (!test_bit(STATUS_READY, &priv->status)) {
6548 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6549 goto done;
6550 }
6551
6552 if (!priv->scan_bands) {
6553 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6554 goto done;
6555 }
6556
6557 if (!priv->scan) {
bb8c093b 6558 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY
6559 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6560 if (!priv->scan) {
6561 rc = -ENOMEM;
6562 goto done;
6563 }
6564 }
6565 scan = priv->scan;
bb8c093b 6566 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
6567
6568 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6569 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6570
bb8c093b 6571 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
6572 u16 interval = 0;
6573 u32 extra;
6574 u32 suspend_time = 100;
6575 u32 scan_suspend_time = 100;
6576 unsigned long flags;
6577
6578 IWL_DEBUG_INFO("Scanning while associated...\n");
6579
6580 spin_lock_irqsave(&priv->lock, flags);
6581 interval = priv->beacon_int;
6582 spin_unlock_irqrestore(&priv->lock, flags);
6583
6584 scan->suspend_time = 0;
15e869d8 6585 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
6586 if (!interval)
6587 interval = suspend_time;
6588 /*
6589 * suspend time format:
6590 * 0-19: beacon interval in usec (time before exec.)
6591 * 20-23: 0
6592 * 24-31: number of beacons (suspend between channels)
6593 */
6594
6595 extra = (suspend_time / interval) << 24;
6596 scan_suspend_time = 0xFF0FFFFF &
6597 (extra | ((suspend_time % interval) * 1024));
6598
6599 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6600 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6601 scan_suspend_time, interval);
6602 }
6603
6604 /* We should add the ability for user to lock to PASSIVE ONLY */
6605 if (priv->one_direct_scan) {
6606 IWL_DEBUG_SCAN
6607 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6608 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY
6609 priv->direct_ssid_len));
6610 scan->direct_scan[0].id = WLAN_EID_SSID;
6611 scan->direct_scan[0].len = priv->direct_ssid_len;
6612 memcpy(scan->direct_scan[0].ssid,
6613 priv->direct_ssid, priv->direct_ssid_len);
6614 direct_mask = 1;
bb8c093b 6615 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
b481de9c
ZY
6616 scan->direct_scan[0].id = WLAN_EID_SSID;
6617 scan->direct_scan[0].len = priv->essid_len;
6618 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6619 direct_mask = 1;
6620 } else
6621 direct_mask = 0;
6622
6623 /* We don't build a direct scan probe request; the uCode will do
6624 * that based on the direct_mask added to each channel entry */
6625 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6626 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
b481de9c
ZY
6627 IWL_MAX_SCAN_SIZE - sizeof(scan), 0));
6628 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6629 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6630 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6631
6632 /* flags + rate selection */
6633
6634 switch (priv->scan_bands) {
6635 case 2:
6636 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6637 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6638 scan->good_CRC_th = 0;
6639 phymode = MODE_IEEE80211G;
6640 break;
6641
6642 case 1:
6643 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6644 scan->good_CRC_th = IWL_GOOD_CRC_TH;
6645 phymode = MODE_IEEE80211A;
6646 break;
6647
6648 default:
6649 IWL_WARNING("Invalid scan band count\n");
6650 goto done;
6651 }
6652
6653 /* select Rx antennas */
6654 scan->flags |= iwl3945_get_antenna_flags(priv);
6655
6656 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6657 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6658
6659 if (direct_mask)
6660 IWL_DEBUG_SCAN
6661 ("Initiating direct scan for %s.\n",
bb8c093b 6662 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY
6663 else
6664 IWL_DEBUG_SCAN("Initiating indirect scan.\n");
6665
6666 scan->channel_count =
bb8c093b 6667 iwl3945_get_channels_for_scan(
b481de9c
ZY
6668 priv, phymode, 1, /* active */
6669 direct_mask,
6670 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6671
6672 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6673 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
6674 cmd.data = scan;
6675 scan->len = cpu_to_le16(cmd.len);
6676
6677 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6678 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
6679 if (rc)
6680 goto done;
6681
6682 queue_delayed_work(priv->workqueue, &priv->scan_check,
6683 IWL_SCAN_CHECK_WATCHDOG);
6684
6685 mutex_unlock(&priv->mutex);
6686 return;
6687
6688 done:
01ebd063 6689 /* inform mac80211 scan aborted */
b481de9c
ZY
6690 queue_work(priv->workqueue, &priv->scan_completed);
6691 mutex_unlock(&priv->mutex);
6692}
6693
bb8c093b 6694static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6695{
bb8c093b 6696 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY
6697
6698 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6699 return;
6700
6701 mutex_lock(&priv->mutex);
bb8c093b 6702 __iwl3945_up(priv);
b481de9c
ZY
6703 mutex_unlock(&priv->mutex);
6704}
6705
bb8c093b 6706static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6707{
bb8c093b 6708 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY
6709
6710 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6711 return;
6712
bb8c093b 6713 iwl3945_down(priv);
b481de9c
ZY
6714 queue_work(priv->workqueue, &priv->up);
6715}
6716
bb8c093b 6717static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6718{
bb8c093b
CH
6719 struct iwl3945_priv *priv =
6720 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY
6721
6722 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6723 return;
6724
6725 mutex_lock(&priv->mutex);
bb8c093b 6726 iwl3945_rx_replenish(priv);
b481de9c
ZY
6727 mutex_unlock(&priv->mutex);
6728}
6729
7878a5a4
MA
6730#define IWL_DELAY_NEXT_SCAN (HZ*2)
6731
bb8c093b 6732static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6733{
bb8c093b 6734 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY
6735 post_associate.work);
6736
6737 int rc = 0;
6738 struct ieee80211_conf *conf = NULL;
0795af57 6739 DECLARE_MAC_BUF(mac);
b481de9c
ZY
6740
6741 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6742 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6743 return;
6744 }
6745
6746
0795af57
JP
6747 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6748 priv->assoc_id,
6749 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY
6750
6751 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6752 return;
6753
6754 mutex_lock(&priv->mutex);
6755
32bfd35d 6756 if (!priv->vif || !priv->is_open) {
6ef89d0a
MA
6757 mutex_unlock(&priv->mutex);
6758 return;
6759 }
bb8c093b 6760 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6761
b481de9c
ZY
6762 conf = ieee80211_get_hw_conf(priv->hw);
6763
6764 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6765 iwl3945_commit_rxon(priv);
b481de9c 6766
bb8c093b
CH
6767 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6768 iwl3945_setup_rxon_timing(priv);
6769 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
6770 sizeof(priv->rxon_timing), &priv->rxon_timing);
6771 if (rc)
6772 IWL_WARNING("REPLY_RXON_TIMING failed - "
6773 "Attempting to continue.\n");
6774
6775 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6776
6777 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6778
6779 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6780 priv->assoc_id, priv->beacon_int);
6781
6782 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6783 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6784 else
6785 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6786
6787 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6788 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6789 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6790 else
6791 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6792
6793 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6794 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6795
6796 }
6797
bb8c093b 6798 iwl3945_commit_rxon(priv);
b481de9c
ZY
6799
6800 switch (priv->iw_mode) {
6801 case IEEE80211_IF_TYPE_STA:
bb8c093b 6802 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
6803 break;
6804
6805 case IEEE80211_IF_TYPE_IBSS:
6806
6807 /* clear out the station table */
bb8c093b 6808 iwl3945_clear_stations_table(priv);
b481de9c 6809
bb8c093b
CH
6810 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6811 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c
ZY
6812 iwl3945_sync_sta(priv, IWL_STA_ID,
6813 (priv->phymode == MODE_IEEE80211A)?
6814 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6815 CMD_ASYNC);
bb8c093b
CH
6816 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6817 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
6818
6819 break;
6820
6821 default:
6822 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6823 __FUNCTION__, priv->iw_mode);
b481de9c
ZY
6824 break;
6825 }
6826
bb8c093b 6827 iwl3945_sequence_reset(priv);
b481de9c 6828
c8b0e6e1 6829#ifdef CONFIG_IWL3945_QOS
bb8c093b 6830 iwl3945_activate_qos(priv, 0);
c8b0e6e1 6831#endif /* CONFIG_IWL3945_QOS */
7878a5a4
MA
6832 /* we have just associated, don't start scan too early */
6833 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY
6834 mutex_unlock(&priv->mutex);
6835}
6836
bb8c093b 6837static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6838{
bb8c093b 6839 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6840
bb8c093b 6841 if (!iwl3945_is_ready(priv))
b481de9c
ZY
6842 return;
6843
6844 mutex_lock(&priv->mutex);
6845
6846 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6847 iwl3945_send_scan_abort(priv);
b481de9c
ZY
6848
6849 mutex_unlock(&priv->mutex);
6850}
6851
76bb77e0
ZY
6852static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6853
bb8c093b 6854static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6855{
bb8c093b
CH
6856 struct iwl3945_priv *priv =
6857 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY
6858
6859 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6860
6861 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6862 return;
6863
a0646470
ZY
6864 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6865 iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6866
b481de9c
ZY
6867 ieee80211_scan_completed(priv->hw);
6868
6869 /* Since setting the TXPOWER may have been deferred while
6870 * performing the scan, fire one off */
6871 mutex_lock(&priv->mutex);
bb8c093b 6872 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY
6873 mutex_unlock(&priv->mutex);
6874}
6875
6876/*****************************************************************************
6877 *
6878 * mac80211 entry point functions
6879 *
6880 *****************************************************************************/
6881
5a66926a
ZY
6882#define UCODE_READY_TIMEOUT (2 * HZ)
6883
bb8c093b 6884static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6885{
bb8c093b 6886 struct iwl3945_priv *priv = hw->priv;
5a66926a 6887 int ret;
b481de9c
ZY
6888
6889 IWL_DEBUG_MAC80211("enter\n");
6890
5a66926a
ZY
6891 if (pci_enable_device(priv->pci_dev)) {
6892 IWL_ERROR("Fail to pci_enable_device\n");
6893 return -ENODEV;
6894 }
6895 pci_restore_state(priv->pci_dev);
6896 pci_enable_msi(priv->pci_dev);
6897
6898 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6899 DRV_NAME, priv);
6900 if (ret) {
6901 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6902 goto out_disable_msi;
6903 }
6904
b481de9c
ZY
6905 /* we should be verifying the device is ready to be opened */
6906 mutex_lock(&priv->mutex);
6907
5a66926a
ZY
6908 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6909 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6910 * ucode filename and max sizes are card-specific. */
6911
6912 if (!priv->ucode_code.len) {
6913 ret = iwl3945_read_ucode(priv);
6914 if (ret) {
6915 IWL_ERROR("Could not read microcode: %d\n", ret);
6916 mutex_unlock(&priv->mutex);
6917 goto out_release_irq;
6918 }
6919 }
b481de9c 6920
e655b9f0 6921 ret = __iwl3945_up(priv);
b481de9c
ZY
6922
6923 mutex_unlock(&priv->mutex);
5a66926a 6924
e655b9f0
ZY
6925 if (ret)
6926 goto out_release_irq;
6927
6928 IWL_DEBUG_INFO("Start UP work.\n");
6929
6930 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6931 return 0;
6932
5a66926a
ZY
6933 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6934 * mac80211 will not be run successfully. */
6935 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6936 test_bit(STATUS_READY, &priv->status),
6937 UCODE_READY_TIMEOUT);
6938 if (!ret) {
6939 if (!test_bit(STATUS_READY, &priv->status)) {
6940 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6941 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6942 ret = -ETIMEDOUT;
6943 goto out_release_irq;
6944 }
6945 }
6946
e655b9f0 6947 priv->is_open = 1;
b481de9c
ZY
6948 IWL_DEBUG_MAC80211("leave\n");
6949 return 0;
5a66926a
ZY
6950
6951out_release_irq:
6952 free_irq(priv->pci_dev->irq, priv);
6953out_disable_msi:
6954 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY
6955 pci_disable_device(priv->pci_dev);
6956 priv->is_open = 0;
6957 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6958 return ret;
b481de9c
ZY
6959}
6960
bb8c093b 6961static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6962{
bb8c093b 6963 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6964
6965 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6966
e655b9f0
ZY
6967 if (!priv->is_open) {
6968 IWL_DEBUG_MAC80211("leave - skip\n");
6969 return;
6970 }
6971
b481de9c 6972 priv->is_open = 0;
5a66926a
ZY
6973
6974 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY
6975 /* stop mac, cancel any scan request and clear
6976 * RXON_FILTER_ASSOC_MSK BIT
6977 */
5a66926a
ZY
6978 mutex_lock(&priv->mutex);
6979 iwl3945_scan_cancel_timeout(priv, 100);
6980 cancel_delayed_work(&priv->post_associate);
fde3571f 6981 mutex_unlock(&priv->mutex);
fde3571f
MA
6982 }
6983
5a66926a
ZY
6984 iwl3945_down(priv);
6985
6986 flush_workqueue(priv->workqueue);
6987 free_irq(priv->pci_dev->irq, priv);
6988 pci_disable_msi(priv->pci_dev);
6989 pci_save_state(priv->pci_dev);
6990 pci_disable_device(priv->pci_dev);
6ef89d0a 6991
b481de9c 6992 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6993}
6994
bb8c093b 6995static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY
6996 struct ieee80211_tx_control *ctl)
6997{
bb8c093b 6998 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6999
7000 IWL_DEBUG_MAC80211("enter\n");
7001
7002 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
7003 IWL_DEBUG_MAC80211("leave - monitor\n");
7004 return -1;
7005 }
7006
7007 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
7008 ctl->tx_rate);
7009
bb8c093b 7010 if (iwl3945_tx_skb(priv, skb, ctl))
b481de9c
ZY
7011 dev_kfree_skb_any(skb);
7012
7013 IWL_DEBUG_MAC80211("leave\n");
7014 return 0;
7015}
7016
bb8c093b 7017static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY
7018 struct ieee80211_if_init_conf *conf)
7019{
bb8c093b 7020 struct iwl3945_priv *priv = hw->priv;
b481de9c 7021 unsigned long flags;
0795af57 7022 DECLARE_MAC_BUF(mac);
b481de9c 7023
32bfd35d 7024 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 7025
32bfd35d
JB
7026 if (priv->vif) {
7027 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 7028 return -EOPNOTSUPP;
b481de9c
ZY
7029 }
7030
7031 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 7032 priv->vif = conf->vif;
b481de9c
ZY
7033
7034 spin_unlock_irqrestore(&priv->lock, flags);
7035
7036 mutex_lock(&priv->mutex);
864792e3
TW
7037
7038 if (conf->mac_addr) {
7039 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
7040 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
7041 }
7042
5a66926a
ZY
7043 if (iwl3945_is_ready(priv))
7044 iwl3945_set_mode(priv, conf->type);
b481de9c 7045
b481de9c
ZY
7046 mutex_unlock(&priv->mutex);
7047
5a66926a 7048 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
7049 return 0;
7050}
7051
7052/**
bb8c093b 7053 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY
7054 *
7055 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
7056 * be set inappropriately and the driver currently sets the hardware up to
7057 * use it whenever needed.
7058 */
bb8c093b 7059static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 7060{
bb8c093b
CH
7061 struct iwl3945_priv *priv = hw->priv;
7062 const struct iwl3945_channel_info *ch_info;
b481de9c 7063 unsigned long flags;
76bb77e0 7064 int ret = 0;
b481de9c
ZY
7065
7066 mutex_lock(&priv->mutex);
7067 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel);
7068
12342c47
ZY
7069 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
7070
bb8c093b 7071 if (!iwl3945_is_ready(priv)) {
b481de9c 7072 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY
7073 ret = -EIO;
7074 goto out;
b481de9c
ZY
7075 }
7076
bb8c093b 7077 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 7078 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY
7079 IWL_DEBUG_MAC80211("leave - scanning\n");
7080 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 7081 mutex_unlock(&priv->mutex);
a0646470 7082 return 0;
b481de9c
ZY
7083 }
7084
7085 spin_lock_irqsave(&priv->lock, flags);
7086
bb8c093b 7087 ch_info = iwl3945_get_channel_info(priv, conf->phymode, conf->channel);
b481de9c
ZY
7088 if (!is_channel_valid(ch_info)) {
7089 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
7090 conf->channel, conf->phymode);
7091 IWL_DEBUG_MAC80211("leave - invalid channel\n");
7092 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY
7093 ret = -EINVAL;
7094 goto out;
b481de9c
ZY
7095 }
7096
bb8c093b 7097 iwl3945_set_rxon_channel(priv, conf->phymode, conf->channel);
b481de9c 7098
bb8c093b 7099 iwl3945_set_flags_for_phymode(priv, conf->phymode);
b481de9c
ZY
7100
7101 /* The list of supported rates and rate mask can be different
7102 * for each phymode; since the phymode may have changed, reset
7103 * the rate mask to what mac80211 lists */
bb8c093b 7104 iwl3945_set_rate(priv);
b481de9c
ZY
7105
7106 spin_unlock_irqrestore(&priv->lock, flags);
7107
7108#ifdef IEEE80211_CONF_CHANNEL_SWITCH
7109 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 7110 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 7111 goto out;
b481de9c
ZY
7112 }
7113#endif
7114
bb8c093b 7115 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY
7116
7117 if (!conf->radio_enabled) {
7118 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 7119 goto out;
b481de9c
ZY
7120 }
7121
bb8c093b 7122 if (iwl3945_is_rfkill(priv)) {
b481de9c 7123 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY
7124 ret = -EIO;
7125 goto out;
b481de9c
ZY
7126 }
7127
bb8c093b 7128 iwl3945_set_rate(priv);
b481de9c
ZY
7129
7130 if (memcmp(&priv->active_rxon,
7131 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 7132 iwl3945_commit_rxon(priv);
b481de9c
ZY
7133 else
7134 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
7135
7136 IWL_DEBUG_MAC80211("leave\n");
7137
76bb77e0 7138out:
a0646470 7139 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 7140 mutex_unlock(&priv->mutex);
76bb77e0 7141 return ret;
b481de9c
ZY
7142}
7143
bb8c093b 7144static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY
7145{
7146 int rc = 0;
7147
d986bcd1 7148 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
7149 return;
7150
7151 /* The following should be done only at AP bring up */
7152 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
7153
7154 /* RXON - unassoc (to set timing command) */
7155 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7156 iwl3945_commit_rxon(priv);
b481de9c
ZY
7157
7158 /* RXON Timing */
bb8c093b
CH
7159 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
7160 iwl3945_setup_rxon_timing(priv);
7161 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
7162 sizeof(priv->rxon_timing), &priv->rxon_timing);
7163 if (rc)
7164 IWL_WARNING("REPLY_RXON_TIMING failed - "
7165 "Attempting to continue.\n");
7166
7167 /* FIXME: what should be the assoc_id for AP? */
7168 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
7169 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
7170 priv->staging_rxon.flags |=
7171 RXON_FLG_SHORT_PREAMBLE_MSK;
7172 else
7173 priv->staging_rxon.flags &=
7174 ~RXON_FLG_SHORT_PREAMBLE_MSK;
7175
7176 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
7177 if (priv->assoc_capability &
7178 WLAN_CAPABILITY_SHORT_SLOT_TIME)
7179 priv->staging_rxon.flags |=
7180 RXON_FLG_SHORT_SLOT_MSK;
7181 else
7182 priv->staging_rxon.flags &=
7183 ~RXON_FLG_SHORT_SLOT_MSK;
7184
7185 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7186 priv->staging_rxon.flags &=
7187 ~RXON_FLG_SHORT_SLOT_MSK;
7188 }
7189 /* restore RXON assoc */
7190 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH
7191 iwl3945_commit_rxon(priv);
7192 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 7193 }
bb8c093b 7194 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
7195
7196 /* FIXME - we need to add code here to detect a totally new
7197 * configuration, reset the AP, unassoc, rxon timing, assoc,
7198 * clear sta table, add BCAST sta... */
7199}
7200
32bfd35d
JB
7201static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
7202 struct ieee80211_vif *vif,
b481de9c
ZY
7203 struct ieee80211_if_conf *conf)
7204{
bb8c093b 7205 struct iwl3945_priv *priv = hw->priv;
0795af57 7206 DECLARE_MAC_BUF(mac);
b481de9c
ZY
7207 unsigned long flags;
7208 int rc;
7209
7210 if (conf == NULL)
7211 return -EIO;
7212
4150c572
JB
7213 /* XXX: this MUST use conf->mac_addr */
7214
b481de9c
ZY
7215 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
7216 (!conf->beacon || !conf->ssid_len)) {
7217 IWL_DEBUG_MAC80211
7218 ("Leaving in AP mode because HostAPD is not ready.\n");
7219 return 0;
7220 }
7221
5a66926a
ZY
7222 if (!iwl3945_is_alive(priv))
7223 return -EAGAIN;
7224
b481de9c
ZY
7225 mutex_lock(&priv->mutex);
7226
b481de9c 7227 if (conf->bssid)
0795af57
JP
7228 IWL_DEBUG_MAC80211("bssid: %s\n",
7229 print_mac(mac, conf->bssid));
b481de9c 7230
4150c572
JB
7231/*
7232 * very dubious code was here; the probe filtering flag is never set:
7233 *
b481de9c
ZY
7234 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
7235 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572
JB
7236 */
7237 if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
b481de9c
ZY
7238 IWL_DEBUG_MAC80211("leave - scanning\n");
7239 mutex_unlock(&priv->mutex);
7240 return 0;
7241 }
7242
32bfd35d
JB
7243 if (priv->vif != vif) {
7244 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b481de9c
ZY
7245 mutex_unlock(&priv->mutex);
7246 return 0;
7247 }
7248
7249 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
7250 if (!conf->bssid) {
7251 conf->bssid = priv->mac_addr;
7252 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP
7253 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
7254 print_mac(mac, conf->bssid));
b481de9c
ZY
7255 }
7256 if (priv->ibss_beacon)
7257 dev_kfree_skb(priv->ibss_beacon);
7258
7259 priv->ibss_beacon = conf->beacon;
7260 }
7261
fde3571f
MA
7262 if (iwl3945_is_rfkill(priv))
7263 goto done;
7264
b481de9c
ZY
7265 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
7266 !is_multicast_ether_addr(conf->bssid)) {
7267 /* If there is currently a HW scan going on in the background
7268 * then we need to cancel it else the RXON below will fail. */
bb8c093b 7269 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY
7270 IWL_WARNING("Aborted scan still in progress "
7271 "after 100ms\n");
7272 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
7273 mutex_unlock(&priv->mutex);
7274 return -EAGAIN;
7275 }
7276 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
7277
7278 /* TODO: Audit driver for usage of these members and see
7279 * if mac80211 deprecates them (priv->bssid looks like it
7280 * shouldn't be there, but I haven't scanned the IBSS code
7281 * to verify) - jpk */
7282 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
7283
7284 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 7285 iwl3945_config_ap(priv);
b481de9c 7286 else {
bb8c093b 7287 rc = iwl3945_commit_rxon(priv);
b481de9c 7288 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 7289 iwl3945_add_station(priv,
556f8db7 7290 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY
7291 }
7292
7293 } else {
bb8c093b 7294 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 7295 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7296 iwl3945_commit_rxon(priv);
b481de9c
ZY
7297 }
7298
fde3571f 7299 done:
b481de9c
ZY
7300 spin_lock_irqsave(&priv->lock, flags);
7301 if (!conf->ssid_len)
7302 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7303 else
7304 memcpy(priv->essid, conf->ssid, conf->ssid_len);
7305
7306 priv->essid_len = conf->ssid_len;
7307 spin_unlock_irqrestore(&priv->lock, flags);
7308
7309 IWL_DEBUG_MAC80211("leave\n");
7310 mutex_unlock(&priv->mutex);
7311
7312 return 0;
7313}
7314
bb8c093b 7315static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB
7316 unsigned int changed_flags,
7317 unsigned int *total_flags,
7318 int mc_count, struct dev_addr_list *mc_list)
7319{
7320 /*
7321 * XXX: dummy
bb8c093b 7322 * see also iwl3945_connection_init_rx_config
4150c572
JB
7323 */
7324 *total_flags = 0;
7325}
7326
bb8c093b 7327static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY
7328 struct ieee80211_if_init_conf *conf)
7329{
bb8c093b 7330 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7331
7332 IWL_DEBUG_MAC80211("enter\n");
7333
7334 mutex_lock(&priv->mutex);
6ef89d0a 7335
fde3571f
MA
7336 if (iwl3945_is_ready_rf(priv)) {
7337 iwl3945_scan_cancel_timeout(priv, 100);
7338 cancel_delayed_work(&priv->post_associate);
7339 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7340 iwl3945_commit_rxon(priv);
7341 }
32bfd35d
JB
7342 if (priv->vif == conf->vif) {
7343 priv->vif = NULL;
b481de9c
ZY
7344 memset(priv->bssid, 0, ETH_ALEN);
7345 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7346 priv->essid_len = 0;
7347 }
7348 mutex_unlock(&priv->mutex);
7349
7350 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
7351}
7352
bb8c093b 7353static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY
7354{
7355 int rc = 0;
7356 unsigned long flags;
bb8c093b 7357 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7358
7359 IWL_DEBUG_MAC80211("enter\n");
7360
15e869d8 7361 mutex_lock(&priv->mutex);
b481de9c
ZY
7362 spin_lock_irqsave(&priv->lock, flags);
7363
bb8c093b 7364 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7365 rc = -EIO;
7366 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7367 goto out_unlock;
7368 }
7369
7370 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7371 rc = -EIO;
7372 IWL_ERROR("ERROR: APs don't scan\n");
7373 goto out_unlock;
7374 }
7375
7878a5a4
MA
7376 /* we don't schedule scan within next_scan_jiffies period */
7377 if (priv->next_scan_jiffies &&
7378 time_after(priv->next_scan_jiffies, jiffies)) {
7379 rc = -EAGAIN;
7380 goto out_unlock;
7381 }
b481de9c 7382 /* if we just finished scan ask for delay */
7878a5a4
MA
7383 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
7384 IWL_DELAY_NEXT_SCAN, jiffies)) {
b481de9c
ZY
7385 rc = -EAGAIN;
7386 goto out_unlock;
7387 }
7388 if (len) {
7878a5a4 7389 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7390 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY
7391
7392 priv->one_direct_scan = 1;
7393 priv->direct_ssid_len = (u8)
7394 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7395 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA
7396 } else
7397 priv->one_direct_scan = 0;
b481de9c 7398
bb8c093b 7399 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY
7400
7401 IWL_DEBUG_MAC80211("leave\n");
7402
7403out_unlock:
7404 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7405 mutex_unlock(&priv->mutex);
b481de9c
ZY
7406
7407 return rc;
7408}
7409
bb8c093b 7410static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY
7411 const u8 *local_addr, const u8 *addr,
7412 struct ieee80211_key_conf *key)
7413{
bb8c093b 7414 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7415 int rc = 0;
7416 u8 sta_id;
7417
7418 IWL_DEBUG_MAC80211("enter\n");
7419
bb8c093b 7420 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY
7421 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7422 return -EOPNOTSUPP;
7423 }
7424
7425 if (is_zero_ether_addr(addr))
7426 /* only support pairwise keys */
7427 return -EOPNOTSUPP;
7428
bb8c093b 7429 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7430 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP
7431 DECLARE_MAC_BUF(mac);
7432
7433 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7434 print_mac(mac, addr));
b481de9c
ZY
7435 return -EINVAL;
7436 }
7437
7438 mutex_lock(&priv->mutex);
7439
bb8c093b 7440 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7441
b481de9c
ZY
7442 switch (cmd) {
7443 case SET_KEY:
bb8c093b 7444 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7445 if (!rc) {
bb8c093b
CH
7446 iwl3945_set_rxon_hwcrypto(priv, 1);
7447 iwl3945_commit_rxon(priv);
b481de9c
ZY
7448 key->hw_key_idx = sta_id;
7449 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7450 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7451 }
7452 break;
7453 case DISABLE_KEY:
bb8c093b 7454 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7455 if (!rc) {
bb8c093b
CH
7456 iwl3945_set_rxon_hwcrypto(priv, 0);
7457 iwl3945_commit_rxon(priv);
b481de9c
ZY
7458 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7459 }
7460 break;
7461 default:
7462 rc = -EINVAL;
7463 }
7464
7465 IWL_DEBUG_MAC80211("leave\n");
7466 mutex_unlock(&priv->mutex);
7467
7468 return rc;
7469}
7470
bb8c093b 7471static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
b481de9c
ZY
7472 const struct ieee80211_tx_queue_params *params)
7473{
bb8c093b 7474 struct iwl3945_priv *priv = hw->priv;
c8b0e6e1 7475#ifdef CONFIG_IWL3945_QOS
b481de9c
ZY
7476 unsigned long flags;
7477 int q;
0054b34d 7478#endif /* CONFIG_IWL3945_QOS */
b481de9c
ZY
7479
7480 IWL_DEBUG_MAC80211("enter\n");
7481
bb8c093b 7482 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7483 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7484 return -EIO;
7485 }
7486
7487 if (queue >= AC_NUM) {
7488 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7489 return 0;
7490 }
7491
c8b0e6e1 7492#ifdef CONFIG_IWL3945_QOS
b481de9c
ZY
7493 if (!priv->qos_data.qos_enable) {
7494 priv->qos_data.qos_active = 0;
7495 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7496 return 0;
7497 }
7498 q = AC_NUM - 1 - queue;
7499
7500 spin_lock_irqsave(&priv->lock, flags);
7501
7502 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7503 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7504 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7505 priv->qos_data.def_qos_parm.ac[q].edca_txop =
7506 cpu_to_le16((params->burst_time * 100));
7507
7508 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7509 priv->qos_data.qos_active = 1;
7510
7511 spin_unlock_irqrestore(&priv->lock, flags);
7512
7513 mutex_lock(&priv->mutex);
7514 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH
7515 iwl3945_activate_qos(priv, 1);
7516 else if (priv->assoc_id && iwl3945_is_associated(priv))
7517 iwl3945_activate_qos(priv, 0);
b481de9c
ZY
7518
7519 mutex_unlock(&priv->mutex);
7520
c8b0e6e1 7521#endif /*CONFIG_IWL3945_QOS */
b481de9c
ZY
7522
7523 IWL_DEBUG_MAC80211("leave\n");
7524 return 0;
7525}
7526
bb8c093b 7527static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY
7528 struct ieee80211_tx_queue_stats *stats)
7529{
bb8c093b 7530 struct iwl3945_priv *priv = hw->priv;
b481de9c 7531 int i, avail;
bb8c093b
CH
7532 struct iwl3945_tx_queue *txq;
7533 struct iwl3945_queue *q;
b481de9c
ZY
7534 unsigned long flags;
7535
7536 IWL_DEBUG_MAC80211("enter\n");
7537
bb8c093b 7538 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7539 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7540 return -EIO;
7541 }
7542
7543 spin_lock_irqsave(&priv->lock, flags);
7544
7545 for (i = 0; i < AC_NUM; i++) {
7546 txq = &priv->txq[i];
7547 q = &txq->q;
bb8c093b 7548 avail = iwl3945_queue_space(q);
b481de9c
ZY
7549
7550 stats->data[i].len = q->n_window - avail;
7551 stats->data[i].limit = q->n_window - q->high_mark;
7552 stats->data[i].count = q->n_window;
7553
7554 }
7555 spin_unlock_irqrestore(&priv->lock, flags);
7556
7557 IWL_DEBUG_MAC80211("leave\n");
7558
7559 return 0;
7560}
7561
bb8c093b 7562static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
7563 struct ieee80211_low_level_stats *stats)
7564{
7565 IWL_DEBUG_MAC80211("enter\n");
7566 IWL_DEBUG_MAC80211("leave\n");
7567
7568 return 0;
7569}
7570
bb8c093b 7571static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY
7572{
7573 IWL_DEBUG_MAC80211("enter\n");
7574 IWL_DEBUG_MAC80211("leave\n");
7575
7576 return 0;
7577}
7578
bb8c093b 7579static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7580{
bb8c093b 7581 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7582 unsigned long flags;
7583
7584 mutex_lock(&priv->mutex);
7585 IWL_DEBUG_MAC80211("enter\n");
7586
c8b0e6e1 7587#ifdef CONFIG_IWL3945_QOS
bb8c093b 7588 iwl3945_reset_qos(priv);
b481de9c
ZY
7589#endif
7590 cancel_delayed_work(&priv->post_associate);
7591
7592 spin_lock_irqsave(&priv->lock, flags);
7593 priv->assoc_id = 0;
7594 priv->assoc_capability = 0;
7595 priv->call_post_assoc_from_beacon = 0;
7596
7597 /* new association get rid of ibss beacon skb */
7598 if (priv->ibss_beacon)
7599 dev_kfree_skb(priv->ibss_beacon);
7600
7601 priv->ibss_beacon = NULL;
7602
7603 priv->beacon_int = priv->hw->conf.beacon_int;
7604 priv->timestamp1 = 0;
7605 priv->timestamp0 = 0;
7606 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7607 priv->beacon_int = 0;
7608
7609 spin_unlock_irqrestore(&priv->lock, flags);
7610
fde3571f
MA
7611 if (!iwl3945_is_ready_rf(priv)) {
7612 IWL_DEBUG_MAC80211("leave - not ready\n");
7613 mutex_unlock(&priv->mutex);
7614 return;
7615 }
7616
15e869d8
MA
7617 /* we are restarting association process
7618 * clear RXON_FILTER_ASSOC_MSK bit
7619 */
7620 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7621 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7622 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7623 iwl3945_commit_rxon(priv);
15e869d8
MA
7624 }
7625
b481de9c
ZY
7626 /* Per mac80211.h: This is only used in IBSS mode... */
7627 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7628
b481de9c
ZY
7629 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7630 mutex_unlock(&priv->mutex);
7631 return;
b481de9c
ZY
7632 }
7633
7634 priv->only_active_channel = 0;
7635
bb8c093b 7636 iwl3945_set_rate(priv);
b481de9c
ZY
7637
7638 mutex_unlock(&priv->mutex);
7639
7640 IWL_DEBUG_MAC80211("leave\n");
7641
7642}
7643
bb8c093b 7644static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY
7645 struct ieee80211_tx_control *control)
7646{
bb8c093b 7647 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7648 unsigned long flags;
7649
7650 mutex_lock(&priv->mutex);
7651 IWL_DEBUG_MAC80211("enter\n");
7652
bb8c093b 7653 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7654 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7655 mutex_unlock(&priv->mutex);
7656 return -EIO;
7657 }
7658
7659 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7660 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7661 mutex_unlock(&priv->mutex);
7662 return -EIO;
7663 }
7664
7665 spin_lock_irqsave(&priv->lock, flags);
7666
7667 if (priv->ibss_beacon)
7668 dev_kfree_skb(priv->ibss_beacon);
7669
7670 priv->ibss_beacon = skb;
7671
7672 priv->assoc_id = 0;
7673
7674 IWL_DEBUG_MAC80211("leave\n");
7675 spin_unlock_irqrestore(&priv->lock, flags);
7676
c8b0e6e1 7677#ifdef CONFIG_IWL3945_QOS
bb8c093b 7678 iwl3945_reset_qos(priv);
b481de9c
ZY
7679#endif
7680
7681 queue_work(priv->workqueue, &priv->post_associate.work);
7682
7683 mutex_unlock(&priv->mutex);
7684
7685 return 0;
7686}
7687
7688/*****************************************************************************
7689 *
7690 * sysfs attributes
7691 *
7692 *****************************************************************************/
7693
c8b0e6e1 7694#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
7695
7696/*
7697 * The following adds a new attribute to the sysfs representation
7698 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7699 * used for controlling the debug level.
7700 *
7701 * See the level definitions in iwl for details.
7702 */
7703
7704static ssize_t show_debug_level(struct device_driver *d, char *buf)
7705{
bb8c093b 7706 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY
7707}
7708static ssize_t store_debug_level(struct device_driver *d,
7709 const char *buf, size_t count)
7710{
7711 char *p = (char *)buf;
7712 u32 val;
7713
7714 val = simple_strtoul(p, &p, 0);
7715 if (p == buf)
7716 printk(KERN_INFO DRV_NAME
7717 ": %s is not in hex or decimal form.\n", buf);
7718 else
bb8c093b 7719 iwl3945_debug_level = val;
b481de9c
ZY
7720
7721 return strnlen(buf, count);
7722}
7723
7724static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7725 show_debug_level, store_debug_level);
7726
c8b0e6e1 7727#endif /* CONFIG_IWL3945_DEBUG */
b481de9c
ZY
7728
7729static ssize_t show_rf_kill(struct device *d,
7730 struct device_attribute *attr, char *buf)
7731{
7732 /*
7733 * 0 - RF kill not enabled
7734 * 1 - SW based RF kill active (sysfs)
7735 * 2 - HW based RF kill active
7736 * 3 - Both HW and SW based RF kill active
7737 */
bb8c093b 7738 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7739 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
7740 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
7741
7742 return sprintf(buf, "%i\n", val);
7743}
7744
7745static ssize_t store_rf_kill(struct device *d,
7746 struct device_attribute *attr,
7747 const char *buf, size_t count)
7748{
bb8c093b 7749 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7750
7751 mutex_lock(&priv->mutex);
bb8c093b 7752 iwl3945_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY
7753 mutex_unlock(&priv->mutex);
7754
7755 return count;
7756}
7757
7758static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
7759
7760static ssize_t show_temperature(struct device *d,
7761 struct device_attribute *attr, char *buf)
7762{
bb8c093b 7763 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7764
bb8c093b 7765 if (!iwl3945_is_alive(priv))
b481de9c
ZY
7766 return -EAGAIN;
7767
bb8c093b 7768 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
7769}
7770
7771static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7772
7773static ssize_t show_rs_window(struct device *d,
7774 struct device_attribute *attr,
7775 char *buf)
7776{
bb8c093b
CH
7777 struct iwl3945_priv *priv = d->driver_data;
7778 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY
7779}
7780static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7781
7782static ssize_t show_tx_power(struct device *d,
7783 struct device_attribute *attr, char *buf)
7784{
bb8c093b 7785 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7786 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7787}
7788
7789static ssize_t store_tx_power(struct device *d,
7790 struct device_attribute *attr,
7791 const char *buf, size_t count)
7792{
bb8c093b 7793 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7794 char *p = (char *)buf;
7795 u32 val;
7796
7797 val = simple_strtoul(p, &p, 10);
7798 if (p == buf)
7799 printk(KERN_INFO DRV_NAME
7800 ": %s is not in decimal form.\n", buf);
7801 else
bb8c093b 7802 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
7803
7804 return count;
7805}
7806
7807static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7808
7809static ssize_t show_flags(struct device *d,
7810 struct device_attribute *attr, char *buf)
7811{
bb8c093b 7812 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7813
7814 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7815}
7816
7817static ssize_t store_flags(struct device *d,
7818 struct device_attribute *attr,
7819 const char *buf, size_t count)
7820{
bb8c093b 7821 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7822 u32 flags = simple_strtoul(buf, NULL, 0);
7823
7824 mutex_lock(&priv->mutex);
7825 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7826 /* Cancel any currently running scans... */
bb8c093b 7827 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY
7828 IWL_WARNING("Could not cancel scan.\n");
7829 else {
7830 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7831 flags);
7832 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7833 iwl3945_commit_rxon(priv);
b481de9c
ZY
7834 }
7835 }
7836 mutex_unlock(&priv->mutex);
7837
7838 return count;
7839}
7840
7841static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7842
7843static ssize_t show_filter_flags(struct device *d,
7844 struct device_attribute *attr, char *buf)
7845{
bb8c093b 7846 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7847
7848 return sprintf(buf, "0x%04X\n",
7849 le32_to_cpu(priv->active_rxon.filter_flags));
7850}
7851
7852static ssize_t store_filter_flags(struct device *d,
7853 struct device_attribute *attr,
7854 const char *buf, size_t count)
7855{
bb8c093b 7856 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7857 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7858
7859 mutex_lock(&priv->mutex);
7860 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7861 /* Cancel any currently running scans... */
bb8c093b 7862 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY
7863 IWL_WARNING("Could not cancel scan.\n");
7864 else {
7865 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7866 "0x%04X\n", filter_flags);
7867 priv->staging_rxon.filter_flags =
7868 cpu_to_le32(filter_flags);
bb8c093b 7869 iwl3945_commit_rxon(priv);
b481de9c
ZY
7870 }
7871 }
7872 mutex_unlock(&priv->mutex);
7873
7874 return count;
7875}
7876
7877static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7878 store_filter_flags);
7879
7880static ssize_t show_tune(struct device *d,
7881 struct device_attribute *attr, char *buf)
7882{
bb8c093b 7883 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7884
7885 return sprintf(buf, "0x%04X\n",
7886 (priv->phymode << 8) |
7887 le16_to_cpu(priv->active_rxon.channel));
7888}
7889
bb8c093b 7890static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode);
b481de9c
ZY
7891
7892static ssize_t store_tune(struct device *d,
7893 struct device_attribute *attr,
7894 const char *buf, size_t count)
7895{
bb8c093b 7896 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7897 char *p = (char *)buf;
7898 u16 tune = simple_strtoul(p, &p, 0);
7899 u8 phymode = (tune >> 8) & 0xff;
7900 u16 channel = tune & 0xff;
7901
7902 IWL_DEBUG_INFO("Tune request to:%d channel:%d\n", phymode, channel);
7903
7904 mutex_lock(&priv->mutex);
7905 if ((le16_to_cpu(priv->staging_rxon.channel) != channel) ||
7906 (priv->phymode != phymode)) {
bb8c093b 7907 const struct iwl3945_channel_info *ch_info;
b481de9c 7908
bb8c093b 7909 ch_info = iwl3945_get_channel_info(priv, phymode, channel);
b481de9c
ZY
7910 if (!ch_info) {
7911 IWL_WARNING("Requested invalid phymode/channel "
7912 "combination: %d %d\n", phymode, channel);
7913 mutex_unlock(&priv->mutex);
7914 return -EINVAL;
7915 }
7916
7917 /* Cancel any currently running scans... */
bb8c093b 7918 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY
7919 IWL_WARNING("Could not cancel scan.\n");
7920 else {
7921 IWL_DEBUG_INFO("Committing phymode and "
7922 "rxon.channel = %d %d\n",
7923 phymode, channel);
7924
bb8c093b
CH
7925 iwl3945_set_rxon_channel(priv, phymode, channel);
7926 iwl3945_set_flags_for_phymode(priv, phymode);
b481de9c 7927
bb8c093b
CH
7928 iwl3945_set_rate(priv);
7929 iwl3945_commit_rxon(priv);
b481de9c
ZY
7930 }
7931 }
7932 mutex_unlock(&priv->mutex);
7933
7934 return count;
7935}
7936
7937static DEVICE_ATTR(tune, S_IWUSR | S_IRUGO, show_tune, store_tune);
7938
c8b0e6e1 7939#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
7940
7941static ssize_t show_measurement(struct device *d,
7942 struct device_attribute *attr, char *buf)
7943{
bb8c093b
CH
7944 struct iwl3945_priv *priv = dev_get_drvdata(d);
7945 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY
7946 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7947 u8 *data = (u8 *) & measure_report;
7948 unsigned long flags;
7949
7950 spin_lock_irqsave(&priv->lock, flags);
7951 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7952 spin_unlock_irqrestore(&priv->lock, flags);
7953 return 0;
7954 }
7955 memcpy(&measure_report, &priv->measure_report, size);
7956 priv->measurement_status = 0;
7957 spin_unlock_irqrestore(&priv->lock, flags);
7958
7959 while (size && (PAGE_SIZE - len)) {
7960 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7961 PAGE_SIZE - len, 1);
7962 len = strlen(buf);
7963 if (PAGE_SIZE - len)
7964 buf[len++] = '\n';
7965
7966 ofs += 16;
7967 size -= min(size, 16U);
7968 }
7969
7970 return len;
7971}
7972
7973static ssize_t store_measurement(struct device *d,
7974 struct device_attribute *attr,
7975 const char *buf, size_t count)
7976{
bb8c093b 7977 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7978 struct ieee80211_measurement_params params = {
7979 .channel = le16_to_cpu(priv->active_rxon.channel),
7980 .start_time = cpu_to_le64(priv->last_tsf),
7981 .duration = cpu_to_le16(1),
7982 };
7983 u8 type = IWL_MEASURE_BASIC;
7984 u8 buffer[32];
7985 u8 channel;
7986
7987 if (count) {
7988 char *p = buffer;
7989 strncpy(buffer, buf, min(sizeof(buffer), count));
7990 channel = simple_strtoul(p, NULL, 0);
7991 if (channel)
7992 params.channel = channel;
7993
7994 p = buffer;
7995 while (*p && *p != ' ')
7996 p++;
7997 if (*p)
7998 type = simple_strtoul(p + 1, NULL, 0);
7999 }
8000
8001 IWL_DEBUG_INFO("Invoking measurement of type %d on "
8002 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 8003 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
8004
8005 return count;
8006}
8007
8008static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
8009 show_measurement, store_measurement);
c8b0e6e1 8010#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c
ZY
8011
8012static ssize_t show_rate(struct device *d,
8013 struct device_attribute *attr, char *buf)
8014{
bb8c093b 8015 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8016 unsigned long flags;
8017 int i;
8018
8019 spin_lock_irqsave(&priv->sta_lock, flags);
8020 if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
8021 i = priv->stations[IWL_AP_ID].current_rate.s.rate;
8022 else
8023 i = priv->stations[IWL_STA_ID].current_rate.s.rate;
8024 spin_unlock_irqrestore(&priv->sta_lock, flags);
8025
bb8c093b 8026 i = iwl3945_rate_index_from_plcp(i);
b481de9c
ZY
8027 if (i == -1)
8028 return sprintf(buf, "0\n");
8029
8030 return sprintf(buf, "%d%s\n",
bb8c093b
CH
8031 (iwl3945_rates[i].ieee >> 1),
8032 (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
b481de9c
ZY
8033}
8034
8035static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
8036
8037static ssize_t store_retry_rate(struct device *d,
8038 struct device_attribute *attr,
8039 const char *buf, size_t count)
8040{
bb8c093b 8041 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8042
8043 priv->retry_rate = simple_strtoul(buf, NULL, 0);
8044 if (priv->retry_rate <= 0)
8045 priv->retry_rate = 1;
8046
8047 return count;
8048}
8049
8050static ssize_t show_retry_rate(struct device *d,
8051 struct device_attribute *attr, char *buf)
8052{
bb8c093b 8053 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8054 return sprintf(buf, "%d", priv->retry_rate);
8055}
8056
8057static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
8058 store_retry_rate);
8059
8060static ssize_t store_power_level(struct device *d,
8061 struct device_attribute *attr,
8062 const char *buf, size_t count)
8063{
bb8c093b 8064 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8065 int rc;
8066 int mode;
8067
8068 mode = simple_strtoul(buf, NULL, 0);
8069 mutex_lock(&priv->mutex);
8070
bb8c093b 8071 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY
8072 rc = -EAGAIN;
8073 goto out;
8074 }
8075
8076 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
8077 mode = IWL_POWER_AC;
8078 else
8079 mode |= IWL_POWER_ENABLED;
8080
8081 if (mode != priv->power_mode) {
bb8c093b 8082 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY
8083 if (rc) {
8084 IWL_DEBUG_MAC80211("failed setting power mode.\n");
8085 goto out;
8086 }
8087 priv->power_mode = mode;
8088 }
8089
8090 rc = count;
8091
8092 out:
8093 mutex_unlock(&priv->mutex);
8094 return rc;
8095}
8096
8097#define MAX_WX_STRING 80
8098
8099/* Values are in microsecond */
8100static const s32 timeout_duration[] = {
8101 350000,
8102 250000,
8103 75000,
8104 37000,
8105 25000,
8106};
8107static const s32 period_duration[] = {
8108 400000,
8109 700000,
8110 1000000,
8111 1000000,
8112 1000000
8113};
8114
8115static ssize_t show_power_level(struct device *d,
8116 struct device_attribute *attr, char *buf)
8117{
bb8c093b 8118 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8119 int level = IWL_POWER_LEVEL(priv->power_mode);
8120 char *p = buf;
8121
8122 p += sprintf(p, "%d ", level);
8123 switch (level) {
8124 case IWL_POWER_MODE_CAM:
8125 case IWL_POWER_AC:
8126 p += sprintf(p, "(AC)");
8127 break;
8128 case IWL_POWER_BATTERY:
8129 p += sprintf(p, "(BATTERY)");
8130 break;
8131 default:
8132 p += sprintf(p,
8133 "(Timeout %dms, Period %dms)",
8134 timeout_duration[level - 1] / 1000,
8135 period_duration[level - 1] / 1000);
8136 }
8137
8138 if (!(priv->power_mode & IWL_POWER_ENABLED))
8139 p += sprintf(p, " OFF\n");
8140 else
8141 p += sprintf(p, " \n");
8142
8143 return (p - buf + 1);
8144
8145}
8146
8147static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
8148 store_power_level);
8149
8150static ssize_t show_channels(struct device *d,
8151 struct device_attribute *attr, char *buf)
8152{
bb8c093b 8153 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8154 int len = 0, i;
8155 struct ieee80211_channel *channels = NULL;
8156 const struct ieee80211_hw_mode *hw_mode = NULL;
8157 int count = 0;
8158
bb8c093b 8159 if (!iwl3945_is_ready(priv))
b481de9c
ZY
8160 return -EAGAIN;
8161
bb8c093b 8162 hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211G);
b481de9c 8163 if (!hw_mode)
bb8c093b 8164 hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211B);
b481de9c
ZY
8165 if (hw_mode) {
8166 channels = hw_mode->channels;
8167 count = hw_mode->num_channels;
8168 }
8169
8170 len +=
8171 sprintf(&buf[len],
8172 "Displaying %d channels in 2.4GHz band "
8173 "(802.11bg):\n", count);
8174
8175 for (i = 0; i < count; i++)
8176 len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
8177 channels[i].chan,
8178 channels[i].power_level,
8179 channels[i].
8180 flag & IEEE80211_CHAN_W_RADAR_DETECT ?
8181 " (IEEE 802.11h required)" : "",
8182 (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
8183 || (channels[i].
8184 flag &
8185 IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
8186 ", IBSS",
8187 channels[i].
8188 flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
8189 "active/passive" : "passive only");
8190
bb8c093b 8191 hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211A);
b481de9c
ZY
8192 if (hw_mode) {
8193 channels = hw_mode->channels;
8194 count = hw_mode->num_channels;
8195 } else {
8196 channels = NULL;
8197 count = 0;
8198 }
8199
8200 len += sprintf(&buf[len], "Displaying %d channels in 5.2GHz band "
8201 "(802.11a):\n", count);
8202
8203 for (i = 0; i < count; i++)
8204 len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
8205 channels[i].chan,
8206 channels[i].power_level,
8207 channels[i].
8208 flag & IEEE80211_CHAN_W_RADAR_DETECT ?
8209 " (IEEE 802.11h required)" : "",
8210 (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
8211 || (channels[i].
8212 flag &
8213 IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
8214 ", IBSS",
8215 channels[i].
8216 flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
8217 "active/passive" : "passive only");
8218
8219 return len;
8220}
8221
8222static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
8223
8224static ssize_t show_statistics(struct device *d,
8225 struct device_attribute *attr, char *buf)
8226{
bb8c093b
CH
8227 struct iwl3945_priv *priv = dev_get_drvdata(d);
8228 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY
8229 u32 len = 0, ofs = 0;
8230 u8 *data = (u8 *) & priv->statistics;
8231 int rc = 0;
8232
bb8c093b 8233 if (!iwl3945_is_alive(priv))
b481de9c
ZY
8234 return -EAGAIN;
8235
8236 mutex_lock(&priv->mutex);
bb8c093b 8237 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY
8238 mutex_unlock(&priv->mutex);
8239
8240 if (rc) {
8241 len = sprintf(buf,
8242 "Error sending statistics request: 0x%08X\n", rc);
8243 return len;
8244 }
8245
8246 while (size && (PAGE_SIZE - len)) {
8247 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
8248 PAGE_SIZE - len, 1);
8249 len = strlen(buf);
8250 if (PAGE_SIZE - len)
8251 buf[len++] = '\n';
8252
8253 ofs += 16;
8254 size -= min(size, 16U);
8255 }
8256
8257 return len;
8258}
8259
8260static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
8261
8262static ssize_t show_antenna(struct device *d,
8263 struct device_attribute *attr, char *buf)
8264{
bb8c093b 8265 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 8266
bb8c093b 8267 if (!iwl3945_is_alive(priv))
b481de9c
ZY
8268 return -EAGAIN;
8269
8270 return sprintf(buf, "%d\n", priv->antenna);
8271}
8272
8273static ssize_t store_antenna(struct device *d,
8274 struct device_attribute *attr,
8275 const char *buf, size_t count)
8276{
8277 int ant;
bb8c093b 8278 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8279
8280 if (count == 0)
8281 return 0;
8282
8283 if (sscanf(buf, "%1i", &ant) != 1) {
8284 IWL_DEBUG_INFO("not in hex or decimal form.\n");
8285 return count;
8286 }
8287
8288 if ((ant >= 0) && (ant <= 2)) {
8289 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 8290 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY
8291 } else
8292 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
8293
8294
8295 return count;
8296}
8297
8298static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
8299
8300static ssize_t show_status(struct device *d,
8301 struct device_attribute *attr, char *buf)
8302{
bb8c093b
CH
8303 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
8304 if (!iwl3945_is_alive(priv))
b481de9c
ZY
8305 return -EAGAIN;
8306 return sprintf(buf, "0x%08x\n", (int)priv->status);
8307}
8308
8309static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
8310
8311static ssize_t dump_error_log(struct device *d,
8312 struct device_attribute *attr,
8313 const char *buf, size_t count)
8314{
8315 char *p = (char *)buf;
8316
8317 if (p[0] == '1')
bb8c093b 8318 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY
8319
8320 return strnlen(buf, count);
8321}
8322
8323static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
8324
8325static ssize_t dump_event_log(struct device *d,
8326 struct device_attribute *attr,
8327 const char *buf, size_t count)
8328{
8329 char *p = (char *)buf;
8330
8331 if (p[0] == '1')
bb8c093b 8332 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY
8333
8334 return strnlen(buf, count);
8335}
8336
8337static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
8338
8339/*****************************************************************************
8340 *
8341 * driver setup and teardown
8342 *
8343 *****************************************************************************/
8344
bb8c093b 8345static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY
8346{
8347 priv->workqueue = create_workqueue(DRV_NAME);
8348
8349 init_waitqueue_head(&priv->wait_command_queue);
8350
bb8c093b
CH
8351 INIT_WORK(&priv->up, iwl3945_bg_up);
8352 INIT_WORK(&priv->restart, iwl3945_bg_restart);
8353 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
8354 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
8355 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
8356 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
8357 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
8358 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
8359 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
8360 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
8361 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
8362 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
8363
8364 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
8365
8366 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 8367 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
8368}
8369
bb8c093b 8370static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 8371{
bb8c093b 8372 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 8373
e47eb6ad 8374 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
8375 cancel_delayed_work(&priv->scan_check);
8376 cancel_delayed_work(&priv->alive_start);
8377 cancel_delayed_work(&priv->post_associate);
8378 cancel_work_sync(&priv->beacon_update);
8379}
8380
bb8c093b 8381static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
8382 &dev_attr_antenna.attr,
8383 &dev_attr_channels.attr,
8384 &dev_attr_dump_errors.attr,
8385 &dev_attr_dump_events.attr,
8386 &dev_attr_flags.attr,
8387 &dev_attr_filter_flags.attr,
c8b0e6e1 8388#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
8389 &dev_attr_measurement.attr,
8390#endif
8391 &dev_attr_power_level.attr,
8392 &dev_attr_rate.attr,
8393 &dev_attr_retry_rate.attr,
8394 &dev_attr_rf_kill.attr,
8395 &dev_attr_rs_window.attr,
8396 &dev_attr_statistics.attr,
8397 &dev_attr_status.attr,
8398 &dev_attr_temperature.attr,
8399 &dev_attr_tune.attr,
8400 &dev_attr_tx_power.attr,
8401
8402 NULL
8403};
8404
bb8c093b 8405static struct attribute_group iwl3945_attribute_group = {
b481de9c 8406 .name = NULL, /* put in device directory */
bb8c093b 8407 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
8408};
8409
bb8c093b
CH
8410static struct ieee80211_ops iwl3945_hw_ops = {
8411 .tx = iwl3945_mac_tx,
8412 .start = iwl3945_mac_start,
8413 .stop = iwl3945_mac_stop,
8414 .add_interface = iwl3945_mac_add_interface,
8415 .remove_interface = iwl3945_mac_remove_interface,
8416 .config = iwl3945_mac_config,
8417 .config_interface = iwl3945_mac_config_interface,
8418 .configure_filter = iwl3945_configure_filter,
8419 .set_key = iwl3945_mac_set_key,
8420 .get_stats = iwl3945_mac_get_stats,
8421 .get_tx_stats = iwl3945_mac_get_tx_stats,
8422 .conf_tx = iwl3945_mac_conf_tx,
8423 .get_tsf = iwl3945_mac_get_tsf,
8424 .reset_tsf = iwl3945_mac_reset_tsf,
8425 .beacon_update = iwl3945_mac_beacon_update,
8426 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY
8427};
8428
bb8c093b 8429static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
8430{
8431 int err = 0;
8432 u32 pci_id;
bb8c093b 8433 struct iwl3945_priv *priv;
b481de9c
ZY
8434 struct ieee80211_hw *hw;
8435 int i;
5a66926a 8436 DECLARE_MAC_BUF(mac);
b481de9c 8437
6440adb5
CB
8438 /* Disabling hardware scan means that mac80211 will perform scans
8439 * "the hard way", rather than using device's scan. */
bb8c093b 8440 if (iwl3945_param_disable_hw_scan) {
b481de9c 8441 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 8442 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY
8443 }
8444
bb8c093b
CH
8445 if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
8446 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c
ZY
8447 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
8448 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
8449 err = -EINVAL;
8450 goto out;
8451 }
8452
8453 /* mac80211 allocates memory for this device instance, including
8454 * space for this driver's private structure */
bb8c093b 8455 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY
8456 if (hw == NULL) {
8457 IWL_ERROR("Can not allocate network device\n");
8458 err = -ENOMEM;
8459 goto out;
8460 }
8461 SET_IEEE80211_DEV(hw, &pdev->dev);
8462
f51359a8
JB
8463 hw->rate_control_algorithm = "iwl-3945-rs";
8464
b481de9c
ZY
8465 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
8466 priv = hw->priv;
8467 priv->hw = hw;
8468
8469 priv->pci_dev = pdev;
6440adb5
CB
8470
8471 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 8472 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 8473#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8474 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY
8475 atomic_set(&priv->restrict_refcnt, 0);
8476#endif
8477 priv->retry_rate = 1;
8478
8479 priv->ibss_beacon = NULL;
8480
8481 /* Tell mac80211 and its clients (e.g. Wireless Extensions)
8482 * the range of signal quality values that we'll provide.
8483 * Negative values for level/noise indicate that we'll provide dBm.
8484 * For WE, at least, non-0 values here *enable* display of values
8485 * in app (iwconfig). */
8486 hw->max_rssi = -20; /* signal level, negative indicates dBm */
8487 hw->max_noise = -20; /* noise level, negative indicates dBm */
8488 hw->max_signal = 100; /* link quality indication (%) */
8489
8490 /* Tell mac80211 our Tx characteristics */
8491 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
8492
6440adb5 8493 /* 4 EDCA QOS priorities */
b481de9c
ZY
8494 hw->queues = 4;
8495
8496 spin_lock_init(&priv->lock);
8497 spin_lock_init(&priv->power_data.lock);
8498 spin_lock_init(&priv->sta_lock);
8499 spin_lock_init(&priv->hcmd_lock);
8500
8501 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8502 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8503
8504 INIT_LIST_HEAD(&priv->free_frames);
8505
8506 mutex_init(&priv->mutex);
8507 if (pci_enable_device(pdev)) {
8508 err = -ENODEV;
8509 goto out_ieee80211_free_hw;
8510 }
8511
8512 pci_set_master(pdev);
8513
6440adb5 8514 /* Clear the driver's (not device's) station table */
bb8c093b 8515 iwl3945_clear_stations_table(priv);
b481de9c
ZY
8516
8517 priv->data_retry_limit = -1;
8518 priv->ieee_channels = NULL;
8519 priv->ieee_rates = NULL;
8520 priv->phymode = -1;
8521
8522 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8523 if (!err)
8524 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8525 if (err) {
8526 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8527 goto out_pci_disable_device;
8528 }
8529
8530 pci_set_drvdata(pdev, priv);
8531 err = pci_request_regions(pdev, DRV_NAME);
8532 if (err)
8533 goto out_pci_disable_device;
6440adb5 8534
b481de9c
ZY
8535 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8536 * PCI Tx retries from interfering with C3 CPU state */
8537 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8538
b481de9c
ZY
8539 priv->hw_base = pci_iomap(pdev, 0, 0);
8540 if (!priv->hw_base) {
8541 err = -ENODEV;
8542 goto out_pci_release_regions;
8543 }
8544
8545 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8546 (unsigned long long) pci_resource_len(pdev, 0));
8547 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8548
8549 /* Initialize module parameter values here */
8550
6440adb5 8551 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8552 if (iwl3945_param_disable) {
b481de9c
ZY
8553 set_bit(STATUS_RF_KILL_SW, &priv->status);
8554 IWL_DEBUG_INFO("Radio disabled.\n");
8555 }
8556
8557 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8558
8559 pci_id =
8560 (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
8561
8562 switch (pci_id) {
8563 case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
8564 case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
8565 case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
8566 case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
8567 priv->is_abg = 0;
8568 break;
8569
8570 /*
8571 * Rest are assumed ABG SKU -- if this is not the
8572 * case then the card will get the wrong 'Detected'
8573 * line in the kernel log however the code that
8574 * initializes the GEO table will detect no A-band
8575 * channels and remove the is_abg mask.
8576 */
8577 default:
8578 priv->is_abg = 1;
8579 break;
8580 }
8581
8582 printk(KERN_INFO DRV_NAME
8583 ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
8584 priv->is_abg ? "A" : "");
8585
8586 /* Device-specific setup */
bb8c093b 8587 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 8588 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY
8589 goto out_iounmap;
8590 }
8591
c8b0e6e1 8592#ifdef CONFIG_IWL3945_QOS
bb8c093b 8593 if (iwl3945_param_qos_enable)
b481de9c
ZY
8594 priv->qos_data.qos_enable = 1;
8595
bb8c093b 8596 iwl3945_reset_qos(priv);
b481de9c
ZY
8597
8598 priv->qos_data.qos_active = 0;
8599 priv->qos_data.qos_cap.val = 0;
c8b0e6e1 8600#endif /* CONFIG_IWL3945_QOS */
b481de9c 8601
bb8c093b
CH
8602 iwl3945_set_rxon_channel(priv, MODE_IEEE80211G, 6);
8603 iwl3945_setup_deferred_work(priv);
8604 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY
8605
8606 priv->rates_mask = IWL_RATES_MASK;
8607 /* If power management is turned on, default to AC mode */
8608 priv->power_mode = IWL_POWER_AC;
8609 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8610
bb8c093b 8611 iwl3945_disable_interrupts(priv);
49df2b33 8612
bb8c093b 8613 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY
8614 if (err) {
8615 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY
8616 goto out_release_irq;
8617 }
8618
5a66926a
ZY
8619 /* nic init */
8620 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8621 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8622
8623 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8624 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8625 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8626 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8627 if (err < 0) {
8628 IWL_DEBUG_INFO("Failed to init the card\n");
8629 goto out_remove_sysfs;
8630 }
8631 /* Read the EEPROM */
8632 err = iwl3945_eeprom_init(priv);
b481de9c 8633 if (err) {
5a66926a
ZY
8634 IWL_ERROR("Unable to init EEPROM\n");
8635 goto out_remove_sysfs;
b481de9c 8636 }
5a66926a
ZY
8637 /* MAC Address location in EEPROM same for 3945/4965 */
8638 get_eeprom_mac(priv, priv->mac_addr);
8639 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8640 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8641
849e0dce
RC
8642 err = iwl3945_init_channel_map(priv);
8643 if (err) {
8644 IWL_ERROR("initializing regulatory failed: %d\n", err);
8645 goto out_remove_sysfs;
8646 }
8647
8648 err = iwl3945_init_geos(priv);
8649 if (err) {
8650 IWL_ERROR("initializing geos failed: %d\n", err);
8651 goto out_free_channel_map;
8652 }
8653 iwl3945_reset_channel_flag(priv);
8654
5a66926a
ZY
8655 iwl3945_rate_control_register(priv->hw);
8656 err = ieee80211_register_hw(priv->hw);
8657 if (err) {
8658 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8659 goto out_free_geos;
5a66926a 8660 }
b481de9c 8661
5a66926a
ZY
8662 priv->hw->conf.beacon_int = 100;
8663 priv->mac80211_registered = 1;
8664 pci_save_state(pdev);
8665 pci_disable_device(pdev);
b481de9c
ZY
8666
8667 return 0;
8668
849e0dce
RC
8669 out_free_geos:
8670 iwl3945_free_geos(priv);
8671 out_free_channel_map:
8672 iwl3945_free_channel_map(priv);
5a66926a 8673 out_remove_sysfs:
bb8c093b 8674 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY
8675
8676 out_release_irq:
b481de9c
ZY
8677 destroy_workqueue(priv->workqueue);
8678 priv->workqueue = NULL;
bb8c093b 8679 iwl3945_unset_hw_setting(priv);
b481de9c
ZY
8680
8681 out_iounmap:
8682 pci_iounmap(pdev, priv->hw_base);
8683 out_pci_release_regions:
8684 pci_release_regions(pdev);
8685 out_pci_disable_device:
8686 pci_disable_device(pdev);
8687 pci_set_drvdata(pdev, NULL);
8688 out_ieee80211_free_hw:
8689 ieee80211_free_hw(priv->hw);
8690 out:
8691 return err;
8692}
8693
bb8c093b 8694static void iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8695{
bb8c093b 8696 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY
8697 struct list_head *p, *q;
8698 int i;
8699
8700 if (!priv)
8701 return;
8702
8703 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8704
b481de9c 8705 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8706
bb8c093b 8707 iwl3945_down(priv);
b481de9c
ZY
8708
8709 /* Free MAC hash list for ADHOC */
8710 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8711 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8712 list_del(p);
bb8c093b 8713 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY
8714 }
8715 }
8716
bb8c093b 8717 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8718
bb8c093b 8719 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
8720
8721 if (priv->rxq.bd)
bb8c093b
CH
8722 iwl3945_rx_queue_free(priv, &priv->rxq);
8723 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8724
bb8c093b
CH
8725 iwl3945_unset_hw_setting(priv);
8726 iwl3945_clear_stations_table(priv);
b481de9c
ZY
8727
8728 if (priv->mac80211_registered) {
8729 ieee80211_unregister_hw(priv->hw);
bb8c093b 8730 iwl3945_rate_control_unregister(priv->hw);
b481de9c
ZY
8731 }
8732
6ef89d0a
MA
8733 /*netif_stop_queue(dev); */
8734 flush_workqueue(priv->workqueue);
8735
bb8c093b 8736 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
8737 * priv->workqueue... so we can't take down the workqueue
8738 * until now... */
8739 destroy_workqueue(priv->workqueue);
8740 priv->workqueue = NULL;
8741
b481de9c
ZY
8742 pci_iounmap(pdev, priv->hw_base);
8743 pci_release_regions(pdev);
8744 pci_disable_device(pdev);
8745 pci_set_drvdata(pdev, NULL);
8746
849e0dce
RC
8747 iwl3945_free_channel_map(priv);
8748 iwl3945_free_geos(priv);
b481de9c
ZY
8749
8750 if (priv->ibss_beacon)
8751 dev_kfree_skb(priv->ibss_beacon);
8752
8753 ieee80211_free_hw(priv->hw);
8754}
8755
8756#ifdef CONFIG_PM
8757
bb8c093b 8758static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8759{
bb8c093b 8760 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8761
e655b9f0
ZY
8762 if (priv->is_open) {
8763 set_bit(STATUS_IN_SUSPEND, &priv->status);
8764 iwl3945_mac_stop(priv->hw);
8765 priv->is_open = 1;
8766 }
b481de9c 8767
b481de9c
ZY
8768 pci_set_power_state(pdev, PCI_D3hot);
8769
b481de9c
ZY
8770 return 0;
8771}
8772
bb8c093b 8773static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8774{
bb8c093b 8775 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8776
b481de9c 8777 pci_set_power_state(pdev, PCI_D0);
b481de9c 8778
e655b9f0
ZY
8779 if (priv->is_open)
8780 iwl3945_mac_start(priv->hw);
b481de9c 8781
e655b9f0 8782 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY
8783 return 0;
8784}
8785
8786#endif /* CONFIG_PM */
8787
8788/*****************************************************************************
8789 *
8790 * driver and module entry point
8791 *
8792 *****************************************************************************/
8793
bb8c093b 8794static struct pci_driver iwl3945_driver = {
b481de9c 8795 .name = DRV_NAME,
bb8c093b
CH
8796 .id_table = iwl3945_hw_card_ids,
8797 .probe = iwl3945_pci_probe,
8798 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8799#ifdef CONFIG_PM
bb8c093b
CH
8800 .suspend = iwl3945_pci_suspend,
8801 .resume = iwl3945_pci_resume,
b481de9c
ZY
8802#endif
8803};
8804
bb8c093b 8805static int __init iwl3945_init(void)
b481de9c
ZY
8806{
8807
8808 int ret;
8809 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8810 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
bb8c093b 8811 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY
8812 if (ret) {
8813 IWL_ERROR("Unable to initialize PCI module\n");
8814 return ret;
8815 }
c8b0e6e1 8816#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8817 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY
8818 if (ret) {
8819 IWL_ERROR("Unable to create driver sysfs file\n");
bb8c093b 8820 pci_unregister_driver(&iwl3945_driver);
b481de9c
ZY
8821 return ret;
8822 }
8823#endif
8824
8825 return ret;
8826}
8827
bb8c093b 8828static void __exit iwl3945_exit(void)
b481de9c 8829{
c8b0e6e1 8830#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8831 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8832#endif
bb8c093b 8833 pci_unregister_driver(&iwl3945_driver);
b481de9c
ZY
8834}
8835
bb8c093b 8836module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8837MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8838module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8839MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8840module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY
8841MODULE_PARM_DESC(hwcrypto,
8842 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8843module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8844MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8845module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY
8846MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8847
bb8c093b 8848module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY
8849MODULE_PARM_DESC(queues_num, "number of hw queues.");
8850
8851/* QoS */
bb8c093b 8852module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY
8853MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8854
bb8c093b
CH
8855module_exit(iwl3945_exit);
8856module_init(iwl3945_init);