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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
d43c36dc | 31 | #include <linux/sched.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
1053d35f RR |
33 | #include <net/mac80211.h> |
34 | #include "iwl-eeprom.h" | |
35 | #include "iwl-dev.h" | |
36 | #include "iwl-core.h" | |
37 | #include "iwl-sta.h" | |
38 | #include "iwl-io.h" | |
39 | #include "iwl-helpers.h" | |
40 | ||
fd4abac5 TW |
41 | /** |
42 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
43 | */ | |
7bfedc59 | 44 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
fd4abac5 TW |
45 | { |
46 | u32 reg = 0; | |
fd4abac5 TW |
47 | int txq_id = txq->q.id; |
48 | ||
49 | if (txq->need_update == 0) | |
7bfedc59 | 50 | return; |
fd4abac5 | 51 | |
f81c1f48 WYG |
52 | if (priv->cfg->base_params->shadow_reg_enable) { |
53 | /* shadow register enabled */ | |
54 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
55 | txq->q.write_ptr | (txq_id << 8)); | |
56 | } else { | |
57 | /* if we're trying to save power */ | |
58 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
59 | /* wake up nic if it's powered down ... | |
60 | * uCode will wake up, and interrupt us again, so next | |
61 | * time we'll skip this part. */ | |
62 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
fd4abac5 | 63 | |
f81c1f48 WYG |
64 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
65 | IWL_DEBUG_INFO(priv, | |
66 | "Tx queue %d requesting wakeup," | |
67 | " GP1 = 0x%x\n", txq_id, reg); | |
68 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
69 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
70 | return; | |
71 | } | |
fd4abac5 | 72 | |
f81c1f48 | 73 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fd4abac5 | 74 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 75 | |
f81c1f48 WYG |
76 | /* |
77 | * else not in power-save mode, | |
78 | * uCode will never sleep when we're | |
79 | * trying to tx (during RFKILL, we're not trying to tx). | |
80 | */ | |
81 | } else | |
82 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
83 | txq->q.write_ptr | (txq_id << 8)); | |
84 | } | |
fd4abac5 | 85 | txq->need_update = 0; |
fd4abac5 | 86 | } |
fd4abac5 | 87 | |
387f3381 SG |
88 | /** |
89 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
90 | */ | |
91 | void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id) | |
92 | { | |
93 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
94 | struct iwl_queue *q = &txq->q; | |
95 | ||
96 | if (q->n_bd == 0) | |
97 | return; | |
98 | ||
99 | while (q->write_ptr != q->read_ptr) { | |
100 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); | |
101 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); | |
102 | } | |
103 | } | |
104 | ||
1053d35f RR |
105 | /** |
106 | * iwl_tx_queue_free - Deallocate DMA queue. | |
107 | * @txq: Transmit queue to deallocate. | |
108 | * | |
109 | * Empty queue by removing and destroying all BD's. | |
110 | * Free all buffers. | |
111 | * 0-fill, but do not free "txq" descriptor structure. | |
112 | */ | |
a8e74e27 | 113 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 114 | { |
da99c4b6 | 115 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
f36d04ab | 116 | struct device *dev = &priv->pci_dev->dev; |
71c55d90 | 117 | int i; |
1053d35f | 118 | |
387f3381 | 119 | iwl_tx_queue_unmap(priv, txq_id); |
1053d35f | 120 | |
1053d35f | 121 | /* De-alloc array of command/tx buffers */ |
961ba60a | 122 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 123 | kfree(txq->cmd[i]); |
1053d35f RR |
124 | |
125 | /* De-alloc circular buffer of TFDs */ | |
126 | if (txq->q.n_bd) | |
f36d04ab SG |
127 | dma_free_coherent(dev, priv->hw_params.tfd_size * |
128 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
1053d35f RR |
129 | |
130 | /* De-alloc array of per-TFD driver data */ | |
131 | kfree(txq->txb); | |
132 | txq->txb = NULL; | |
133 | ||
c2acea8e JB |
134 | /* deallocate arrays */ |
135 | kfree(txq->cmd); | |
136 | kfree(txq->meta); | |
137 | txq->cmd = NULL; | |
138 | txq->meta = NULL; | |
139 | ||
1053d35f RR |
140 | /* 0-fill queue descriptor structure */ |
141 | memset(txq, 0, sizeof(*txq)); | |
142 | } | |
961ba60a TW |
143 | |
144 | /** | |
387f3381 | 145 | * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue |
961ba60a | 146 | */ |
387f3381 | 147 | void iwl_cmd_queue_unmap(struct iwl_priv *priv) |
961ba60a | 148 | { |
13bb9483 | 149 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
961ba60a | 150 | struct iwl_queue *q = &txq->q; |
71c55d90 | 151 | int i; |
961ba60a TW |
152 | |
153 | if (q->n_bd == 0) | |
154 | return; | |
155 | ||
387f3381 | 156 | while (q->read_ptr != q->write_ptr) { |
dd487449 ZY |
157 | i = get_cmd_index(q, q->read_ptr, 0); |
158 | ||
3598e177 | 159 | if (txq->meta[i].flags & CMD_MAPPED) { |
387f3381 SG |
160 | pci_unmap_single(priv->pci_dev, |
161 | dma_unmap_addr(&txq->meta[i], mapping), | |
162 | dma_unmap_len(&txq->meta[i], len), | |
163 | PCI_DMA_BIDIRECTIONAL); | |
3598e177 SG |
164 | txq->meta[i].flags = 0; |
165 | } | |
dd487449 | 166 | |
3598e177 | 167 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
dd487449 | 168 | } |
387f3381 | 169 | |
3598e177 SG |
170 | i = q->n_window; |
171 | if (txq->meta[i].flags & CMD_MAPPED) { | |
dd487449 | 172 | pci_unmap_single(priv->pci_dev, |
2e724443 FT |
173 | dma_unmap_addr(&txq->meta[i], mapping), |
174 | dma_unmap_len(&txq->meta[i], len), | |
dd487449 | 175 | PCI_DMA_BIDIRECTIONAL); |
3598e177 | 176 | txq->meta[i].flags = 0; |
dd487449 | 177 | } |
387f3381 SG |
178 | } |
179 | ||
180 | /** | |
181 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
182 | * @txq: Transmit queue to deallocate. | |
183 | * | |
184 | * Empty queue by removing and destroying all BD's. | |
185 | * Free all buffers. | |
186 | * 0-fill, but do not free "txq" descriptor structure. | |
187 | */ | |
188 | void iwl_cmd_queue_free(struct iwl_priv *priv) | |
189 | { | |
190 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; | |
191 | struct device *dev = &priv->pci_dev->dev; | |
192 | int i; | |
193 | ||
194 | iwl_cmd_queue_unmap(priv); | |
dd487449 | 195 | |
961ba60a TW |
196 | /* De-alloc array of command/tx buffers */ |
197 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
198 | kfree(txq->cmd[i]); | |
199 | ||
200 | /* De-alloc circular buffer of TFDs */ | |
201 | if (txq->q.n_bd) | |
f36d04ab SG |
202 | dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd, |
203 | txq->tfds, txq->q.dma_addr); | |
961ba60a | 204 | |
28142986 RC |
205 | /* deallocate arrays */ |
206 | kfree(txq->cmd); | |
207 | kfree(txq->meta); | |
208 | txq->cmd = NULL; | |
209 | txq->meta = NULL; | |
210 | ||
961ba60a TW |
211 | /* 0-fill queue descriptor structure */ |
212 | memset(txq, 0, sizeof(*txq)); | |
213 | } | |
3e5d238f | 214 | |
fd4abac5 TW |
215 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
216 | * DMA services | |
217 | * | |
218 | * Theory of operation | |
219 | * | |
220 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
221 | * of buffer descriptors, each of which points to one or more data buffers for | |
222 | * the device to read from or fill. Driver and device exchange status of each | |
223 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
224 | * entries in each circular buffer, to protect against confusing empty and full | |
225 | * queue states. | |
226 | * | |
227 | * The device reads or writes the data in the queues via the device's several | |
228 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
229 | * | |
230 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
231 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
232 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
233 | * Tx queue resumed. | |
234 | * | |
fd4abac5 TW |
235 | ***************************************************/ |
236 | ||
237 | int iwl_queue_space(const struct iwl_queue *q) | |
238 | { | |
239 | int s = q->read_ptr - q->write_ptr; | |
240 | ||
241 | if (q->read_ptr > q->write_ptr) | |
242 | s -= q->n_bd; | |
243 | ||
244 | if (s <= 0) | |
245 | s += q->n_window; | |
246 | /* keep some reserve to not confuse empty and full situations */ | |
247 | s -= 2; | |
248 | if (s < 0) | |
249 | s = 0; | |
250 | return s; | |
251 | } | |
fd4abac5 TW |
252 | |
253 | ||
1053d35f RR |
254 | /** |
255 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
256 | */ | |
443cfd45 | 257 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
258 | int count, int slots_num, u32 id) |
259 | { | |
260 | q->n_bd = count; | |
261 | q->n_window = slots_num; | |
262 | q->id = id; | |
263 | ||
264 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
265 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
266 | if (WARN_ON(!is_power_of_2(count))) |
267 | return -EINVAL; | |
1053d35f RR |
268 | |
269 | /* slots_num must be power-of-two size, otherwise | |
270 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
271 | if (WARN_ON(!is_power_of_2(slots_num))) |
272 | return -EINVAL; | |
1053d35f RR |
273 | |
274 | q->low_mark = q->n_window / 4; | |
275 | if (q->low_mark < 4) | |
276 | q->low_mark = 4; | |
277 | ||
278 | q->high_mark = q->n_window / 8; | |
279 | if (q->high_mark < 2) | |
280 | q->high_mark = 2; | |
281 | ||
282 | q->write_ptr = q->read_ptr = 0; | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | /** | |
288 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
289 | */ | |
290 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 291 | struct iwl_tx_queue *txq, u32 id) |
1053d35f | 292 | { |
f36d04ab | 293 | struct device *dev = &priv->pci_dev->dev; |
3978e5bc | 294 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
295 | |
296 | /* Driver private data, only for Tx (not command) queues, | |
297 | * not shared with device. */ | |
13bb9483 | 298 | if (id != priv->cmd_queue) { |
519c7c41 | 299 | txq->txb = kzalloc(sizeof(txq->txb[0]) * |
1053d35f RR |
300 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); |
301 | if (!txq->txb) { | |
15b1687c | 302 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
303 | "structures failed\n"); |
304 | goto error; | |
305 | } | |
3978e5bc | 306 | } else { |
1053d35f | 307 | txq->txb = NULL; |
3978e5bc | 308 | } |
1053d35f RR |
309 | |
310 | /* Circular buffer of transmit frame descriptors (TFDs), | |
311 | * shared with device */ | |
f36d04ab SG |
312 | txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, |
313 | GFP_KERNEL); | |
499b1883 | 314 | if (!txq->tfds) { |
3978e5bc | 315 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
316 | goto error; |
317 | } | |
318 | txq->q.id = id; | |
319 | ||
320 | return 0; | |
321 | ||
322 | error: | |
323 | kfree(txq->txb); | |
324 | txq->txb = NULL; | |
325 | ||
326 | return -ENOMEM; | |
327 | } | |
328 | ||
1053d35f RR |
329 | /** |
330 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
331 | */ | |
a8e74e27 SO |
332 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
333 | int slots_num, u32 txq_id) | |
1053d35f | 334 | { |
da99c4b6 | 335 | int i, len; |
73b7d742 | 336 | int ret; |
c2acea8e | 337 | int actual_slots = slots_num; |
1053d35f RR |
338 | |
339 | /* | |
340 | * Alloc buffer array for commands (Tx or other types of commands). | |
13bb9483 | 341 | * For the command queue (#4/#9), allocate command space + one big |
1053d35f RR |
342 | * command for scan, since scan command is very huge; the system will |
343 | * not have two scans at the same time, so only one is needed. | |
344 | * For normal Tx queues (all other queues), no super-size command | |
345 | * space is needed. | |
346 | */ | |
13bb9483 | 347 | if (txq_id == priv->cmd_queue) |
c2acea8e JB |
348 | actual_slots++; |
349 | ||
350 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, | |
351 | GFP_KERNEL); | |
352 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, | |
353 | GFP_KERNEL); | |
354 | ||
355 | if (!txq->meta || !txq->cmd) | |
356 | goto out_free_arrays; | |
357 | ||
358 | len = sizeof(struct iwl_device_cmd); | |
359 | for (i = 0; i < actual_slots; i++) { | |
360 | /* only happens for cmd queue */ | |
361 | if (i == slots_num) | |
89612124 | 362 | len = IWL_MAX_CMD_SIZE; |
da99c4b6 | 363 | |
49898852 | 364 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 365 | if (!txq->cmd[i]) |
73b7d742 | 366 | goto err; |
da99c4b6 | 367 | } |
1053d35f RR |
368 | |
369 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
370 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
371 | if (ret) | |
372 | goto err; | |
1053d35f | 373 | |
1053d35f RR |
374 | txq->need_update = 0; |
375 | ||
1a716557 | 376 | /* |
ea9b307f JB |
377 | * For the default queues 0-3, set up the swq_id |
378 | * already -- all others need to get one later | |
379 | * (if they need one at all). | |
1a716557 | 380 | */ |
ea9b307f JB |
381 | if (txq_id < 4) |
382 | iwl_set_swq_id(txq, txq_id, txq_id); | |
45af8195 | 383 | |
1053d35f RR |
384 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
385 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
386 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
387 | ||
388 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
3e41ace5 JB |
389 | ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
390 | if (ret) | |
391 | return ret; | |
1053d35f RR |
392 | |
393 | /* Tell device where to find queue */ | |
a8e74e27 | 394 | priv->cfg->ops->lib->txq_init(priv, txq); |
1053d35f RR |
395 | |
396 | return 0; | |
73b7d742 | 397 | err: |
c2acea8e | 398 | for (i = 0; i < actual_slots; i++) |
73b7d742 | 399 | kfree(txq->cmd[i]); |
c2acea8e JB |
400 | out_free_arrays: |
401 | kfree(txq->meta); | |
402 | kfree(txq->cmd); | |
73b7d742 | 403 | |
73b7d742 | 404 | return -ENOMEM; |
1053d35f | 405 | } |
a8e74e27 | 406 | |
de0f60ea ZY |
407 | void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
408 | int slots_num, u32 txq_id) | |
409 | { | |
410 | int actual_slots = slots_num; | |
411 | ||
13bb9483 | 412 | if (txq_id == priv->cmd_queue) |
de0f60ea ZY |
413 | actual_slots++; |
414 | ||
415 | memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots); | |
416 | ||
417 | txq->need_update = 0; | |
418 | ||
419 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
420 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
421 | ||
422 | /* Tell device where to find queue */ | |
423 | priv->cfg->ops->lib->txq_init(priv, txq); | |
424 | } | |
de0f60ea | 425 | |
fd4abac5 TW |
426 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
427 | ||
428 | /** | |
429 | * iwl_enqueue_hcmd - enqueue a uCode command | |
430 | * @priv: device private data point | |
431 | * @cmd: a point to the ucode command structure | |
432 | * | |
433 | * The function returns < 0 values to indicate the operation is | |
434 | * failed. On success, it turns the index (> 0) of command in the | |
435 | * command queue. | |
436 | */ | |
437 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
438 | { | |
13bb9483 | 439 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
fd4abac5 | 440 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
441 | struct iwl_device_cmd *out_cmd; |
442 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 443 | dma_addr_t phys_addr; |
fd4abac5 | 444 | unsigned long flags; |
f3674227 TW |
445 | u32 idx; |
446 | u16 fix_size; | |
0975cc8f | 447 | bool is_ct_kill = false; |
fd4abac5 | 448 | |
fd4abac5 TW |
449 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); |
450 | ||
3e41ace5 JB |
451 | /* |
452 | * If any of the command structures end up being larger than | |
fd4abac5 | 453 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then |
89612124 AK |
454 | * we will need to increase the size of the TFD entries |
455 | * Also, check to see if command buffer should not exceed the size | |
3e41ace5 JB |
456 | * of device_cmd and max_cmd_size. |
457 | */ | |
458 | if (WARN_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
459 | !(cmd->flags & CMD_SIZE_HUGE))) | |
460 | return -EINVAL; | |
461 | ||
462 | if (WARN_ON(fix_size > IWL_MAX_CMD_SIZE)) | |
463 | return -EINVAL; | |
fd4abac5 | 464 | |
7812b167 | 465 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
466 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
467 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
468 | return -EIO; |
469 | } | |
7b21f00e JB |
470 | |
471 | /* | |
472 | * As we only have a single huge buffer, check that the command | |
473 | * is synchronous (otherwise buffers could end up being reused). | |
474 | */ | |
475 | ||
476 | if (WARN_ON((cmd->flags & CMD_ASYNC) && (cmd->flags & CMD_SIZE_HUGE))) | |
477 | return -EINVAL; | |
fd4abac5 | 478 | |
3598e177 SG |
479 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
480 | ||
c2acea8e | 481 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
3598e177 SG |
482 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
483 | ||
2d237f71 | 484 | IWL_ERR(priv, "No space in command queue\n"); |
f42e7662 | 485 | is_ct_kill = iwl_check_for_ct_kill(priv); |
0975cc8f | 486 | if (!is_ct_kill) { |
7812b167 | 487 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); |
e649437f | 488 | iwlagn_fw_error(priv, false); |
7812b167 | 489 | } |
fd4abac5 TW |
490 | return -ENOSPC; |
491 | } | |
492 | ||
c2acea8e | 493 | idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); |
da99c4b6 | 494 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
495 | out_meta = &txq->meta[idx]; |
496 | ||
3598e177 SG |
497 | if (WARN_ON(out_meta->flags & CMD_MAPPED)) { |
498 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
499 | return -ENOSPC; | |
500 | } | |
501 | ||
8ce73f3a | 502 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
3598e177 | 503 | out_meta->flags = cmd->flags | CMD_MAPPED; |
c2acea8e JB |
504 | if (cmd->flags & CMD_WANT_SKB) |
505 | out_meta->source = cmd; | |
506 | if (cmd->flags & CMD_ASYNC) | |
507 | out_meta->callback = cmd->callback; | |
fd4abac5 TW |
508 | |
509 | out_cmd->hdr.cmd = cmd->id; | |
fd4abac5 TW |
510 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); |
511 | ||
512 | /* At this point, the out_cmd now has all of the incoming cmd | |
513 | * information */ | |
514 | ||
515 | out_cmd->hdr.flags = 0; | |
13bb9483 | 516 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) | |
fd4abac5 | 517 | INDEX_TO_SEQ(q->write_ptr)); |
c2acea8e | 518 | if (cmd->flags & CMD_SIZE_HUGE) |
9734cb23 | 519 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
fd4abac5 | 520 | |
ded2ae7c EK |
521 | #ifdef CONFIG_IWLWIFI_DEBUG |
522 | switch (out_cmd->hdr.cmd) { | |
523 | case REPLY_TX_LINK_QUALITY_CMD: | |
524 | case SENSITIVITY_CMD: | |
e1623446 | 525 | IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
526 | "%d bytes at %d[%d]:%d\n", |
527 | get_cmd_string(out_cmd->hdr.cmd), | |
528 | out_cmd->hdr.cmd, | |
529 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
13bb9483 JB |
530 | q->write_ptr, idx, priv->cmd_queue); |
531 | break; | |
ded2ae7c | 532 | default: |
e1623446 | 533 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
534 | "%d bytes at %d[%d]:%d\n", |
535 | get_cmd_string(out_cmd->hdr.cmd), | |
536 | out_cmd->hdr.cmd, | |
537 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
13bb9483 | 538 | q->write_ptr, idx, priv->cmd_queue); |
ded2ae7c EK |
539 | } |
540 | #endif | |
fd4abac5 TW |
541 | txq->need_update = 1; |
542 | ||
df833b1d RC |
543 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
544 | fix_size, PCI_DMA_BIDIRECTIONAL); | |
2e724443 FT |
545 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
546 | dma_unmap_len_set(out_meta, len, fix_size); | |
df833b1d | 547 | |
be1a71a1 JB |
548 | trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags); |
549 | ||
df833b1d RC |
550 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
551 | phys_addr, fix_size, 1, | |
552 | U32_PAD(cmd->len)); | |
553 | ||
fd4abac5 TW |
554 | /* Increment and update queue's write index */ |
555 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 556 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 TW |
557 | |
558 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
7bfedc59 | 559 | return idx; |
fd4abac5 TW |
560 | } |
561 | ||
17b88929 TW |
562 | /** |
563 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
564 | * | |
565 | * When FW advances 'R' index, all entries between old and new 'R' index | |
566 | * need to be reclaimed. As result, some free space forms. If there is | |
567 | * enough free space (> low mark), wake the stack that feeds us. | |
568 | */ | |
499b1883 TW |
569 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, |
570 | int idx, int cmd_idx) | |
17b88929 TW |
571 | { |
572 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
573 | struct iwl_queue *q = &txq->q; | |
574 | int nfreed = 0; | |
575 | ||
499b1883 | 576 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 577 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 578 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 579 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
580 | return; |
581 | } | |
582 | ||
499b1883 TW |
583 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
584 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 585 | |
499b1883 | 586 | if (nfreed++ > 0) { |
15b1687c | 587 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 588 | q->write_ptr, q->read_ptr); |
e649437f | 589 | iwlagn_fw_error(priv, false); |
17b88929 | 590 | } |
da99c4b6 | 591 | |
17b88929 TW |
592 | } |
593 | } | |
594 | ||
595 | /** | |
596 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
597 | * @rxb: Rx buffer to reclaim | |
598 | * | |
599 | * If an Rx buffer has an async callback associated with it the callback | |
600 | * will be executed. The attached skb (if present) will only be freed | |
601 | * if the callback returns 1 | |
602 | */ | |
603 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
604 | { | |
2f301227 | 605 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
606 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
607 | int txq_id = SEQ_TO_QUEUE(sequence); | |
608 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 609 | int cmd_index; |
9734cb23 | 610 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
c2acea8e JB |
611 | struct iwl_device_cmd *cmd; |
612 | struct iwl_cmd_meta *meta; | |
13bb9483 | 613 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
3598e177 | 614 | unsigned long flags; |
17b88929 TW |
615 | |
616 | /* If a Tx command is being handled and it isn't in the actual | |
617 | * command queue then there a command routing bug has been introduced | |
618 | * in the queue management code. */ | |
13bb9483 JB |
619 | if (WARN(txq_id != priv->cmd_queue, |
620 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", | |
621 | txq_id, priv->cmd_queue, sequence, | |
622 | priv->txq[priv->cmd_queue].q.read_ptr, | |
623 | priv->txq[priv->cmd_queue].q.write_ptr)) { | |
ec741164 | 624 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 625 | return; |
01ef9323 | 626 | } |
17b88929 | 627 | |
dd487449 ZY |
628 | cmd_index = get_cmd_index(&txq->q, index, huge); |
629 | cmd = txq->cmd[cmd_index]; | |
630 | meta = &txq->meta[cmd_index]; | |
17b88929 | 631 | |
c33de625 | 632 | pci_unmap_single(priv->pci_dev, |
2e724443 FT |
633 | dma_unmap_addr(meta, mapping), |
634 | dma_unmap_len(meta, len), | |
c33de625 RC |
635 | PCI_DMA_BIDIRECTIONAL); |
636 | ||
17b88929 | 637 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 638 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
639 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
640 | rxb->page = NULL; | |
2624e96c SG |
641 | } else if (meta->callback) |
642 | meta->callback(priv, cmd, pkt); | |
643 | ||
644 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
17b88929 | 645 | |
499b1883 | 646 | iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
17b88929 | 647 | |
c2acea8e | 648 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 | 649 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
91dd6c27 | 650 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", |
d2dfe6df | 651 | get_cmd_string(cmd->hdr.cmd)); |
17b88929 TW |
652 | wake_up_interruptible(&priv->wait_command_queue); |
653 | } | |
3598e177 SG |
654 | |
655 | /* Mark as unmapped */ | |
dd487449 | 656 | meta->flags = 0; |
3598e177 SG |
657 | |
658 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
17b88929 | 659 | } |